mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Revision 188:bcfe06ba3d64, committed 2018-11-08
- Comitter:
- AnnaBridge
- Date:
- Thu Nov 08 11:46:34 2018 +0000
- Parent:
- 187:0387e8f68319
- Child:
- 189:f392fc9709a3
- Commit message:
- mbed-dev library. Release version 164
Changed in this revision
--- a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
- * @version V1.0.1
- * @date 07. Sep 2017
+ * @version V1.0.2
+ * @date 09. April 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -450,7 +450,9 @@
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ #if __has_builtin(__builtin_arm_get_fpscr)
+ // Re-enable using built-in when GCC has been fixed
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
@@ -473,7 +475,9 @@
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ #if __has_builtin(__builtin_arm_set_fpscr)
+ // Re-enable using built-in when GCC has been fixed
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
--- a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h Thu Sep 06 13:40:20 2018 +0100 +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h Thu Nov 08 11:46:34 2018 +0000 @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.0.6 + * @date 02. March 2018 ******************************************************************************/ //------------------------------------------------------------------------------
--- a/cmsis/TARGET_CORTEX_A/core_ca.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_A/core_ca.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_ca.h
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
- * @version V1.00
- * @date 22. Feb 2017
+ * @version V1.0.1
+ * @date 07. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
@@ -1284,8 +1284,6 @@
} else {
// INTID 0-15 Software Generated Interrupt
GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
- // Forward the interrupt to the CPU interface that requested it
- GICDistributor->SGIR = (IRQn | 0x02000000U);
}
}
--- a/cmsis/TARGET_CORTEX_M/cmsis_armcc.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h Thu Nov 08 11:46:34 2018 +0000
@@ -337,8 +337,6 @@
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
@@ -372,9 +370,6 @@
#endif
}
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-
/*@} end of CMSIS_Core_RegAccFunctions */
--- a/cmsis/TARGET_CORTEX_M/cmsis_armclang.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h Thu Nov 08 11:46:34 2018 +0000
@@ -237,7 +237,7 @@
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
@@ -252,7 +252,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
@@ -291,7 +291,7 @@
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
@@ -306,7 +306,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
@@ -346,7 +346,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
@@ -581,7 +581,7 @@
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return result;
#endif
@@ -603,7 +603,7 @@
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return result;
#endif
@@ -669,7 +669,7 @@
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return result;
#endif
@@ -691,7 +691,7 @@
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return result;
#endif
@@ -742,10 +742,6 @@
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
@@ -770,10 +766,6 @@
#define __set_FPSCR(x) ((void)(x))
#endif
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
/*@} end of CMSIS_Core_RegAccFunctions */
--- a/cmsis/TARGET_CORTEX_M/cmsis_gcc.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler GCC header file
- * @version V5.0.3
- * @date 16. January 2018
+ * @version V5.0.4
+ * @date 09. April 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -246,7 +246,7 @@
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
@@ -261,7 +261,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
@@ -300,7 +300,7 @@
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
@@ -315,7 +315,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
@@ -355,7 +355,7 @@
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
@@ -596,7 +596,7 @@
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return result;
#endif
@@ -617,7 +617,7 @@
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return result;
#endif
@@ -683,7 +683,7 @@
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return result;
#endif
@@ -705,7 +705,7 @@
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
- register uint32_t result;
+ uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return result;
#endif
@@ -758,9 +758,6 @@
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
@@ -770,7 +767,9 @@
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
@@ -794,7 +793,9 @@
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
@@ -805,10 +806,6 @@
#endif
}
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
/*@} end of CMSIS_Core_RegAccFunctions */
--- a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version V5.0.5
- * @date 10. January 2018
+ * @version V5.0.7
+ * @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
@@ -340,8 +340,17 @@
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
- #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
- #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
@@ -716,12 +725,25 @@
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
return res;
}
+
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
@@ -826,78 +848,78 @@
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
- __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
- __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
- __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
- __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
- __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
- __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
- __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
--- a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv8mbl.h
* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
- * @version V5.0.4
- * @date 10. January 2018
+ * @version V5.0.7
+ * @date 22. June 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -59,7 +59,7 @@
\ingroup Cortex_ARMv8MBL
@{
*/
-
+
#include "cmsis_version.h"
/* CMSIS definitions */
@@ -415,6 +415,9 @@
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
@@ -721,8 +724,8 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
@@ -730,26 +733,18 @@
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -772,68 +767,25 @@
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -845,21 +797,15 @@
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
@@ -1239,8 +1185,8 @@
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
@@ -1266,12 +1212,36 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
@@ -1513,6 +1483,58 @@
/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
@@ -1556,7 +1578,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_armv8mml.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version V5.0.4
- * @date 10. January 2018
+ * @version V5.0.7
+ * @date 06. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
-
+
/* CMSIS Armv8MML definitions */
#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@@ -90,12 +90,12 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
-
+
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -113,7 +113,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -130,18 +130,18 @@
#else
#define __FPU_USED 0U
#endif
-
+
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
-
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -159,12 +159,12 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
-
+
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -568,6 +568,9 @@
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
@@ -1383,8 +1386,8 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
@@ -1392,26 +1395,18 @@
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -1434,68 +1429,25 @@
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1507,22 +1459,16 @@
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
/*@}*/ /* end of group CMSIS_TPI */
@@ -1587,8 +1533,8 @@
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
@@ -2136,6 +2082,27 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
/**
\brief Set Priority Grouping
@@ -2495,7 +2462,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm0.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm0.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 10. January 2018
+ * @version V5.0.5
+ * @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -572,8 +572,8 @@
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
@@ -599,12 +599,20 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
@@ -758,6 +766,59 @@
/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
@@ -792,7 +853,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm0plus.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V5.0.4
- * @date 10. January 2018
+ * @version V5.0.6
+ * @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -690,8 +690,8 @@
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
@@ -717,12 +717,20 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
@@ -876,6 +884,58 @@
/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
@@ -920,7 +980,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cmsis/TARGET_CORTEX_M/core_cm1.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
--- a/cmsis/TARGET_CORTEX_M/core_cm23.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm23.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm23.h
* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version V5.0.4
- * @date 10. January 2018
+ * @version V5.0.7
+ * @date 22. June 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -68,7 +68,7 @@
#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
__CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-#define __CORTEX_M (23U) /*!< Cortex-M Core */
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
@@ -415,6 +415,9 @@
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
@@ -721,7 +724,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -730,29 +733,26 @@
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -775,6 +775,9 @@
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
@@ -782,61 +785,79 @@
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -848,21 +869,18 @@
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
@@ -1269,12 +1287,36 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
@@ -1516,6 +1558,58 @@
/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
@@ -1559,7 +1653,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm3.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm3.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 08. January 2018
+ * @version V5.0.8
+ * @date 04. June 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
-
+
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@@ -995,7 +995,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -1006,7 +1006,7 @@
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
@@ -1022,11 +1022,8 @@
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -1079,8 +1076,11 @@
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1105,12 +1105,15 @@
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1132,11 +1135,11 @@
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
@@ -1459,6 +1462,11 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
/**
\brief Set Priority Grouping
@@ -1751,7 +1759,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm33.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm33.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 08. January 2018
+ * @version V5.0.9
+ * @date 06. July 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -61,14 +61,14 @@
*/
#include "cmsis_version.h"
-
+
/* CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
- __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (33U) /*!< Cortex-M Core */
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
@@ -90,7 +90,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -113,7 +113,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -136,7 +136,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -159,7 +159,7 @@
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
+ #define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
@@ -568,6 +568,9 @@
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
@@ -1383,7 +1386,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -1392,29 +1395,26 @@
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -1437,6 +1437,9 @@
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
@@ -1444,61 +1447,79 @@
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1510,22 +1531,19 @@
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
/*@}*/ /* end of group CMSIS_TPI */
@@ -1590,8 +1608,8 @@
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
@@ -2139,6 +2157,27 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
/**
\brief Set Priority Grouping
@@ -2498,7 +2537,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm4.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm4.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 08. January 2018
+ * @version V5.0.8
+ * @date 04. June 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -61,7 +61,7 @@
*/
#include "cmsis_version.h"
-
+
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
@@ -1060,7 +1060,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -1071,7 +1071,7 @@
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
@@ -1087,11 +1087,8 @@
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -1144,8 +1141,11 @@
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1170,12 +1170,15 @@
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1197,11 +1200,11 @@
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
@@ -1633,6 +1636,14 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
/**
\brief Set Priority Grouping
@@ -1925,7 +1936,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_cm7.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_cm7.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cm7.h
* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 08. January 2018
+ * @version V5.0.8
+ * @date 04. June 2018
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -62,7 +62,7 @@
#include "cmsis_version.h"
-/* CMSIS CM7 definitions */
+/* CMSIS CM7 definitions */
#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
@@ -1265,7 +1265,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -1276,7 +1276,7 @@
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
@@ -1292,11 +1292,8 @@
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
-
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
@@ -1349,8 +1346,11 @@
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1375,12 +1375,15 @@
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1402,12 +1405,12 @@
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
/*@}*/ /* end of group CMSIS_TPI */
@@ -1841,6 +1844,14 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
/**
\brief Set Priority Grouping
@@ -2133,7 +2144,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
@@ -2308,9 +2319,9 @@
__STATIC_INLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- register uint32_t ccsidr;
- register uint32_t sets;
- register uint32_t ways;
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
--- a/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h Thu Sep 06 13:40:20 2018 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,201 +0,0 @@ -/**************************************************************************//** - * @file core_cmSecureAccess.h - * @brief CMSIS Cortex-M Core Secure Access Header File - * @version XXX - * @date 10. June 2016 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2016 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CM_SECURE_ACCESS_H -#define __CORE_CM_SECURE_ACCESS_H - - -/* ########################### Core Secure Access ########################### */ - -#ifdef FEATURE_UVISOR -#include "uvisor-lib/uvisor-lib.h" - -/* Secure uVisor implementation. */ - -/** Set the value at the target address. - * - * Equivalent to: `*address = value`. - * @param address[in] Target address - * @param value[in] Value to write at the address location. - */ -#define SECURE_WRITE(address, value) \ - uvisor_write(public_box, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL) - -/** Get the value at the target address. - * - * @param address[in] Target address - * @returns The value `*address`. - */ -#define SECURE_READ(address) \ - uvisor_read(public_box, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL) - -/** Get the selected bits at the target address. - * - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @returns The value `*address & mask`. - */ -#define SECURE_BITS_GET(address, mask) \ - UVISOR_BITS_GET(public_box, UVISOR_RGW_SHARED, address, mask) - -/** Check the selected bits at the target address. - * - * @param address[in] Address at which to check the bits - * @param mask[in] Bits to select out of the target address - * @returns The value `((*address & mask) == mask)`. - */ -#define SECURE_BITS_CHECK(address, mask) \ - UVISOR_BITS_CHECK(public_box, UVISOR_RGW_SHARED, address, mask) - -/** Set the selected bits to 1 at the target address. - * - * Equivalent to: `*address |= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_SET(address, mask) \ - UVISOR_BITS_SET(public_box, UVISOR_RGW_SHARED, address, mask) - -/** Clear the selected bits at the target address. - * - * Equivalent to: `*address &= ~mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_CLEAR(address, mask) \ - UVISOR_BITS_CLEAR(public_box, UVISOR_RGW_SHARED, address, mask) - -/** Set the selected bits at the target address to the given value. - * - * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @param value[in] Value to write at the address location. Note: The value - * must be already shifted to the correct bit position - */ -#define SECURE_BITS_SET_VALUE(address, mask, value) \ - UVISOR_BITS_SET_VALUE(public_box, UVISOR_RGW_SHARED, address, mask, value) - -/** Toggle the selected bits at the target address. - * - * Equivalent to: `*address ^= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_TOGGLE(address, mask) \ - UVISOR_BITS_TOGGLE(public_box, UVISOR_RGW_SHARED, address, mask) - -#else - -/* Insecure fallback implementation. */ - -/** Set the value at the target address. - * - * Equivalent to: `*address = value`. - * @param address[in] Target address - * @param value[in] Value to write at the address location. - */ -#define SECURE_WRITE(address, value) \ - *(address) = (value) - -/** Get the value at the target address. - * - * @param address[in] Target address - * @returns The value `*address`. - */ -#define SECURE_READ(address) \ - (*(address)) - -/** Get the selected bits at the target address. - * - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @returns The value `*address & mask`. - */ -#define SECURE_BITS_GET(address, mask) \ - (*(address) & (mask)) - -/** Check the selected bits at the target address. - * - * @param address[in] Address at which to check the bits - * @param mask[in] Bits to select out of the target address - * @returns The value `((*address & mask) == mask)`. - */ -#define SECURE_BITS_CHECK(address, mask) \ - ((*(address) & (mask)) == (mask)) - -/** Set the selected bits to 1 at the target address. - * - * Equivalent to: `*address |= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_SET(address, mask) \ - *(address) |= (mask) - -/** Clear the selected bits at the target address. - * - * Equivalent to: `*address &= ~mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_CLEAR(address, mask) \ - *(address) &= ~(mask) - -/** Set the selected bits at the target address to the given value. - * - * Equivalent to: `*address = (*address & ~mask) | (value & mask)`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - * @param value[in] Value to write at the address location. Note: The value - * must be already shifted to the correct bit position - */ -#define SECURE_BITS_SET_VALUE(address, mask, value) \ - *(address) = (*(address) & ~(mask)) | ((value) & (mask)) - -/** Toggle the selected bits at the target address. - * - * Equivalent to: `*address ^= mask`. - * @param address[in] Target address - * @param mask[in] Bits to select out of the target address - */ -#define SECURE_BITS_TOGGLE(address, mask) \ - *(address) ^= (mask) - -#endif - -#endif /* __CORE_CM_SECURE_ACCESS_H */
--- a/cmsis/TARGET_CORTEX_M/core_sc000.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_sc000.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 10. January 2018
+ * @version V5.0.5
+ * @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -727,6 +727,12 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
@@ -920,7 +926,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/core_sc300.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/core_sc300.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V5.0.3
- * @date 10. January 2018
+ * @version V5.0.6
+ * @date 04. June 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -977,7 +977,7 @@
*/
typedef struct
{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@@ -988,7 +988,7 @@
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
@@ -1058,8 +1058,11 @@
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1084,12 +1087,15 @@
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@@ -1111,11 +1117,11 @@
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
@@ -1436,6 +1442,12 @@
#define NVIC_USER_IRQ_OFFSET 16
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
/**
\brief Set Priority Grouping
@@ -1728,7 +1740,7 @@
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
-__STATIC_INLINE void __NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
--- a/cmsis/TARGET_CORTEX_M/mbed_tz_context.c Thu Sep 06 13:40:20 2018 +0100 +++ b/cmsis/TARGET_CORTEX_M/mbed_tz_context.c Thu Nov 08 11:46:34 2018 +0000 @@ -20,17 +20,8 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 15. October 2016 - * $Revision: 1.1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - Sample implementation - * - *---------------------------------------------------------------------------*/ - + */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "RTE_Components.h"
--- a/cmsis/TARGET_CORTEX_M/mpu_armv7.h Thu Sep 06 13:40:20 2018 +0100
+++ b/cmsis/TARGET_CORTEX_M/mpu_armv7.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,8 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
- * @version V5.0.4
- * @date 10. January 2018
+ * @version V5.0.5
+ * @date 06. September 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
@@ -31,41 +31,41 @@
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
-#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
-#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
-#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
-#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
-#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
-#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
-#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
-#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
-#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
-#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
-#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
-#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
-#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
-#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
-#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
-#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
-#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
-#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
-#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
-#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
-#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
-#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
-#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
-#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
-#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
-#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
-#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
-#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
-#define ARM_MPU_AP_NONE 0U
-#define ARM_MPU_AP_PRIV 1U
-#define ARM_MPU_AP_URO 2U
-#define ARM_MPU_AP_FULL 3U
-#define ARM_MPU_AP_PRO 5U
-#define ARM_MPU_AP_RO 6U
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
@@ -78,6 +78,37 @@
(MPU_RBAR_VALID_Msk))
/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
@@ -90,15 +121,60 @@
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
- ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
- (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
- (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
- (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
- (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
- (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
- (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
- (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
- (MPU_RASR_ENABLE_Msk))
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
/**
--- a/cmsis/TARGET_CORTEX_M/mpu_armv8.h Thu Sep 06 13:40:20 2018 +0100 +++ b/cmsis/TARGET_CORTEX_M/mpu_armv8.h Thu Nov 08 11:46:34 2018 +0000 @@ -87,7 +87,7 @@ * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Pos) | \ + ((BASE & MPU_RBAR_BASE_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
--- a/drivers/AnalogIn.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/AnalogIn.h Thu Nov 08 11:46:34 2018 +0000
@@ -79,7 +79,7 @@
/** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @returns
- * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+ * 16-bit unsigned short representing the current input voltage, normalized to a 16-bit value
*/
unsigned short read_u16()
{
@@ -114,7 +114,7 @@
}
protected:
-
+ #if !defined(DOXYGEN_ONLY)
virtual void lock()
{
_mutex->lock();
@@ -127,6 +127,7 @@
analogin_t _adc;
static SingletonPtr<PlatformMutex> _mutex;
+ #endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/AnalogOut.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/AnalogOut.h Thu Nov 08 11:46:34 2018 +0000
@@ -79,7 +79,7 @@
/** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @param value 16-bit unsigned short representing the output voltage,
- * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+ * normalized to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
*/
void write_u16(unsigned short value)
{
@@ -141,7 +141,7 @@
}
protected:
-
+ #if !defined(DOXYGEN_ONLY)
virtual void lock()
{
_mutex.lock();
@@ -154,6 +154,7 @@
dac_t _dac;
PlatformMutex _mutex;
+ #endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/CAN.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/CAN.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,6 @@
#if DEVICE_CAN
-#include "cmsis.h"
#include "platform/mbed_power_mgmt.h"
namespace mbed {
--- a/drivers/CAN.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/CAN.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,7 +55,7 @@
* @param _type Type of Data: Use enum CANType for valid parameter values
* @param _format Data Format: Use enum CANFormat for valid parameter values
*/
- CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard)
+ CANMessage(unsigned _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard)
{
len = _len & 0xF;
type = _type;
@@ -69,7 +69,7 @@
* @param _id Message ID
* @param _format Data Format: Use enum CANType for valid parameter values
*/
- CANMessage(int _id, CANFormat _format = CANStandard)
+ CANMessage(unsigned _id, CANFormat _format = CANStandard)
{
len = 0;
type = CANRemote;
@@ -85,7 +85,7 @@
class CAN : private NonCopyable<CAN> {
public:
- /** Creates an CAN interface connected to specific pins.
+ /** Creates a CAN interface connected to specific pins.
*
* @param rd read from transmitter
* @param td transmit to transmitter
@@ -94,11 +94,14 @@
* @code
* #include "mbed.h"
*
+ *
* Ticker ticker;
* DigitalOut led1(LED1);
* DigitalOut led2(LED2);
- * CAN can1(p9, p10);
- * CAN can2(p30, p29);
+ * //The constructor takes in RX, and TX pin respectively.
+ * //These pins, for this example, are defined in mbed_app.json
+ * CAN can1(MBED_CONF_APP_CAN1_RD, MBED_CONF_APP_CAN1_TD);
+ * CAN can2(MBED_CONF_APP_CAN2_RD, MBED_CONF_APP_CAN2_TD);
*
* char counter = 0;
*
@@ -121,14 +124,15 @@
* wait(0.2);
* }
* }
+ *
* @endcode
*/
CAN(PinName rd, PinName td);
/** Initialize CAN interface and set the frequency
*
- * @param rd the rd pin
- * @param td the td pin
+ * @param rd the read pin
+ * @param td the transmit pin
* @param hz the bus frequency in hertz
*/
CAN(PinName rd, PinName td, int hz);
@@ -197,7 +201,7 @@
*/
int mode(Mode mode);
- /** Filter out incomming messages
+ /** Filter out incoming messages
*
* @param id the id to filter on
* @param mask the mask applied to the id
@@ -288,12 +292,14 @@
static void _irq_handler(uint32_t id, CanIrqType type);
+#if !defined(DOXYGEN_ONLY)
protected:
virtual void lock();
virtual void unlock();
can_t _can;
Callback<void()> _irq[IrqCnt];
PlatformMutex _mutex;
+#endif
};
} // namespace mbed
--- a/drivers/DigitalIn.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/DigitalIn.h Thu Nov 08 11:46:34 2018 +0000
@@ -108,6 +108,11 @@
/** An operator shorthand for read()
* \sa DigitalIn::read()
+ * @code
+ * DigitalIn button(BUTTON1);
+ * DigitalOut led(LED1);
+ * led = button; // Equivalent to led.write(button.read())
+ * @endcode
*/
operator int()
{
@@ -116,7 +121,9 @@
}
protected:
+ #if !defined(DOXYGEN_ONLY)
gpio_t gpio;
+ #endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/DigitalInOut.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/DigitalInOut.h Thu Nov 08 11:46:34 2018 +0000
@@ -121,6 +121,13 @@
/** A shorthand for write()
* \sa DigitalInOut::write()
+ * @code
+ * DigitalInOut inout(PIN);
+ * DigitalIn button(BUTTON1);
+ * inout.output();
+ *
+ * inout = button; // Equivalent to inout.write(button.read())
+ * @endcode
*/
DigitalInOut &operator= (int value)
{
@@ -129,7 +136,8 @@
return *this;
}
- /** A shorthand for write()
+ /**A shorthand for write() using the assignment operator which copies the
+ * state from the DigitalInOut argument.
* \sa DigitalInOut::write()
*/
DigitalInOut &operator= (DigitalInOut &rhs)
@@ -142,6 +150,13 @@
/** A shorthand for read()
* \sa DigitalInOut::read()
+ * @code
+ * DigitalInOut inout(PIN);
+ * DigitalOut led(LED1);
+ *
+ * inout.input();
+ * led = inout; // Equivalent to led.write(inout.read())
+ * @endcode
*/
operator int()
{
@@ -150,7 +165,9 @@
}
protected:
+ #if !defined(DOXYGEN_ONLY)
gpio_t gpio;
+ #endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/DigitalOut.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/DigitalOut.h Thu Nov 08 11:46:34 2018 +0000
@@ -104,6 +104,11 @@
/** A shorthand for write()
* \sa DigitalOut::write()
+ * @code
+ * DigitalIn button(BUTTON1);
+ * DigitalOut led(LED1);
+ * led = button; // Equivalent to led.write(button.read())
+ * @endcode
*/
DigitalOut &operator= (int value)
{
@@ -112,7 +117,8 @@
return *this;
}
- /** A shorthand for write()
+ /** A shorthand for write() using the assignment operator which copies the
+ * state from the DigitalOut argument.
* \sa DigitalOut::write()
*/
DigitalOut &operator= (DigitalOut &rhs)
@@ -125,6 +131,11 @@
/** A shorthand for read()
* \sa DigitalOut::read()
+ * @code
+ * DigitalIn button(BUTTON1);
+ * DigitalOut led(LED1);
+ * led = button; // Equivalent to led.write(button.read())
+ * @endcode
*/
operator int()
{
@@ -133,7 +144,9 @@
}
protected:
+ #if !defined(DOXYGEN_ONLY)
gpio_t gpio;
+ #endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/Ethernet.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/Ethernet.h Thu Nov 08 11:46:34 2018 +0000
@@ -59,7 +59,7 @@
public:
- /** Initialise the ethernet interface.
+ /** Initialize the ethernet interface.
*/
Ethernet();
--- a/drivers/FlashIAP.cpp Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/FlashIAP.cpp Thu Nov 08 11:46:34 2018 +0000 @@ -24,7 +24,7 @@ #include <string.h> #include <algorithm> #include "FlashIAP.h" -#include "mbed_assert.h" +#include "platform/mbed_assert.h" #ifdef DEVICE_FLASH
--- a/drivers/FlashIAP.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/FlashIAP.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,6 +28,20 @@
#include "platform/SingletonPtr.h"
#include "platform/PlatformMutex.h"
#include "platform/NonCopyable.h"
+#include <algorithm>
+
+// Export ROM end address
+#if defined(TOOLCHAIN_GCC_ARM)
+extern uint32_t __etext;
+#define FLASHIAP_ROM_END ((uint32_t) &__etext)
+#elif defined(TOOLCHAIN_ARM)
+extern uint32_t Load$$LR$$LR_IROM1$$Limit[];
+#define FLASHIAP_ROM_END ((uint32_t)Load$$LR$$LR_IROM1$$Limit)
+#elif defined(TOOLCHAIN_IAR)
+#pragma section=".rodata"
+#pragma section=".text"
+#define FLASHIAP_ROM_END (std::max((uint32_t) __section_end(".rodata"), (uint32_t) __section_end(".text")))
+#endif
namespace mbed {
--- a/drivers/I2C.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/I2C.h Thu Nov 08 11:46:34 2018 +0000
@@ -163,7 +163,7 @@
* This function locks the deep sleep until any event has occurred
*
* @param address 8/10 bit I2C slave address
- * @param tx_buffer The TX buffer with data to be transfered
+ * @param tx_buffer The TX buffer with data to be transferred
* @param tx_length The length of TX buffer in bytes
* @param rx_buffer The RX buffer which is used for received data
* @param rx_length The length of RX buffer in bytes
--- a/drivers/I2CSlave.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/I2CSlave.h Thu Nov 08 11:46:34 2018 +0000
@@ -25,38 +25,41 @@
namespace mbed {
/** \addtogroup drivers */
-/** An I2C Slave, used for communicating with an I2C Master device
+/** An I2C Slave, used for communicating with an I2C Master device.
*
* @note Synchronization level: Not protected
*
- * Example:
+ * Example Simple I2C responder:
* @code
- * // Simple I2C responder
* #include <mbed.h>
*
- * I2CSlave slave(p9, p10);
+ * const int SLAVE_ADDRESS = 0xA0;
+ * const char message[] = "Slave!";
+ *
+ * I2CSlave slave(I2C_SDA, I2C_SCL);
*
* int main() {
- * char buf[10];
- * char msg[] = "Slave!";
- *
- * slave.address(0xA0);
+ * slave.address(SLAVE_ADDRESS);
* while (1) {
- * int i = slave.receive();
- * switch (i) {
+ * int operation = slave.receive();
+ * switch (operation) {
* case I2CSlave::ReadAddressed:
- * slave.write(msg, strlen(msg) + 1); // Includes null char
+ * int status = slave.write(message, sizeof(message));
+ * if (status == 0) {
+ * printf("Written message: %s\n", message);
+ * } else {
+ * printf("Failed to write message.\n");
+ * }
* break;
* case I2CSlave::WriteGeneral:
- * slave.read(buf, 10);
- * printf("Read G: %s\n", buf);
+ * int byte_read = slave.read();
+ * printf("Read General: %c (%d)\n", byte_read, byte_read);
* break;
* case I2CSlave::WriteAddressed:
- * slave.read(buf, 10);
- * printf("Read A: %s\n", buf);
+ * int byte_read = slave.read();
+ * printf("Read Addressed: %c (%d)\n", byte_read, byte_read);
* break;
* }
- * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
* }
* }
* @endcode
@@ -74,71 +77,71 @@
/** Create an I2C Slave interface, connected to the specified pins.
*
- * @param sda I2C data line pin
- * @param scl I2C clock line pin
+ * @param sda I2C data line pin.
+ * @param scl I2C clock line pin.
*/
I2CSlave(PinName sda, PinName scl);
- /** Set the frequency of the I2C interface
+ /** Set the frequency of the I2C interface.
*
- * @param hz The bus frequency in hertz
+ * @param hz The bus frequency in Hertz.
*/
void frequency(int hz);
- /** Checks to see if this I2C Slave has been addressed.
+ /** Check if this I2C Slave has been addressed.
*
- * @returns
- * A status indicating if the device has been addressed, and how
- * - NoData - the slave has not been addressed
- * - ReadAddressed - the master has requested a read from this slave
- * - WriteAddressed - the master is writing to this slave
- * - WriteGeneral - the master is writing to all slave
+ * @return A status indicating if the device has been addressed and how.
+ * @retval NoData The slave has not been addressed.
+ * @retval ReadAddressed The master has requested a read from this slave.
+ * @retval WriteAddressed The master is writing to this slave.
+ * @retval WriteGeneral The master is writing to all slave.
*/
int receive(void);
- /** Read from an I2C master.
+ /** Read specified number of bytes from an I2C master.
*
- * @param data pointer to the byte array to read data in to
- * @param length maximum number of bytes to read
+ * @param data Pointer to the buffer to read data into.
+ * @param length Number of bytes to read.
*
- * @returns
- * 0 on success,
- * non-0 otherwise
+ * @return Result of the operation.
+ * @retval 0 If the number of bytes read is equal to length requested.
+ * @retval nonzero On error or if the number of bytes read is less than requested.
*/
int read(char *data, int length);
/** Read a single byte from an I2C master.
*
- * @returns
- * the byte read
+ * @return The byte read.
*/
int read(void);
/** Write to an I2C master.
*
- * @param data pointer to the byte array to be transmitted
- * @param length the number of bytes to transmite
+ * @param data Pointer to the buffer containing the data to be sent.
+ * @param length Number of bytes to send.
*
- * @returns
- * 0 on success,
- * non-0 otherwise
+ * @return
+ * @retval 0 If written all bytes successfully.
+ * @retval nonzero On error or if the number of bytes written is less than requested.
*/
int write(const char *data, int length);
/** Write a single byte to an I2C master.
*
- * @param data the byte to write
+ * @param data Value to write.
*
- * @returns
- * '1' if an ACK was received,
- * '0' otherwise
+ * @return Result of the operation.
+ * @retval 0 If a NACK is received.
+ * @retval 1 If an ACK is received.
+ * @retval 2 On timeout.
*/
int write(int data);
- /** Sets the I2C slave address.
+ /** Set the I2C slave address.
*
- * @param address The address to set for the slave (ignoring the least
- * signifcant bit). If set to 0, the slave will only respond to the
+ * @param address The address to set for the slave (least significant bit is ignored).
+ *
+ * @note If address is set to 0, the slave will only respond to the
* general call address.
*/
void address(int address);
@@ -147,8 +150,13 @@
*/
void stop(void);
+#if !defined(DOXYGEN_ONLY)
+
protected:
+ /* Internal i2c object identifying the resources */
i2c_t _i2c;
+
+#endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/InterruptIn.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/InterruptIn.h Thu Nov 08 11:46:34 2018 +0000
@@ -48,6 +48,7 @@
* }
*
* int main() {
+ * // register trigger() to be called upon the rising edge of event
* event.rise(&trigger);
* while(1) {
* led = !led;
@@ -71,7 +72,10 @@
* and the pin configured to the specified mode.
*
* @param pin InterruptIn pin to connect to
- * @param mode The mode to set the pin to (PullUp/PullDown/etc.)
+ * @param mode Desired Pin mode configuration.
+ * (Valid values could be PullNone, PullDown, PullUp and PullDefault.
+ * See PinNames.h for your target for definitions)
+ *
*/
InterruptIn(PinName pin, PinMode mode);
@@ -142,22 +146,23 @@
/** Set the input pin mode
*
- * @param pull PullUp, PullDown, PullNone
+ * @param pull PullUp, PullDown, PullNone, PullDefault
+ * See PinNames.h for your target for definitions)
*/
void mode(PinMode pull);
- /** Enable IRQ. This method depends on hw implementation, might enable one
+ /** Enable IRQ. This method depends on hardware implementation, might enable one
* port interrupts. For further information, check gpio_irq_enable().
*/
void enable_irq();
- /** Disable IRQ. This method depends on hw implementation, might disable one
+ /** Disable IRQ. This method depends on hardware implementation, might disable one
* port interrupts. For further information, check gpio_irq_disable().
*/
void disable_irq();
static void _irq_handler(uint32_t id, gpio_irq_event event);
-
+#if !defined(DOXYGEN_ONLY)
protected:
gpio_t gpio;
gpio_irq_t gpio_irq;
@@ -166,6 +171,7 @@
Callback<void()> _fall;
void irq_init(PinName pin);
+#endif
};
} // namespace mbed
--- a/drivers/MbedCRC.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/MbedCRC.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -22,52 +22,22 @@
/** \addtogroup drivers */
/** @{*/
+SingletonPtr<PlatformMutex> mbed_crc_mutex;
+
/* Default values for different types of polynomials
*/
template<>
-MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC():
+ _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true),
_crc_table((uint32_t *)Table_CRC_32bit_ANSI)
{
mbed_crc_ctor();
}
template<>
-MbedCRC<POLY_8BIT_CCITT, 8>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
- _crc_table((uint32_t *)Table_CRC_8bit_CCITT)
-{
- mbed_crc_ctor();
-}
-
-template<>
-MbedCRC<POLY_7BIT_SD, 7>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
- _crc_table((uint32_t *)Table_CRC_7Bit_SD)
-{
- mbed_crc_ctor();
-}
-
-template<>
-MbedCRC<POLY_16BIT_CCITT, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
- _crc_table((uint32_t *)Table_CRC_16bit_CCITT)
-{
- mbed_crc_ctor();
-}
-
-template<>
-MbedCRC<POLY_16BIT_IBM, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
- _crc_table((uint32_t *)Table_CRC_16bit_IBM)
-{
- mbed_crc_ctor();
-}
-
-template<>
-MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC():
- _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true),
- _crc_table((uint32_t *)Table_CRC_32bit_ANSI)
+MbedCRC<POLY_32BIT_REV_ANSI, 32>::MbedCRC():
+ _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(false), _reflect_remainder(false),
+ _crc_table((uint32_t *)Table_CRC_32bit_Rev_ANSI)
{
mbed_crc_ctor();
}
--- a/drivers/MbedCRC.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/MbedCRC.h Thu Nov 08 11:46:34 2018 +0000
@@ -19,6 +19,8 @@
#include "drivers/TableCRC.h"
#include "hal/crc_api.h"
#include "platform/mbed_assert.h"
+#include "platform/SingletonPtr.h"
+#include "platform/PlatformMutex.h"
/* This is invalid warning from the compiler for below section of code
if ((width < 8) && (NULL == _crc_table)) {
@@ -45,6 +47,7 @@
* ROM polynomial tables for supported polynomials (:: crc_polynomial_t) will be used for
* software CRC computation, if ROM tables are not available then CRC is computed runtime
* bit by bit for all data input.
+ * @note Synchronization level: Thread safe
*
* @tparam polynomial CRC polynomial value in hex
* @tparam width CRC polynomial width
@@ -79,12 +82,10 @@
* uint32_t crc = 0;
*
* printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width());
- *
* ct.compute_partial_start(&crc);
* ct.compute_partial((void *)&test, 4, &crc);
* ct.compute_partial((void *)&test[4], 5, &crc);
* ct.compute_partial_stop(&crc);
- *
* printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
* return 0;
* }
@@ -92,12 +93,21 @@
* @ingroup drivers
*/
+extern SingletonPtr<PlatformMutex> mbed_crc_mutex;
+
template <uint32_t polynomial = POLY_32BIT_ANSI, uint8_t width = 32>
class MbedCRC {
-public:
- enum CrcMode { HARDWARE = 0, TABLE, BITWISE };
public:
+ enum CrcMode
+ {
+#ifdef DEVICE_CRC
+ HARDWARE = 0,
+#endif
+ TABLE = 1,
+ BITWISE
+ };
+
typedef uint64_t crc_data_size_t;
/** Lifetime of CRC object
@@ -106,18 +116,18 @@
* @param final_xor Final Xor value
* @param reflect_data
* @param reflect_remainder
- * @note Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t
+ * @note Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t
* MbedCRC <POLY_7BIT_SD, 7> ct; --- Valid POLY_7BIT_SD
* MbedCRC <0x1021, 16> ct; --- Valid POLY_16BIT_CCITT
* MbedCRC <POLY_16BIT_CCITT, 32> ct; --- Invalid, compilation error
- * MbedCRC <POLY_16BIT_CCITT, 32> ct (i,f,rd,rr) Consturctor can be used for not supported polynomials
+ * MbedCRC <POLY_16BIT_CCITT, 32> ct (i,f,rd,rr) Constructor can be used for not supported polynomials
* MbedCRC<POLY_16BIT_CCITT, 16> sd(0, 0, false, false); Constructor can also be used for supported
* polynomials with different intial/final/reflect values
*
*/
MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder) :
_initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data),
- _reflect_remainder(reflect_remainder), _crc_table(NULL)
+ _reflect_remainder(reflect_remainder)
{
mbed_crc_ctor();
}
@@ -128,6 +138,8 @@
}
/** Compute CRC for the data input
+ * Compute CRC performs the initialization, computation and collection of
+ * final CRC.
*
* @param buffer Data bytes
* @param size Size of data
@@ -137,55 +149,76 @@
int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc)
{
MBED_ASSERT(crc != NULL);
- int32_t status;
- if (0 != (status = compute_partial_start(crc))) {
- *crc = 0;
+ int32_t status = 0;
+
+ status = compute_partial_start(crc);
+ if (0 != status) {
+ unlock();
return status;
}
- if (0 != (status = compute_partial(buffer, size, crc))) {
- *crc = 0;
+
+ status = compute_partial(buffer, size, crc);
+ if (0 != status) {
+ unlock();
return status;
}
- if (0 != (status = compute_partial_stop(crc))) {
- *crc = 0;
- return status;
+
+ status = compute_partial_stop(crc);
+ if (0 != status) {
+ *crc = 0;
}
- return 0;
+
+ return status;
+
}
/** Compute partial CRC for the data input.
*
* CRC data if not available fully, CRC can be computed in parts with available data.
- * Previous CRC output should be passed as argument to the current compute_partial call.
- * @pre: Call \ref compute_partial_start to start the partial CRC calculation.
- * @post: Call \ref compute_partial_stop to get the final CRC value.
+ *
+ * In case of hardware, intermediate values and states are saved by hardware. Mutex
+ * locking is used to serialize access to hardware CRC.
+ *
+ * In case of software CRC, previous CRC output should be passed as argument to the
+ * current compute_partial call. Please note the intermediate CRC value is maintained by
+ * application and not the driver.
+ *
+ * @pre: Call `compute_partial_start` to start the partial CRC calculation.
+ * @post: Call `compute_partial_stop` to get the final CRC value.
*
* @param buffer Data bytes
* @param size Size of data
* @param crc CRC value is intermediate CRC value filled by API.
* @return 0 on success or a negative error code on failure
- * @note: CRC as output in compute_partial is not final CRC value, call @ref compute_partial_stop
+ * @note: CRC as output in compute_partial is not final CRC value, call `compute_partial_stop`
* to get final correct CRC value.
*/
int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc)
{
+ int32_t status = 0;
+
switch (_mode) {
- case HARDWARE:
#ifdef DEVICE_CRC
+ case HARDWARE:
hal_crc_compute_partial((uint8_t *)buffer, size);
-#endif // DEVICE_CRC
*crc = 0;
- return 0;
+ break;
+#endif
case TABLE:
- return table_compute_partial(buffer, size, crc);
+ status = table_compute_partial(buffer, size, crc);
+ break;
case BITWISE:
- return bitwise_compute_partial(buffer, size, crc);
+ status = bitwise_compute_partial(buffer, size, crc);
+ break;
+ default:
+ status = -1;
+ break;
}
- return -1;
+ return status;
}
- /** Compute partial start, indicate start of partial computation
+ /** Compute partial start, indicate start of partial computation.
*
* This API should be called before performing any partial computation
* with compute_partial API.
@@ -193,7 +226,7 @@
* @param crc Initial CRC value set by the API
* @return 0 on success or a negative in case of failure
* @note: CRC is an out parameter and must be reused with compute_partial
- * and compute_partial_stop without any modifications in application.
+ * and `compute_partial_stop` without any modifications in application.
*/
int32_t compute_partial_start(uint32_t *crc)
{
@@ -201,6 +234,7 @@
#ifdef DEVICE_CRC
if (_mode == HARDWARE) {
+ lock();
crc_mbed_config_t config;
config.polynomial = polynomial;
config.width = width;
@@ -211,7 +245,7 @@
hal_crc_compute_partial_start(&config);
}
-#endif // DEVICE_CRC
+#endif
*crc = _initial_value;
return 0;
@@ -224,29 +258,34 @@
* This API is used to perform final computation to get correct CRC value.
*
* @param crc CRC result
+ * @return 0 on success or a negative in case of failure.
*/
int32_t compute_partial_stop(uint32_t *crc)
{
MBED_ASSERT(crc != NULL);
+#ifdef DEVICE_CRC
if (_mode == HARDWARE) {
-#ifdef DEVICE_CRC
*crc = hal_crc_get_result();
+ unlock();
return 0;
-#else
- return -1;
+ }
#endif
- }
-
uint32_t p_crc = *crc;
if ((width < 8) && (NULL == _crc_table)) {
p_crc = (uint32_t)(p_crc << (8 - width));
}
- *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask();
+ // Optimized algorithm for 32BitANSI does not need additional reflect_remainder
+ if ((TABLE == _mode) && (POLY_32BIT_REV_ANSI == polynomial)) {
+ *crc = (p_crc ^ _final_xor) & get_crc_mask();
+ } else {
+ *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask();
+ }
+ unlock();
return 0;
}
- /** Get the current CRC polynomial
+ /** Get the current CRC polynomial.
*
* @return Polynomial value
*/
@@ -272,7 +311,29 @@
uint32_t *_crc_table;
CrcMode _mode;
- /** Get the current CRC data size
+ /** Acquire exclusive access to CRC hardware/software.
+ */
+ void lock()
+ {
+#ifdef DEVICE_CRC
+ if (_mode == HARDWARE) {
+ mbed_crc_mutex->lock();
+ }
+#endif
+ }
+
+ /** Release exclusive access to CRC hardware/software.
+ */
+ virtual void unlock()
+ {
+#ifdef DEVICE_CRC
+ if (_mode == HARDWARE) {
+ mbed_crc_mutex->unlock();
+ }
+#endif
+ }
+
+ /** Get the current CRC data size.
*
* @return CRC data size in bytes
*/
@@ -281,7 +342,7 @@
return (width <= 8 ? 1 : (width <= 16 ? 2 : 4));
}
- /** Get the top bit of current CRC
+ /** Get the top bit of current CRC.
*
* @return Top bit is set high for respective data width of current CRC
* Top bit for CRC width less then 8 bits will be set as 8th bit.
@@ -291,7 +352,7 @@
return (width < 8 ? (1u << 7) : (uint32_t)(1ul << (width - 1)));
}
- /** Get the CRC data mask
+ /** Get the CRC data mask.
*
* @return CRC data mask is generated based on current CRC width
*/
@@ -300,7 +361,7 @@
return (width < 8 ? ((1u << 8) - 1) : (uint32_t)((uint64_t)(1ull << width) - 1));
}
- /** Final value of CRC is reflected
+ /** Final value of CRC is reflected.
*
* @param data final crc value, which should be reflected
* @return Reflected CRC value
@@ -323,7 +384,7 @@
}
}
- /** Data bytes are reflected
+ /** Data bytes are reflected.
*
* @param data value to be reflected
* @return Reflected data value
@@ -345,7 +406,7 @@
}
}
- /** Bitwise CRC computation
+ /** Bitwise CRC computation.
*
* @param buffer data buffer
* @param size size of the data
@@ -355,7 +416,6 @@
int32_t bitwise_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
{
MBED_ASSERT(crc != NULL);
- MBED_ASSERT(buffer != NULL);
const uint8_t *data = static_cast<const uint8_t *>(buffer);
uint32_t p_crc = *crc;
@@ -390,7 +450,7 @@
return 0;
}
- /** CRC computation using ROM tables
+ /** CRC computation using ROM tables.
*
* @param buffer data buffer
* @param size size of the data
@@ -400,7 +460,6 @@
int32_t table_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
{
MBED_ASSERT(crc != NULL);
- MBED_ASSERT(buffer != NULL);
const uint8_t *data = static_cast<const uint8_t *>(buffer);
uint32_t p_crc = *crc;
@@ -420,25 +479,36 @@
}
} else {
uint32_t *crc_table = (uint32_t *)_crc_table;
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
- p_crc = crc_table[data_byte] ^ (p_crc << 8);
+ if (POLY_32BIT_REV_ANSI == polynomial) {
+ for (crc_data_size_t i = 0; i < size; i++) {
+ p_crc = (p_crc >> 4) ^ crc_table[(p_crc ^ (data[i] >> 0)) & 0xf];
+ p_crc = (p_crc >> 4) ^ crc_table[(p_crc ^ (data[i] >> 4)) & 0xf];
+ }
+ }
+ else {
+ for (crc_data_size_t byte = 0; byte < size; byte++) {
+ data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
+ p_crc = crc_table[data_byte] ^ (p_crc << 8);
+ }
}
}
*crc = p_crc & get_crc_mask();
return 0;
}
- /** Constructor init called from all specialized cases of constructor
+ /** Constructor init called from all specialized cases of constructor.
* Note: All construtor common code should be in this function.
*/
void mbed_crc_ctor(void)
{
MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported");
- _mode = (_crc_table != NULL) ? TABLE : BITWISE;
-
#ifdef DEVICE_CRC
+ if (POLY_32BIT_REV_ANSI == polynomial) {
+ _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI;
+ _mode = TABLE;
+ return;
+ }
crc_mbed_config_t config;
config.polynomial = polynomial;
config.width = width;
@@ -449,8 +519,34 @@
if (hal_crc_is_supported(&config)) {
_mode = HARDWARE;
+ return;
}
#endif
+
+ switch (polynomial) {
+ case POLY_32BIT_ANSI:
+ _crc_table = (uint32_t *)Table_CRC_32bit_ANSI;
+ break;
+ case POLY_32BIT_REV_ANSI:
+ _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI;
+ break;
+ case POLY_8BIT_CCITT:
+ _crc_table = (uint32_t *)Table_CRC_8bit_CCITT;
+ break;
+ case POLY_7BIT_SD:
+ _crc_table = (uint32_t *)Table_CRC_7Bit_SD;
+ break;
+ case POLY_16BIT_CCITT:
+ _crc_table = (uint32_t *)Table_CRC_16bit_CCITT;
+ break;
+ case POLY_16BIT_IBM:
+ _crc_table = (uint32_t *)Table_CRC_16bit_IBM;
+ break;
+ default:
+ _crc_table = NULL;
+ break;
+ }
+ _mode = (_crc_table != NULL) ? TABLE : BITWISE;
}
};
--- a/drivers/PortIn.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/PortIn.h Thu Nov 08 11:46:34 2018 +0000
@@ -32,20 +32,20 @@
*
* Example:
* @code
- * // Switch on an LED if any of mbed pins 21-26 is high
+ * // Turn on an LED if any pins of Port2[0:5] are high
*
* #include "mbed.h"
*
- * PortIn p(Port2, 0x0000003F); // p21-p26
- * DigitalOut ind(LED4);
+ * PortIn p(Port2, 0x0000003F); // Port2 pins [0:5] only
+ * DigitalOut led(LED4);
*
* int main() {
* while(1) {
* int pins = p.read();
* if(pins) {
- * ind = 1;
+ * led = 1;
* } else {
- * ind = 0;
+ * led = 0;
* }
* }
* }
@@ -55,10 +55,10 @@
class PortIn {
public:
- /** Create an PortIn, connected to the specified port
+ /** Create a PortIn, connected to the specified port
*
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param port Port to connect to (as defined in target's PortNames.h)
+ * @param mask Bitmask defines which port pins should be an input (0 - ignore, 1 - include)
*/
PortIn(PortName port, int mask = 0xFFFFFFFF)
{
@@ -67,10 +67,10 @@
core_util_critical_section_exit();
}
- /** Read the value currently output on the port
+ /** Read the value input to the port
*
* @returns
- * An integer with each bit corresponding to associated port pin setting
+ * An integer with each bit corresponding to the associated pin value
*/
int read()
{
--- a/drivers/PortOut.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/PortOut.h Thu Nov 08 11:46:34 2018 +0000
@@ -25,7 +25,7 @@
namespace mbed {
/** \addtogroup drivers */
-/** A multiple pin digital out
+/** A multiple pin digital output
*
* @note Synchronization level: Interrupt safe
*
@@ -54,10 +54,10 @@
class PortOut {
public:
- /** Create an PortOut, connected to the specified port
+ /** Create a PortOut, connected to the specified port
*
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param port Port to connect to (as defined in target's PortNames.h)
+ * @param mask Bitmask defines which port pins are an output (0 - ignore, 1 - include)
*/
PortOut(PortName port, int mask = 0xFFFFFFFF)
{
@@ -78,7 +78,7 @@
/** Read the value currently output on the port
*
* @returns
- * An integer with each bit corresponding to associated PortOut pin setting
+ * An integer with each bit corresponding to associated pin value
*/
int read()
{
--- a/drivers/PwmOut.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/PwmOut.h Thu Nov 08 11:46:34 2018 +0000
@@ -32,7 +32,7 @@
*
* Example
* @code
- * // Fade a led on.
+ * // Gradually change the intensity of the LED.
* #include "mbed.h"
*
* PwmOut led(LED1);
@@ -71,7 +71,7 @@
core_util_critical_section_exit();
}
- /** Set the ouput duty-cycle, specified as a percentage (float)
+ /** Set the output duty-cycle, specified as a percentage (float)
*
* @param value A floating-point value representing the output duty-cycle,
* specified as a percentage. The value should lie between
@@ -118,8 +118,8 @@
core_util_critical_section_exit();
}
- /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
- * @param ms Change the period of a PWM signal in milli-seconds without modifying the duty cycle
+ /** Set the PWM period, specified in milliseconds (int), keeping the duty cycle the same.
+ * @param ms Change the period of a PWM signal in milliseconds without modifying the duty cycle
*/
void period_ms(int ms)
{
@@ -128,8 +128,8 @@
core_util_critical_section_exit();
}
- /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
- * @param us Change the period of a PWM signal in micro-seconds without modifying the duty cycle
+ /** Set the PWM period, specified in microseconds (int), keeping the duty cycle the same.
+ * @param us Change the period of a PWM signal in microseconds without modifying the duty cycle
*/
void period_us(int us)
{
@@ -148,8 +148,8 @@
core_util_critical_section_exit();
}
- /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
- * @param ms Change the pulse width of a PWM signal specified in milli-seconds
+ /** Set the PWM pulsewidth, specified in milliseconds (int), keeping the period the same.
+ * @param ms Change the pulse width of a PWM signal specified in milliseconds
*/
void pulsewidth_ms(int ms)
{
@@ -158,8 +158,8 @@
core_util_critical_section_exit();
}
- /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
- * @param us Change the pulse width of a PWM signal specified in micro-seconds
+ /** Set the PWM pulsewidth, specified in microseconds (int), keeping the period the same.
+ * @param us Change the pulse width of a PWM signal specified in microseconds
*/
void pulsewidth_us(int us)
{
@@ -197,6 +197,7 @@
return read();
}
+#if !(DOXYGEN_ONLY)
protected:
/** Lock deep sleep only if it is not yet locked */
void lock_deep_sleep()
@@ -218,6 +219,7 @@
pwmout_t _pwm;
bool _deep_sleep_locked;
+#endif
};
} // namespace mbed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/QSPI.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,288 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "drivers/QSPI.h"
+#include "platform/mbed_critical.h"
+#include <string.h>
+
+#if DEVICE_QSPI
+
+namespace mbed {
+
+QSPI *QSPI::_owner = NULL;
+SingletonPtr<PlatformMutex> QSPI::_mutex;
+
+QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
+{
+ _qspi_io0 = io0;
+ _qspi_io1 = io1;
+ _qspi_io2 = io2;
+ _qspi_io3 = io3;
+ _qspi_clk = sclk;
+ _qspi_cs = ssel;
+ _inst_width = QSPI_CFG_BUS_SINGLE;
+ _address_width = QSPI_CFG_BUS_SINGLE;
+ _address_size = QSPI_CFG_ADDR_SIZE_24;
+ _alt_width = QSPI_CFG_BUS_SINGLE;
+ _alt_size = QSPI_CFG_ALT_SIZE_8;
+ _data_width = QSPI_CFG_BUS_SINGLE;
+ _num_dummy_cycles = 0;
+ _mode = mode;
+ _hz = ONE_MHZ;
+ _initialized = false;
+
+ //Go ahead init the device here with the default config
+ bool success = _initialize();
+ MBED_ASSERT(success);
+}
+
+qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
+{
+ qspi_status_t ret_status = QSPI_STATUS_OK;
+
+ lock();
+ _inst_width = inst_width;
+ _address_width = address_width;
+ _address_size = address_size;
+ _alt_width = alt_width;
+ _alt_size = alt_size;
+ _data_width = data_width;
+ _num_dummy_cycles = dummy_cycles;
+
+ unlock();
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::set_frequency(int hz)
+{
+ qspi_status_t ret_status = QSPI_STATUS_OK;
+
+ if (_initialized) {
+ lock();
+ _hz = hz;
+ //If the same owner, just change freq.
+ //Otherwise we may have to change mode as well, so call _acquire
+ if (_owner == this) {
+ if (QSPI_STATUS_OK != qspi_frequency(&_qspi, _hz)) {
+ ret_status = QSPI_STATUS_ERROR;
+ }
+ } else {
+ _acquire();
+ }
+ unlock();
+ } else {
+ ret_status = QSPI_STATUS_ERROR;
+ }
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::read(int address, char *rx_buffer, size_t *rx_length)
+{
+ qspi_status_t ret_status = QSPI_STATUS_ERROR;
+
+ if (_initialized) {
+ if ((rx_length != NULL) && (rx_buffer != NULL)) {
+ if (*rx_length != 0) {
+ lock();
+ if (true == _acquire()) {
+ _build_qspi_command(-1, address, -1);
+ if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
+ ret_status = QSPI_STATUS_OK;
+ }
+ }
+ unlock();
+ }
+ } else {
+ ret_status = QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::write(int address, const char *tx_buffer, size_t *tx_length)
+{
+ qspi_status_t ret_status = QSPI_STATUS_ERROR;
+
+ if (_initialized) {
+ if ((tx_length != NULL) && (tx_buffer != NULL)) {
+ if (*tx_length != 0) {
+ lock();
+ if (true == _acquire()) {
+ _build_qspi_command(-1, address, -1);
+ if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
+ ret_status = QSPI_STATUS_OK;
+ }
+ }
+ unlock();
+ }
+ } else {
+ ret_status = QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length)
+{
+ qspi_status_t ret_status = QSPI_STATUS_ERROR;
+
+ if (_initialized) {
+ if ((rx_length != NULL) && (rx_buffer != NULL)) {
+ if (*rx_length != 0) {
+ lock();
+ if (true == _acquire()) {
+ _build_qspi_command(instruction, address, alt);
+ if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
+ ret_status = QSPI_STATUS_OK;
+ }
+ }
+ unlock();
+ }
+ } else {
+ ret_status = QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length)
+{
+ qspi_status_t ret_status = QSPI_STATUS_ERROR;
+
+ if (_initialized) {
+ if ((tx_length != NULL) && (tx_buffer != NULL)) {
+ if (*tx_length != 0) {
+ lock();
+ if (true == _acquire()) {
+ _build_qspi_command(instruction, address, alt);
+ if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
+ ret_status = QSPI_STATUS_OK;
+ }
+ }
+ unlock();
+ }
+ } else {
+ ret_status = QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ return ret_status;
+}
+
+qspi_status_t QSPI::command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
+{
+ qspi_status_t ret_status = QSPI_STATUS_ERROR;
+
+ if (_initialized) {
+ lock();
+ if (true == _acquire()) {
+ _build_qspi_command(instruction, address, -1); //We just need the command
+ if (QSPI_STATUS_OK == qspi_command_transfer(&_qspi, &_qspi_command, (const void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length)) {
+ ret_status = QSPI_STATUS_OK;
+ }
+ }
+ unlock();
+ }
+
+ return ret_status;
+}
+
+void QSPI::lock()
+{
+ _mutex->lock();
+}
+
+void QSPI::unlock()
+{
+ _mutex->unlock();
+}
+
+// Note: Private helper function to initialize qspi HAL
+bool QSPI::_initialize()
+{
+ if (_mode != 0 && _mode != 1) {
+ _initialized = false;
+ return _initialized;
+ }
+
+ qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
+ if (QSPI_STATUS_OK == ret) {
+ _initialized = true;
+ } else {
+ _initialized = false;
+ }
+
+ return _initialized;
+}
+
+// Note: Private function with no locking
+bool QSPI::_acquire()
+{
+ if (_owner != this) {
+ //This will set freq as well
+ _initialize();
+ _owner = this;
+ }
+
+ return _initialized;
+}
+
+void QSPI::_build_qspi_command(int instruction, int address, int alt)
+{
+ memset(&_qspi_command, 0, sizeof(qspi_command_t));
+ //Set up instruction phase parameters
+ _qspi_command.instruction.bus_width = _inst_width;
+ if (instruction != -1) {
+ _qspi_command.instruction.value = instruction;
+ _qspi_command.instruction.disabled = false;
+ } else {
+ _qspi_command.instruction.disabled = true;
+ }
+
+ //Set up address phase parameters
+ _qspi_command.address.bus_width = _address_width;
+ _qspi_command.address.size = _address_size;
+ if (address != -1) {
+ _qspi_command.address.value = address;
+ _qspi_command.address.disabled = false;
+ } else {
+ _qspi_command.address.disabled = true;
+ }
+
+ //Set up alt phase parameters
+ _qspi_command.alt.bus_width = _alt_width;
+ _qspi_command.alt.size = _alt_size;
+ if (alt != -1) {
+ _qspi_command.alt.value = alt;
+ _qspi_command.alt.disabled = false;
+ } else {
+ _qspi_command.alt.disabled = true;
+ }
+
+ _qspi_command.dummy_count = _num_dummy_cycles;
+
+ //Set up bus width for data phase
+ _qspi_command.data.bus_width = _data_width;
+}
+
+} // namespace mbed
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/QSPI.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,231 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_H
+#define MBED_QSPI_H
+
+#include "platform/platform.h"
+
+#if defined (DEVICE_QSPI) || defined(DOXYGEN_ONLY)
+
+#include "hal/qspi_api.h"
+#include "platform/PlatformMutex.h"
+#include "platform/SingletonPtr.h"
+#include "platform/NonCopyable.h"
+
+#define ONE_MHZ 1000000
+
+namespace mbed {
+
+/** \addtogroup drivers */
+
+/** A QSPI Driver, used for communicating with QSPI slave devices
+ *
+ * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
+ * Most QSPI devices will also require Chip Select which is indicated by ssel.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
+ *
+ * #include "mbed.h"
+ *
+ * #define CMD_WRITE 0x02
+ * #define CMD_READ 0x03
+ * #define ADDRESS 0x1000
+ *
+ * // hardware ssel (where applicable)
+ * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
+ *
+ *
+ * int main() {
+ * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
+ * char rx_buf[4];
+ * int buf_len = sizeof(tx_buf);
+ *
+ * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
+ * if (result != QSPI_STATUS_OK) {
+ * printf("Write failed");
+ * }
+ * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
+ * if (result != QSPI_STATUS_OK) {
+ * printf("Read failed");
+ * }
+ *
+ * }
+ * @endcode
+ * @ingroup drivers
+ */
+class QSPI : private NonCopyable<QSPI> {
+
+public:
+
+ /** Create a QSPI master connected to the specified pins
+ *
+ * io0-io3 is used to specify the Pins used for Quad SPI mode
+ *
+ * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
+ * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
+ * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
+ * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
+ * @param sclk QSPI Clock pin
+ * @param ssel QSPI chip select pin
+ * @param mode Clock polarity and phase mode (0 - 3) of SPI
+ * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
+ *
+ */
+ QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
+ virtual ~QSPI()
+ {
+ }
+
+ /** Configure the data transmission format
+ *
+ * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
+ * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
+ * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
+ * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
+ * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
+ * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
+ * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
+ *
+ */
+ qspi_status_t configure_format(qspi_bus_width_t inst_width,
+ qspi_bus_width_t address_width,
+ qspi_address_size_t address_size,
+ qspi_bus_width_t alt_width,
+ qspi_alt_size_t alt_size,
+ qspi_bus_width_t data_width,
+ int dummy_cycles);
+
+ /** Set the qspi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
+ */
+ qspi_status_t set_frequency(int hz = ONE_MHZ);
+
+ /** Read from QSPI peripheral with the preset read_instruction and alt_value
+ *
+ * @param address Address to be accessed in QSPI peripheral
+ * @param rx_buffer Buffer for data to be read from the peripheral
+ * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
+ *
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
+ */
+ qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
+
+ /** Write to QSPI peripheral using custom write instruction
+ *
+ * @param address Address to be accessed in QSPI peripheral
+ * @param tx_buffer Buffer containing data to be sent to peripheral
+ * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
+ *
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
+ */
+ qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
+
+ /** Read from QSPI peripheral using custom read instruction, alt values
+ *
+ * @param instruction Instruction value to be used in instruction phase
+ * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
+ * @param address Address to be accessed in QSPI peripheral
+ * @param rx_buffer Buffer for data to be read from the peripheral
+ * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
+ *
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
+ */
+ qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
+
+ /** Write to QSPI peripheral using custom write instruction, alt values
+ *
+ * @param instruction Instruction value to be used in instruction phase
+ * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
+ * @param address Address to be accessed in QSPI peripheral
+ * @param tx_buffer Buffer containing data to be sent to peripheral
+ * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
+ *
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
+ */
+ qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
+
+ /** Perform a transaction to write to an address(a control register) and get the status results
+ *
+ * @param instruction Instruction value to be used in instruction phase
+ * @param address Some instruction might require address. Use -1 if no address
+ * @param tx_buffer Buffer containing data to be sent to peripheral
+ * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
+ * @param rx_buffer Buffer for data to be read from the peripheral
+ * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
+ *
+ * @returns
+ * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
+ */
+ qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
+
+#if !defined(DOXYGEN_ONLY)
+protected:
+ /** Acquire exclusive access to this SPI bus
+ */
+ virtual void lock(void);
+
+ /** Release exclusive access to this SPI bus
+ */
+ virtual void unlock(void);
+
+ qspi_t _qspi;
+
+ bool acquire(void);
+ static QSPI *_owner;
+ static SingletonPtr<PlatformMutex> _mutex;
+ qspi_bus_width_t _inst_width; //Bus width for Instruction phase
+ qspi_bus_width_t _address_width; //Bus width for Address phase
+ qspi_address_size_t _address_size;
+ qspi_bus_width_t _alt_width; //Bus width for Alt phase
+ qspi_alt_size_t _alt_size;
+ qspi_bus_width_t _data_width; //Bus width for Data phase
+ qspi_command_t _qspi_command; //QSPI Hal command struct
+ unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
+ int _hz; //Bus Frequency
+ int _mode; //SPI mode
+ bool _initialized;
+ PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
+
+private:
+ /* Private acquire function without locking/unlocking
+ * Implemented in order to avoid duplicate locking and boost performance
+ */
+ bool _acquire(void);
+ bool _initialize();
+
+ /*
+ * This function builds the qspi command struct to be send to Hal
+ */
+ inline void _build_qspi_command(int instruction, int address, int alt);
+#endif
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
--- a/drivers/RawSerial.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/RawSerial.h Thu Nov 08 11:46:34 2018 +0000
@@ -88,6 +88,7 @@
int printf(const char *format, ...);
+#if !(DOXYGEN_ONLY)
protected:
/* Acquire exclusive access to this serial port
@@ -97,6 +98,7 @@
/* Release exclusive access to this serial port
*/
virtual void unlock(void);
+#endif
};
} // namespace mbed
--- a/drivers/SPI.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/SPI.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -41,9 +41,14 @@
_write_fill(SPI_FILL_CHAR)
{
// No lock needed in the constructor
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+}
- spi_init(&_spi, mosi, miso, sclk, ssel);
- _acquire();
+SPI::~SPI()
+{
+ if (_owner == this) {
+ _owner = NULL;
+ }
}
void SPI::format(int bits, int mode)
--- a/drivers/SPI.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/SPI.h Thu Nov 08 11:46:34 2018 +0000
@@ -36,39 +36,44 @@
namespace mbed {
/** \addtogroup drivers */
-/** A SPI Master, used for communicating with SPI slave devices
+/** A SPI Master, used for communicating with SPI slave devices.
*
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz.
*
* Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using DigitalOut pins
+ * can be controlled using DigitalOut pins.
*
* @note Synchronization level: Thread safe
*
- * Example:
+ * Example of how to send a byte to a SPI slave and record the response:
* @code
- * // Send a byte to a SPI slave, and record the response
- *
* #include "mbed.h"
*
- * // hardware ssel (where applicable)
- * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ * SPI device(SPI_MOSI, SPI_MISO, SPI_SCLK)
*
- * // software ssel
- * SPI device(p5, p6, p7); // mosi, miso, sclk
- * DigitalOut cs(p8); // ssel
+ * DigitalOut chip_select(SPI_CS);
*
* int main() {
- * // hardware ssel (where applicable)
- * //int response = device.write(0xFF);
- *
* device.lock();
- * // software ssel
- * cs = 0;
+ * chip_select = 0;
+ *
* int response = device.write(0xFF);
- * cs = 1;
+ *
+ * chip_select = 1;
* device.unlock();
+ * }
+ * @endcode
*
+ * Example using hardware Chip Select line:
+ * @code
+ * #include "mbed.h"
+ *
+ * SPI device(SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS)
+ *
+ * int main() {
+ * device.lock();
+ * int response = device.write(0xFF);
+ * device.unlock();
* }
* @endcode
* @ingroup drivers
@@ -77,21 +82,22 @@
public:
- /** Create a SPI master connected to the specified pins
+ /** Create a SPI master connected to the specified pins.
*
- * mosi or miso can be specified as NC if not used
+ * @note You can specify mosi or miso as NC if not used.
*
- * @param mosi SPI Master Out, Slave In pin
- * @param miso SPI Master In, Slave Out pin
- * @param sclk SPI Clock pin
- * @param ssel SPI chip select pin
+ * @param mosi SPI Master Out, Slave In pin.
+ * @param miso SPI Master In, Slave Out pin.
+ * @param sclk SPI Clock pin.
+ * @param ssel SPI Chip Select pin.
*/
SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel = NC);
+ virtual ~SPI();
- /** Configure the data transmission format
+ /** Configure the data transmission format.
*
- * @param bits Number of bits per SPI frame (4 - 16)
- * @param mode Clock polarity and phase mode (0 - 3)
+ * @param bits Number of bits per SPI frame (4 - 16).
+ * @param mode Clock polarity and phase mode (0 - 3).
*
* @code
* mode | POL PHA
@@ -104,51 +110,50 @@
*/
void format(int bits, int mode = 0);
- /** Set the spi bus clock frequency
+ /** Set the SPI bus clock frequency.
*
- * @param hz SCLK frequency in hz (default = 1MHz)
+ * @param hz Clock frequency in Hz (default = 1MHz).
*/
void frequency(int hz = 1000000);
- /** Write to the SPI Slave and return the response
+ /** Write to the SPI Slave and return the response.
*
- * @param value Data to be sent to the SPI slave
+ * @param value Data to be sent to the SPI slave.
*
- * @returns
- * Response from the SPI slave
+ * @return Response from the SPI slave.
*/
virtual int write(int value);
- /** Write to the SPI Slave and obtain the response
+ /** Write to the SPI Slave and obtain the response.
*
* The total number of bytes sent and received will be the maximum of
* tx_length and rx_length. The bytes written will be padded with the
* value 0xff.
*
- * @param tx_buffer Pointer to the byte-array of data to write to the device
- * @param tx_length Number of bytes to write, may be zero
- * @param rx_buffer Pointer to the byte-array of data to read from the device
- * @param rx_length Number of bytes to read, may be zero
- * @returns
+ * @param tx_buffer Pointer to the byte-array of data to write to the device.
+ * @param tx_length Number of bytes to write, may be zero.
+ * @param rx_buffer Pointer to the byte-array of data to read from the device.
+ * @param rx_length Number of bytes to read, may be zero.
+ * @return
* The number of bytes written and read from the device. This is
* maximum of tx_length and rx_length.
*/
virtual int write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
- /** Acquire exclusive access to this SPI bus
+ /** Acquire exclusive access to this SPI bus.
*/
virtual void lock(void);
- /** Release exclusive access to this SPI bus
+ /** Release exclusive access to this SPI bus.
*/
virtual void unlock(void);
- /** Set default write data
+ /** Set default write data.
* SPI requires the master to send some data during a read operation.
* Different devices may require different default byte values.
* For example: A SD Card requires default bytes to be 0xFF.
*
- * @param data Default character to be transmitted while read operation
+ * @param data Default character to be transmitted during a read operation.
*/
void set_default_write_value(char data);
@@ -156,17 +161,20 @@
/** Start non-blocking SPI transfer using 8bit buffers.
*
- * This function locks the deep sleep until any event has occurred
+ * This function locks the deep sleep until any event has occurred.
*
- * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
- * the default SPI value is sent
- * @param tx_length The length of TX buffer in bytes
+ * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
+ * the default SPI value is sent.
+ * @param tx_length The length of TX buffer in bytes.
* @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored
- * @param rx_length The length of RX buffer in bytes
- * @param callback The event callback function
- * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
- * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+ * received data are ignored.
+ * @param rx_length The length of RX buffer in bytes.
+ * @param callback The event callback function.
+ * @param event The event mask of events to modify. @see spi_api.h for SPI events.
+ *
+ * @return Operation result.
+ * @retval 0 If the transfer has started.
+ * @retval -1 If SPI peripheral is busy.
*/
template<typename Type>
int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t &callback, int event = SPI_EVENT_COMPLETE)
@@ -178,75 +186,85 @@
return 0;
}
- /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+ /** Abort the on-going SPI transfer, and continue with transfers in the queue, if any.
*/
void abort_transfer();
- /** Clear the transaction buffer
+ /** Clear the queue of transfers.
*/
void clear_transfer_buffer();
- /** Clear the transaction buffer and abort on-going transfer.
+ /** Clear the queue of transfers and abort the on-going transfer.
*/
void abort_all_transfers();
- /** Configure DMA usage suggestion for non-blocking transfers
+ /** Configure DMA usage suggestion for non-blocking transfers.
+ *
+ * @param usage The usage DMA hint for peripheral.
*
- * @param usage The usage DMA hint for peripheral
- * @return Zero if the usage was set, -1 if a transaction is on-going
- */
+ * @return Result of the operation.
+ * @retval 0 The usage was set.
+ * @retval -1 Usage cannot be set as there is an ongoing transaction.
+ */
int set_dma_usage(DMAUsage usage);
protected:
- /** SPI IRQ handler
- *
- */
+ /** SPI interrupt handler.
+ */
void irq_handler_asynch(void);
- /** Common transfer method
+ /** Start the transfer or put it on the queue.
*
- * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+ * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
* the default SPI value is sent
- * @param tx_length The length of TX buffer in bytes
+ * @param tx_length The length of TX buffer in bytes.
* @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored
- * @param rx_length The length of RX buffer in bytes
- * @param bit_width The buffers element width
- * @param callback The event callback function
- * @param event The logical OR of events to modify
- * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
- */
+ * received data are ignored.
+ * @param rx_length The length of RX buffer in bytes.
+ * @param bit_width The buffers element width in bits.
+ * @param callback The event callback function.
+ * @param event The event mask of events to modify.
+ *
+ * @return Operation success.
+ * @retval 0 A transfer was started or added to the queue.
+ * @retval -1 Transfer can't be added because queue is full.
+ */
int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
- /**
+ /** Put a transfer on the transfer queue.
*
- * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
- * the default SPI value is sent
- * @param tx_length The length of TX buffer in bytes
+ * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
+ * the default SPI value is sent.
+ * @param tx_length The length of TX buffer in bytes.
* @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored
- * @param rx_length The length of RX buffer in bytes
- * @param bit_width The buffers element width
- * @param callback The event callback function
- * @param event The logical OR of events to modify
- * @return Zero if a transfer was added to the queue, or -1 if the queue is full
- */
+ * received data are ignored.
+ * @param rx_length The length of RX buffer in bytes.
+ * @param bit_width The buffers element width in bits.
+ * @param callback The event callback function.
+ * @param event The event mask of events to modify.
+ *
+ * @return Operation success.
+ * @retval 0 A transfer was added to the queue.
+ * @retval -1 Transfer can't be added because queue is full.
+ */
int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
- /** Configures a callback, spi peripheral and initiate a new transfer
+ /** Configure a callback, SPI peripheral, and initiate a new transfer.
*
- * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
- * the default SPI value is sent
- * @param tx_length The length of TX buffer in bytes
+ * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
+ * the default SPI value is sent.
+ * @param tx_length The length of TX buffer in bytes.
* @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored
- * @param rx_length The length of RX buffer in bytes
- * @param bit_width The buffers element width
- * @param callback The event callback function
- * @param event The logical OR of events to modify
- */
+ * received data are ignored.
+ * @param rx_length The length of RX buffer in bytes.
+ * @param bit_width The buffers element width.
+ * @param callback The event callback function.
+ * @param event The event mask of events to modify.
+ */
void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
+#if !defined(DOXYGEN_ONLY)
+
private:
/** Lock deep sleep only if it is not yet locked */
void lock_deep_sleep();
@@ -257,49 +275,63 @@
#if TRANSACTION_QUEUE_SIZE_SPI
- /** Start a new transaction
+ /** Start a new transaction.
*
- * @param data Transaction data
- */
+ * @param data Transaction data.
+ */
void start_transaction(transaction_t *data);
- /** Dequeue a transaction
- *
- */
+ /** Dequeue a transaction and start the transfer if there was one pending.
+ */
void dequeue_transaction();
+
+ /* Queue of pending transfers */
static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
#endif
-#endif
+#endif //!defined(DOXYGEN_ONLY)
-public:
- virtual ~SPI()
- {
- }
+#endif //DEVICE_SPI_ASYNCH
+
+#if !defined(DOXYGEN_ONLY)
protected:
+ /* Internal SPI object identifying the resources */
spi_t _spi;
#if DEVICE_SPI_ASYNCH
+ /* Interrupt */
CThunk<SPI> _irq;
+ /* Interrupt handler callback */
event_callback_t _callback;
+ /* Current preferred DMA mode @see dma_api.h */
DMAUsage _usage;
+ /* Current sate of the sleep manager */
bool _deep_sleep_locked;
#endif
+ /* Take over the physical SPI and apply our settings (thread safe) */
void aquire(void);
+ /* Current user of the SPI */
static SPI *_owner;
+ /* Used by lock and unlock for thread safety */
static SingletonPtr<PlatformMutex> _mutex;
+ /* Size of the SPI frame */
int _bits;
+ /* Clock polairy and phase */
int _mode;
+ /* Clock frequency */
int _hz;
+ /* Default character used for NULL transfers */
char _write_fill;
private:
- /* Private acquire function without locking/unlocking
- * Implemented in order to avoid duplicate locking and boost performance
+ /** Private acquire function without locking/unlocking.
+ * Implemented in order to avoid duplicate locking and boost performance.
*/
void _acquire(void);
+
+#endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/SPISlave.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/SPISlave.h Thu Nov 08 11:46:34 2018 +0000
@@ -26,19 +26,18 @@
namespace mbed {
/** \addtogroup drivers */
-/** A SPI slave, used for communicating with a SPI Master device
+/** A SPI slave, used for communicating with a SPI master device.
*
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ * The default format is set to 8 bits, mode 0 and a clock frequency of 1MHz.
*
* @note Synchronization level: Not protected
*
- * Example:
+ * Example of how to reply to a SPI master as slave:
* @code
- * // Reply to a SPI master as slave
*
* #include "mbed.h"
*
- * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ * SPISlave device(SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS);
*
* int main() {
* device.reply(0x00); // Prime SPI with first reply
@@ -57,21 +56,21 @@
public:
- /** Create a SPI slave connected to the specified pins
+ /** Create a SPI slave connected to the specified pins.
*
- * mosi or miso can be specified as NC if not used
+ * @note Either mosi or miso can be specified as NC if not used.
*
- * @param mosi SPI Master Out, Slave In pin
- * @param miso SPI Master In, Slave Out pin
- * @param sclk SPI Clock pin
- * @param ssel SPI chip select pin
+ * @param mosi SPI Master Out, Slave In pin.
+ * @param miso SPI Master In, Slave Out pin.
+ * @param sclk SPI Clock pin.
+ * @param ssel SPI Chip Select pin.
*/
SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
- /** Configure the data transmission format
+ /** Configure the data transmission format.
*
- * @param bits Number of bits per SPI frame (4 - 16)
- * @param mode Clock polarity and phase mode (0 - 3)
+ * @param bits Number of bits per SPI frame (4 - 16).
+ * @param mode Clock polarity and phase mode (0 - 3).
*
* @code
* mode | POL PHA
@@ -84,40 +83,47 @@
*/
void format(int bits, int mode = 0);
- /** Set the spi bus clock frequency
+ /** Set the SPI bus clock frequency.
*
- * @param hz SCLK frequency in hz (default = 1MHz)
+ * @param hz Clock frequency in hz (default = 1MHz).
*/
void frequency(int hz = 1000000);
- /** Polls the SPI to see if data has been received
+ /** Polls the SPI to see if data has been received.
*
- * @returns
- * 0 if no data,
- * 1 otherwise
+ * @return Presence of received data.
+ * @retval 0 No data waiting.
+ * @retval 1 Data waiting.
*/
int receive(void);
- /** Retrieve data from receive buffer as slave
+ /** Retrieve data from receive buffer as slave.
*
- * @returns
- * the data in the receive buffer
+ * @return The data in the receive buffer.
*/
int read(void);
/** Fill the transmission buffer with the value to be written out
* as slave on the next received message from the master.
*
- * @param value the data to be transmitted next
+ * @param value The data to be transmitted next.
*/
void reply(int value);
+#if !defined(DOXYGEN_ONLY)
+
protected:
+ /* Internal SPI object identifying the resources */
spi_t _spi;
+ /* How many bits in an SPI frame */
int _bits;
+ /* Clock phase and polarity */
int _mode;
+ /* Clock frequency */
int _hz;
+
+#endif //!defined(DOXYGEN_ONLY)
};
} // namespace mbed
--- a/drivers/Serial.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/Serial.h Thu Nov 08 11:46:34 2018 +0000
@@ -20,10 +20,10 @@
#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
-#include "Stream.h"
+#include "platform/Stream.h"
#include "SerialBase.h"
-#include "PlatformMutex.h"
-#include "serial_api.h"
+#include "platform/PlatformMutex.h"
+#include "hal/serial_api.h"
#include "platform/NonCopyable.h"
namespace mbed {
@@ -63,10 +63,10 @@
* @param tx Transmit pin
* @param rx Receive pin
* @param name The name of the stream associated with this serial port (optional)
- * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
+ * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE or 9600)
*
* @note
- * Either tx or rx may be specified as NC if unused
+ * Either tx or rx may be specified as NC (Not Connected) if unused
*/
Serial(PinName tx, PinName rx, const char *name = NULL, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
@@ -78,7 +78,7 @@
* @param baud The baud rate of the serial port
*
* @note
- * Either tx or rx may be specified as NC if unused
+ * Either tx or rx may be specified as NC (Not Connected) if unused
*/
Serial(PinName tx, PinName rx, int baud);
@@ -99,6 +99,7 @@
return SerialBase::writeable();
}
+#if !(DOXYGEN_ONLY)
protected:
virtual int _getc();
virtual int _putc(int c);
@@ -106,6 +107,7 @@
virtual void unlock();
PlatformMutex _mutex;
+#endif
};
} // namespace mbed
--- a/drivers/SerialBase.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/SerialBase.h Thu Nov 08 11:46:34 2018 +0000
@@ -20,14 +20,14 @@
#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY)
-#include "Callback.h"
-#include "serial_api.h"
-#include "mbed_toolchain.h"
+#include "platform/Callback.h"
+#include "hal/serial_api.h"
+#include "platform/mbed_toolchain.h"
#include "platform/NonCopyable.h"
#if DEVICE_SERIAL_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
+#include "platform/CThunk.h"
+#include "hal/dma_api.h"
#endif
namespace mbed {
@@ -97,7 +97,7 @@
/** Attach a function to call whenever a serial interrupt is generated
*
* @param func A pointer to a void function, or 0 to set as none
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
*/
void attach(Callback<void()> func, IrqType type = RxIrq);
@@ -105,7 +105,7 @@
*
* @param obj pointer to the object to call the member function on
* @param method pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
* @deprecated
* The attach function does not support cv-qualifiers. Replaced by
* attach(callback(obj, method), type).
@@ -123,7 +123,7 @@
*
* @param obj pointer to the object to call the member function on
* @param method pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
* @deprecated
* The attach function does not support cv-qualifiers. Replaced by
* attach(callback(obj, method), type).
@@ -167,7 +167,7 @@
#if DEVICE_SERIAL_ASYNCH
- /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+ /** Begin asynchronous write using 8bit buffer. The completion invokes registered TX event callback
*
* This function locks the deep sleep until any event has occurred
*
@@ -178,7 +178,7 @@
*/
int write(const uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_TX_COMPLETE);
- /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+ /** Begin asynchronous write using 16bit buffer. The completion invokes registered TX event callback
*
* This function locks the deep sleep until any event has occurred
*
@@ -193,7 +193,7 @@
*/
void abort_write();
- /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+ /** Begin asynchronous reading using 8bit buffer. The completion invokes registered RX event callback.
*
* This function locks the deep sleep until any event has occurred
*
@@ -205,7 +205,7 @@
*/
int read(uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
- /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+ /** Begin asynchronous reading using 16bit buffer. The completion invokes registered RX event callback.
*
* This function locks the deep sleep until any event has occurred
*
--- a/drivers/SerialWireOutput.h Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/SerialWireOutput.h Thu Nov 08 11:46:34 2018 +0000 @@ -14,6 +14,9 @@ * limitations under the License. */ +#ifndef MBED_SERIALWIREOUTPUT_H +#define MBED_SERIALWIREOUTPUT_H + #if defined(DEVICE_ITM) #include "hal/itm_api.h" @@ -70,4 +73,6 @@ } // namespace mbed -#endif +#endif // DEVICE_ITM + +#endif // MBED_SERIALWIREOUTPUT_H
--- a/drivers/TableCRC.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/TableCRC.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -143,5 +143,13 @@
0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
};
+extern const uint32_t Table_CRC_32bit_Rev_ANSI[MBED_OPTIMIZED_CRC_TABLE_SIZE] = {
+ 0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac,
+ 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,
+ 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c,
+ 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c
+};
+
+
/** @}*/
} // namespace mbed
--- a/drivers/TableCRC.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/TableCRC.h Thu Nov 08 11:46:34 2018 +0000
@@ -23,13 +23,15 @@
/** \addtogroup drivers */
/** @{*/
-#define MBED_CRC_TABLE_SIZE 256
+#define MBED_CRC_TABLE_SIZE 256
+#define MBED_OPTIMIZED_CRC_TABLE_SIZE 16
extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE];
extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE];
extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE];
extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE];
extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE];
+extern const uint32_t Table_CRC_32bit_Rev_ANSI[MBED_OPTIMIZED_CRC_TABLE_SIZE];
/** @}*/
} // namespace mbed
--- a/drivers/Ticker.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/Ticker.h Thu Nov 08 11:46:34 2018 +0000
@@ -35,7 +35,7 @@
*
* Example:
* @code
- * // Toggle the blinking led after 5 seconds
+ * // Toggle the blinking LED after 5 seconds
*
* #include "mbed.h"
*
@@ -70,7 +70,7 @@
{
}
- // When low power ticker is in use, then do not disable deep-sleep.
+ // When low power ticker is in use, then do not disable deep sleep.
Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)
{
#if DEVICE_LPTICKER
@@ -106,13 +106,13 @@
attach(callback(obj, method), t);
}
- /** Attach a function to be called by the Ticker, specifying the interval in micro-seconds
+ /** Attach a function to be called by the Ticker, specifying the interval in microseconds
*
* @param func pointer to the function to be called
* @param t the time between calls in micro-seconds
*
- * @note setting @a t to a value shorter that it takes to process the ticker callback
- * will cause the system to hang. Ticker callback will be called constantly with no time
+ * @note setting @a t to a value shorter than it takes to process the ticker callback
+ * causes the system to hang. Ticker callback is called constantly with no time
* for threads scheduling.
*
*/
@@ -128,11 +128,11 @@
core_util_critical_section_exit();
}
- /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds
+ /** Attach a member function to be called by the Ticker, specifying the interval in microseconds
*
* @param obj pointer to the object to call the member function on
* @param method pointer to the member function to be called
- * @param t the time between calls in micro-seconds
+ * @param t the time between calls in microseconds
* @deprecated
* The attach_us function does not support cv-qualifiers. Replaced by
* attach_us(callback(obj, method), t).
@@ -155,14 +155,16 @@
*/
void detach();
+#if !defined(DOXYGEN_ONLY)
protected:
void setup(us_timestamp_t t);
virtual void handler();
protected:
- us_timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ us_timestamp_t _delay; /**< Time delay (in microseconds) for resetting the multishot callback. */
Callback<void()> _function; /**< Callback. */
- bool _lock_deepsleep; /**< Flag which indicates if deep-sleep should be disabled. */
+ bool _lock_deepsleep; /**< Flag which indicates if deep sleep should be disabled. */
+#endif
};
} // namespace mbed
--- a/drivers/Timeout.h Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/Timeout.h Thu Nov 08 11:46:34 2018 +0000 @@ -25,7 +25,7 @@ /** A Timeout is used to call a function at a point in the future * - * You can use as many seperate Timeout objects as you require. + * You can use as many separate Timeout objects as you require. * * @note Synchronization level: Interrupt safe *
--- a/drivers/Timer.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/Timer.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -79,7 +79,7 @@
float Timer::read()
{
- return (float)read_us() / 1000000.0f;
+ return (float)read_high_resolution_us() / 1000000.0f;
}
int Timer::read_ms()
--- a/drivers/Timer.h Thu Sep 06 13:40:20 2018 +0100
+++ b/drivers/Timer.h Thu Nov 08 11:46:34 2018 +0000
@@ -30,7 +30,7 @@
*
* Example:
* @code
- * // Count the time to toggle a LED
+ * // Count the time to toggle an LED
*
* #include "mbed.h"
*
@@ -65,7 +65,7 @@
/** Reset the timer to 0.
*
- * If it was already counting, it will continue
+ * If it was already running, it will continue
*/
void reset();
@@ -75,15 +75,15 @@
*/
float read();
- /** Get the time passed in milli-seconds
+ /** Get the time passed in milliseconds
*
- * @returns Time passed in milli seconds
+ * @returns Time passed in milliseconds
*/
int read_ms();
- /** Get the time passed in micro-seconds
+ /** Get the time passed in microseconds
*
- * @returns Time passed in micro seconds
+ * @returns Time passed in microseconds
*/
int read_us();
@@ -91,18 +91,21 @@
*/
operator float();
- /** Get in a high resolution type the time passed in micro-seconds.
+ /** Get in a high resolution type the time passed in microseconds.
+ * Returns a 64 bit integer.
*/
us_timestamp_t read_high_resolution_us();
+#if !defined(DOXYGEN_ONLY)
protected:
us_timestamp_t slicetime();
int _running; // whether the timer is running
us_timestamp_t _start; // the start time of the latest slice
us_timestamp_t _time; // any accumulated time from previous slices
const ticker_data_t *_ticker_data;
- bool _lock_deepsleep; // flag which indicates if deep-sleep should be disabled
+ bool _lock_deepsleep; // flag that indicates if deep sleep should be disabled
};
+#endif
} // namespace mbed
--- a/drivers/TimerEvent.cpp Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/TimerEvent.cpp Thu Nov 08 11:46:34 2018 +0000 @@ -14,7 +14,6 @@ * limitations under the License. */ #include "drivers/TimerEvent.h" -#include "cmsis.h" #include <stddef.h> #include "hal/ticker_api.h"
--- a/drivers/UARTSerial.cpp Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/UARTSerial.cpp Thu Nov 08 11:46:34 2018 +0000 @@ -13,11 +13,10 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +#include "drivers/UARTSerial.h" #if (DEVICE_SERIAL && DEVICE_INTERRUPTIN) -#include <errno.h> -#include "UARTSerial.h" #include "platform/mbed_poll.h" #if MBED_CONF_RTOS_PRESENT
--- a/drivers/UARTSerial.h Thu Sep 06 13:40:20 2018 +0100 +++ b/drivers/UARTSerial.h Thu Nov 08 11:46:34 2018 +0000 @@ -21,12 +21,12 @@ #if (DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY) -#include "FileHandle.h" +#include "platform/FileHandle.h" #include "SerialBase.h" #include "InterruptIn.h" -#include "PlatformMutex.h" -#include "serial_api.h" -#include "CircularBuffer.h" +#include "platform/PlatformMutex.h" +#include "hal/serial_api.h" +#include "platform/CircularBuffer.h" #include "platform/NonCopyable.h" #ifndef MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/LowPowerTickerWrapper.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,310 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal/LowPowerTickerWrapper.h"
+#include "platform/Callback.h"
+
+LowPowerTickerWrapper::LowPowerTickerWrapper(const ticker_data_t *data, const ticker_interface_t *interface, uint32_t min_cycles_between_writes, uint32_t min_cycles_until_match)
+ : _intf(data->interface), _min_count_between_writes(min_cycles_between_writes + 1), _min_count_until_match(min_cycles_until_match + 1), _suspended(false)
+{
+ core_util_critical_section_enter();
+
+ this->data.interface = interface;
+ this->data.queue = data->queue;
+ _reset();
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::irq_handler(ticker_irq_handler_type handler)
+{
+ core_util_critical_section_enter();
+
+ if (_pending_fire_now || _match_check(_intf->read()) || _suspended) {
+ _timeout.detach();
+ _pending_timeout = false;
+ _pending_match = false;
+ _pending_fire_now = false;
+ if (handler) {
+ handler(&data);
+ }
+ } else {
+ // Spurious interrupt
+ _intf->clear_interrupt();
+ }
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::suspend()
+{
+ core_util_critical_section_enter();
+
+ // Wait until rescheduling is allowed
+ while (!_set_interrupt_allowed) {
+ timestamp_t current = _intf->read();
+ if (((current - _last_actual_set_interrupt) & _mask) >= _min_count_between_writes) {
+ _set_interrupt_allowed = true;
+ }
+ }
+
+ _reset();
+ _suspended = true;
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::resume()
+{
+ core_util_critical_section_enter();
+
+ // Wait until rescheduling is allowed
+ while (!_set_interrupt_allowed) {
+ timestamp_t current = _intf->read();
+ if (((current - _last_actual_set_interrupt) & _mask) >= _min_count_between_writes) {
+ _set_interrupt_allowed = true;
+ }
+ }
+
+ _suspended = false;
+
+ core_util_critical_section_exit();
+}
+
+bool LowPowerTickerWrapper::timeout_pending()
+{
+ core_util_critical_section_enter();
+
+ bool pending = _pending_timeout;
+
+ core_util_critical_section_exit();
+ return pending;
+}
+
+void LowPowerTickerWrapper::init()
+{
+ core_util_critical_section_enter();
+
+ _reset();
+ _intf->init();
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::free()
+{
+ core_util_critical_section_enter();
+
+ _reset();
+ _intf->free();
+
+ core_util_critical_section_exit();
+}
+
+uint32_t LowPowerTickerWrapper::read()
+{
+ core_util_critical_section_enter();
+
+ timestamp_t current = _intf->read();
+ if (!_suspended && _match_check(current)) {
+ _intf->fire_interrupt();
+ }
+
+ core_util_critical_section_exit();
+ return current;
+}
+
+void LowPowerTickerWrapper::set_interrupt(timestamp_t timestamp)
+{
+ core_util_critical_section_enter();
+
+ _last_set_interrupt = _intf->read();
+ _cur_match_time = timestamp;
+ _pending_match = true;
+ if (!_suspended) {
+ _schedule_match(_last_set_interrupt);
+ } else {
+ _intf->set_interrupt(timestamp);
+ _last_actual_set_interrupt = _last_set_interrupt;
+ _set_interrupt_allowed = false;
+ }
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::disable_interrupt()
+{
+ core_util_critical_section_enter();
+
+ _intf->disable_interrupt();
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::clear_interrupt()
+{
+ core_util_critical_section_enter();
+
+ _intf->clear_interrupt();
+
+ core_util_critical_section_exit();
+}
+
+void LowPowerTickerWrapper::fire_interrupt()
+{
+ core_util_critical_section_enter();
+
+ _pending_fire_now = 1;
+ _intf->fire_interrupt();
+
+ core_util_critical_section_exit();
+}
+
+const ticker_info_t *LowPowerTickerWrapper::get_info()
+{
+
+ core_util_critical_section_enter();
+
+ const ticker_info_t *info = _intf->get_info();
+
+ core_util_critical_section_exit();
+ return info;
+}
+
+void LowPowerTickerWrapper::_reset()
+{
+ MBED_ASSERT(core_util_in_critical_section());
+
+ _timeout.detach();
+ _pending_timeout = false;
+ _pending_match = false;
+ _pending_fire_now = false;
+ _set_interrupt_allowed = true;
+ _cur_match_time = 0;
+ _last_set_interrupt = 0;
+ _last_actual_set_interrupt = 0;
+
+ const ticker_info_t *info = _intf->get_info();
+ if (info->bits >= 32) {
+ _mask = 0xffffffff;
+ } else {
+ _mask = ((uint64_t)1 << info->bits) - 1;
+ }
+
+ // Round us_per_tick up
+ _us_per_tick = (1000000 + info->frequency - 1) / info->frequency;
+}
+
+void LowPowerTickerWrapper::_timeout_handler()
+{
+ core_util_critical_section_enter();
+ _pending_timeout = false;
+
+ timestamp_t current = _intf->read();
+ /* Add extra check for '_last_set_interrupt == _cur_match_time'
+ *
+ * When '_last_set_interrupt == _cur_match_time', _ticker_match_interval_passed sees it as
+ * one-round interval rather than just-pass, so add extra check for it. In rare cases, we
+ * may trap in _timeout_handler/_schedule_match loop. This check can break it.
+ */
+ if ((_last_set_interrupt == _cur_match_time) ||
+ _ticker_match_interval_passed(_last_set_interrupt, current, _cur_match_time)) {
+ _intf->fire_interrupt();
+ } else {
+ _schedule_match(current);
+ }
+
+ core_util_critical_section_exit();
+}
+
+bool LowPowerTickerWrapper::_match_check(timestamp_t current)
+{
+ MBED_ASSERT(core_util_in_critical_section());
+
+ if (!_pending_match) {
+ return false;
+ }
+ /* Add extra check for '_last_set_interrupt == _cur_match_time' as above */
+ return (_last_set_interrupt == _cur_match_time) ||
+ _ticker_match_interval_passed(_last_set_interrupt, current, _cur_match_time);
+}
+
+uint32_t LowPowerTickerWrapper::_lp_ticks_to_us(uint32_t ticks)
+{
+ MBED_ASSERT(core_util_in_critical_section());
+
+ // Add 4 microseconds to round up the micro second ticker time (which has a frequency of at least 250KHz - 4us period)
+ return _us_per_tick * ticks + 4;
+}
+
+void LowPowerTickerWrapper::_schedule_match(timestamp_t current)
+{
+ MBED_ASSERT(core_util_in_critical_section());
+
+ // Check if _intf->set_interrupt is allowed
+ if (!_set_interrupt_allowed) {
+ if (((current - _last_actual_set_interrupt) & _mask) >= _min_count_between_writes) {
+ _set_interrupt_allowed = true;
+ }
+ }
+
+ uint32_t cycles_until_match = (_cur_match_time - current) & _mask;
+ bool too_close = cycles_until_match < _min_count_until_match;
+
+ if (!_set_interrupt_allowed) {
+
+ // Can't use _intf->set_interrupt so use microsecond Timeout instead
+
+ // Speed optimization - if a timer has already been scheduled
+ // then don't schedule it again.
+ if (!_pending_timeout) {
+ uint32_t ticks = cycles_until_match < _min_count_until_match ? cycles_until_match : _min_count_until_match;
+ _timeout.attach_us(mbed::callback(this, &LowPowerTickerWrapper::_timeout_handler), _lp_ticks_to_us(ticks));
+ _pending_timeout = true;
+ }
+ return;
+ }
+
+ if (!too_close) {
+
+ // Schedule LP ticker
+ _intf->set_interrupt(_cur_match_time);
+ current = _intf->read();
+ _last_actual_set_interrupt = current;
+ _set_interrupt_allowed = false;
+
+ // Check for overflow
+ uint32_t new_cycles_until_match = (_cur_match_time - current) & _mask;
+ if (new_cycles_until_match > cycles_until_match) {
+ // Overflow so fire now
+ _intf->fire_interrupt();
+ return;
+ }
+
+ // Update variables with new time
+ cycles_until_match = new_cycles_until_match;
+ too_close = cycles_until_match < _min_count_until_match;
+ }
+
+ if (too_close) {
+
+ // Low power ticker incremented to less than _min_count_until_match
+ // so low power ticker may not fire. Use Timeout to ensure it does fire.
+ uint32_t ticks = cycles_until_match < _min_count_until_match ? cycles_until_match : _min_count_until_match;
+ _timeout.attach_us(mbed::callback(this, &LowPowerTickerWrapper::_timeout_handler), _lp_ticks_to_us(ticks));
+ _pending_timeout = true;
+ return;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/LowPowerTickerWrapper.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,242 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOW_POWER_TICKER_WRAPPER_H
+#define MBED_LOW_POWER_TICKER_WRAPPER_H
+
+#include "device.h"
+
+#include "hal/ticker_api.h"
+#include "hal/us_ticker_api.h"
+#include "drivers/Timeout.h"
+
+
+class LowPowerTickerWrapper {
+public:
+
+
+ /**
+ * Create a new wrapped low power ticker object
+ *
+ * @param data Low power ticker data to wrap
+ * @param interface new ticker interface functions
+ * @param min_cycles_between_writes The number of whole low power clock periods
+ * which must complete before subsequent calls to set_interrupt
+ * @param min_cycles_until_match The minimum number of whole low power clock periods
+ * from the current time for which the match timestamp passed to set_interrupt is
+ * guaranteed to fire.
+ *
+ * N = min_cycles_between_writes
+ *
+ * 0 1 N - 1 N N + 1 N + 2 N + 3
+ * |-------|------...------|-------|-------|-------|-------|
+ * ^ ^
+ * | |
+ * set_interrupt Next set_interrupt allowed
+ *
+ * N = min_cycles_until_match
+ *
+ * 0 1 N - 1 N N + 1 N + 2 N + 3
+ * |-------|------...------|-------|-------|-------|-------|
+ * ^ ^
+ * | |
+ * set_interrupt Earliest match timestamp allowed
+ *
+ *
+ */
+
+ LowPowerTickerWrapper(const ticker_data_t *data, const ticker_interface_t *interface, uint32_t min_cycles_between_writes, uint32_t min_cycles_until_match);
+
+ /**
+ * Interrupt handler called by the underlying driver/hardware
+ *
+ * @param handler The callback which would normally be called by the underlying driver/hardware
+ */
+ void irq_handler(ticker_irq_handler_type handler);
+
+ /**
+ * Suspend wrapper operation and pass through interrupts.
+ *
+ * This stops to wrapper layer from using the microsecond ticker.
+ * This should be called before using the low power ticker APIs directly.
+ *
+ * @warning: Make sure to suspend the LP ticker first (call ticker_suspend()),
+ * otherwise the behavior is undefined.
+ */
+ void suspend();
+
+ /**
+ * Resume wrapper operation and filter interrupts normally
+ */
+ void resume();
+
+ /**
+ * Check if a Timeout object is being used
+ *
+ * @return true if Timeout is used for scheduling false otherwise
+ */
+ bool timeout_pending();
+
+ /*
+ * Implementation of ticker_init
+ */
+ void init();
+
+ /*
+ * Implementation of free
+ */
+ void free();
+
+ /*
+ * Implementation of read
+ */
+ uint32_t read();
+
+ /*
+ * Implementation of set_interrupt
+ */
+ void set_interrupt(timestamp_t timestamp);
+
+ /*
+ * Implementation of disable_interrupt
+ */
+ void disable_interrupt();
+
+ /*
+ * Implementation of clear_interrupt
+ */
+ void clear_interrupt();
+
+ /*
+ * Implementation of fire_interrupt
+ */
+ void fire_interrupt();
+
+ /*
+ * Implementation of get_info
+ */
+ const ticker_info_t *get_info();
+
+ ticker_data_t data;
+
+private:
+ mbed::Timeout _timeout;
+ const ticker_interface_t *const _intf;
+
+ /*
+ * The number of low power clock cycles which must pass between subsequent
+ * calls to intf->set_interrupt
+ */
+ const uint32_t _min_count_between_writes;
+
+ /*
+ * The minimum number of low power clock cycles in the future that
+ * a match value can be set to and still fire
+ */
+ const uint32_t _min_count_until_match;
+
+ /*
+ * Flag to indicate if the timer is suspended
+ */
+ bool _suspended;
+
+ /*
+ * _cur_match_time is valid and Timeout is scheduled to fire
+ */
+ bool _pending_timeout;
+
+ /*
+ * set_interrupt has been called and _cur_match_time is valid
+ */
+ bool _pending_match;
+
+ /*
+ * The function LowPowerTickerWrapper::fire_interrupt has been called
+ * and an interrupt is expected.
+ */
+ bool _pending_fire_now;
+
+ /*
+ * It is safe to call intf->set_interrupt
+ */
+ bool _set_interrupt_allowed;
+
+ /*
+ * Last value written by LowPowerTickerWrapper::set_interrupt
+ */
+ timestamp_t _cur_match_time;
+
+ /*
+ * Time of last call to LowPowerTickerWrapper::set_interrupt
+ */
+ uint32_t _last_set_interrupt;
+
+ /*
+ * Time of last call to intf->set_interrupt
+ */
+ uint32_t _last_actual_set_interrupt;
+
+ /*
+ * Mask of valid bits from intf->read()
+ */
+ uint32_t _mask;
+
+ /*
+ * Microsecond per low power tick (rounded up)
+ */
+ uint32_t _us_per_tick;
+
+
+ void _reset();
+
+ /**
+ * Set the low power ticker match time when hardware is ready
+ *
+ * This event is scheduled to set the lp timer after the previous write
+ * has taken effect and it is safe to write a new value without blocking.
+ * If the time has already passed then this function fires and interrupt
+ * immediately.
+ */
+ void _timeout_handler();
+
+ /*
+ * Check match time has passed
+ */
+ bool _match_check(timestamp_t current);
+
+ /*
+ * Convert low power ticks to approximate microseconds
+ *
+ * This value is always larger or equal to exact value.
+ */
+ uint32_t _lp_ticks_to_us(uint32_t);
+
+ /*
+ * Schedule a match interrupt to fire at the correct time
+ *
+ * @param current The current low power ticker time
+ */
+ void _schedule_match(timestamp_t current);
+
+};
+
+#endif
+
+/** @}*/
+
+
--- a/hal/crc_api.h Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/crc_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -33,6 +33,7 @@
POLY_16BIT_CCITT = 0x1021, // x16+x12+x5+1
POLY_16BIT_IBM = 0x8005, // x16+x15+x2+1
POLY_32BIT_ANSI = 0x04C11DB7, // x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
+ POLY_32BIT_REV_ANSI = 0xEDB88320
} crc_polynomial_t;
typedef struct crc_mbed_config {
--- a/hal/mbed_critical_section_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_critical_section_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -49,10 +49,8 @@
MBED_WEAK void hal_critical_section_exit(void)
{
-#ifndef FEATURE_UVISOR
// Interrupts must be disabled on invoking an exit from a critical section
MBED_ASSERT(!are_interrupts_enabled());
-#endif
state_saved = false;
// Restore the IRQs to their state prior to entering the critical section
--- a/hal/mbed_lp_ticker_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_lp_ticker_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,11 +14,10 @@
* limitations under the License.
*/
#include "hal/lp_ticker_api.h"
+#include "hal/mbed_lp_ticker_wrapper.h"
#if DEVICE_LPTICKER
-void lp_ticker_set_interrupt_wrapper(timestamp_t timestamp);
-
static ticker_event_queue_t events = { 0 };
static ticker_irq_handler_type irq_handler = ticker_irq_handler;
@@ -28,13 +27,10 @@
.read = lp_ticker_read,
.disable_interrupt = lp_ticker_disable_interrupt,
.clear_interrupt = lp_ticker_clear_interrupt,
-#if LPTICKER_DELAY_TICKS > 0
- .set_interrupt = lp_ticker_set_interrupt_wrapper,
-#else
.set_interrupt = lp_ticker_set_interrupt,
-#endif
.fire_interrupt = lp_ticker_fire_interrupt,
.get_info = lp_ticker_get_info,
+ .free = lp_ticker_free,
};
static const ticker_data_t lp_data = {
@@ -44,7 +40,11 @@
const ticker_data_t *get_lp_ticker_data(void)
{
+#if LPTICKER_DELAY_TICKS > 0
+ return get_lp_ticker_wrapper_data(&lp_data);
+#else
return &lp_data;
+#endif
}
ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler)
@@ -58,9 +58,13 @@
void lp_ticker_irq_handler(void)
{
+#if LPTICKER_DELAY_TICKS > 0
+ lp_ticker_wrapper_irq_handler(irq_handler);
+#else
if (irq_handler) {
irq_handler(&lp_data);
}
+#endif
}
#endif
--- a/hal/mbed_lp_ticker_wrapper.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_lp_ticker_wrapper.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -13,144 +13,115 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include "hal/lp_ticker_api.h"
+#include "hal/mbed_lp_ticker_wrapper.h"
#if DEVICE_LPTICKER && (LPTICKER_DELAY_TICKS > 0)
-#include "Timeout.h"
-#include "mbed_critical.h"
-
-static const timestamp_t min_delta = LPTICKER_DELAY_TICKS;
-
-static bool init = false;
-static bool pending = false;
-static bool timeout_pending = false;
-static timestamp_t last_set_interrupt = 0;
-static timestamp_t last_request = 0;
-static timestamp_t next = 0;
-
-static timestamp_t mask;
-static timestamp_t reschedule_us;
+#include "hal/LowPowerTickerWrapper.h"
+#include "platform/mbed_critical.h"
// Do not use SingletonPtr since this must be initialized in a critical section
-static mbed::Timeout *timeout;
-static uint64_t timeout_data[sizeof(mbed::Timeout) / 8];
+static LowPowerTickerWrapper *ticker_wrapper;
+static uint64_t ticker_wrapper_data[(sizeof(LowPowerTickerWrapper) + 7) / 8];
+static bool init = false;
-/**
- * Initialize variables
- */
-static void init_local()
+static void lp_ticker_wrapper_init()
{
- MBED_ASSERT(core_util_in_critical_section());
+ ticker_wrapper->init();
+}
- const ticker_info_t *info = lp_ticker_get_info();
- if (info->bits >= 32) {
- mask = 0xffffffff;
- } else {
- mask = ((uint64_t)1 << info->bits) - 1;
- }
+static uint32_t lp_ticker_wrapper_read()
+{
+ return ticker_wrapper->read();
+}
- // Round us_per_tick up
- timestamp_t us_per_tick = (1000000 + info->frequency - 1) / info->frequency;
+static void lp_ticker_wrapper_set_interrupt(timestamp_t timestamp)
+{
+ ticker_wrapper->set_interrupt(timestamp);
+}
- // Add 1 tick to the min delta for the case where the clock transitions after you read it
- // Add 4 microseconds to round up the micro second ticker time (which has a frequency of at least 250KHz - 4us period)
- reschedule_us = (min_delta + 1) * us_per_tick + 4;
-
- timeout = new (timeout_data) mbed::Timeout();
+static void lp_ticker_wrapper_disable_interrupt()
+{
+ ticker_wrapper->disable_interrupt();
}
-/**
- * Call lp_ticker_set_interrupt with a value that is guaranteed to fire
- *
- * Assumptions
- * -Only one low power clock tick can pass from the last read (last_read)
- * -The closest an interrupt can fire is max_delta + 1
- *
- * @param last_read The last value read from lp_ticker_read
- * @param timestamp The timestamp to trigger the interrupt at
- */
-static void set_interrupt_safe(timestamp_t last_read, timestamp_t timestamp)
+static void lp_ticker_wrapper_clear_interrupt()
+{
+ ticker_wrapper->clear_interrupt();
+}
+
+static void lp_ticker_wrapper_fire_interrupt()
{
- MBED_ASSERT(core_util_in_critical_section());
- uint32_t delta = (timestamp - last_read) & mask;
- if (delta < min_delta + 2) {
- timestamp = (last_read + min_delta + 2) & mask;
- }
- lp_ticker_set_interrupt(timestamp);
+ ticker_wrapper->fire_interrupt();
+}
+
+static const ticker_info_t *lp_ticker_wrapper_get_info()
+{
+ return ticker_wrapper->get_info();
}
-/**
- * Set the low power ticker match time when hardware is ready
- *
- * This event is scheduled to set the lp timer after the previous write
- * has taken effect and it is safe to write a new value without blocking.
- * If the time has already passed then this function fires and interrupt
- * immediately.
- */
-static void set_interrupt_later()
+static void lp_ticker_wrapper_free()
+{
+ ticker_wrapper->free();
+}
+
+static const ticker_interface_t lp_interface = {
+ lp_ticker_wrapper_init,
+ lp_ticker_wrapper_read,
+ lp_ticker_wrapper_disable_interrupt,
+ lp_ticker_wrapper_clear_interrupt,
+ lp_ticker_wrapper_set_interrupt,
+ lp_ticker_wrapper_fire_interrupt,
+ lp_ticker_wrapper_free,
+ lp_ticker_wrapper_get_info
+};
+
+void lp_ticker_wrapper_irq_handler(ticker_irq_handler_type handler)
{
core_util_critical_section_enter();
- timestamp_t current = lp_ticker_read();
- if (_ticker_match_interval_passed(last_request, current, next)) {
- lp_ticker_fire_interrupt();
- } else {
- set_interrupt_safe(current, next);
- last_set_interrupt = lp_ticker_read();
+ if (!init) {
+ // Force ticker to initialize
+ get_lp_ticker_data();
}
- timeout_pending = false;
+
+ ticker_wrapper->irq_handler(handler);
core_util_critical_section_exit();
}
-/**
- * Wrapper around lp_ticker_set_interrupt to prevent blocking
- *
- * Problems this function is solving:
- * 1. Interrupt may not fire if set earlier than LPTICKER_DELAY_TICKS low power clock cycles
- * 2. Setting the interrupt back-to-back will block
- *
- * This wrapper function prevents lp_ticker_set_interrupt from being called
- * back-to-back and blocking while the first write is in progress. This function
- * avoids that problem by scheduling a timeout event if the lp ticker is in the
- * middle of a write operation.
- *
- * @param timestamp Time to call ticker irq
- * @note this is a utility function and it's not required part of HAL implementation
- */
-extern "C" void lp_ticker_set_interrupt_wrapper(timestamp_t timestamp)
+const ticker_data_t *get_lp_ticker_wrapper_data(const ticker_data_t *data)
{
core_util_critical_section_enter();
if (!init) {
- init_local();
+ ticker_wrapper = new (ticker_wrapper_data) LowPowerTickerWrapper(data, &lp_interface, LPTICKER_DELAY_TICKS, LPTICKER_DELAY_TICKS);
init = true;
}
- timestamp_t current = lp_ticker_read();
- if (pending) {
- // Check if pending should be cleared
- if (((current - last_set_interrupt) & mask) >= min_delta) {
- pending = false;
- }
+ core_util_critical_section_exit();
+
+ return &ticker_wrapper->data;
+}
+
+void lp_ticker_wrapper_suspend()
+{
+ if (!init) {
+ // Force ticker to initialize
+ get_lp_ticker_data();
}
- if (pending || timeout_pending) {
- next = timestamp;
- last_request = current;
- if (!timeout_pending) {
- timeout->attach_us(set_interrupt_later, reschedule_us);
- timeout_pending = true;
- }
- } else {
- // Schedule immediately if nothing is pending
- set_interrupt_safe(current, timestamp);
- last_set_interrupt = lp_ticker_read();
- pending = true;
+ ticker_wrapper->suspend();
+}
+
+void lp_ticker_wrapper_resume()
+{
+ if (!init) {
+ // Force ticker to initialize
+ get_lp_ticker_data();
}
- core_util_critical_section_exit();
+ ticker_wrapper->resume();
}
#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_lp_ticker_wrapper.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,81 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LP_TICKER_WRAPPER_H
+#define MBED_LP_TICKER_WRAPPER_H
+
+#include "device.h"
+
+#if DEVICE_LPTICKER
+
+#include "hal/ticker_api.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
+
+/**
+ * Interrupt handler for the wrapped lp ticker
+ *
+ * @param handler the function which would normally be called by the
+ * lp ticker handler when it is not wrapped
+ */
+void lp_ticker_wrapper_irq_handler(ticker_irq_handler_type handler);
+
+/**
+ * Get wrapped lp ticker data
+ *
+ * @param data hardware low power ticker object
+ * @return wrapped low power ticker object
+ */
+const ticker_data_t *get_lp_ticker_wrapper_data(const ticker_data_t *data);
+
+/**
+ * Suspend the wrapper layer code
+ *
+ * Pass through all interrupts to the low power ticker and stop using
+ * the microsecond ticker.
+ *
+ * @warning: Make sure to suspend the LP ticker first (call ticker_suspend()),
+ * otherwise the behavior is undefined.
+ */
+void lp_ticker_wrapper_suspend(void);
+
+/**
+ * Resume the wrapper layer code
+ *
+ * Resume operation of the wrapper layer. Interrupts will be filtered
+ * as normal and the microsecond timer will be used for interrupts scheduled
+ * too quickly back-to-back.
+ */
+void lp_ticker_wrapper_resume(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
--- a/hal/mbed_sleep_manager.c Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_sleep_manager.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,17 +14,18 @@
* limitations under the License.
*/
-#include "mbed_assert.h"
-#include "mbed_power_mgmt.h"
-#include "mbed_critical.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_power_mgmt.h"
+#include "platform/mbed_critical.h"
#include "sleep_api.h"
-#include "mbed_error.h"
-#include "mbed_debug.h"
-#include "mbed_stats.h"
+#include "platform/mbed_error.h"
+#include "platform/mbed_debug.h"
+#include "platform/mbed_stats.h"
+#include "us_ticker_api.h"
#include "lp_ticker_api.h"
#include <limits.h>
#include <stdio.h>
-#include "mbed_stats.h"
+#include "platform/mbed_stats.h"
#if DEVICE_SLEEP
@@ -162,6 +163,10 @@
if (deep_sleep_lock == USHRT_MAX) {
core_util_critical_section_exit();
MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_OVERFLOW), "DeepSleepLock overflow (> USHRT_MAX)", deep_sleep_lock);
+ // When running sleep_manager tests, the mbed_error() is overridden
+ // and no longer calls mbed_halt_system(). Return to prevent
+ // execution of the following code.
+ return;
}
core_util_atomic_incr_u16(&deep_sleep_lock, 1);
core_util_critical_section_exit();
@@ -173,6 +178,10 @@
if (deep_sleep_lock == 0) {
core_util_critical_section_exit();
MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_UNDERFLOW), "DeepSleepLock underflow (< 0)", deep_sleep_lock);
+ // When running sleep_manager tests, the mbed_error() is overridden
+ // and no longer calls mbed_halt_system(). Return to prevent
+ // execution of the following code.
+ return;
}
core_util_atomic_decr_u16(&deep_sleep_lock, 1);
core_util_critical_section_exit();
@@ -183,6 +192,19 @@
return deep_sleep_lock == 0 ? true : false;
}
+bool sleep_manager_can_deep_sleep_test_check()
+{
+ const uint32_t check_time_us = 2000;
+ const ticker_data_t *const ticker = get_us_ticker_data();
+ uint32_t start = ticker_read(ticker);
+ while ((ticker_read(ticker) - start) < check_time_us) {
+ if (sleep_manager_can_deep_sleep()) {
+ return true;
+ }
+ }
+ return false;
+}
+
void sleep_manager_sleep_auto(void)
{
#ifdef MBED_SLEEP_TRACING_ENABLED
--- a/hal/mbed_ticker_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_ticker_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
#include <stddef.h>
#include "hal/ticker_api.h"
#include "platform/mbed_critical.h"
-#include "mbed_assert.h"
+#include "platform/mbed_assert.h"
static void schedule_interrupt(const ticker_data_t *const ticker);
static void update_present_time(const ticker_data_t *const ticker);
@@ -32,6 +32,9 @@
if (ticker->queue->initialized) {
return;
}
+ if (ticker->queue->suspended) {
+ return;
+ }
ticker->interface->init();
@@ -44,7 +47,7 @@
uint8_t frequency_shifts = 0;
for (uint8_t i = 31; i > 0; --i) {
- if ((1 << i) == frequency) {
+ if ((1U << i) == frequency) {
frequency_shifts = i;
break;
}
@@ -70,6 +73,7 @@
ticker->queue->max_delta_us = max_delta_us;
ticker->queue->present_time = 0;
ticker->queue->dispatching = false;
+ ticker->queue->suspended = false;
ticker->queue->initialized = true;
update_present_time(ticker);
@@ -121,6 +125,9 @@
static void update_present_time(const ticker_data_t *const ticker)
{
ticker_event_queue_t *queue = ticker->queue;
+ if (queue->suspended) {
+ return;
+ }
uint32_t ticker_time = ticker->interface->read();
if (ticker_time == ticker->queue->tick_last_read) {
// No work to do
@@ -165,9 +172,9 @@
}
/**
- * Given the absolute timestamp compute the hal tick timestamp.
+ * Given the absolute timestamp compute the hal tick timestamp rounded up.
*/
-static timestamp_t compute_tick(const ticker_data_t *const ticker, us_timestamp_t timestamp)
+static timestamp_t compute_tick_round_up(const ticker_data_t *const ticker, us_timestamp_t timestamp)
{
ticker_event_queue_t *queue = ticker->queue;
us_timestamp_t delta_us = timestamp - queue->present_time;
@@ -186,14 +193,14 @@
} else if (0 != queue->frequency_shifts) {
// Optimized frequencies divisible by 2
- delta = (delta_us << ticker->queue->frequency_shifts) / 1000000;
+ delta = ((delta_us << ticker->queue->frequency_shifts) + 1000000 - 1) / 1000000;
if (delta > ticker->queue->max_delta) {
delta = ticker->queue->max_delta;
}
} else {
// General case
- delta = delta_us * queue->frequency / 1000000;
+ delta = (delta_us * queue->frequency + 1000000 - 1) / 1000000;
if (delta > ticker->queue->max_delta) {
delta = ticker->queue->max_delta;
}
@@ -230,7 +237,7 @@
static void schedule_interrupt(const ticker_data_t *const ticker)
{
ticker_event_queue_t *queue = ticker->queue;
- if (ticker->queue->dispatching) {
+ if (queue->suspended || ticker->queue->dispatching) {
// Don't schedule the next interrupt until dispatching is
// finished. This prevents repeated calls to interface->set_interrupt
return;
@@ -249,14 +256,11 @@
return;
}
- timestamp_t match_tick = compute_tick(ticker, match_time);
- // The time has been checked to be future, but it could still round
- // to the last tick as a result of us to ticks conversion
- if (match_tick == queue->tick_last_read) {
- // Match time has already expired so fire immediately
- ticker->interface->fire_interrupt();
- return;
- }
+ timestamp_t match_tick = compute_tick_round_up(ticker, match_time);
+
+ // The same tick should never occur since match_tick is rounded up.
+ // If the same tick is returned scheduling will not work correctly.
+ MBED_ASSERT(match_tick != queue->tick_last_read);
ticker->interface->set_interrupt(match_tick);
timestamp_t cur_tick = ticker->interface->read();
@@ -285,6 +289,10 @@
core_util_critical_section_enter();
ticker->interface->clear_interrupt();
+ if (ticker->queue->suspended) {
+ core_util_critical_section_exit();
+ return;
+ }
/* Go through all the pending TimerEvents */
ticker->queue->dispatching = true;
@@ -430,3 +438,29 @@
return ret;
}
+
+void ticker_suspend(const ticker_data_t *const ticker)
+{
+ core_util_critical_section_enter();
+
+ ticker->queue->suspended = true;
+
+ core_util_critical_section_exit();
+}
+
+void ticker_resume(const ticker_data_t *const ticker)
+{
+ core_util_critical_section_enter();
+
+ ticker->queue->suspended = false;
+ if (ticker->queue->initialized) {
+ ticker->queue->tick_last_read = ticker->interface->read();
+
+ update_present_time(ticker);
+ schedule_interrupt(ticker);
+ } else {
+ initialize(ticker);
+ }
+
+ core_util_critical_section_exit();
+}
--- a/hal/mbed_us_ticker_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/mbed_us_ticker_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -27,6 +27,7 @@
.set_interrupt = us_ticker_set_interrupt,
.fire_interrupt = us_ticker_fire_interrupt,
.get_info = us_ticker_get_info,
+ .free = us_ticker_free,
};
static const ticker_data_t us_data = {
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/qspi_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,194 @@
+
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_API_H
+#define MBED_QSPI_API_H
+
+#include "device.h"
+#include <stdbool.h>
+
+#if DEVICE_QSPI
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_qspi QSPI HAL
+ * @{
+ */
+
+/** QSPI HAL object
+ */
+typedef struct qspi_s qspi_t;
+
+/** QSPI Bus width
+ *
+ * Some parts of commands provide variable bus width
+ */
+typedef enum qspi_bus_width {
+ QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_BUS_DUAL,
+ QSPI_CFG_BUS_QUAD,
+} qspi_bus_width_t;
+
+/** Address size in bits
+ */
+typedef enum qspi_address_size {
+ QSPI_CFG_ADDR_SIZE_8,
+ QSPI_CFG_ADDR_SIZE_16,
+ QSPI_CFG_ADDR_SIZE_24,
+ QSPI_CFG_ADDR_SIZE_32,
+} qspi_address_size_t;
+
+/** Alternative size in bits
+ */
+typedef enum qspi_alt_size {
+ QSPI_CFG_ALT_SIZE_8,
+ QSPI_CFG_ALT_SIZE_16,
+ QSPI_CFG_ALT_SIZE_24,
+ QSPI_CFG_ALT_SIZE_32,
+} qspi_alt_size_t;
+
+/** QSPI command
+ *
+ * Defines a frame format. It consists of instruction, address, alternative, dummy count and data
+ */
+typedef struct qspi_command {
+ struct {
+ qspi_bus_width_t bus_width; /**< Bus width for the instruction >*/
+ uint8_t value; /**< Instruction value >*/
+ bool disabled; /**< Instruction phase skipped if disabled is set to true >*/
+ } instruction;
+ struct {
+ qspi_bus_width_t bus_width; /**< Bus width for the address >*/
+ qspi_address_size_t size; /**< Address size >*/
+ uint32_t value; /**< Address value >*/
+ bool disabled; /**< Address phase skipped if disabled is set to true >*/
+ } address;
+ struct {
+ qspi_bus_width_t bus_width; /**< Bus width for alternative >*/
+ qspi_alt_size_t size; /**< Alternative size >*/
+ uint32_t value; /**< Alternative value >*/
+ bool disabled; /**< Alternative phase skipped if disabled is set to true >*/
+ } alt;
+ uint8_t dummy_count; /**< Dummy cycles count >*/
+ struct {
+ qspi_bus_width_t bus_width; /**< Bus width for data >*/
+ } data;
+} qspi_command_t;
+
+/** QSPI return status
+ */
+typedef enum qspi_status {
+ QSPI_STATUS_ERROR = -1, /**< Generic error >*/
+ QSPI_STATUS_INVALID_PARAMETER = -2, /**< The parameter is invalid >*/
+ QSPI_STATUS_OK = 0, /**< Function executed sucessfully >*/
+} qspi_status_t;
+
+/** Initialize QSPI peripheral.
+ *
+ * It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled
+ *
+ * @param obj QSPI object
+ * @param io0 Data pin 0
+ * @param io1 Data pin 1
+ * @param io2 Data pin 2
+ * @param io3 Data pin 3
+ * @param sclk The clock pin
+ * @param ssel The chip select pin
+ * @param hz The bus frequency
+ * @param mode Clock polarity and phase mode (0 - 3)
+ * @return QSPI_STATUS_OK if initialisation successfully executed
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode);
+
+/** Deinitilize QSPI peripheral
+ *
+ * It should release pins that are associated with the QSPI object, and disable clocks for QSPI peripheral module that was associated with the object
+ *
+ * @param obj QSPI object
+ * @return QSPI_STATUS_OK if deinitialisation successfully executed
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_free(qspi_t *obj);
+
+/** Set the QSPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and the bus clock
+ * Configures the QSPI peripheral's baud rate
+ * @param obj The SPI object to configure
+ * @param hz The baud rate in Hz
+ * @return QSPI_STATUS_OK if frequency was set
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_frequency(qspi_t *obj, int hz);
+
+/** Send a command and block of data
+ *
+ * @param obj QSPI object
+ * @param command QSPI command
+ * @param data TX buffer
+ * @param[in,out] length in - TX buffer length in bytes, out - number of bytes written
+ * @return QSPI_STATUS_OK if the data has been succesfully sent
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length);
+
+/** Send a command (and optionally data) and get the response. Can be used to send/receive device specific commands
+ *
+ * @param obj QSPI object
+ * @param command QSPI command
+ * @param tx_data TX buffer
+ * @param tx_size TX buffer length in bytes
+ * @param rx_data RX buffer
+ * @param rx_size RX buffer length in bytes
+ * @return QSPI_STATUS_OK if the data has been succesfully sent
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size);
+
+/** Receive a command and block of data
+ *
+ * @param obj QSPI object
+ * @param command QSPI command
+ * @param data RX buffer
+ * @param[in,out] length in - RX buffer length in bytes, out - number of bytes read
+ * @return QSPI_STATUS_OK if data has been succesfully received
+ QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
+ QSPI_STATUS_ERROR otherwise
+ */
+qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+/** @}*/
--- a/hal/ticker_api.h Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/ticker_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -64,6 +64,7 @@
void (*clear_interrupt)(void); /**< Clear interrupt function */
void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
void (*fire_interrupt)(void); /**< Fire interrupt right-away */
+ void (*free)(void); /**< Disable function */
const ticker_info_t *(*get_info)(void); /**< Return info about this ticker's implementation */
} ticker_interface_t;
@@ -81,6 +82,7 @@
us_timestamp_t present_time; /**< Store the timestamp used for present time */
bool initialized; /**< Indicate if the instance is initialized */
bool dispatching; /**< The function ticker_irq_handler is dispatching */
+ bool suspended; /**< Indicate if the instance is suspended */
uint8_t frequency_shifts; /**< If frequency is a value of 2^n, this is n, otherwise 0 */
} ticker_event_queue_t;
@@ -183,6 +185,27 @@
*/
int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
+/** Suspend this ticker
+ *
+ * When suspended reads will always return the same time and no
+ * events will be dispatched. When suspended the common layer
+ * will only ever call the interface function clear_interrupt()
+ * and that is only if ticker_irq_handler is called.
+ *
+ *
+ * @param ticker The ticker object.
+ */
+void ticker_suspend(const ticker_data_t *const ticker);
+
+/** Resume this ticker
+ *
+ * When resumed the ticker will ignore any time that has passed
+ * and continue counting up where it left off.
+ *
+ * @param ticker The ticker object.
+ */
+void ticker_resume(const ticker_data_t *const ticker);
+
/* Private functions
*
* @cond PRIVATE
--- a/hal/us_ticker_api.h Thu Sep 06 13:40:20 2018 +0100
+++ b/hal/us_ticker_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -170,6 +170,25 @@
* except us_ticker_init(), calling any function other than init is undefined.
*
* @note This function stops the ticker from counting.
+ *
+ * Pseudo Code:
+ * @code
+ * uint32_t us_ticker_free()
+ * {
+ * // Disable timer
+ * TIMER_CTRL &= ~TIMER_CTRL_ENABLE_Msk;
+ *
+ * // Disable the compare interrupt
+ * TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
+ *
+ * // Disable timer interrupt
+ * NVIC_DisableIRQ(TIMER_IRQn);
+ *
+ * // Disable clock gate so processor cannot read TIMER registers
+ * POWER_CTRL &= ~POWER_CTRL_TIMER_Msk;
+ * }
+ * @endcode
+ *
*/
void us_ticker_free(void);
--- a/mbed.h Thu Sep 06 13:40:20 2018 +0100 +++ b/mbed.h Thu Nov 08 11:46:34 2018 +0000 @@ -73,6 +73,7 @@ #include "drivers/UARTSerial.h" #include "drivers/FlashIAP.h" #include "drivers/MbedCRC.h" +#include "drivers/QSPI.h" // mbed Internal components #include "drivers/Timer.h"
--- a/platform/ATCmdParser.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/ATCmdParser.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -210,7 +210,8 @@
restart:
_aborted = false;
// Iterate through each line in the expected response
- while (response[0]) {
+ // response being NULL means we just want to check for OOBs
+ while (!response || response[0]) {
// Since response is const, we need to copy it into our buffer to
// add the line's null terminator and clobber value-matches with asterisks.
//
@@ -219,7 +220,7 @@
int offset = 0;
bool whole_line_wanted = false;
- while (response[i]) {
+ while (response && response[i]) {
if (response[i] == '%' && response[i + 1] != '%' && response[i + 1] != '*') {
_buffer[offset++] = '%';
_buffer[offset++] = '*';
@@ -252,6 +253,11 @@
int j = 0;
while (true) {
+ // If just peeking for OOBs, and at start of line, check
+ // readability
+ if (!response && j == 0 && !_fh->readable()) {
+ return false;
+ }
// Receive next character
int c = getc();
if (c < 0) {
@@ -279,6 +285,7 @@
if ((unsigned)j == oob->len && memcmp(
oob->prefix, _buffer + offset, oob->len) == 0) {
debug_if(_dbg_on, "AT! %s\n", oob->prefix);
+ _oob_cb_count++;
oob->cb();
if (_aborted) {
@@ -297,7 +304,7 @@
// Don't attempt scanning until we get delimiter if they included it in format
// This allows recv("Foo: %s\n") to work, and not match with just the first character of a string
// (scanf does not itself match whitespace in its format string, so \n is not significant to it)
- } else {
+ } else if (response) {
sscanf(_buffer + offset, _buffer, &count);
}
@@ -383,52 +390,9 @@
bool ATCmdParser::process_oob()
{
- if (!_fh->readable()) {
- return false;
- }
-
- int i = 0;
- while (true) {
- // Receive next character
- int c = getc();
- if (c < 0) {
- return false;
- }
- // Simplify newlines (borrowed from retarget.cpp)
- if ((c == CR && _in_prev != LF) ||
- (c == LF && _in_prev != CR)) {
- _in_prev = c;
- c = '\n';
- } else if ((c == CR && _in_prev == LF) ||
- (c == LF && _in_prev == CR)) {
- _in_prev = c;
- // onto next character
- continue;
- } else {
- _in_prev = c;
- }
- _buffer[i++] = c;
- _buffer[i] = 0;
-
- // Check for oob data
- struct oob *oob = _oobs;
- while (oob) {
- if (i == (int)oob->len && memcmp(
- oob->prefix, _buffer, oob->len) == 0) {
- debug_if(_dbg_on, "AT! %s\r\n", oob->prefix);
- oob->cb();
- return true;
- }
- oob = oob->next;
- }
-
- // Clear the buffer when we hit a newline or ran out of space
- // running out of space usually means we ran into binary data
- if (((i + 1) >= _buffer_size) || (c == '\n')) {
- debug_if(_dbg_on, "AT< %s", _buffer);
- i = 0;
- }
- }
+ int pre_count = _oob_cb_count;
+ recv(NULL);
+ return _oob_cb_count != pre_count;
}
--- a/platform/ATCmdParser.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/ATCmdParser.h Thu Nov 08 11:46:34 2018 +0000
@@ -65,6 +65,7 @@
// Parsing information
const char *_output_delimiter;
int _output_delim_size;
+ int _oob_cb_count;
char _in_prev;
bool _dbg_on;
bool _aborted;
@@ -82,15 +83,15 @@
/**
* Constructor
*
- * @param fh A FileHandle to a digital interface to use for AT commands
- * @param output_delimiter end of command line termination
- * @param buffer_size size of internal buffer for transaction
- * @param timeout timeout of the connection
- * @param debug turns on/off debug output for AT commands
+ * @param fh A FileHandle to the digital interface, used for AT commands
+ * @param output_delimiter End of command-line termination
+ * @param buffer_size Size of internal buffer for transaction
+ * @param timeout Timeout of the connection
+ * @param debug Turns on/off debug output for AT commands
*/
ATCmdParser(FileHandle *fh, const char *output_delimiter = "\r",
int buffer_size = 256, int timeout = 8000, bool debug = false)
- : _fh(fh), _buffer_size(buffer_size), _in_prev(0), _oobs(NULL)
+ : _fh(fh), _buffer_size(buffer_size), _oob_cb_count(0), _in_prev(0), _oobs(NULL)
{
_buffer = new char[buffer_size];
set_timeout(timeout);
@@ -114,7 +115,8 @@
/**
* Allows timeout to be changed between commands
*
- * @param timeout timeout of the connection
+ * @param timeout ATCmdParser APIs (read/write/send/recv ..etc) throw an
+ * error if no response is received in `timeout` duration
*/
void set_timeout(int timeout)
{
@@ -122,13 +124,15 @@
}
/**
- * For backwards compatibility.
+ * For backward compatibility.
* @deprecated Do not use this function. This function has been replaced with set_timeout for consistency.
*
* Please use set_timeout(int) API only from now on.
* Allows timeout to be changed between commands
*
- * @param timeout timeout of the connection
+ * @param timeout ATCmdParser APIs (read/write/send/recv ..etc) throw an
+ * error if no response is received in `timeout` duration
+ *
*/
MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_timeout for consistency")
void setTimeout(int timeout)
@@ -139,7 +143,7 @@
/**
* Sets string of characters to use as line delimiters
*
- * @param output_delimiter string of characters to use as line delimiters
+ * @param output_delimiter String of characters to use as line delimiters
*/
void set_delimiter(const char *output_delimiter)
{
@@ -165,7 +169,7 @@
/**
* Allows traces from modem to be turned on or off
*
- * @param on set as 1 to turn on traces and vice versa.
+ * @param on Set as 1 to turn on traces and vice versa.
*/
void debug_on(uint8_t on)
{
@@ -173,12 +177,12 @@
}
/**
- * For backwards compatibility.
+ * For backward compatibility.
* @deprecated Do not use this function. This function has been replaced with debug_on for consistency.
*
* Allows traces from modem to be turned on or off
*
- * @param on set as 1 to turn on traces and vice versa.
+ * @param on Set as 1 to turn on traces and vice versa.
*/
MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with debug_on for consistency")
void debugOn(uint8_t on)
@@ -237,8 +241,8 @@
/**
* Write an array of bytes to the underlying stream
*
- * @param data the array of bytes to write
- * @param size number of bytes to write
+ * @param data The array of bytes to write
+ * @param size Number of bytes to write
* @return number of bytes written or -1 on failure
*/
int write(const char *data, int size);
@@ -246,8 +250,8 @@
/**
* Read an array of bytes from the underlying stream
*
- * @param data the destination for the read bytes
- * @param size number of bytes to read
+ * @param data The buffer for filling the read bytes
+ * @param size Number of bytes to read
* @return number of bytes read or -1 on failure
*/
int read(char *data, int size);
@@ -256,8 +260,8 @@
* Direct printf to underlying stream
* @see printf
*
- * @param format format string to pass to printf
- * @param ... arguments to printf
+ * @param format Format string to pass to printf
+ * @param ... Variable arguments to printf
* @return number of bytes written or -1 on failure
*/
int printf(const char *format, ...) MBED_PRINTF_METHOD(1, 2);
@@ -268,8 +272,8 @@
* Direct scanf on underlying stream
* @see scanf
*
- * @param format format string to pass to scanf
- * @param ... arguments to scanf
+ * @param format Format string to pass to scanf
+ * @param ... Variable arguments to scanf
* @return number of bytes read or -1 on failure
*/
int scanf(const char *format, ...) MBED_SCANF_METHOD(1, 2);
@@ -279,8 +283,8 @@
/**
* Attach a callback for out-of-band data
*
- * @param prefix string on when to initiate callback
- * @param func callback to call when string is read
+ * @param prefix String on when to initiate callback
+ * @param func Callback to call when string is read
* @note out-of-band data is only processed during a scanf call
*/
void oob(const char *prefix, mbed::Callback<void()> func);
@@ -293,7 +297,7 @@
/**
* Abort current recv
*
- * Can be called from oob handler to interrupt the current
+ * Can be called from out-of-band handler to interrupt the current
* recv operation.
*/
void abort();
@@ -304,7 +308,7 @@
* Process out-of-band data in the receive buffer. This function
* returns immediately if there is no data to process.
*
- * @return true if oob data processed, false otherwise
+ * @return true if out-of-band data processed, false otherwise
*/
bool process_oob(void);
};
--- a/platform/Callback.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/Callback.h Thu Nov 08 11:46:34 2018 +0000
@@ -601,7 +601,7 @@
/** Static thunk for passing as C-style function
* @param func Callback to call passed as void pointer
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func)
{
@@ -1226,7 +1226,7 @@
* @param func Callback to call passed as void pointer
* @param a0 An argument to be called with function func
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func, A0 a0)
{
@@ -1852,7 +1852,7 @@
* @param a0 An argument to be called with function func
* @param a1 An argument to be called with function func
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func, A0 a0, A1 a1)
{
@@ -2479,7 +2479,7 @@
* @param a1 An argument to be called with function func
* @param a2 An argument to be called with function func
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func, A0 a0, A1 a1, A2 a2)
{
@@ -3107,7 +3107,7 @@
* @param a2 An argument to be called with function func
* @param a3 An argument to be called with function func
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3)
{
@@ -3736,7 +3736,7 @@
* @param a3 An argument to be called with function func
* @param a4 An argument to be called with function func
* @return the value as determined by func which is of
- * type and determined by the signiture of func
+ * type and determined by the signature of func
*/
static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4)
{
@@ -3832,10 +3832,10 @@
typedef Callback<void(int)> event_callback_t;
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R>
Callback<R()> callback(R(*func)() = 0)
@@ -3843,10 +3843,10 @@
return Callback<R()>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R>
Callback<R()> callback(const Callback<R()> &func)
@@ -3854,11 +3854,11 @@
return Callback<R()>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R>
Callback<R()> callback(U *obj, R(T::*method)())
@@ -3866,11 +3866,11 @@
return Callback<R()>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R>
Callback<R()> callback(const U *obj, R(T::*method)() const)
@@ -3878,11 +3878,11 @@
return Callback<R()>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R>
Callback<R()> callback(volatile U *obj, R(T::*method)() volatile)
@@ -3890,11 +3890,11 @@
return Callback<R()>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R>
Callback<R()> callback(const volatile U *obj, R(T::*method)() const volatile)
@@ -3902,11 +3902,11 @@
return Callback<R()>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R>
Callback<R()> callback(R(*func)(T *), U *arg)
@@ -3914,11 +3914,11 @@
return Callback<R()>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R>
Callback<R()> callback(R(*func)(const T *), const U *arg)
@@ -3926,11 +3926,11 @@
return Callback<R()>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R>
Callback<R()> callback(R(*func)(volatile T *), volatile U *arg)
@@ -3938,11 +3938,11 @@
return Callback<R()>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R>
Callback<R()> callback(R(*func)(const volatile T *), const volatile U *arg)
@@ -3950,11 +3950,11 @@
return Callback<R()>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -3966,11 +3966,11 @@
return Callback<R()>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -3982,11 +3982,11 @@
return Callback<R()>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -3998,11 +3998,11 @@
return Callback<R()>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4015,10 +4015,10 @@
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0>
Callback<R(A0)> callback(R(*func)(A0) = 0)
@@ -4026,10 +4026,10 @@
return Callback<R(A0)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0>
Callback<R(A0)> callback(const Callback<R(A0)> &func)
@@ -4037,11 +4037,11 @@
return Callback<R(A0)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(U *obj, R(T::*method)(A0))
@@ -4049,11 +4049,11 @@
return Callback<R(A0)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(const U *obj, R(T::*method)(A0) const)
@@ -4061,11 +4061,11 @@
return Callback<R(A0)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(volatile U *obj, R(T::*method)(A0) volatile)
@@ -4073,11 +4073,11 @@
return Callback<R(A0)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(const volatile U *obj, R(T::*method)(A0) const volatile)
@@ -4085,11 +4085,11 @@
return Callback<R(A0)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(R(*func)(T *, A0), U *arg)
@@ -4097,11 +4097,11 @@
return Callback<R(A0)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(R(*func)(const T *, A0), const U *arg)
@@ -4109,11 +4109,11 @@
return Callback<R(A0)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(R(*func)(volatile T *, A0), volatile U *arg)
@@ -4121,11 +4121,11 @@
return Callback<R(A0)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0>
Callback<R(A0)> callback(R(*func)(const volatile T *, A0), const volatile U *arg)
@@ -4133,11 +4133,11 @@
return Callback<R(A0)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4149,11 +4149,11 @@
return Callback<R(A0)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4165,11 +4165,11 @@
return Callback<R(A0)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4181,11 +4181,11 @@
return Callback<R(A0)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4198,10 +4198,10 @@
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(R(*func)(A0, A1) = 0)
@@ -4209,10 +4209,10 @@
return Callback<R(A0, A1)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(const Callback<R(A0, A1)> &func)
@@ -4220,11 +4220,11 @@
return Callback<R(A0, A1)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(U *obj, R(T::*method)(A0, A1))
@@ -4232,11 +4232,11 @@
return Callback<R(A0, A1)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(const U *obj, R(T::*method)(A0, A1) const)
@@ -4244,11 +4244,11 @@
return Callback<R(A0, A1)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(volatile U *obj, R(T::*method)(A0, A1) volatile)
@@ -4256,11 +4256,11 @@
return Callback<R(A0, A1)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
@@ -4268,11 +4268,11 @@
return Callback<R(A0, A1)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(R(*func)(T *, A0, A1), U *arg)
@@ -4280,11 +4280,11 @@
return Callback<R(A0, A1)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(R(*func)(const T *, A0, A1), const U *arg)
@@ -4292,11 +4292,11 @@
return Callback<R(A0, A1)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(R(*func)(volatile T *, A0, A1), volatile U *arg)
@@ -4304,11 +4304,11 @@
return Callback<R(A0, A1)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1>
Callback<R(A0, A1)> callback(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
@@ -4316,11 +4316,11 @@
return Callback<R(A0, A1)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4332,11 +4332,11 @@
return Callback<R(A0, A1)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4348,11 +4348,11 @@
return Callback<R(A0, A1)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4364,11 +4364,11 @@
return Callback<R(A0, A1)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4381,10 +4381,10 @@
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(R(*func)(A0, A1, A2) = 0)
@@ -4392,10 +4392,10 @@
return Callback<R(A0, A1, A2)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(const Callback<R(A0, A1, A2)> &func)
@@ -4403,11 +4403,11 @@
return Callback<R(A0, A1, A2)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(U *obj, R(T::*method)(A0, A1, A2))
@@ -4415,11 +4415,11 @@
return Callback<R(A0, A1, A2)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(const U *obj, R(T::*method)(A0, A1, A2) const)
@@ -4427,11 +4427,11 @@
return Callback<R(A0, A1, A2)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
@@ -4439,11 +4439,11 @@
return Callback<R(A0, A1, A2)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
@@ -4451,11 +4451,11 @@
return Callback<R(A0, A1, A2)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(R(*func)(T *, A0, A1, A2), U *arg)
@@ -4463,11 +4463,11 @@
return Callback<R(A0, A1, A2)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(R(*func)(const T *, A0, A1, A2), const U *arg)
@@ -4475,11 +4475,11 @@
return Callback<R(A0, A1, A2)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
@@ -4487,11 +4487,11 @@
return Callback<R(A0, A1, A2)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
Callback<R(A0, A1, A2)> callback(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
@@ -4499,11 +4499,11 @@
return Callback<R(A0, A1, A2)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4515,11 +4515,11 @@
return Callback<R(A0, A1, A2)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4531,11 +4531,11 @@
return Callback<R(A0, A1, A2)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4547,11 +4547,11 @@
return Callback<R(A0, A1, A2)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4564,10 +4564,10 @@
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(R(*func)(A0, A1, A2, A3) = 0)
@@ -4575,10 +4575,10 @@
return Callback<R(A0, A1, A2, A3)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(const Callback<R(A0, A1, A2, A3)> &func)
@@ -4586,11 +4586,11 @@
return Callback<R(A0, A1, A2, A3)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(U *obj, R(T::*method)(A0, A1, A2, A3))
@@ -4598,11 +4598,11 @@
return Callback<R(A0, A1, A2, A3)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
@@ -4610,11 +4610,11 @@
return Callback<R(A0, A1, A2, A3)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
@@ -4622,11 +4622,11 @@
return Callback<R(A0, A1, A2, A3)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
@@ -4634,11 +4634,11 @@
return Callback<R(A0, A1, A2, A3)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(R(*func)(T *, A0, A1, A2, A3), U *arg)
@@ -4646,11 +4646,11 @@
return Callback<R(A0, A1, A2, A3)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
@@ -4658,11 +4658,11 @@
return Callback<R(A0, A1, A2, A3)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
@@ -4670,11 +4670,11 @@
return Callback<R(A0, A1, A2, A3)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
Callback<R(A0, A1, A2, A3)> callback(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
@@ -4682,11 +4682,11 @@
return Callback<R(A0, A1, A2, A3)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4698,11 +4698,11 @@
return Callback<R(A0, A1, A2, A3)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4714,11 +4714,11 @@
return Callback<R(A0, A1, A2, A3)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4730,11 +4730,11 @@
return Callback<R(A0, A1, A2, A3)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4747,10 +4747,10 @@
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(A0, A1, A2, A3, A4) = 0)
@@ -4758,10 +4758,10 @@
return Callback<R(A0, A1, A2, A3, A4)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(const Callback<R(A0, A1, A2, A3, A4)> &func)
@@ -4769,11 +4769,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
@@ -4781,11 +4781,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
@@ -4793,11 +4793,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
@@ -4805,11 +4805,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param method Member function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
@@ -4817,11 +4817,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
@@ -4829,11 +4829,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
@@ -4841,11 +4841,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
@@ -4853,11 +4853,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param func Static function to attach
* @param arg Pointer argument to function
- * @return Callback with infered type
+ * @return Callback with inferred type
*/
template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
@@ -4865,11 +4865,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4881,11 +4881,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4897,11 +4897,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
@@ -4913,11 +4913,11 @@
return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
}
-/** Create a callback class with type infered from the arguments
+/** Create a callback class with type inferred from the arguments
*
* @param obj Optional pointer to object to bind to function
* @param func Static function to attach
- * @return Callback with infered type
+ * @return Callback with inferred type
* @deprecated
* Arguments to callback have been reordered to callback(func, arg)
*/
--- a/platform/CircularBuffer.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/CircularBuffer.h Thu Nov 08 11:46:34 2018 +0000
@@ -92,10 +92,14 @@
core_util_critical_section_enter();
if (full()) {
_tail++;
- _tail %= BufferSize;
+ if (_tail == BufferSize) {
+ _tail = 0;
+ }
}
_pool[_head++] = data;
- _head %= BufferSize;
+ if (_head == BufferSize) {
+ _head = 0;
+ }
if (_head == _tail) {
_full = true;
}
@@ -113,7 +117,9 @@
core_util_critical_section_enter();
if (!empty()) {
data = _pool[_tail++];
- _tail %= BufferSize;
+ if (_tail == BufferSize) {
+ _tail = 0;
+ }
_full = false;
data_popped = true;
}
@@ -194,9 +200,9 @@
private:
T _pool[BufferSize];
- volatile CounterType _head;
- volatile CounterType _tail;
- volatile bool _full;
+ CounterType _head;
+ CounterType _tail;
+ bool _full;
};
/**@}*/
--- a/platform/DirHandle.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/DirHandle.h Thu Nov 08 11:46:34 2018 +0000
@@ -30,18 +30,24 @@
*/
-/** Represents a directory stream. Objects of this type are returned
- * by an opendir function. The core functions are read and seek,
+/** Represents a directory stream. An opendir function returns
+ * objects of this type. The core functions are read and seek,
* but only a subset needs to be provided.
*
- * If a FileSystemLike class defines the opendir method, then the
- * directories of an object of that type can be accessed by
- * DIR *d = opendir("/example/directory") (or opendir("/example")
- * to open the root of the filesystem), and then using readdir(d) etc.
+ * If a FileSystemLike class defines the opendir method, then you
+ * can access the directories of an object of that type by either:
+ * @code
+ * DIR *d = opendir("/example/directory");
+ * @endcode
+ * or
+ * @code
+ * DIR *d = opendir("/example");
+ * @endcode
+ * to open the root of the file system.
*
* The root directory is considered to contain all FileHandle and
- * FileSystem objects, so the DIR* returned by opendir("/") will
- * reflect this.
+ * FileSystem objects, so the DIR pointer returned by opendir("/")
+ * reflects this.
*
* @note to create a directory, @see Dir
* @note Synchronization level: Set by subclass
@@ -113,7 +119,7 @@
return close();
};
- /** Return the directory entry at the current position, and
+ /** Returns the directory entry at the current position, and
* advances the position to the next entry.
*
* @returns
--- a/platform/FileBase.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/FileBase.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -13,6 +13,8 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
+#include <cstring>
+
#include "platform/FileBase.h"
#include "platform/FileLike.h"
#include "platform/FileHandle.h"
@@ -21,6 +23,7 @@
FileBase *FileBase::_head = NULL;
SingletonPtr<PlatformMutex> FileBase::_mutex;
+FileBase *FileBase::_default = NULL;
FileBase::FileBase(const char *name, PathType t) : _next(NULL),
_name(name),
@@ -52,26 +55,42 @@
p->_next = _next;
}
}
+
+ if (_default == this) {
+ _default = NULL;
+ }
+
_mutex->unlock();
if (getPathType() == FilePathType) {
- extern void remove_filehandle(FileHandle * file);
- remove_filehandle(static_cast<FileHandle *>(static_cast<FileLike *>(this)));
+ extern void remove_filehandle(FileHandle *file);
+ remove_filehandle(static_cast<FileLike *>(this));
}
}
+void FileBase::set_as_default()
+{
+ _mutex->lock();
+ _default = this;
+ _mutex->unlock();
+}
+
FileBase *FileBase::lookup(const char *name, unsigned int len)
{
_mutex->lock();
FileBase *p = _head;
while (p != NULL) {
/* Check that p->_name matches name and is the correct length */
- if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+ if (p->_name != NULL && len == std::strlen(p->_name) && std::memcmp(p->_name, name, len) == 0) {
_mutex->unlock();
return p;
}
p = p->_next;
}
+ if (len == (sizeof "default") - 1 && std::memcmp("default", name, len) == 0) {
+ _mutex->unlock();
+ return _default;
+ }
_mutex->unlock();
return NULL;
}
--- a/platform/FileBase.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/FileBase.h Thu Nov 08 11:46:34 2018 +0000
@@ -18,9 +18,6 @@
typedef int FILEHANDLE;
-#include <cstdio>
-#include <cstring>
-
#include "platform/platform.h"
#include "platform/SingletonPtr.h"
#include "platform/PlatformMutex.h"
@@ -55,9 +52,11 @@
static FileBase *get(int n);
- /* disallow copy constructor and assignment operators */
+ void set_as_default();
+
private:
static FileBase *_head;
+ static FileBase *_default;
static SingletonPtr<PlatformMutex> _mutex;
FileBase *_next;
--- a/platform/FileHandle.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/FileHandle.h Thu Nov 08 11:46:34 2018 +0000
@@ -36,7 +36,7 @@
/** Class FileHandle
*
* An abstract interface that represents operations on a file-like
- * object. The core functions are read, write, and seek, but only
+ * object. The core functions are read, write and seek, but only
* a subset of these operations can be provided.
*
* @note to create a file, @see File
@@ -50,7 +50,7 @@
*
* Devices acting as FileHandles should follow POSIX semantics:
*
- * * if no data is available, and non-blocking set return -EAGAIN
+ * * if no data is available, and nonblocking set, return -EAGAIN
* * if no data is available, and blocking set, wait until some data is available
* * If any data is available, call returns immediately
*
@@ -65,8 +65,8 @@
* Devices acting as FileHandles should follow POSIX semantics:
*
* * if blocking, block until all data is written
- * * if no data can be written, and non-blocking set, return -EAGAIN
- * * if some data can be written, and non-blocking set, write partial
+ * * if no data can be written, and nonblocking set, return -EAGAIN
+ * * if some data can be written, and nonblocking set, write partial
*
* @param buffer The buffer to write from
* @param size The number of bytes to write
@@ -181,11 +181,11 @@
return size();
}
- /** Set blocking or non-blocking mode of the file operation like read/write.
- * Definition depends upon the subclass implementing FileHandle.
+ /** Set blocking or nonblocking mode of the file operation like read/write.
+ * Definition depends on the subclass implementing FileHandle.
* The default is blocking.
*
- * @param blocking true for blocking mode, false for non-blocking mode.
+ * @param blocking true for blocking mode, false for nonblocking mode.
*
* @return 0 on success
* @return Negative error code on failure
@@ -195,9 +195,9 @@
return blocking ? 0 : -ENOTTY;
}
- /** Check current blocking or non-blocking mode for file operations.
+ /** Check current blocking or nonblocking mode for file operations.
*
- * @return true for blocking mode, false for non-blocking mode.
+ * @return true for blocking mode, false for nonblocking mode.
*/
virtual bool is_blocking() const
{
@@ -205,9 +205,9 @@
}
/** Check for poll event flags
- * The input parameter can be used or ignored - the could always return all events,
- * or could check just the events listed in events.
- * Call is non-blocking - returns instantaneous state of events.
+ * You can use or ignore the input parameter. You can return all events
+ * or check just the events listed in events.
+ * Call is nonblocking - returns instantaneous state of events.
* Whenever an event occurs, the derived class should call the sigio() callback).
*
* @param events bitmask of poll events we're interested in - POLLIN/POLLOUT etc.
@@ -220,7 +220,7 @@
return POLLIN | POLLOUT;
}
- /** Definition depends upon the subclass implementing FileHandle.
+ /** Definition depends on the subclass implementing FileHandle.
* For example, if the FileHandle is of type Stream, writable() could return
* true when there is ample buffer space available for write() calls.
*
@@ -231,7 +231,7 @@
return poll(POLLOUT) & POLLOUT;
}
- /** Definition depends upon the subclass implementing FileHandle.
+ /** Definition depends on the subclass implementing FileHandle.
* For example, if the FileHandle is of type Stream, readable() could return
* true when there is something available to read.
*
@@ -250,11 +250,11 @@
* The callback may be called in an interrupt context and should not
* perform expensive operations.
*
- * Note! This is not intended as an attach-like asynchronous api, but rather
- * as a building block for constructing such functionality.
+ * Note! This is not intended as an attach-like asynchronous API, but rather
+ * as a building block for constructing such functionality.
*
* The exact timing of when the registered function
- * is called is not guaranteed and susceptible to change. It should be used
+ * is called is not guaranteed and is susceptible to change. It should be used
* as a cue to make read/write/poll calls to find the current state.
*
* @param func Function to call on state change
--- a/platform/NonCopyable.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/NonCopyable.h Thu Nov 08 11:46:34 2018 +0000
@@ -23,91 +23,106 @@
namespace mbed {
+/** \addtogroup platform */
+/** @{*/
/**
- * Inheriting from this class autogeneration of copy construction and copy
- * assignment operations.
- *
- * Classes which are not value type should inherit privately from this class
- * to avoid generation of invalid copy constructor or copy assignment operator
- * which can lead to unnoticeable programming errors.
- *
- * As an example consider the following signature:
- *
+ * \defgroup platform_NonCopyable NonCopyable class
+ * @{
+ */
+
+/**
+ * Prevents generation of copy constructor and copy assignment operator in
+ * derived classes.
+ *
+ * @par Usage
+ *
+ * To prevent generation of copy constructor and copy assignment operator,
+ * inherit privately from the NonCopyable class.
+ *
+ * @code
+ * class Resource : NonCopyable<Resource> { };
+ *
+ * Resource r;
+ * // generates compile time error:
+ * Resource r2 = r;
+ * @endcode
+ *
+ * @par Background information
+ *
+ * Instances of polymorphic classes are not meant to be copied. The
+ * C++ standards generate a default copy constructor and copy assignment
+ * function if these functions have not been defined in the class.
+ *
+ * Consider the following example:
+ *
* @code
- * class Resource;
- *
- * class Foo {
+ * // base class representing a connection
+ * struct Connection {
+ * Connection();
+ * virtual ~Connection();
+ * virtual void open() = 0;
+ * }
+ *
+ * class SerialConnection : public Connection {
* public:
- * Foo() : _resource(new Resource()) { }
- * ~Foo() { delete _resource; }
+ * SerialConnection(Serial*);
+ *
* private:
- * Resource* _resource;
+ * Serial* _serial;
+ * };
+ *
+ * Connection& get_connection() {
+ * static SerialConnection serial_connection;
+ * return serial_connection;
* }
*
- * Foo get_foo();
- *
- * Foo foo = get_foo();
+ * Connection connection = get_connection();
* @endcode
- *
- * There is a bug in this function, it returns a temporary value which will be
- * byte copied into foo then destroyed. Unfortunately, internally the Foo class
- * manage a pointer to a Resource object. This pointer will be released when the
- * temporary is destroyed and foo will manage a pointer to an already released
- * Resource.
- *
- * Two issues has to be fixed in the example above:
- * - Function signature has to be changed to reflect the fact that Foo
- * instances cannot be copied. In that case accessor should return a
- * reference to give access to objects already existing and managed.
- * Generator on the other hand should return a pointer to the created object.
- *
+ *
+ * There is a subtle bug in this code, the function get_connection returns a
+ * reference to a Connection which is captured by value instead of reference.
+ *
+ * When `get_connection` returns a reference to serial_connection it is copied into
+ * the local variable connection. The vtable and others members defined in Connection
+ * are copied, but members defined in SerialConnection are left apart. This can cause
+ * severe crashes or bugs if the virtual functions captured use members not present
+ * in the base declaration.
+ *
+ * To solve that problem, the copy constructor and assignment operator have to
+ * be declared (but don't need to be defined) in the private section of the
+ * Connection class:
+ *
* @code
- * // return a reference to an already managed Foo instance
- * Foo& get_foo();
- * Foo& foo = get_foo();
- *
- * // create a new Foo instance
- * Foo* make_foo();
- * Foo* m = make_foo();
- * @endcode
- *
- * - Copy constructor and copy assignment operator has to be made private
- * in the Foo class. It prevents unwanted copy of Foo objects. This can be
- * done by declaring copy constructor and copy assignment in the private
- * section of the Foo class.
- *
- * @code
- * class Foo {
- * public:
- * Foo() : _resource(new Resource()) { }
- * ~Foo() { delete _resource; }
+ * struct Connection {
* private:
- * // disallow copy operations
- * Foo(const Foo&);
- * Foo& operator=(const Foo&);
- * // data members
- * Resource* _resource;
+ * Connection(const Connection&);
+ * Connection& operator=(const Connection&);
* }
* @endcode
- *
- * Another solution is to inherit privately from the NonCopyable class.
- * It reduces the boiler plate needed to avoid copy operations but more
- * importantly it clarifies the programmer intent and the object semantic.
- *
- * class Foo : private NonCopyable<Foo> {
- * public:
- * Foo() : _resource(new Resource()) { }
- * ~Foo() { delete _resource; }
- * private:
- * Resource* _resource;
+ *
+ * Although manually declaring private copy constructor and assignment functions
+ * works, it is not ideal. These declarations are usually easy to forget,
+ * not immediately visible, and may be obscure to uninformed programmers.
+ *
+ * Using the NonCopyable class reduces the boilerplate required and expresses
+ * the intent because class inheritance appears right after the class name
+ * declaration.
+ *
+ * @code
+ * struct Connection : private NonCopyable<Connection> {
+ * // regular declarations
* }
- *
- * @tparam T The type that should be made non copyable. It prevent cases where
- * the empty base optimization cannot be applied and therefore ensure that the
- * cost of this semantic sugar is null.
- *
+ * @endcode
+ *
+ *
+ * @par Implementation details
+ *
+ * Using a template type prevents cases where the empty base optimization cannot
+ * be applied and therefore ensures that the cost of the NonCopyable semantic
+ * sugar is null.
+ *
* As an example, the empty base optimization is prohibited if one of the empty
- * base class is also a base type of the first non static data member:
+ * base classes is also a base type of the first nonstatic data member:
*
* @code
* struct A { };
@@ -121,11 +136,11 @@
* };
*
* // empty base optimization cannot be applied here because A from C and A from
- * // B shall have a different address. In that case, with the alignment
+ * // B have a different address. In that case, with the alignment
* // sizeof(C) == 2* sizeof(int)
* @endcode
*
- * The solution to that problem is to templatize the empty class to makes it
+ * The solution to that problem is to templatize the empty class to make it
* unique to the type it is applied to:
*
* @code
@@ -142,12 +157,15 @@
* // kind of A. sizeof(C) == sizeof(B) == sizeof(int).
* @endcode
*
- * @note Compile time errors are disabled if the develop or the release profile
- * is used. To override this behavior and force compile time errors in all profile
+ * @tparam T The type that should be made noncopyable.
+ *
+ * @note Compile time errors are disabled if you use the develop or release profile.
+ * To override this behavior and force compile time errors in all profiles,
* set the configuration parameter "platform.force-non-copyable-error" to true.
*/
template<typename T>
class NonCopyable {
+#ifndef DOXYGEN_ONLY
protected:
/**
* Disallow construction of NonCopyable objects from outside of its hierarchy.
@@ -162,11 +180,11 @@
/**
* NonCopyable copy constructor.
*
- * A compile time warning is issued when this function is used and a runtime
- * warning is printed when the copy construction of the non copyable happens.
+ * A compile time warning is issued when this function is used, and a runtime
+ * warning is printed when the copy construction of the noncopyable happens.
*
* If you see this warning, your code is probably doing something unspecified.
- * Copy of non copyable resources can lead to resource leak and random error.
+ * Copying of noncopyable resources can lead to resource leak and random error.
*/
MBED_DEPRECATED("Invalid copy construction of a NonCopyable resource.")
NonCopyable(const NonCopyable &)
@@ -177,11 +195,11 @@
/**
* NonCopyable copy assignment operator.
*
- * A compile time warning is issued when this function is used and a runtime
- * warning is printed when the copy construction of the non copyable happens.
+ * A compile time warning is issued when this function is used, and a runtime
+ * warning is printed when the copy construction of the noncopyable happens.
*
* If you see this warning, your code is probably doing something unspecified.
- * Copy of non copyable resources can lead to resource leak and random error.
+ * Copying of noncopyable resources can lead to resource leak and random error.
*/
MBED_DEPRECATED("Invalid copy assignment of a NonCopyable resource.")
NonCopyable &operator=(const NonCopyable &)
@@ -193,19 +211,24 @@
#else
private:
/**
- * Declare copy constructor as private, any attempt to copy construct
+ * Declare copy constructor as private. Any attempt to copy construct
* a NonCopyable will fail at compile time.
*/
NonCopyable(const NonCopyable &);
/**
- * Declare copy assignment operator as private, any attempt to copy assign
+ * Declare copy assignment operator as private. Any attempt to copy assign
* a NonCopyable will fail at compile time.
*/
NonCopyable &operator=(const NonCopyable &);
#endif
+#endif
};
+/**@}*/
+
+/**@}*/
+
} // namespace mbed
#endif /* MBED_NONCOPYABLE_H_ */
--- a/platform/PlatformMutex.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/PlatformMutex.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,10 +1,3 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_PlatformMutex PlatformMutex class
- * @{
- */
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
@@ -25,32 +18,67 @@
#include "platform/NonCopyable.h"
+/** \addtogroup platform
+ * @{
+ */
+
+/** \defgroup platform_PlatformMutex PlatformMutex class
+ * @{
+ */
+
+/** The PlatformMutex class is used to synchronize the execution of threads.
+ *
+ * Mbed drivers use the PlatformMutex class instead of rtos::Mutex.
+ * This enables the use of drivers when the Mbed OS is compiled without the RTOS.
+ *
+ * @note
+ * - When the RTOS is present, the PlatformMutex becomes a typedef for rtos::Mutex.
+ * - When the RTOS is absent, all methods are defined as noop.
+ */
+
#ifdef MBED_CONF_RTOS_PRESENT
+
#include "rtos/Mutex.h"
typedef rtos::Mutex PlatformMutex;
+
#else
-/** A stub mutex for when an RTOS is not present
-*/
-class PlatformMutex : private mbed::NonCopyable<PlatformMutex> {
+
+class PlatformMutex: private mbed::NonCopyable<PlatformMutex> {
public:
+ /** Create a PlatformMutex object.
+ *
+ * @note When the RTOS is present, this is an alias for rtos::Mutex::Mutex().
+ */
PlatformMutex()
{
- // Stub
+ }
- }
+ /** PlatformMutex destructor.
+ *
+ * @note When the RTOS is present, this is an alias for rtos::Mutex::~Mutex().
+ */
~PlatformMutex()
{
- // Stub
}
+ /** Wait until a PlatformMutex becomes available.
+ *
+ * @note
+ * - When the RTOS is present, this is an alias for rtos::Mutex::lock().
+ * - When the RTOS is absent, this is a noop.
+ */
void lock()
{
- // Do nothing
}
+ /** Unlock a PlatformMutex that the same thread has previously locked.
+ *
+ * @note
+ * - When the RTOS is present, this is an alias for rtos::Mutex::unlock().
+ * - When the RTOS is absent, this is a noop.
+ */
void unlock()
{
- // Do nothing
}
};
--- a/platform/ScopedLock.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/ScopedLock.h Thu Nov 08 11:46:34 2018 +0000
@@ -60,7 +60,7 @@
template <typename Lockable>
class ScopedLock : private NonCopyable<ScopedLock<Lockable> > {
public:
- /** Locks given locable object
+ /** Locks given lockable object
*
* @param lockable reference to the instance of Lockable object
* @note lockable object should outlive the ScopedLock object
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/SharedPtr.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,288 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SHAREDPTR_H__
+#define __SHAREDPTR_H__
+
+#include <stdlib.h>
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include "platform/mbed_critical.h"
+
+/** Shared pointer class.
+ *
+ * A shared pointer is a "smart" pointer that retains ownership of an object using
+ * reference counting accross all smart pointers referencing that object.
+ *
+ * @code
+ * #include "platform/SharedPtr.h"
+ *
+ * void test() {
+ * struct MyStruct { int a; };
+ *
+ * // Create shared pointer
+ * SharedPtr<MyStruct> ptr( new MyStruct );
+ *
+ * // Increase reference count
+ * SharedPtr<MyStruct> ptr2( ptr );
+ *
+ * ptr = NULL; // Reference to the struct instance is still held by ptr2
+ *
+ * ptr2 = NULL; // The raw pointer is freed
+ * }
+ * @endcode
+ *
+ *
+ * It is similar to the std::shared_ptr class introduced in C++11;
+ * however, this is not a compatible implementation (no weak pointer, no make_shared, no custom deleters and so on.)
+ *
+ * Usage: SharedPtr<Class> ptr(new Class())
+ *
+ * When ptr is passed around by value, the copy constructor and
+ * destructor manages the reference count of the raw pointer.
+ * If the counter reaches zero, delete is called on the raw pointer.
+ *
+ * To avoid loops, use "weak" references by calling the original
+ * pointer directly through ptr.get().
+ */
+
+template <class T>
+class SharedPtr {
+public:
+ /**
+ * @brief Create empty SharedPtr not pointing to anything.
+ * @details Used for variable declaration.
+ */
+ SharedPtr(): _ptr(NULL), _counter(NULL)
+ {
+ }
+
+ /**
+ * @brief Create new SharedPtr
+ * @param ptr Pointer to take control over
+ */
+ SharedPtr(T *ptr): _ptr(ptr), _counter(NULL)
+ {
+ // Allocate counter on the heap, so it can be shared
+ if (_ptr != NULL) {
+ _counter = new uint32_t;
+ *_counter = 1;
+ }
+ }
+
+ /**
+ * @brief Destructor.
+ * @details Decrement reference counter, and delete object if no longer pointed to.
+ */
+ ~SharedPtr()
+ {
+ decrement_counter();
+ }
+
+ /**
+ * @brief Copy constructor.
+ * @details Create new SharedPtr from other SharedPtr by
+ * copying pointer to original object and pointer to counter.
+ * @param source Object being copied from.
+ */
+ SharedPtr(const SharedPtr &source): _ptr(source._ptr), _counter(source._counter)
+ {
+ // Increment reference counter
+ if (_ptr != NULL) {
+ core_util_atomic_incr_u32(_counter, 1);
+ }
+ }
+
+ /**
+ * @brief Assignment operator.
+ * @details Cleanup previous reference and assign new pointer and counter.
+ * @param source Object being assigned from.
+ * @return Object being assigned.
+ */
+ SharedPtr operator=(const SharedPtr &source)
+ {
+ if (this != &source) {
+ // Clean up by decrementing counter
+ decrement_counter();
+
+ // Assign new values
+ _ptr = source.get();
+ _counter = source.get_counter();
+
+ // Increment new counter
+ if (_ptr != NULL) {
+ core_util_atomic_incr_u32(_counter, 1);
+ }
+ }
+
+ return *this;
+ }
+
+ /**
+ * @brief Replaces the managed pointer with a new unmanaged pointer.
+ * @param[in] ptr the new raw pointer to manage.
+ */
+ void reset(T *ptr)
+ {
+ // Clean up by decrementing counter
+ decrement_counter();
+
+ if (ptr != NULL) {
+ // Allocate counter on the heap, so it can be shared
+ _counter = new uint32_t;
+ *_counter = 1;
+ }
+ }
+
+ /**
+ * @brief Replace the managed pointer with a NULL pointer.
+ */
+ void reset()
+ {
+ reset(NULL);
+ }
+
+ /**
+ * @brief Raw pointer accessor.
+ * @details Get raw pointer to object pointed to.
+ * @return Pointer.
+ */
+ T *get() const
+ {
+ return _ptr;
+ }
+
+ /**
+ * @brief Reference count accessor.
+ * @return Reference count.
+ */
+ uint32_t use_count() const
+ {
+ if (_ptr != NULL) {
+ core_util_critical_section_enter();
+ uint32_t current_counter = *_counter;
+ core_util_critical_section_exit();
+ return current_counter;
+ } else {
+ return 0;
+ }
+ }
+
+ /**
+ * @brief Dereference object operator.
+ * @details Override to return the object pointed to.
+ */
+ T &operator*() const
+ {
+ return *_ptr;
+ }
+
+ /**
+ * @brief Dereference object member operator.
+ * @details Override to return return member in object pointed to.
+ */
+ T *operator->() const
+ {
+ return _ptr;
+ }
+
+ /**
+ * @brief Boolean conversion operator.
+ * @return Whether or not the pointer is NULL.
+ */
+ operator bool() const
+ {
+ return (_ptr != NULL);
+ }
+
+private:
+ /**
+ * @brief Get pointer to reference counter.
+ * @return Pointer to reference counter.
+ */
+ uint32_t *get_counter() const
+ {
+ return _counter;
+ }
+
+ /**
+ * @brief Decrement reference counter.
+ * @details If count reaches zero, free counter and delete object pointed to.
+ */
+ void decrement_counter()
+ {
+ if (_ptr != NULL) {
+ uint32_t new_value = core_util_atomic_decr_u32(_counter, 1);
+ if (new_value == 0) {
+ delete _counter;
+ _counter = NULL;
+ delete _ptr;
+ _ptr = NULL;
+ }
+ }
+ }
+
+private:
+ // Pointer to shared object
+ T *_ptr;
+
+ // Pointer to shared reference counter
+ uint32_t *_counter;
+};
+
+/** Non-member relational operators.
+ */
+template <class T, class U>
+bool operator== (const SharedPtr<T> &lhs, const SharedPtr<U> &rhs)
+{
+ return (lhs.get() == rhs.get());
+}
+
+template <class T, typename U>
+bool operator== (const SharedPtr<T> &lhs, U rhs)
+{
+ return (lhs.get() == (T *) rhs);
+}
+
+template <class T, typename U>
+bool operator== (U lhs, const SharedPtr<T> &rhs)
+{
+ return ((T *) lhs == rhs.get());
+}
+
+/** Non-member relational operators.
+ */
+template <class T, class U>
+bool operator!= (const SharedPtr<T> &lhs, const SharedPtr<U> &rhs)
+{
+ return (lhs.get() != rhs.get());
+}
+
+template <class T, typename U>
+bool operator!= (const SharedPtr<T> &lhs, U rhs)
+{
+ return (lhs.get() != (T *) rhs);
+}
+
+template <class T, typename U>
+bool operator!= (U lhs, const SharedPtr<T> &rhs)
+{
+ return ((T *) lhs != rhs.get());
+}
+
+#endif // __SHAREDPTR_H__
--- a/platform/SingletonPtr.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/SingletonPtr.h Thu Nov 08 11:46:34 2018 +0000
@@ -43,6 +43,10 @@
inline static void singleton_lock(void)
{
#ifdef MBED_CONF_RTOS_PRESENT
+ if (!singleton_mutex_id) {
+ // RTOS has not booted yet so no mutex is needed
+ return;
+ }
osMutexAcquire(singleton_mutex_id, osWaitForever);
#endif
}
@@ -56,6 +60,10 @@
inline static void singleton_unlock(void)
{
#ifdef MBED_CONF_RTOS_PRESENT
+ if (!singleton_mutex_id) {
+ // RTOS has not booted yet so no mutex is needed
+ return;
+ }
osMutexRelease(singleton_mutex_id);
#endif
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/Span.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1012 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PLATFORM_SPAN_H_
+#define MBED_PLATFORM_SPAN_H_
+
+#include <algorithm>
+#include <stddef.h>
+#include <stdint.h>
+
+#include "platform/mbed_assert.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Span Span class
+ * @{
+ */
+
+// Internal details of Span
+// It is used construct Span from Span of convertible types (non const -> const)
+namespace span_detail {
+
+// If From type is convertible to To type, then the compilation constant value is
+// true; otherwise, it is false.
+template<typename From, typename To>
+class is_convertible
+{
+ struct true_type { char x[512]; };
+ struct false_type { };
+
+ static const From& generator();
+ static true_type sink(const To &);
+ static false_type sink(...);
+
+public:
+ static const bool value = sizeof(true_type) == sizeof(sink(generator()));
+};
+
+}
+
+#if defined(DOXYGEN_ONLY)
+/**
+ * Special value for the Extent parameter of Span.
+ * If the type uses this value, then the size of the array is stored in the object
+ * at runtime.
+ *
+ * @relates Span
+ */
+const ptrdiff_t SPAN_DYNAMIC_EXTENT = -1;
+#else
+#define SPAN_DYNAMIC_EXTENT -1
+#endif
+
+/**
+ * Nonowning view to a sequence of contiguous elements.
+ *
+ * Spans encapsulate a pointer to a sequence of contiguous elements and its size
+ * into a single object. Span can replace the traditional pair of pointer and
+ * size arguments passed as array definitions in function calls.
+ *
+ * @par Operations
+ *
+ * Span objects can be copied and assigned like regular value types with the help
+ * of the copy constructor or the copy assignment (=) operator.
+ *
+ * You can retrieve elements of the object with the subscript ([]) operator. You can access the
+ * pointer to the first element of the sequence viewed with data().
+ * The function size() returns the number of elements in the sequence, and
+ * empty() informs whether there is any element in the sequence.
+ *
+ * You can slice Span from the beginning of the sequence (first()), from the end
+ * of the sequence (last()) or from an arbitrary point of the sequence (subspan()).
+ *
+ * @par Size encoding
+ *
+ * The size of the sequence can be encoded in the type itself or in the value of
+ * the instance with the help of the template parameter Extent:
+ *
+ * - Span<uint8_t, 6>: Span over a sequence of 6 elements.
+ * - Span<uint8_t>: Span over an arbitrary long sequence.
+ *
+ * When the size is encoded in the type itself, it is guaranteed that the Span
+ * view is a valid sequence (not empty() and not NULL) - unless Extent equals 0.
+ * The type system also prevents automatic conversion from Span of different
+ * sizes. Finally, the Span object is internally represented as a single pointer.
+ *
+ * When the size of the sequence viewed is encoded in the Span value, Span
+ * instances can view an empty sequence. The function empty() helps client code
+ * decide whether Span is viewing valid content or not.
+ *
+ * @par Example
+ *
+ * - Encoding fixed size array: Array values in parameter decays automatically
+ * to pointer, which leaves room for subtitle bugs:
+ *
+ * @code
+ typedef uint8_t mac_address_t[6];
+ void process_mac(mac_address_t);
+
+ // compile just fine
+ uint8_t *invalid_value = NULL;
+ process_mac(invalid_value);
+
+
+ // correct way
+ typedef Span<uint8_t, 6> mac_address_t;
+ void process_mac(mac_address_t);
+
+ // compilation error
+ uint8_t *invalid_value = NULL;
+ process_mac(invalid_value);
+
+ // compilation ok
+ uint8_t valid_value[6];
+ process_mac(valid_value);
+ * @endcode
+ *
+ * - Arbitrary buffer: When dealing with multiple buffers, it becomes painful to
+ * keep track of every buffer size and pointer.
+ *
+ * @code
+ const uint8_t options_tag[OPTIONS_TAG_SIZE];
+
+ struct parsed_value_t {
+ uint8_t *header;
+ uint8_t *options;
+ uint8_t *payload;
+ size_t payload_size;
+ }
+
+ parsed_value_t parse(uint8_t *buffer, size_t buffer_size)
+ {
+ parsed_value_t parsed_value { 0 };
+
+ if (buffer != NULL && buffer_size <= MINIMAL_BUFFER_SIZE) {
+ return parsed_value;
+ }
+
+ parsed_value.header = buffer;
+ parsed_value.header_size = BUFFER_HEADER_SIZE;
+
+ if (memcmp(buffer + HEADER_OPTIONS_INDEX, options_tag, sizeof(options_tag)) == 0) {
+ options = buffer + BUFFER_HEADER_SIZE;
+ payload = buffer + BUFFER_HEADER_SIZE + OPTIONS_SIZE;
+ payload_size = buffer_size - BUFFER_HEADER_SIZE + OPTIONS_SIZE;
+ } else {
+ payload = buffer + BUFFER_HEADER_SIZE;
+ payload_size = buffer_size - BUFFER_HEADER_SIZE;
+ }
+
+ return parsed_value;
+ }
+
+
+ //with Span
+ struct parsed_value_t {
+ Span<uint8_t> header;
+ Span<uint8_t> options;
+ Span<uint8_t> payload;
+ }
+
+ parsed_value_t parse(const Span<uint8_t> &buffer)
+ {
+ parsed_value_t parsed_value;
+
+ if (buffer.size() <= MINIMAL_BUFFER_SIZE) {
+ return parsed_value;
+ }
+
+ parsed_value.header = buffer.first(BUFFER_HEADER_SIZE);
+
+ if (buffer.subspan<HEADER_OPTIONS_INDEX, sizeof(options_tag)>() == option_tag) {
+ options = buffer.supspan(parsed_value.header.size(), OPTIONS_SIZE);
+ }
+
+ payload = buffer.subspan(parsed_value.header.size() + parsed_value.options.size());
+
+ return parsed_value;
+ }
+ * @endcode
+ *
+ * @note You can create Span instances with the help of the function template
+ * make_Span() and make_const_Span().
+ *
+ * @note Span<T, Extent> objects can be implicitly converted to Span<T> objects
+ * where required.
+ *
+ * @tparam ElementType type of objects the Span views.
+ *
+ * @tparam Extent The size of the contiguous sequence viewed. The default value
+ * SPAN_DYNAMIC_SIZE is special because it allows construction of Span objects of
+ * any size (set at runtime).
+ */
+template<typename ElementType, ptrdiff_t Extent = SPAN_DYNAMIC_EXTENT>
+struct Span {
+
+ /**
+ * Type of the element contained
+ */
+ typedef ElementType element_type;
+
+ /**
+ * Type of the index.
+ */
+ typedef ptrdiff_t index_type;
+
+ /**
+ * Pointer to an ElementType
+ */
+ typedef element_type *pointer;
+
+ /**
+ * Reference to an ElementType
+ */
+ typedef element_type &reference;
+
+ /**
+ * Size of the Extent; -1 if dynamic.
+ */
+ static const index_type extent = Extent;
+
+ MBED_STATIC_ASSERT(Extent >= 0, "Invalid extent for a Span");
+
+ /**
+ * Construct an empty Span.
+ *
+ * @post a call to size() returns 0, and data() returns NULL.
+ *
+ * @note This function is not accessible if Extent != SPAN_DYNAMIC_EXTENT or
+ * Extent != 0 .
+ */
+ Span() :
+ _data(NULL)
+ {
+ MBED_STATIC_ASSERT(
+ Extent == 0,
+ "Cannot default construct a static-extent Span (unless Extent is 0)"
+ );
+ }
+
+ /**
+ * Construct a Span from a pointer to a buffer and its size.
+ *
+ * @param ptr Pointer to the beginning of the data viewed.
+ *
+ * @param count Number of elements viewed.
+ *
+ * @pre [ptr, ptr + count) must be be a valid range.
+ * @pre count must be equal to Extent.
+ *
+ * @post a call to size() returns Extent, and data() returns @p ptr.
+ */
+ Span(pointer ptr, index_type count) :
+ _data(ptr)
+ {
+ MBED_ASSERT(count == Extent);
+ MBED_ASSERT(Extent == 0 || ptr != NULL);
+ }
+
+ /**
+ * Construct a Span from the range [first, last).
+ *
+ * @param first Pointer to the beginning of the data viewed.
+ * @param last End of the range (element after the last element).
+ *
+ * @pre [first, last) must be be a valid range.
+ * @pre first <= last.
+ * @pre last - first must be equal to Extent.
+ *
+ * @post a call to size() returns Extent, and data() returns @p first.
+ */
+ Span(pointer first, pointer last) :
+ _data(first)
+ {
+ MBED_ASSERT(first <= last);
+ MBED_ASSERT((last - first) == Extent);
+ MBED_ASSERT(Extent == 0 || first != NULL);
+ }
+
+ /**
+ * Construct a Span from the reference to an array.
+ *
+ * @param elements Reference to the array viewed.
+ *
+ * @post a call to size() returns Extent, and data() returns a
+ * pointer to elements.
+ */
+ Span(element_type (&elements)[Extent]):
+ _data(elements) { }
+
+ /**
+ * Construct a Span object from another Span of the same size.
+ *
+ * @param other The Span object used to construct this.
+ *
+ * @note For Span with a positive extent, this function is not accessible.
+ *
+ * @note OtherElementType(*)[] must be convertible to ElementType(*)[].
+ */
+ template<typename OtherElementType>
+ Span(const Span<OtherElementType, Extent> &other):
+ _data(other.data())
+ {
+ MBED_STATIC_ASSERT(
+ (span_detail::is_convertible<OtherElementType (*)[1], ElementType (*)[1]>::value),
+ "OtherElementType(*)[] should be convertible to ElementType (*)[]"
+ );
+ }
+
+ /**
+ * Return the size of the sequence viewed.
+ *
+ * @return The size of the sequence viewed.
+ */
+ index_type size() const
+ {
+ return Extent;
+ }
+
+ /**
+ * Return if the sequence is empty or not.
+ *
+ * @return true if the sequence is empty and false otherwise.
+ */
+ bool empty() const
+ {
+ return size() == 0;
+ }
+
+ /**
+ * Returns a reference to the element at position @p index.
+ *
+ * @param index Index of the element to access.
+ *
+ * @return A reference to the element at the index specified in input.
+ *
+ * @pre 0 <= index < Extent.
+ */
+ reference operator[](index_type index) const
+ {
+#ifdef MBED_DEBUG
+ MBED_ASSERT(0 <= index && index < Extent);
+#endif
+ return _data[index];
+ }
+
+ /**
+ * Return a pointer to the first element of the sequence or NULL if the Span
+ * is empty().
+ *
+ * @return The pointer to the first element of the Span.
+ */
+ pointer data() const
+ {
+ return _data;
+ }
+
+ /**
+ * Create a new Span over the first @p Count elements of the existing view.
+ *
+ * @tparam Count The number of element viewed by the new Span
+ *
+ * @return A new Span over the first @p Count elements.
+ *
+ * @pre Count >= 0 && Count <= size().
+ */
+ template<ptrdiff_t Count>
+ Span<element_type, Count> first() const
+ {
+ MBED_STATIC_ASSERT(
+ (0 <= Count) && (Count <= Extent),
+ "Invalid subspan extent"
+ );
+ return Span<element_type, Count>(_data, Count);
+ }
+
+ /**
+ * Create a new Span over the last @p Count elements of the existing view.
+ *
+ * @tparam Count The number of element viewed by the new Span.
+ *
+ * @return A new Span over the last @p Count elements.
+ *
+ * @pre Count >= 0 && Count <= size().
+ */
+ template<ptrdiff_t Count>
+ Span<element_type, Count> last() const
+ {
+ MBED_STATIC_ASSERT(
+ (0 <= Count) && (Count <= Extent),
+ "Invalid subspan extent"
+ );
+ return Span<element_type, Count>(_data + (Extent - Count), Count);
+ }
+
+ /**
+ * Create a subspan that is a view of other Count elements; the view starts at
+ * element Offset.
+ *
+ * @tparam Offset The offset of the first element viewed by the subspan.
+ *
+ * @tparam Count The number of elements present in the subspan. If Count
+ * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
+ * containing the rest of the elements is returned.
+ *
+ * @return A subspan of this starting at Offset and Count long.
+ */
+ template<std::ptrdiff_t Offset, std::ptrdiff_t Count>
+ Span<element_type, Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count>
+ subspan() const
+ {
+ MBED_STATIC_ASSERT(
+ 0 <= Offset && Offset <= Extent,
+ "Invalid subspan offset"
+ );
+ MBED_STATIC_ASSERT(
+ (Count == SPAN_DYNAMIC_EXTENT) ||
+ (0 <= Count && (Count + Offset) <= Extent),
+ "Invalid subspan count"
+ );
+ return Span<element_type, Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count>(
+ _data + Offset,
+ Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count
+ );
+ }
+
+ /**
+ * Create a new Span over the first @p count elements of the existing view.
+ *
+ * @param count The number of element viewed by the new Span.
+ *
+ * @return A new Span over the first @p count elements.
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> first(index_type count) const
+ {
+ MBED_ASSERT(0 <= count && count <= Extent);
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(_data, count);
+ }
+
+ /**
+ * Create a new Span over the last @p count elements of the existing view.
+ *
+ * @param count The number of elements viewed by the new Span.
+ *
+ * @return A new Span over the last @p count elements.
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> last(index_type count) const
+ {
+ MBED_ASSERT(0 <= count && count <= Extent);
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(
+ _data + (Extent - count),
+ count
+ );
+ }
+
+ /**
+ * Create a subspan that is a view of other count elements; the view starts at
+ * element offset.
+ *
+ * @param offset The offset of the first element viewed by the subspan.
+ *
+ * @param count The number of elements present in the subspan. If Count
+ * is equal to SPAN_DYNAMIC_EXTENT, then a span starting at offset and
+ * containing the rest of the elements is returned.
+ *
+ * @return
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> subspan(
+ index_type offset, index_type count = SPAN_DYNAMIC_EXTENT
+ ) const
+ {
+ MBED_ASSERT(0 <= offset && offset <= Extent);
+ MBED_ASSERT(
+ (count == SPAN_DYNAMIC_EXTENT) ||
+ (0 <= count && (count + offset) <= Extent)
+ );
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(
+ _data + offset,
+ count == SPAN_DYNAMIC_EXTENT ? Extent - offset : count
+ );
+ }
+
+private:
+ pointer _data;
+};
+
+/**
+ * Span specialization that handle dynamic size.
+ */
+template<typename ElementType>
+struct Span<ElementType, SPAN_DYNAMIC_EXTENT> {
+ /**
+ * Type of the element contained.
+ */
+ typedef ElementType element_type;
+
+ /**
+ * Type of the index.
+ */
+ typedef ptrdiff_t index_type;
+
+ /**
+ * Pointer to an ElementType.
+ */
+ typedef element_type *pointer;
+
+ /**
+ * Reference to an ElementType.
+ */
+ typedef element_type &reference;
+
+ /**
+ * Size of the Extent; -1 if dynamic.
+ */
+ static const index_type extent = SPAN_DYNAMIC_EXTENT;
+
+ /**
+ * Construct an empty Span.
+ *
+ * @post a call to size() returns 0, and data() returns NULL.
+ *
+ * @note This function is not accessible if Extent != SPAN_DYNAMIC_EXTENT or
+ * Extent != 0 .
+ */
+ Span() :
+ _data(NULL), _size(0) { }
+
+ /**
+ * Construct a Span from a pointer to a buffer and its size.
+ *
+ * @param ptr Pointer to the beginning of the data viewed.
+ *
+ * @param count Number of elements viewed.
+ *
+ * @pre [ptr, ptr + count) must be be a valid range.
+ * @pre count must be equal to extent.
+ *
+ * @post a call to size() returns count, and data() returns @p ptr.
+ */
+ Span(pointer ptr, index_type count) :
+ _data(ptr), _size(count)
+ {
+ MBED_ASSERT(count >= 0);
+ MBED_ASSERT(ptr != NULL || count == 0);
+ }
+
+ /**
+ * Construct a Span from the range [first, last).
+ *
+ * @param first Pointer to the beginning of the data viewed.
+ * @param last End of the range (element after the last element).
+ *
+ * @pre [first, last) must be be a valid range.
+ * @pre first <= last.
+ *
+ * @post a call to size() returns the result of (last - first), and
+ * data() returns @p first.
+ */
+ Span(pointer first, pointer last) :
+ _data(first), _size(last - first)
+ {
+ MBED_ASSERT(first <= last);
+ MBED_ASSERT(first != NULL || (last - first) == 0);
+ }
+
+ /**
+ * Construct a Span from the reference to an array.
+ *
+ * @param elements Reference to the array viewed.
+ *
+ * @tparam Count Number of elements of T presents in the array.
+ *
+ * @post a call to size() returns Count, and data() returns a
+ * pointer to elements.
+ */
+ template<size_t Count>
+ Span(element_type (&elements)[Count]):
+ _data(elements), _size(Count) { }
+
+ /**
+ * Construct a Span object from another Span.
+ *
+ * @param other The Span object used to construct this.
+ *
+ * @note For Span with a positive extent, this function is not accessible.
+ *
+ * @note OtherElementType(*)[] must be convertible to ElementType(*)[].
+ */
+ template<typename OtherElementType, ptrdiff_t OtherExtent>
+ Span(const Span<OtherElementType, OtherExtent> &other):
+ _data(other.data()), _size(other.size())
+ {
+ MBED_STATIC_ASSERT(
+ (span_detail::is_convertible<OtherElementType (*)[1], ElementType (*)[1]>::value),
+ "OtherElementType(*)[] should be convertible to ElementType (*)[]"
+ );
+ }
+
+ /**
+ * Return the size of the array viewed.
+ *
+ * @return The number of elements present in the array viewed.
+ */
+ index_type size() const
+ {
+ return _size;
+ }
+
+ /**
+ * Return if the sequence viewed is empty or not.
+ *
+ * @return true if the sequence is empty and false otherwise.
+ */
+ bool empty() const
+ {
+ return size() == 0;
+ }
+
+ /**
+ * Access to an element of the sequence.
+ *
+ * @param index Element index to access.
+ *
+ * @return A reference to the element at the index specified in input.
+ *
+ * @pre index is less than size().
+ */
+ reference operator[](index_type index) const
+ {
+#ifdef MBED_DEBUG
+ MBED_ASSERT(0 <= index && index < _size);
+#endif
+ return _data[index];
+ }
+
+ /**
+ * Get the raw pointer to the sequence viewed.
+ *
+ * @return The raw pointer to the first element viewed.
+ */
+ pointer data() const
+ {
+ return _data;
+ }
+
+ /**
+ * Create a new Span over the first @p Count elements of the existing view.
+ *
+ * @tparam Count The number of elements viewed by the new Span.
+ *
+ * @return A new Span over the first @p Count elements.
+ *
+ * @pre Count >= 0 && Count <= size().
+ */
+ template<ptrdiff_t Count>
+ Span<element_type, Count> first() const
+ {
+ MBED_ASSERT((Count >= 0) && (Count <= _size));
+ return Span<element_type, Count>(_data, Count);
+ }
+
+ /**
+ * Create a new Span over the last @p Count elements of the existing view.
+ *
+ * @tparam Count The number of elements viewed by the new Span.
+ *
+ * @return A new Span over the last @p Count elements.
+ *
+ * @pre Count >= 0 && Count <= size().
+ */
+ template<ptrdiff_t Count>
+ Span<element_type, Count> last() const
+ {
+ MBED_ASSERT((0 <= Count) && (Count <= _size));
+ return Span<element_type, Count>(_data + (_size - Count), Count);
+ }
+
+ /**
+ * Create a subspan that is a view other Count elements; the view starts at
+ * element Offset.
+ *
+ * @tparam Offset The offset of the first element viewed by the subspan.
+ *
+ * @tparam Count The number of elements present in the subspan. If Count
+ * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
+ * containing the rest of the elements is returned.
+ *
+ * @return A subspan of this starting at Offset and Count long.
+ */
+ template<std::ptrdiff_t Offset, std::ptrdiff_t Count>
+ Span<element_type, Count>
+ subspan() const
+ {
+ MBED_ASSERT(0 <= Offset && Offset <= _size);
+ MBED_ASSERT(
+ (Count == SPAN_DYNAMIC_EXTENT) ||
+ (0 <= Count && (Count + Offset) <= _size)
+ );
+ return Span<element_type, Count>(
+ _data + Offset,
+ Count == SPAN_DYNAMIC_EXTENT ? _size - Offset : Count
+ );
+ }
+
+ /**
+ * Create a new Span over the first @p count elements of the existing view.
+ *
+ * @param count The number of elements viewed by the new Span.
+ *
+ * @return A new Span over the first @p count elements.
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> first(index_type count) const
+ {
+ MBED_ASSERT(0 <= count && count <= _size);
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(_data, count);
+ }
+
+ /**
+ * Create a new Span over the last @p count elements of the existing view.
+ *
+ * @param count The number of elements viewed by the new Span.
+ *
+ * @return A new Span over the last @p count elements.
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> last(index_type count) const
+ {
+ MBED_ASSERT(0 <= count && count <= _size);
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(
+ _data + (_size - count),
+ count
+ );
+ }
+
+ /**
+ * Create a subspan that is a view of other count elements; the view starts at
+ * element offset.
+ *
+ * @param offset The offset of the first element viewed by the subspan.
+ *
+ * @param count The number of elements present in the subspan. If Count
+ * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
+ * containing the rest of the elements is returned.
+ *
+ * @return A subspan of this starting at offset and count long.
+ */
+ Span<element_type, SPAN_DYNAMIC_EXTENT> subspan(
+ index_type offset, index_type count = SPAN_DYNAMIC_EXTENT
+ ) const
+ {
+ MBED_ASSERT(0 <= offset && offset <= _size);
+ MBED_ASSERT(
+ (count == SPAN_DYNAMIC_EXTENT) ||
+ (0 <= count && (count + offset) <= _size)
+ );
+ return Span<element_type, SPAN_DYNAMIC_EXTENT>(
+ _data + offset,
+ count == SPAN_DYNAMIC_EXTENT ? _size - offset : count
+ );
+ }
+
+private:
+ pointer _data;
+ index_type _size;
+};
+
+/**
+ * Equality operator between two Span objects.
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if Spans in input have the same size and the same content and
+ * false otherwise.
+ *
+ * @relates Span
+ */
+template<typename T, typename U, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator==(const Span<T, LhsExtent> &lhs, const Span<U, RhsExtent> &rhs)
+{
+ if (lhs.size() != rhs.size()) {
+ return false;
+ }
+
+ if (lhs.data() == rhs.data()) {
+ return true;
+ }
+
+ return std::equal(lhs.data(), lhs.data() + lhs.size(), rhs.data());
+}
+
+/**
+ * Equality operation between a Span and a reference to a C++ array.
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if elements in input have the same size and the same content and
+ * false otherwise.
+ */
+template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator==(const Span<T, LhsExtent> &lhs, T (&rhs)[RhsExtent])
+{
+ return lhs == Span<T>(rhs);
+}
+
+/**
+ * Equality operation between a Span and a reference to a C++ array.
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if elements in input have the same size and the same content
+ * and false otherwise.
+ */
+template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator==(T (&lhs)[LhsExtent], const Span<T, RhsExtent> &rhs)
+{
+ return Span<T>(lhs) == rhs;
+}
+
+/**
+ * Not equal operator
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if arrays in input do not have the same size or the same content
+ * and false otherwise.
+ *
+ * @relates Span
+ */
+template<typename T, typename U, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator!=(const Span<T, LhsExtent> &lhs, const Span<U, RhsExtent> &rhs)
+{
+ return !(lhs == rhs);
+}
+
+/**
+ * Not Equal operation between a Span and a reference to a C++ array.
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if elements in input have the same size and the same content
+ * and false otherwise.
+ */
+template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator!=(const Span<T, LhsExtent> &lhs, T (&rhs)[RhsExtent])
+{
+ return !(lhs == Span<T, RhsExtent>(rhs));
+}
+
+/**
+ * Not Equal operation between a Span and a reference to a C++ array.
+ *
+ * @param lhs Left side of the binary operation.
+ * @param rhs Right side of the binary operation.
+ *
+ * @return True if elements in input have the same size and the same content
+ * and false otherwise.
+ */
+template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
+bool operator!=(T (&lhs)[LhsExtent], const Span<T, RhsExtent> &rhs)
+{
+ return !(Span<T, LhsExtent>(lhs) == rhs);
+}
+
+/**
+ * Generate a Span from a reference to a C/C++ array.
+ *
+ * @tparam T Type of elements held in elements.
+ * @tparam Extent Number of items held in elements.
+ *
+ * @param elements The reference to the array viewed.
+ *
+ * @return The Span to elements.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ *
+ * @relates Span
+ */
+template<typename T, size_t Size>
+Span<T, Size> make_Span(T (&elements)[Size])
+{
+ return Span<T, Size>(elements);
+}
+
+/**
+ * Generate a Span from a pointer to a C/C++ array.
+ *
+ * @tparam Extent Number of items held in elements.
+ * @tparam T Type of elements held in elements.
+ *
+ * @param elements The reference to the array viewed.
+ *
+ * @return The Span to elements.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ */
+template<ptrdiff_t Extent, typename T>
+Span<T, Extent> make_Span(T *elements)
+{
+ return Span<T, Extent>(elements, Extent);
+}
+
+/**
+ * Generate a Span from a C/C++ pointer and the size of the array.
+ *
+ * @tparam T Type of elements held in array_ptr.
+ *
+ * @param array_ptr The pointer to the array viewed.
+ * @param array_size The number of T elements in the array.
+ *
+ * @return The Span to array_ptr with a size of array_size.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ *
+ * @relates Span
+ */
+template<typename T>
+Span<T> make_Span(T *array_ptr, ptrdiff_t array_size)
+{
+ return Span<T>(array_ptr, array_size);
+}
+
+/**
+ * Generate a Span to a const content from a reference to a C/C++ array.
+ *
+ * @tparam T Type of elements held in elements.
+ * @tparam Extent Number of items held in elements.
+ *
+ * @param elements The array viewed.
+ * @return The Span to elements.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ */
+template<typename T, size_t Extent>
+Span<const T, Extent> make_const_Span(const T (&elements)[Extent])
+{
+ return Span<const T, Extent>(elements);
+}
+
+/**
+ * Generate a Span to a const content from a pointer to a C/C++ array.
+ *
+ * @tparam Extent Number of items held in elements.
+ * @tparam T Type of elements held in elements.
+ *
+ * @param elements The reference to the array viewed.
+ *
+ * @return The Span to elements.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ *
+ * @relates Span
+ */
+template<size_t Extent, typename T>
+Span<const T, Extent> make_const_Span(const T *elements)
+{
+ return Span<const T, Extent>(elements, Extent);
+}
+
+/**
+ * Generate a Span to a const content from a C/C++ pointer and the size of the
+ * array.
+ *
+ * @tparam T Type of elements held in array_ptr.
+ *
+ * @param array_ptr The pointer to the array to viewed.
+ * @param array_size The number of T elements in the array.
+ *
+ * @return The Span to array_ptr with a size of array_size.
+ *
+ * @note This helper avoids the typing of template parameter when Span is
+ * created 'inline'.
+ *
+ * @relates Span
+ */
+template<typename T>
+Span<const T> make_const_Span(T *array_ptr, size_t array_size)
+{
+ return Span<const T>(array_ptr, array_size);
+}
+
+/**@}*/
+
+/**@}*/
+
+} // namespace mbed
+
+#endif /* MBED_PLATFORM_SPAN_H_ */
--- a/platform/mbed_alloc_wrappers.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_alloc_wrappers.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -30,7 +30,7 @@
activated by defining the MBED_HEAP_STATS_ENABLED macro.
- the second can be used to trace each memory call by automatically invoking
a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
- activated by defining the MBED_MEM_TRACING_ENABLED macro.
+ activated by setting the configuration option MBED_MEM_TRACING_ENABLED to true.
Both tracers can be activated and deactivated in any combination. If both tracers
are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
@@ -40,15 +40,24 @@
/* Implementation of the runtime max heap usage checker */
/******************************************************************************/
-/* Size must be a multiple of 8 to keep alignment */
typedef struct {
uint32_t size;
- uint32_t pad;
+ uint32_t signature;
} alloc_info_t;
#ifdef MBED_HEAP_STATS_ENABLED
+#define MBED_HEAP_STATS_SIGNATURE (0xdeadbeef)
+
static SingletonPtr<PlatformMutex> malloc_stats_mutex;
-static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0, 0, 0};
+
+typedef struct {
+ size_t size;
+}mbed_heap_overhead_t;
+
+#define MALLOC_HEADER_SIZE (sizeof(mbed_heap_overhead_t))
+#define MALLOC_HEADER_PTR(p) (mbed_heap_overhead_t *)((char *)(p) - MALLOC_HEADER_SIZE)
+#define MALLOC_HEAP_TOTAL_SIZE(p) (((p)->size) & (~0x1))
#endif
void mbed_stats_heap_get(mbed_stats_heap_t *stats)
@@ -71,10 +80,6 @@
#if defined(TOOLCHAIN_GCC)
-#ifdef FEATURE_UVISOR
-#include "uvisor-lib/uvisor-lib.h"
-#endif/* FEATURE_UVISOR */
-
extern "C" {
void *__real__malloc_r(struct _reent *r, size_t size);
void *__real__memalign_r(struct _reent *r, size_t alignment, size_t bytes);
@@ -85,8 +90,6 @@
void free_wrapper(struct _reent *r, void *ptr, void *caller);
}
-// TODO: memory tracing doesn't work with uVisor enabled.
-#if !defined(FEATURE_UVISOR)
extern "C" void *__wrap__malloc_r(struct _reent *r, size_t size)
{
@@ -96,7 +99,7 @@
extern "C" void *malloc_wrapper(struct _reent *r, size_t size, void *caller)
{
void *ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -104,6 +107,7 @@
alloc_info_t *alloc_info = (alloc_info_t *)__real__malloc_r(r, size + sizeof(alloc_info_t));
if (alloc_info != NULL) {
alloc_info->size = size;
+ alloc_info->signature = MBED_HEAP_STATS_SIGNATURE;
ptr = (void *)(alloc_info + 1);
heap_stats.current_size += size;
heap_stats.total_size += size;
@@ -111,6 +115,7 @@
if (heap_stats.current_size > heap_stats.max_size) {
heap_stats.max_size = heap_stats.current_size;
}
+ heap_stats.overhead_size += MALLOC_HEAP_TOTAL_SIZE(MALLOC_HEADER_PTR(alloc_info)) - size;
} else {
heap_stats.alloc_fail_cnt += 1;
}
@@ -118,17 +123,17 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
ptr = __real__malloc_r(r, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_malloc(ptr, size, caller);
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return ptr;
}
extern "C" void *__wrap__realloc_r(struct _reent *r, void *ptr, size_t size)
{
void *new_ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -161,10 +166,10 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
new_ptr = __real__realloc_r(r, ptr, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return new_ptr;
}
@@ -175,7 +180,7 @@
extern "C" void free_wrapper(struct _reent *r, void *ptr, void *caller)
{
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -183,24 +188,33 @@
alloc_info_t *alloc_info = NULL;
if (ptr != NULL) {
alloc_info = ((alloc_info_t *)ptr) - 1;
- heap_stats.current_size -= alloc_info->size;
- heap_stats.alloc_cnt -= 1;
+ if (MBED_HEAP_STATS_SIGNATURE == alloc_info->signature) {
+ size_t user_size = alloc_info->size;
+ size_t alloc_size = MALLOC_HEAP_TOTAL_SIZE(MALLOC_HEADER_PTR(alloc_info));
+ alloc_info->signature = 0x0;
+ heap_stats.current_size -= user_size;
+ heap_stats.alloc_cnt -= 1;
+ heap_stats.overhead_size -= (alloc_size - user_size);
+ __real__free_r(r, (void *)alloc_info);
+ } else {
+ __real__free_r(r, ptr);
+ }
}
- __real__free_r(r, (void *)alloc_info);
+
malloc_stats_mutex->unlock();
#else // #ifdef MBED_HEAP_STATS_ENABLED
__real__free_r(r, ptr);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_free(ptr, caller);
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
}
extern "C" void *__wrap__calloc_r(struct _reent *r, size_t nmemb, size_t size)
{
void *ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -213,10 +227,10 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
ptr = __real__calloc_r(r, nmemb, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return ptr;
}
@@ -225,8 +239,6 @@
return __real__memalign_r(r, alignment, bytes);
}
-#endif // if !defined(FEATURE_UVISOR)
-
/******************************************************************************/
/* ARMCC / IAR memory allocation wrappers */
@@ -266,7 +278,6 @@
void free_wrapper(void *ptr, void *caller);
}
-
extern "C" void *SUB_MALLOC(size_t size)
{
return malloc_wrapper(size, MBED_CALLER_ADDR());
@@ -275,7 +286,7 @@
extern "C" void *malloc_wrapper(size_t size, void *caller)
{
void *ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -283,6 +294,7 @@
alloc_info_t *alloc_info = (alloc_info_t *)SUPER_MALLOC(size + sizeof(alloc_info_t));
if (alloc_info != NULL) {
alloc_info->size = size;
+ alloc_info->signature = MBED_HEAP_STATS_SIGNATURE;
ptr = (void *)(alloc_info + 1);
heap_stats.current_size += size;
heap_stats.total_size += size;
@@ -290,6 +302,7 @@
if (heap_stats.current_size > heap_stats.max_size) {
heap_stats.max_size = heap_stats.current_size;
}
+ heap_stats.overhead_size += MALLOC_HEAP_TOTAL_SIZE(MALLOC_HEADER_PTR(alloc_info)) - size;
} else {
heap_stats.alloc_fail_cnt += 1;
}
@@ -297,10 +310,10 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
ptr = SUPER_MALLOC(size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_malloc(ptr, size, caller);
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return ptr;
}
@@ -308,7 +321,7 @@
extern "C" void *SUB_REALLOC(void *ptr, size_t size)
{
void *new_ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -328,7 +341,7 @@
// If the new buffer has been allocated copy the data to it
// and free the old buffer
- if (new_ptr != NULL) {
+ if ((new_ptr != NULL) && (ptr != NULL)) {
uint32_t copy_size = (old_size < size) ? old_size : size;
memcpy(new_ptr, (void *)ptr, copy_size);
free(ptr);
@@ -336,17 +349,17 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
new_ptr = SUPER_REALLOC(ptr, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return new_ptr;
}
extern "C" void *SUB_CALLOC(size_t nmemb, size_t size)
{
void *ptr = NULL;
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -358,10 +371,10 @@
#else // #ifdef MBED_HEAP_STATS_ENABLED
ptr = SUPER_CALLOC(nmemb, size);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
return ptr;
}
@@ -372,7 +385,7 @@
extern "C" void free_wrapper(void *ptr, void *caller)
{
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_lock();
#endif
#ifdef MBED_HEAP_STATS_ENABLED
@@ -380,18 +393,27 @@
alloc_info_t *alloc_info = NULL;
if (ptr != NULL) {
alloc_info = ((alloc_info_t *)ptr) - 1;
- heap_stats.current_size -= alloc_info->size;
- heap_stats.alloc_cnt -= 1;
+ if (MBED_HEAP_STATS_SIGNATURE == alloc_info->signature) {
+ size_t user_size = alloc_info->size;
+ size_t alloc_size = MALLOC_HEAP_TOTAL_SIZE(MALLOC_HEADER_PTR(alloc_info));
+ alloc_info->signature = 0x0;
+ heap_stats.current_size -= user_size;
+ heap_stats.alloc_cnt -= 1;
+ heap_stats.overhead_size -= (alloc_size - user_size);
+ SUPER_FREE((void *)alloc_info);
+ } else {
+ SUPER_FREE(ptr);
+ }
}
- SUPER_FREE((void *)alloc_info);
+
malloc_stats_mutex->unlock();
#else // #ifdef MBED_HEAP_STATS_ENABLED
SUPER_FREE(ptr);
#endif // #ifdef MBED_HEAP_STATS_ENABLED
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
mbed_mem_trace_free(ptr, caller);
mbed_mem_trace_unlock();
-#endif // #ifdef MBED_MEM_TRACING_ENABLED
+#endif // #if MBED_MEM_TRACING_ENABLED
}
#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
@@ -402,7 +424,7 @@
#else
-#ifdef MBED_MEM_TRACING_ENABLED
+#if MBED_MEM_TRACING_ENABLED
#error Memory tracing is not supported with the current toolchain.
#endif
--- a/platform/mbed_assert.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_assert.h Thu Nov 08 11:46:34 2018 +0000
@@ -29,11 +29,11 @@
extern "C" {
#endif
-/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro fails.
* This function is active only if NDEBUG is not defined prior to including this
* assert header file.
* In case of MBED_ASSERT failing condition, error() is called with the assertation message.
- * @param expr Expresion to be checked.
+ * @param expr Expression to be checked.
* @param file File where assertation failed.
* @param line Failing assertation line number.
*/
--- a/platform/mbed_critical.c Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_critical.c Thu Nov 08 11:46:34 2018 +0000
@@ -77,13 +77,8 @@
void core_util_critical_section_enter(void)
{
-// FIXME
-#ifdef FEATURE_UVISOR
-#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
-#else
// If the reentrancy counter overflows something has gone badly wrong.
MBED_ASSERT(critical_section_reentrancy_counter < UINT32_MAX);
-#endif /* FEATURE_UVISOR */
hal_critical_section_enter();
@@ -92,10 +87,6 @@
void core_util_critical_section_exit(void)
{
-// FIXME
-#ifdef FEATURE_UVISOR
-#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
-#endif /* FEATURE_UVISOR */
// If critical_section_enter has not previously been called, do nothing
if (critical_section_reentrancy_counter == 0) {
--- a/platform/mbed_critical.h Thu Sep 06 13:40:20 2018 +0100 +++ b/platform/mbed_critical.h Thu Nov 08 11:46:34 2018 +0000 @@ -39,7 +39,7 @@ * This function can be called to determine whether or not interrupts are currently enabled. * @note * NOTE: - * This function works for both cortex-A and cortex-M, although the underlyng implementation + * This function works for both cortex-A and cortex-M, although the underlying implementation * differs. * @return true if interrupts are enabled, false otherwise */ @@ -50,7 +50,7 @@ * This function can be called to determine if the code is running on interrupt context. * @note * NOTE: - * This function works for both cortex-A and cortex-M, although the underlyng implementation + * This function works for both cortex-A and cortex-M, although the underlying implementation * differs. * @return true if in an isr, false otherwise */
--- a/platform/mbed_error.c Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_error.c Thu Nov 08 11:46:34 2018 +0000
@@ -120,7 +120,7 @@
error_count++;
//Clear the context capturing buffer
- memset(¤t_error_ctx, sizeof(mbed_error_ctx), 0);
+ memset(¤t_error_ctx, 0, sizeof(mbed_error_ctx));
//Capture error information
current_error_ctx.error_status = error_status;
current_error_ctx.error_address = (uint32_t)caller;
@@ -279,7 +279,7 @@
//Make sure we dont multiple clients resetting
core_util_critical_section_enter();
//Clear the error and context capturing buffer
- memset(&last_error_ctx, sizeof(mbed_error_ctx), 0);
+ memset(&last_error_ctx, 0, sizeof(mbed_error_ctx));
//reset error count to 0
error_count = 0;
#if MBED_CONF_PLATFORM_ERROR_HIST_ENABLED
@@ -389,7 +389,7 @@
threads = (osRtxThread_t *)&osRtxInfo.thread.idle;
print_threads_info(threads);
#endif
-
+ mbed_error_printf(MBED_CONF_PLATFORM_ERROR_DECODE_HTTP_URL_STR, ctx->error_status);
mbed_error_printf("\n-- MbedOS Error Info --\n");
}
#endif //ifndef NDEBUG
--- a/platform/mbed_error.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_error.h Thu Nov 08 11:46:34 2018 +0000
@@ -90,7 +90,7 @@
* System Error Status-es - 0x80XX0100 to 0x80XX0FFF - This corresponds to System error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n
* Custom Error Status-es - 0xA0XX1000 to 0xA0XXFFFF - This corresponds to Custom error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n\n
*
- * The ERROR CODE(values encoded into ERROR CODE bit-field in mbed_error_status_t) value range for each error type is also seperated as below:\n
+ * The ERROR CODE(values encoded into ERROR CODE bit-field in mbed_error_status_t) value range for each error type is also separated as below:\n
* Posix Error Codes - 1 to 255.\n
* System Error Codes - 256 to 4095.\n
* Custom Error Codes - 4096 to 65535.\n
@@ -231,31 +231,32 @@
* @note
* \n Below are the module code mappings:\n
\verbatim
- MBED_MODULE_APPLICATION 0 Application
- MBED_MODULE_PLATFORM 1 Platform
- MODULE_KERNEL 2 RTX Kernel
- MBED_MODULE_NETWORK_STACK 3 Network stack
- MBED_MODULE_HAL 4 HAL - Hardware Abstraction Layer
- MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM 5 Memory Subsystem
- MBED_MODULE_FILESYSTEM 6 Filesystem
- MBED_MODULE_BLOCK_DEVICE 7 Block device
- MBED_MODULE_DRIVER 8 Driver
- MBED_MODULE_DRIVER_SERIAL 9 Serial Driver
- MBED_MODULE_DRIVER_RTC 10 RTC Driver
- MBED_MODULE_DRIVER_I2C 11 I2C Driver
- MODULE_DRIVER_SPI 12 SPI Driver
- MODULE_DRIVER_GPIO 13 GPIO Driver
- MODULE_DRIVER_ANALOG 14 Analog Driver
- MODULE_DRIVER_DIGITAL 15 DigitalIO Driver
- MODULE_DRIVER_CAN 16 CAN Driver
- MODULE_DRIVER_ETHERNET 17 Ethernet Driver
- MODULE_DRIVER_CRC 18 CRC Module
- MODULE_DRIVER_PWM 19 PWM Driver
- MODULE_DRIVER_QSPI 20 QSPI Driver
- MODULE_DRIVER_USB 21 USB Driver
- MODULE_TARGET_SDK 22 SDK
+ MBED_MODULE_APPLICATION 0 Application
+ MBED_MODULE_PLATFORM 1 Platform
+ MBED_MODULE_KERNEL 2 RTX Kernel
+ MBED_MODULE_NETWORK_STACK 3 Network stack
+ MBED_MODULE_HAL 4 HAL - Hardware Abstraction Layer
+ MBED_MODULE_MEMORY_SUBSYSTEM 5 Memory Subsystem
+ MBED_MODULE_FILESYSTEM 6 Filesystem
+ MBED_MODULE_BLOCK_DEVICE 7 Block device
+ MBED_MODULE_DRIVER 8 Driver
+ MBED_MODULE_DRIVER_SERIAL 9 Serial Driver
+ MBED_MODULE_DRIVER_RTC 10 RTC Driver
+ MBED_MODULE_DRIVER_I2C 11 I2C Driver
+ MBED_MODULE_DRIVER_SPI 12 SPI Driver
+ MBED_MODULE_DRIVER_GPIO 13 GPIO Driver
+ MBED_MODULE_DRIVER_ANALOG 14 Analog Driver
+ MBED_MODULE_DRIVER_DIGITAL 15 DigitalIO Driver
+ MBED_MODULE_DRIVER_CAN 16 CAN Driver
+ MBED_MODULE_DRIVER_ETHERNET 17 Ethernet Driver
+ MBED_MODULE_DRIVER_CRC 18 CRC Module
+ MBED_MODULE_DRIVER_PWM 19 PWM Driver
+ MBED_MODULE_DRIVER_QSPI 20 QSPI Driver
+ MBED_MODULE_DRIVER_USB 21 USB Driver
+ MBED_MODULE_TARGET_SDK 22 SDK
+ MBED_MODULE_BLE 23 BLE
- MBED_MODULE_UNKNOWN 255 Unknown module
+ MBED_MODULE_UNKNOWN 255 Unknown module
\endverbatim
*
*/
@@ -265,7 +266,7 @@
MBED_MODULE_KERNEL,
MBED_MODULE_NETWORK_STACK,
MBED_MODULE_HAL,
- MBED_MODULE_NETWORK_STACKMODULE_MEMORY_SUBSYSTEM,
+ MBED_MODULE_MEMORY_SUBSYSTEM,
MBED_MODULE_FILESYSTEM,
MBED_MODULE_BLOCK_DEVICE,
MBED_MODULE_DRIVER,
@@ -283,13 +284,14 @@
MBED_MODULE_DRIVER_QSPI,
MBED_MODULE_DRIVER_USB,
MBED_MODULE_TARGET_SDK,
+ MBED_MODULE_BLE,
/* Add More entities here as required */
MBED_MODULE_UNKNOWN = 255,
MBED_MODULE_MAX = MBED_MODULE_UNKNOWN
} mbed_module_type_t;
-//Use MBED_SUCCESS(=0) or any postive number for successful returns
+//Use MBED_SUCCESS(=0) or any positive number for successful returns
#define MBED_SUCCESS 0
#define MBED_POSIX_ERROR_BASE 0
@@ -468,7 +470,7 @@
INVALID_DATA 258 Invalid data
INVALID_FORMAT 259 Invalid format
INVALID_INDEX 260 Invalid Index
- INVALID_SIZE 261 Inavlid Size
+ INVALID_SIZE 261 Invalid Size
INVALID_OPERATION 262 Invalid Operation
NOT_FOUND 263 Not Found
ACCESS_DENIED 264 Access Denied
@@ -483,9 +485,9 @@
OPERATION_ABORTED 273 Operation failed
WRITE_PROTECTED 274 Attempt to write to write-protected resource
NO_RESPONSE 275 No response
- SEMAPHORE_LOCK_FAILED 276 Sempahore lock failed
+ SEMAPHORE_LOCK_FAILED 276 Semaphore lock failed
MUTEX_LOCK_FAILED 277 Mutex lock failed
- SEMAPHORE_UNLOCK_FAILED 278 Sempahore unlock failed
+ SEMAPHORE_UNLOCK_FAILED 278 Semaphore unlock failed
MUTEX_UNLOCK_FAILED 279 Mutex unlock failed
CRC_ERROR 280 CRC error or mismatch
OPEN_FAILED 281 Open failed
@@ -523,11 +525,14 @@
DEVICE_BUSY 313 Device Busy
CONFIG_UNSUPPORTED 314 Configuration not supported
CONFIG_MISMATCH 315 Configuration mismatch
- ALREADY_INITIALIZED 316 Already initialzied
+ ALREADY_INITIALIZED 316 Already initialized
HARDFAULT_EXCEPTION 317 HardFault exception
MEMMANAGE_EXCEPTION 318 MemManage exception
BUSFAULT_EXCEPTION 319 BusFault exception
USAGEFAULT_EXCEPTION 320 UsageFault exception
+ BLE_NO_FRAME_INITIALIZED, 321 BLE No frame initialized
+ BLE_BACKEND_CREATION_FAILED 322 BLE Backend creation failed
+ BLE_BACKEND_NOT_INITIALIZED 323 BLE Backend not initialized
\endverbatim
*
* @note
@@ -560,13 +565,12 @@
*
* \verbatim
++ MbedOS Error Info ++
- Error Status: 0x80040103
- Error Code: 259
- Error Module: 04
- Error Message: HAL Module error
- Error Location: 0x000067C7
- Error Value: 0x00005566
- Current Thread: Id: 0x200024A8 EntryFn: 0x0000FB0D StackSize: 0x00001000 StackMem: 0x200014A8 SP: 0x2002FFD8
+ Error Status: 0x80FF013D Code: 317 Module: 255
+ Error Message: Fault exception
+ Location: 0x5CD1
+ Error Value: 0x4A2A
+ Current Thread: Id: 0x20001E80 Entry: 0x5EB1 StackSize: 0x1000 StackMem: 0x20000E80 SP: 0x2002FF90
+ For more info, visit: https://mbed.com/s/error?error=0x80FF013D&mbedos=999999&core=0x410FC241&compile=1&ver=5060528
-- MbedOS Error Info --
\endverbatim
*/
@@ -716,7 +720,7 @@
MBED_DEFINE_SYSTEM_ERROR(INVALID_DATA_DETECTED, 2), /* 258 Invalid data detected */
MBED_DEFINE_SYSTEM_ERROR(INVALID_FORMAT, 3), /* 259 Invalid format */
MBED_DEFINE_SYSTEM_ERROR(INVALID_INDEX, 4), /* 260 Invalid Index */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_SIZE, 5), /* 261 Inavlid Size */
+ MBED_DEFINE_SYSTEM_ERROR(INVALID_SIZE, 5), /* 261 Invalid Size */
MBED_DEFINE_SYSTEM_ERROR(INVALID_OPERATION, 6), /* 262 Invalid Operation */
MBED_DEFINE_SYSTEM_ERROR(ITEM_NOT_FOUND, 7), /* 263 Item Not Found */
MBED_DEFINE_SYSTEM_ERROR(ACCESS_DENIED, 8), /* 264 Access Denied */
@@ -731,9 +735,9 @@
MBED_DEFINE_SYSTEM_ERROR(OPERATION_ABORTED, 17), /* 273 Operation failed */
MBED_DEFINE_SYSTEM_ERROR(WRITE_PROTECTED, 18), /* 274 Attempt to write to write-protected resource */
MBED_DEFINE_SYSTEM_ERROR(NO_RESPONSE, 19), /* 275 No response */
- MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_LOCK_FAILED, 20), /* 276 Sempahore lock failed */
+ MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_LOCK_FAILED, 20), /* 276 Semaphore lock failed */
MBED_DEFINE_SYSTEM_ERROR(MUTEX_LOCK_FAILED, 21), /* 277 Mutex lock failed */
- MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_UNLOCK_FAILED, 22), /* 278 Sempahore unlock failed */
+ MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_UNLOCK_FAILED, 22), /* 278 Semaphore unlock failed */
MBED_DEFINE_SYSTEM_ERROR(MUTEX_UNLOCK_FAILED, 23), /* 279 Mutex unlock failed */
MBED_DEFINE_SYSTEM_ERROR(CRC_ERROR, 24), /* 280 CRC error or mismatch */
MBED_DEFINE_SYSTEM_ERROR(OPEN_FAILED, 25), /* 281 Open failed */
@@ -771,11 +775,14 @@
MBED_DEFINE_SYSTEM_ERROR(DEVICE_BUSY, 57), /* 313 Device Busy */
MBED_DEFINE_SYSTEM_ERROR(CONFIG_UNSUPPORTED, 58), /* 314 Configuration not supported */
MBED_DEFINE_SYSTEM_ERROR(CONFIG_MISMATCH, 59), /* 315 Configuration mismatch */
- MBED_DEFINE_SYSTEM_ERROR(ALREADY_INITIALIZED, 60), /* 316 Already initialzied */
+ MBED_DEFINE_SYSTEM_ERROR(ALREADY_INITIALIZED, 60), /* 316 Already initialized */
MBED_DEFINE_SYSTEM_ERROR(HARDFAULT_EXCEPTION, 61), /* 317 HardFault exception */
MBED_DEFINE_SYSTEM_ERROR(MEMMANAGE_EXCEPTION, 62), /* 318 MemManage exception */
MBED_DEFINE_SYSTEM_ERROR(BUSFAULT_EXCEPTION, 63), /* 319 BusFault exception */
MBED_DEFINE_SYSTEM_ERROR(USAGEFAULT_EXCEPTION, 64), /* 320 UsageFault exception*/
+ MBED_DEFINE_SYSTEM_ERROR(BLE_NO_FRAME_INITIALIZED, 65), /* 321 BLE No frame initialized */
+ MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_CREATION_FAILED, 66), /* 322 BLE Backend creation failed */
+ MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_NOT_INITIALIZED, 67), /* 323 BLE Backend not initialized */
//Everytime you add a new system error code, you must update
//Error documentation under Handbook to capture the info on
@@ -915,7 +922,6 @@
* Callback/Error hook function prototype. Applications needing a callback when an error is reported can use mbed_set_error_hook function
* to register a callback/error hook function using the following prototype. When an error happens in the system error handling
* implementation will invoke this callback with the mbed_error_status_t reported and the error context at the time of error.
- * @param error_status mbed_error_status_t status being reported.
* @param error_ctx Error context structure associated with this error.
* @return void
*
--- a/platform/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -64,6 +64,40 @@
"max-error-filename-len": {
"help": "Sets the maximum length of buffer used for capturing the filename in error context. This needs error-filename-capture-enabled feature.",
"value": 16
+ },
+ "memory-tracing-enabled": {
+ "macro_name": "MBED_MEM_TRACING_ENABLED",
+ "help": "Enable tracing of each memory call by invoking a callback on each memory operation. See mbed_mem_trace.h in the HAL API for more information",
+ "value": false
+ },
+ "sys-stats-enabled": {
+ "macro_name": "MBED_SYS_STATS_ENABLED",
+ "help": "Set to 1 to enable system stats. When enabled the function mbed_stats_sys_get returns non-zero data. See mbed_stats.h for more information",
+ "value": null
+ },
+ "stack-stats-enabled": {
+ "macro_name": "MBED_STACK_STATS_ENABLED",
+ "help": "Set to 1 to enable stack stats. When enabled the functions mbed_stats_stack_get and mbed_stats_stack_get_each return non-zero data. See mbed_stats.h for more information",
+ "value": null
+ },
+ "cpu-stats-enabled": {
+ "macro_name": "MBED_CPU_STATS_ENABLED",
+ "help": "Set to 1 to enable cpu stats. When enabled the function mbed_stats_cpu_get returns non-zero data. See mbed_stats.h for more information",
+ "value": null
+ },
+ "heap-stats-enabled": {
+ "macro_name": "MBED_HEAP_STATS_ENABLED",
+ "help": "Set to 1 to enable heap stats. When enabled the function mbed_stats_heap_get returns non-zero data. See mbed_stats.h for more information",
+ "value": null
+ },
+ "thread-stats-enabled": {
+ "macro_name": "MBED_THREAD_STATS_ENABLED",
+ "help": "Set to 1 to enable thread stats. When enabled the function mbed_stats_thread_get_each returns non-zero data. See mbed_stats.h for more information",
+ "value": null
+ },
+ "error-decode-http-url-str": {
+ "help": "HTTP URL string for ARM Mbed-OS Error Decode microsite",
+ "value": "\"\\nFor more info, visit: https://armmbed.github.io/mbedos-error/?error=0x%08X\""
}
},
"target_overrides": {
--- a/platform/mbed_mem_trace.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_mem_trace.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,12 +28,14 @@
#include <stdint.h>
#include <stddef.h>
-/* Operation types for tracer */
+/**
+ * enum Memory operation types for tracer
+ */
enum {
- MBED_MEM_TRACE_MALLOC,
- MBED_MEM_TRACE_REALLOC,
- MBED_MEM_TRACE_CALLOC,
- MBED_MEM_TRACE_FREE
+ MBED_MEM_TRACE_MALLOC, /**< Identifier for malloc operation */
+ MBED_MEM_TRACE_REALLOC, /**< Identifier for realloc operation */
+ MBED_MEM_TRACE_CALLOC, /**< Identifier for calloc operation */
+ MBED_MEM_TRACE_FREE /**< Identifier for free operation */
};
/**
--- a/platform/mbed_poll.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_poll.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -20,8 +20,8 @@
#include "rtos/Thread.h"
using namespace rtos;
#else
-#include "Timer.h"
-#include "LowPowerTimer.h"
+#include "drivers/Timer.h"
+#include "drivers/LowPowerTimer.h"
#endif
namespace mbed {
@@ -29,7 +29,7 @@
// timeout -1 forever, or milliseconds
int poll(pollfh fhs[], unsigned nfhs, int timeout)
{
- /**
+ /*
* TODO Proper wake-up mechanism.
* In order to correctly detect availability of read/write a FileHandle, we needed
* a select or poll mechanisms. We opted for poll as POSIX defines in
--- a/platform/mbed_power_mgmt.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_power_mgmt.h Thu Nov 08 11:46:34 2018 +0000
@@ -23,7 +23,7 @@
#ifndef MBED_POWER_MGMT_H
#define MBED_POWER_MGMT_H
-#include "sleep_api.h"
+#include "hal/sleep_api.h"
#include "mbed_toolchain.h"
#include "hal/ticker_api.h"
#include <stdbool.h>
@@ -32,7 +32,8 @@
extern "C" {
#endif
-/** Sleep manager API
+/**
+ * @defgroup hal_sleep_manager Sleep manager API
* The sleep manager provides API to automatically select sleep mode.
*
* There are two sleep modes:
@@ -43,6 +44,17 @@
* are not allowed (=disabled) during the deepsleep. For instance, high frequency
* clocks.
*
+ * # Defined behavior
+ * * The lock is a counter
+ * * The lock can be locked up to USHRT_MAX - Verified by ::test_lock_eq_ushrt_max and ::test_lock_gt_ushrt_max
+ * * The lock has to be equally unlocked as locked - Verified by ::test_lone_unlock and ::test_lock_eq_ushrt_max
+ * * The function sleep_manager_lock_deep_sleep_internal() locks the automatic deep mode selection - Verified by ::test_lock_unlock
+ * * The function sleep_manager_unlock_deep_sleep_internal() unlocks the automatic deep mode selection - Verified by ::test_lock_unlock
+ * * The function sleep_manager_sleep_auto() chooses the sleep or deep sleep modes based on the lock - Verified by ::test_sleep_auto
+ * * The function sleep_manager_lock_deep_sleep_internal() is IRQ and thread safe - Verified by ::sleep_manager_multithread_test and ::sleep_manager_irq_test
+ * * The function sleep_manager_unlock_deep_sleep_internal() is IRQ and thread safe - Verified by ::sleep_manager_multithread_test and ::sleep_manager_irq_test
+ * * The function sleep_manager_sleep_auto() is IRQ and thread safe
+ *
* Example:
* @code
*
@@ -63,7 +75,19 @@
* return _sensor.start(event, callback);
* }
* @endcode
+ * @{
*/
+
+/**
+ * @defgroup hal_sleep_manager_tests Sleep manager API tests
+ * Tests to validate the proper implementation of the sleep manager
+ *
+ * To run the sleep manager hal tests use the command:
+ *
+ * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-sleep_manager*
+ *
+ */
+
#ifdef MBED_SLEEP_TRACING_ENABLED
void sleep_tracker_lock(const char *const filename, int line);
@@ -122,7 +146,18 @@
*/
bool sleep_manager_can_deep_sleep(void);
-/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+/** Check if the target can deep sleep within a period of time
+ *
+ * This function in intended for use in testing. The amount
+ * of time this functions waits for deeps sleep to be available
+ * is currently 2ms. This may change in the future depending
+ * on testing requirements.
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep_test_check(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deepsleep modes based
* on the deepsleep locking counter
*
* This function is IRQ and thread safe
@@ -138,7 +173,6 @@
*
* @note This function can be a noop if not implemented by the platform.
* @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
- * @note This function will be a noop while uVisor is in use.
* @note This function will be a noop if the following conditions are met:
* - The RTOS is present
* - The processor turn off the Systick clock during sleep
@@ -158,13 +192,11 @@
*/
static inline void sleep(void)
{
-#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
#if DEVICE_SLEEP
-#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_SYSTICK_CLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
sleep_manager_sleep_auto();
-#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_SYSTICK_CLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
#endif /* DEVICE_SLEEP */
-#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
}
/** Send the microcontroller to deep sleep
@@ -174,7 +206,6 @@
*
* @note This function can be a noop if not implemented by the platform.
* @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
- * @note This function will be a noop while uVisor is in use.
*
* This processor is setup ready for deep sleep, and sent to sleep. This mode
* has the same sleep features as sleep plus it powers down peripherals and clocks. All state
@@ -191,20 +222,9 @@
MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
static inline void deepsleep(void)
{
-#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
#if DEVICE_SLEEP
sleep_manager_sleep_auto();
#endif /* DEVICE_SLEEP */
-#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
-}
-
-/** Resets the processor and most of the sub-system
- *
- * @note Does not affect the debug sub-system
- */
-static inline void system_reset(void)
-{
- NVIC_SystemReset();
}
/** Provides the time spent in sleep mode since boot.
@@ -235,6 +255,17 @@
*/
us_timestamp_t mbed_uptime(void);
+/** @}*/
+
+/** Resets the processor and most of the sub-system
+ *
+ * @note Does not affect the debug sub-system
+ */
+static inline void system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
#ifdef __cplusplus
}
#endif
--- a/platform/mbed_retarget.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_retarget.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -1469,7 +1469,7 @@
#endif
-#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)))
+#if MBED_MEM_TRACING_ENABLED && (defined(__CC_ARM) || defined(__ICCARM__) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)))
// If the memory tracing is enabled, the wrappers in mbed_alloc_wrappers.cpp
// provide the implementation for these. Note: this needs to use the wrappers
@@ -1515,7 +1515,7 @@
free_wrapper(ptr, MBED_CALLER_ADDR());
}
-#elif defined(MBED_MEM_TRACING_ENABLED) && defined(__GNUC__)
+#elif MBED_MEM_TRACING_ENABLED && defined(__GNUC__)
#include <reent.h>
--- a/platform/mbed_rtc_time.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_rtc_time.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -33,6 +33,8 @@
#include "drivers/LowPowerTimer.h"
+#define US_PER_SEC 1000000
+
static SingletonPtr<mbed::LowPowerTimer> _rtc_lp_timer;
static uint64_t _rtc_lp_base;
static bool _rtc_enabled;
@@ -50,7 +52,7 @@
static time_t _rtc_lpticker_read(void)
{
- return (uint64_t)_rtc_lp_timer->read() + _rtc_lp_base;
+ return _rtc_lp_timer->read_high_resolution_us() / US_PER_SEC + _rtc_lp_base;
}
static void _rtc_lpticker_write(time_t t)
--- a/platform/mbed_rtc_time.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_rtc_time.h Thu Nov 08 11:46:34 2018 +0000
@@ -31,7 +31,7 @@
*
* Provides mechanisms to set and read the current time, based
* on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formating functions.
+ * standard C manipulation and formatting functions.
*
* Example:
* @code
@@ -40,10 +40,10 @@
* int main() {
* set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
*
- * while(1) {
+ * while (true) {
* time_t seconds = time(NULL);
*
- * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ * printf("Time as seconds since January 1, 1970 = %u\n", (unsigned int)seconds);
*
* printf("Time as a basic string = %s", ctime(&seconds));
*
@@ -59,7 +59,7 @@
/** Set the current time
*
- * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * Initializes and sets the time of the microcontroller Real-Time Clock (RTC)
* to the time represented by the number of seconds since January 1, 1970
* (the UNIX timestamp).
*
@@ -84,8 +84,8 @@
*
* @param read_rtc pointer to function which returns current UNIX timestamp
* @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
- * @param init_rtc pointer to funtion which initializes RTC, can be NULL
- * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ * @param init_rtc pointer to function which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function which returns if the RTC is enabled, can be NULL
*/
void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
--- a/platform/mbed_stats.c Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_stats.c Thu Nov 08 11:46:34 2018 +0000
@@ -41,7 +41,10 @@
osThreadId_t *threads;
threads = malloc(sizeof(osThreadId_t) * thread_n);
- MBED_ASSERT(threads != NULL);
+ // Don't fail on lack of memory
+ if (!threads) {
+ return;
+ }
osKernelLock();
thread_n = osThreadEnumerate(threads, thread_n);
@@ -69,7 +72,10 @@
osThreadId_t *threads;
threads = malloc(sizeof(osThreadId_t) * count);
- MBED_ASSERT(threads != NULL);
+ // Don't fail on lack of memory
+ if (!threads) {
+ return 0;
+ }
osKernelLock();
count = osThreadEnumerate(threads, count);
--- a/platform/mbed_stats.h Thu Sep 06 13:40:20 2018 +0100
+++ b/platform/mbed_stats.h Thu Nov 08 11:46:34 2018 +0000
@@ -42,16 +42,17 @@
* struct mbed_stats_heap_t definition
*/
typedef struct {
- uint32_t current_size; /**< Bytes allocated currently. */
- uint32_t max_size; /**< Max bytes allocated at a given time. */
- uint32_t total_size; /**< Cumulative sum of bytes ever allocated. */
- uint32_t reserved_size; /**< Current number of bytes allocated for the heap. */
- uint32_t alloc_cnt; /**< Current number of allocations. */
- uint32_t alloc_fail_cnt; /**< Number of failed allocations. */
+ uint32_t current_size; /**< Bytes currently allocated on the heap */
+ uint32_t max_size; /**< Maximum bytes allocated on the heap at one time since reset */
+ uint32_t total_size; /**< Cumulative sum of bytes allocated on the heap that have not been freed */
+ uint32_t reserved_size; /**< Current number of bytes reserved for the heap */
+ uint32_t alloc_cnt; /**< Current number of allocations that have not been freed since reset */
+ uint32_t alloc_fail_cnt; /**< Number of failed allocations since reset */
+ uint32_t overhead_size; /**< Number of bytes used to store heap statistics. This overhead takes up space on the heap, reducing the available heap space */
} mbed_stats_heap_t;
/**
- * Fill the passed in heap stat structure with heap stats.
+ * Fill the passed in heap stat structure with the heap statistics.
*
* @param stats A pointer to the mbed_stats_heap_t structure to fill
*/
@@ -61,14 +62,14 @@
* struct mbed_stats_stack_t definition
*/
typedef struct {
- uint32_t thread_id; /**< Identifier for thread that owns the stack or 0 if multiple threads. */
- uint32_t max_size; /**< Maximum number of bytes used on the stack. */
- uint32_t reserved_size; /**< Current number of bytes allocated for the stack. */
- uint32_t stack_cnt; /**< Number of stacks stats accumulated in the structure. */
+ uint32_t thread_id; /**< Identifier for the thread that owns the stack or 0 if representing accumulated statistics */
+ uint32_t max_size; /**< Maximum number of bytes used on the stack since the thread was started */
+ uint32_t reserved_size; /**< Current number of bytes reserved for the stack */
+ uint32_t stack_cnt; /**< The number of stacks represented in the accumulated statistics or 1 if repesenting a single stack */
} mbed_stats_stack_t;
/**
- * Fill the passed in structure with stack stats accumulated for all threads. The thread_id will be 0
+ * Fill the passed in structure with stack statistics accumulated for all threads. The thread_id will be 0
* and stack_cnt will represent number of threads.
*
* @param stats A pointer to the mbed_stats_stack_t structure to fill
@@ -76,12 +77,13 @@
void mbed_stats_stack_get(mbed_stats_stack_t *stats);
/**
- * Fill the passed array of stat structures with the stack stats for each available thread.
+ * Fill the passed array of structures with the stack statistics for each available thread.
*
* @param stats A pointer to an array of mbed_stats_stack_t structures to fill
* @param count The number of mbed_stats_stack_t structures in the provided array
- * @return The number of mbed_stats_stack_t structures that have been filled,
- * this is equal to the number of stacks on the system.
+ * @return The number of mbed_stats_stack_t structures that have been filled.
+ * If the number of stacks on the system is less than or equal to count, it will equal the number of stacks on the system.
+ * If the number of stacks on the system is greater than count, it will equal count.
*/
size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
@@ -89,10 +91,10 @@
* struct mbed_stats_cpu_t definition
*/
typedef struct {
- us_timestamp_t uptime; /**< Time since system is up and running */
- us_timestamp_t idle_time; /**< Time spent in idle thread since system is up and running */
- us_timestamp_t sleep_time; /**< Time spent in sleep since system is up and running */
- us_timestamp_t deep_sleep_time; /**< Time spent in deep sleep since system is up and running */
+ us_timestamp_t uptime; /**< Time since the system has started */
+ us_timestamp_t idle_time; /**< Time spent in the idle thread since the system has started */
+ us_timestamp_t sleep_time; /**< Time spent in sleep since the system has started */
+ us_timestamp_t deep_sleep_time; /**< Time spent in deep sleep since the system has started */
} mbed_stats_cpu_t;
/**
@@ -106,21 +108,22 @@
* struct mbed_stats_thread_t definition
*/
typedef struct {
- uint32_t id; /**< Thread Object Identifier */
- uint32_t state; /**< Thread Object State */
- uint32_t priority; /**< Thread Priority */
- uint32_t stack_size; /**< Thread Stack Size */
- uint32_t stack_space; /**< Thread remaining stack size */
- const char *name; /**< Thread Object name */
+ uint32_t id; /**< ID of the thread */
+ uint32_t state; /**< State of the thread */
+ uint32_t priority; /**< Priority of the thread (higher number indicates higher priority) */
+ uint32_t stack_size; /**< Current number of bytes reserved for the stack */
+ uint32_t stack_space; /**< Current number of free bytes remaining on the stack */
+ const char *name; /**< Name of the thread */
} mbed_stats_thread_t;
/**
- * Fill the passed array of stat structures with the thread stats for each available thread.
+ * Fill the passed array of stat structures with the thread statistics for each available thread.
*
* @param stats A pointer to an array of mbed_stats_thread_t structures to fill
* @param count The number of mbed_stats_thread_t structures in the provided array
- * @return The number of mbed_stats_thread_t structures that have been filled,
- * this is equal to the number of threads on the system.
+ * @return The number of mbed_stats_thread_t structures that have been filled.
+ * If the number of threads on the system is less than or equal to count, it will equal the number of threads on the system.
+ * If the number of threads on the system is greater than count, it will equal count.
*/
size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count);
@@ -137,14 +140,14 @@
* struct mbed_stats_sys_t definition
*/
typedef struct {
- uint32_t os_version; /**< Mbed OS Version (Release only) */
- uint32_t cpu_id; /**< CPUID Register data (Cortex-M only supported) */
+ uint32_t os_version; /**< Mbed OS version (populated only for tagged releases) */
+ uint32_t cpu_id; /**< CPUID register data (Cortex-M only supported) */
mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */
uint32_t compiler_version; /**< Compiler version */
} mbed_stats_sys_t;
/**
- * Fill the passed in sys stat structure with system stats.
+ * Fill the passed in system stat structure with system statistics.
*
* @param stats A pointer to the mbed_stats_sys_t structure to fill
*/
--- a/platform/mbed_toolchain.h Thu Sep 06 13:40:20 2018 +0100 +++ b/platform/mbed_toolchain.h Thu Nov 08 11:46:34 2018 +0000 @@ -144,6 +144,8 @@ #ifndef MBED_WEAK #if defined(__ICCARM__) #define MBED_WEAK __weak +#elif defined(__MINGW32__) +#define MBED_WEAK #else #define MBED_WEAK __attribute__((weak)) #endif
--- a/platform/mbed_version.h Thu Sep 06 13:40:20 2018 +0100 +++ b/platform/mbed_version.h Thu Nov 08 11:46:34 2018 +0000 @@ -24,7 +24,7 @@ #ifndef MBED_VERSION_H #define MBED_VERSION_H -#define MBED_LIBRARY_VERSION 163 +#define MBED_LIBRARY_VERSION 164 /** MBED_MAJOR_VERSION * Mbed 2 major version @@ -39,7 +39,7 @@ /** MBED_PATCH_VERSION * Mbed 2 patch version */ -#define MBED_PATCH_VERSION 163 +#define MBED_PATCH_VERSION 164 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -69,7 +69,7 @@
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
-M_VECTOR_RAM_SIZE = 0x100;
+M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
SECTIONS
{
@@ -77,12 +77,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -121,30 +121,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -152,14 +152,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -177,13 +177,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -77,12 +77,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -121,30 +121,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -152,14 +152,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -177,13 +177,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -77,12 +77,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -121,30 +121,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -152,14 +152,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -177,13 +177,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -77,12 +77,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -121,30 +121,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -152,14 +152,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -177,13 +177,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -77,12 +77,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -121,30 +121,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -152,14 +152,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -177,13 +177,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_GCC_ARM/BEETLE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_GCC_ARM/BEETLE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -75,21 +75,11 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_TEXT_OFFSET = 0x0;
- __UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET;
- .text __UVISOR_TEXT_START :
+ .text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
-
*(.text*)
KEEP(*(.init))
@@ -134,68 +124,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
- /* ensure that uvisor bss is at the beginning of memory */
- /* Note: The uVisor expects this section at a fixed location, as specified by
- * the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x140;
- __UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_BSS_START (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN((1 << LOG2CEIL(LENGTH(RAM))) / 8);
- __uvisor_bss_end = .;
- } > RAM
-
- /* Heap space for the page allocator */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN(32);
- __uvisor_page_end = .;
- } > RAM
-
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -203,47 +155,19 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to allow
- * discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > FLASH
-
/* From now on you can insert any other SRAM region. */
.uninitialized (NOLOAD):
@@ -258,13 +182,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
@@ -275,14 +199,12 @@
.heap :
{
. = ALIGN(8);
- __uvisor_heap_start = .;
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
- __uvisor_heap_end = .;
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
@@ -293,10 +215,5 @@
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM);
- __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
} /* End of sections */
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_GCC_ARM/startup_BEETLE.S Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_GCC_ARM/startup_BEETLE.S Thu Nov 08 11:46:34 2018 +0000
@@ -103,13 +103,6 @@
Reset_Handler:
ldr r0, =SystemInit
blx r0
-/* The call to uvisor_init() happens independently of uVisor being enabled or
-* not, so it is conditionally compiled only based on FEATURE_UVISOR. */
-#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
- /* Call uvisor_init() */
- ldr r0, =uvisor_init
- blx r0
-#endif /* FEATURE_UVISOR && TARGET_UVISOR_SUPPORTED */
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -152,4 +152,9 @@
DualTimer_ClearInterrupt(DUALTIMER0);
}
+void lp_ticker_free(void)
+{
+
+}
+
#endif
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c Thu Nov 08 11:46:34 2018 +0000
@@ -23,10 +23,8 @@
EFlash_DriverInitialize();
EFlash_ClockConfig();
-#if !defined(FEATURE_UVISOR) || !defined(TARGET_UVISOR_SUPPORTED)
/* Enable Flash Cache Stats */
FCache_DriverInitialize();
FCache_Enable(1);
FCache_Invalidate();
-#endif
}
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -111,3 +111,8 @@
void us_ticker_clear_interrupt(void) {
Timer_ClearInterrupt(TIMER0);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld Thu Nov 08 11:46:34 2018 +0000
@@ -72,12 +72,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -116,30 +116,30 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
- . = ALIGN(4);
+ . = ALIGN(8);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -147,14 +147,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -172,13 +172,13 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -108,6 +108,11 @@
cmsdk_ticker_fire_interrupt(&timer_data);
}
+void lp_ticker_free(void)
+{
+
+}
+
void TIMER1_IRQHandler(void)
{
cmsdk_ticker_irq_handler(&timer_data);
--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -112,6 +112,11 @@
cmsdk_ticker_fire_interrupt(&timer_data);
}
+void us_ticker_free(void)
+{
+
+}
+
void TIMER0_IRQHandler(void)
{
cmsdk_ticker_irq_handler(&timer_data);
--- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -87,3 +87,8 @@
US_TICKER_TIMER2->TimerIntClr = 0x1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -81,3 +81,8 @@
US_TICKER_TIMER2->TimerIntClr = 0x1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c Thu Nov 08 11:46:34 2018 +0000
@@ -259,8 +259,8 @@
* \n
* \n false :To disable retention during the hibernation.
* \n
- * @return : SUCCESS : Configured successfully.
- * FAILURE : For invalid bank.
+ * @return : ADI_SYS_SUCCESS : Configured successfully.
+ * ADI_SYS_FAILURE : For invalid bank.
* @note: Please note that respective linker file need to support the configuration. Only BANK-1 and
BANK-2 of SRAM is valid.
*/
@@ -269,7 +269,7 @@
#ifdef ADI_DEBUG
if((eBank != ADI_SRAM_BANK_1) && (eBank != ADI_SRAM_BANK_2))
{
- return FAILURE;
+ return ADI_SYS_FAILURE;
}
#endif
pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY;
@@ -282,5 +282,5 @@
pADI_PMG0->SRAMRET &= ~((uint32_t)eBank >> 1);
}
- return SUCCESS;
+ return ADI_SYS_SUCCESS;
}
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld Thu Nov 08 11:46:34 2018 +0000
@@ -128,7 +128,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -146,7 +146,7 @@
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -164,13 +164,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -178,7 +178,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -186,7 +186,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -194,7 +194,7 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
KEEP(*(.bss.gChannelControlDataArray))
KEEP(*(.bss.thread_stack_main))
@@ -202,16 +202,16 @@
KEEP(*(.bss.os_thread_def_stack_event_loop_thread))
*(COMMON)
*(.bss)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > DSRAM_C
.bss2 :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss2_start__ = .;
*(.bss*)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss2_end__ = .;
} > DSRAM_B
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -355,6 +355,10 @@
event_timer(); // enable the timer and interrupt
}
+void us_ticker_free(void)
+{
+ adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+}
/*
** EOF
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h Thu Nov 08 11:46:34 2018 +0000
@@ -40,9 +40,12 @@
#endif /* __cplusplus */
/*! \cond PRIVATE */
-#define SUCCESS 0u
-
-#define FAILURE 1u
+/*! System API function return codes */
+typedef enum
+{
+ ADI_SYS_SUCCESS = 0, /*!< No error detected. */
+ ADI_SYS_FAILURE, /*!< The API call failed. */
+} ADI_SYS_RESULT;
/* System clock constant */
#define __HFOSC 26000000u
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld Thu Nov 08 11:46:34 2018 +0000
@@ -130,7 +130,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -148,7 +148,7 @@
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -166,13 +166,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -180,7 +180,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -188,7 +188,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -353,6 +353,10 @@
event_timer(); // enable the timer and interrupt
}
+void us_ticker_free(void)
+{
+ adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+}
/*
** EOF
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -11,8 +11,8 @@
.ANY (+RO)
}
- ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
+ ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -11,8 +11,8 @@
.ANY (+RO)
}
- ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
+ ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld Thu Nov 08 11:46:34 2018 +0000
@@ -5,7 +5,7 @@
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
+ ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
@@ -15,7 +15,7 @@
SECTIONS {
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
@@ -25,29 +25,29 @@
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -58,7 +58,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
@@ -70,36 +70,36 @@
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
- . = ALIGN(4);
+ . = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
- . = ALIGN(4);
+ . = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
@@ -114,5 +114,5 @@
_estack = .;
} > ram
- . = ALIGN(4);
+ . = ALIGN(8);
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -11,8 +11,8 @@
.ANY (+RO)
}
- ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
+ ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -11,8 +11,8 @@
.ANY (+RO)
}
- ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
+ ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld Thu Nov 08 11:46:34 2018 +0000
@@ -5,7 +5,7 @@
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
+ ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
@@ -15,7 +15,7 @@
SECTIONS {
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
@@ -25,29 +25,29 @@
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -58,7 +58,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
@@ -70,36 +70,36 @@
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
- . = ALIGN(4);
+ . = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
- . = ALIGN(4);
+ . = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
@@ -114,5 +114,5 @@
_estack = .;
} > ram
- . = ALIGN(4);
+ . = ALIGN(8);
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -18,8 +18,8 @@
}
;
- [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4)
+ [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)
{
;
RW data
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct Thu Nov 08 11:46:34 2018 +0000
@@ -10,8 +10,8 @@
.ANY (+RO)
}
- ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
- RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
+ ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
+ RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld Thu Nov 08 11:46:34 2018 +0000
@@ -5,7 +5,7 @@
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
+ ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
@@ -15,7 +15,7 @@
SECTIONS {
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
@@ -25,29 +25,29 @@
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -58,7 +58,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
@@ -70,36 +70,36 @@
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
- . = ALIGN(4);
+ . = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
- . = ALIGN(4);
+ . = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
@@ -114,5 +114,5 @@
_estack = .;
} > ram
- . = ALIGN(4);
+ . = ALIGN(8);
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld Thu Nov 08 11:46:34 2018 +0000
@@ -15,7 +15,7 @@
SECTIONS {
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
@@ -25,29 +25,29 @@
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -58,7 +58,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
@@ -70,36 +70,36 @@
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
- . = ALIGN(4);
+ . = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
- . = ALIGN(4);
+ . = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
@@ -114,5 +114,5 @@
_estack = .;
} > ram
- . = ALIGN(4);
+ . = ALIGN(8);
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -167,3 +167,8 @@
tc_clear_interrupt(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0);
NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/samg55j19.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device/TOOLCHAIN_GCC_ARM/samg55j19.ld Thu Nov 08 11:46:34 2018 +0000
@@ -15,7 +15,7 @@
SECTIONS {
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
@@ -25,29 +25,29 @@
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -58,7 +58,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
@@ -70,36 +70,36 @@
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
- . = ALIGN(4);
+ . = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
- . = ALIGN(4);
+ . = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
@@ -114,5 +114,5 @@
_estack = .;
} > ram
- . = ALIGN(4);
+ . = ALIGN(8);
}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -131,3 +131,8 @@
{
NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2);
}
+
+void lp_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -186,3 +186,8 @@
{
NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
}
+
+void us_ticker_free(void)
+{
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,109 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)SCB0_BASE,
+ UART_1 = (int)SCB1_BASE,
+ UART_2 = (int)SCB2_BASE,
+ UART_3 = (int)SCB3_BASE,
+ UART_4 = (int)SCB4_BASE,
+ UART_5 = (int)SCB5_BASE,
+ UART_6 = (int)SCB6_BASE,
+ UART_7 = (int)SCB7_BASE,
+} UARTName;
+
+
+typedef enum {
+ SPI_0 = (int)SCB0_BASE,
+ SPI_1 = (int)SCB1_BASE,
+ SPI_2 = (int)SCB2_BASE,
+ SPI_3 = (int)SCB3_BASE,
+ SPI_4 = (int)SCB4_BASE,
+ SPI_5 = (int)SCB5_BASE,
+ SPI_6 = (int)SCB6_BASE,
+ SPI_7 = (int)SCB7_BASE,
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)SCB0_BASE,
+ I2C_1 = (int)SCB1_BASE,
+ I2C_2 = (int)SCB2_BASE,
+ I2C_3 = (int)SCB3_BASE,
+ I2C_4 = (int)SCB4_BASE,
+ I2C_5 = (int)SCB5_BASE,
+ I2C_6 = (int)SCB6_BASE,
+ I2C_7 = (int)SCB7_BASE,
+} I2CName;
+
+typedef enum {
+ PWM_32b_0 = TCPWM0_BASE,
+ PWM_32b_1,
+ PWM_32b_2,
+ PWM_32b_3,
+ PWM_32b_4,
+ PWM_32b_5,
+ PWM_32b_6,
+ PWM_32b_7,
+ PWM_16b_0 = TCPWM1_BASE,
+ PWM_16b_1,
+ PWM_16b_2,
+ PWM_16b_3,
+ PWM_16b_4,
+ PWM_16b_5,
+ PWM_16b_6,
+ PWM_16b_7,
+ PWM_16b_8,
+ PWM_16b_9,
+ PWM_16b_10,
+ PWM_16b_11,
+ PWM_16b_12,
+ PWM_16b_13,
+ PWM_16b_14,
+ PWM_16b_15,
+ PWM_16b_16,
+ PWM_16b_17,
+ PWM_16b_18,
+ PWM_16b_19,
+ PWM_16b_20,
+ PWM_16b_21,
+ PWM_16b_22,
+ PWM_16b_23,
+} PWMName;
+
+typedef enum {
+ ADC_0 = (int)SAR_BASE,
+} ADCName;
+
+typedef enum {
+ DAC_0 = (int)CTDAC0_BASE,
+} DACName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,62 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + + +// //*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM_OUT[]; +#endif + +//*** SERIAL *** +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif + +//*** SPI *** +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** ADC *** +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,84 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PINNAMESTYPES_H
+#define MBED_PINNAMESTYPES_H
+
+#include "cmsis.h"
+
+typedef enum {
+ PIN_INPUT = 0,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrainDriveLow = 3,
+ OpenDrainDriveHigh = 4,
+ OpenDrain = OpenDrainDriveLow,
+ PushPull = 5,
+ AnalogMode = 6,
+ PullDefault = PullNone
+} PinMode;
+
+typedef struct {
+ en_hsiom_sel_t hsiom : 8;
+ en_clk_dst_t clock : 8;
+ PinMode mode : 4;
+ PinDirection dir : 1;
+} PinFunction;
+
+// Encode pin function.
+// Output function
+#define CY_PIN_FUNCTION(hsiom, clock, mode, dir) (int)(((dir) << 20) | ((mode) << 16) | ((clock) << 8) | (hsiom))
+#define CY_PIN_OUT_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PushPull, PIN_OUTPUT)
+#define CY_PIN_OD_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, OpenDrain, PIN_OUTPUT)
+#define CY_PIN_IN_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullDefault, PIN_INPUT)
+#define CY_PIN_PULLUP_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullUp, PIN_INPUT)
+#define CY_PIN_ANALOG_FUNCTION(clock) CY_PIN_FUNCTION(HSIOM_SEL_GPIO, clock, AnalogMode, 0)
+
+// Create unique name to force 32-bit PWM usage on a pin.
+#define CY_PIN_FORCE_PWM_32(pin) ((uint32_t)(pin) + 0x8000)
+
+static inline en_hsiom_sel_t CY_PIN_HSIOM(int function)
+{
+ return (en_hsiom_sel_t)(function & 0xFF);
+}
+
+static inline en_clk_dst_t CY_PIN_CLOCK(int function)
+{
+ return (en_clk_dst_t)((function >> 8) & 0xFF);
+}
+
+static inline PinMode CY_PIN_MODE(int function)
+{
+ return (PinMode)((function >> 16) & 0x0F);
+}
+
+static inline PinDirection CY_PIN_DIRECTION(int function)
+{
+ return (PinDirection)((function >> 20) & 1);
+}
+
+static inline int CY_PERIPHERAL_BASE(int peripheral)
+{
+ return peripheral & 0xffff0000;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/PortNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,47 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Port[15-0]
+typedef enum {
+ Port0 = 0x0,
+ Port1 = 0x1,
+ Port2 = 0x2,
+ Port3 = 0x3,
+ Port4 = 0x4,
+ Port5 = 0x5,
+ Port6 = 0x6,
+ Port7 = 0x7,
+ Port8 = 0x8,
+ Port9 = 0x9,
+ Port10 = 0xA,
+ Port11 = 0xB,
+ Port12 = 0xC,
+ Port13 = 0xD,
+ Port14 = 0xE
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,364 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralNames.h"
+#include "PeripheralPins.h"
+#include "pinmap.h"
+
+#if DEVICE_SERIAL
+//*** SERIAL ***
+const PinMap PinMap_UART_RX[] = {
+ {P0_2, UART_0, CY_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX, PCLK_SCB0_CLOCK)},
+ {P1_0, UART_7, CY_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)},
+ {P5_0, UART_5, CY_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
+ {P6_0, UART_3, CY_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX, PCLK_SCB3_CLOCK)},
+ {P6_4, UART_6, CY_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
+ {P7_0, UART_4, CY_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
+ {P8_0, UART_4, CY_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
+ {P9_0, UART_2, CY_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)},
+ {P10_0, UART_1, CY_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)},
+ {P11_0, UART_5, CY_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
+ {P12_0, UART_6, CY_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
+ {P13_0, UART_6, CY_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_UART_TX[] = {
+ {P0_3, UART_0, CY_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX, PCLK_SCB0_CLOCK)},
+ {P1_1, UART_7, CY_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)},
+ {P5_1, UART_5, CY_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
+ {P6_1, UART_3, CY_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX, PCLK_SCB3_CLOCK)},
+ {P6_5, UART_6, CY_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
+ {P7_1, UART_4, CY_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
+ {P8_1, UART_4, CY_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
+ {P9_1, UART_2, CY_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)},
+ {P10_1, UART_1, CY_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)},
+ {P11_1, UART_5, CY_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
+ {P12_1, UART_6, CY_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
+ {P13_1, UART_6, CY_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_UART_RTS[] = {
+ {P0_4, UART_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS, PCLK_SCB0_CLOCK)},
+ {P1_2, UART_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS, PCLK_SCB7_CLOCK)},
+ {P5_2, UART_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
+ {P6_2, UART_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS, PCLK_SCB3_CLOCK)},
+ {P6_6, UART_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
+ {P7_2, UART_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
+ {P8_2, UART_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
+ {P9_2, UART_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)},
+ {P10_2, UART_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)},
+ {P11_2, UART_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
+ {P12_2, UART_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_UART_CTS[] = {
+ {P0_5, UART_0, CY_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS, PCLK_SCB0_CLOCK)},
+ {P1_3, UART_7, CY_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS, PCLK_SCB7_CLOCK)},
+ {P5_3, UART_5, CY_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
+ {P6_3, UART_3, CY_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS, PCLK_SCB3_CLOCK)},
+ {P6_7, UART_6, CY_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
+ {P7_3, UART_4, CY_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
+ {P8_3, UART_4, CY_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
+ {P9_3, UART_2, CY_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)},
+ {P10_3, UART_1, CY_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)},
+ {P11_3, UART_5, CY_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
+ {P12_3, UART_6, CY_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_SERIAL
+
+
+#if DEVICE_I2C
+//*** I2C ***
+const PinMap PinMap_I2C_SCL[] = {
+ {P0_2, I2C_0, CY_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL, PCLK_SCB0_CLOCK)},
+ {P1_0, I2C_7, CY_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)},
+ {P5_0, I2C_5, CY_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
+ {P6_0, I2C_3, CY_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL, PCLK_SCB3_CLOCK)},
+ {P6_4, I2C_6, CY_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
+ {P7_0, I2C_4, CY_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
+ {P8_0, I2C_4, CY_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
+ {P9_0, I2C_2, CY_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)},
+ {P10_0, I2C_1, CY_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)},
+ {P11_0, I2C_5, CY_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
+ {P12_0, I2C_6, CY_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
+ {P13_0, I2C_6, CY_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_I2C_SDA[] = {
+ {P0_3, I2C_0, CY_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA, PCLK_SCB0_CLOCK)},
+ {P1_1, I2C_7, CY_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)},
+ {P5_1, I2C_5, CY_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
+ {P6_1, I2C_3, CY_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA, PCLK_SCB3_CLOCK)},
+ {P6_5, I2C_6, CY_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
+ {P7_1, I2C_4, CY_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
+ {P8_1, I2C_4, CY_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
+ {P9_1, I2C_2, CY_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)},
+ {P10_1, I2C_1, CY_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)},
+ {P11_1, I2C_5, CY_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
+ {P12_1, I2C_6, CY_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
+ {P13_1, I2C_6, CY_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_I2C
+
+#if DEVICE_SPI
+//*** SPI ***
+const PinMap PinMap_SPI_MOSI[] = {
+ {P0_2, SPI_0, CY_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI, PCLK_SCB0_CLOCK)},
+ {P1_0, SPI_7, CY_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)},
+ {P5_0, SPI_5, CY_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
+ {P6_0, SPI_3, CY_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI, PCLK_SCB3_CLOCK)},
+ {P6_4, SPI_6, CY_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
+ {P7_0, SPI_4, CY_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
+ {P8_0, SPI_4, CY_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
+ {P9_0, SPI_2, CY_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)},
+ {P10_0, SPI_1, CY_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)},
+ {P11_0, SPI_5, CY_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
+ {P12_0, SPI_6, CY_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
+ {P13_0, SPI_6, CY_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_SPI_MISO[] = {
+ {P0_3, SPI_0, CY_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO, PCLK_SCB0_CLOCK)},
+ {P1_1, SPI_7, CY_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)},
+ {P5_1, SPI_5, CY_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
+ {P6_1, SPI_3, CY_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO, PCLK_SCB3_CLOCK)},
+ {P6_5, SPI_6, CY_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
+ {P7_1, SPI_4, CY_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
+ {P8_1, SPI_4, CY_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
+ {P9_1, SPI_2, CY_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)},
+ {P10_1, SPI_1, CY_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)},
+ {P11_1, SPI_5, CY_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
+ {P12_1, SPI_6, CY_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
+ {P13_1, SPI_6, CY_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_SPI_SCLK[] = {
+ {P0_4, SPI_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK, PCLK_SCB0_CLOCK)},
+ {P1_2, SPI_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK, PCLK_SCB7_CLOCK)},
+ {P5_2, SPI_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
+ {P6_2, SPI_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK, PCLK_SCB3_CLOCK)},
+ {P6_6, SPI_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
+ {P7_2, SPI_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
+
+ {P8_2, SPI_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
+ {P9_2, SPI_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)},
+ {P10_2, SPI_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)},
+ {P11_2, SPI_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
+ {P12_2, SPI_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+const PinMap PinMap_SPI_SSEL[] = {
+ {P0_5, SPI_0, CY_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0, PCLK_SCB0_CLOCK)},
+ {P1_3, SPI_7, CY_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0, PCLK_SCB7_CLOCK)},
+ {P5_3, SPI_5, CY_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
+ {P6_3, SPI_3, CY_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0, PCLK_SCB3_CLOCK)},
+ {P6_7, SPI_6, CY_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
+ {P7_3, SPI_4, CY_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
+ {P8_3, SPI_4, CY_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
+ {P9_3, SPI_2, CY_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)},
+ {P10_3, SPI_1, CY_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)},
+ {P11_3, SPI_5, CY_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
+ {P12_3, SPI_6, CY_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_SPI
+
+#if DEVICE_PWMOUT
+//*** PWM ***
+const PinMap PinMap_PWM_OUT[] = {
+ // 16-bit PWM outputs
+ {P0_0, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
+ {P0_2, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
+ {P0_4, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
+ {P1_0, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
+ {P1_2, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
+ {P1_4, PWM_16b_13, CY_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
+ {P5_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
+ {P5_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
+ {P5_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
+ {P5_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
+ {P6_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
+ {P6_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)},
+ {P6_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)},
+ {P6_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
+ {P7_0, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
+ {P7_2, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
+ {P7_4, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14, PCLK_TCPWM1_CLOCKS14)},
+ {P7_6, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)},
+ {P8_0, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)},
+ {P8_2, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)},
+ {P8_4, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)},
+ {P8_6, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)},
+ {P9_0, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)},
+ {P9_2, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)},
+ {P9_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
+ {P9_6, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
+ {P10_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)},
+ {P10_2, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23, PCLK_TCPWM1_CLOCKS23)},
+ {P10_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
+ {P10_6, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
+ {P11_0, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
+ {P11_2, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
+ {P11_4, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
+ {P12_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
+ {P12_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
+ {P12_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
+ {P12_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
+ {P13_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
+ {P13_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
+ // 16-bit PWM inverted outputs
+ {P0_1, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
+ {P0_3, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
+ {P0_5, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
+ {P1_1, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
+ {P1_3, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
+ {P1_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
+ {P5_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
+ {P5_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
+ {P5_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
+ {P6_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
+ {P6_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)},
+ {P6_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)},
+ {P6_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
+ {P7_1, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
+ {P7_3, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13, PCLK_TCPWM1_CLOCKS13)},
+ {P7_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
+ {P7_7, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)},
+ {P8_1, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)},
+ {P8_3, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)},
+ {P8_5, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)},
+ {P8_7, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)},
+ {P9_1, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)},
+ {P9_3, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)},
+ {P9_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
+ {P9_7, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
+ {P10_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)},
+ {P10_3, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23, PCLK_TCPWM1_CLOCKS23)},
+ {P10_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
+ {P11_1, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
+ {P11_3, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
+ {P11_5, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
+ {P12_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
+ {P12_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
+ {P12_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
+ {P12_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)},
+ {P13_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
+ {P13_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
+ // 32-bit PWM outputs
+ {PWM32(P0_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P0_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P0_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P1_0), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P1_2), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P1_4), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P5_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P5_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P5_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P5_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P6_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P6_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P6_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P6_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P7_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P7_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P7_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P7_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P8_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P8_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P8_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P8_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P9_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P9_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P9_4), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P9_6), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P10_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P10_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P10_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P10_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P11_0), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P11_2), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P11_4), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P12_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P12_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P12_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P12_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P13_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P13_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
+ // 32-bit PWM inverted outputs
+ {PWM32(P0_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P0_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P0_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P1_1), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P1_3), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P1_5), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P5_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P5_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P5_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P6_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P6_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P6_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P6_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P7_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P7_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P7_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P7_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P8_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P8_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P8_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P8_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P9_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P9_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P9_5), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P9_7), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P10_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P10_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P10_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P11_1), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
+ {PWM32(P11_3), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
+ {PWM32(P11_5), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
+ {PWM32(P12_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
+ {PWM32(P12_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
+ {PWM32(P12_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
+ {PWM32(P12_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
+ {PWM32(P13_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
+ {PWM32(P13_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_PWMOUT
+
+#if DEVICE_ANALOGIN
+const PinMap PinMap_ADC[] = {
+ {P10_0, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_1, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_2, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_3, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_4, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_5, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_6, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {P10_7, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_ANALOGIN
+
+#if DEVICE_ANALOGOUT
+const PinMap PinMap_DAC[] = {
+ {P9_6, DAC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)},
+ {NC, NC, 0}
+};
+#endif // DEVICE_ANALOGIN
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/PDL_Version.txt Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,2 @@ +version 3.0.1 +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,207 @@
+#! armcc -E
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm0plus.scat
+;* \version 2.10
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+;* SPDX-License-Identifier: Apache-2.0
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+; RAM
+#define RAM_START 0x08000000
+#define RAM_SIZE 0x00010000
+; Flash
+; Flash
+#define FLASH_START 0x10000000
+#define FLASH_SIZE 0x00078000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ .cy_app_header +0
+ {
+ * (.cy_app_header)
+ }
+
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ .ANY (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ .cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,279 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +__initial_sp EQU 0x08010000 + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Saves and disables the interrupts +Cy_SaveIRQ PROC + EXPORT Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + + +; Restores the interrupts +Cy_RestoreIRQ PROC + EXPORT Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + ENDP + + +; Weak function for startup customization +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,393 @@
+/***************************************************************************//**
+* \file cy8c6xx7_cm0plus.ld
+* \version 2.10
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
+ */
+ ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x78000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .cy_app_header :
+ {
+ KEEP(*(.cy_app_header))
+ } > flash
+
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment copy table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+
+ /* To clear multiple BSS sections,
+ * uncomment zero table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,415 @@
+/**************************************************************************//**
+ * @file startup_psoc63_cm0plus.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ bl _start
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */
+ def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,216 @@
+/***************************************************************************//**
+* \file cy8c6xx7_cm0plus.icf
+* \version 2.10
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000;
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x10078000;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x4000;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO {first section .intvec, readonly};
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+
+/*-Placement-*/
+
+/* Flash */
+".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
+place in IROM1_region { block RO };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+".cy_xip" : place at start of EROM1_region { section .cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_app_header,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00100000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.S Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,417 @@
+;/**************************************************************************//**
+; * @file startup_psoc63_cm0plus.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0plus Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .intvec_ram:DATA:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ PUBLIC __ramVectors
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD 0x0000000D ; NMI_Handler is defined in ROM code
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External interrupts Power Mode Description
+ DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0
+ DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1
+ DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2
+ DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3
+ DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4
+ DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5
+ DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6
+ DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7
+ DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8
+ DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9
+ DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10
+ DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11
+ DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12
+ DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13
+ DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14
+ DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15
+ DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16
+ DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17
+ DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18
+ DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19
+ DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20
+ DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21
+ DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22
+ DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23
+ DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24
+ DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25
+ DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26
+ DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27
+ DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28
+ DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29
+ DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30
+ DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
+__ramVectors
+ DS32 __Vectors_Size
+
+
+ THUMB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default handlers
+;;
+ PUBWEAK Default_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Default_Handler
+ B Default_Handler
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Saves and disables the interrupts
+;;
+ PUBLIC Cy_SaveIRQ
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_SaveIRQ
+ MRS r0, PRIMASK
+ CPSID I
+ BX LR
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Restores the interrupts
+;;
+ PUBLIC Cy_RestoreIRQ
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_RestoreIRQ
+ MSR PRIMASK, r0
+ BX LR
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Weak function for startup customization
+;;
+ PUBWEAK Cy_OnResetUser
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_OnResetUser
+ BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+ ; Define strong function for startup customization
+ LDR R0, =Cy_OnResetUser
+ BLX R0
+
+ ; Copy vectors from ROM to RAM
+ LDR r1, =__vector_table
+ LDR r0, =__ramVectors
+ LDR r2, =__Vectors_Size
+intvec_copy
+ LDR r3, [r1]
+ STR r3, [r0]
+ ADDS r0, r0, #4
+ ADDS r1, r1, #4
+ SUBS r2, r2, #1
+ CMP r2, #0
+ BNE intvec_copy
+
+ ; Update Vector Table Offset Register
+ LDR r0, =__ramVectors
+ LDR r1, =0xE000ED08
+ STR r0, [r1]
+ dsb
+
+ LDR R0, =__iar_program_start
+ BLX R0
+
+; Should never get here
+Cy_Main_Exited
+ B Cy_Main_Exited
+
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+
+ PUBWEAK Cy_SysLib_FaultHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+Cy_SysLib_FaultHandler
+ B Cy_SysLib_FaultHandler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ IMPORT Cy_SysLib_FaultHandler
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq L_MSP
+ mrs r0, PSP
+ b L_API_call
+L_MSP
+ mrs r0, MSP
+L_API_call
+ ; Storing LR content for Creator call stack trace
+ push {LR}
+ bl Cy_SysLib_FaultHandler
+
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+ ; External interrupts
+ PUBWEAK NvicMux0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux0_IRQHandler
+ B NvicMux0_IRQHandler
+
+ PUBWEAK NvicMux1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux1_IRQHandler
+ B NvicMux1_IRQHandler
+
+ PUBWEAK NvicMux2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux2_IRQHandler
+ B NvicMux2_IRQHandler
+
+ PUBWEAK NvicMux3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux3_IRQHandler
+ B NvicMux3_IRQHandler
+
+ PUBWEAK NvicMux4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux4_IRQHandler
+ B NvicMux4_IRQHandler
+
+ PUBWEAK NvicMux5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux5_IRQHandler
+ B NvicMux5_IRQHandler
+
+ PUBWEAK NvicMux6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux6_IRQHandler
+ B NvicMux6_IRQHandler
+
+ PUBWEAK NvicMux7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux7_IRQHandler
+ B NvicMux7_IRQHandler
+
+ PUBWEAK NvicMux8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux8_IRQHandler
+ B NvicMux8_IRQHandler
+
+ PUBWEAK NvicMux9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux9_IRQHandler
+ B NvicMux9_IRQHandler
+
+ PUBWEAK NvicMux10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux10_IRQHandler
+ B NvicMux10_IRQHandler
+
+ PUBWEAK NvicMux11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux11_IRQHandler
+ B NvicMux11_IRQHandler
+
+ PUBWEAK NvicMux12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux12_IRQHandler
+ B NvicMux12_IRQHandler
+
+ PUBWEAK NvicMux13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux13_IRQHandler
+ B NvicMux13_IRQHandler
+
+ PUBWEAK NvicMux14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux14_IRQHandler
+ B NvicMux14_IRQHandler
+
+ PUBWEAK NvicMux15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux15_IRQHandler
+ B NvicMux15_IRQHandler
+
+ PUBWEAK NvicMux16_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux16_IRQHandler
+ B NvicMux16_IRQHandler
+
+ PUBWEAK NvicMux17_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux17_IRQHandler
+ B NvicMux17_IRQHandler
+
+ PUBWEAK NvicMux18_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux18_IRQHandler
+ B NvicMux18_IRQHandler
+
+ PUBWEAK NvicMux19_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux19_IRQHandler
+ B NvicMux19_IRQHandler
+
+ PUBWEAK NvicMux20_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux20_IRQHandler
+ B NvicMux20_IRQHandler
+
+ PUBWEAK NvicMux21_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux21_IRQHandler
+ B NvicMux21_IRQHandler
+
+ PUBWEAK NvicMux22_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux22_IRQHandler
+ B NvicMux22_IRQHandler
+
+ PUBWEAK NvicMux23_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux23_IRQHandler
+ B NvicMux23_IRQHandler
+
+ PUBWEAK NvicMux24_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux24_IRQHandler
+ B NvicMux24_IRQHandler
+
+ PUBWEAK NvicMux25_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux25_IRQHandler
+ B NvicMux25_IRQHandler
+
+ PUBWEAK NvicMux26_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux26_IRQHandler
+ B NvicMux26_IRQHandler
+
+ PUBWEAK NvicMux27_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux27_IRQHandler
+ B NvicMux27_IRQHandler
+
+ PUBWEAK NvicMux28_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux28_IRQHandler
+ B NvicMux28_IRQHandler
+
+ PUBWEAK NvicMux29_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux29_IRQHandler
+ B NvicMux29_IRQHandler
+
+ PUBWEAK NvicMux30_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux30_IRQHandler
+ B NvicMux30_IRQHandler
+
+ PUBWEAK NvicMux31_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux31_IRQHandler
+ B NvicMux31_IRQHandler
+
+
+ END
+
+
+; [] END OF FILE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/ipc_rpc_m0.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,38 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "psoc6_utils.h"
+#include "ipc_rpc.h"
+#include "rpc_defs.h"
+#include "cy_ipc_config.h"
+#include "ipc/cy_ipc_pipe.h"
+
+#define RPC_GEN RPC_GEN_IMPLEMENTATION
+#include "rpc_api.h"
+#undef RPC_GEN
+
+
+void ipcrpc_init(void)
+{
+ uint32_t rpc_counter = 0;
+
+#define RPC_GEN RPC_GEN_INITIALIZATION
+#include "rpc_api.h"
+#undef RPC_GEN
+}
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,636 @@
+/***************************************************************************//**
+* \file system_psoc63_cm0plus.c
+* \version 2.10
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2017-2018, Future Electronics
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "device.h"
+#include "system_psoc63.h"
+#include "cy_device_headers.h"
+#include "ipc_rpc.h"
+#include "psoc6_utils.h"
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ #if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+ #include "syslib/cy_syslib.h"
+ #endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+ #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "ipc/cy_ipc_drv.h"
+ #include "flash/cy_flash.h"
+ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_SLOWCLK_FREQ_HZ
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
+#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)
+ uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
+#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+/* WDT lock bits */
+#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u)
+#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u)
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
+ CY_DELAY_1K_THRESHOLD;
+
+uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
+ CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
+
+#define CY_ROOT_PATH_SRC_IMO (0UL)
+#define CY_ROOT_PATH_SRC_EXT (1UL)
+#if (SRSS_ECO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ECO (2UL)
+#endif /* (SRSS_ECO_PRESENT == 1U) */
+#if (SRSS_ALTHF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ALTHF (3UL)
+#endif /* (SRSS_ALTHF_PRESENT == 1U) */
+#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
+#if (SRSS_ALTLF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
+#endif /* (SRSS_ALTLF_PRESENT == 1U) */
+#if (SRSS_PILO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
+#endif /* (SRSS_PILO_PRESENT == 1U) */
+
+
+/*******************************************************************************
+* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
+*******************************************************************************/
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+
+
+/*******************************************************************************
+* Function Name: mbed_sdk_init
+****************************************************************************//**
+*
+* Mbed's post-memory-initialization function.
+* Used here to initialize common parts of the Cypress libraries.
+*
+*******************************************************************************/
+void mbed_sdk_init(void)
+{
+ /* Initialize shared resource manager */
+ cy_srm_initialize();
+ /* Initialize system and clocks. */
+ /* Placed here as it must be done after proper LIBC initialization. */
+ SystemInit();
+ /* Allocate and initialize semaphores for the system operations. */
+ Cy_IPC_SystemSemaInit();
+ Cy_IPC_SystemPipeInit();
+ Cy_Flash_Init();
+ ipcrpc_init();
+}
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+*
+* Initializes the system:
+* - Restores FLL registers to the default state.
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+*
+*******************************************************************************/
+void SystemInit(void)
+{
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0);
+ SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1);
+ SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk);
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* Allocate and initialize semaphores for the system operations. */
+ Cy_IPC_SystemSemaInit();
+ Cy_IPC_SystemPipeInit();
+ Cy_Flash_Init();
+ #endif /* CY_IPC_DEFAULT_CFG_DISABLE */
+
+ #if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+ if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
+ {
+ /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+ IPC_STRUCT7->DATA = 0UL;
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ IPC_STRUCT7->RELEASE = 0UL;
+ }
+ #endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+#endif /* CY_DEVICE_PSOC6ABLE2 */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t srcFreqHz;
+ uint32_t pathFreqHz;
+ uint32_t slowClkDiv;
+ uint32_t periClkDiv;
+ uint32_t rootPath;
+ uint32_t srcClk;
+
+ /* Get root path clock for the high-frequency clock # 0 */
+ rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
+
+ /* Get source of the root path clock */
+ srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
+
+ /* Get frequency of the source */
+ switch (srcClk)
+ {
+ case CY_ROOT_PATH_SRC_IMO:
+ srcFreqHz = CY_CLK_IMO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_EXT:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+
+ #if (SRSS_ECO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ECO:
+ srcFreqHz = CY_CLK_ECO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ECO_PRESENT == 1U) */
+
+#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ALTHF:
+ srcFreqHz = cy_BleEcoClockFreqHz;
+ break;
+#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
+
+ case CY_ROOT_PATH_SRC_DSI_MUX:
+ {
+ uint32_t dsi_src;
+ dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
+ switch (dsi_src)
+ {
+ case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
+ srcFreqHz = CY_CLK_WCO_FREQ_HZ;
+ break;
+
+ #if (SRSS_ALTLF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
+ srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ALTLF_PRESENT == 1U) */
+
+ #if (SRSS_PILO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
+ srcFreqHz = CY_CLK_PILO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_PILO_PRESENT == 1U) */
+
+ default:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+ }
+ }
+ break;
+
+ default:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+ }
+
+ if (rootPath == 0UL)
+ {
+ /* FLL */
+ bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
+ bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
+ bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
+ (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
+ if ((fllOutputAuto && fllLocked) || fllOutputOutput)
+ {
+ uint32_t fllMult;
+ uint32_t refDiv;
+ uint32_t outputDiv;
+
+ fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
+ refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
+ outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
+
+ pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else if (rootPath == 1UL)
+ {
+ /* PLL */
+ bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL]));
+ bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]));
+ bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) ||
+ (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])));
+ if ((pllOutputAuto && pllLocked) || pllOutputOutput)
+ {
+ uint32_t feedbackDiv;
+ uint32_t referenceDiv;
+ uint32_t outputDiv;
+
+ feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+ referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+ outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+
+ pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
+
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else
+ {
+ /* Direct */
+ pathFreqHz = srcFreqHz;
+ }
+
+ /* Get frequency after hf_clk pre-divider */
+ pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
+ cy_Hfclk0FreqHz = pathFreqHz;
+
+ /* Slow Clock Divider */
+ slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+
+ /* Peripheral Clock Divider */
+ periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+
+ pathFreqHz = pathFreqHz / periClkDiv;
+ cy_PeriClkFreqHz = pathFreqHz;
+ pathFreqHz = pathFreqHz / slowClkDiv;
+ SystemCoreClock = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqHz = SystemCoreClock;
+ cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+}
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+ uint32_t regValue;
+
+ /* Get current power mode */
+ regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+ return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+ uint32_t regValue;
+ uint32_t interruptState;
+ uint32_t cpuState;
+
+ interruptState = Cy_SaveIRQ();
+
+ cpuState = Cy_SysGetCM4Status();
+ if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+ {
+ Cy_SysResetCM4();
+ }
+
+ CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_ENABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_RestoreIRQ(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SaveIRQ();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_DISABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_RestoreIRQ(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SaveIRQ();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RETAINED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ Cy_RestoreIRQ(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SaveIRQ();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RESET;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_RestoreIRQ(interruptState);
+}
+#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/PDL_Version.txt Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,2 @@ +version 3.0.1 +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,212 @@
+#! armcc -E
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.scat
+;* \version 2.10
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+;* SPDX-License-Identifier: Apache-2.0
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+; RAM
+#define RAM_START 0x08010000
+#define RAM_SIZE 0x00037800
+; Flash
+; Flash
+#define FLASH_START 0x10080000
+#define FLASH_SIZE 0x00078000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START 0x14000000
+#define EM_EEPROM_SIZE 0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START 0x16000800
+#define SFLASH_USER_DATA_SIZE 0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START 0x16001A00
+#define SFLASH_NAR_SIZE 0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START 0x16007C00
+#define SFLASH_TOC_2_SIZE 0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START 0x16007E00
+#define SFLASH_RTOC_2_SIZE 0x00000200
+
+; External memory
+#define XIP_START 0x18000000
+#define XIP_SIZE 0x08000000
+
+; eFuse
+#define EFUSE_START 0x90700000
+#define EFUSE_SIZE 0x100000
+
+
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+ ER_FLASH_VECTORS +0
+ {
+ * (RESET, +FIRST)
+ }
+
+ ER_FLASH_CODE +0 FIXED
+ {
+ * (InRoot$$Sections)
+ * (+RO)
+ }
+
+ ER_RAM_VECTORS RAM_START UNINIT
+ {
+ * (RESET_RAM, +FIRST)
+ }
+
+ RW_RAM_DATA +0
+ {
+ * (.cy_ramfunc)
+ .ANY (+RW, +ZI)
+ }
+
+ ; Place variables in the section that should not be initialized during the
+ ; device startup.
+ RW_IRAM1 +0 UNINIT
+ {
+ * (.noinit)
+ }
+
+ ; Used for the digital signature of the secure application and the
+ ; Bootloader SDK appication. The size of the section depends on the required
+ ; data size.
+ .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+ {
+ * (.cy_app_signature)
+ }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+ .cy_em_eeprom +0
+ {
+ * (.cy_em_eeprom)
+ }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+ .cy_sflash_user_data +0
+ {
+ * (.cy_sflash_user_data)
+ }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+ .cy_sflash_nar +0
+ {
+ * (.cy_sflash_nar)
+ }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+ .cy_sflash_public_key +0
+ {
+ * (.cy_sflash_public_key)
+ }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+ .cy_toc_part2 +0
+ {
+ * (.cy_toc_part2)
+ }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+ .cy_rtoc_part2 +0
+ {
+ * (.cy_rtoc_part2)
+ }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+ .cy_xip +0
+ {
+ * (.cy_xip)
+ }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+ .cy_efuse +0
+ {
+ * (.cy_efuse)
+ }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+ .cymeta +0 { * (.cymeta) }
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,654 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x08047800 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Power Mode Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Saves and disables the interrupts +Cy_SaveIRQ PROC + EXPORT Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + + +; Restores the interrupts +Cy_RestoreIRQ PROC + EXPORT Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + ENDP + + +; Weak function for startup customization +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,399 @@
+/***************************************************************************//**
+* \file cy8c6xx7_cm4_dual.ld
+* \version 2.10
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+ * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+ */
+ ram (rwx) : ORIGIN = 0x08010000, LENGTH = 0x37800
+ flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x78000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment copy table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+
+ /* To clear multiple BSS sections,
+ * uncomment zero table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ : AT (__etext)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK appication.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ .cy_xip :
+ {
+ KEEP(*(.cy_xip))
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00100000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,641 @@
+/**************************************************************************//**
+ * @file startup_psoc63_cm4.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /* Device startup customization */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Saves and disables the interrupts */
+ .global Cy_SaveIRQ
+ .func Cy_SaveIRQ, Cy_SaveIRQ
+ .type Cy_SaveIRQ, %function
+Cy_SaveIRQ:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+ .size Cy_SaveIRQ, . - Cy_SaveIRQ
+ .endfunc
+
+ /* Restores the interrupts */
+ .global Cy_RestoreIRQ
+ .func Cy_RestoreIRQ, Cy_RestoreIRQ
+ .type Cy_RestoreIRQ, %function
+Cy_RestoreIRQ:
+ msr PRIMASK, r0
+ bx lr
+ .size Cy_RestoreIRQ, . - Cy_RestoreIRQ
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ bl Cy_OnResetUser
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+ bl _start
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+
+ .type Fault_Handler, %function
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+.L_API_call:
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+ .end
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,217 @@
+/***************************************************************************//**
+* \file cy8c6xx7_cm4_dual.icf
+* \version 2.10
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x100F8000;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+ define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+ define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+ define symbol __ICFEDIT_size_heap__ = 0x3800;
+} else {
+ define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO {first section .intvec, readonly};
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize { section .noinit, section .intvec_ram };
+
+
+/*-Placement-*/
+
+/* Flash */
+place at start of IROM1_region { block RO };
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+".cy_xip" : place at start of EROM1_region { section .cy_xip };
+
+/* RAM */
+place at start of IRAM1_region { readwrite section .intvec_ram};
+place in IRAM1_region { readwrite };
+place at end of IRAM1_region { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep { section .cy_app_signature,
+ section .cy_em_eeprom,
+ section .cy_sflash_user_data,
+ section .cy_sflash_nar,
+ section .cy_sflash_public_key,
+ section .cy_toc_part2,
+ section .cy_rtoc_part2,
+ section .cy_efuse,
+ section .cy_xip,
+ section .cymeta,
+ };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start = 0x10000000;
+define exported symbol __cy_memory_0_length = 0x00100000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start = 0x14000000;
+define exported symbol __cy_memory_1_length = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start = 0x16000000;
+define exported symbol __cy_memory_2_length = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start = 0x18000000;
+define exported symbol __cy_memory_3_length = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start = 0x90700000;
+define exported symbol __cy_memory_4_length = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.S Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1148 @@
+;/**************************************************************************//**
+; * @file startup_psoc63_cm4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device Series
+; * @version V5.00
+; * @date 08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .intvec_ram:DATA:NOROOT(2)
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN Cy_SystemInitFpuEnable
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ PUBLIC __ramVectors
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD 0x0000000D ; NMI_Handler is defined in ROM code
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+
+ ; External interrupts Description
+ DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
+ DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
+ DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
+ DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
+ DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
+ DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
+ DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
+ DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
+ DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
+ DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
+ DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
+ DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
+ DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
+ DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
+ DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
+ DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
+ DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
+ DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
+ DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
+ DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
+ DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
+ DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
+ DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
+ DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
+ DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
+ DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
+ DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
+ DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
+ DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
+ DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
+ DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
+ DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
+ DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
+ DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
+ DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
+ DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
+ DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
+ DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
+ DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
+ DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
+ DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
+ DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
+ DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
+ DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
+ DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
+ DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
+ DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
+ DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
+ DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
+ DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
+ DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
+ DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
+ DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
+ DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
+ DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
+ DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
+ DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
+ DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
+ DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
+ DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
+ DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
+ DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
+ DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
+ DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
+ DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
+ DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
+ DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
+ DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
+ DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
+ DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
+ DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
+ DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
+ DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
+ DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
+ DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
+ DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
+ DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
+ DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
+ DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
+ DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
+ DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
+ DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
+ DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
+ DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
+ DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
+ DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
+ DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
+ DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
+ DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
+ DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
+ DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
+ DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
+ DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
+ DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
+ DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
+ DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
+ DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
+ DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
+ DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
+ DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
+ DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
+ DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
+ DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
+ DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
+ DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
+ DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
+ DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
+ DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
+ DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
+ DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
+ DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
+ DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
+ DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
+ DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
+ DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
+ DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
+ DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
+ DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
+ DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
+ DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
+ DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
+ DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
+ DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
+ DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
+ DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
+ DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
+ DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
+ DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
+ DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
+ DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
+ DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
+ DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
+ DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
+ DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
+ DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
+ DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
+ DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
+ DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
+ DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
+ DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
+ DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
+ DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
+ DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_med_IRQHandler ; USB Interrupt
+ DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
+ DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
+__ramVectors
+ DS32 __Vectors_Size
+
+
+ THUMB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default handlers
+;;
+ PUBWEAK Default_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Default_Handler
+ B Default_Handler
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Saves and disables the interrupts
+;;
+ PUBLIC Cy_SaveIRQ
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_SaveIRQ
+ MRS r0, PRIMASK
+ CPSID I
+ BX LR
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Restores the interrupts
+;;
+ PUBLIC Cy_RestoreIRQ
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_RestoreIRQ
+ MSR PRIMASK, r0
+ BX LR
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Weak function for startup customization
+;;
+ PUBWEAK Cy_OnResetUser
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_OnResetUser
+ BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Define strong version to return zero for
+;; __iar_program_start to skip data sections
+;; initialization.
+;;
+ PUBLIC __low_level_init
+ SECTION .text:CODE:REORDER:NOROOT(2)
+__low_level_init
+ MOVS R0, #1
+ BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+ ; Define strong function for startup customization
+ LDR R0, =Cy_OnResetUser
+ BLX R0
+
+ ; Copy vectors from ROM to RAM
+ LDR r1, =__vector_table
+ LDR r0, =__ramVectors
+ LDR r2, =__Vectors_Size
+intvec_copy
+ LDR r3, [r1]
+ STR r3, [r0]
+ ADDS r0, r0, #4
+ ADDS r1, r1, #4
+ SUBS r2, r2, #1
+ CMP r2, #0
+ BNE intvec_copy
+
+ ; Update Vector Table Offset Register
+ LDR r0, =__ramVectors
+ LDR r1, =0xE000ED08
+ STR r0, [r1]
+ dsb
+
+ ; Enable the FPU if used
+ LDR R0, =Cy_SystemInitFpuEnable
+ BLX R0
+
+ LDR R0, =__iar_program_start
+ BLX R0
+
+; Should never get here
+Cy_Main_Exited
+ B Cy_Main_Exited
+
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+
+ PUBWEAK Cy_SysLib_FaultHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+Cy_SysLib_FaultHandler
+ B Cy_SysLib_FaultHandler
+
+ PUBWEAK HardFault_Wrapper
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Wrapper
+ IMPORT Cy_SysLib_FaultHandler
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq L_MSP
+ mrs r0, PSP
+ b L_API_call
+L_MSP
+ mrs r0, MSP
+L_API_call
+ ; Storing LR content for Creator call stack trace
+ push {LR}
+ bl Cy_SysLib_FaultHandler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Wrapper
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B HardFault_Wrapper
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B HardFault_Wrapper
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B HardFault_Wrapper
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+ ; External interrupts
+ PUBWEAK ioss_interrupts_gpio_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_0_IRQHandler
+ B ioss_interrupts_gpio_0_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_1_IRQHandler
+ B ioss_interrupts_gpio_1_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_2_IRQHandler
+ B ioss_interrupts_gpio_2_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_3_IRQHandler
+ B ioss_interrupts_gpio_3_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_4_IRQHandler
+ B ioss_interrupts_gpio_4_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_5_IRQHandler
+ B ioss_interrupts_gpio_5_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_6_IRQHandler
+ B ioss_interrupts_gpio_6_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_7_IRQHandler
+ B ioss_interrupts_gpio_7_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_8_IRQHandler
+ B ioss_interrupts_gpio_8_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_9_IRQHandler
+ B ioss_interrupts_gpio_9_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_10_IRQHandler
+ B ioss_interrupts_gpio_10_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_11_IRQHandler
+ B ioss_interrupts_gpio_11_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_12_IRQHandler
+ B ioss_interrupts_gpio_12_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_13_IRQHandler
+ B ioss_interrupts_gpio_13_IRQHandler
+
+ PUBWEAK ioss_interrupts_gpio_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupts_gpio_14_IRQHandler
+ B ioss_interrupts_gpio_14_IRQHandler
+
+ PUBWEAK ioss_interrupt_gpio_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupt_gpio_IRQHandler
+ B ioss_interrupt_gpio_IRQHandler
+
+ PUBWEAK ioss_interrupt_vdd_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ioss_interrupt_vdd_IRQHandler
+ B ioss_interrupt_vdd_IRQHandler
+
+ PUBWEAK lpcomp_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+lpcomp_interrupt_IRQHandler
+ B lpcomp_interrupt_IRQHandler
+
+ PUBWEAK scb_8_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_8_interrupt_IRQHandler
+ B scb_8_interrupt_IRQHandler
+
+ PUBWEAK srss_interrupt_mcwdt_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+srss_interrupt_mcwdt_0_IRQHandler
+ B srss_interrupt_mcwdt_0_IRQHandler
+
+ PUBWEAK srss_interrupt_mcwdt_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+srss_interrupt_mcwdt_1_IRQHandler
+ B srss_interrupt_mcwdt_1_IRQHandler
+
+ PUBWEAK srss_interrupt_backup_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+srss_interrupt_backup_IRQHandler
+ B srss_interrupt_backup_IRQHandler
+
+ PUBWEAK srss_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+srss_interrupt_IRQHandler
+ B srss_interrupt_IRQHandler
+
+ PUBWEAK pass_interrupt_ctbs_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+pass_interrupt_ctbs_IRQHandler
+ B pass_interrupt_ctbs_IRQHandler
+
+ PUBWEAK bless_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+bless_interrupt_IRQHandler
+ B bless_interrupt_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_0_IRQHandler
+ B cpuss_interrupts_ipc_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_1_IRQHandler
+ B cpuss_interrupts_ipc_1_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_2_IRQHandler
+ B cpuss_interrupts_ipc_2_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_3_IRQHandler
+ B cpuss_interrupts_ipc_3_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_4_IRQHandler
+ B cpuss_interrupts_ipc_4_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_5_IRQHandler
+ B cpuss_interrupts_ipc_5_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_6_IRQHandler
+ B cpuss_interrupts_ipc_6_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_7_IRQHandler
+ B cpuss_interrupts_ipc_7_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_8_IRQHandler
+ B cpuss_interrupts_ipc_8_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_9_IRQHandler
+ B cpuss_interrupts_ipc_9_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_10_IRQHandler
+ B cpuss_interrupts_ipc_10_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_11_IRQHandler
+ B cpuss_interrupts_ipc_11_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_12_IRQHandler
+ B cpuss_interrupts_ipc_12_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_13_IRQHandler
+ B cpuss_interrupts_ipc_13_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_14_IRQHandler
+ B cpuss_interrupts_ipc_14_IRQHandler
+
+ PUBWEAK cpuss_interrupts_ipc_15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_ipc_15_IRQHandler
+ B cpuss_interrupts_ipc_15_IRQHandler
+
+ PUBWEAK scb_0_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_0_interrupt_IRQHandler
+ B scb_0_interrupt_IRQHandler
+
+ PUBWEAK scb_1_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_1_interrupt_IRQHandler
+ B scb_1_interrupt_IRQHandler
+
+ PUBWEAK scb_2_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_2_interrupt_IRQHandler
+ B scb_2_interrupt_IRQHandler
+
+ PUBWEAK scb_3_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_3_interrupt_IRQHandler
+ B scb_3_interrupt_IRQHandler
+
+ PUBWEAK scb_4_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_4_interrupt_IRQHandler
+ B scb_4_interrupt_IRQHandler
+
+ PUBWEAK scb_5_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_5_interrupt_IRQHandler
+ B scb_5_interrupt_IRQHandler
+
+ PUBWEAK scb_6_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_6_interrupt_IRQHandler
+ B scb_6_interrupt_IRQHandler
+
+ PUBWEAK scb_7_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+scb_7_interrupt_IRQHandler
+ B scb_7_interrupt_IRQHandler
+
+ PUBWEAK csd_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+csd_interrupt_IRQHandler
+ B csd_interrupt_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_0_IRQHandler
+ B cpuss_interrupts_dw0_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_1_IRQHandler
+ B cpuss_interrupts_dw0_1_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_2_IRQHandler
+ B cpuss_interrupts_dw0_2_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_3_IRQHandler
+ B cpuss_interrupts_dw0_3_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_4_IRQHandler
+ B cpuss_interrupts_dw0_4_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_5_IRQHandler
+ B cpuss_interrupts_dw0_5_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_6_IRQHandler
+ B cpuss_interrupts_dw0_6_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_7_IRQHandler
+ B cpuss_interrupts_dw0_7_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_8_IRQHandler
+ B cpuss_interrupts_dw0_8_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_9_IRQHandler
+ B cpuss_interrupts_dw0_9_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_10_IRQHandler
+ B cpuss_interrupts_dw0_10_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_11_IRQHandler
+ B cpuss_interrupts_dw0_11_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_12_IRQHandler
+ B cpuss_interrupts_dw0_12_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_13_IRQHandler
+ B cpuss_interrupts_dw0_13_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_14_IRQHandler
+ B cpuss_interrupts_dw0_14_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw0_15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw0_15_IRQHandler
+ B cpuss_interrupts_dw0_15_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_0_IRQHandler
+ B cpuss_interrupts_dw1_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_1_IRQHandler
+ B cpuss_interrupts_dw1_1_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_2_IRQHandler
+ B cpuss_interrupts_dw1_2_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_3_IRQHandler
+ B cpuss_interrupts_dw1_3_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_4_IRQHandler
+ B cpuss_interrupts_dw1_4_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_5_IRQHandler
+ B cpuss_interrupts_dw1_5_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_6_IRQHandler
+ B cpuss_interrupts_dw1_6_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_7_IRQHandler
+ B cpuss_interrupts_dw1_7_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_8_IRQHandler
+ B cpuss_interrupts_dw1_8_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_9_IRQHandler
+ B cpuss_interrupts_dw1_9_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_10_IRQHandler
+ B cpuss_interrupts_dw1_10_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_11_IRQHandler
+ B cpuss_interrupts_dw1_11_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_12_IRQHandler
+ B cpuss_interrupts_dw1_12_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_13_IRQHandler
+ B cpuss_interrupts_dw1_13_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_14_IRQHandler
+ B cpuss_interrupts_dw1_14_IRQHandler
+
+ PUBWEAK cpuss_interrupts_dw1_15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_dw1_15_IRQHandler
+ B cpuss_interrupts_dw1_15_IRQHandler
+
+ PUBWEAK cpuss_interrupts_fault_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_fault_0_IRQHandler
+ B cpuss_interrupts_fault_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_fault_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_fault_1_IRQHandler
+ B cpuss_interrupts_fault_1_IRQHandler
+
+ PUBWEAK cpuss_interrupt_crypto_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupt_crypto_IRQHandler
+ B cpuss_interrupt_crypto_IRQHandler
+
+ PUBWEAK cpuss_interrupt_fm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupt_fm_IRQHandler
+ B cpuss_interrupt_fm_IRQHandler
+
+ PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_cm0_cti_0_IRQHandler
+ B cpuss_interrupts_cm0_cti_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_cm0_cti_1_IRQHandler
+ B cpuss_interrupts_cm0_cti_1_IRQHandler
+
+ PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_cm4_cti_0_IRQHandler
+ B cpuss_interrupts_cm4_cti_0_IRQHandler
+
+ PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+cpuss_interrupts_cm4_cti_1_IRQHandler
+ B cpuss_interrupts_cm4_cti_1_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_0_IRQHandler
+ B tcpwm_0_interrupts_0_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_1_IRQHandler
+ B tcpwm_0_interrupts_1_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_2_IRQHandler
+ B tcpwm_0_interrupts_2_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_3_IRQHandler
+ B tcpwm_0_interrupts_3_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_4_IRQHandler
+ B tcpwm_0_interrupts_4_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_5_IRQHandler
+ B tcpwm_0_interrupts_5_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_6_IRQHandler
+ B tcpwm_0_interrupts_6_IRQHandler
+
+ PUBWEAK tcpwm_0_interrupts_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_0_interrupts_7_IRQHandler
+ B tcpwm_0_interrupts_7_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_0_IRQHandler
+ B tcpwm_1_interrupts_0_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_1_IRQHandler
+ B tcpwm_1_interrupts_1_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_2_IRQHandler
+ B tcpwm_1_interrupts_2_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_3_IRQHandler
+ B tcpwm_1_interrupts_3_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_4_IRQHandler
+ B tcpwm_1_interrupts_4_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_5_IRQHandler
+ B tcpwm_1_interrupts_5_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_6_IRQHandler
+ B tcpwm_1_interrupts_6_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_7_IRQHandler
+ B tcpwm_1_interrupts_7_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_8_IRQHandler
+ B tcpwm_1_interrupts_8_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_9_IRQHandler
+ B tcpwm_1_interrupts_9_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_10_IRQHandler
+ B tcpwm_1_interrupts_10_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_11_IRQHandler
+ B tcpwm_1_interrupts_11_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_12_IRQHandler
+ B tcpwm_1_interrupts_12_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_13_IRQHandler
+ B tcpwm_1_interrupts_13_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_14_IRQHandler
+ B tcpwm_1_interrupts_14_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_15_IRQHandler
+ B tcpwm_1_interrupts_15_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_16_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_16_IRQHandler
+ B tcpwm_1_interrupts_16_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_17_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_17_IRQHandler
+ B tcpwm_1_interrupts_17_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_18_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_18_IRQHandler
+ B tcpwm_1_interrupts_18_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_19_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_19_IRQHandler
+ B tcpwm_1_interrupts_19_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_20_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_20_IRQHandler
+ B tcpwm_1_interrupts_20_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_21_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_21_IRQHandler
+ B tcpwm_1_interrupts_21_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_22_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_22_IRQHandler
+ B tcpwm_1_interrupts_22_IRQHandler
+
+ PUBWEAK tcpwm_1_interrupts_23_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+tcpwm_1_interrupts_23_IRQHandler
+ B tcpwm_1_interrupts_23_IRQHandler
+
+ PUBWEAK udb_interrupts_0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_0_IRQHandler
+ B udb_interrupts_0_IRQHandler
+
+ PUBWEAK udb_interrupts_1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_1_IRQHandler
+ B udb_interrupts_1_IRQHandler
+
+ PUBWEAK udb_interrupts_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_2_IRQHandler
+ B udb_interrupts_2_IRQHandler
+
+ PUBWEAK udb_interrupts_3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_3_IRQHandler
+ B udb_interrupts_3_IRQHandler
+
+ PUBWEAK udb_interrupts_4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_4_IRQHandler
+ B udb_interrupts_4_IRQHandler
+
+ PUBWEAK udb_interrupts_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_5_IRQHandler
+ B udb_interrupts_5_IRQHandler
+
+ PUBWEAK udb_interrupts_6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_6_IRQHandler
+ B udb_interrupts_6_IRQHandler
+
+ PUBWEAK udb_interrupts_7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_7_IRQHandler
+ B udb_interrupts_7_IRQHandler
+
+ PUBWEAK udb_interrupts_8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_8_IRQHandler
+ B udb_interrupts_8_IRQHandler
+
+ PUBWEAK udb_interrupts_9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_9_IRQHandler
+ B udb_interrupts_9_IRQHandler
+
+ PUBWEAK udb_interrupts_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_10_IRQHandler
+ B udb_interrupts_10_IRQHandler
+
+ PUBWEAK udb_interrupts_11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_11_IRQHandler
+ B udb_interrupts_11_IRQHandler
+
+ PUBWEAK udb_interrupts_12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_12_IRQHandler
+ B udb_interrupts_12_IRQHandler
+
+ PUBWEAK udb_interrupts_13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_13_IRQHandler
+ B udb_interrupts_13_IRQHandler
+
+ PUBWEAK udb_interrupts_14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_14_IRQHandler
+ B udb_interrupts_14_IRQHandler
+
+ PUBWEAK udb_interrupts_15_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+udb_interrupts_15_IRQHandler
+ B udb_interrupts_15_IRQHandler
+
+ PUBWEAK pass_interrupt_sar_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+pass_interrupt_sar_IRQHandler
+ B pass_interrupt_sar_IRQHandler
+
+ PUBWEAK audioss_interrupt_i2s_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+audioss_interrupt_i2s_IRQHandler
+ B audioss_interrupt_i2s_IRQHandler
+
+ PUBWEAK audioss_interrupt_pdm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+audioss_interrupt_pdm_IRQHandler
+ B audioss_interrupt_pdm_IRQHandler
+
+ PUBWEAK profile_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+profile_interrupt_IRQHandler
+ B profile_interrupt_IRQHandler
+
+ PUBWEAK smif_interrupt_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+smif_interrupt_IRQHandler
+ B smif_interrupt_IRQHandler
+
+ PUBWEAK usb_interrupt_hi_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+usb_interrupt_hi_IRQHandler
+ B usb_interrupt_hi_IRQHandler
+
+ PUBWEAK usb_interrupt_med_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+usb_interrupt_med_IRQHandler
+ B usb_interrupt_med_IRQHandler
+
+ PUBWEAK usb_interrupt_lo_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+usb_interrupt_lo_IRQHandler
+ B usb_interrupt_lo_IRQHandler
+
+ PUBWEAK pass_interrupt_dacs_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+pass_interrupt_dacs_IRQHandler
+ B pass_interrupt_dacs_IRQHandler
+
+
+ END
+
+
+; [] END OF FILE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/LICENSE.txt Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,52 @@ +Copyright (c) 2017-2018 Future Electronics. +Copyright (c) 2007-2018 Cypress Semiconductor. + +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,1655 @@ +:020000041000EA +:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC +:400040009101001061080010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001089 +:400080009101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001020 +:4000C00010B5064C2378002B07D1054B002B02D0044800E000BF0123237010BD2819000800000000C0510010084B10B5002B03D00749084800E000BF07480368002B00D11A +:4001000010BD064B002BFBD09847F9E7000000002C190008C051001094020008000000007047EFF3108072B6704780F310887047FFF7F6FF72B6104C104DAC4209DA2168F0 +:400140006268A368043B02DBC858D050FAE70C34F3E70B490B4A0020521A02DD043A8850FCDC094809490860BFF34F8F00F0FCF800F01EF8FEE70000E4950110FC950110BB +:40018000281900089C2800080000000808ED00E0FEE7FEE700B504207146084202D0EFF3098001E0EFF30880043001F067FEFEE7002110B5080000F063FA002000F0C2FAAB +:4001C00000F0DEF962B60B4B5B689B0301D501F0F7FD002000F09CFDFA20400001F006FE054800F031F905F0BBF8002001F0AEFDF9E7C0460000264000000810F8B5E023D7 +:40020000504C9B00E2580F231340D022990092000919885807224C4D0240032A05D0042A05D0002A0FD0494811E028680FE0C022920089581F220A40112A01D0132A04D198 +:400240008020000203E0424801E0FA20C001002B27D1B223B1210322DB00C900E658635867581B0F3F0F1340174205D0354F7958090F0A40012A01D1F20701D4032B3AD1B4 +:40028000B023344ADB00E658A158E758C904C90C02F0B8FBB603F901B60BC90F7043013127E0012B27D1C823C0210322DB00C900E658635867583F0F174205D0214F7958EF +:4002C000090F0A40012A01D1F20703D49B009B0F032B10D1C0227F23D200A758A1583B401F27A658090A3940584302F08BFB310C394002F087FBE0239B00E3589B069B0F81 +:40030000D840154B68601C691969240A090E013102F078FBE1B2A860013102F073FB0F4BE860286104000E49C01802F06BFBFA210C4B28758900E01802F064FBA861C0030A +:40034000E861F8BD00002640C000000800366E0100127A0084050000000021403F420F0040420F00E7030000B021E02010B530241F4BC9005A588000520052085A501A5814 +:40038000A2431A50802252045A501A491A4A80209950A021043289019950FF21174AC005995081315A5892009208024380205A505A580006024301205A505A5882435A505B +:4003C00000F06CFBFFF71AFF00F056FA00F05EFA01F0EAF9B0235B055A78002A02D05B78212B03D10022064BDA605A6010BDC0460000264001000200840500008C0500008A +:40040000E0002340024BD86F032318407047C0460400214010B5FFF784FE074A074BD16F0B4007490B43D367102306490A681A42FCD0FFF77AFE10BD04002140FCFF00004B +:400440000100FA058800214070B50F4C0600FFF768FEE36F0500DB439B0701D1FFF7DAFFB0230A4A9B00D650E26F094B09491340094A1343E36710230A681A42FCD02800DF +:40048000FFF753FE70BDC0460400214000002140FCFF0000880021400300FA05436870B50400012B02D1007B06F07CF92500A2682B1B01359A4203D9E87B06F073F9F6E758 +:4004C00070BD000010B5034A0349002000F0C4FA10BDC046B96700109D04001007B50022030000911000110000F03AFA07BD10B500F0ACFA10BD10B500F0CAFA10BD10B541 +:400500000400007B00F0F2F8606010BD10B50400007B216900F0B4F8606010BD10B5037B0169180000F0CCF810BD10B50400C06800F008F9606010BD10B5C06800F016F93D +:4005400010BD10B50400C06800F022F9606010BD10B5C06800F036F910BD10B504000C23C05E00F055F8606010BD10B50C23C05E00F06EF810BD10B5C06800F035F910BD5F +:4005800010B500221849042000F0F4FD01221749042000F0EFFD02221549042000F0EAFD03221449042000F0E5FD04221249100000F0E0FD05221149042000F0DBFD062283 +:4005C0000F49042000F0D6FD07220E49042000F0D1FD08220C49042000F0CCFD09220B49042000F0C7FD10BDFF0400100D0500101D0500102B05001039050010430500108D +:40060000510500105B0500106B0500107705001070B507260512EDB206400D2D11D801F094FC0A4901224B5D1C003441144003D1B24013434B5501E00124644201F089FC05 +:4006400001E001246442200070BDC0464419000870B50412E4B20D2C0FD80725054001F074FC064901220B5D1E002E41164202D0AA4093430B5501F06CFC70BD44190008B7 +:40068000F8B50C00050001F060FC0C2301225D431300A3401A00094E71198F683A4008D13B43AD598B60631C4B60AB4202D94A6000E0FF2401F04DFC2000F8BDE0000008FD +:4006C00070B50C00050001F040FC01210C23A1406B43054AD3189A680A4201D08A439A6001F037FC70BDC046E0000008F0B50C2485B0019001F029FC019B114D5C432B19CA +:400700005B68029003932E1971680198FFF7B8FF0700FF280DD173682A59934201D9002373602A1953680399994202D001335360E9E7029801F00DFC380005B0F0BDC04627 +:40074000E000000810B5040007280AD801F0FDFB054B0E331A5D002A01D101321A5501F0F8FB0120404210BD4419000810B5040007280AD801F0E9FB044B0E331A5D012A8E +:4007800001D100221A5501F0E4FB10BD4419000870B505001F280ED801F0D7FB084B30335C5D002C02D101225A5501E00124644201F0CFFB01E001246442200070BDC04614 +:4007C000E000000810B504001F280AD801F0BDFB044B30331A5D012A01D100221A5501F0B8FB10BDE000000870B5B024C025144B144A15496405ED00E35CA25C615C665D5A +:400800003F251F242A400C4024039201224311002B407F2219430B003240520413430B4A1C0A110050310B701B0C8B7000234C7011005031595CC1540133062BF8D170BD5A +:40084000040600000506000003060000E000000810B50248B03000F0ABFC10BDDC19000810B50248583000F0A3FC10BDDC19000810B5FFF7F5FF10BD10B5034A8021603271 +:40088000042000F019FB10BDDC1A000870B501F05CFB0500094800F0DFFB094C200000F00DFC2000343000F009FC2000683000F005FC280001F04DFB70BDC046DC19000897 +:4008C000404500108A22044952000B6853430022CB181A717047C046CC1B00088A230A495B000A6809485A438A18926810B5920082180868D26A4343CB18002119718A42FF +:4009000000D0904710BDC046CC1B0008CC1D00088A21084A490013684B43D3181B79002BF9D101211533FF334343D318197110607047C046CC1B00088A20074A074940005C +:40094000D36C4343CB181B79002BF9D1D06CD36C59424B41D3647047CC1D0008CC1B0008F0B585B0039300238A2714001E00029001917F000A9A96424FD2FFF7DDFF03004B +:400980007B432D490090CA18D46000220431944206D00198855CD018081805740132F6E7019A350012190192721CFF32944622499B1B0A98AA1B0C00A8420BD9654507D045 +:4009C000039A1E48545DEA18821814750135F0E780225200009B00987B43E418029B2261A360FFF795FF164B134ADB6C7B43D3181E79009BF6B27B43D2180832114B002E8F +:400A000000D1114B0221032000F086FB0028EAD17342734104002E00ACE7002CADD1002B07D0029B064A9B00D318DB6A002B00D0984705B0F0BDC046CC1B0008D01B000839 +:400A4000CC1D0008DD080010C508001010B5022000F004FC10BD000070B5040015000200022000F087FB0849022000F097FB074AA400136D14190133E5621365012B01D1B3 +:400A8000FFF7E4FF70BDC046C5080010CC1D000810B5022000F0C8FB10BD0000F0B5962191B0002001F002FA01F0D8F9002801D101F0C6F9012001F077F8E8217E4C7F4BC1 +:400AC000626C89011A400A436264626C0193120AD2B23A2A04D1636C794A13400B4363643422002103A803F00DFD03AA0021754800F002FF3422002103A803F003FD03AA9F +:400B00000121704800F0F8FE0822042623686E4D134323602369334207D1002D04D0012001F07EF9013DF5E701E0002D00D1FEE7A02603220127654CF600A35903AD934305 +:400B40003B43A351D2196249280003F0D2FC280001F06AFB5F4901980B685F4A03400B608021136949041B021B0A0B4313611369019902200B401361E0230F219B00E2588E +:400B80008A433A43E250E25821318A438021E250E25809060A43E250002100F075FB0021032000F071FB0021042000F06DFB0321002000F069FB0321380000F065FB444B34 +:400BC0000522191D280003F094FC2900380000F091FB002800D0FEE74049380000F0DCFB002800D0FEE73E4B3E4AE1580A403A43E250E1583C4A0A408021E250E258090666 +:400C00000A43E250A259394B1340A351A259384B13408022920113438022A351A35912021343A351244B1A68324B1340224A136001F092F9C0235B00E3583B4204D12E4AC4 +:400C4000A3585B005B08A3506421002001F02EF9C0230021294A1B01D15080210901535801981B4C0340802080010343535080232349DB00D150D35823002A000C3343CBE4 +:400C800043C243CB43C243CB43C229000D4800F0ADFE23002A00303313CB13C213CB13C213CB13C22900174800F0A0FE164A174B1A6011B0F0BDC04600002740FF00FFFFFD +:400CC000FFC5FFDF0000324020A1070000002640EC45001090002140000021401027000004050000FEFCFFFFFFFF00FFFFF0FFFFFF8FFFFFFFFCFFFF0C0500000000014026 +:400D000000FF00800003324001001180000E1F4110B5054801F07EF90122044B1A70002801D101F083F910BD38010008201E0008030010B5FF24800882009B1ADB009C402D +:400D40009940E243214007282DD8174B01F050FE04090E13181D2227186A02401143196221E0586A0240114359621CE0986A02401143996217E0D86A02401143D96212E061 +:400D8000186B0240114319630DE0586B02401143596308E0986B02401143996303E0D86B02401143D96310BD00002140064B10309A68064B9A4203D183009858995002E027 +:400DC000034B8000C058704700ED00E00000000800000010F7B5051E01913DD00023C05E002802DBA978FFF7A3FF6A680023E85E9201002812DB1A4B81088900C918FF23A7 +:400E000003271C00C0250740FF00BC401A40BA40AD004E59A64332434A5113E003250F2381B20B402940A940FC352F002A408F408A40083B9B080B4C9B001B19DE69BE43D0 +:400E40003243DA61074B00259A68074B9A4204D10199FFF7ABFF00E0044D2800FEBDC04600E100E000ED00E000000008010056000369002B03DA89B24160002000E001486C +:400E80007047C04601008A000368002B01DB034803E089B2C26081600020704701008A000369002B03DAC36800200B6000E001487047C04601008A0070B5040010000F2C9B +:400EC0002BD8002A07D1002927D1154B6401E418144B1C6022E000291FD01F260E401CD1104D0F4B6401E4186960AA60CA0831002C6003F007FB31002000FFF7B9FF3100F7 +:400F00002A1D2868FFF7C0FF011E04D12868FFF7AFFF011E02D0044900E00449080070BD00002340241E000801018A0003018A00194BF7B51A680193D76804003B680E007C +:400F4000834223D90025A94202D100F0FEFF0500019B18680368002B01DB104C10E063095A01A41A012279689B00CB181968A2400C0014400CD10A431A600021FFF778FF05 +:400F8000002E07D1280000F0E4FF03E0044C01E0044CF2E72000FEBD241E00080301880004018A0002018800194BF7B51A680193D76804003B680E00834223D90025A9423D +:400FC00002D100F0C2FF0500019B18680368002B01DB104C10E063095A01A41A0122A24079689B00CB18196811420DD00024914319600021FFF73CFF002E07D1280000F013 +:40100000A8FF03E0044C01E0044CF2E72000FEBD241E00080301880004018A00020188000A4B1B68DA68136883420DD9430999005B01C31A0120984052688B581840431E54 +:401040009841034BC01800E002487047241E00080001880004018A00024B1A68002A00D118607047301E0008F0B52C246043104C1E0024681F0A2018FF2426403C400D4F7F +:4010800006607601F61906610B4E1B0C44606401A4191E04836033434461A3600023059DC261016283619D4201D02B888381F0BD301E00080000234000102340F0B50389D4 +:4010C00085B002AD2B800368066A1933AB704368476A0095826AC16A040003930369C068FFF7C2FF00213B000A0000913000FFF7BBFF216B2800FFF76DFE0023EA5E002AB1 +:4011000005DB1F231A401E3B9340024A136005B0F0BDC04600E100E0F7B52C25124C6843276801933C182669002E08D04D4379198869002805D13568002D02DA03E00B4820 +:4011400011E00B480FE06768012425004B689D4013882D041D431560F2608C61BC40019BA4B24B62B460FEBD301E000804028A0007028A002C235843064B1B681818C369B6 +:40118000934204D9036A9200D150002000E002487047C046301E00080A028A00034B1A682C235843101881627047C046301E000873B5002642690400D56801962B0CB34295 +:4011C0001CD01B040069136013680369B34215DA01A9FFF765FEB0420CD10198E26903681E0C0378934205D2226A9B009B58002B00D0984731002069FFF73AFEADB2002D63 +:401200000ED063691D6000251B68636AAB4202D09847656203E0A36A002B00D09847A56163691B6873BD00000A4B1A682C23584310180C23C25E002A09DB1F231A401E3B23 +:401240009340054AD367BFF34F8FBFF36F8F00207047C046301E000804E100E0084B1A682C23584310180C23C25E002A05DB1F231A401E3B9340034A136000207047C04635 +:40128000301E000800E100E0042819D804290FD94B1EFF3B132B13D81F231940094B8000C018C02304229B00C1504033C25005E00723D0301940034B8000C150002000E051 +:4012C000014870470000264001004A00084B8200D218D0239B00D05807231840042806D1C0239B00D0581F231840E1331843704700002640F0B5012819D1C022224BD2009E +:401300009A58002A0CDB8A78901E0E280FD84C78601E11280BD8C8780D7800282FD101E01A4830E07026152D01D9AE4201D2184829E00E79022E14D0F82124024901F8271E +:401340000C4021007F2412047F033A4011432C4021438024C022C006240520400143D2009950C020C0248005360706403200E4001D590849002029400A431A5103E0382628 +:40138000122DD4D9D1E7F0BD0000264003004A0001004A00FFFFFFCFF8B50D00012819D1C02180240D4BC9005A582406C826224307001C005A50F600A3593B4206D1002D30 +:4013C0000AD0012000F02CFD013DF5E70020002D03D101E0024800E00248F8BD0000264001004A0002004A00494BF7B51C789C46002C05D0474B484CE358002B00DB82E017 +:40140000464B984200D980E09A427ED8444B99427BD80123644663703F4B424CFF280BD8A3260F25F6009F592840AF43384398511859A843083D1FE03B4E0F25B04204D882 +:401440001E592840AE43304317E01E59AE433500060A35431D51354DA84206D8FF261D59000130400F3EB54306E0F02500022D011E5928402E4D354028431851FF2A10D825 +:40148000A326FF27F6009D5912013A400F3FBD432A439A511A5927481040E022D20210430AE0F027204D3F03AA4207D81D592148120417402840384318511EE01859164EDD +:4014C000009010020740019700981A4F154D3840019F074315481F517459824205D8F020120500040240144804E0F020120600050240124820400243725162465160054AE5 +:401500000020995002E00E4800E00E48FEBDC046341E00081C050000000026400F060000FFFFFF0014050000FF040000FF050000FFF0FFFFFFFFF0FFFFFF0FFFFFFFFFF08D +:4015400003004A0001004A00A423F0B500251F4ADB008446D0582B000002020A85B00292039363461A484570AB421BD1029A039B1A43AA4226D0029C039D029E039F0A00D8 +:4015800063464068614601F0D3FBEB0762081A4300900191009801996B088018594132003B000BE0029A039B44680800290001F0BFFB2B00620880185941220001F098FB3B +:4015C000029003910298039905B0F0BD00002640341E0008174B70B5C318DA179B185340042B22DD8023144E144D1B027459A405A40D984209D9124B0521C01801F002FAF8 +:40160000201AC343DB17184009E00E4B0521181A01F0F8F90C4B0019984200D90B4873599B0A9B020343735101E000242000201A70BDC0460080FFFF000026403C0500005F +:401640000280FFFF02800000FE030000FF0300001E4A0300904238D010D840282ED005D8002831D010282DD119482EE0802827D08021100049008B4227D023E0154A904296 +:4016800014D008D8A022120690421DD0124AA020934211D016E0114A904209D0104A904208D0104A90420DD10F480EE0A42003E00E480AE00E4808E0C00306E00D4804E0A5 +:4016C0000D4802E00D4800E0002070470600520001005000010000F0090000A0040000F0050000F0030000F00100520002005200030052000200500005005200FF00520092 +:40170000F0230F4A1B06C318934201D8580A15E0EC230C4A1B06C318934203D8580A80235B0207E0EA231B06C018904204D88023400A9B02184301E0012040427047C04608 +:40174000FFFF0F00FF7F000010B50400FFF7D8FF0022431C02D0E40562426241100010BD0B4B10B51B69002B10DB0A4B0A4C1868FFF76EFF0121094B094A995099580029D9 +:40178000FCD1064909590029F8D100E0054810BD00002340401E00088C040000000025400C0400000200500010B5022202490020FFF7E0FC10BDC0469503000810B5FFF74B +:4017C000CFFF10BD70B50400FFF7BEFF002824D0FEF714FDE022124B52051A605C600024FA219C60DC600F4B0F4A1D691B692D0E013555431B0ADBB201335D430B4B8900C2 +:40180000186801F0FFF80100280001F0FBF8084BC118200002F08CFE00E0064870BDC046401E00080000214060F59000C4000008980800000600520070B505000C00FFF76E +:4018400083FF002828D0002C26D0FEF7D7FCC022124BD2041A608322FA2152005A609D60DC600F4B0F4A1C691B69240E013454431B0ADBB201335C430B4B8900186801F0B9 +:40188000C1F80100200001F0BDF8E1239B00C118002002F04DFE00E0044870BD401E000800002140808D5B00C4000008060052000F4B30B5C0180F4BC009C01800011F23D2 +:4018C000032909D81D00C9008D4013408B400468AC432343036009E01D000439C9008D4013408B404468AC432343436030BDC0460000CEBF00100304F7B504000E001500E1 +:4019000000286ED0002A6CD0012312688B40002A01D1436000E08360B30001930F231900B0008140A26A8A4369680B4083401343A3622A7A31002000FFF7BAFF03207100C2 +:4019400088400322636A83431800EB6813408B400343636201231F00B7400097FF43BC462F6962461F40B740A0691031104038436F69A0611F40B740E06A10403843E0620D +:40198000A86903221840B0400600E869276B10408A408840009930430A4397436A6A384356000222206304201640AA6A616B92000240286A324303401A43EB6AD800182322 +:4019C0000340FF2013432A6B019D520102401343FE2292002A40934081430B436363002000E00148FEBDC04601005A0000281BD0002919D00D4B0E4AC318DB099B180A682C +:401A00001B010260CA6882620A69C2624A6902638A6842624A6882618A694263CA6900201A600A6A5A6000E0024870470000CEBF0010030401005A0010B50F24022006495C +:401A4000064BCA58A2430243CA50F02212028B58A34303438B5010BD0000214004F0000010B50F2403200649064BCA58A2430243CA50F02212028B58A34303438B5010BD7F +:401A80000000214004F000000449054A054B88580340C020C00103438B5070470000214004F00000FF8FFFFF0449054A054B885803408020C00103438B50704700002140BF +:401AC00004F00000FF8FFFFFF8B50500072700F03CFA1C4C060063693B409D422DD0022D0FD18021184A490493690B439361FFF7A3FF03226369BB4313436361FFF7C4FFD8 +:401B000009E003226369C820BB431343636100F087F9FFF7C9FF072362699A432B4013436361052D09D1C82000F07AF9FFF798FF054A064B91690B409361300000F009FA66 +:401B4000F8BDC0460000264000F02540FFFFFFFE031E03D1084B5869C00F0CE00020012B09D1054918008A69920F1A4201D18869C00F01231840704700002640072370B53A +:401B8000084CA2691A4090420BD0A5699D4303402B43A361002904D0904202D9C82000F03FF970BD00002640F7B5060000F0CDF9B022E8211F27244D244C01902B595205F9 +:401BC000C900525C3B409B1A5A1E9341B34236D0002E13D180211E4A490493690B439361FFF72AFF0B222B59BB4313432B51FFF74BFFB023E8225B05D2000CE00B222B59C5 +:401C00000920BB4313432B5100F00AF9FFF74CFFB022104B5205D35C2959DAB21F23994313400B432B51012E09D1092000F0F8F8FFF716FF064A084B91690B4093610198E9 +:401C400000F087F9F7BDC046000026401CFF000000F0254041070000FFFFFFFE70B5050000F073F92C1E20D0124B19681F2901D900241AE0EC68002C17D02C68002C14D038 +:401C80005E6800243200002A04D0AA42F0D014005269F8E7002E01D15D6000E0656100222C61012401316A61196000F052F9200070BDC046501E0008F0B5060085B00D0012 +:401CC000204F042901D001291AD100207C68002C35D01D4B984232D02379B3420ED1A368002B01D02B4209D1E36801A85A689B6842608360057023689847BC606469E6E758 +:401D0000BC68022902D1002C00D024690020002C15D00D4B984212D02379B3420DD1A368002B01D02B4208D1E36801A85A689B68426083600570236898472469E7E705B0CA +:401D4000F0BDC046501E0008FF00420070B5194C06002368002B0AD100F0F7F823680500002B10D004210020FFF7A6FF0BE001210020FFF7A1FF0028EED002210020FFF79C +:401D80009BFF0D4C14E004210C4A13698B431361012E01D030BF00E020BF280000F0D9F823680024A34203D008212000FFF784FF200070BD501E0008FF00420000ED00E072 +:401DC00010B5E82400F0C1F8064B07495A68A4010A4022435A605A68114059605B6800F0B8F810BD00002640FF00FC0F70B5802504002D02AC4206D9064B186800F09CF86D +:401E0000054BE418F6E7054B1868604300F094F870BDC046DC0000080080FFFFD800000810B5034B1B78584300F086F810BDC046D40000080122014B9A6070470000254032 +:401E400080220020034B12069A649B6C834200DA0148704700002740030046008022054B120198585B68DBB2002B02D08023DB021843704700002640FEE7000002680A4B08 +:401E800010B51A6042685A6082689A60C268DA6002691A6142695A6182699A61C269DA61FFF7EAFF10BDC04678050008F0B51922002800D14B32E82403258A429241194ED8 +:401EC000640033595242AB43134333513359164F3B403351154B5C68AC4322435A605A6817405F60002808D00023102913D921338B429B415B4201330DE003001D290AD96D +:401F000001233A2907D9DB18572904D976338B4240410422131A0F21054A1068884303431360F0BD00002140FFFCFFFFFC00214000002540000000000230800803D001309E +:401F40000238FCD1C046C0467047EFF3108072B6704780F310887047094B042803D11A68104318600BE0C022000692041040902204499200885004211A688A431A6070471C +:401F800010E000E000002140F8B50778012F06D0082F34D11C4B1868FFF7DBFF31E00320FFF73EF8194B984229D000F0CFF8012825D0022003F0D8F90600FFF7C6FF124D59 +:401FC000286003F0D5F9040006281AD0022E0AD1033CB4433000E4B204F026FE002C0BD100280ED008E0380004F01EFE022C03D0002801D1FFF7AAFE2868FFF7AAFF04480B +:4020000000E00020F8BDC0467C1E000801018800FF004200002803D0024B5860002000E0014870477C1E00080100160000B58BB000212822684602F065FA6A46154B1648F7 +:402040009381FB2313835383F83B1377013353770C33D3770132D3776A460232D3776A465B3353846B4601220733DA77FFF7F6FD03F05AF903F060F903F05AF906A803F0FD +:40208000A7F9002804D1054B6846019303F074F90BB000BD901300004C01000898050008014B024AD050704778F0010000003C4010B50BF0EFFA10BDF8B58023FA250C0037 +:4020C00001271B0218430D4E0004F061AD00326C0A4B01203A4205D1002D0CD0013DFFF79FFEF4E7002D06D01A6C10431864DB6A0020238000E00248F8BDC04600003C4007 +:402100000400160070B5FA2401260D4B000418400C4D0143E961A4002B6C0A4A0120334205D1002C0AD0013CFFF77AFEF4E7002C04D0136C18431064002000E0024870BD34 +:402140000000FF7F00003C400400160010B500242000FFF7BBF8032804D00134052CF7D1002000E0012010BDA023034ADB00D058012318407047C0460000264030B524259E +:402180009DB02A00002101A802F0BCF9154B164C0493164B2A0000210AA808930993069402F0B0F9124B2A000D93124B00211193114B13A812930F9402F0A4F90F4B01A9D9 +:4021C00016930F4B0F481A931894FFF70FFC0AA90D48FFF70BFC13A90C48FFF707FC1DB030BDC046666666660000FFFF1C1C1C1C66E6EE661C1A1A1A1A1A000066E6666601 +:402200001A1A001C00013240800132400002324010200349034A8B5803438B507047C04600003C4070F00100F0B585B00090002800D147E1BE4F7B689B0301D5FFF7C0FD6B +:402240000122BC4BBC4C1D001959114204D0BB495B58134200D037E1FFF790FFB84AB94BEA508022009BD2021B781343B64AAB50B64AB74BEA50B74B5A6801231A4200D078 +:4022800024E1B54A116F08220A4008D1B34BB44918681300884202D900F0B4FB431E2A68002B03D0AF485B03034300E0AE4B13432B607B699F499E4E01275B000DD53900DF +:4022C0000320FFF75BFC73699B0F3B420AD08022B369D2051343B36104E00320A34A8B5803438B502B5940200193019AA04BA14E13432B51FFF794FD0123AA598D4F1A42F5 +:4023000008D1BB514020FFF78BFD03234020BB51FFF786FDFA27019A974B984E1A4016430192FF002E51964A964BD3581022134207D1002F00D1CBE00120013FFFF770FDCD +:40234000F1E7002F00D1C3E008218F4A0120AB580B43AB50FFF7FCFB002802D18B4E019B1E438B4B1E4001231E432E511E00894C724BEB58334207D1002C00D1A8E0012097 +:40238000013CFFF74DFDF3E7002C00D1A0E00B27C02181484901FFF7B5FE041E05D102AB991D7D48FFF788FE0400013F002F00D196E0002C25D1C02202AB9E1D33885201AA +:4023C0009342E5D131007548FFF776FE041E18D180233288DB001A4200D083E00B27019380216E48C900FFF78DFE041E04D131006A48FFF761FE0400013F002F70D0002CB3 +:4024000068D0B0256D056B78002B44D06B78212B41D0634FEB5B002B3DD0002C00D0FEE002AB9E1D31005F48FFF746FE041E00D0F5E0C021E85B3488084060398C43400898 +:40244000594920430140F020EA5BC000EB5BD201024011439B05554A9B0F1140DB02194350483180FFF74EFE041E00D0D7E031004F48FFF721FE041E00D0D0E0C022EB5B04 +:4024800031889B069B0F9B019143194348483180FFF738FE0400002C00D0C0E0009B454859781D78444B49001943FFF72BFE041E04D142494248FFF725FE04006801FFF7D6 +:4024C000AFFCACE03F4CAAE03F4CA8E03F4CA6E03F4CA4E03388019A934200D080E701E03B4C8EE731003B48FFF7E6FD041E00D087E732883F2310009843009B36499F78F9 +:40250000DB78012F0ED10222012B04D89FB2D21B92B2019201E0170001947022104330802E4A66E0002B5BD0019401275BE0C0460000264000003C40A0F00100B4F00100AC +:4025400006000001A4F00100A8F0010001000100ACF00100FC003C4000F03D40C800000800093D00041A0080040A0080C4F0010030000300B0F00100EFFFFEFF20000200CA +:40258000000032401040000068F0010028000200FFFFFBFFF07E0E00021E0000031E000016180000071E00007FF8FFFFFFE7FFFF061E0000081E000001100000376800007B +:4025C0000F1E000001001600030016000200160004001600091E0000C00000080048E80101201F0001907F2082436F38024332800C4ADA400A6031880B4839433180FFF750 +:4026000081FD009B0400DB78DF1B03231F40019B9B001F43054BBFB23780EF50F1E6200005B0F0BD0024F400091E000064F00100014B18687047C046C0000008024B58690F +:402640004000C00F7047C046000026400120024B1B68DB0D984370470000264010B50A00002808D0FA23FF33994204D8034901F040FF002000E0024810BDC04607080016C4 +:4026800001001600F0B57D4C7D4BA54407900C000492994200D8ECE08B187A4A93420ED9794A914200D8E4E0784A934207D9784A914200D8DDE0774A934200D9D9E0FFF718 +:4026C000BDFF0523019300280BD0734B5D6907231D40EBB20193022D03D10520FFF7F4F90195FFF7B3FF01230393002810D06B4B694AD158E823B022DB005205D25C1F2307 +:402700000B40934204D10120FFF74EFA00230393F0231B06E3185D0A06936D0200210320FEF706FC0028F9D1070008AB5B1B0293049BBB4273D980239B00EB180593002615 +:402740002B00069A9A4214D8049ABA4211D9079A0299D25DCA54002E08D18021490559180978521A511E8A41160000E00126013705E0802252059A1812780299CA54059A64 +:4027800001339A42DDD10024A6423FD08023C8265B05ED182800FFF715F804000120FFF73FFBA423A422DB032340D203934203D1013E002EEED128E0394B9C4204D1FEF71E +:4027C000FDFF384B0400F8E70120002C1ED1C82608A92800FFF730F804000120FFF720FBA423A422DB032340D203934203D1013E002EEDD109E02A4B01209C4206D1FEF780 +:40280000DDFF284B04009842F9D00120264A029B944663440293002C02D1059D88E70024002801D0FFF706FB00210320FEF7BCFB0028F9D1FFF702FF002805D0019B022B9B +:4028400002D11800FFF740F9FFF700FF002805D0039B002B02D11800FFF7A6F9134B9C4207D0134B9C4204D00020844202D0114800E0114889239B009D44F0BDDCFDFFFFEA +:40288000FFFFFF0F00001010FFFFFF1300800014FF070016000A0016000026401CFF0000010050000200500000FEFFFF0200520006005200130016000100160010B50A0031 +:4028C000002807D0FA23FF33994203D80249FFF7D9FE00E0014810BD0708001601001600002070470020704710B5FFF799FA10BD10B5FDF7FCFD074B1B681B6800229A5E9D +:40290000002A05DB1F231A401E3B9340024A136010BDC046801E000800E100E010B5FDF7EAFD094B1B681B6800229A5E002A09DB1F231A401E3B9340044AD367BFF34F8FCA +:40294000BFF36F8F10BDC046801E000804E100E0A023034ADB00D058032318407047C04600002640024B034AD058C00F7047C0461C0500000000264010B5FEF7E5FD10BD77 +:4029800010B5FEF731FD10BD10B5FEF723FE10BD10B5FFF7F3FB0220FFF782FB094C0A4923681868FEF716FA23681B6800229A5E002A05DB1F231A401E3B9340034A13600A +:4029C00010BDC046801E0008B120001000E100E00420704710B5FFF7B8FA10BD10B5FFF7B8FA10BD10B50021FFF7C8F810BD000002B4714649084900095C49008E4402BCBF +:402A00007047C046002243088B4274D303098B425FD3030A8B4244D3030B8B4228D3030C8B420DD3FF22090212BA030C8B4202D31212090265D0030B8B4219D300E0090A03 +:402A4000C30B8B4201D3CB03C01A5241830B8B4201D38B03C01A5241430B8B4201D34B03C01A5241030B8B4201D30B03C01A5241C30A8B4201D3CB02C01A5241830A8B42AC +:402A800001D38B02C01A5241430A8B4201D34B02C01A5241030A8B4201D30B02C01A5241CDD2C3098B4201D3CB01C01A524183098B4201D38B01C01A524143098B4201D320 +:402AC0004B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524183088B4201D38B00C01A524143088B4201D34B00C01A5241411A00D20146524110462E +:402B00007047FFE701B5002000F0F0F802BDC0460029F7D076E7704703460B437FD4002243088B4274D303098B425FD3030A8B4244D3030B8B4228D3030C8B420DD3FF2267 +:402B4000090212BA030C8B4202D31212090265D0030B8B4219D300E0090AC30B8B4201D3CB03C01A5241830B8B4201D38B03C01A5241430B8B4201D34B03C01A5241030B23 +:402B80008B4201D30B03C01A5241C30A8B4201D3CB02C01A5241830A8B4201D38B02C01A5241430A8B4201D34B02C01A5241030A8B4201D30B02C01A5241CDD2C3098B4221 +:402BC00001D3CB01C01A524183098B4201D38B01C01A524143098B4201D34B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524183088B4201D38B007B +:402C0000C01A524143088B4201D34B00C01A5241411A00D201465241104670475DE0CA0F00D04942031000D34042534000229C4603098B422DD3030A8B4212D3FC228901BF +:402C400012BA030A8B420CD3890192118B4208D3890192118B4204D389013AD0921100E08909C3098B4201D3CB01C01A524183098B4201D38B01C01A524143098B4201D3C7 +:402C80004B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524183088B4201D38B00C01A5241D9D243088B4201D34B00C01A5241411A00D20146634601 +:402CC00052415B10104601D34042002B00D54942704763465B1000D3404201B5002000F005F802BD0029F8D016E770477047C046002B11D1002A0FD1002900D1002802D090 +:402D00000021C943081C07B4024802A14018029003BDC046D9FFFFFF03B4684601B5029800F050F8019B9E4602B00CBC7047C046F0B54F464646C0B41604360C99463300C8 +:402D400005042C0C070C150C63437E436F4365431C0CAD1964199C46A64203D980235B02984647446346250CEF191D044B464A4343432D0C240464199918C91920000CBCA3 +:402D800090469946F0BDC04670B500220C4B04000D0001F05DFA002804D12000290001F0B5F970BD064B00222000290000F05AFE01F0ACF980231B069C466044F1E7C046E0 +:402DC0000000E041F0B54D46564644465F46F0B4924683B004000D0099468B422FD82CD04946504601F05CFA29000600200001F057FA331A9846203B9B4600D574E053461A +:402E00005A4693401F005346424693401E00AF4229D826D05B46A41BBD41002B00DA79E0002200230092019301235A4693400193012342469340009319E08242D0D900221A +:402E40000023009201930C9B002B01D01C605D600098019903B03CBC90469946A246AB46F0BDA342D6D900220023009201934346002BE8D0FB0772081A4346467B080EE0D4 +:402E8000AB4201D1A2420CD8A41A9D41012024196D410021013E24184D41002E06D0AB42EED9013E24196D41002EF8D15B460098019900196941002B22DB2B005A46D34044 +:402EC0002A004446E2401C005B461500002B2CDB26009E40330026004746BE403200801A994100900191AEE7424620239B1A5246DA40414613004A468A4017001F4382E7AB +:402F0000424620239B1A2A0046469A402300F3401343D5E74246202300219B1A0022009101920122DA40019282E74246202326009B1ADE402F00B446974066463B003343D8 +:402F4000C9E7C046F0B556464D4644465F46F0B41D000E034C00CB0F87B0070092468146360B640D98466AD06D4B9C4235D08022430F12041343F6001E43C3009946694B51 +:402F800000279C460023644402932B0368001B0BED0F51469B46400D009500D178E0604B98426CD05B46DA004B0F802109040B4313439B465346D9005A4B9C4600236044E4 +:402FC0004246201A6A40924601901F430F2F00D9B0E05548BF00C0598746374300D088E0002399460233082700260293CDE74346B34649460093029B009A9246022B00D07A +:40300000BFE1002153460122002689461A40444B002136030C0D2405360B2643434C1B0526401E437600D207760816434846310007B03CBC90469946A246AB46F0BD330077 +:4030400003434FD0002E00D1BCE1300001F00AF903000B3B1C2B00DDADE11D220100D31A08393A008F408E40DA40B9461643304B00279C46002360444442029385E753460E +:403080005A4613432CD1002300219B46023397E70B4320D05B46002B00D19EE1584601F0E1F803000B3B1C2B00DD8FE102005946083A91408B461D21CB1A5146D9400B0043 +:4030C00059460B4351469B469140194B9C4660444042002374E7002300219B4601336FE703236DE70023994601330427002602934BE703230C27029347E70122D51A382DA6 +:4031000000DCB0E153461A4000210023002689467EE700238026994600223603004B77E7FF07000001FCFFFF40510010FFFF0F80F30300005E4500D972E100D16DE1019B36 +:403140004D46013B01930023340002935B461E020B0E1E430B020393330C994633041B0C494620000093FFF74DFC009B370043430600494620009846FFF7CAFC2C0C090439 +:403180000C43A04509D9E419731EA74200D95CE1A04500D859E1023EE4194346E41A49462000FFF72FFC0300009A80465343494620009B46FFF7ACFC2A040904120C0A4314 +:4031C00093450DD94346D219013B974200D93AE1934500D837E102235B429C46D219E0445B46D21A4346360433439B460399180C0B0C1D00059309045B46090C0C001B04F8 +:403200001B0C4443049159436B4368431B190D0CEB189C4203D980246402A44660441C0C09041B04090C20185D18824200D2DEE000D1D7E0161A029B9C465D1BAC459B41CE +:403240005B42F61AB74200D106E149463000FFF7D9FB009B04004343494630009846FFF757FC2E0C09040E43B04509D9F619631EB74200D9F3E0B04500D8F0E0023CF619CE +:403280004346F31A494618000293FFF7BBFB009B06004343494602989846FFF739FC2D0409042D0C0D43A84509D9ED19731EAF4200D9D6E0A84500D8D3E0023EED192404A4 +:4032C000210043463143049E059A3000ED1A0B040C0C1B0C58436643534354439A19030C9B189E4203D980225202944664441A0C00041B04000C14191B18A54250D34DD0F4 +:4033000001231943964A019B94466344002B00DCF3E64A0709D00F220A40042A05D00A1D8A42894149428B4411005A46D20108D55A468C4B1A4093468022D2009446019B7C +:403340006344894A934200DD5BE65A46C908500708435602514601225B058146360B5B0D0A4055E680231B031E4211D05A461A420ED15E461E433603360B2A0089467B4B4B +:4033800046E6032B00D1E1E0012BBBD11A40BBE61E433603360B4246744B39E6002BB1D07D194A1EAF4252D91100A542A8D1039A9A42A5D1A6E703003E00283B9E400023D5 +:4033C000994654E600F04EFF203041E603005246283B9A400021934677E6504600F042FF20305EE6029B0026AB4200D323E7039E0299B44661448846B045B6415B467642FB +:40340000F619B218013B0291974213D290424FD800D18EE0161A9B460DE7894500D28EE674084B46F60735005B081D434B46DB0702938BE69742EDD10399029CA142E5D9E8 +:403440003E1A9B46F7E69846CAE61E00A5E6AC423ED874D0110053E70121494252E71C000EE71E002BE71F2D3CDC20230A0058465B1B9840EA4099400243481E81415E4694 +:403480001143EE404B0709D00F230B40042B05D00B00191D99429B415B42F61833023CD55346012200211A40002601238946AFE502235B429C46039CE344A446029B634479 +:4034C0009846A045B6417642F6190293B218B1E603988A1E41008142B6417642F619AD19039161E71F225242D31A5A46DA401300202D29D040225846551BA8400143481ED7 +:40350000814107200B4318400026002809D00F2200261A401900042ABBD10B0070077602360BDB0803439946012253461A4000236EE502998D42BBD89B4600267BE6039882 +:403540009842C5D3110032E70020D7E780265B4636031E433603360B009A8946034B57E5FF030000FFFFFFFEFE070000FF070000F0B55F4656464D464446F0B40D039946E5 +:403580004E002B0B87B00700924680469B46760DCC0F002E69D06D4B9E4235D05B468022DD001204430F13432B439B46C3009846674B00279C460023664401934A461503D6 +:4035C0005000D20F53462D0B400D914600D176E05E4A90426CD080225B0F120413435C4AED0094461D4353460022DB00604449463618701C6140029017430F2F00D9AFE0AD +:403600005448BF00C759BF465B461F4300D088E000239B469846023308270193CEE74946022A6AD0032A00D109E2012A00D0BBE111400022002300259046CCB200212D036B +:403640000A0D12052D0B1543434A1B0515401D436D00E4076D0825434046290007B03CBC90469946A246AB46F0BD034352D05B46002B00D18AE1584600F0F4FD03000B3B24 +:403680001C2B00DD7BE11D22D31A3A0001005D46DA4008398D4013008F402B439B46B8462E4B00279C46002360444642019385E752462A432CD100250023022297E75246D4 +:4036C0002A4321D0002D00D154E1280000F0CAFD03000B3B1C2B00DD46E11D21CB1A51460200D9405346083A954093400D431B4A944660444042002279E7012400220C40A4 +:40370000124B0025904699E70025002301226EE703226CE700239B4698460133042701934CE703230C27019348E700238025984600242D03054B81E75D464346019A6FE786 +:403740005D4643462100019A6AE7C046FF07000001FCFFFF80510010FFFF0F80F30300004246120C91461A0C9446424617044A461B041B0C5A43604690464A464243100071 +:40378000039262461C003F0C7A437C4342440192220C9246019A5244904506D98246802040028046C24450460390100C049048462404240C1204121905922A0C2D042D0C38 +:4037C00068432C00824648467C4350438146200C8046574357444744BA4503D9802040028046C144380C3F04B84648442404240C01900498A044404404905846000C814646 +:4038000058460404200C8246070048465F434C464343604660436446834650464443380C8446E4186444A34203D980235B029C46E34448463F04230C3F0C2404E41957463D +:4038400068436F4384464D46504655434243380C814662444A445B44944503D9802040028446654403983F04834604983F0C8446E344C345804140428246100484460198EA +:40388000674484466744A344BC46A345A4419946D44464428742BF41D4458041E144A04699459B417F424042C8440743120CBA18A045A4415F423B0064422343D71843467A +:4038C0007D19DB0D6D021D435B465A02059B1A43531E9A415B46DB0D1A4343465B021343EA0107D501225C0813402343EA07029E13436D08574AB218002A4BDD580709D0BB +:403900000F201840042805D0181D98429B415B42ED180300E80104D54F4A15408022D200B2184E48824200DDE7E60124DB08680718436D02530580462D0B5B0D0C407DE6CF +:40394000802259461203114208D0154206D115432D0398462D0B4C46414B6FE65D4615432D032D0B3E4B69E603005546283B9D400023BCE6504600F075FC2030A8E60300D1 +:40398000283B9F400023BB46984689E600F06AFC203073E60124A61A382E07DD00220C4000230025904649E6029EA3E71F2E20DC20222C001800921BF040944093400443A7 +:4039C000581E83411C43F540630709D00F232340042B05D023001C1D9C4292415242AD182B021FD5012400220C4001230025904624E61F202C004042821AD440202E1CD003 +:403A00004022961BB5402B43581E83410720234318400025002809D00F2200251A401C00042AD8D1230068076D022D0B0124DB08034398460C40002300E60025E3E78022DD +:403A40000124120315432D0398462D0B0C40044BF4E5C046FF030000FFFFFFFEFE070000FF070000F0B557464E464546E0B40E001100F20F9246C500420F18033703740020 +:403A8000400A4E0F7F0A3043CF4E17435A00640D520DDB0FC900B24200D1E5E001267340A61AB446534500D1AFE0002E00DC0DE1002A3AD103000B4300D0E4E06B0709D09C +:403AC0000F232B40042B05D02B1DAB42AD416D427F191D003B0200D488E0BB4B01349C4200D110E13A00B94B51461A4001235007ED08520264050543120B640D0B400021AC +:403B0000280012030D0D120B64052D0515436208AF4CDB072C401443640064081C4321001CBC90469946A246F0BDA74B9C42C5D080231B0418436346382B00DDFDE01F2B10 +:403B400000DD30E1624620239B1A02009A40664690460A009940F24046464B1E99413243114363460200DA40691A8D429B410D00BA1A5B42D71A3B0235D57A02530A98464C +:403B80004346002B00D1C4E0404600F06BFB0300083B1F2B00DDC5E020222900D21A4746D1409F400A009D403A439C4200DDC0E01C1B631C1F2B00DDE4E02021140028003D +:403BC000C91AD8408C408D400443DA40681E854117002543002471E7424663461A4300D14CE2674645466B0700D069E7012351467807ED08FA080B40054373498C4238D0DC +:403C000012036405120B640D79E7002E00DC9AE0002A47D06C4A944200D14FE78022120410436246382A00DC08E10143481E81410022C9B24919D219A942BF410D007F42D7 +:403C4000BF183A0200D442E15F4A0134944200D14EE101205D4A69083A4028400843D507054357089A4629E706000E4300D017E714E72900114300D1F9E1802109030A436B +:403C80001203120B3BE701235B429846C4446346002B72D1691A8D429B413F1A5B42FF1A0D0068E702000A4300D107E7012252429046C4446246002A00D0E6E06918A942E2 +:403CC000B6413F187642F7190D00BAE7002E00D080E0621C5205520D012A00DCF9E06A1A91464D45B6413A1A7642921B9046120200D499E04D1BA9428941C71B49427A1A9C +:403D000090469A463CE752460123002513400022F5E6280000F0A6FA20300300083B1F2B00DC39E72A002838824000259C4200DC3EE7264FE41A1740C0E60143481E8141B9 +:403D40000022C9B210E7002E00D0F1E0621C94465205520D012A00DCA0E01B4A944500D1C5E06918A94292413F185242D2194908D5070D4357086446A0E6134B9C4200D06A +:403D8000D9E69BE611001F3CE1400C00202B00D180E04021CB1A9A4015436A1E95410027254300241FE763460200203BDA406346202B71D0402366469B1B98400143481E83 +:403DC000814111430022CFE6FF070000FFFF7FFFFFFF0F80002C48D0CA4CA24200D1A2E07442A1468024240427434C46382C00DDDBE01F2C00DD44E14E462024A41B3E00B3 +:403E0000A640A246B0464C462E00E640B4464646644626435446A5406C1EA54134002C434D46EF400D1B28E04A4643464D461A4300D0A5E6002300240025DEE61F2A5ADCA8 +:403E400066462022921B060096409146B04662460E00D640424616434A4691404A1E9141020060463143C240E4E63C002C435AD0F443A146002C52D14D1BA9428941C71B8D +:403E800049427F1A14009A4675E69E4A944200D0C7E613E600227FE700208FE7002C00D0C8E03B002B4300D10FE103000B4300D104E66918A9429B413F185B42DF193B02B2 +:403EC00000D41AE1904B0D001F406446F6E59A4689E63A002A43002C5CD1002A75D102000A4300D1CAE007000D009A46E6E564460022002581E662460600203AD6406246C1 +:403F0000B046202A00D1B7E040226646921B904001434246481E8141114300228AE6794CA24200D061E707000D0014009A46C5E5002C41D13C002C4378D0F443A146002C86 +:403F400020D0704CA24271D04C46382C00DDB2E01F2C00DDBCE02026341BA2463C005646B4404E46A0462C00F440A446444666463443A4465446A54064466E1EB541254390 +:403F80004C46E7406D188D4289413F184942CF19140056E6002A2FD102000A4300D184E007000D009A46574C88E53D436F1EBD41ECB200270D1B60E7524CA24236D07442E1 +:403FC00080263604A1463743BEE702000A4300D174E56A1A90464545B6413A1A7642921B9446120200D4F7E54D1BA9428941C71B49427F1A9A4661E502000A433AD0ED0899 +:404000007C072C438025FA082D032A4208D0C7082F4205D145072C003A009A46C9080C43670FD200E5001743364C47E507000D00140043E53A002A4343D002000A4319D034 +:40404000ED087C072C438025FA082D032A4207D0C6082E4204D147073C003200C9080C43D700620FE50017439A46264C26E50022002544E5234C21E5002049E700230025EF +:40408000BBE54C463E00203CE6404C46B446202C31D040244E46A61BB7403D436C1EA54164462C4300270D1BE7E6802200231203144C0025A1E53D436F1EBD410027EDB2AA +:4040C00060E707000D000F4CF8E407000D00F5E44E463C00203EF440A0464C46202C0ED040244E46A41BA7403D436F1EBD4144460027254346E70027CFE70D0073E50027E5 +:40410000F2E7C046FF070000FFFF7FFF0B0330B5134D1A0B4B005B0DC90F0024AB4211DD104CA34210DC8024640322430E4CE41A1F2C0CDD0D48C31ADA4013005C420029CD +:4041400000D11C00200030BD094BCC18FAE7E040084CA44663449A4013000343EEE7C046FE0300001D0400003304000013040000FFFFFF7FEDFBFFFF70B5051E28D000F017 +:4041800071F8154B154A1B1AD21A1F2A16DD2C00134A0025D21A94405A052403240B520D002124030B0D240B1B0523430D4C1205234013435B002800590870BD0B212C0051 +:4041C000081AC440954024035A05240B520DE7E700220024E4E7C0461E0400003304000013040000FFFF0F808446101C62468C46191C634600E0C0461FB500F001F90028B4 +:4042000001D40021C8421FBD10B500F055F84042013010BD10B500F0F3F8002801DB002010BD012010BDC04610B500F0E9F8002801DD002010BD012010BDC04610B500F069 +:404240007BF8002801DC002010BD012010BDC04610B500F071F8002801DA002010BD012010BDC0461C2101231B04984201D3000C10391B0A984201D3000A08391B09984244 +:4042800001D30009043902A2105C40187047C0460403020201010101000000000000000010B5002903D1FFF7DDFF203002E0081CFFF7D8FF10BDC046F0B55F4656464D46AD +:4042C0004446F0B41F035C00DB0F9A46194B0E034D00C90F8046360B6D0D8B4691463F0B640D9D4219D0134B9C421BD00123A54206D018003CBC90469946A246AB46F0BDAF +:40430000BE42F6D1C845F4D1D34510D0002DF0D1304303005A1E9341EBE7310001230143E7D1E0E73A430123002AE2D1DEE70023DFE7C046FF070000F0B55F4644465646AA +:404340004D46F0B41F033C0B2C4F0E034D00A3465C008446360B6D0DC90F9046640DDB0FBD422BD0254FBC422ED0002D0ED130430700814678427841002C17D15F463A4391 +:4043800014D14B460020002B0AD006E0002C02D15846024301D099421AD00123484218433CBC90469946A246AB46F0BD0028F2D058425841012240421043F1E7370007435A +:4043C000D0D002204042EBE75F461743CDD0F8E7A542E2DC05DB5E45DFD808D000205E45DED248424841012340421843D8E7C445D3D80020C445F4D3D2E7C046FF070000C6 +:40440000F0B55F464D4644465646F0B41C03240BA4462F4C0F034D005E00C90F80463F0B6D0D8B469146760DDB0FA54220D0284CA64222D0002D12D1384344424441002E05 +:4044400020D0002C0DD05C42634101245B421C4320003CBC90469946A246AB46F0BD002E17D05B4519D05B465C4201231C43EFE7390002240143EBD1D9E761460224114317 +:40448000E6D1D7E761460A43DBD100240028DFD0E9E761460A43E4D1E5E7B54203DD01225C421443D4E7B542CDDB6745DBD809D000246745CCD259464C4261410124494239 +:4044C0000C43C5E7C845CED80024C845F3D3BFE7FF07000030B50024A24208D0035D651C0C5DA34201D0181B02E02C00F4E7002030BD002310B59A4203D0CC5CC454013372 +:40450000F9E710BD03008218934202D019700133FAE77047F8B5C046F8BC08BC9E467047F8B5C046F8BC08BC9E4670470000000001B40248844601BC604700BF990200081A +:4045400003000000010000000100000000000000050360000400000001000000000000000100000006046000080000004C1B00086108001008000000010000000200000063 +:4045800002000000080800030900000001000000000000000300000009090003080000006C1B0008710800100A0000000100000004000000040000000A0A000C0B00000066 +:4045C0000100000000000000050000000B0B000C100000008C1B0008510800100A0029000300000003001800030000001920010219010200000000000C00000000000000B3 +:4046000000000000006800000000000000000000000000000000121200000000000000000000000000000000000000BA0000000000000000000000000000000000001D1DFA +:40464000000000000D0000000800000000020000000000000000000000000000000000000000000000000000000000000B0000000000000064000000000000002002000092 +:404680007C01000031010000090901120C00FF0380ABCDABCD80409C1B04041BFFFFFFFF000000000410080007070400F216FBE0FBE01F60427EF56D720096BE209000000F +:4046C00010502604060037D7F401FA00960064004B0032001E00140003040506020D1100F1D9001055D90010A7DF0010A5DA001057DB001053DF00106BDF00102DE000101A +:40470000D1DB001039DC001015DE001043DE00107BE0001041DF00100FE000100FE000100FE00010E9DE001091DE0010D5DE001075150110811501104D2501103526011082 +:4047400041260110A1DA0010EFD90010EBDF001055DB00108FDB001063DF001085DF001079E0001035DC001091DC00102FDE001069DE0010E7E000104BDF001079E000100F +:4047800079E0001079E0001039DF001079E0001079E0001079E0001079E0001079E0001079E0001079E00010DFF50010E7F50010E3F50010DDF50010BBF50010B7F500100A +:4047C000D5F50010D3F50010AFF50010B3F50010EBF50010D7F50010D1F50010EFF50010EFF50010ADF50010DBF50010CD0C011081100110450E0110F10B011001FF001072 +:40480000B5FB001085060110C901011021F7001085F70010D9110110110A01106101011035FB001011060110F15B0010C10A011079120110051601105117011025180110C4 +:4048400041140110D51201108D150110B5130110DF130110EF130110F1130110F51301100FE00010E1130110EB130110E91301107D29011035230110E928011099280110D6 +:40488000352901104D26011059250110F1250110B526011025BE0010572301104D2301105323011051230110552301104F2301100FE000100FE000100FE00010F9AC00109A +:4048C000453C0110273C0110273C0110273C01105D3C01103D7B0110273C01102D7B0110457B0110357B0110DF400110D74001104140011039400110373C01101F3C011034 +:40490000153C01103B3C011031400110614001102F3C011059400110B9400110273C0110694001105140011049400110273C0110653C01106D3C0110753C01102B3C0110A5 +:404940002B3C0110453C0110273C0110273C0110273C01105D3C01103D7B0110273C01102D7B0110457B0110357B0110DF400110D74001104140011039400110373C0110A7 +:404980001F3C0110153C01103B3C011031400110614001102F3C011059400110B9400110273C0110694001105140011049400110273C0110653C01106D3C0110753C011031 +:4049C0002B3C01102B3C0110696401105D640110756401102B3C01102B3C0110096101104561011015610110396101102D61011021610110516101105D610110516401104F +:404A0000B5660110B9660110C56601109D660110A96601102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C011082 +:404A40002B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C01102B3C011069610110A7570110BC +:404A8000555601105556011055560110D957011069570110555601104D5701101958011063570110F3570110E9570110D75501105556011055560110555601105B55011014 +:404AC0003757011081550110B9570110DF560110EF56011069560110555601102F580110A556011097560110555601102357011067580110555601105556011055560110FA +:404B0000F9630110ED63011005640110ED5601108756011055600110916001106160011085600110796001106D6001109D600110A9600110E1630110F1650110FD6501103C +:404B400009660110D9650110E5650110555601105556011055560110555601105556011055560110555601105556011055560110555601105556011055560110555601107F +:404B8000555601105556011055560110555601105556011055560110555601105556011055560110555601105556011055560110B5600110D75A0110055A0110055A0110DD +:404BC000055A01101B5B0110815A0110055A0110C95A0110C95A0110735A0110315B01101F5B0110815901107D590110615A01101559011007590110075901101959011072 +:404C0000FB5A0110355A0110495A0110095A0110055A0110655B0110215A01100D5A0110055A0110655A0110815B01107D5B0110055A0110055A01102563011019630110E5 +:404C400031630110A95B0110035901109D5F0110A55F0110B15F0110BD5F0110A55F0110A55F0110C95F0110D55F01100D630110FD6401100965011015650110E56401109E +:404C8000F1640110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110FE +:404CC000055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110055A0110E15F011008000000060F0020200107021900000007070E0562 +:404D0000020220001C1202000103000E030600040040270700000707010200020307030400000000000000000000000000000000000000000000000000080000A757011057 +:404D4000555601105556011055560110D957011069570110555601104D5701101958011063570110F3570110E9570110D75501105556011055560110555601105B55011051 +:404D80003757011081550110B9570110DF560110EF56011069560110555601102F580110A55601109756011055560110235701106758011055560110555601105556011037 +:404DC000D75A0110055A0110055A0110055A01101B5B0110815A0110055A0110C95A0110C95A0110735A0110315B01101F5B0110815901107D590110615A011015590110B3 +:404E0000075901100759011019590110FB5A0110355A0110495A0110095A0110055A0110655B0110215A01100D5A0110055A0110655A0110815B01107D5B0110055A011014 +:404E4000055A011008000000060F0020200107021900000007070E05020220001C1202000103000E032000800000C00000000004000000A822000000000000040000F7FF90 +:404E8000FF7F0000003000000000000000000000000000000000000000000000000000000000000000000000355E0110ED5F0110555F0110955E0110FB5F01107D5F011022 +:404EC000655E011009600110615F0110935E01100D600110795F01107D5E0110FB5F0110715F0110675E0110FB5F0110695F0110AB5E011019600110855F0110B15E01101F +:404F0000296001108D5F011055560110055A01102B3C011055560110055A01102B3C011055560110055A01102B3C011055560110055A01102B3C011055560110055A01101E +:404F40002B3C011055560110055A01102B3C011055560110055A01102B3C011055560110055A01102B3C0110BF5E011041600110955F011055560110055A01102B3C011044 +:404F800055560110055A01102B3C011055560110055A01102B3C011055560110055A01102B3C011055560110055A01102B3C01107961011055630110FD6201107761011054 +:404FC00049630110F56201109F610110A163011005630110756101103D630110ED62011055560110055A01102B3C011055560110055A01102B3C011055560110055A011081 +:405000002B3C011055560110055A01102B3C011055560110055A01102B3C0110A16401105D65011000000000AF64011071650110BD270110BD6401109B650110ED2701105F +:405040008164011021650110412401108F6401103F6501105D24011030303031423830303031303230333034303530363037303830393041304230433044304530463130A4 +:40508000313131323133313431353136313731383139314131423143314431453146323032313232323332343235323632373238323932413242324332443245324633307A +:4050C000333133323333333433353336333733383339334133423343334433454142000026002B00300036003C0043004B0055005F006A00770086009600A800BD00D400CC +:40510000EE000B012B014F017801A601DA01130254029D02EE024A03B1032404A5043605D9058F065C0742084409650AAA0B160DAF0E79107C12BD1445171C1A4B1DDE20A6 +:40514000343100100230001008310010F82F0010083100101231001008310010F82F0010023000100230001012310010F82F0010EE2F0010EE2F0010EE2F001064330010A0 +:405180006037001020360010203600101E36001038370010383700102A3700101E360010383700102A370010383700101E3600104037001040370010403700104039001054 +:4051C00000000000F8B5074600256846058078683C1D2D492E46002807D06268002A06D0800702D1207A800701D00D4649E0FDF7CFFBFDF793FBFDF7EBFB00F029F9002855 +:405200003DD1788C0006C00F00F0A2F905460004000C34D11D49084600F0A4FE0004000C2DD12289A17A2068194C002806D02060A280E68021810021FFF764F9684601F0DA +:405240001BFC054613486B460078E2888000001DC1B21B88A088D418A04206D3C01A801A80B201F09BF9044600E00B4C00F044FD002C04D100F07CFB08490120087000F03D +:40528000F5F82846F8BD00000100160025540010901E0008CC1E0008FFFF00006401000810B503480078012801D101F013F810BD6401000810B5FDF74BFB032801D100F086 +:4052C000FFFD00F0FDF901F059FC00F07DFE02490020087010BD00006401000800487047901E000870B5044600208A0703D08A07920F891A091D084B89B2DA889E885518D8 +:40530000B54206D81D68AA182260DA885118D98070BD024870BD0000901E000803001600004870479C1E000810B501F033FB10BD10B501F039FB10BD10B501F03DFB10BD54 +:405340000549002806D0054981800521017000214170817008467047010016008203000010B5FFF79DFF10BD10B501F02DFB10BD10B501F03BFB10BD38B505460020694608 +:405380000880002D09D0284601F03CFC0446684601F066FB002C02D015E00C4838BD01F01DFB2846FFF70EFF04000CD1284601F0B1FB040007D1FDF7CBFA032803D100F058 +:4053C00055FD00F093FD204638BD00000100160038B50446002069460880002C08D06189090A05D1617A102902D8E179102901D90A4838BDA0816946204601F0CFFB054626 +:405400006946A08909884018A081002D04D1102221460348FFF76DF8284638BD010016009C1E00087047000010B5084900200978002909D005F052FE044605F015FD201ACD +:4054400080B281004018C00810BD00006C01000810B5FCF793FE442202490348FFF749F8002010BD84460010AC1E000810B5FDF73FFA10BD10B519461046044C01F0C4F9CB +:40548000002800D00024204610BD0000FFFF000010B501F0E5F910BD10B501F0CBF910BD010010B5044806D0044A01201070002007F064FD002010BDFFFF00006C01000848 +:4054C00070B50024034D20462C7007F085FD2C70204670BD6C01000801480078704700006C01000870B5591C89B24C080B4D64000021451906E028685054000A5618891C6C +:40550000707089B2A142F6D3D80705D0D0182038D15CC47FD454C17770BD000000103C4030B50A4C002100195B1E07E054186478555C240225430560891C89B29942F5DBDB +:40554000994201D1515C016030BD000000103C40F8B50746FF2000F0F3F9164EFF2070701548164900684018406B0024410F301D0125022901D0457000E0447005700D4882 +:40558000801C4470384612F03DFB070010D112F07BFB3070012000F0D3F912F07FFB68460470447012F0E4FE6846457012F0E0FE3846F8BD6D0100086801000840F03D40C6 +:4055C000F0B50021094D5B1E08E0441924685718260A7E705454001D891C89B29942F4DB994202D1401900685054F0BD00103C4070B500210A4E5B1E09E0541864782502AE +:40560000545C2C4385192C60001D891C89B29942F3DB994202D1515C8019016070BD000000103C40F0B50599091FCFB200217E1E0AE054186478555C24022543144C0419D6 +:405640002560001D891C89B2B142F2DBFC0710D01C78515C24020E4A0C4381180C609C785D782102001D294384182160001DD9780BE059781A7809021143054A84182160B9 +:40568000D978001D9B780902194380180160F0BD00103C4038B509480024447012F0FEFA69460C704C70684612F062FE012069464870684612F05CFE002038BD6F010008AA +:4056C00010B501F08BF90A480078012805D1FCF73DFD012809D012F02FFF05490020891E0870062000F02CF910BD12F00FFFF4E76F01000810B50B46062816D006DC01281B +:405700000FD0032801D1FFF7C5FF10BD0B2811D0112813D01228F8D11146184612F018FA10BD0020FFF714FF10BD1146184612F09DFD10BD04480078107010BD1146184663 +:4057400012F016FA10BD000071010008F8B5184D184E28688019846AE00719D001F07AF90127012811D1002001F046FA052000F0E7F81149FF204870881C4078002804D10B +:4057800028688019416B39434163286880198762E0050CD50848801C0078052802D1042000F0CEF8FF202968013089198862F8BD6801000840F03D406D01000805490028B2 +:4057C00005D005494A784270097801700021084670470000010016007101000838B504000C4816D06178012913D801F0F7F8607812F074FD207000280AD1694608706846BD +:4058000000F090F869460878012801D104202070002038BD0100160010B5094900280CD00278082A09D24278042A06D205494A700078087012F032FA0021084610BD000022 +:40584000010016007101000810B504460448032C05D801F0C3F8204612F04CFD002010BDFFFF160010B50400054808D06178012905D801F0B3F8204612F07AFD002010BD9C +:405880000100160010B5FCF761FC0122084992040028084B086804D0C018016A1143016210BDC018016A9143016212F04FF910BD6801000880F03D400949087805280ED15F +:4058C0004A780848084900684018002A03D1416B490849004163C16A01221143C16270476F0100086801000840F03D4001480078704700006F01000802484078022800D09F +:40590000012070476D010008012807D0032807D0042803D0052803D0FF207047012070470220704710B5040002D012F065F9207010BD000001494870704700006F01000808 +:4059400010B50446FCF7EAFF062C01D9FF2C01D102480470FCF7CCFF10BD00006F01000801494870704700006D010008002070471CB5002469460C70022001902346054AE1 +:40598000054800F0F5F904480068401C00D1034C20461CBDE559001074010008FFFF00003EB50F4A01460D4800230124126800290BD0012908D1684600930481438169469A +:4059C000104600F0D0F980B23EBD68460093048143816946104600F0C1F9F4E7FFFF00007401000810B50089002100280BD0012802D0052807D103E000200DF061FD02E02A +:405A0000084600F0F5F8002010BD000010B50248006800F041FC10BD74010008FFB581B01F00154606463CD000F0D8FFFCF776FF2F49304B4878401CC0B2044606E02201A6 +:405A4000D218127A202A2AD0641CE4B2202CF6D3002406E02201D218127A202A1FD0641CE4B28442F6D32024202C1AD03470029821490202120A200602432001C618726042 +:405A80001F501B4869180078009120280CD0FFF7CBFC0746BD4223D3281AF0601BE04C70E2E7164805B0F0BD13484042854207D9FFF7F6FC014611488142F3D0009807E084 +:405AC000A8B2FFF7EDFC01460C488142EAD00020F060074804703472FCF70AFF0020E1E7FFF7EEFC781B012100F01EF9DCE7000078010008F01E0008C063FFFFFFFF000083 +:405B000070B5074CA5780E2D07D2FFF787FF002802D1A178491CA17070BD024870BD000078010008FFFF0000F8B520280BD2234D07017C19207A202805D000F04FFFE06877 +:405B4000002802D031E00120F8BDFCF7E7FEFFF76BFC012100F0E8F80020184EE060FFF7AFFCFCF7C5FE00F0ADF80546202819D0FCF7D4FE280186191148F168814205D90F +:405B80000646FFF78DFC0021304604E088B2FFF787FC0021F06800F0C7F8FCF7A9FE0948057002E00749202008702020034920720020C8516060E060F8BD0000F01E000858 +:405BC000409C00007801000810B5074CA178002908D0FFF7A9FF002802D1A078401EA070002010BD014810BD78010008FFFF0000F0B500258BB02E46089500F0EFFE00235F +:405C00006A4618462C49040161180C7A202C02D0C96800291DD000211154401CC0B22028F0D300240993099800280FD06846005D00283BD020482101081806684168089119 +:405C400000210160202241600272C160002D04D028E0012111540B46DFE700F033F80546202819D0144829010818C7681348874207D90021074600F057F8FCF74FFE3846A8 +:405C800006E00021384600F04FF8FCF747FEB8B2FFF706FCFCF72CFE094805700998002808D00125002E01D00898B047641CE4B2202CB8D30BB0F0BDF01E0008409C000007 +:405CC0007801000830B50023DB432020094C00210A011219157A202D06D0D268002A03D09A4201D808461346491CC9B22029EFD330BD0000F01E000830B50020084C05463A +:405D00002023020111190B72A550401C4D60C0B2CD602028F5D303480370457030BD0000F01E00087801000830B50B4D00231A015219147A202C0AD0D468002901D02418C6 +:405D400004E0844201D9241A00E00024D4605B1CDBB2202BEBD330BDF01E000810B50EC900F0B2FA10BD10B50EC900F0E9FA10BD38B50024E443054600290AD0052000909D +:405D80004B68097804A000F043FA2860401C00D00024204638BD00007461736B000000000EB5002005216A46009011815081034869460068FFF7D7FF0EBD000074010008D6 +:405DC00010B51D481D4C0178491E0170FF206070FCF7C8FD002825D0FCF72AFC01460020FCF7CAFDFCF7D0FD411C14DB80B2012811D862881248824208D0124B0021601C97 +:405E0000FFF77EFE002802D10220207010BD0D2010F086FE10BDFF20F530FCF765FD00F065F810BD0548084B02220021401CFFF767FE0028EBD110BD7A0100087C010008F0 +:405E4000FFFF0000855E0010C15D001010B503480078042801D100F049F810BD7C01000801480078704700007C010008044800210170FF214170FF21F53141807047000090 +:405E80007C01000806490878401E087005480178012901D003210170FF214170704700007A0100087C01000801494880704700007C01000801490870704700007C01000886 +:405EC00010B5054C6078FF2803D000F007F8FF2060700020207010BD7C01000810B502484078FFF771FE10BD7C01000810B5FF22043280210820FCF743FD0B4C6078FF28EE +:405F000001D0FFF7EBFF0848084B04220021401CFFF7F6FD002803D00D2010F001FE10BD0120207010BD00007C010008C15D0010C0080A21484380B20849C82801D2084848 +:405F400009E002461923C83A5B019A4201D2400801E0FF20F5304880704700007C010008FFFF000010B50F4A002313600E4A13600E4B18600E4801600E49012008600E49FA +:405F80000860282090600E490C4808600D49143008603C38506000F0C5F800F0F5F9002010BD00009801000880010008AC010008B00100089C0100088C010008182100087D +:405FC00090010008A401000800207047014610B50020002910D0094B1A689C685118A14209D25868196080188A0704D08A07920F891A091D196010BD002010BD8001000861 +:40600000F8B50024164E671E321F3D463168136806E01422624310328A58521C1BD0641C9C42F6D36A1C14D02C461422544322460C3288500C214843FFF7C8FF31680028FC +:4060400008510AD031680020103408517068401C70602846F8BD2546E4E73846F8BD000090010008F3B50026F64381B000281FDB2149096888421BD80299002918D01E4F63 +:40608000142204463F1D54432546396810354859401C0DD0FAF72FFAFCF740FC38682F1F4159C359994205DBFAF721FAFCF720FC3046FEBD214608310091465801590C20F9 +:4060C000704308180C220299FEF713FA0A48761C001D0068C159B14200D100260649009A091D865008684159491C4151FAF7FFF9FCF7FEFB0020FEBD8C010008002803DB64 +:4061000007490968884202D90020C043704704491422091D0968504310300858704700008C010008F0B500200D4A451E0346171F50600FE014260146714314680E1DA35119 +:406140000C461668083433511668083435511468401C635039688842ECD30020F0BD000090010008F3B50026F64381B0002845DB26490968884241D8029900293ED0234FAD +:40618000142204463F1D54432546396810354859401C33D0FAF7AFF9FCF7C0FB3868415900292DD0211D009146580C21005971430F46C1190C220298FEF79BF913480021D1 +:4061C000001D0068761C00590C34C0190160416081600E48001D00680159B14200D100260A49009A091D865008684159491E4151FAF77DF9FCF77CFB0020FEBD3046FEBD4B +:40620000FAF775F9FCF774FBF8E700008C010008FEB504460D4600201E49089E0860471E009001900290002C11D0486885420ED2002A0CD0002E0AD0642E08D808460C30BE +:4062400001681C2068430C18207A002801D03846FEBD0120226020721846FFF7D1FE6060401C13D06681A6810A4827610C3067610179A94200D205710021684601810A464D +:406280002846029B00F05CF82846FEBD00202072DDE700009801000810B5002810DB0949496888420CD807491C220C310968504308184068FFF722FF002801D0002010BD32 +:4062C000012010BD9801000838B50124009400F03DF838BDFEB50027184EFF433D4600240EE01C20316860430818017A002906D04068FFF703FF002801D0254603E0641CBF +:406300003079A042EDDA681C16D01C2130684D434419FAF7F0F8FCF701FB69466068FFF721FF0546FAF7E3F8FCF7E2FA002DD5D1216868468847D1E7FEBD0000A4010008AB +:4063400038B50024009400F001F838BD1FB500220C49541E0A60002811DB496888420ED808491C220C31096850430818406801A9FFF778FE401C02D0002004B010BD20461B +:40638000FBE7000098010008F0B50021114A4D1E174611710C3F0B46BD6016E008461C2460431668041D355114680646235014680836A3551468361DA353044616680A3432 +:4063C000335318301468491C255078688142E5D30020F0BDA401000838B500210091002811DB0F49097888420DDA0D4D04010C3529680859002807D0201D0818694600F0DA +:4064000073F9002801D0002038BDFCF787FA28680F34015D491E0155FCF76AFA009838BDB4010008F7B582B0002502986E1E06602F48D21C024017462E4A2C4610460C38C8 +:406440000178106805E02301C358002B0FD0641CE4B28C42F7D3711C29D03401211D40180191039900F02EF9002820D101E02646F1E72048016820460C300F521D480399A6 +:40648000026820460E3011541A480399026820460F30115403993846484300F0A1F8154900280968085102D00024009011E001251AE01048016801980818009900F02FF9B7 +:4064C000002801D0012502E00098C0190090641CE4B203988442ECD3002D05D10298054906600879401C0871284605B0F0BD0000FCFF0000C0010008F8B50D4600216A4658 +:406500008C461180002839DB23490978884235DA214B04010C3319680A59002A2ED020460C300B5A801C0E5C184670438018954224D3854222D2002006E007465F43BF182F +:40654000AF4206D0401CC0B2B042F6D36046002814D0114E271DC8190C366A46294600F008F900280AD168460088012808D030682946C01900F0D3F8002803D00120F8BD9D +:406580000020F8BDFCF7CAF930680F34015D491C0155FCF7ADF9F3E7B4010008F8B50F46002400F031F8002817D10C4900220B460C334A600EE021011D680E466A501D6804 +:4065C0000C36AA53B61C1D680F31AA551D68641C6A54E4B2BC42EED31A71F8BDB401000800280BD0C01C074A81085068890053884118994203D8936851601818704700201A +:4066000070470000B4010008F8B5064600200F4D009029700C0121466846FEF763FE00280CD129460C3100980860301B001F84B221466846FEF756FE002801D00448F8BD27 +:406640006C800098A8600020F8BD0000B4010008FFFF0000F8B5002827DB19490978884223DA174C05010C342168485900281CD028460C30085A009028460E300E5C401C88 +:406680000E5420682F1DC01900F064F800280CD12068002445590EE0094829460C300068C01900F03CF8002801D00120F8BD00982D18641CE4B2B442EED30020F8BD000093 +:4066C000B401000830B50D4604000BD0A800FFF787FF6060002805D000202570C0436080002030BD012030BD70B50D46040005D0002D03D00220205E002801DA012070BDF0 +:40670000FCF70CF90221615E60688900405828606088401E6080FCF7EBF8002070BD70B50D46040007D0002D05D002212078615E401E814201DB012070BDFCF7EFF86088E9 +:40674000401C00B26080616880000D50FCF7D0F8002070BD10B5040009D0227800216068FDF7D0FE0020C0436080002010BD012010BDF0B500231D46002802D00224045F0A +:406780000AE00120F0BD46689F00F6598E4201D1012503E05B1CDBB29C42F4DA15700020F0BD000001B503480122436811466846984708BD4821000810B50021052010F0E4 +:4067C0005DFA10BD70B50546FCF7A8F80D4C218A002914D0638A8B4209D100206082208201202070A3682A46E068984707E0E0680121C018F9F772FE608A401C6082FCF732 +:4068000077F870BD4821000810B50023084A00280BD0002909D001241470141D0BC413825382F9F74FFE012010BD1370F5E700004821000807B509480378012B01D0002059 +:406840000EBD02230370C16002820021418201216846F9F743FE01200EBD00004821000804480021C160018241820121017008467047000048210008FEB5114C114F089EDB +:40688000099D00280BD0002909D0002A07D0002E05D0002D03D0002B01D01B2B01D93C460CE00096019508F03FFC042802D0052803D003E0034C133400E000242046FEBDA4 +:4068C000FFFF160001001600FEB50E4C0E4F089E099D00280BD0002909D0002A07D0002D05D0002E03D0002B01D01B2B01D93C4606E00096019508F060FC042800D1002489 +:406900002046FEBDFFFF160001001600F0B589B015460F460646144C00F060F8002E20D0002F1ED0002D1CD0102239466846FDF7E0FD1022314604A8FDF7DBFD1021684605 +:4069400010F0DAFB102104A810F0D6FB2B46102204A9684608F000FC1021284610F0CCFB0024204609B0F0BD0100160010B50FF04FFD0AF0A7FC0EF089FC10BD10B50FF074 +:4069800049FE0BF0DBFC10BD10B508F007FE0FF097FB10BD10B50DF089F80FF049FD0AF02BFD0EF07DFC10BD10B50DF07FF80FF043FE0BF0D1FC10BD10B50DF077F808F0AC +:4069C00019FE0FF08DFB10BD10B5022801D100F089FAFEF78BFFFEF797FF10BD10B500F07DFBFEF783FFFEF78FFF10BD10B5FEF77DFF012801D1FEF77FFF10BD10B501886E +:406A00008A0703D08A07920F891A091D0379827B1031534359438BB241888C0703D08C07A40F091B091D447910316143C918438989B2DC0703D092015118103189B29A07B6 +:406A400005D5C0794422504340180C3081B2084610BD000001488078704700009C2100080100034803D00348008808800020704701001600C801000810B504000C4815D030 +:406A8000FEF74EFC817B44238A01C179594351181C312180827B9B005A43891880312180407AC000083008182080002010BD00000100160000B501464A7809781202114337 +:406AC000124A11488BB091421BD111490978002917D1FEF725FC0146102206A8FDF709FDFEF7FCFB01680191808869468881FFF775FF6846FEF766FB002802D1684600F016 +:406B000009F80BB000BD000002001600030C00006401000870B5184D00280BD0FEF700FC0446807A800701D4FFF72EFFA07AC00703D004E01048801E70BDFFF717FFA07A26 +:406B4000000701D4FFF71AFF204610F0EFFB002810D110F071FB00280CD100F0D1FD002808D110F05DF8002804D10DF05DFB002800D10025284670BD0300160010B5064C11 +:406B800010F066FC002804D110F094FC002800D10024204610BD0000FFFF160070B5044640890D46002681070BD0C00709D020881B38E12804D26088FB2801D81B2800D2FB +:406BC0000B4E2046FFF71AFF2880617A5322C900083140182880A17BD20051430922D20189184018034928800880304670BD000001001600C8010008014988707047000054 +:406C00009C2100080021002807D04268002A04D0034A80891288904200D2024908467047C80100080100160070B50546FEF75EFE074CFF280AD0FEF7E9FE012806D10020EA +:406C4000012D04D103494978002900D1204670BD020016005C21000870B5054613480E460078A84201D8002404E01148016AD02068430C18002C13D0228B50060AD5D2072B +:406C8000D20FA078022106F05DFA208B40218843208305E0D207D20FA078012106F052FA3146284604F050FC70BD0000CC1E00085C210008F8B50546002004460B4E0090C2 +:406CC0000FE022466946284601F008FD0098002801D010F001FBA878214603F0A0FF641CE4B2B08AA042ECD8F8BD0000F0210008FFB50446C034A068002103468C468E46B6 +:406D00002033997887B0002915D05E78F200511D06920591415C0091911D0291415CD51D0495475D151D0395455D82580192109A002A07D03CE00A99FF2008700899002070 +:406D400008605EE0002908D0DA78002A05D1002D03D0491E029AC9B281540098854227D3002925D1019810F0B7FAA268059900235354A26802995354A26804995354A268EF +:406D800003995354A26806995350A06820304178491C8907890F4170A16820318878401E0006000E887027D02148864601208446A0686346014620318A78002B0AD04E7804 +:406DC000F1004B1DC35C0093CB1DC75C0B1DC55C40580190002A28D0009885421FD20199401B4A190899C0B20A60B8420CD2099A2918C9B210700BE00A99FF200870089947 +:406E00000B600B480BB0F0BDE819C1B2099807700A980670F000A268001D115405E00A98FF2101700899002008607046EAE70000FFFF0000064A02235188891C89B2518047 +:406E4000814201D8102900D95380508870470000CC0100080148407870470000CC010008F8B517460D460446FBF758FDC034A16820318878042827D0E8780202A87810436A +:406E80000A78521C9207920F0A70A16820318A78521C8A70A1682022525CD6008D51A168721D8854A2680021331DD154F21DA168B8428F540CD33946FBF72AFEC0B20029A1 +:406EC00007D0401CC0B204E0FBF712FD0448F8BD0120A168B61D8855FBF70AFD0020F8BDFFFF0000FEB575480478FEF7FFFC012831D1FBF72DFD724D032831D1A87B012806 +:406F000029D800F033FF012803D100F003FF012808D0A87B002818D06849002020390A782B6A10E0A87B0028E2D10EE0824201D8002102E0D021414359188031C97801294C +:406F400009D0401CC0B28242F0D8FEF789FF032802D3FEF7CBFFAFE0FEF782FF0128FAD05848007800285FD004F052F900285BD00CF0C8F9002857D0FEF748FD002853D018 +:406F800004F08CF800284FD111F084F801284BD06878C00703D000F0F1FE012844D0287E002841D16878484F002803D1FEF794FA002860D06878000706D504F06FF8064623 +:406FC00000F0E4F8304377D16A7801A9684608F03DF90646B4426FD83C48864206D3FEF77BFA002868D06878002865D104F010F9002861D03648006A80B2029068784007C3 +:4070000003D56846008805F02BFA03F007FE6846008803F041FE03F027FF2E490988814203D10120FEF78CFC46E0FBF7D3FC054603F01AFF69468988401A301AA0420ADB09 +:407040000CF060F9012806D1FEF7E0FC012802D1387003F09BFE2846FBF7C0FC3878012803D01B4902980862DBE70120FEF762FC00F0E4FD1BE004F0CBF800281CD0102489 +:4070800003F0F2FE214603F017FD03F005FEFEF7BDFC002810D00120387003F077FE0020FEF748FC00F0CAFD38780128B9D1FEF7E9FB00203870FEBD0748FEBDEC1E0008B7 +:4070C0005C2100086D010008CC010008FF7F000040123C40E6010008FFFF000010B517480078002825D01648046AFEF7FFFB032821D004281FD005281AD103F061FE00F082 +:40710000B1FD03F0EFFE8007800F022810D10D48418800290CD08321095D002908D101210170207E0221C207D20FA07806F00AF810BD0024D9E700F095FD10BDCC1E000871 +:407140005C210008DC010008F8B50646002406F0DBF90546304606F00FFA03460A480021868A0DE001228A401046174628401F40002803D0002F01D1224394B2491CC9B257 +:407180008E42EFD82046F8BDF0210008F8B500252C460A4F0A4E0CE0D020396A604308180079002803D02046FFF7CEFF0543641CE4B23078A042EFD82846F8BD5C210008D9 +:4071C000CC1E000808B50020694648706846FEF705FB69460020085608BD70B50D4601F0BBFF04000BD02079002808D0FFF7F6FBE178A0782A4605F0E9FA002070BD02201A +:4072000070BD00000148007F70470000CC1E00088030C078002800D00120704700B500F001F800BD10B5094BD0225043196A85300A5C074C521CD2B20A54648A196AA24269 +:4072400001D300220A54196A085C10BD5C210008F021000870B50D4601F07EFF04000BD002F0F3FD002807D021462A460A310620FEF740FA002070BD022070BD70B50D4647 +:4072800001F06AFF040007D002F0DFFD002803D0207B2870002070BD022070BDF8B50F4606460146384606F025F9044614480078B04201D8002504E01248016AD020704380 +:4072C0000D18002D12D0284601F084FF032C0ED0002C0BD000220121304602F091F9284603F0C8FA0221284603F0DEFAF8BD3146384606F0C7F90146304606F05FFDEEE76B +:40730000CC1E00085C210008F7B52B4F0446F8682A4D0078297F884201D30720FEBD07F0CDFE002801D00C20FEBD2078611C05F06DFCFF2822D1F868297F007888421DD287 +:4073400005F0B6FC0646FF2816D02178621C03F083FB1B4821780068426B601C904705462078611C02F0B2FEFF2802D0314602F033FE002D04D01CE007251AE01F2518E02D +:407380000298002815D1F86841680078C200101A401C08180622611CFDF7ABF8F868217842680078C300181A1154F8680178491C01702846FEBD0000CC010008CC1E0008EC +:4073C000EC01000810B507F079FE002801D00C2010BD05F0EBFB05480068006B804702F011FE002000F0A2F9002010BDEC01000870B50D46044610210FF07EFE102160180C +:4074000006460FF079FE334610221946204607F0A3FE102130460FF06FFE0220287020460CF028FE70BD0000F8B504464078217802028006870FE0781143A67809050002BE +:40744000090D0643084601F087FE00210546F2B2002816D0002C10D0022F0ED0032F0CD0002A0AD00279092A07D0002A05D0134A8223527D1B5C9A4207D8288900210CF049 +:40748000E8FC20460FF028FF0D49002914D10D48224600682946436930469847084988420AD1284680308178F2B2491C8170FF232146284600F02FFAF8BD0000AC1E0008C5 +:4074C000FFFF0000FC01000800207047F8B5434D0646E8680078002805D007F0EFFD002803D00C20F8BD0220F8BD3078711C05F08DFB0446FF280ED005F024FA3848317891 +:407500000068826B701C90470746204602F0A0FD002F02D060E01F275EE0E968087800285AD0421EA24246D0C200101A4968821FC01F8A18085C114602F0C8FDFF2802D0E5 +:40754000214602F049FDE86842680078C100081A801F1118E000061B701C009010180622FCF7C7FFE86842680078C100081AC01F115C9155E868426800981218204603F08D +:407580006BFAE8680078401EC0B205F0DBF9E86841680078C200101A801F081806220021FCF7B0FFE868002142680078C300181AC01F11540CE04868E1000C1B611C4018B9 +:4075C00006220021FCF79EFFE968002049680855E8680178491E01703846F8BDCC010008EC01000810B500F05BFA0CF01DFE002010BD000010B5014605220A48FCF779FF97 +:407600000849052208463438FCF773FF01F000F9044880224438C17B1143C17300F088FA10BD0000A021000810B5044600786178E2780843A1781143084321790843617917 +:40764000084305D007F024FD002803D00C2010BD122010BD204605F0D1FB002010BD000010B50078002105F02FF8024902200876002010BD5C21000810B502788178407804 +:40768000002305F037F8024901200876002010BD5C21000810B50C4605F08AFC064A117E012900D1002000211176022121700CF03DFA002010BD00005C210008024A936853 +:4076C0000360D06808607047CC01000870B505460024800708D50948807A400604D500F06FFA002800D10224680705D500F086FA002801D104200443204670BDAC1E00089E +:4077000010B5FBF765F905F041FF074807F034FE012000F033F8040001D105F01DF909F041FD204610BD0000B81E000870B50024104D114E002811D0304608210C30FDF745 +:40774000D1FD0404240C13D1287FC100091AF068001DFDF7C7FD0404240C09D1F06800210170297F4068CA00521A0021FCF7CAFE204670BDCC1E0008CC010008F1B54D4874 +:407780009F22817A82B0114000248172FDF7C8FD0746807AC00706D0474802990068C268384690470446B87A800708D5002C7CD1424802990068C26A384690470446002CE8 +:4077C00073D1787A102809D83A492031009108770298FFF7ABFF040002D066E0384C64E038480025457045734571C5750576457645758570C5708571C573042144300173E1 +:407800001F21C1809B21417245732E4EFF2020363073757300F09CFB07F0CEF802F0F6FA30462030C5700298012814D100980178D02041433046FDF755FD0004000C08D131 +:407840000098007841012048FDF74CFD0404240C01D01B48FEBD002507E02846029902F04FFA040005D16D1CEDB200980078A842F3D8144900204431C87288724439887335 +:40788000401E4883FF200877B87A0121000700280848C27A01DA0A4301E052085200C272032030757075F175B1750849002008702046FEBDAC1E0008FC010008EC010008FA +:4078C000FFFF00005C210008D00100087A01000870B505460E46084605F016FE0446304605F04AFE0121A9400A46224001400A4301D0012070BD002070BD10B5044608467D +:4079000005F03AFE0121A140014201D0012010BD002010BD7047FEB51C4616460F46054602F0A8FFA878FFF779FC02460190334639460094284600F00DF8002808D1A87853 +:407940000199FFF789F9FF2C02D138460FF0C4FCFEBD0000FFB50D4685B004468178164610460E9F05F07AFE00280ED0FF2F27D0C8200159F800031D0A58C01DCB5C085C65 +:407980005278834216D9012716E02648D022016AA078504385300A5C002A01D1224A927C521E0A54FF2F02D128460FF095FC012009B0F0BD9006870F69460898088108E0E4 +:4079C0006878A9788006870FE8780002014368460181204602F044FA0390002806D032462946204600F0C3FD0398E1E7384600F0F4FE074604A800903B4602AA21460196F9 +:407A0000284600F02FFC094BB200A178D218FF208854684600893B46C2B2A078314605F047FBE1E75C210008F0210008C5210008F8B518480026009027E000253046FFF718 +:407A400083FB07001ED01448D022016A3046504385300C5C12E0601CFBF75AF8CCB23846E040C007C00F07D02146304603F0CCF821463046FFF712FC6D1CEDB20748818A82 +:407A8000A942E8D8761C0098F6B20078B042D4D8F8BD0000CC1E00085C210008F021000810B5FEF729F90020FFF768FE04F054FFFAF74EFF032803D1FEF7D8F9FEF716FA47 +:407AC0000FF0C6FC09F06EFB002010BDF8B5002400F04CF90125012800D1012406F0F0FE012801D1022004430F4E1049002004270A78336A0FE0D021414359180979002943 +:407B000007D001290BD002290BD0082181402143CCB2401CC0B28242EDD87470F8BD2C43F7E73C43F5E700005C210008CC1E0008F8B5FF2069461E4E0870F07B0024C009D1 +:407B400035D01C4D15E0D020316A60430F188320C05D01280BD102236A46FF21384602F0DAF901280ED04420C05D01280AD0641CE4B22878A042E6D8F07B4006400EF0730D +:407B8000002410E04520C05D00280FD10121384600F0D4FC0AE0D020316A6043081800F092FC641CE4B22878A042F4D80020F8BD5C210008CC1E000810B5FFF787FF10BD53 +:407BC000F8B500252C460B4E0EE049682C20604308180122694607F005FE0006000E01D0054D05E0641CE4B2B1680878A042ECD82846F8BDCC010008FFFF0000F8B5002535 +:407C00002C460C4E0FE04068E100091B401801226946FFF779FB69460870002801D0064D05E0641CE4B2F0680178A142EBD82846F8BD0000CC010008FFFF000010B5084C54 +:407C4000FDF754FE052809D02078012806D1FDF74DFE052802D020780028F1D110BD0000CC01000810B5FDF741FE012803D0FDF73DFE0228F7D110BDF8B504468079254681 +:407C8000603517460E46002806D0687FFDF79CFF0020A071FF206877A671002E09D0687FFF2806D12046A178024B3A467D30FDF727FFF8BD7992001010B5827904468A431E +:407CC00082716034607FFF2803D0FDF77DFFFF20607710BD30B50D4C022061690C4B8AB29978002901D0022906D11D785B78EB18282B01D9032002E0032900D10120510516 +:407D0000490DC0020143616130BD0000C0113C40BA21000800B500F031F8002807D0012805D0032801D0042801D0002000BD012000BD000002460448806901040020C90C12 +:407D4000114200D00120704700103C40014600B50020C90701D000F009F800BD014600B50020C90701D000F001F800BD0248006AC005C00F7047000000103C4004488069EE +:407D800080B2410501D5042070474007800F704700103C4038B50446000610D5FFF7EEFF01280CD1684603F033F86846007800F0E3FB012002F0E8FD0220FFF7FDFE034860 +:407DC000006801692046884738BD0000EC01000810B5034A0178117004F084FF002010BDBA21000870B50446FFF7C0FF002801D00C2070BDA27B01212848002A827801D025 +:407E00000A4301E05208520082706279012A0AD0C17849084900C1702079214E012806D0042804D00AE0C2780A43C270F4E70622E11D301DFCF75DFBA079B072194D28681E +:407E40000168204688472079012808D06188208806F0A2FB2080207904280CD013E02868C168E01D88470021E01D04F0A3FF0120C002208007E02868C168E01D8847002129 +:407E8000E01D04F097FF2079B070204604F038FFB07A05F0EBF8002070BD00005C210008BA210008EC01000808B50178FFF75EFF814201D10C2008BD002927D00720694640 +:407EC0000870FFF75BFF012801D0042808D11A49887A091D02F0FAF8FF2801D00B2008BDFFF718FF01280BD10121684600F092F8012801D0092008BD6846007804F09EF870 +:407F0000FFF7E8FE04F030FF012011E0FFF702FF012806D1684602F07BFF6846007800F087FB04F017FFFFF721FF0028FBD10220FFF742FE002008BDBA21000810B5034A41 +:407F40000178517004F0EEFF002010BDBA21000838B5002168460FF035F9002801D01F2038BD01210098C90201804180002505714571857107214173857304F0C1FE009CCF +:407F8000202200212046FCF7BDFA25702A460021601CFCF7B7FA204604F0A4FE204604F0C1FF00980FF098F90B2200210248FCF7A9FA002038BD0000BA21000810B5044695 +:407FC0000748844209D8204601F0C6F8002804D00089A04201D1012010BD002010BD0000FF0E0000074A9179491C8906890E917138220A4092014907090E114308430249E5 +:40800000084070475C210008FF0E0000C006C00E70470000F3B5174B0E4618781649401C164AC4B281B000200978126A10E0A14200D80024A14201D8002502E0D025654368 +:4080400055192F79002F07D0401C641CC0B2E4B28142ECD80020FEBD1C700021204601F04FFE2E712046FFF7BDFF2881019804700120FEBDE0010008CC1E00085C210008A4 +:4080800010B507F0D9F80222002100F003F804F08BFB10BD10B5094B40074907000F090F185A595A40185043C0086421FAF730FD002800D1012080B210BD0000C846001033 +:4080C000F7B54120405C88B015460C46002802D02878042802D200200BB0F0BD6946087200262046FFF794F8012800D00126204603A93C300191009023460327217F38333B +:408100003246606A07F058F902A8089900900B46019120463A4603A9283006F0E5FF06006846007A287002D1204600F0C1FA204601F0D2FD3046CFE7FFB587B00C460546AF +:408140001078694608724120005D1746002829D000262046FFF75CF8012800D00126204603A93C30019100902346217F38333246606A07F021F902A80090291D019120463D +:408180002B1D03A928300A9A06F0AEFF05006846007A388005D1204601F09EFD204600F087FA28460BB0F0BDFFB50C464020415C25468035107889B0164600290BD06946DF +:4081C0000873C0B2002814D000272046FFF720F8012810D010E0002100910190A078099B129A0C9903F038F80120E87100200DB0F0BD1F20FBE7012703200890204604A964 +:408200003C30019100902346617F38333A46206A07F0D2F8A0780C9902F066FF0F4A0999801803AA01900B4600920291204604A92830089A06F0A5FF02466846007B30701E +:408240000120E8710C99064DA3788900491912985854204601F04AFD1046C8E700103C40C5210008FFB506464020405C89B015460C46002810D0084601F0F2FD01280BD0F7 +:40828000288869468883002813D000272046FEF7BFFF01280FD00FE02878002100910190A078331DFF22139902F0D6FF00200DB0F0BD0220FBE70127204603A93C3001916D +:4082C00000902346617F38333A46206A07F074F8A078139902F008FF00900C4A009912988918029007AA009201912046331D03A928300C9A06F045FF02466846808B28809C +:40830000204601F0F3FC1046D1E7000000103C4070B5054680350446E9784030002908D0012905D10179042902D14078002808D070BD01790C29F8D00D29F9D1287800287E +:40834000F6D0A078FEF700FF2979C840C007C00FEED0A07802F058FC2979A078FEF79EFF70BD000010B518490446484028D0002101231A468A40904221D0491C2029F8D3BB +:4083800000212046C840C243520618D0400616D0491C1929F5D3A0B2210C020AC3B2884201D193420BD01F21204600F01BFA182805D8A00E062100F015FA022801D2002049 +:4083C00010BD012010BD0000D6BE898E70B50D460446FEF71DFF01280AD0E87AA97A00020143A07802F0E0FE012808D0002070BD00222421204606F03CF8242070BD28218F +:408400005A200155204600F037FD282070BD000008490978814201D8002004E00649D022096A504308188030C079012800D0002070470000CC1E00085C210008014610B558 +:40844000002049070FD5094A0021146A084A137807E0D0224A43A2181279022A04D0491CC9B28B42F5D810BD012010BD5C210008CC1E0008014610B5002049070FD5094ACF +:408480000021146A084A137807E0D0224A43A2181279022A04D0491CC9B28B42F5D810BD012010BD5C210008CC1E000810B5044601468034E06A002804D089780EF02AFF71 +:4084C0000020E06210BD38B50546002000902846FEF79EFE01282BD1284601F0B6FC002826D028792C46C01E4034030002F0FCF90705051B1B051B201B00284601F0B6FC10 +:40850000012810D0284605F09BF900280BD0284605F0A0F9012806D0A97868460EF068FE002803D105E06079002801D10120607138BD2846009905F0EDFD38BD4030417172 +:40854000704740308171704770B50546403528790C46052904D0002C05D1801E022802D8022006F003F82C7170BD017170479200101880304161704770B53C2502F0AAF8CA +:40858000040004D020460021473002F007FD0023FF222946204600F05BFD002C02D0A07802F00EF870BD000010B50B490978814201D8002404E00949D022096A50430C18A7 +:4085C00020217F200155002C05D020890BF0B4FC204600F06DF810BDCC1E00085C21000870B505460F480078A84201D8002404E00D48016AD02068430C18002C11D02079C2 +:4086000007280ED1204600F0BAF8204605F0E0FF0A21484302462046044B29467F30FDF76FFA70BDCC1E00085C2100089DA0001010B502F04FF8002802D0807801F0C0FF2B +:4086400010BD38B5044600206946087001236A46FF21204601F018FC054601236A46FF21204601F058FC2843012812D0214640318A79002A02D1087901280CD048790128A8 +:408680000DD0022A0FD0E079400602D5204605F04BFF002038BD204601F0C2FEF9E72046FFF711FFF5E7204600F028F8F1E7000010B50446408A00280DD00748F521807AD8 +:4086C0000840C00607D5204605F082FF82B2618AA07803F0BFFF10BDAC1E000810B50023054C0B60A48A944205D992001018803042690A60436110BDF0210008FEB506469F +:40870000002000900190A8208559B17868460EF06FFD002801D00720FEBD0098374660370290344678884034608238882082E08BA082304605F035FFA88CE18B884207D158 +:40874000288A3988884203D1688A7988884203D0F07920210843F071688A7880288A3880A88CE083FEF766FBA083E08BFEF772FBE0763046029905F009FD0198FEBD38B52E +:40878000044600200090A07900280FD14420005D052801D00E2809D1A17868460EF028FD002803D12046009905F034FE38BD10B501F054FE002010BD70B50C4605460146D0 +:4087C000204605F025F8002805D0A17828460EF095FD232070BD0D2070BD002800D102207047704770B500231A46491E0CE00446D440E507ED0F541C0646E640F407E40F89 +:40880000A54200D05B1C521C8A42F0D3D8B270BD30B50021124C0A46A05C002308E0C50701D0491CC9B201290AD840085B1CDBB20028F4D1012903D8521CD2B2052AEBD3F5 +:4088400002290BD207488118C87B0122082B03D29A400243D0B200E01043C87330BD0000A02100085C2100087FB504468034E16A05460E46183108226846FBF73AFE314672 +:408880002031082202A8FBF734FE102168460EF033FCE06A102108300EF02EFCE06A2B46083028331022694606F056FC7FBD10B504460821FFF700FA10212046FFF7FCF92B +:4088C0002079052822D0062820D008281DD1218900200BF07DFA072020712046FEF798FC012819D00E212046FFF72EFE002180200155204601F06EFE2046FFF7D7FD204668 +:40890000FFF7D6FE2046FFF79CFE10BD2089012200210BF041FADEE70521E4E7FFB581B01F4604460821FFF7C7F910212046FFF7C3F92079082803D0092804D0042503E068 +:408940000425012601E009250026204601F074FA00212046FFF7F8FD25712046FFF7A6FD0398002E02D0012808D00BE001280AD12089002202990BF00FFA04E02189029889 +:408980000BF026FA0127002180200155012F07D0204601F01FFE2046FFF753FE05B0F0BD5A2102980855204605F090FD054605480121428A2046FFF75FF9002DEED109202A +:4089C0002071EBE7AC1E000870B50C460546FEF71FFC012809D108212846FFF76DF90023012221462846FFF799FF70BD10B5044601F022FA2046FFF759FD00212046FFF759 +:408A0000A3FD10BD70B505461A24FEF701FC012809D108212846FFF74FF90023012221462846FFF77BFF70BD38B5044600200090A17868460EF0DCFB002801D00D2038BDFB +:408A40002046009D01F0A4FB2946204605F05CFC05480821428A2046FFF70EF906212046FFF772FD002038BDAC1E0008F8B50446002000900E46A17868460EF0B9FB002827 +:408A800001D00D20F8BD204604213830009D0EF010F9AC200059082118300EF00AF9012E02D1204601F074FB2946204605F0B0FB05480821428A2046FFF7DEF8022120469B +:408AC000FFF742FD0020F8BDAC1E000810B50446FFF7CAFE03212046FFF736FD204601F0C9FE10BD10B50021FFF7C0FF10BD000038B5044600200090A17868460EF078FBA8 +:408B0000002811D12046009A01F096F91146204605F005FC05480821428A2046FFF7ACF807212046FFF710FD38BD0000AC1E000838B5044600200090A17868460EF058FB5F +:408B4000002810D12046009905F0B5FC06480821428A2046FFF790F804212046FFF7F4FC204601F087FE38BDAC1E000810B5FFF79EFE10BDF8B50446002000900E46A178D4 +:408B800068460EF035FB002801D00D20F8BDAC20005908212030009D0EF08BF8204604213C300EF086F8002E02D1204601F0F0FA2946204605F053FB0E480821428A2046C4 +:408BC000FFF75AF8204601F08AFD00280AD0204600F026F8002803D009212046FFF7B4FC0020F8BD08212046FFF7AEFC204601F041FEF5E7AC1E000810B54421095C0829A0 +:408C000006D0092908D00A2901D100F09BF810BD0B21FFF799FC10BD00F002F810BD000070B504460079052805D0062803D0082811D00C2070BD03220621204605F019FCB3 +:408C40000F480821428A2046FFF716F811212046FFF77AFC12E006215A200155204605F035FC05466220025B0A20424301212046FFF702F8002D01D109202071002070BD6E +:408C8000AC1E000838B5044600200090A17868460EF0AEFA002801D00D2038BD2046009D00F074FA08202071204601F071FA2946204605F034FB0021412001550F21204630 +:408CC000FFF742FC204601F0D5FD002038BD10B5024601F0B1F810211046FFF735FC10BD10B50446FEF794FA012809D04420005D112805D100231A4606212046FFF70EFE6A +:408D000010BD10B5FFF7D3FD10BD000038B5044600200090A17868460EF06AFA00280DD12046009905F0C7FB05480821428A2046FEF7A2FF0D212046FFF706FC38BD000083 +:408D4000AC1E000838B5044600200090A17868460EF04EFA002801D00D2038BD2046009905F09EFB05480821428A2046FEF784FF0C212046FFF7E8FB002038BDAC1E000812 +:408D8000007870477CB536490978814201D8002404E03449D022096A50430C18002C5DD0204601F052F8002858D0207903280CD005280CD06220015BA07804F0D7F82646FE +:408DC0004036B079012805D030E0042000E0062020712BE00021204604F069FD25468035A86A002804D0A1780EF094FA0020A8620020B071E87801280CD02046C030417B6A +:408E00007D22114041732046FFF71BFC2079072805D007E02046C030417B7E22F1E72046FFF746FC0221204601F03EFD0E48407BC00713D02079042810D120896946088079 +:408E40006034207A88702089000AC870A07A08716089000A487168460BF028FA7CBD0000CC1E00085C210008A021000810B55A22115400F05DF810BD10B50446FF21FEF782 +:408E80001BFF09202071A07804F0B2F810BD000010B512490978814201D8002404E01049D022096A50430C18002C15D0204600F0DDFF002810D10B480068C169204688473B +:408EC000E07EC00608D4BC20005D012804D10648006801682046884710BD0000CC1E00085C210008FC0100080802000810B504468079002809D022215A200155FF212046EA +:408F0000FEF7DAFE204600F013F810BD10B5037902464032002B03D09176092B02D003E0002100E02221917600F002F810BD0000FEB5044600890027009027812079254662 +:408F4000803500282FD001282DD002282BD0002005F00CFB0AE002AA01A9204604F044FC002808D1A17801980EF0C8F9204604F067FC0028EFD0FF212046FEF79DFE204642 +:408F8000FDF798FE3049AF70887B002804D0401E0006000E887306D1F9F7C0FC2A4840304770F9F7A5FC26466036B07FFCF70CFEA86A002803D0A1780EF0ACF9AF62E86A1C +:408FC000002803D0A1780EF0A5F9EF6225464035A97E002934D0009800F0B6F8F07FFCF7F3FD2046FFF74CF8A07802F0C1F8204602F0ACFEA0780AF0E1F8E87B02F0B8FB5C +:40900000A87BFF26FF2805D0104909680A6C00219047AE73EE73A07801F0D2FA0B20FEF7CBFD01F02DF9F9F793FC032807D10648807B002803D1FF20F530FCF735FFFEBD71 +:409040001F21A976C7E700005C210008EC010008FFB583B01E461746054606F0D7F804006AD020460C303146009001F079FF2046062200211830FBF745FA2046062200218A +:409080001230FBF73FFA2D48224600683946836A284698470190049820702846FEF7B8F8012148402E4640366070002D11D028896080F07920710498002811D16879607120 +:4090C000F08BE08028466030018821814088608109E01B488069C005C00F2071002060800498022824D02846062248300099FBF700FAFF2F11D0114801210068026C38463E +:40910000904710482C220068416838465043021D8A180A30085C114601E02079009903F075FD0546FF2801D003F034F8B773F573204601990AF0CFFD07B0F0BDEC0100084F +:4091400000103C40D40100080A4610B5014600200AF00AFF10BD000000B50146FEF756FF084A1278824201D8002004E0064AD023126A58431018002802D002898A4200D0D4 +:40918000002000BDCC1E00085C21000838B504468034E16A002907D1817868460EF03AF8002801D10098E062E06A38BD10B5014600F056FE012803D08878FEF733F810BD01 +:4091C0000348026A8878D02148438430105C10BD5C21000870B5054604468035A879012811D10948A178026AD02048438430165C3046FEF76DFB002805D10220A871A07894 +:40920000314603F0BFF970BD5C2100080EB500220A216B460292198100905A811046029B00990EF04CF90EBD70B5104DA87A00281AD00F4C217FFF2916D0608B01F036F89D +:40924000012811D10020A872401E6083FF20207701F0EAFD044601F021FF010002D0204600F0D8FBFEF7E4FB70BD0000A02100085C2100087047000070B5104AC0B2117803 +:40928000491E11700E490978814201D8002404E00C49D022096A50430C18A07900280BD025466035687FFF2806D02046FFF71EFE0020A071FF20687770BD00007A01000882 +:4092C000CC1E00085C2100087047490510B5490F0B0001F009FB060704080C0C0F073E21FFF7C4FD10BD0821FFF710FE10BDFFF71FFE10BDFFF7FAFD10BD0000F8B52B48F7 +:40930000002500904DE0A84201D8002604E02848016AD02068430E18F9F700FB30464030C48A078B0021C1820183F9F7E1FA304600F08BFD012831D1A00702D52846FFF783 +:4093400021FDE00602D52846FFF7A2FDA00602D52846FFF75BFF600609D5F9F7DFFA1449002040314870F9F7C3FA00F005FF200602D5284600F020F8600702D5284600F071 +:4093800043FCE00703D021463046FFF79EFFF80704D00849B0780968496988476D1C0098EDB20078A842AED8F8BD0000CC1E00085C2100080802000805490978814201D8B5 +:4093C000002070470349D022096A504308187047CC1E00085C21000810B50446054800680168204688470448006801692046884710BD0000FC01000808020008F8B5054673 +:40940000FF20694608702888FFF7A6FE040035D000F01BFD002831D0207909282ED002236A460021204600F076FD012828D02046FDF7EEFE0646E07920210843E07120468C +:4094400004F052FA002823D0294601F005FA02236A46FF21204600F017FD01281AD04620005D00281BD02325E079DF210840E0712946204604F08FFB2846F8BD0220F8BD63 +:4094800068460078012801D02A20F8BD2320F8BD0720F8BD02204034A0710020F8BD002E05D02046FFF72AF90500DDD1E4E70C20F8BD000070B50E460C2501F0EDF80400D8 +:4094C00013D00025228929460A480AF073F80123FF2202212046FFF7BBFDA07801F0F2FB2046FFF725FD022000E000203070284670BD00000E200000F8B5044601F0CCF86C +:40950000002801D00C20F8BD6079A11D00F0DEFDFF2801D00B20F8BD02216846FEF77AFD012859D13248017868460078814201D8002504E02F49D022096A50430D18002D07 +:409540004AD000212846FEF7FFFF2E46002040367071B0712848002100684268284690470620FEF729FB2F46208A60373880E289A189A87809F0A4FCF083608A78800420E7 +:40958000F0760320B0831B4806228778A11D2430FAF7AFFF2079012820D06079F0710121A01D03F007FCFB20074012488770217E012918D0C278FB210A40C2700F482146FF +:4095C0000068826828469047A978204603F0C2F82846FFF7ECF8F8BD0920F8BD0020F07104200743E1E7C17804221143C170E5E7CC1E00085C21000808020008EC010008E0 +:4096000070B5164602461B480D460078D0211A4B5143904201D8002401E0186A4418002C26D0204600F01CFC012809D1186A8431405C1146FEF74CF9002801D104F07AFE5E +:409640000E483146006882692046904700280CD0204680308178A94201D3491B00E000218170208929460AF0F4FB204601F002F970BD0000CC1E00085C210008FC01000869 +:4096800070B505460088FFF767FD040014D000F0DCFB002810D02079092822D0A97825464035A976204604F011FF0646A879012804D06220025B02E0022070BD6A8A0A20C3 +:4096C000424301212046FEF7D7FA01F055FB8021204602F059FD01F06BFB002E01D109202071002070BD0EB5002218216B460292198100905A810120029B00990DF0DFFE10 +:409700000EBD0000F8B5194E0025B07A002824D101F0C4FC26E001F0BBFC1549401801680068CCB287B22146384600F0BFFD012814D010480121478304774577B1720E49AE +:409740000978A14201D8002003E0006AD0214C430019002801D001F08DF8F8BD01F09EFC6D1CEDB20028D6D1F8BD0000A021000800103C405C210008CC1E000810B5044670 +:40978000C0060FD50C4900200B6A0C490A7807E0D021414359180979022909D0401CC0B28242F5D806480068C1692046884710BD00F050F8F6E700005C210008CC1E00081E +:4097C000EC01000810B50088FFF7C6FC040007D04420005D082805D00B2803D00C2010BD022010BD2046FFF71BFA002803D009212046FEF7A9FE002010BD70B50546008863 +:40980000FFF7AAFC040008D0264640363079082805D00B2803D00C2070BD022070BDAC20005910220830A91CFAF763FE2046FFF71BF83079082804D02046FFF783FA0028AF +:4098400003D00A212046FEF77FFE204601F012F8002070BD70B51E491E4D0978814201D8002403E0D0212A6A414354182179022904D0002901D003F0BBFB70BD01228321A4 +:409880000A5501F03FFC032020710820FEF794F900212046FEF758FE0121204601F004F8204647300121064601F078FB0A480068416A304688470246012300212046FFF736 +:4098C000C7FBA078FFF788FDA87B401CA87370BDCC1E00085C210008EC01000810B50C46002121700088FFF737FC03000BD000F0ACFA002807D00948F521807A0840C00684 +:4099000003D4112010BD022010BD022020705A8A188900210AF044FB002010BDAC1E000870B50088FFF718FC040008D000F08DFA002804D0E079C10903D0002070BD0220A8 +:4099400070BDC1068025002908DA2843E07108480221428A2046FEF78FF9EEE7204600F053FC0028ECD1E1792943E17170BD0000AC1E0008F8B50F46002569460D702E4628 +:409980000088FFF7E9FB040010D000F05EFA00280CD0E079410638D4E17E4A0708D48A074021002A1BDA0843E0712EE00220F8BD05F02CFC067021894180E1898180A17EC3 +:4099C0004170218A0546C180022038702978104809F002FF28460AF087FA0020F8BD0843E07102236A460C21204600F04DFA00280BD102236A46FF21204600F08CFA0028CC +:409A000003D1204604F090FD05462846F8BD00001D0400003EB500220F236C460292238100910190628169460EC900200DF047FD3EBD0000F8B50F46054600F04BFE04003A +:409A400052D0032020710026832006552046E6703146473001F0A2FA05F0EEFB25464035EA8B6179FEF716FB1030FF2281B249321346204604F094FD0920FEF79DF8A07884 +:409A800001F05CFB0021204600F00EFF00212046FEF75AFD6E710023AE713A4619462046FFF7D6FA1248002100684268204690471048817B491C8173A078FFF78DFC00F0DD +:409AC000EBFD040007D00B480021243003F072F9204600F0C3FCF8F73BFF032803D14034E08BFCF725FAF8BD284603F081FAF8BD080200085C210008F8B50446FF206946AD +:409B0000087000262088FFF727FB05001AD0FDF77FFB002812D02948807AC00710D0284600F093F900280DD0287903280CD004280AD0072808D0092836D103E00C20F8BDAE +:409B40001120F8BD0220F8BD4420405D01282BD02846FFF71BFB070028D00822211DFAF7C8FC3846A1782030017261881022090A417221460C311838FAF7BBFC02236A46C1 +:409B8000FF21284600F0C7F9012811D002236A460521284600F078F9012809D0284600F03FFC06463046F8BD0D20F8BD0720F8BD01212846FEF7C8FCF4E70000AC1E0008CD +:409BC00010B50E4AC0B21178491E11700C490978814201D8002404E00A49D022096A50430C18208B102108432083A07803F000FA08212046FFF78AF910BD00007A01000855 +:409C0000CC1E00085C21000810B517490978814201D8002404E01549D022096A50430C18002C1AD020464030417902290BD1002141718320005D012810D02046C030417B4E +:409C40007D2211404173207E0021C207D20FA07803F078FA2046FEF7F4FC10BD2046C030417B7E22EDE70000CC1E00085C21000870B505460E460088FFF76EFA04000BD0BC +:409C800000F0E3F8002807D01248F521807A0840C00603D4112070BD022070BD6020005B5E21095B401C48430004C10C6888884201D2122070BD60822079072802D1204699 +:409CC000FEF7F6FC02203070208900210AF090F9002070BDAC1E0008416A491C416204D1017F491C4906490E01777047016A491C016204D1417F491C4906490E41777047CB +:409D0000F3B506463D4881B00078B04201D8002404E03B48016AD02070430C18002C05D0FBF7FEFA807AC00702D00EE00220FEBD2546C0352F68F8F7F1FDD02200212046E3 +:409D4000FAF7E0FB2F60F8F7D3FD2E480299006882682046904705004DD1A6700026E676267131462046FEF7EFFB204600F064F8204603F05FFD244F6782862006551F48F0 +:409D8000F5212038807A084000D00120A07526830298002805D020462021C030FBF7A2FA85B2C020005920220021FAF7ABFB4C20A664065320464030C671FF21C1738173FA +:409DC0000122603042750275C27582754276027603228276C27606774277002022186032401CC0B251770328F8D305484030C07820736034E780E8B2FEBD0000CC1E000857 +:409E00005C210008FC010008FFFF000010B50020074B084AFF2119541418401CC0B221740428F8D31F2119541018017410BD0000A02100085C2100080021416201770162FA +:409E4000417740300170417070470079002805D0012803D0022801D0012070470020704780308079002800D00120704740300079002807D0012805D0052803D00E2801D05F +:409E80000120704700207047F0B5002405461470C07E0126C006002803DA0124142900D116702846FFF7E2FF002803D00124052900D11670E87E470708D480070ED5012469 +:409EC0000C290BD11670E87E400707D5E87E800704D4012B01D10C2905D001248320405D012802D008E00024F8E7A879800703D50124082900D11670012B02D1092900D1FB +:409F000000242046F0BD10B5807803F035FB002800D0012010BDFFB581B0019F04980026403714460D46022810D17879012803D1012D00D120700126B879022800D10126B7 +:409F4000019803F087FC012800D1012600232370797980208122022908D1012D02D0002D02D002E0227000E020700126B979012908D10126002D02D0012D02D002E02270E9 +:409F800000E020700198A030017F032902D0042908D003E0162D11D101262670007F022804D00BE0162D09D1002607E00126182D03D0162D01D0172D00D12270049802282E +:409FC00006D12078C00702D00120207000E02370304605B0F0BD000010B5084A1278824201D8002004E0064AD023126A584310184030C173084602F0CDF810BDCC1E000831 +:40A000005C210008F8B500240F4D104E17E0A04201D8002103E0D020316A604309180846FFF713FF002808D00F464037F87BFF2803D001F09DFBFF20F873641CE4B22878B3 +:40A04000A042E4D8F8BD0000CC1E00085C210008F8B5064600240F4D18E0A04201D8002104E00D48016AD020604309180846FFF7ECFE002808D00F464037F87BB04203D13E +:40A0800001F076FBFF20F873641CE4B22878A042E3D8F8BDCC1E00085C21000810B50449C0B20A78521E0A70FEF77EFA10BD00007A01000810B50449C0B20A78521E0A7098 +:40A0C000FEF78EFA10BD00007A010008F3B50024C70781B0134EFF0F1FE0A04201D8002504E01148016AD02060430D182846FFF7ACFE00280FD02946062248310298FAF76A +:40A10000E9F9002807D14035E879C007C00F874201D12046FEBD641CE4B23078A042DCD8FF20FEBDCC1E00085C21000830B50446FF281BD000210E4B0E4D14E0884201D8C3 +:40A14000002203E0D0202A6A484312181046FFF77CFE002805D04032907BA04201D1012030BD491CC9B218788842E7D8002030BDCC1E00085C21000810B500F055FE0446D0 +:40A1800000F08CFF010002D02046FFF743FC10BD70B5054604468035A879002827D1FF20E075174BA078D0225043196A85300A5CD026521CD2B20A54A078196A7043114E35 +:40A1C0008530768AB24201D300220A54A078D02250430246196A85328E5C84300E54A1783046FDF775FB002802D00120A87170BD0220A871A078314602F0C4F970BD000049 +:40A200005C210008F02100087CB50446FF206A46002110700191014602232046FFF77BFE01280FD002236A4608212046FFF72CFE012807D0A17801A80CF0DAFF002809D09E +:40A2400007207CBD68460078002801D023207CBD2A207CBD2046019DFCF7DAFF00280BD02946204604F016F804480221428A2046FDF702FD00207CBD11207CBDAC1E00088D +:40A2800070B50024074E084D07E0D020316A60430818FEF7D6F9641CE4B22878A042F4D8002070BD5C210008CC1E0008F0B50F46810785B0890F0291000A6946888055484A +:40A2C0000078B84201D8002404E05348016AD02078430C18002C26D000F0DAFE06466846808800280BD00298012840D002283ED0032809D04120005D01286ED085E047481F +:40A3000030180068608180E000200290A17802A80CF046FF002807D04120005D012877D12046FFF7D9FC73E06846029D82882946304602F095FF394830180068608120468A +:40A34000FDF7E6FF01AA21462846FDF7B9FE002807D0384600F0C0FCA17828460CF0B0FF28E0EF772946204603F094FC4DE00020009020890390A17868460CF0FFFE0028B7 +:40A3800002D0002005B0F0BD6846009D8288291D304602F065FF2148301800686081384600F09AFC2046FDF7B3FF8020005D00280FD106E03D205A2108552046FEF75CFD04 +:40A3C00026E001AA21462846029BFDF7B5FE002804D028460CF06AFFECE713E00298FEF700FA01460398287003980901000A0843687068468088A870000AE8702846FFF795 +:40A4000072F905E02046FFF767FC384600F064FC0120B7E7CC1E00085C21000800103C4070B501790546032904D0042904D0072908D109E0052400E006240121FEF716FB45 +:40A44000002805D00D2070BD0824FEF7EDFAF7E7284600F00FFA2C71002070BDF0B587B0054604F0D3FE044604F0C9FE019004F0BCFE009004F0CEFE029004F0DDFE0690D7 +:40A480000098207000982F46000A607000984037000C0590A07000982E46000EE070F87E20710198607101986036000AA07101984149000C0490E071387F2072B88B0522E1 +:40A4C000000A6072B87FA072F88B000AE072307820733088000A6073B078A0737088000AE073204610300391FAF703F80020E870A878039902F0C8FD0020687106980299B5 +:40A500004001084300216175A075000AE07504E0F98B288849004018288000F0A5FC2988042200F05FFE0128F2D023481038417C027C090211433182C17C827C0902114389 +:40A540007182007DB0820298307600983081059870810198B0810498F0811848298801601821204602F0A6F87088F98BC000F8F7CFFA124980B28860012183204155A878C6 +:40A5800000F07EFBB188A87802F0F8FBF98BA878042208F02BFAF8F71DFA0446A87808F0E7FC06494031086200F07CFB2046F8F715FA07B0F0BD00006C21000800123C4046 +:40A5C00010B50021FFF79CFB002801D0002010BD012010BDFEB50546803001908079002839D0AE780096D021294C4E433746206A8437C05D0099FDF780F9012828D0226A66 +:40A600002046D15D491CCCB22249498AA14200D80024019B002199713346FF218533D154026A8636D1550021006A0B4681550A46009802F0C7FAE97DFF2904D0284603F0EB +:40A6400064F8FF20E87503F075FE0026114F1AE0019803218171FEBD00200090224669462846FEF73BF80099002904D0FF231A462846FDF750F9641C788AE4B2A04200D8C0 +:40A680000024761CF6B2788AB042E5D8FEBD00005C210008F021000800B5022000F002F800BD000030B5044608480021036A0848027807E0D020484318180579A54204D012 +:40A6C000491CC9B28A42F5D8002030BD5C210008CC1E000800B50120FFF7E4FF00BD10B5044604F093FD218901808034E16A4160E16A2831816009F085FB10BDF7B50746CF +:40A700000C460879897882B0092807D0F9772046FFF7A6FB4D4E012806D00FE038460CF0EDFD022005B0F0BDA178D0204843326A8430105CFDF7CCF8012824D0A078FDF7FC +:40A7400067FE01281FD03D780121384603F0CCFC2046FEF72BFD0190A17802F07FFF002818D0204681213A4AC0300C2D3ED023DC26464036002D26D0012D27D0062D33D07D +:40A780000B2D4BD128E06846027C21463846FEF713F8C7E7A078D0225043316A85300A5C002A01D12B4A927C521E0A54A17838460CF0A4FD0720B5E7122D24D0142D25D07E +:40A7C000162D2BD104E00122B27101E002227271427B0A43427321E02046FCF719FD01281CD10020307019E00120FBE7E07E400704D4528A04212046FDF73EFAE07E022176 +:40A800000843E0760AE0528A102104E0E07EC00604D5528A40212046FDF72EFA009504AA21463846019BFDF7BFFC69460A7CA0780323019902F03CFCA0780199FCF70CFA8B +:40A84000A17838460CF05AFD00206BE75C210008AC1E0008F02100088A8802804A884280CA8882800A89C2808A890281498941817047000010B50246803293790021002BC3 +:40A8800003D19278002A00D00121064A927A002A00D000210279092A00D10121807802F085FC10BDA021000870B50C460546FCF7AFFC00280BD1012C06D92879092806D06D +:40A8C0002846FFF720FB0446002C02D004E0012402E0287EC007FAD1287E2146C207D20FA87802F02FFC70BD30B47446641E2578641CAB4200D21D46635D5B00E31830BCEC +:40A90000184700000B4B01280BD002280BD004280BD008280CD10748803002630548A83005E0202002E0382000E05020C01801607047000000103C400149886070470000A8 +:40A9400000103C4010B50446FF20F130012C04D0022C05D0042C08D105E0FF20D53004E0FF20D93001E0FF20DD30002202F074FD03490869034A80B2A0431080086110BD63 +:40A9800000103C40E2010008034A1169034B89B2814319801161704700103C40E2010008034A1169034B89B2014319801161704700103C40E2010008F8B5244F14243A680C +:40A9C000054665432C46936813341B5DF1269B0036019B191E4E9B1900931E68B6B2760876001E602C2306465E43002909D190685168035D301D08181649FF22C96902F027 +:40AA000007FB3868A91D80688022035D40181149896A02F0FDFA38680E498068096A035D4019202202F0F4FA38680A4980680C35035D4019496A402202F0EAFA3868012187 +:40AA40004068805B084300990860F8BDD401000800103C40F0210008F8B505460120A84086B214460F46012231467C2002F0F4FC3A463146782002F0EFFC607826780002EC +:40AA80000643E078A27800020243607923790002034307480C2180694D430649401944182660001D44182260001D40180360F8BDF021000800103C40401880B270470000EA +:40AAC00030B5124BCC061B7849095B0701255B0F640E0902ED02012B10D0022B0ED0032B01D0042B09D18007800FD2072843120E0243144306482143816230BD044321439D +:40AB0000D001084303492843886030BDF021000800F13D4080143C4010B5234A12785207520F012A29D0022A27D0032A01D0042A22D1421C13461C78007822465C782402D5 +:40AB400022439C78DB78240422431B061A431202164C0243A260481C024613780978184653781B0218439378D2781B0418431206104300020843E06010BD4278037812020B +:40AB800013430B4A1361C37880781B021843506148780B78000203439361C878897800020143D16110BD0000F021000800F13D4000143C400B4A12785207520F012A09D061 +:40ABC000022A07D0032A01D0042A02D1064A106051607047054A83B21360000C5060916070470000F021000800F13D4000143C40044A002180180268491C89B21029FAD3A2 +:40AC00007047000000103C4010B50C4602F08CFC01494018046010BD00103C40704770B50C46054600F018F821462846FFF7ECFF70BD0000002310B5F121064A09011846D3 +:40AC40008C182360091D401CC0B289B21028F7D310BD000000103C4070B50C46054602F069FC0549054A097D694309190902214389B28018016070BDF021000800103C40A4 +:40AC800010B504490863FF20012220211D3002F0E3FB10BD80103C400149086070470000C0103C4000B50549012088600449442008600420FFF774FE00BD000040123C40AD +:40ACC00000103C400349086302494520803908607047000080103C40054AD1687C2389B2994380000843D06002494D200860704740123C4000103C4070470000054B19688B +:40AD00000722920289B2002801D0114300E0914319607047001F3C4010B5094800784007400F012808D0022806D0032801D0042801D10DF067FA10BD02495420086010BD11 +:40AD4000F021000800103C4010B5094800784007400F012808D0022806D0032801D0042801D10DF057FA10BD02495320086010BDF021000800103C4000B503490888488003 +:40AD8000FFF702FE00BD0000E201000810B5F7F7A7FD012802D10320FAF756FD0120FBF72BFF02495020086010BD000000103C4000B502484088FFF7F3FD00BDE20100082D +:40ADC00010B5FAF779FD10BD03490868012280B2D203104308607047001F3C40884201D8081A03E00022D243101A401880B27047884201D9401A00E0081A044980B28842D4 +:40AE000003D901210904081A80B27047FF7F000000210170704710B50B4602460021F820FAF760FB10BD00000148006BC0B2704780103C4010B50A490978814201D8002443 +:40AE400004E00849D022096A50430C18F7F766FDC0342068C48BF7F74BFD204610BD0000CC1E00085C2100080148806880B27047C0103C400148406880B2704740503D4038 +:40AE800000280DD00C4A90690870000A4870D0698870000AC870106A0871000A48717047064A10680870000A487050688870000AC8709068F0E7000040103C40C0113C4048 +:40AEC00000B5024A00F004F800BD0000FF7F000000B51346FFF782FF984201D8022800D2002000BD0148006980B27047001A3C400148406A80B2704700103C40014840698E +:40AF000080B2704740103C400148006880B2704700503D400148C06B80B2704700103C40F8B50646002402F0EFFA0546304602F023FB064609480021878A0BE001208840A0 +:40AF4000034602462B403240134301D02043C4B2491CC9B28F42F1D82046F8BDF0210008002910D00B4B196B8AB2596B9B6B89B20270120A42708170090A9BB2C17003715B +:40AF8000190A41717047044B996A8AB2D96A1B6B89B2EDE700123C4040103C40012905D0054989690904C90F017070470249403189688907C90FF7E700103C40FFB581B095 +:40AFC00000242D4B2D4D0B9E002805D0022803D003283ED006281DD1A86B2F4684B2A004850E2007000F012802D0252D1AD916E00C2D14D106230021F820FAF773FA0623DB +:40B000000021F820029AFAF76DFA002E01D0B86B1DE0002304980480184605B0F0BDFFF7D3FEF9E706230021F820FAF75BFA062DEFD30A98002806D0AD1F0246ABB200214B +:40B04000F820FAF74FFAB86B002E80B2E1D03080DFE7A86B84B2A004800E0C28DFD106230021F820FAF73EFA06230021F820029AFAF738FAA86BCCE7FFFF0000C0103C40B9 +:40B08000024800684005C00F70470000001F3C400148C06870470000F02100080248806A8006800E7047000000543D40084910B58000084B4218D9687C2489B2A1430843D9 +:40B0C000D8600548101800688006800E10BD00003044010040123C4000103C400148406880B27047001A3C4010B5054B1A8A9C8A5443444398684A432018801810BD0000F4 +:40B10000F021000870B50B4908630B49D024444325460B6AFF2285355A5523460D6A8433EA54096A002286340A550123114601F049FD70BD80103C405C21000870B50B4A6C +:40B14000D02141430D46146AFF23853563550C46156A84342B55126A00238631535400220123114601F02EFD70BD00005C21000870B50B4AD02141430D46146AFF238535E8 +:40B1800063550C46156A84342B55126A00238631535402F0C3F90349C98D02F07BF870BD5C210008AC1E000870B50D460B490978814201D8002404E00949D022096A50435D +:40B1C0000C18F7F7ABFBC0342068C48BF7F790FB02222946204600F005F870BDCC1E00085C21000810B50023884201D8081A03E00024E443201A4018044980B2884201D83A +:40B20000824200D90123184610BD0000FF7F0000024840680006C00F70470000C0103C4070B55478157824022543D47888232602947834435679127936023243002900D02C +:40B2400098230449086303488038181805604460826070BD80103C40FFB581B015460E4607460A9CFFF740FF002C0AD022460B9B049902F021F90549B0004018C55505B066 +:40B28000F0BD0B9A049902F0FDF8F4E7C5210008F8B59C469308394D002403E0A600AF598751641C9C42F9D39207920F4B1C002A06D0012A15D0022A27D0032A39D13EE05F +:40B2C0001D7809782A465D782D022A439D78DB782D042A431B061A4312020A43A100425027E0A600AD590C78CB7822464C781B06240222438C78240422431A431202EBB24E +:40B300001A438251C978301812E0A200AB584C780D7824062D042C431D042D0E2D022C43DBB21C438450CB788C7819022143101841606046012801D1FFF7EEFCF8BDA40087 +:40B340002A59097815022D0E09062D04294315042D0E2D022943D2B2114301511A461B78194653781B0219439378D2781B041943120611430902090A2018D9E750F13D400C +:40B3800070B50C4D2A785407640F012C08D0022C06D0032C01D0042C01D100F00FF870BD02460B46044CA888082121620021FAF71FF970BDF021000880143C40F0B52B4A11 +:40B3C00008232A4E503A5363546B9C435463820703D000238F08BF001DE08C08002203E09300C558F550521CA242F9D3A30014E0C218521C144625782A4665782D022A43D8 +:40B40000A578E4782D042A4324062243C45C12022243F2501B1D9F42EAD88A0724D089070022890F012904D0022904D0032917D107E0C25C14E0C018417800780A0202437D +:40B440000EE0C01801460A7810464A78120210438A78C97812041043090608430202120A0248103818180261F0BD000050F13D4070B51A4909784907490F012921D0022911 +:40B480001FD0032901D004291AD10446FFF75CFC134D00216018401C02461378184653781B0218439378D2781B04184312061043625C000210434A191061091D1029E9D3EB +:40B4C00070BD212504466D01FFF73EFC1023224600212846FAF78CF870BD0000F021000800F13D40154909784907490F012918D0022916D0032901D0042911D1411C0A463B +:40B5000013780078194653781B0219439378D2781B0419431206114309020143084801627047417802780902064B0A439A63C178807809020843D86370470000F021000805 +:40B5400000F13D4040143C4008B5094A127D4243521812020A4380210A4369460A8001F0E9FF69460988034A8018016008BD0000F021000800103C40FEB5044600266846DD +:40B580000680868006810125A078FBF7DDFD0746A078FFF7C5FC0743A078FFF787FD0743A07802AB01AA694600F020FA3146264660363177002F55D12079092852D06846F3 +:40B5C000808800284ED0204602F03AF9002849D0684681882046C030002909D00168CA79022A05D0CA7AD30902D05206520ECA720068817A002905D0C17AC90902D1217EAF +:40B60000890600D50025214640318A79012A06D04979022903D0BC21095D02290CD1718BC08BFFF7DBFB69468988C91C884202D30D49884200D9002568468088002811D066 +:40B64000012D0FD10421204600F0B0FD01203077684681880422204600F0CAFD208B082188432083FEBD0000FF7F0000F8B5044680782521C001C9024018394940184069BB +:40B6800086B2F7F74BF9FFF7C3FD002864D0207E000761D420466030017F01295CD146210B5D00252146C0312A46012B07D1438B0868C08B834251D0401C83424ED0294888 +:40B6C00003689BB200938368FFF7CEFB5F06264B03D5009D2D1AED18ADB20F687988814201D2401A05E0814209D93F888F4206D2081AC01882B21D48824200D900221B4848 +:40B70000854229D8D00700D0521C50083146F7F7FFF907464800301A4004010C0A2901D9012300E00223581C704340000A30A84212D81021204600F039FDF81881B210226A +:40B74000204600F055FD204600F08EFC00F01EFC208B082108432083F7F7CAF8F8BD000000103C4000503D4000000100FF7F0000FF2806D0034B196A012289B28240914376 +:40B7800019627047801F3C4030B513490A680146C0310B689A80037902464032022B13D00B6800241B88958B6D00EB181B190C689BB223809279012A05D160304088096847 +:40B7C00000011818888330BD044B5B6A93830B6803249B88E7E7000080503D4040123C40F0B585B0002704460546C03403972068252201880291A978D202C90189182E466D +:40B8000040360191B17901297ED044494A68828088682168802208822068022781880291C17A1143C17203F007FDF28B6979FCF731FC0146284660300090C18203F0FCFCF0 +:40B84000B18BC9198AB26979FCF724FCB179344A012921685FD00B8AD31A1B18D833CB8103992F4B0918F07E5843081821688881B08B410002980818C01987B22068591EAA +:40B88000078020680290C089884210D9491CF7F73FF90299381A088027682149F889F7F737F9F9812068022901D20221C181B07901282BD1009920684988028809015118B1 +:40B8C000818300980321C08A09030005000D8843A035297D8907C90F09030143687D8007C00F42030A430F4901984018C26221688989C16320680B49028A0198403140185F +:40B9000042602168C98900E002E0C16005B0F0BD8089039087E7CB891B18A0E780503D407102000000103C40F8B52F4DAA6AEB6B92B29CB28378E606F60EB34214D12A4E7F +:40B94000034689074036C03300290EDA002160300177186801884180F06819680880A00602D41968A009C881F8BD1968CC8B641CCC83696A1C68A183E96A1C685704A18007 +:40B9800011061C68890FE17191041C68890EA1711968FF0FCC7AD20B3C43CC7219688A728321095C002910D11968002A07D10A884A80F1681A681180696B1A68D181296BBA +:40B9C0001A681182A96B1A68918119688A7A002A06D000224A830022042100F0BFFCF8BD4A8B521CF6E7000000503D4010B52524C001E4020019044C001944690C80816928 +:40BA00001180C069188010BD00103C402522C001D2028018024A8018406908807047000000103C403EB5044600F06EFD684606F0D5F9684600780022022836D26846817864 +:40BA40001B4803781B48994201D3002103E0D025036A6943591821604078430706D4800707D514482030007E800702D060318A8015E00A4660326846D388808883420DD9E2 +:40BA800083235B5C002B07D1C0310968C9890C2902D8012800D9401E908000E093800298002801D000F0F8FC3EBD22603EBD0000CC1E00085C21000802488068C006C00ED4 +:40BAC0007047000000503D4008B5034680786946FFF79CFFFFF7C8F9C0331968801C0988401A01210904401880B24910884207D2694609884900F7F70BF8401CC0B208BD10 +:40BB0000012008BD2522C001D2028018024A8018806908807047000000103C40F8B5054604464034A0792F462E466037C03601282AD13068798BC08BFFF750F92D49884244 +:40BB400005D2032803D24021284600F01DFBA079012819D13168788BC98B884214D18320405D0028284613D0FFF70EFE2021284600F00AFB284600F03DF9284600F0CEFA33 +:40BB8000E08A82210843E082607902280ED019E0FFF726FE4021284600F0F6FAF6F7D8FE0328E7D1E08BFAF7C3F9E3E73168788BC98B884206D1284600F006F9E08A042123 +:40BBC0000843E082BC20405D022811D13168788BC98B88420CD108480068416A284688471021284600F0D0FA208B012108432083F8BD0000FFFF000008020008F3B506460F +:40BC00000446C036306881B0818B0088FFF7E6F821792546204F4035032919D91921C902884215D9FFF720F93168898BFFF748F9717900290CD1002820D081004018C20831 +:40BC40002046A178154B7E30F9F75AFF012070718320005D00281DD1207903281AD90E4B0299703330685943AF238289DB00C91A8A420FD9A979012909D103E0E88A38430F +:40BC8000E882E3E76034C08B618B884202D0E88A3843E882FEBD000001020000C19B0010F8B582782523D201DB02D51876220446125AC03420684A43C1898918C1812068D0 +:40BCC00081898918818126682721F0890901884211D94F1C3946F6F71BFF3188081A308026683946F089F6F713FFF1812068022901D20221C1812068024980896918C863A4 +:40BD0000F8BD000000103C402521C001C90242180D4800211018016041608160C160016141618161C161016241628162C162016341638163C16304484030101801604160EA +:40BD40008160C1607047000000103C40F8B50446FFF712F88320A178005D06F039F91649086882B28868254680B246060023C035002E1CDAC006A478C00EA04217D1FFF7BE +:40BD800073F8101A01221204801880B201280ED90124CC60C8688007FCD56846FFF742FE0098002801D000F015F92C7100E02B71FEF7FEFFF8BD000000503D4010B500F04D +:40BDC000A3FB06F06DF910BD81782522C901D20289186030064A038A89180B62428A4A628A6A808A92B2120A120210438862704700103C4081782522C901D20289185E2219 +:40BE0000135A074A89184B610246603213888B615288CA61C0300068808B48637047000000103C4081782522C901D20289180A4A8918CA6A032392B21B039A43A030837D63 +:40BE4000C07D9B07DB0F1B038007C00F134340031843C8627047000000103C40F0B581782522C901D2028B1801466031244A0C899A1814604C8954608C89946004464034AD +:40BE8000E67ECD8936023543D560E48B54610C8894614C88D4610C8A14624C8A54620D7E46792D028C8A760335432543ACB294628324134E245C40360025C030002C0CD03E +:40BEC000D56200689B19808818600E4B0A2018628888106355639563F0BDCC8A03272405240D3F03BC43D4620468A489D4630468278A9C1967600768FF89E760E1E70000D2 +:40BF000000103C4000543D4030B581782522C901D2028C181C4962181368014660310B8153684B8193688B81D368DDB2CD811D0A03464033DD7615699D835569DD839369EB +:40BF40009BB20B80D5694D80156A0D82556A4D82926A92B2D5B28D82D504ED0E520B0D764271002B01D000220A770749403161180A68C03003689A804A6803681A82C9685B +:40BF80000068C18130BD000000103C4008B510490122086883B2886840060FD5FEF764FF181A01231B04C01880B201280ED90120C860C8688007FCD5002A07D06846FFF709 +:40BFC00031FD0098002801D000F004F808BD000000503D4070B581782522C901D2028B18144A9168490604D50121D160D1688907FCD50146C0310C46096809881160642170 +:40C000000D4D095A5B191963014680310B46C97800290CD000215160DB7881785B014024234319439160807806F0A2F870BD2168C989F0E700503D4000103C40044A1168AC +:40C04000FF23F13389B29943000101431160704740503D4003490869012280B21203104308617047001E3C40FEB5044680786946254648708035E8780870062027468870D6 +:40C08000C03738680088088102A9684606F08CF8002838D10520694688701E480126807A800603D5286B017E807A01E01B210846EA78002A00D102262246A032137D012B31 +:40C0C00022D089003C313B68527D9C890919012A1DD080003C30FF302D300F4F08183946F6F716FD801985B26846858060003946F6F70EFD401CA84201D96946888001A937 +:40C10000684606F051F8FEBDC9007031DBE7C0007030E0E7AC1E0008710200001CB581786A4651708321095C1170042191704030C08B908001A9684606F036F81CBD10B5EF +:40C1400086B081786C466175014680310A46C97821750821A17500212181A1725E231B5AA3810223E381D278A274012222700191C02109580988218280786075214605A833 +:40C1800006F012F806B010BD10B5807805F0F8FF10BD0000FF2806D0034B196A012282400A4390B218627047801F3C40C030026810290ED09179D18201680A884A800168FC +:40C1C000CA8B0A830168CA894A820068818981827047518AD18101688A8A8A8101684A880A8001688A7D8A710068018BC1837047F7B5064680780D46252288B0C101D2027D +:40C200008918039106AB05AA01A9FFF7EFFB3446C034374620686037798BC08BFEF7DEFD03462068798BC08B401980B2FEF7D6FD01460A98082828D1304640308279012A25 +:40C2400023D1444A914220D993421ED2002B1CD02268B97E927F891AC9B20091C08B029068466A1A8088049050430299F6F73AFD00994018401C85B202984200681A4243AF +:40C28000049840004843101803E0684680884000684321680A8810180880206800908179387E684308182521F6F732FC009881710A98082809D02068C18B4919C183803647 +:40C2C000F078254E00280DD033E03079032803D12068418B491941832A460821304600F03DF8ECE72168F88ACA8968431218CA8121688A891018888125682721E889090187 +:40C30000884211D94F1C3946F6F702FC2988081A288025683946E889F6F7FAFBE9812068022901D20221C1812068818903988019C1632068C17980798A07D20FC9079200CC +:40C34000090F1143000208430399891988630BB0F0BD0000FF7F000000103C40FEB50F460446002069460880888016460881A07801AB02AAFFF73AFB254620460123C0354E +:40C3800040302179042F02D003294AD053E0092902D0032908D030E0217EC9062DD4C18A01221943920226E029688A7A012A1AD18A8B002A10D1A2782526D201F602961960 +:40C3C000264A926862273F5B3F01BA1892B28A832249C03971184A63C18A02221143C1822179032909D12968498B062905D3C18AFF22194301321143C1822046FFF78EFB2A +:40C40000684601882046FFF7F9FB8320005D002806D168460089002802D02046FFF7ACF8FEBD2968498B062905D3C18AFF22194301321143C182002708E02868C18B491C3C +:40C44000C1832046FFF76AFB7F1CBFB2B742F4D3684601882046FFF7D1FBFEBDC0103C40F1B50B4F0025386A84B20A48406986B202E0A01984B20125012221460098FEF747 +:40C48000B1FE0128F5D0002D00D03C62F8BD000040123C40C0133C40F8B5002405F0F0FC0546174E174F27E0E80722D03078A04201D8002003E0D020396A60430818FFF710 +:40C4C00003FB01463078A04201D8002003E0D0203A6A604310180822FFF78AFE3078A04201D8002003E0D020396A60430818FFF7BBFD6D08641CE4B2002DD5D1F8BD00000D +:40C50000CC1E00085C210008FEB5684605F0E6FC68460078002830D00024184D184E29E0C00722D02878A04201D8002003E0D020316A60430818FFF7C7FA01462878A04221 +:40C5400001D8002003E0D020326A604310180822FFF74EFE2878A04201D8002003E0D020316A60430818FFF77FFD01984008641CE4B2019001980028D2D1FEBDCC1E000865 +:40C580005C21000810B50C4600F0C8FF06494018016889B20A091201FF21224301310A43C9008A43026010BD00103C4070B526490446097800204907490F40250346012963 +:40C5C0000FD002290DD0032901D0042924D100201E4E0146012C24D0032C1ED0052C25D122E000211A4E0A46012C08D0032C02D0052C09D106E0B56002210A2204E00421BE +:40C600000C2201E004210D223461306AC0B204460C42FAD03262336170BDB56202200A2104E004200C2101E004200D21F462726B14460442FBD07163706B0821884370635F +:40C64000F362D0B270BD0000F021000800F13D4080143C40F8B505460D48164600780F46A84201D8002404E00A48016AD02068430C187F20005DF9F7A7FABA1B0A20424351 +:40C680002046054B29467F30F9F73AFAF8BD0000CC1E00085C210008B5A00010044A106303488030816102494B2080390860704780103C40024610B50B460F20002180018A +:40C6C000F8F796FF10BD000013B50C46002269460F20F9F70FF869460978E0030843034980B208630249472008601CBD40113C4000103C407FB50E4604461D46002202A943 +:40C700000E20F8F7F7FF1048F10100780F4A4007400F03280BD0042809D0A00208436946097A084380B21063A009906307E0E80301436846007A014388B21063946304490C +:40C74000462008607FBD0000F021000840113C4000103C40017E012901D9012101764279C9B253000B430179CA001A4310210A4303498A6002880A604088486070470000DA +:40C7800040103C4006490978814201D8002004E00449D022096A50430818603043837047CC1E00085C2100080349884200D908460249486270470000FF0F000040113C4090 +:40C7C0000148806B80B27047C0103C402521C001C902401807494118086A1070000A5070486A9070000AD070886AC0B21071000A5071704700103C4070B50E4D14462A78D6 +:40C800005207520F012A09D0022A07D0032A01D0042A02D1224600F00FF870BD02460B46E8880021F8F7CCFE012CF6D1FEF774FA70BD0000F0210008F8B594461B4F8207B2 +:40C8400005D01A4F0023103F8E08B60015E08C08002303E09D007E5946515B1CA342F9D3A3000CE0DA191469C454240AC5186C70240A220AAC70EA701B1D9E42F2D88A07B9 +:40C880000DD00A4A103A9A18146900228907890F03E09D184455240A521C9142F9D86046012801D1FEF738FAF8BD000050F13D4010B5114909784907490F01290FD002295C +:40C8C0000DD0032901D0042908D10C49496A0170090A4170090A8170090AC17010BD084A11680170090A417051688170090AC170FEF712FA10BD0000F021000800F13D40C3 +:40C9000080143C400148806B80B27047C0103C4010B50A49F1240A681421414393681331595C24018B001B19102906D251682C225043085A02495918086010BDD401000873 +:40C9400000103C400121814010B589B200227C2000F082FD10BD0000FEB5FF210120FDF7F1FF3F210220FDF7EDFF1F210420FDF7E9FFFF210820FDF7E5FF3020FEF704F873 +:40C980007D48802101607D4C20784007400F032801D0042803D10BF03BFD0BF01FFC7748774E00784007400F022806D0032804D0042802D0012807D00BE00321316003281A +:40C9C00005D0042803D004E00020306001E00BF02FFC002211460320F8F78CFE69486A49028D4A61428D8A61828DCA610546624F00242035803709E03C636248818E62480A +:40CA000001632046FEF7B4FB641CE4B22878A042F2D85D480621C03881635A4C5A48218F816320460C30029000F0B0F9062268460299F7F75EFD69464879C02108436946D0 +:40CA40004871684600F0DAF900F0B0F8FFF702FB4A4800784007400F032829D0042827D0E08FB8634748444940304088C0314860E08D0121C903084343490862434901205A +:40CA8000086141498031C8683F2280B212029043072212021043C8603F20FDF781FF374C20784007400F022804D0012802D008E04820D6E7FEF748F9354907208861FEF72D +:40CAC0002BF9E020FEF794F8E820FEF791F8F020FEF78EF80020FBF7D3FA2C490020486110228A618915F96227494031C86022485B21016020784007400F032801D00428A7 +:40CB000001D10BF095FB20784007400F022806D0032804D0042802D001280AD00BE01D4830601D490869012280B252031043086101E01A4830601448C038416B0122114303 +:40CB400089B24163816B114389B2816314494015086014482978006805F0FEF906F00CFB00231846FFF7D0F85B1CDBB2042BF8D30D4900204870FEBD00103C40F021000844 +:40CB8000001F3C40AC1E0008C0113C40001A3C4080143C4003200000001E3C40E023000040503D40D00100089C21000804480021C1638163024974204039086070470000BE +:40CBC00040103C4070B51E4614460D4600F0A6FC0C49411808680122D20280B2012E09D0904300090001FF22284301329043002C04D005E01043044A1040F2E710221043AF +:40CC0000086070BD00103C40FFF90000F3B5254A84B0926900924A780B78120213430393CA788B78120213434A790979FF20120211438C461C499E46CA6B92B20292896B27 +:40CC4000742289B20191184940390A60174900220F7F24E00121144B9140009C403BE3181C6889B2A5B21C681B68A4B2039E9BB26E407546654064462E435C4026430CD129 +:40CC8000029B194209D00199D140CB070499DB0F8B4202D1104606B0F0BD521CD2B29742D8D8F8E7F021000840103C40CC1E000830B50A49FF20C96B094A8CB200210125B2 +:40CCC000137F05E02A468A40224204D0491CC9B28B42F7D830BD084630BD000040103C40CC1E000810B50446E020FDF781FF20782246401CC3B20021E020F8F711FC10BDAB +:40CD000042790021012A02D901214171090342790A430179042914D049001143827B032A01D8D2001143427B52010A43817909021143012252031143054A91610088D0615C +:40CD4000704711460122920211430222E5E7000000103C4000B50120FDF716FE01494120086000BD00103C4000B50120FDF718FE01494020086000BD00103C40024A1063EA +:40CD800001488030C160704780103C404178027809020A4306490A60C2788378120213434B604279007912021043886070470000C0113C404278130202781A4301290CD0D5 +:40CDC0000C498A62C278837812021343CB6242790079120210430863704707490A63C2788378120213434B6342790079120210438863704740103C4000123C404178027895 +:40CE000009020A4306498A61C278837812021343CB61427900791202104308627047000040103C404178027809020A4306494A60C2788378120213438B60427900791202B7 +:40CE40001043C86070470000001F3C40F0B50021FF2501350E4E0F4C15E0F1238A001B01D21893191A6892B2D7070AD0520852001A60884201D12A4300E0AA4301273A43AA +:40CE80001A60491CC9B2E27A8A42E6D8F0BD000000103C407C21000810B500222021302000F0DAFA05494320086001F009FDC007FBD10220FDF768FD10BD000000103C40A1 +:40CEC00030B591B0054640216846FDF7A4FF0A4C0849A1630220FDF763FD6A782021302000F0BAFA4220206001F0EAFCC007FBD011B030BDFFFF000000103C40017942792B +:40CF0000490011438279D2000A43FF2101310A4303490A6302888A624088C8627047000000103C4010B50446E820FDF761FE20782246401CC3B20021E820F8F7F1FA10BD2C +:40CF40004178027809020A430749CA63C17882780902054B0A4340331A60417900790902084358607047000000123C40024A1063014880304160704780103C40094810B529 +:40CF800081420DD8C8000521F5F7C2FD064989680818064980B2486003497220C039086010BD0000409C0000C0103C40001A3C4010B5074948200860064C206B4006FCD405 +:40CFC000002211461020F8F795FB606B80B210BD00103C4040113C400349732008600349042048637047000000103C4000113C4010B500F093FA0121490200F04BF910BD04 +:40D0000010B500F08BFA0121890200F043F910BDF0B515460F4604461E46FF2A04D000222946184600F0D6F86078237800020343E078A17800020143607922790002024336 +:40D040000C207043C419084827183B60241D23181960241D20180260FF2D04D001222946304600F0B7F8F0BD00103C40012808D8044A916901235B0299434002084380B2AD +:40D080009061704700103C40084A106348780B78000203439360C8788B7800020343D36048790979000201431161704780103C40F8B51C4615460E46074600F041FAA9009E +:40D0C000044A2143801801600349B0004018C455F8BD000000103C40D92100080149C86070470000C0103C40044A916B8905890D8002084380B290637047000080103C403D +:40D1000010B50E490B68142141439A681331515CF122890012018918094A89180A6892B2D40709D0520852000A605A682C235843105A01221043086010BD0000D401000852 +:40D1400000103C4038B5174B1B78834201D8002304E0154BD0241B6A60431B182024012906D0022904D0002A05D0002903D005E0188B204301E0188BA0431883187E8006A6 +:40D180000ED58320C05C00280AD198786946FEF7B9FC68460088002802D01846FEF766FA38BD0000CC1E00085C21000810B50C4600F0B4F90649401801688AB240218A43E4 +:40D1C000A10111430122D2029143016010BD000000103C40F12380001B01C018054BC3181868002A80B201D0084300E0884318607047000000103C4070470000F0B5174BE5 +:40D200008C07C318002C03D000209508AD0014E09408002003E01D6886008D51401CA042F9D3A0000BE01C680C54240A0E187470240AB470240AF470001D8542F3D89407BC +:40D240000AD01C6800239207920F03E0C5184C55240A5B1C9A42F9D8F0BD000000103C40134610B50A4A12785207520F012A09D0022A07D0032A01D0042A02D11A46FFF7F5 +:40D28000BDFF10BD0A460021F8F72CF910BD0000F0210008034A8018026892B20A4302607047000000103C40F0B5264BC518880703D000239708BF001DE09408002003E083 +:40D2C0008300CE58EE50401CA042F9D3A30014E0C818401C044626783046667836023043A678E4783604304324062043CC5C00022043E8501B1D9F42EAD8900721D092070E +:40D300000020920F012A04D0022A04D0032A17D107E0C85C14E0C81841780278080210430EE0C81801460A7810464A78120210438A78C97812041043090608430002000A81 +:40D34000E850F0BD00103C40F0B5424C00198C0704D000249D08AD00AC461DE09D08002403E0A6008F598751641CAC42F9D3AC0014E00D196D1C2E4637783D4677783F02B3 +:40D380003D43B778F6783F043D43360635430E5D2D0235430551241DA445EAD89B079B0F551C002B22D0012B31D0022B40D0032B1BD112780B5D1206134309198A784978E2 +:40D3C000120409020A43134303512B78EA7819466B7812061B021943AB781B04194311430902090A0019401C0160F0BD2B462D78127829465D782D0229439D78DB782D0492 +:40D4000029431B061943090211430151F0BD1678D578334656782D06360233439678095D360433432B431B020B430351D178D9E755780B5D2D062B431578091949782D04D1 +:40D4400009020D432B430351D178927809021143C8E7000000103C4070B5094BC5182868002384B2080003D104E040085B1C9BB2C607FAD08C439A40224390B2286070BDFB +:40D4800000103C40134610B50A4A12785207520F012A09D0022A07D0032A01D0042A02D11A46FFF701FF10BD0A460021F8F7A0F810BD0000F021000838B514460C4A1278FC +:40D4C0005207520F012A0BD0022A09D0032A01D0042A04D11B1F9BB22246FFF735FF38BD00930A4623460021F8F79CF838BD0000F0210008034A80008018405C8007800F43 +:40D5000070470000D921000800B500F00DF802494018006880B200BD00103C40014900014018704708420100014900014018704704420100A121000149024018704700009F +:40D54000034A928A424350180249800040187047F021000800410100054B02469B8AFF208B4203D9880003494018805C70470000F0210008C521000800B5FFF7DBFF024905 +:40D580004018006880B200BD00103C40F0B5304902460B680020002B14D10A6052070D26520F0024B601012A0DD0092503276D02FF020423022A1BD0032A2FD0042A2DD090 +:40D5C00012200C60F0BD112292018A80CA80032252028A600122D202CA6040220A8205224A828A82CC610C624C628E618C62F0BD8D80CD8001225203CF608A6012110A82E8 +:40D600004B828B82D2008E61CA61832252010A62432292014A628922520116E08D80CD800522D202CF608A60FF2201320A824B8229228B82D2028A61064ACA61054AC0323A +:40D640000A62054A4A62044AC0328A62F0BD0000F0210008C0480100404A010010B503460C460846FFF788FF02462046FFF74CFF012199400A4001400A4301D0002010BD12 +:40D68000012010BD0A4600B501461046FFF764FF00BD000010B50F4801680F480818846AFF2102310C4202D0F8F750F80DE0406B400F022801D1A00607D5FAF72BF9074867 +:40D6C0000069012180B201F071FA20460AF0E0FA10BD00006801000840F03D4000103C40F8B50446002000900E461546A178684609F07EFD002801D00720F8BD2B46324611 +:40D700002046009900F0A8FEF8BD38B50546002000900C46A978684609F06AFD002804D1009928464C7000F0F2FE38BDF8B5044600206A46107005460846FBF721FB0600AD +:40D7400004D0012806D0162E3AD10DE001236A46002102E001236A4619462046FCF7DBFB0546012804D02BE001236A461621F4E78320005D012811D1CD20005DC0070DD02F +:40D7800068460078C1090DD1C00701D0232200E02A2231462046FFF7A3FF11E068460078C0090DD068460078C10720464030002901D0232100E02A2181762046FBF75CFB8D +:40D7C0002846F8BD10B582790A4201D0FAF774FA10BD10B5044680780021FFF7CFFA01212046FDF761F810BD8030C368002B0AD00B60817A11700169C160C17A81720021D3 +:40D80000016108467047014870470000FFFF00008030C368002B04D00369002B04D004487047C160827201E00161C27200207047FFFF000000218030C160016170470000CF +:40D840008030C068002801D00020704700487047FFFF000070B505468035E8680024002806D0FBF78DFA002801D0012800D101242869002806D0FBF783FA002801D00128BB +:40D8800000D10124204670BD70B50446C0790E461546C1090AD04006400EE07101F0B6FC067021894180856006F0F1FA70BD70B50446C0790D46810601D43A2D13D13A2D7F +:40D8C00002D0DF210840E07101F0A0FC0570218941805E21095B818060342188C1806188018106F0CBF970BD38B54621095C04468034002910D1A16A00290DD18178684622 +:40D9000009F088FC002807D100980021A062C181A06A4185A06A4180A06A38BD01480078704700003C22000810B50446FCF798FA01280AD10648A178026AD020484384305B +:40D94000105CF9F7C5FF012801D000F0F3FC10BD5C21000870B50C460546F9F759FC012838D02879032803D0042801D0072830D1E079A67900020643A8783146FDF714FCFA +:40D9800001282DD0284660304683A17809020182627811430182217909024182E27811434182617981823246611C284600F09DFB02212846FAF7C2FD2846C030417B822282 +:40D9C00011434173287E0221C207D20FA878FFF7B9FB70BD01222421284600F04AFD70BD28215A2041552846FBF746FA70BD704770B50C460546FAF7E9FC00284FD120217D +:40DA00002846FAF759F9F4F789FF284661784030C176E17809028183A278114381836179C38B0A022179114320228B4203D0EB791343EB71C183E1792E460B02A179603611 +:40DA4000194333888B4203D0EB791343EB713180617A0B02217A1943738843828B4203D0EB791343EB717180C18B70888000F5F74FF8401E318880B2814200D93080012134 +:40DA80002846FAF75EFDC035687B822108436873E07AA17A000201437183F4F729FF70BD70470000F8B50D4606460027F9F7B0FB012845D0264CA07AC00707D04420805DAE +:40DAC000002806D0102803D01F212CE01A212AE001273046FBF75AFB002823D0344680340822691CE06AF6F704FDE06A697A20300172A97A4172E06A2946183008220B314A +:40DB0000F6F7F7FC29463046042213313830F6F7F0FC39463046FBF72DF8002810D1002F0FD012E007210322304600F0A2FC628A08213046FAF7A0F811213046FAF704FD61 +:40DB4000F8BD06213046FAF710FD01202070F8BDAC1E0008704770B50446403000790D46022813D126468036F06A08222030691CF6F7BFFC29462046042209313C30F6F7FC +:40DB8000B8FC2046FAF7A2FF0120307070BD10B5FBF732F810BD70B50E4605462021FAF78BF82C468034A06A002804D0A97809F0B1FB0020A06231462846FFF778FE00211E +:40DBC0002846FAF7BEFC2846FAF73BFD002070BD38B504460020009020790D46032803D0042801D007281CD12046F9F711FB012818D0A178684609F0FBFA002811D10C48B8 +:40DC00006A78807A00991040F5221040A075E07E08221043E076204600F05CFB2046FAF710FD38BD08222421204600F022FC38BDAC1E00087047000070B50D460446022126 +:40DC4000FAF73AF82046F9F7E3FA012805D009222421204600F00DFC70BD0C486978807A6A1C0840F5210840A075E07E08210843E076E079EF210840E07100212046FFF73D +:40DC800003FE2046FAF7DDFC70BD0000AC1E000870470000F3B581B004460298FBF770F805462046FCF7D1F800287DD0192D04D32046029900F0ABF976E0264640363079F1 +:40DCC000002700900300FCF70FFE0E1C1C1C08081C1C1C0808080808081C0298354A01780020135C8B4201D1012702E0401C0728F7D38320005D002801D1072901D0002F0F +:40DD000003D00098022816D02EE0A078FFF770F9002301223D212046FAF700FE3D20B0762046FFF756FDA178029809F0C9FA2046FBF7FEF8FEBDFFF7F1FD002814D1042D1E +:40DD400012D00D2D10D0112D0ED0152D0CD0072D0AD0092D08D0202217480299F6F7C9FB012000F003FC1FE020460299FFF7DEFC012819D0A8000F4D029908352A582046AE +:40DD80009047A178029809F09BFAFFF7C7FD0228D0D109480849007880002A5820469047002000F0E3FBFEBDA178029809F088FAFEBD0000D84600101C22000870B50D46EF +:40DDC00011490978814201D8002404E00F49D022096A50430C18002C15D0204600218030C1718079032802D12046FCF7F3FB2046FFF79AFD192D04D20549A80009582046AC +:40DE00008847FCF73DFA70BDCC1E00085C2100084447001010B50446403000790E2805D12046FAF72FFF01208034207010BD10B50446F9F7EDF9012802D1002040342070EA +:40DE400010BD10B5044640300179062905D00F2902D12046FAF73BFF10BD2046FAF748FE01208034207010BD70B50446054640342079072805D12846FBF7DEFF2846FAF738 +:40DE800031FE20790F2801D10020607070BD000038B5044600220E4800920D46807AF5210840C0060FD52046FBF7E0FF01280AD0A178684609F09CF9002803D12046009954 +:40DEC00000F0B4FA38BD2946204600F0A0F838BDAC1E000810B504461021F9F7EDFE2046FAF7E6FB10BD000070B5054610480C46807A400704D409782846FFF706FC70BD04 +:40DF00006078032803D1A1782846FAF75DFD6078122803D110212846F9F7CEFE60781628EDD10448A1780068C2682846904770BDAC1E00080802000810B5FAF7D1FE10BD84 +:40DF400010B54978FAF740FD10BD10B5FAF7C8FE10BD10B54421095C032901D1FAF7E8FD10BD012140304170704710B54421095C042904D00C2901D1FAF7C8FE10BDFAF7A1 +:40DF8000F5FD10BD10B50446F9F742F9014620464030012900D1417000790D2802D12046FAF7AFFE10BD70B502790D460446052A03D0062A01D0082A01D1FAF717FD687824 +:40DFC0005A21085509212046FAF7CFFAFCF7D4FE80212046FEF7D8F8FCF7EAFEA078FFF70FF82046FCF746FC70BD10B50446FF21F9F762FE16215A2001552046FAF798FF42 +:40E00000A078FEF7F5FF2046FCF734FC10BD70B50C460546FBF724FF002802D02078E87570BD21782846FFF770FB70BD70B5054648780C46032802D12846FAF7E3FC60786B +:40E04000122806D110212846F9F736FE2846FAF72FFB0748214600684268284690476078162804D10348006881682846884770BDFC01000808020008704770B50D460446B5 +:40E080000421F9F719FE6878A076E8780002E081A9780843E081687900022082297908432082E07E04210843E076800704D4204600F03AFA072815D0E079410612D5BF2112 +:40E0C0000840E07101F0A2F80021017021894180E1898180A17E4170218AC18005F004FFFCF7CEF870BD7047704770B50446C07815460A4600280AD00020E070C1B2A0783D +:40E10000FDF78EF8A0782946FEF7C8FA70BD0120F3E70000F8B5064601200C46087005221949601CF6F7E5F9B078FCF783FE0546B0786946FDF7E6FC684600880A214843CB +:40E14000114942191039887B002802D0401E4300C018101835460C30603568834A7C0B7C12021A432A82CA7C8B7C12021A436A82097DA982A071000AE07108223146204694 +:40E18000FCF7BCFAF8BD00006C2100087CB505468030866A0C46A878FCF74CFE014628465C30009001AB3246284600F031FAA878FCF740FE69468988FCF710FE69462846F4 +:40E1C0008988603041830021217029464031CA7E62700A7FA2708A8B120AE2708A7F2271C98B0C22090A61710178A1710188090AE1718178217240886946000A6072888885 +:40E20000A072000AE07229462046FCF777FA7CBD70B5054603200C4608702E4680360822601CF16AF6F765F9F06A08222030017A6172407AA072F16A204618310B30F6F70B +:40E2400058F929462046042238311330F6F751F9172229462046FCF751FA002070BD70B50546042008700C46AC20415908222031601CF6F73EF92946204604223C31093056 +:40E28000F6F737F90D2229462046FCF737FA002070BD000070B505460C46C07910210843E8710820207002460021601CF6F72AF90748F522817A11406170C07A0922C007A0 +:40E2C000C00FA07029462046FCF718FA002070BDAC1E000870B5054609200C46087008220021601CF6F70EF9A87D607005480922C07A2946C007C00FA0702046FCF7FEF91C +:40E30000002070BDAC1E00080B4610B501460A20187001221846FCF7F1F9002010BD0B4610B501460B20187001221846FCF7E6F9002010BDFEB50020694608720546334F4B +:40E3400060E03348016AD02068430E183046FFF777FA002854D18720805D002850D101AA69463046FFF740FA002849D100980478002C09D0012C16D00C2C23D0092C21D000 +:40E3800069460A79314629E0012302AA00213046FBF7C1FD012804D030460099FFF7F6FE2EE00C221FE0012302AA19463046FBF7B2FD012804D030460099FFF7ABFE1FE073 +:40E3C000082210E0012302AA21463046FBF75CFD00286846027906D131460098FCF78EF9022C05D00CE031460098FAF7E5F907E0B0780121FEF7DAFE09213046FAF7B5F851 +:40E400006D1CEDB23878A8429BD8FEBDCC1E00085C21000810B50B46122119708178D977014601221846FCF769F910BD10B50B46132119708178D9770649896AC90603D16F +:40E44000018B402211430183014601221846FCF755F910BD00113C4010B50C461121217062700146A37003222046FCF747F9002010BD38B50446002000900D46A1786846C1 +:40E4800008F0B6FE002801D0072038BD00980D210170457002222146FCF730F9002038BD0B4610B501460520187001221846FCF725F9002010BD0B4610B50146062018705F +:40E4C00001221846FCF71AF9002010BD38B5044600200090A178684608F08AFE002801D01F2038BD009D022028705A20005D6870A078E877208B1021084320832046FFF7AA +:40E5000068F9022221462846FCF7F8F838BD10B50B46072119708178D977014602221846FCF7ECF8002010BDF8B50546002000900D4EA9783488684608F05AFE002801D035 +:40E540000720F8BD00980C210170717941708470210AC170F2880271110A417106222946FCF7CCF80020F8BDAC1E0008094A1178002906D0012909D0022908D1002807D00E +:40E5800001E0012804D00021002900D0107070470121F9E73C22000800B500F016F800BD704770B50546FFF79FF9044602884188A87804F085FCA084E0886082A088208235 +:40E5C0006088E0812088A08170BD4018400870470246603000885E21895A401C4843C10800D101214008528A00E0401A8242FCD9704710B56021095A80780A01511A10311A +:40E600008CB2FCF717FC2146FCF756FA10BD0000FFB581B0054604464035288A69460A9F08801E46A078FDF76DFA694609880A20491C41431048807B002802D0401E420087 +:40E640008018081881B20298FCF736FA3080A07804F024FC06468320005D012804D1E98BA078042204F0C2F9A078314604F05CFD388005B0F0BD00005C210008F8B51546E8 +:40E680000E46074600F00EFA0446012804D02A463146384600F0B6F92046F8BD014600B50020890701D500F00BF900BD014600B50020890701D500F003F900BDF0B593B015 +:40E6C0000020FF210391059007901290012612A92F2005F008FD002804D000F097FD0446002600E0129CFEF76BF881040507890E40060891C00F891F2D0F06900491202949 +:40E7000031D2062D2FD800F0DBF8C0072BD03E2020700220A0700120E07003210420624F062D2DD0022D2ED0042D2ED025715E48417949084900417106986071A01D06216C +:40E74000FCF769FBFCF79CFC070006D0574A611D1268A01D126A904703900498012DC0B2029020D044E0002E02D0204605F0C2FC00F04CFD402102A8FCF74DFB13B0F0BDB4 +:40E7800002202071D3E72171D1E720717879C007CDD0002E02D0204605F0ACFC002600F035FD0446C3E70398FF280BD040482C220068416803985043095A4120884301D16A +:40E7C000012007903B48407E012804D10799002901D1012F02D0002F06D007E00120059020730D270B2006E00128F7D00020029020730D270220A0700898062824D0049812 +:40E800002746C1B20D373846FCF705FB0598012817D12948006B03A9C007C00FFCF730FBA07C8009012806D13946062203A8F5F751FE002805D10020203FF8770290022087 +:40E84000A07002980D30C7B2FEF75CF8694688806A4601A90620F6F74DFF69460878E0557F1E16486770407801280BD12A46A01D069900F017F9012811D02A46A01D0699EA +:40E8800000F0C0F8002E04D02046059905F018FC74E7054801224179114341716EE7204605F028FC6AE700005C210008EC010008D4010008A021000800103C407D2200089E +:40E8C0000248806B0004000E7047000000103C4010B50446000701D5FFF7F0FEE00601D5FFF7ECFE0248006881692046884710BDEC01000810B502460178FFF7E1FF814270 +:40E9000001D10C2010BD0D485378002443705470002908D000F06EF81046FEF7D1FA0420F9F74AF907E01046FEF7B6FA0520F9F743F903480476002010BD00007D22000801 +:40E940007C210008F8B50446FFF7BAFF002801D00C20F8BD6079164DFD2702260128E8781DD03840E87013480068416820468847A0790128A87814D03840A8702046FEF7D2 +:40E98000BDFA0B48218862882030914203D1017E0122114301762179012904D006E03043E0E73043E9E7017E314301760020F8BD5C210008EC01000838B5002001460090BE +:40E9C000684608F0FFFB002801D01F2038BD009C002161712171A1711021218020466180FEF78CFA204608F077FC00F003F8002038BD000002480021017007218170704706 +:40EA00007D220008F7B50C2082B0254D0F46002400902878E040C0072DD02148E10040380E18062230460299F5F754FD00280AD1B079B84207D1F079002801D0062802D167 +:40EA4000049804280BD02878E040C00713D0641CE4B2082CDDD300980C2803D00BE00420F07119E0A878401CC0B2A870082801D10020A870C4B20A48E10040380E180622D8 +:40EA800030460299F5F735FDB7710498F07128780121A14008432870002005B0F0BD00007D220008F7B5164E00243546403529780120A040014217D0E0008719B979019818 +:40EAC000814211D1062238460099F5F703FD00280AD1F879022810D004280ED001280CD0002807D0062805D0641CE4B2082CDED30020FEBD02980428FAD00120FEBD000075 +:40EB00003D22000801484078704700007D22000870B5064614460D46500702D5A8B2FAF72DFE200702D5B0B2FAF7E8FBA00702D5280CFFF7CDFEE00702D0300CF9F72AF99E +:40EB400070BD70B5044660C8F8F7C8FA2089C01F0300FBF7C9FE0C071A121E212412122712171312F3F7F4FE032801D1F7F76EF9294630466289FFF7CBFF70BD284604F054 +:40EB800063FD70BDFAF750FB70BD2846F8F74CFC70BDF8F74DFF70BDFAF76CFB70BDFAF793FB70BDE8B2FAF7ADFD70BDF3B5002189B0069105910C460391009101910291C7 +:40EBC000F74989688EB230400490B00618D5FCF74BF9F44908800120F6F7B2FEF24900200870F3F77DFE012802D10020F6F72CFE2020FBF7A1FE0420F7F75CF901200590EA +:40EC0000EA487107009024D5E5484030006987B20498400718D5F80613D5E5480021026A009800780BE0884201D8002502E0D0234B43D5182B79022B29D0491CC9B288426B +:40EC4000F1D8B80880000390394600220420FBF759FE300775D5D748406B80B20190D0488030806A87B2049800076BD5019804218843384367D0D048C06BC006C00E02906A +:40EC8000009801780298814211D8002515E02846FDF7E4F82846FCF777FD2846FDF74FFA40212846FDF770FAFDF770F9C9E7C048D022016A029850430D18002F05D02846C2 +:40ECC0004030C18A3C433943C18201988207B84801463C31403006910090002A3DDA2879002803D1C420405D002833D102212846FCF71AFE2846FDF7B7F907A90298FCF738 +:40ED000001FFA878012103F0A1F9002817D1FDF755F8002813D14620405D012807D1C0217A204959405BC98B401E884207D08320405D002808D16846808B002804D0012081 +:40ED400006E0ABE099E095E00698FCF76BFE0020009908700120F6F703FEF80657D52879002803D1C420405D00284DD104212846FCF7DAFDF3F7ECFD03280CD1C0204059BB +:40ED8000807A002810D18320405D00280CD101212846FCF785FFC0204059807A002803D18320405D00280DD000980078012809D0002810D17E480021C06B807803F046F9F9 +:40EDC000002808D02846FDF74FF90698FCF72AFE0099002008707648C06B002809D001216A465172017B1172FDF7F4F802A8F6F739FD28460A3009F015FA2846C0300179CC +:40EE0000002901D1012101710220F6F7A9FDF80705D07805400F022801D1F6F7A1FD28464030018B06912946C031CA88C08A824201D00443C880087B002805D1A035287F49 +:40EE4000012801D010208443600609D500984078002802D04020844302E0009801214170394600220820FBF74DFD544901980840504948633F2000028443019840070DD5EE +:40EE8000F6F71EFBF6F78CFF4A4904204863FCF7BFF9012802D10220F6F762FDB00719D53F48806B85B20498800709D50399280408430390FFF704FDC00701D00120059023 +:40EEC00081210398490488430390294600220220FBF718FDF0073AD03148006A85B20498C0072CD02804044329208001054206D033492846096849698847012864D005203E +:40EF000040068443A8071AD50220F6F729FD284F2037B87AC00712D0787B00280FD0387BF97A88420BD2274800688168387B14225043801D0818FDF775FF00207873812074 +:40EF400040048443294600220120FBF7DBFCF00605D50120F6F7F4FC1020FBF7EDFC700602D54020FBF7E8FC039806992043084301D00120059007206946088103980090B6 +:40EF80000194049848810598002807D069460EC90A98002850D0002008F04CFA0BB0F0BD00103C40E6010008CC010008CC1E00085C21000800113C4000503D40FBFF00006A +:40EFC000EC010008D4010008FBF784FB074600218030C170384640300090807BFF2808D138464830FBF7BCFF384600214730FBF7D5FF00983946C0794831FBF767F8FF2846 +:40F0000005D0292080058443FDF7AEFE7AE73846FCF77AFF3846FCF7E3FB3846FCF71EFF3846FDF78CF840213846FDF7ADF8FCF7ADFFFDF78FFE65E7002008F040FAADE7DE +:40F04000F0B587B0054605A81E461746019100900C9C04AB06AA02A903A800F0CFF92846FCF706FA21463046FCF78AF96846017A0398FBF79FFD05A904A8FBF74DFD68467A +:40F08000027E21463846FBF71BFD07B0F0BD000070B50948C4782046F8F758FE06462046FFF7FCFA05462046F9F7C8F9014630462843084370BD00005C21000870B5094885 +:40F0C00084782046F8F74AFE06462046FFF7EEFA05462046F9F7CEF9014630462843084370BD00005C210008F8B5069E1F463478042C17D3231FDDB23B460095FFF7A0FF62 +:40F100003819001FFCF7EEF90520FDF74FFA0446012229460798FDF76FFB3570E00701D00020F8BD1F20F8BDF8B51C46009301271346069E079D3A46FFF782FF2846FCF761 +:40F14000D1F90520FDF732FA0546012221463046FDF752FB2846F8BDF8B51D4616460F460024FCF785F931463846FCF709F90320FDF71CFA012231462846FDF73DFB2046CA +:40F18000F8BDF8B5069D089E2C780094FFF758FF0120FDF70BFA07463046FDF789FB0023224631460798FCF773F8241D2C70780701D41F20F8BD0020F8BDF8B51C4600932F +:40F1C00001271346079E069D3A46FFF739FF0120FDF7ECF90746002221462846FDF70CFB3046FDF765FB3846F8BD10B500F02CF90446F9F7B7F80128F8D1204610BD10B5B5 +:40F2000000F022F90002000A10BD0000004870478422000808B500F017F96B4600210090585CC006C00E421F0B2A04D9491CC9B20429F5D3EFE708BD08B56A4600210B203A +:40F24000F6F758FA6846007808BD0000FEB5064601200290042017460D46444C0090FBF703FE28802146FBF727FC3080F8070BD0FBF73EFE019028880199FBF721FEA04221 +:40F2800002D2044601983080B8070BD5FBF742FE019028880199FBF713FEA04202D204460198308078070AD5FBF728FE074628883946FBF705FEA04201D204463780F6F765 +:40F2C0000BF900280AD0FBF709FF074628883946FBF784FDA04201D2044637802448807B00283BD0FBF710FE074628883946FBF7E7FD0546A04231D2FCF7DEFB1D4909789A +:40F30000814201D8002004E01949D022096A504308180190F7F77CFF002817D101983D21C0300068C089F3F7F3FB401DC0B200900A280BD90A21F3F7EBFB0091854204D39A +:40F34000391A281A8FB285B200E0002537802C460198F7F75DFF002800D102900098FDF7BDFE0298FDF7C0FE2046FEBDFFFF00005C210008CC1E000810B50E4C0C492346DE +:40F380000833A160002142189278002A00D05A54491CC9B20429F6D3FF21A0689A314843A06000F051F8F8F7DDFF0128F9D110BD040302015C21000870B5059C049D207046 +:40F3C000060A6670060CA670000EE0704806D101400E0843207104221946601DF5F789F82046042229460930F5F783F870BD00000149086070470000E8010008F8B5079C76 +:40F400000E46E178069D09020160A77839430902016067783943090201602778394301602079611D4006400E30702079C009107004221846F5F75DF821460422093128469F +:40F44000F5F757F8F8BD000010B5FBF70DFD094A916848400849096848408108C3084409414063405940C30F59404008C9070843906010BD5C210008E8010008F3B5074669 +:40F4800081B00E4800240E4E0E4D10E031682C234A6821465943535CDB0706D01B315118029801F02BFB002805D0641CE4B2E97AA142EBD8FEBD3C70FEBD0000FFFF000054 +:40F4C000D40100087C210008FFB585B00C4600200090A004850E0E99684601810026FFF711FB6106C90F27073F0F0191012805D13A460798FFF7C2F8012849D069462F200E +:40F5000004F0F1FD002843D1009C3E2020700599022001290CD0A070A81FC6B20120E0703B00FBF7E1F907080A0C120E121012000B20A070F2E7002008E0012006E00320D7 +:40F5400004E0042002E0022000E0FF20207101986071A01D06220799F4F7CBFF0598012818D0267320460D30AA1F0899F4F7C1FFED1DEDB203AA02A90620F6F7BBF86846D7 +:40F58000007B60556D1E65702046059904F098FD09B0F0BD01202073E4E700000249014808607047A8470010EC010008704700207047FF2070470120704710B5400606D580 +:40F5C000FF210020FAF736FA0220F8F7F5FA10BD7047704770470020704770477047002070470020704700207047002070470020704700000249014808607047EC4700104A +:40F60000EC01000870B512248AB00D46064600292FD000200290039004900590102202A92846F4F757FF002823D00821684607F040FB6946487940214006400E08436946FC +:40F64000487103226C46C91C02A8F4F752FF0322E11CF01CF4F74DFF06AA294602A8F7F755F90404240C04D1032206A93046F4F740FF20460AB070BDF0B50546FF2129704E +:40F680000022144C144B072011462468DB7A0FE02C2766684F43F65DF60707D014274F43A6681337F75D0126BE403243491CC9B28B42EDD8D143002207E0CC0702D02A7060 +:40F6C0000020F0BD4908521CD2B29342F9D90029F3D1F0BDD40100087C21000870B50546FF210D4A297014680C4A0A480021D37A0CE02C2266684A43B25AD60704D052077A +:40F7000002D52970002070BD491CC9B28B42F0D870BD0000FFFF0000D40100087C210008F8B50C460546FF206946087068798009012807D022782946684601F063FA68463D +:40F740000078F8BD2946684601F092FA68460178FF29F4D00A4E2C22306851434068091D411806222846F4F7C4FE30682C2241686846007850430A30085C801C2070DEE79C +:40F78000D40100083EB50446FF206946087213480068C007C00F19D001216846FBF7E0FB684640798009012813D02278694602A801F028FA6846017AFF2907D008482C2240 +:40F7C0000068514340680A31405C20706846007A3EBD694602A801F04BFAF7E7001F3C40D4010008F0B589B01646044600256A461570FF201075CC48072700680278CB483D +:40F800000790C07A82426FD2204606F0C7FB07006AD10C27F7F7E2F8FBF732FC002804D0C248203840784007F2D1A27A211D684601F0E8F9BE490746884220D1684606902A +:40F8400000208446FF206946087007990727CB7AB5490020096807910EE007992C2249684243895CC907C90F614503D106990027087012E0401CC0B28342EED80DE0002E61 +:40F880000BD1A9486A46006881681078142250431330085C6A46107501252846384303D105A8FFF7E9FE0746002FB1D16846017D9D48142300688268684600785843133044 +:40F8C0001154012E11D098482C230068002241686846007858430A52934800684168684600785843801C0AE01AE18F482C220068062341686846007850430A5A1A400A52B4 +:40F900000020019002900390049087482C230068A27A41686846007858430A300A54824800684168684600785843002A03D00A5A10231A430A527C482C22006841686846FF +:40F94000007850430B300818214610220B31F4F7D0FD75482C22006841686846007850431B300818214610221B31F4F7C2FD6E482C2200684168684600785043001D0818BA +:40F980000622211DF4F7B5FD6748142200688168684600785043081806220021F4F7B2FD6148142200688168684600785043801D081806220021F4F7A5FD5B481422006895 +:40F9C00081686846007850430C30081806220021F4F798FD012E33D0534C2C22206841686846007850431B300818102201A9F4F771FD0223002820686946406809780FD00B +:40FA00002C225143425A1A43425220686946426808782C214843801C115A012319430EE02C225143425A9A43425220686946426808782C214843801C115A4908490011527D +:40FA4000394C2C22206841686846007850430B300818102201A9F4F73DFD0028206822D06946097842682C204143505A04231843505221682C234A6869460978594380235A +:40FA8000184350526946226808782C21414353680B315918142392685843801D1018FFF7B1FD074608E04168684600782C2250430A5A84239A430A5220682C2142686846CC +:40FAC00000784843011D0A305118105CFDF79EF80823FF28206869464068097804D02C225143425A1A4303E02C225143425A9A43425220682C2241686846007801235043BD +:40FB00000A5A1A430A52684600210078FAF754FF38462843304303D120680178491C0170384609B0F0BD0000D40100087C210008FFFF000038B50A461B4909784907490FE8 +:40FB4000022903D0032901D004292AD11749897A490626D50146684601F054F80006000E1FD1134C2C222068082341686846007850430A5A1A430A5268460078FAF7D6FAB9 +:40FB800000280AD020682C22416868460078012350430A5A9B021A430A5268460078FDF7AFFA002038BD0000F0210008AC1E0008D4010008F1B584B000260396FAF78AFD7C +:40FBC0000446FBF75DFA002830D0049880057DD5FF2069460870002101A8FBF7C1F96946487A8009012824D0022836D001273A4601A9684601F006F805000AD0012047405E +:40FC00003A4601A9684600F0FDFFB6490546884225D0B5482C2200684168684600785043085CC04380071AD4AE4D1AE0012005B0F0BD01A96846FFF721FC050011D101201B +:40FC40000390A9482C22006841686846007850430A30095C4720015503E00027C7E747200755F8F78BF8002D57D1012823D0042821D00220F8F75EF801281CD19A4D2C2160 +:40FC800028684268684600784843011D0A305118105CFCF7BBFFFF283FD028682C22416868460078082350430A5A1A430A5268460078FDF725FA039800281CD08A4D1422CC +:40FCC0002868816868460078504300E032E00818062201A9F4F70DFC286814228168684600785043024613328B5C08187F492022096AFDF78DF9684600784E2108557A4952 +:40FD00002C22096850434968001D0918204606224830F4F7EEFB012675E0754880694007800F012803D100217248FDF743F8FDF71BF868E00498400665D5FF2668466E49B4 +:40FD40000670684F0868012280B2920310430860002101A8FBF704F9FBF792F925464035AE73012600284ED06846407A8009012828D0002201A9684600F044FF002806D0E0 +:40FD8000012201A9684600F03DFFB8420AD056492C2309684A68694609785943515CC943890701D5002812D05448807AC0072AD00020FDF71DF94E4880694007800F0128C3 +:40FDC0001AD01DE001A9684600F052FFEAE768460078A87344492C230968584303464A680A33D25CEA714968001D0918204606224830F4F77EFB06E000213E48FCF7DAFF16 +:40FE0000FCF7B2FF0026049800053CD5FF2568460570344E002101A8FBF7A2F8002201A9684600F0EFFE002806D0012201A9684600F0E8FEB04221D02B492C2309684A68B8 +:40FE4000694609785943515CC943890716D428488169006A89B2C0050CD44807800F012803D100212348FCF7A5FF0020FDF7C0F8FCF77AFF4034A5730020D8E6002804D043 +:40FE80004034A57301263046D1E6174D2C222868022341686846007850430A5A9A430A522868142281686846007850431330085C00221946FDF78EF96846214600784031F3 +:40FEC00088732A682C256843054653680A355B5DCB715168001D0918204606224830F4F708FBCFE7FFFF0000D4010008F021000800103C40F0010008001F3C407C210008E6 +:40FF0000F0B500278BB004463E46FAF7E3FB08907A4D60057ED500200690059009A9039004900191009007AB03AA05A90320FBF745F86946898B4906CA0F002816D16846B9 +:40FF4000407C03A98009012802A815D000F05AFE6B4988420AD029682C234A686946097A5943515CC943890700D465486946497E8909012904D011E0FFF780FA0127F5E7A3 +:40FF8000002873D128682C2241686846007A50430B30091805A800F0B1FD0126002865D10120F7F7C7FE01281BD169460A7A28682C214A434068131DC1180A32805CFCF725 +:40FFC00025FEFF2852D028682C2241686846007A082350430A5A1A430A526846007AFDF78FF83800474F1AD02868142281686846007A50430818062203A9F4F77AFA286863 +:020000041001E9 +:40000000142281686846007A5043024613328B5C081800E02AE02022396AFCF7F9FF002E24D028682C2241686846007A402350430A5A1A430A522868142281686846007ADD +:4000400050430C300818062205A9F4F752FA2868142281686846007A5043024613328B5C0C3008184022796AFCF7D2FFE00606D525490868012280B2D20310430860E004D9 +:400080002AD500206946087209A90191009007AB03AA05A90320FAF791FF00281CD16846808B03A94006C20F6846407C8009012802A804D000F0A6FD002803D00CE0FFF7D8 +:4000C000DDF9F9E728682C2241686846007A5043085CC04380070ED509208001044201D1200508D508984030817B0020F9F7A2FC0220F7F761FD0BB0F0BD0000D401000806 +:40010000FFFF0000F0210008001F3C4070B50C24F6F764FCFAF7B4FF002803D00E484078400717D1FAF786FD0C4D002128680A4C01702034E27A2C214A4340680021F4F70C +:40014000E1F9E27A14204243286800218068F4F7D9F90024204670BD5C210008D4010008F8B5144800784007400F022803D0032801D004281DD11048807A400619D500244D +:400180000E4F08250E4E11E038682C21426820464843115A0B4BA94311523A681940526811522046FCF7ACFF641CE4B2F07AA042EAD8F8BDF0210008AC1E0008D401000813 +:4001C0007C210008FFFB0000F0B504468BB0AD48002607903546600605D4A00603D4E00501D4A00528D5FFF711F809A90191009008AB03AA05A90020FAF7E0FE0790600624 +:4002000001D4A006EED5002069460872FF2000900798002810D1088C41060007000F01906846407CCA0F8009012803A902A804D000F0E8FC002804D000E1FFF71FF9012659 +:40024000F8E76846407E904F8009012810D1019801280DD138682C2241686846007A50430B30091805A800F049FC01250028E3D186488078F8F7FEF801281CD169460A7A9B +:4002800038682C214A434068131DC1180A32805CFCF7BCFC0090FF28CED038682C2241686846007A082350430A5A1A430A526846007AFCF725FF019801283DD1002D3BD01A +:4002C0003868002E05D081686846007A1422504305E041686846007A2C225043001D0818062203A9F4F7F6F80006000E01D1002E24D168463A68007A2C23434351680B3361 +:40030000C9181423926858430C301018FFF77AF909903868142281686846007A504302461332801D8B5C081859498022896AFCF76FFE099800287DD1002E3CD03868142241 +:4003400081686846007A50430818062203A9F4F7D0F83868142281686846007A5043024613328B5C08184A492022096AFCF750FE0098FF281FD0386842686846017A2C202E +:400380004143505A430702D5019B012B01D1002D03D001235B021843505238682C2241686846007A202350430A5A1A430A526846007AFCF7A5FE002D40D038682C22416892 +:4003C0006846007A402350430A5A1A430A523868142281686846007A50430C300818062205A9F4F786F83868142281686846007A5043024613320C308B5C08182449402294 +:40040000496AFCF705FE21482030807A400715D50098FF2812D038682C2142686846007A4843115A4B0703D501235B0219431152684600E002E0007AFCF762FE200606D531 +:4004400014490868012280B2D20310430860E00501D4A00510D5002069460872079800280AD1088C4006C20F487C03A98009012802A803D000F0C6FB0BB0F0BDFEF7FEFF46 +:40048000FAE70000FFFF0000D40100085C210008F0210008001F3C4010B5054A01781175411C034806220E30F4F723F8002010BDA0210008F8B515461E46024600206B46E5 +:4004C0001870684600F09EFB0406240E02D002242046F8BD0948002E006881686846007802D01422504302E014225043801D091806222846F3F7FDFFEAE70000D4010008CA +:400500000148C07A704700007C210008F8B50646002768463C4D0770286802240078002818D0304605F03EFD040013D10C24F6F755FAFAF7A5FD002803D0344840784007CD +:4005400008D13278711C684600F05CFB0406240E02D002242046F8BD28682C2241686846007850430F5268460078FCF7D1F9296808780028EED06A461278431E93422AD042 +:400580004B682C2148432C3819182C20424398182C22F3F7AEFF2968142288680978142351436A461278143941185A4380181A46F3F79FFF28682C224168007850432C38BF +:4005C00008180021F3F79EFF2868142281680078504314380DE048682C214A4380180A460021F3F78FFF286814228168684600785043081814220021F3F784FF28680178E0 +:40060000491E0170A6E70000D40100085C21000838B50A46174909784907490F022903D0032901D0042922D11349897A49061ED50146684600F0E6FA0006000E17D10F4B56 +:4006400069461868097842682C204143505A0824A043505219682C234A68694609785943074B1840505269460878FCF749FD002038BD0000F0210008AC1E0008D401000816 +:40068000FFFB0000F0B58BB00446FF206946087200200A90A00605D4600603D4200601D4A0057DD5FEF7B2FD08A909900191009007AB03AA05A90020FAF780FC01908E4E4F +:4006C000A00601D460066CD50198002869D10025694600950D72888B4006C20F487C03A98009012802A804D000F08CFA070009D013E0FEF7C3FE070001D001250DE0012020 +:400700000A900AE030682C2241686846007A5043085CC043800700D4784F6846407E800901281BD16846808B0007000F012815D130682C2241686846007A50430B300918D4 +:4007400005A800F0DBF9002804D00225384304D0012703E001210091F8E70027002F7AD167488078FDF7A2FF01281ED130682C2142686846007A4843011D0A305118105C95 +:40078000FCF744FAFF2866D030682C2241686846007A082350430A5A1A430A52684601E0A5E06EE0007AFCF7ABFC30682C2142686846007A4843115A4B0707D501235B0247 +:4007C000194311526846007AFCF79AFC00984D4F002824D030686946097A40682C225143425A40231A434252306869468268087A142148430C301018062205A9F3F779FEE7 +:40080000306869468268087A1421484301461331535C0C3010184022796AFCF7F9FB0A98002818D03068142281686846007A50430818062203A9F3F75CFE30681422816868 +:400840006846007A5043024613328B5C08182022396AFCF7DDFB002D13D06846818B0807000F012805D12848407E012801D1022D10D06846008C009003AA0020099BFEF72A +:4008800023FEA00533D50020694608720198002807D015E06846008C009005AB03AA0120EDE7888B4006C20F487C03A98009012802A81ED000F0A6F96846007AFF2816D0D0 +:4008C00030682C2142686846007A4843115ACB439B070CD50A4B20339B7A9B0707D501235B02194311526846007AFCF709FC0BB0F0BDFEF7C3FDDFE7D4010008FFFF000061 +:400900005C210008F0210008A021000870B5054605F05AFB04000DD107484078400709D1F6F75CF8FAF7ACFB01462878884201D0FAF7E4F9204670BD5C21000870B50646DA +:4009400005F048FB040010D1094D287EF5F73CF900280AD132887D20EA82C00042432846044B00211830F5F7CBF8204670BD0000A02100085D0B011038B505460020694681 +:400980000C240870FAF77CFB002803D01E484078400708D12A78691C684600F033F90406240E02D00224204638BDE8790223174A002810684168684600780ED02C2568433E +:4009C0000D5A9D430D521068142281686846007850431330085C002211E02C256843851C4D5DED07DFD00D5A1D430D521068142281686846007850431330085C01220221FA +:400A0000FCF7E8FBCFE700005C210008D4010008F8B50024264E054600291AD00C213046F4F760FC0004000C40D1E9792C2041433068001DF4F756FC0004000C36D1E9797D +:400A40001420414330680830F4F74CFC0004000C2CD118484022817A002711438172E879154D2C21E87230680770EA7A40684A433946F3F747FDEA7A1420424330680021EE +:400A80008068F3F73FFDFF2007E014223168624313328968641C8854E4B2E97AA142F4D8E1200649AF728000C8820020F8BD0000D4010008AC1E00087C210008A021000847 +:400AC00070B5FF2815D00B4A0446126853682C2254431A5BD5070CD055070AD5002903D0012189020A4301E003490A401A53FCF707FB70BDD4010008FFFB000070B5164C4A +:400B000088B00E46050023D0002E21D0002000900190029003906879400619D5102269463046F3F7D7FC0006000E11D00322E91C6846F3F7DEFC04AA31466846F5F7E6FE4F +:400B4000032204A92846F3F7C5FC002800D10024204608B070BD0000FFFF0000F8B51E491F4B0878401E08701C480021C28A7D20C000424319481830F4F7C2FF0024194DBE +:400B800023E0194B20461A682C26516870430E5CF60718D00B30091820461423584392680746861D9019FEF72DFD0006000E0AD10D48133700680D498068896AC35D8019B3 +:400BC0008022FCF725FA641CE4B2E87AA042D8D801206873F8BD00007A010008A02100085D0B01107C210008D4010008F021000810B5014606220248F3F77BFC10BD00007A +:400C0000F0010008F7B582B016490091FF20029900240870144E154F1FE030682C21254640684D43291D401806220399F3F752FC002810D13068294640680A31425C049982 +:400C40008A4208D1405DC00705D0029804700020009005B0F0BD641CE4B2F87AA042DCD80098F6E7FFFF0000D40100087C210008F3B581B0FF200199114F08700024114D77 +:400C8000114E17E02868062281681420604308180299F3F71FFC00280AD1286841682C206043085CC00703D001980027047004E0641CE4B2F07AA042E4D83846FEBD00000E +:400CC000FFFF0000D40100087C210008FEB50446002069460190087007460646014606225448F3F70FFC5348FCF72AF96079524D022801D003287DD1A279E11D6846FFF7AC +:400D000081FF0606360E23D14C482C230168684600784A684343D25C120619D5142289685043801D0818FCF77DF84448142200688168684600785043024613328B5C801D55 +:400D40000818892180224901FCF762F9012001902079012801D0042815D168460078FF2811D036492C22096842434B681B329A1889681423584308181146FEF743FC0606FB +:400D8000360E0BD000260198002842D0A87A01210843A87268460078287345E0274F2C2238684168684600785043085CC043800702D5E01DFCF7C4F83868142281686846E8 +:400DC0000078504309180622E01DF3F792FB386814228168684600785043024613328B5C081817492022096AFCF712F938684168684600E014E000782C2250430A5A012360 +:400E00005B021A430A5268460078FCF779F90127B9E76079022801D0032801D1801E6071A87A40084000A872002F01D00120A0713046FEBDF00100087C210008D401000867 +:400E4000F0210008F3B587B00C46FF206946087000250595019508728548039060792F46022801D0032800D10127207E022801D0032800D10125FAF703F9002810D02079FD +:400E80007C4E012819D06279002F01D0921ED2B2A11D6846FFF7B6FE0390002816D0BEE0002F02D06079801E6071002D02D06079801E6071002009B0F0BD002DEFD002A846 +:400EC000FEF70CFC039000287ED0A8E06A482C230168684600784A6843431B33D31889681422504308181946FEF78CFB0799039040310491002836D0002D66D05E482C22F0 +:400F000000684168684600785043085C40075CD506220021A01DF3F7F5FA04986179C1710121A01DFBF746FF534D1422286881686846007850431330085CFBF787FF2868B7 +:400F40002C22416868460078032350430A5A1B021A430A5268460078FCF7D2F8B07A04210843B07279E04448142200688168684600785043024613328B5C08183F4920223F +:400F8000096AFCF745F806220021A01DF3F7BAFA04986179C1710121A01DFBF70BFF0120019035482C220068FF23416868460078013350430A5A1A430A5268460078FCF794 +:400FC0009FF82D48006801E01AE028E0816868460078142250431330085CFBF737FF002D1DD025482C2100684268684600784843115A4B0713D501235B0219431152A9E7E7 +:401000001D482C220068012341686846007A50430A5A5B021A430A526846007A9CE7B07AFB210840B072002D17D00598002814D1207E801E20766846007AFF280DD00E4925 +:401040002C2209685043496801230A5A5B029A430A526846007AFCF753F8002F05D00198002802D16079801E6071039823E70000FFFF00007C210008D4010008F0210008CB +:40108000FEB5054640790027424E022801D0032845D16846FEF722FB07063F0E12D13E4C6846226800782C21414353680B315918142392685843801D1018FEF7A3FA0706E6 +:4010C0003F0E05D06879022827D0032825D026E020681422816868460078504302461332801D8B5C08182D498022896AFBF790FF0120687120682C224168684600780123C6 +:4011000050430A5A5B021A430A5268460078FBF7F7FFB07A022108431CE0801E687101204002002401900FE01B482C22006862434168019B885A98438852C00702D02046E9 +:40114000FBF7DEFF641CE4B2F07AA042ECD8B07AFD210840B0720F49A8792039104A03280BD0022812D001280CD0002050768878FD22104088703846FEBD01205076A879F7 +:40118000801EA871887802221043F3E701205076F1E700007C210008D4010008F0210008A021000810B509490748096888420AD10748084BC28A7D20C0004243044800214B +:4011C0001830F4F79DFC10BDEC470010EC010008A02100085D0B0110F7B515460C46F9F74FFF0746FF2C3DD0002F3BD014212646687C4E432C2180094C4301281AD11C4893 +:40120000214600680A314268525C0099921C4031CA714168201D0918284606220C30F3F768F91348062200688068811928461830F3F75FF90098F5F7EBFF002815D0042031 +:401240000C49897A01420DD0094800684168095D490707D58068B61D8119284606221230F3F747F9F807C00FFEBD0120E8E70000D40100087C21000810B510490A781049B7 +:40128000824201D8002003E0D0230A6A58431018002812D00A6B138802468032146B23800B6B146B5B88A3810B6B126B19881289914202D05A8800F009FB10BDCC1E0008C9 +:4012C0005C210008024901484860704750480010F8010008F7B50D463449334F897A84B03E4689065DD52C468034216B0A8B2946C0310091824204D3886820308078002820 +:401300004FD0002A02D12A48006B828828460699F5F7A6FD0646B84208D12889002102F098FD069805F0D8FF00263AE00027FF2069460197087200988068203081780129F2 +:4013400003D1A178002900D0C170A078401CA070A878FCF711F90407240FA878FCF7D4F80007000F04430F2C00D00127002416E00120009002AB03AA01A92846F5F7B8FC2B +:4013800000280AD10199002907D06846037AFF2B03D0027B2846F6F7BEFA641CE4B2BC42E6D3304607B0F0BDFFFF0000AC1E00085C21000870B50446C034217B0546002969 +:4013C0000CD0284600F0CAFA072807D0207B152802D1284600F018F80020207370BD704700487047FFFF000070470120704770470020704700207047024901484860704755 +:4014000030480010F801000870B50646FDF7FEFE04463089354620808035286B4089E080286BC08A2081286B00896080286B808AA0803046F7F705F9204604F027FF70BDED +:40144000FEB5044600790D46C01E05280DD848482E78807A20278006002807DB31462046FCF753F9E07E3843E076FEBD40212046FCF7A8F9A8786946000288806978084346 +:401480006946888029790A026946CA80E9780A436946CA80A9790A0269460A8069790A4369460A80297A0A0269464A80E97925460A4369464A808035296BC88069460888CD +:4014C000296B88806946C888296B488269464888296B0882204600F099FA2046F5F798FE00281ED1FDF7A8FE5E210A5B6179F6F7D1FD22460146A032507D0128286B408988 +:4015000026D080003C3083B2107D0128286B008B21D080003C3082B2103189B22046FDF73FF86420015BA078FBF728FC142E15D00F49A07D897AEF2239400843E17E384346 +:4015400011403943E176A0752046FFF75DFFFEBDC0007030D7E7C0007030DCE71521CC200155A07D3843A0752046FFF723FFFEBDAC1E0008014A526812691047F801000876 +:40158000014A526812691047F8010008F3B585B0FF206A460024107301941472184A2046927A920628D5059EC036B26820329578002917D1002D14D0009003AB02AA01A9B4 +:4015C0000598F5F795FB07466846037BFF2B06D00199002903D0027A0598F6F79CF9002F00D00124B0682030C178002904D0002D02D00124491EC170204607B0F0BD0000E0 +:40160000AC1E000870B504464878142801D015283BD1E07EEF21084020210843E076A07DDF210840A07540212046FCF7CBF82046F5F7EEFD002820D1FDF7FEFD5E210A5B9B +:401640006179F6F727FD22460546A032517D204680300129016B498918D089003C318BB2006B117D008B012913D080003C3082B21035A9B22046FCF793FF6420015BA0785F +:40168000FBF77CFB2046FFF7BFFE70BDC9007031E5E7C0007030EAE710B5044604F036FE00280CD106490A6B928822800A6BD28862800A6B1289A280096B4989E18010BD01 +:4016C0005C21000810B5044604F026FE002806D103490A6B12882280096B4988618010BD5C21000870B5054604F01CFE002817D12888F7F731FD040013D0F8F7A6FB0028D1 +:401700000FD0207909280ED02046F8F7AFFB01280BD0F5F763F9AA886988204600F0D6F870BD022070BD0C2070BD2A2070BD000010B5044604F0FCFD002806D10349228853 +:401740000B6B1A80096B62884A8010BD5C210008F3B5064631480025807A83B080065AD53746C0373868344680340090206B0290B8680190F1F7D2F8D02200213046F2F7A7 +:40178000C1FE029820630198B86000983860F1F7AFF8049801280FD130462421C830F3F7A1FD05042D0C36D130461A21B030F3F799FD05042D0C2ED11A220021206BF2F791 +:4017C000A1FE3046049900F05DF81549226B086B80881080086B226B00895080226B1B209080226BD080226B1081226B50810A6B236BD2889A81096B226B4989D181FF21B5 +:40180000226B49311182226B5182226B9182226BD182216B0883284605B0F0BDAC1E00085C21000810B504460020002906D00C211248F3F757FD0004000C1DD10F491B226A +:4018400030390B6B1A80FF220B6B49325A800B6B22889A8022880B6BD2007032DA800B6B62881A816288096BD20070324A81044920238A7A1A438A7210BD00008C210008D4 +:40188000AC1E000870B50546C03500290FD1A86820308678002408E0A868E1004058002801D005F019FD641CE4B2B442F4D324220021A868F2F726FEA868FF2120300170A9 +:4018C000A86800212030417070BD000070B5064604468036306B03898B4206D1838A934203D11D4B1B78002B07D0E37E9D0606D5A57DAD0603D41A2070BD002070BDDB067A +:4019000028D483891546AB4200D91D460180306B82812046F5F77CFC00280ED1FDF78CFC5E210A5B6179F6F7B5FB316B1030CB8981B22A462046FCF733FE6420015BA078FF +:40194000FBF71CFAE07E10210843E0761420C0342073D2E7232070BDF801000838B50546002000900C46A978684605F041FC002807D0142C03D1E87EEF210840E8760720B9 +:4019800038BD0098092204702C468034216B89784170216B4988090A8170216B897BC170216BC989090A0171216B09784171216B0988090A8171216B097BC171216B898951 +:4019C000090A01722946F8F799FE38BD70B504460088F7F7C1FB014680310B46096B2289CD89AA4203D1E5884E88B54206D0CA811A6BE1885180044A01211170A28861883A +:401A0000FFF764FF70BD0000F801000830B50024002835D0014680310A6BD3881588AB4200D32B4615899D4201D0138101240A6B538A9589AB4200D32B46958A9D4201D0DC +:401A4000938201240A6B958853889D4200D22B4655899D4201D053810124096B0A8ACB899A4200D31A46CB8A934201D0CA820124B421095C012200F007F802490020087010 +:401A8000204630BDF80100088030006B0129838A09D099080F39038989B28B4200D21946002A03D005E0D9080E39F4E7028B8A4200D901837047000070B504461B3CE12CD4 +:401AC0001CD2104C246BA588854217D30E4DA94214D8FF204930814210D3E6888E420DD3FB2A0BD81B2A09D32189914206D3AB4204D8834202D36089984201D2122070BDCA +:401B0000002070BD5C21000848080000F0B5314A0446314B002110465D5C491CC9B2A542FAD1A3009E462D4B491EDB7DCDB29C462A4C00216B003434E45A284B4E003433EC +:401B40009E5B254B5B5C9F00244BDF59BF897F00F619B6B2B44202D90020614625E0B24200D932460E46491CC9B2AE42E5D11CE01A4B4D0034335B5B1E1B052E09D2164D90 +:401B8000164E6D5CAF00F559AD896D005B199BB206E0124F75467F59FF89FF1CBE4217D39A4200D91A46491CC9B28C45E0D8094988420CD1101B04280AD9084A71465158CD +:401BC000C01E897C80B2002901D1401E80B2F0BD0020F0BDFFFF000000020008B4220008F7B50546002082B0164604460090F9F73BF90346002015E081006A581278002AED +:401C00000ED0062A0CD0464A670010556958098ACA1A012109045118424A641CD153E4B2401CC0B2697D8142E6D8012021E0014611E03C4B94467246DA53019B6246DA8352 +:401C4000374A575C5318BC46203BDF7F57546746491EDF77C9B2002909D0324B4F00DA5BFB18203B0193DB8B9E467245E1D3401CC0B2A042DBD300200399641EA446294CC5 +:401C8000086015E026494200095CA35A8F00EF591219FF895288DB19DB1C93420AD9039A136801228A4013430399401CC0B20B606045E7DB0399096800290BD0184A125C35 +:401CC0000120904001430398016001200090009805B0F0BD124801788A00A858807C3070B170002801D00128F1D1AA5821889289638852008A1892B2934204D9511A05E01F +:401D0000491EB180E3E7591A042905D9C91E89B2B1800028F4D0DAE70020B080D7E7000000020008E822000870B50A46034641780024007800F010FA264DFF2847D09E78C5 +:401D400025493300F8F7D0FD09060A0F13171B1F242943008000085800781CE0800008584068106034E08000085800890EE080000858807A0FE080000858808906E080001B +:401D80000858C08902E080000858008A10801FE080000858807C10701AE080000B581B7813700B585B6853600B581B8913810B589B7A93720B589B8993810B58DB89D381A9 +:401DC0000B581B8A13820858807C907400E02C46204670BD01001600B4220008F8B50446002020606060254EA060F07D002809D001280CD0224669463046FFF7F1FE012834 +:401E00001AD031E005202070FF20A070F8BD307E2070317DA170002801D00128F6D1317D8900715889894900C91E89B2A1800028ECD1491EA180F8BD0127104867701C30C5 +:401E4000009905F0B1FB054680003058807C2070B17D2846A94207D9FFF758FEA080A5700098AF40B843A06020783076A0783075A178A088890071580881F8BDB422000835 +:401E8000F8B5154F05460026387D344600901EE0E80716D0009880003858018AA0003858008AF8F79BFF0121C903884201D3002807D1094821461C3005F0EAFB0120A0402D +:401EC0000643641C787D6D08E4B2A04201D3002DDED13046F8BD0000B4220008F8B505460020287068602872F8F7BEFF0746F8F7C1FFFF213931884201D2022600E003266C +:401F0000002420E0A00010580178002919D0062917D0008A0121C01B0904401880B24910884201D8B0420CD801202870917DA14203D96968A040014369602146054805F0F7 +:401F4000A7FB641CE4B2034A1C3A507DA042D9D8F8BD0000D022000870B51C4DFF222A7505222A7600266975EE75A975334606E014225A4312189C005B1C2A51DBB28B4219 +:401F8000F6D30C4603E0A200641CAE50E4B2052CF9D314224A4310180A4601460B481C3005F09BFA00280FD100240AE0A000285821460670012000F00BF8002804D1641C21 +:401FC000E4B2A97DA142F1D870BD0000B4220008F3B583B0002668461A4C0671607D0D4600282BD069464D70039808702946039800F0B2F80746FF281ED0024601A968466A +:4020000000F060F9B8002258711E51602258090C118122589672225891812258D18121582A460E8220580521817420461C30039905F07EFA05B0F0BD0348FBE70248401CEE +:40204000F8E70000B422000801001600F8B50F4606460024F8F708FF0546F8F70BFFFF213931884201D2BF1C00E0FF1C0B48B2008258F9B2107800280ED006280CD0108A27 +:402080000122401B1204801882B20120C003824201D88A4200D801242046F8BDB4220008F8B52B4D0024E87D022801D20020F8BDF8F7DAFE264F264B002134370126360463 +:4020C0005D7D11E08B00D2581378002B0AD0062B08D0204B1955128A6300121A9219641CFA52E4B2491CC9B2194A8D42EAD8012117E008460AE07B53164BF2831A18203A61 +:402100001D5CD67F1E54401ED577C0B2002806D04500EE19203E7A5BF38B9A42EBD3491CC9B2A142E5D30B49388809787B888A0007498A58D2898218D21C9A4206D80A7DBB +:4021400092008958C989C91C8842AFD80120F8BDB422000800020008022804D20348807D401E884200DAFF2108467047B422000810B50146014805F0FBF910BDD022000854 +:402180000A4610B50146024805F066FA10BD0000D02200080A4610B50146024805F04CFA10BD0000D0220008F3B500980C46417800250078FFF7D0FF06463F48FF2E78D0C0 +:4021C00000993E4F89783E4A0B00F8F78DFB09060F161D242D34393E72002178062968D232462146009800F06DF863E0216891425FD8B000385841605CE02188914258D882 +:40220000B0003858018155E02178022951D2B000385881724EE021881922D201914248D8B0003858818145E02188914241D8B0003858C1813EE0B10079582088088239E04C +:402240002178052935D2B0002FE02178062930D2616891422DD8218991422AD8A17A022927D2A3891921C9018B4222D8E18991421FD8A17C05291CD232462146009800F0DD +:4022800021F8B0003A58616851603A58218911813A58A17A91723A58A18991813A58E189D1813A58218A1182A17C3858817401E0FFE705462846FCBD01001600B42200080F +:4022C000FF18000010B51A4B92009A58097814781170002C0BD0002917D1D87D401EC0B2D875012811D1194600204B7D1DE0012901D0022909D1D97D491CC9B2D975012904 +:4023000003D1417819750078187610BD82008A581278002A07D0062A05D082008A58927C0A76087510BD401CC0B28342EED810BDB4220008A03001777047000002490148E8 +:402340000860704798480010080200087047704770477047704770470249014808607047704800100802000870B5224DA030447E6E7D002334404476067E2D7D2E400676EB +:40238000857E2C400C70047EC57E2C4014700D780224032D00D30C701578032D00D31470447E0025012C02D0022C04D00CE0047E012C03D008E0047E022C05D10C78167869 +:4023C000B44201D00D701570047D0E78344200D00D70447D1678344200D015700978002901D0012381751178002901D00123C175184670BD7C2100081CB50400684681701A +:4024000008D020896A4610802046A030417D1171007DD0702146C031487B820701D57D2202E0C20702D07E221040487303496846096888472046F6F704F91CBD54020008A6 +:4024400010B541780078491EC9B2FAF73DF9024904200876002010BD5C21000810B5C1780278491ECBB281784078FAF743F9024903200876002010BD5C210008F0B587B08A +:402480000026694600960E740E75054605AA04A9FFF76AFF2C46A0340746012814D1A07D022602282AD000200290E07D022827D0002001902846FCF79CF80090A878009B7B +:4024C000019A0299FAF75EF91F48807A800604D5A17D00222846FFF7D7FA03966846007C009E00906846007D019000200290A97802A804F07DFE002818D103E00120D3E7C1 +:402500000120D6E702981823019A0099037041708270C670310A017105222946F8F7EEF880212846F5F7C8FB03982077002F08D1607F002805D10320607700212846FFF7FC +:402540005BFF07B0F0BD0000AC1E0008014A12689269104708020008F8B50F460546F4F757FE214EF17AC907C90F12D02C467978A0342176B97801276176677700280DD0D0 +:402580002846FFF77BFFC035687B822108436873F8BD39462846FBF73AFDF8BDB07A800604D5002201212846FFF76EFA00200090A978684604F01CFE0028E4D10098172248 +:4025C00002700A4A2946537D4370127D82700322F8F794F8728A80212846F5F74DFB042020776777CFE70000AC1E00087C21000870B506460E480C46C07AC007C00F30469E +:402600000DD0F4F705FE00280CD035466078A0352876A07868763046FFF730FF70BDFBF7F6FC70BD172224213046FBF722FF70BDAC1E0008014A1268D269104708020008C7 +:40264000014A1268126A10470802000870B517490978814201D8002504E01549D022096A50430D18002D1FD02C46A034207F02281AD1E07D60750E48A17D21752030027D69 +:40268000E276407DA07609482038807A800603D501222846FFF7F8F9002020770320607700212846FFF7A8FE70BD0000CC1E00085C210008FEB50C460746F4F7A9FD0128EA +:4026C0001DD080213846F5F7F7FA2E48A578017D407D667805400E402079E1780002014330463C462843A0340191002804D0B878F8F75AFD012808D0002E0FD00FE0182208 +:4027000024213846FBF7B5FEFEBD28215A20C155002020773846F6F7AFFBFEBD667D002D00D1257D207D28420ED0607D30420BD000200090607F00281BD1032060770021C6 +:402740003846FFF759FE14E0022D17D00021022E16D0002202200090B878019BFAF712F80948807A800604D5002229463846FFF78BF9E675A57500982077FEBD0121E6E731 +:402780000122E7E77C210008AC1E000870B50C46F6F7E2FC0546002060702070002D0BD02846F7F752FB002806D0A035687D6070287D2070002070BD022070BD10B501785C +:4027C0004478CA078378084903D14A7D224009D08A750078800703D4087D184002D0C875002010BD112010BD7C210008F8B50746FF2168460170FE783D793888F6F7ACFC1F +:4028000004000FD0F7F721FB00280BD0B9782148CA0709D0B422175D89070AD4067D2E4005D008E01E20F8BD477D3740F4D11120F8BDB520065D2546A035687D304209D07D +:40284000287D384206D00320687700212046FFF7D3FD14E002236A4618212046F7F75BFB01280ED002236A46FF212046F7F70CFB012806D0AF76EE76204600F07FF800209C +:40288000F8BD68460078002801D02320F8BD2A20F8BD00007C21000870B50E4605468021FAF790FF2C460020A03420770C48017DE176407DA0760B48807A800604D5217D80 +:4028C00001222846FFF7E0F82846F4F7A1FC002805D10320607731462846FFF78DFD70BD7C210008AC1E000870B505468021FAF769FF2C460021A03421770C49087DE076E9 +:40290000487DA0760A48807A800604D5217D01222846FFF7B9F8607F002803D100212846FFF76AFD0320607770BD00007C210008AC1E000810B50F490978814201D800207C +:4029400004E00D49D022096A5043081800280FD00949A03020318A7D037D9A4203D1CB7D447DA34204D08276C97DC1760121017710BD0000CC1E00085C210008F8B5054647 +:402980002C460020A0346077207F012801D1022060772846F4F73CFC134F00281AD0032600200090A978684604F022FC002810D1009816220270A27E4270E27E82702946AA +:4029C0000322F7F79BFE7A8A80212846F5F754F92677F8BDB87A04268006E1D5A17E00222846FFF751F8DBE7AC1E0008F7B54804040C82B0384801900178029816468142F6 +:402A000005D919200002844201D8082E01D9334C52E0029F0620474331483D182879012801D0022802D1029800F0C8FB2C48C4536E71C45B408B84421ED22146F0F768F861 +:402A4000002919D10094019800240078019011E006202146414322480E183079012801D0022804D170880099F0F752F87180641C0198E4B2A042EBD8029800F033F8174999 +:402A8000044688421DD0164E6C80F15B708B814206D2F0F73DF8002902D1029800F000FC718BF05BF0F734F8002908D0022028710B48017F491C0177204605B0F0BD012096 +:402AC000F5E72879002803D06888801C80B200E00A2068800320EAE7CC1E0008FFFF0000F2220008F0B50646AFB00020039001200690E0480090E048089030460622DF49B6 +:402B00005043002501904018029050E028460621DA4A4843811804910979012901D0022943D1B54241D0039F14214F430BACE5550199105A515A00F0A3F93F1904467860ED +:402B400001282AD0049802994079497905914118A14204D90020B860F860069015E00499201A49880919081A04912146EFF7D0FFB96004990598081A2146EFF7C9FFF96036 +:402B80000098844201D2A0B20090F868A04201D9012000E00020387403E00020B860F86006900398401CC0B203906D1CEDB208980078A842AAD8069800280ED00398002801 +:402BC0000ED000200490AD490198085A01900020044605900546039045E00020C04343E1A64806760199415A418300203CE1284606214843A14907904018069000790128A7 +:402C000001D002282DD1B5422BD01420214641430BA80F18B8680099EFF77AFFB960F8680099EFF775FFF9600698069940884979A70042181FA9CA510099EFF769FF27A872 +:402C4000C1518E490798095A019800F019F901901FA8C0590099EFF75BFF1FA8641CC151E4B26D1CEDB208980078A842BFD8601E054681B20A901FA800F0FAFAA9B227A869 +:402C800000F0F6FA002729E00898002500780790B80006901DE0062029464143774808180179012901D0022911D1B5420FD04188407908180099EFF72BFF0A4606981FA994 +:402CC0000858824203D106982BA90D5004E06D1CEDB20798A842DED87F1CFFB2A742D3D3002559E0AE002BA806968059062148436249401840880099EFF70AFF1FA88059EE +:402D00000F4686B209902146681CEFF701FF880008902BA907900858062148435749401840880099EFF7F4FE07981FAA105A012C82B223D9B94201D3B1420ED9BA4201D326 +:402D4000B2420AD9914214D3B24201D2B94201D8012000E00020002810D08F420ED196420CD10A98854209D0069923AA0998505010E0B942EED8B242ECD3E9E7089827A906 +:402D800009580198401E08180199EFF7C1FE069823AA11506D1CEDB2A542A3D300205BE000991FAA8900555823AA535800202E461F469D424DD0002122E0142251430BAA09 +:402DC00089188A680020B24205D3BA4203D8AA4200D915460120C968B14206D3B94204D8994200D20B46012007E0002805D18A4214D99642F7D88F42F5D36146491CC9B2E4 +:402E00008C46A142D9D3002823D0AB4210D30399581B884207D8002905D01AE0964218D98F42E0D315E003905819400804900EE0019803991818401B88420AD903900198ED +:402E40005919081840080199EFF762FE0491012005900098401CC0B20090A042A0D30598002800D1B9E6049802994880029840882FB0F0BDFFFF0000CC1E0008F2220008D4 +:402E800010B50C46002807D0002C05D0EFF740FE20460C00FAD110BD002010BD014606225143064A04488A181179012901D0022900D1508870470000FFFF0000F222000875 +:402EC000FEB5284B1B780293834209D91923DB01994205D89A4203D8062901D3062A01D22148FEBD914201D10846FEBD49040E0C51041E4A0F0C117F002905D0012906D1B0 +:402F00001146097E814202D1F0198008FEBD3D4624E001200024019016E0204606214843124942181279012A0CD1085A29460090EFF7EEFD002905D028460099EFF7E8FD1C +:402F4000002909D1641CE4B20298A042E5D80198002801D06808FEBD6D1EADB2B542D8D2D2E70000CC1E0008FFFF0000F2220008FEB5062107466A4E4F43BC1921790129E8 +:402F800006D0022904D0F7F76FFF6188401860E0337E0121062283426ED1624B00241D780BE0062363439B191B79012B01D0022B01D1844203D1641CE4B2A542F1D8A542B5 +:402FC00003D1F7F751FF0A3043E06846447101718271694601A8FEF7A7FE06204443A019418868460088411A68460180F7F73CFF0546684601882846F7F7FAFE04466846C2 +:40300000018803222846F8F7EDF8002823D06846018801222846F8F7E5F8002812D0778B20463946EFF774FD7819401A01E0708B001984B2032221462846F8F7D3F80028B7 +:40304000F5D16BE0768B20463146EFF761FD4819801984B262E0718B2046EFF759FD481901E0708B001984B2032221462846F8F7B9F80028F5D151E0684643710171827101 +:40308000694601A8FEF750FE684661880088091868460180F7F7E8FE0546684601882846F7F7A6FE02902079022817D0768B6846018803222846F8F795F800281FD0684668 +:4030C000018801222846F8F78DF800280298314610D0EFF71DFDA819401A02E0F65BE6E7A01984B2032221462846F8F77BF80028F6D113E0EFF70CFDA8190818A9E731460A +:403100000298EFF705FD481900E0A01984B2032221462846F8F766F80028F6D12046FEBDF2220008CC1E000810B50B460621104C484302191179012906D0022904D0205A36 +:403140004008F3F777FE10BD0A498B4206D15188022903D3C8031904401807E0215A50880818C01A801EEFF7D3FCC803000C10BDF2220008FFFF0000F0B500200E4A84469E +:40318000014606460A4B0B4CFF20157809E006270A467A43A352121953801671491C5071C9B28D42F3D82076638326776046F0BDFFFF0000F2220008CC1E0008F8B50146E0 +:4031C0000020009026480078844688421AD9084606225043234F8646C0190279002A11D000220271204B7246BB52FF2643804671387F1C46401E3877387E354688422CD18A +:40320000002019E01948009027E0062201465143CA191279012A02D0022A06D00AE0795AA14207D20C46064604E0795A994201D20B460546401CC0B28445E6D8FF2E01D0A2 +:40324000304602E0FF2D03D0284600F029F804E0FF2038760020C04378830098F8BD0000CC1E0008F2220008FFFF000001001600F0B58C4600230FE00022C91A491E08E05C +:403280009600371884597D68AC4201DD85517C60521C9142F4DC5B1C61466345ECDBF0BDFEB5064615480621374606764F43C15B41830146002479181148009100780190C1 +:4032C00016E006200D49604345182879012801D002280AD1B44208D06888C95B421800984088101AEFF7FEFC6980641C0198E4B2A042E6D8009800214180FEBDF22200088D +:40330000CC1E00080348C078002801D000207047012070478025000810B5012200F046F810BD000010B5054802780121002A017002D10120F2F734FB002010BD0C02000888 +:4033400070B5144D297803200129287002D10120F2F726FBEDF7CFF8EFF7E0FA00246C60FF22813221460C48F1F7CCF8F02200210A48F1F7C7F80948F030C47004704470B4 +:40338000C47304734473EDF7B2F8EFF7B1FA002070BD00000C020008102300089024000810B5002200F002F810BD0000F8B515460C460646EDF79FF8EFF7B0FA264A1078E8 +:4033C000012808D01078022805D0EDF790F8EFF78FFA1120F8BD0C20464320483018C1788378994205D3EDF782F8EFF781FA1220F8BD46780C277E43416867687118266851 +:40340000A4684F600E608C60C178431C491CC1704178491CC9B219708078814201D1002018705068401C50601078012805D0EDF75EF8EFF75DFA0020F8BD02201070EDF7D6 +:4034400056F8EFF755FA002D03D00020F2F7A8FAF1E70120FAE700000C0200088025000810B51248002101704160FF2281321048F1F748F8F02200210E48F1F743F80D48DA +:4034800018220021F030F1F73DF80A482021F03081701421817306494160064901610649816006494161F2F761FA10BD0C020008102300089024000843EB0010456C0110C7 +:4034C000F8B50025164C01262F462078002815D0012813D0022802D003281CD11AE000F021F8EDF708F8EFF719FA6068002800D12670ECF7FCFFEFF7FBF90CE0ECF7FBFF7F +:40350000EFF70CFA2078002802D020780128F0D10125EEE72770002DD7D00020F8BD00000C020008FEB5214D214E0027FF24ECF7E2FFEFF7F3F900200C2141438919C97816 +:40354000002901D0044602E0401C0228F4D3FF2C2AD00C204443A41921780C2260685143081801460EC9029301920091076047608760E078401EE0702078401CC0B2207038 +:40358000A178884200D127706868002802D06868401E6860ECF7ABFFEFF7AAF9A1680029C4D068468847C1E7FEBD00000C0200088025000810B5830A082B04D03F2B05D0E9 +:4035C00004F078F810BD00F025F910BD01F0A8FB10BD10B50C460146207800F02BFE0028204603D003F0DFFA002010BD00F082FD1F2010BD38B504460020009069460520FF +:4036000000F071FD00280AD101200099052C07D010220A708C704870FF20FFF7DAFF38BD1A220A708870F6E710B5820A082A04D03F2A05D004F0F0F810BD00F015FA10BD8F +:4036400001F072FB10BD0000F8B5044640782578000205430020694608702846FFF7E4FF01282BD16946A0780978884226D022498D420CD0891D8D4209D0C91C8D4206D0E0 +:40368000C91C8D4203D01C4925318D4204D11221284600F0A1F80CE00022022805D32079E178000201430A05120D12212846FFF781FF204603F0C8FD1220F8BDA80A0F4E59 +:4036C00008280ED03F282A46314610D0E01C04F0EDF8204603F0B8FD3146284600F010F8F8BD2A463146E01C00F0CEF9F1E7E01C01F070FBEDE700000D2000009825000889 +:40370000F8B50D4604460020694608702E48871D844212D0BC4210D0F81C84420DD0C01C84420AD028481830844206D0401C844203D025482530844201D101200870A00A3F +:4037400008280ED03F280A46294620460FD004F0FFF806466846007800280BD001281FD116E00A462946204600F0C2F9F1E701F051FCEEE70022002D05D0687829780002FF +:4037800001430A05120D31462046FFF713FF07E0BC4201D13A2E05D03146204600F01CF83046F8BD68782978000201430805000DF5F7D2FC05460021204600F00DF83A21F5 +:4037C0002846FAF774F8EBE70D2000000148007B70470000A0210008F8B5054600200E4600906946082000F07EFC002801D00720F8BD009C0F202070A670FFF7E7FFE0700C +:403800002571280A6071042060702146FF20FFF7E0FEF8BDF7B584B00546002002900420694608718649874B681A0C22EE1806278D423BD010DC8449681A8D4230D006DC79 +:40384000002E28D0012E28D0052E13D128E006282AD009280ED120E0172829D006DC012824D0022819D0162804D11FE019281FD01A281DD07549284609688847694609794C +:40388000401869460871724928460968884769460979401805E0781C03E06846027107E005206946087103E00B20FAE7684607716846007902A9001D00F015FC002802D0E6 +:4038C000072007B0F0BD029C29462046059A00F001F90420694608715949491C681A8D420AD005DC5B48281806D005280BD103E0072801D0152806D10699A171069968462B +:40390000090AE17107710598002821D14C49491F681A8D425AD009DC4F4F002E20D0012E2FD0052E44D00D2E06D148E003285CD0072866D01B286FD0484B01AA1B682146C5 +:4039400028469847464B01AA1B682146284698476846007960702146FF20FFF73AFEB0E769460979387D6118887069460979000A6118C87069460879801CC0B20871797D55 +:403980005BE06946087908222018801C0021F0F7B9FDB87AF52108406946097961188870F87A6946C0070979C00F6118C87023E0F3F708FC05E069460879401C1FE0F3F779 +:4039C00021FC6946097961188870F4E7684600792118891C0698F3F700FC002801D06071B6E769460879401D09E06946087908212018801C03F05DF9694608790830087170 +:403A0000A6E76946087914492018801C08221831F0F76FFDF0E7FFE7124A694612680698904760716946087809796118887069460879401CC0B20871497820188170BAE726 +:403A40001A200000FEDFFFFF0F2000004C0200083C020008EBDFFFFFAC1E0008480200083802000858020008064AC0B21378834206D3401E1269C0B2105C087001207047E4 +:403A8000002070471402000830B4074BD2B21C78944206D39B689200D218403AD26B30BC104730BC704700001402000807484E21017007494160FF3139318160FF313931A5 +:403AC000C160FF313931016170470000140200084449001070B504460E2016460D462070FFF774FEA070E570280A2071667170BDF8B50D4D16460F46C1B22A780120914206 +:403B000010D88C00E868314620184038C26B38469047002806D16868314620184038C26B38469047F8BD000014020008F8B5054600260D4F69460620009600F0D4FA002802 +:403B400001D00720F8BD009C324639462046FFF7C1FFA571280AE071062060702146FF20FFF737FDF8BD00001F20000070B50446054640220021F0F7C5FC40222349284695 +:403B8000F0F7B7FC2249F522887A20341040C0060028207802DA3022104301E0CF2210402070887AC2070720002A2A7F01D0024301E0D208D2002A778A7A93060122002B96 +:403BC0000ADA6378C0252B436370A37808251343A370E3782B43E3708B7A5B060AD5A378F8252B43A370E3780343E370E07904231843E071C87AC00706D0E078F021084362 +:403C0000E07020791043207170BD0000654E0010AC1E000810B50022F3F776FB10BD10B5F3F7D0FB10BD002070470120704710B5F3F74AFC10BD0020704710B5F3F746FC66 +:403C400010BD0000044A0178D180407800020143D180002070470000A021000810B5F3F7E3FC10BD10B5F3F7FBFC10BD10B5F3F703FD10BD10B5F3F70DFD10BD38B5044669 +:403C80000020009069460E2000F02DFA002801D0072038BD00993E200870032088702078C870A07808716088000A487120798871A088000AC871A0790872E088000A4872F9 +:403CC000207A88722089000AC8720A2048700320FFF77FFC38BDF8B50546002000906946232000F000FA002801D00720F8BD009C3E2020700A2100F09DFA014601200029B2 +:403D000046D001260A20A07007462878E070A978217169880622090A61716878A0712879E0712046294608300C31F0F7E2FB0C20002E0ED0204629460E3006221231F0F790 +:403D4000D8FB20462946143006221831F0F7D1FB1820AA7921188A70EA88801C120ACA702A7A21188A702A89801C120ACA70AA7A21188A706A89801C120ACA70221869796D +:403D80009170401C607021463846FFF722FCF8BD0026A0700127B8E7F8B5044600200E46009015466946082000F09DF9002801D00020F8BD0099082008708E70CC70200A0D +:403DC00008714D7104204870FF20FFF702FCF8BD38B50C460021054600916946072000F082F9002801D0002038BD0099302008708D70CC70200A087103204870FF20FFF730 +:403E0000E8FB38BD38B50546002000906946112000F069F9002801D0002038BD009C3E2020700520A0702878E07028880822000A2071601D6968F0F75CFBA9680D200A7812 +:403E400062734978A173607021460520FFF7C1FB38BD38B5054600200C4600906946092000F041F9002801D0002038BD00991320087001208870CD70280A08714C71200A1F +:403E8000887105204870FF20FFF7A3FB38BD38B50546002000906946102000F024F9002801D0072038BD009C3E2020700420A0702878E070A87820716888000A60712878D1 +:403EC00000280BD0A01D08220021F0F71BFB0C20607021460420FFF77CFB38BDA01D0822A968F0F706FBF2E738B504460020009069460C2000F0F7F8002801D0002038BD69 +:403F000000990C20087020788870A078C8706088000A08716078487120798871A088000AC871A0790872E088000A487208204870FF20FFF74EFB38BD38B504460020009092 +:403F40006946062000F0CFF8002801D0072038BD0099572008708C70200AC87002204870FF20FFF736FB38BDF8B5064600200C46009015466946082000F0B5F8002801D0E2 +:403F80000020F8BD0099052008708E70CC70200A08714D7104204870FF20FFF71AFBF8BDFEB507460020009010480E46019015466946082000F097F8002801D00720FEBD27 +:403FC000009C324620460199FFF784FDA771380AE0710620002E03D1290A25726172082060702146FF20FFF7F4FAFEBD7B0C0000F8B5054600200E4600900C4F69460620F6 +:4040000000F071F8002801D00720F8BD009C324639462046FFF75EFDA571280AE071062060702146FF20FFF7D4FAF8BD7C0C000010B5F5F7E3F910BD10B5F5F73BFA10BDE5 +:4040400010B5F5F759FA10BD10B5F5F7BBFB10BD10B5F5F7D2FB10BD10B5F5F761FC10BD10B5F3F7C7FA10BD10B501220A70F5F743FD10BDF8B505460020074600900D4E2D +:404080006946142000F02FF8002801D00720F8BD009C3A4631462046FFF71CFD1022A01DA918F0F726FA142060702146FF20FFF790FAF8BD1720000010B5F3F799F910BD6E +:4040C00010B50029014601D00B2000E00220FFF780FA002010BD10B5FAF70CFC10BD10B5FAF730FC10BD0A4610B5C1B2104603F02BF810BD10B503F0C3F810BDF8B50546FD +:40410000C078AE78154C00020643A07C27468000C03FC019403004222946F0F7EAF9A07C238A8100C81940302A1D102B15D07D50A17C00234900C91980310E80A17C0B55CF +:40414000A17C491CC9B2A174102900D3A374218A491C2182114602F017FDF8BD9C2600083EB5134C0025E07C21460555E07CC0398000085803F09AF8E07C401CC0B2E074AF +:40418000102800D3E574208A401E20820948807A00280CD00095019511206A4602951081558129460A460020029B03F088F93EBD9C260008A021000870B5184C0025207AD2 +:4041C000002825D1F1F764F915488574C574058225726572A572A5821DE0A07A00280DD0401EA0720D4A0006410DC03A8818515C4068022907D0042907D101E01920F0E77C +:4042000003F03EF801E0FFF7ABFFE07A401EE072E07A0128E1D80348057070BD702700089C2600082802000810B5FFF7C5FF002010BD00001C4B13285A7A31D00EDC0E2803 +:404240002ED006DC052820D0082827D00C2829D11DE00F2824D0102824D11FE03E280AD004DC1A2817D030281CD112E0572814D0FF2817D114E0500614D5491E0120884023 +:40428000D98880B201420BD10CE0012006E0802004E0202002E0022000E00420024201D00120704700207047A021000838B505460020009069460920FFF715FF002801D03D +:4042C000072038BD009CFF2020700320A0702878E07028880422000A2071601DA91CF0F708F9072060702146FF20FFF772F9002038BD03B583B0002069460090888001AAA9 +:4043000004A91220F1F7F6F969460320FFF7EBFE00280ED10099FF2008700620887068468088C870000A087103204870FF20FFF750F905B000BD03B583B00020694600905B +:40434000888001AA04A91120F1F7D4F969460320FFF7C9FE00280ED10099FF2008700720887068468088C870000A087103204870FF20FFF72EF905B000BD000038B50446E1 +:4043800000200C4900900878401E087069460520FFF7A9FE00280CD10099FF20087002208870200ECC70087103204870FF20FFF710F938BD2802000810B50B4C617E0029BB +:4043C0000BD00A49884209D1F2F7D8FB607E022801D1F0F76FFF0020607610BD02F0F4FB607E00F031FF10BD5C210008C0FD0000FEB5044600200290607F0F46401CC6B298 +:4044000002A9301DFFF76FFE002801D00720FEBD029D21463931E81D019100902246637F1E3229392046F2F727FA0C49884204D12846FFF75FFE1220FEBD002208492846C0 +:40444000FFF748FB607FA871361D6E70022038702946FF20FFF7BDF80020FEBD01001600A9FD0000FEB5044600200290607F0F46401DC6B202A9301DFFF735FE002801D06D +:404480000720FEBD029D2246A91D481D019100902146637F1E3210312046F2F715FA0C49884204D12846FFF725FE1220FEBD002208492846FFF70EFB607FA872361D6E701C +:4044C000022038702946FF20FFF783F80020FEBD01001600A8FD0000F8B5044600200E46009069462420FFF7FEFD002801D00720F8BD009D002225492846FFF7EBFA2146CB +:404500002046AA1D20311030F2F700FA002804D02846FFF7EFFD1220F8BD2178A97521882846090AE97521681C30090C29762168090E69762179A976A188090AE976616843 +:40454000090C29776168090E6977217AA9772189090AE977A168090C0171A168090E4171217B001D8170A189090AC170E168090C0171E168090E41712420687002203070B4 +:404580002946FF20FFF725F80020F8BDADFD00000120704738B500200D46009069461020FFF7A1FD002801D0072038BD009C00220B492046FFF78EFAA11D0020F6F760FC6E +:4045C00021460C310120F6F75BFC10206070022028702146FF20FEF7FCFF002038BD0000A1FD00007CB500200D46009069460620FFF779FD002801D007207CBD009C002243 +:404600000B492046FFF766FA01A8F1F7D7F868460079A07168464079E07106206070022028702146FF20FEF7D4FF00207CBD0000A2FD000010B5012008700024034803F064 +:40464000BFFA002800D00C24204610BDF342011010B5012008700024034803F097FA002800D00C24204610BD37430110F3B5044683B000200190207D002601461131CAB20B +:40468000332802D9122005B0F0BD01A9101DFFF72AFD002801D00720F5E7019D002232492846FFF717FA2068FAF7A2FE277DAF710520009009E080194019801C394602F016 +:4046C000F8FA0836083FF6B2FFB20098082FF2D880194019801C394602F0EBFA217D009822790818C1B268188270A288091D120AC2706268C9B2120C02716268120E427186 +:40470000227A681882702289091D120AC270A268C9B2120C0271A268120E4271227B68188270A289091D120AC270E268C9B2120C0271E268120E4271227C68188270228A7C +:40474000091D120AC2702269120C02712269120E427169700498022101702946FF20FEF738FF00208FE70000ACFD0000FEB50F460546FF2069460871002000902888F4F764 +:40478000EBFC060027D0F5F760FB002823D069460720FFF7A8FC002801D00720FEBD009C00220E492046FFF795F92878A07128880223000AE07101AAFF213046F5F7ABFBB5 +:4047C000207207206070022038702146FF20FEF700FF0020FEBD0220FEBD0000AAFD000010B500240C708179002904D0012905D01224204610BDF8F7C9FAFAE7F8F7FEFA4F +:40480000F7E70000F8B505460F460088F4F7A4FC04006FD0F5F719FB00286BD00020009069460620FFF75FFC002801D00720F8BD009EF6F7A1FA2046F2F7EAFC00283FD156 +:40484000FAF7FAFC5E210A5B6179F3F723FC2246A0320146537D2848012B837A05D09B060DD5B0231B595B890AE09B0603D5B0231B595B8900E01B23DB00703302E01B23D3 +:404880009B003C33127D807A9BB2012A05D080060DD5B0200059008B0AE0800603D5B0200059008B00E01B20C000703002E01B2080003C3082B2103189B22046F9F770FE08 +:4048C00068886034E080F6F773FA00220B493046FFF700F92978B17129880620090AF1717070022038703146FF20FEF772FE0020F8BDFFE70220FBE7AC1E0008B0FD0000AD +:4049000010B500240C70F0F787FF0349884200D11224204610BD000001001600F8B504460E460088F4F718FC05002AD0F5F78DFA002826D0A178A878FDF72CFC002801D08E +:404940001220F8BD0020009069460620FFF7CBFB002801D00720F8BD009D00220A492846FFF7B8F82078A87120882946000AE8710620687002203070FF20FEF72AFE0020CD +:40498000F8BD0220F8BD0000B2FD0000F8B504460F460088F4F7E0FB050043D0F5F755FA00283FD00020009069460620FFF79BFB002801D00720F8BD2879009E09280CD066 +:4049C0002389E288A1886088FDF776F8002806D03046FFF78FFB1220F8BD0C220FE0E87E810604D5A97D890601D41A2207E0C00604D42046FCF7EAFF024600E023220A4923 +:404A00003046FFF767F82178B17121880620090AF1717070022038703146FF20FEF7D9FD0020F8BD0220F8BDB1FD0000024600200870024912784A7370470000A021000855 +:404A4000F8B504460F460088F4F786FB060026D0F5F7FBF9002822D00020009069460620FFF741FB002801D00720F8BDA178B078009DF8F7C1FB00220A492846FFF72AF8F0 +:404A80002078A87120882946000AE8710620687002203870FF20FEF79CFD0020F8BD0220F8BD0000ABFD0000F3B5044683B000200090054621786A46517101202056032617 +:404AC0001071002809D0042807D0821D05D0921D03D0121D01D0143007D101290FD001A8F0F7C0FE2949884200D112256946301DFFF7F9FA002830D0072005B0F0BD608806 +:404B0000FF2811D0F4F728FB070000D10225F5F79CF9002806D0002DE8D1EDF7FFFE6078387317E00225E1E7EDF7F8FE0020184B184A08E0D027196A4743C91901D0677874 +:404B40000F73401CC0B211788142F3D8104861784030C170EDF7CCFEC8E7009E2A460E493046FEF7B7FF2078B071A078F07160880221000A307207207070049801703146A5 +:404B8000FF20FEF726FD2846B7E70000010016005C210008CC1E0008A5FD000010B5044602200870F7F7D8FE207800F04DFB10BD7CB505460020184C009020780E461228C2 +:404BC00007D22979154B01A82A68F0F727FF002801D00C207CBD20786946401C20700620FFF781FA002801D007207CBD009C00220B492046FEF76EFF2879A071684600795E +:404C0000E07106206070022030702146FF20FEF7E0FC00207CBD0000280200087D430110C1FD0000F8B505460020154C009020780E4600280FD06878F0F776FF002802D1C7 +:404C40002078401E207069460520FFF74CFA002803D00720F8BD0C20F8BD009C002209492046FEF737FF2878A07105206070022030702146FF20FEF7ACFC0020F8BD0000E5 +:404C800028020008C2FD000038B500200D46009069461020FFF727FA002801D0072038BD009C00221C492046FEF714FF1B48016B0978A171016B0988090AE171016B897846 +:404CC0002172016B4988090A6172016B0979A172016B8988090AE172016B89792173016BC988090A6173016B097AA173016B0989090AE173016B897A2174006B214640896D +:404D0000000A60741020607002202870FF20FEF760FC002038BD0000A7FD00005C21000810B502F0C7FC10BD10B5264B0022C41A98423CD01FDC244BC41A98423CD011DCAF +:404D4000224C031BA0422AD007DC214BC01822D0012822D0C92832D12EE0012B2CD0022B2DD129E02300F5F7BFFD092A271618272A2A181E2A002300F5F7B6FD18211B1ED7 +:404D80001E0D1D151E13212121212121212121212113170F132104220EE002220CE007220AE0012208E0032206E0052204E0152202E0302200E00A220A70012010BD002036 +:404DC00010BD0000ACFD0000A3FD0000A0FD00009A03FFFF10B53D4BD41A9A425AD01CDC3B4BD41A9A4240D00FDC3A4C131BA2422FD005DC384BD31825D0012B20D125E0E4 +:404E0000012B29D0022B1BD12CE0641F2300F5F76BFD062F3217383B3E17092C52D007DC2300F5F761FD080D40430D0D461C490D152C23D0162C30D0172C31D0182C3ED0CB +:404E400000F0B2FF10BD00F022FD10BD00F040FC10BD00F053FC10BD00F026FD10BD00F02AFB10BD00F0B0FC10BD00F0FEFA10BD00F04CFB10BD00F010FB10BD00F051FBFB +:404E800010BD00F039FA10BD00F016FA10BD00F0E5FA10BD00F031FB10BD00F045FB10BD00F053FB10BD00F08FFA10BD00F03CFA10BD00F0E5FA10BD00F0F4FA10BD00F06B +:404EC00019FB10BD00F046FB10BD0000ABFD0000A0FD000049FD00009A03FFFF3EB50020009001900290012008700D4602A90C20FFF7F9F8002801D007203EBD029C002262 +:404F000010492046FEF7E6FD01A96846F2F7D6FB0098A071010AE171010C2172000E60720198A072010AE172010C2173000E60730C206070022028702146FF20FEF749FB42 +:404F400000203EBDB3FD0000F7B582B006460027012000971070154669460620FFF7C3F8002802D0072005B0F0BD009CF00701D01220F8E73A4620460399FEF7ABFD084895 +:404F800030180068A071000AE07106206070022028702146FF20FEF71CFB0020E3E7000000103C4010B50A4600880249FFF7CCFF10BD000067FC0000FEB5064600270120FD +:404FC000009708700D4669460820FFF78CF8002801D00720FEBD009C3A460D492046FEF779FD01AA31460520F0F784FB0198A071010AE171010C2172000E607208206070B4 +:40500000022028702146FF20FEF7E3FA0020FEBD49FD000070B5674B0E460024C11A664D984270D020DC654BC11A984257D013DC634BC11A984238D007DC6249411825D088 +:40504000012928D0E3296ED12AE0012932D056293BD0572967D13DE00B00F5F745FC08A6454A4F555F656AA60C240B00F5F73CFC1A9D6B70752B2B7A267F93989D9D9D9DC7 +:405080009D9D9D9D9D9D9D5184898E9D1146304600F09AF816E011463046FFF783FF70BD11463046FFF788FF70BD1146304600F0BFF870BD3046F7F769FE04E011463046D1 +:4050C0006A682EE00446204670BD11463046FFF787FBF7E711463046FFF75CFAF2E711463046FFF77FFAEDE711463046FFF7B0FAE8E711463046FFF79DFAE3E711463046A1 +:40510000FFF7D2FCDEE719E011463046FFF7F8FBD8E711463046FFF741FDD3E71146AA6830469047CEE740E011463046FFF79AF9C8E711463046FFF75BF9C3E7114630469F +:40514000FFF714FBBEE711463046FFF779FCB9E711463046FFF78AFAB4E711463046FFF7BBF9AFE711463046FFF74CFBAAE711463046FFF7D3FBA5E711463046FFF718FD2E +:40518000A0E711463046FFF74DFD9BE711463046FFF74CFC96E711463046FFF79FFE91E71146304600F01EF88CE7314600F01EFE88E70000AAFD000028020008A2FD0000C9 +:4051C0004AFD00009A03FFFF0188CA0701D012207047034A40888918086000207047000000103C40F8B5064600200090012008700D4669460C20FEF776FF002801D007203E +:40520000F8BD009C002209492046FEF763FC3078F2F75CFAA07105206070022028702146FF20FEF7D6F90020F8BD0000B4FD00000EB5017800914068019002AA69460420F3 +:40524000F0F758FA00200EBD38B505460020009069460520FEF747FF002801D0072038BD009C002207492046FEF734FC064821464576A57105206070FF20FEF7AAF9002013 +:4052800038BD0000C0FD00005C21000803480249416081607047000091450110280200080348024941600349816070478D49011028020008894C011070B50D4604460146AC +:4052C00010222846EFF715F92146284610310D221030EFF70EF9214628461D3104223930EFF707F92120225C214628466A7722311E30EFF7FEF870BD70B50D4604460146E8 +:4053000010222846EFF7F5F82146284610310D221030EFF7EEF8627F214628466A771E311E30EFF7E6F870BD70B50C46054601461022A018EFF7DDF829462046103110228E +:405340002030EFF7D6F82022A818C1780902216083781943090221604078014308022060A95C0843242120606818C2781202626083781A4312026260407802431002606057 +:40538000695C0843282160606818C2781202A26083781A431202A260407802431002A060695C08432C21A0606818C2781202E26083781A431202E260407802431002E0601D +:4053C000695C0843E06070BD10B5C27812020A6083781A4312020A6043781A4312020A6003781A430A6002790A75037A1B024B60C47923431B024B60827913431A024A6044 +:4054000043791A434A60037B1B028B60C47A23431B028B60827A13431A028A60437A1A438A60037C1B02CB60C47B23431B02CB60827B13431A02CA60437B1A43CA60037D09 +:405440001B020B61C47C23431B020B61827C13431A020A61407C02430A6110BD427812020A80007802430A80704770B50C460546014606222046EFF73CF8A879A07170BDFA +:40548000427812020A8003781A430A80C27812024A80807802434A80704702780A70407848707047427812020A8003781A430A80807888707047427812020A8003781A43B0 +:4054C0000A80C27812024A8083781A434A80427912028A8003791A438A80C2791202CA8083791A43CA80427A12020A81007A02430A817047007808707047427812020A8095 +:4055000003781A430A8080788870704702780A7042784A70C27812024A80807802434A807047007808707047C27812020A6083781A4312020A6043781A4312020A600378DE +:405540001A430A6000790871704702780A7040784870704700780870704710B50B460178401C197001460622581CEEF7C2FF10BD034610B5084608221946EEF7BAFF10BDDF +:40558000427812020A8003781A430A80C27812024A8083781A434A80427912028A8003791A438A80C2791202CA8083791A43CA80427A12020A81037A1A430A81C27A1202EF +:4055C0004A81837A1A434A81427B12028A81007B02438A81704770B5054640780C46000208802978062208432080E87800026080A978084360802879207168796071A91D6D +:40560000A01DEEF776FF287B2076A87B0002A081697B0843A081287C0002E081E97B0843E081A87C00022082697C08432082287D00026082E97C08436082A87D0002A0826F +:40564000697D0843A082287E0002E082E97D0843E08270BD7047427812020A8003781A430A8080788870704770B50D460446014610222846EEF73DFF214610221031A81811 +:40568000EEF737FF70BD034610B5084640221946EEF72FFF10BD427812020A80007802430A80704710B50B4641780A021A800178801C0A431A8001461022981CEEF719FFB4 +:4056C00010BD427812020A80007802430A807047427812020A80007802430A807047427812020A80007802430A8070477047427812020A80007802430A80704700780870DE +:405700007047427812020A80007802430A807047427812020A8003781A430A80807888707047007808707047427812020A80007802430A80704710B50B460178401C19708A +:4057400001460622581CEEF7D4FE10BD10B502780B460A701F2A03D8411C581CEEF7C9FE10BD00780870704770B5054640780C46000208802978062208432080E878000289 +:405780006080A978084360802879207168796071A879A071E91DE01DEEF7ABFE687B6073A87BA07370BD0022835C0B70521C491CD2B2082AF8D37047034610B508460522F3 +:4057C0001946EEF796FE10BD034610B5084606221946EEF78EFE10BD034610B5084606221946EEF786FE10BD02780A7040784870704702780A71827812020A8043781A430A +:405800000A80027912024A80C3781A434A8042794A7180798871704710B502780B460A701F2A03D8411C581CEEF763FE10BD70B5054640780C4600020880297808220843D8 +:405840002080A91C201DEEF754FEE87A102200026080A97A08436080294620460C310C30EEF747FE70BD02780A7042784A70807888707047427812020A8003781A430A801D +:40588000C27812024A80807802434A807047427812020A8003781A430A80C27812024A80807802434A80704702780A70027912024A60C3781A4312024A6083781A43120293 +:4058C0004A60407802434A60704710B504460088F2F774FB00280AD0A07815280FD008DC05280CD013280AD0142806D107E0022010BD1A2803D03B2801D0122010BD002028 +:4059000010BD012070470078012801D912207047002070470020704710B50446012008702088F2F74BFB002822D06188A08881421CD8114A891F914218D2511D884215D86A +:4059400021890D4B0A460A3A1B1F9A420ED2E288FF23F4339A4209D8521C4243C9005000814203D9A0896189884203D2122010BD022010BD002010BD7B0C00000020704795 +:4059800010B501220A700179037E0A46194303292FD8002A02D1417903292AD8018842888A4226D8154B091F994222D2042A20D38289C1898A421CD8114B921F9A4218D249 +:4059C0005A1D914215D8428A0D4C13460A3B241FA3420ED2038AFF24F434A34209D85B1C4B43D20059008A4203D9C18A808A814201D2122010BD002010BD0000FD3F00001C +:405A00007B0C0000002070470020704710B50088F2F7D4FA002801D0002010BD022010BD10B50088F2F7CAFA002801D0002010BD022010BD10B50088F2F7C0FA002801D0A0 +:405A4000002010BD022010BD10B501220A700088F2F7B4FA002801D0002010BD022010BD002070470078272801D912207047002070470078012801D9122070470020704781 +:405A800010B501790388428804291BD801290AD0934217D80124A403A24213D8202B11D3827B032A0ED8012901D0042902D18179032907D84179032904D8407B410701D0FA +:405AC000C00800D0122010BD00781F2801D9122070470020704741780A09817812011143C2780A430179114342790A438179C0791143084300D01220704701794A090AD1FA +:405B0000027843781A438378C07803431A430A4301D0002070471220704700207047017840780143012901D91220704700207047017901290FD8018842888A420BD8084B2F +:405B4000091F994207D2042A05D34179032902D88079032801D912207047002070470000FD3F000010B501220A700088F2F726FA002801D0002010BD022010BD00207047EA +:405B80000178272902D88078072801D9122070470020704710B50088F2F710FA002801D0002010BD022010BD0120704710B50088F2F704FA002801D0002010BD022010BD8B +:405BC00010B504460088F2F7F9F9002804D0A078012803D9122010BD022010BD002010BD0020704710B504460088F2F7E7F9002804D06088002803D0002010BD022010BD4D +:405C0000122010BDF8B50E460021054600910120307069460820FEF766FA002801D00720F8BD2868009C056800220A492046FDF751FFA571280AE071280C2072280E607286 +:405C400008206070022030702146FF20FDF7C1FC0020F8BD26FD000010B50020F1F7C2FC002010BDC27812020A6083781A4312020A6043781A4312020A6003781A430A605D +:405C800002790A71407948717047C27812020A6083781A4312020A6043781A4312020A6003781A430A60007908717047C27812020A6083781A4312020A6043781A431202FC +:405CC0000A60007802430A60704710B5C27812020A6083781A4312020A6043781A4312020A6003781A430A6002790A71182A01D918220A71002205E083188C185B79521CE2 +:405D00002372D2B20B799342F6D810BDC27812020A6083781A4312020A6043781A4312020A6003781A430A60C27912024A6083791A4312024A6043791A4312024A60007990 +:405D400002434A60704700003EB500200290012008700D4602A90820FEF7C5F9002801D007203EBD6846029CEFF7EAFA00220D492046FDF7AFFE68460078A0716846407819 +:405D8000E07168468088207268468078607208206070022028702146FF20FDF71AFC00203EBD00002FFD00000F4B00B5D2181300F4F79AFD0B070A0D090916101309070A2D +:405DC0000900FFF762FF00BDFFF77FFF00BDFFF749FF00BDFFF76AFF00BDFFF797FF00BD0078087000BD0000E002FFFF10B50C4601460F4B0020C9180B00F4F775FD0D0C2E +:405E00000D0C080C1717171717170C12170011462046FFF7F7FE10BD11462046FFF71CFF10BD11462046FFF78FFF10BD012010BDDD02FFFF70B5054600780C468872691CD4 +:405E40000622201DEEF755FB2046E91D10221B30EEF74FFB29462046173110220B30EEF748FB70BD704710B50B460178401C197001460622581CEEF73CFB10BD10B50B4684 +:405E80000178401C197001460622581CEEF731FB10BD704710B50B460178401C197001460622581CEEF725FB10BD007808707047427812020A80007802430A80704770B5C1 +:405EC000054600780C460870691C0622601CEEF710FBE879E07170BD7047002070470000F8B50D46114914781646411808D0104807460E37007D012908D002290BD10CE0C0 +:405F0000FAF7FEFA29198870641C03E02A19921C012305E0E4B23470F8BD2A19921C00233946FAF7C7FA6871A41DF3E7D6DFFFFFA02100080649401805D0012805D0022819 +:405F400003D00020704701207047062070470000D6DFFFFF10B50022F9F744FCC0B210BD10B5FAF7D3F810BD10B5FAF795FA10BD10B5FAF791FA10BD0020704710B5FAF7BE +:405F8000C5FA10BD10B5FAF7C1FC10BD10B5FAF7D5FC10BD10B5FAF7EFFC10BD10B500F025F810BD014A12681269104734020008014A1268D269104734020008014A126885 +:405FC000926A104734020008014A1268D26C104734020008014A1268926D104734020008014AD2685268104734020008807A012801D912207047002070470078012801D913 +:40600000122070470020704700207047002801D000207047122070470078012801D91220704700207047000000880449401E884201D312207047002070470000B8A10000EB +:406040000178012902D8C079012801D91220704700207047014A12681268104734020008014A12689269104734020008014A1268D26B104734020008014A1268126B10474E +:4060800034020008014A1268526A104734020008014A1268D268104734020008014A1268926C104734020008014A1268526D104734020008014AD2681268104734020008F3 +:4060C00004480349016004494160044981607047084F001034020008D95E0110DB5E011006480549016006494160064981600249C031C16070470000A84E00103402000828 +:40610000E15E0110355F0110014A12689268104734020008014A1268126A104734020008014A1268526C104734020008014A1268926B104734020008014A1268D26A104779 +:4061400034020008014A12685269104734020008014A1268126D104734020008014A1268D26D104734020008014AD268926810473402000870477047427812020A80037805 +:406180001A430A80C27812024A8083781A434A80427912028A80007902438A807047427812020A8003781A430A80C27812024A80807802434A8070470749401805D0012830 +:4061C00005D00D2805D0002070470220704704207047082070470000DEDFFFFF0020704770470000FEB50D4627491646147840180022002802D00C2844D115E06B461A71C1 +:4062000001A96846FBF75EFA6B461988281981701988A41C090AC170E0B25A8829188A705A88120ACA702BE069460A7202A96846FBF732FA6946898828198170694689884D +:40624000A41C090AC170E0B269462A18C98891706946C988801C090AD170C0B269462A180988917069460988801C090AD170C0B2694649882A18917069464988090AD17027 +:40628000801CC4B23470FEBDDDDFFFFF38B504460020009069460F20FDF725FF002801D0072038BD00993E200870072088702078C8702088000A0871A07848716088000A75 +:4062C00088712079C871A088000A0872A0794872E088000A8872207AC8722089000A08730B2048700720FDF774F938BD10B5FBF7D3F910BD10B5FBF7E5F910BD10B5FBF71D +:40630000F1F910BD10B5FBF713FA10BD014A1268926A104744020008014A12681269104744020008014A12685268104744020008014A1268D269104744020008002801D008 +:406340000020704712207047002801D0002070471220704710B504460088F1F72FFE002816D0618808461B38E1280FD2A0880A4A90420BD8FF224932904207D3074A126B2F +:406380009388994202D8D188884203D9122010BD022010BD002010BD480800005C21000810B50021002815D0028813461B3BE12B0FD24088084B98420BD8FF2349339842F5 +:4063C00007D3064B1B6B9C88A24202D8DA88904200D91221084610BD480800005C210008014A1268526A104744020008014A1268D268104744020008014A1268126810477A +:4064000044020008014A1268926910474402000804480349016004494160044981607047804F001044020008E1610110DD6101100448034901600449416004498160704742 +:40644000B04F001044020008E5610110B9610110014A1268D26A104744020008014A12685269104744020008014A12689268104744020008014A1268126A10474402000828 +:4064800002780A7042784A7080788870704702780A7042784A7082788A70C078C8707047427812020A80007802430A80704702780A7042784A708078887070474278120217 +:4064C0000A8003781A430A8082788A70C278CA7002790A7182791202CA8040790243CA8070470000014A1268926A104750020008014A1268526B104750020008014A126890 +:406500005268104750020008014A12681269104750020008014A1268D2691047500200080178272907D84178012901D0022902D18078012801D912207047002070470178C0 +:40654000272907D8C178012901D0022902D18078072801D9122070470020704710B50088F1F72CFD002801D0002010BD022010BD017803290FD84278032A0CD8807803284C +:4065800009D8CB0701D1002A05D0890701D4002801D0002070471220704710B504460088F1F70CFD00280BD0A078032812D8E17803290FD82279032A0CD8C30702D003E0EA +:4065C000022010BD002905D0800701D4002A01D0002010BD122010BD014A1268526A104750020008014A1268126B104750020008014A12681268104750020008014A126891 +:40660000D268104750020008014A1268926910475002000804480349016004494160044981607047E04F00105002000835660110D166011000207047044803490160044988 +:4066400041600449816070471C50001050020008596601108D27011038B504460020009069460A20FDF73FFD002801D0072038BD00993E2008700C208870A078C8702078A9 +:4066800008712088000A4871E07888712079C871062048700C20FCF79CFF38BD014A1268D26A104750020008014A1268926B10475002000800207047014A12685269104773 +:4066C00050020008014A1268126A1047500200080020704710B50B48017A01290ED0C17A00290CD001210172407A064BC000C03BC1184A884968185CEEF7CEFE10BD0021D2 +:40670000017210BD7027000870B503461448C47A192C0BD3022B05D0042B02D10846FDF7E9FC70BD0846FDF71BFD70BD847AE5000B4CC03C6355837ADB001B195960817AC2 +:40674000C90009194A80C17A491CC172817A491CC9B281721929E8D30021817270BD00007027000810B50F4CE17A002918D0617A2246C900C03A515C022904D0042904D1A6 +:40678000FDF7B8FC01E0FDF7EBFCE07A401EE072607A401CC0B26072192801D30020607210BD000070270008F7B5A14C84B02046E030039009380090401E0E46C0340190A0 +:4067C000E07B354601281CD0A07B012836D0A18A4A19082A02D90822511A8DB2002D0CD0002833D0A18A206A4018401E2A460499EDF77FFEA08A4019A082207C012829D085 +:406800002FE0A08A618A42198A4204D280B28019A08207B0F0BD081A0021A18280B26182E173002807D004992A1A091815460498EDF75FFEAEB2002EC2D1EAE7618AA28AD5 +:40684000891A8DB2B542C9D93546C7E7A18A01980818CBE700F068F90028DAD000202074E073608A002802D0A18A8142D1D3A08A0028CED000200290A07D01280CD0022850 +:4068800065D00220FCF7B6FE012020740021E173A1736182A1821DE0A08A03281CD9A07B002824D100270098F0F704F9002801D10420A0823A460120039900F00EF90128D7 +:4068C0000BD00420FCF796FE012020740021A173A1826182FCF78EFE9EE00120A073A28A012A04D9521E206A0099EDF702FE216A8F78381D6082502F10D9487802020878D1 +:40690000012110430022FCF755FEA07B012802D1216A00F0F8F80020A07331E0A28A82427AD3121A1206120EA28206D00918491E0198EDF7DEFD01200290FA1C216A0120C4 +:40694000069B00F079F80020A073608260E0A08A052861D33648D130C1798279080210430205A07B120D002815D10220039900F0B4F8012807D00520FCF73CFE009820620F +:406980000120E07348E00120A073A28A206A521E0099EDF7AEFD216A264AC8788F7800020743781D80B26082127DBA4213D20820FCF720FE012020740027A7826782E77391 +:4069C000FCF718FEA07B012803D10220216A00F09AF8A77320E0A28A82421DD3121A1206120EA28206D00918491E0198EDF781FD01200290E07B002806D13F1DBAB2216A0C +:406A00000220069B00F018F80020A0736082E0730298012800D12DE7B54200D3F9E60498721B16464119EDF764FDB6B2C8E60000B0260008AC1E00083EB5044600200D4640 +:406A4000009001900290012C14D0022C11D108206946088100954A81002B69460EC90BD0002000F0E7FC002803D02946204600F04AF83EBD1220EBE7002000F020FDF2E7FC +:406A800070B5047800250E2C03D10179C57809020D43FFF767FE0E2C02D12846FDF78CFC024800210172FFF715FE70BD7027000810B5FFF729FEFFF70DFE10BDF8B5154633 +:406AC00007465C1B2046069EEDF713FDA81982B221463846FFF7ECFFF8BD10B50B46012802D002280BD103E0084600F013FB03E01146184600F066FB0006000E01D0002030 +:406B000010BD012010BD10B5012805D0022802D1084600F0E1FB10BD084600F095FB10BD10B5FCF767FD10BDFCB514A00068009013A0144E0068019031460020C0316C46CA +:406B4000012711E03318C0339A7D255CAA4209D001AD2D5CAA4205D000228A829A7D012A00D18F82401C80B28A8A8242EAD890B2042801D00020FCBD0120FCBD01030C00ED +:406B800001091000B026000808B50B46C17882780902891889B20091014604220220FFF78DFF002008BD3EB54178002217236C46029223810090891C61810120029B0099CE +:406BC00000F07DFC00203EBD06480021017241728172C17201748182016241828173C1737047000070270008002210B511461046FCF7E0FC10BD0EB50021019102911921C7 +:406C00006B461981009001205881002A69460EC902D000F00FFC0EBD012000F050FC0EBD10B5FFF7D1FF034B034A04490448EEF721FC10BDF76B0110A9670110396A011039 +:406C4000E96B011010B50189032913D0172907D018290BD0192902D10068FFF711FF10BD428901680420FFF723FF10BD0068FDF745FA10BD03C800F015F810BD3EB500227F +:406C800003236C460292238101910090628169460EC9012000F0CEFB002801D000203EBD01203EBD10B5052802D10020EFF78AFD10BDF8B50E460546F8F7C6FB0023009061 +:406CC0006C46AB20E15C002900D1E0545B1CDBB2042BF7D32A463146204600F001F8F8BDF7B58AB03A480890001D054606900898019038480F460168069800910291039002 +:406D0000012600241835042233A10898EDF7F1FB0099069880310A7902704979417006980422801C0A99EDF7E4FB8E206946087530460899303048702819049001A800F0C4 +:406D40004FF8002021186A5C002A01D130226A54401CC0B21428F5D31434761CF6B2E4B2032EE5D9281D029000200390019568460475174E0024082F1DD9082730190490BF +:406D800001A800F02DF8002030222118735C002B00D17254401CC0B21428F6D36946097D3120685469461434087DE4B2401CC0B2087500212954BC42E0D3002004E00C996F +:406DC000325C0A54401CC0B2B842F8D30DB0F0BD942700085C0200083030303000000000F0B5BD4E07463446C56885B04034BB482060BB486060B948C043A060B848C04327 +:406E0000E060B8482061387C362801D8402104E0762801D8802100E0C021019104280AD23968042208180021EDF76CFB3A7C3968802088541CE088280DD279680422081816 +:406E4000001F0021EDF75EFB3A7C796880208918203908770CE0B9680422081888380021EDF750FB3A7CB96880208918A039087600200090387C694640098870387CC0004B +:406E8000C8700198800903900020D2E00020844602988001864660467146800009183A7CC9B28A421AD3042901D23A6806E0882902D2091F7A6801E0BA68883951180A7894 +:406EC000120232504B781A43120232508B781A4312023250C9780A43325016E0019A083A8A4201DB00210FE06A4611780902315052781143090231506A469278114309022D +:406F000031506A46D278114331506046401CC0B284461028BFD32068286060686860A068A860E068E86020692861002084460007000F86466046102817D37046C01E000778 +:406F4000800E3158704608300007800E305841407046801C0007800E32587046800033585A4051401F22D14131506046142809D26968AA6808461040EA688A431043E0614C +:406F800059481EE0282807D2A96868684840E9684840E061554814E03C280BD2A868EA680346696810430840194611400843E0614F4806E0A96868684840E9684840E06161 +:406FC0004C48A061E0692969A269411828681B23D8411018091870468000305808186061E8682861A868E86068680221C841A86028686860606928606046401CC0B28446D2 +:40700000502894D320682968401820606068696840186060A068A9684018A060E068E9684018E06020692969401820610298401CC0B203990290884200D227E7F968207800 +:40704000C8702088F968000A88702068F968000C48702068F968000E0870F9682079C871A088F968000A88716068F968000C48716068F968000E0871F968207AC872208976 +:40708000F968000A8872A068F968000C4872A068F968000E0872F968207BC873A089F968000A8873E068F968000C4873E068F968000E0873F968207CC874208AF968000A95 +:4070C00088742069F968000C48742069F968000E087405B0F0BD0000F02700080123456789ABCDEFF0E1D2C39979825AA1EBD96EDCBC1B8FD6C162CA30B500224B1E4C083D +:4071000005E0815CC55C8554C1545B1E521C9442F7DC30BD10B5044608484068EFF75CF92060002807D00649087B002801D0401E0873002010BD034810BD0000600200082D +:40714000A0210008FFFF000070B50A4D0446302905D8E868EFF740F92060002805D1A868EFF73AF92060002801D0002070BD024870BD000060020008FFFF000010B5044682 +:4071800005480068EFF728F92060002801D0002010BD024810BD000060020008FFFF000010B50446880005490858EFF715F92060002801D0002010BD014810BD70280008D9 +:4071C000FFFF000010B504460846F0F71FFF064980000858EFF700F92060002801D0002010BD024810BD000050280008FFFF000010B50446880005490858EFF7EDF8206096 +:40720000002801D0002010BD014810BD60280008FFFF000010B50446880005490858EFF7DBF82060002801D0002010BD014810BD80280008FFFF000010B5FCF711F9FCF7E7 +:4072400071F8002010BD0000014610B509484068EFF752F9002801D0074810BD0749087B401CC0B20873042801D904200873002010BD000060020008FFFF0000A02100088E +:4072800070B5084C05460146E068EFF735F9002806D02946A068EFF72FF9002800D0024870BD000060020008FFFF0000014610B502480068EFF720F910BD00006002000819 +:4072C0000246880010B5034908581146EFF714F910BD00007028000810B504464078217800020843F0F792FE0349800008582146EFF702F910BD00005028000802468800E1 +:4073000010B5034908581146EFF7F6F810BD0000602800080246880010B5034908581146EFF7EAF810BD000080280008F8B5040076D03C4E20783075A078F07520797075BE +:407340006079B0753546A07B20352870EBF740FBC0B2022801D0032805D1707D042802D12079401E707500242EE081070DD08107890F401A0C3082B22B48A700717D381860 +:40738000EFF750F800284BD101E00830F3E726482022103038180221EFF744F800283FD121482022203038180221EFF73BF8002836D11D484022303038180221EFF732F84B +:4073C00000282DD1641CE4B22878A042307DCCD881070BD08107890F401A0C3082B2B17D1248EFF71FF800281AD101E00830F5E70E4850220421001DEFF714F800280FD1A0 +:407400000A48482201210830EFF70CF8002807D10648302208210C30EFF704F8002800D00348F8BDAC1E00085028000860020008FFFF00001FB50446EBF770FA01A9204639 +:40744000FBF76AFF0446EBF753FA204604B010BDF8B5154CA068EFF7FDF8E068EFF7FAF86068EFF7F7F82068EFF7F4F800240F4F0F4E14E0A5007859EFF7ECF80B481030A3 +:407480004059EFF7E7F8094820304059EFF7E2F8064830304059EFF7DDF8641CE4B23078A042E7D80020F8BD6002000850280008CC1E000810B5FBF743FF002010BD1FB5A8 +:4074C0000446EBF72BFA01A92046FBF769FF0446EBF70EFA204604B010BDF8B5054600202870F02316466B800246034607E00C245C439F0064187F195B1CDBB27C60B342DD +:40750000F5D3344604E0A1004919641CE4B24A60052CF8D3002408E022460121284600F007F8002803D1641CE4B2B442F4D3F8BD70B50B460546002411461846FAF70CFE5A +:40754000FF2810D0800040194268FF2111704268002151704268917042681181426851814068416000E0014C204670BD0100160010B50C4B89001C7800220818002C01D059 +:4075800041680A8144686189002901D0491E618140688178002902D0491E817000E042701A7010BD70020008F0B500230746FF209C461C461E4D1A4621E0CE071CD09E00C4 +:4075C000F6197668B6467678A64201D934461846002C11D176463678AE420DD8AE4208D105460120A840104301229A400243D2B200E00022184635465B1CDBB2490800293E +:40760000DBD1002C10D1002A0ED0D30708D08B00DB195B681B89634502D3D8B284460846491CC9B25208F0D1024A01211170F0BDFFFF00007002000803460020052906D254 +:40764000002B04D08900C91849680A70704701487047000001001600034610B5002005290ED2002B0CD08900C9184B685C78944208D25A70802A02D1496806228A7010BDDD +:40768000024810BD0148FE3010BD0000010016000246890089184A68002053891B1D53814A6813895B1C138149684A68521C4A6070470000F7B5054682B000205249534A20 +:4076C00000900427681AAE188D421BD00ADC002E1AD04E2E1AD04F2E18D0F5208000301A15D10DE001280BD0032807D0072803D0474940180BD107E00A2708E00B2706E06E +:407700000C2704E0442702E0072700E006276946381DFCF7E8FC002802D0072005B0F0BD009C294667702046039AFCF7D3F90398002864D1344B2A465B1CE81A049F049D04 +:4077400034493F0AEDB29A4238D008DC002E23D0F5208000301A3CD0012850D14CE002280BD0062804D02A49491C401847D11BE0A11D0020F3F784FB41E0087DA071000A08 +:40778000E071087D2072487D6072000AA072487D21460931E0722CE0214608310498EFF76DFD06E060712AE0214608310498EFF751FDA571E771002821D0F3E7251DA01DCD +:4077C00008220021ECF79EFEA87960210843A87115E00879A0710889E071000A2072487960720888A072000AE072C88821460A312073000AC87002E0A01DFCF7B7F92146B3 +:40780000FF20FBF7E6FE89E702100000D3F3FFFFFDFBFFFFAC1E000830B51E4B0224C21A984235D015DC1C4B0325C21A984225D008DC1A4A801826D0172826D0184A8018E6 +:407840001AD11DE02A2A1ED0602A19D0782A13D11BE0144BD01A9A4210D007DC124810180CD001280AD0022806D107E0042805D001229202801A08D0002030BD002000E082 +:407880000820087002E00D7000E00C70012030BD0420F6E77C0C0000030C0000FAFBFFFF05F8FFFF890300007BFCFFFF10B5224C131BA2423CD016DC204C131BA24228D01F +:4078C00008DC1F4BD2182DD0172A2ED01D4BD21808D121E02A2B22D0602B1DD0782B01D1FDF7EFFE10BD184C1A1BA34211D007DC164A9A180DD0012A0BD0022AF2D108E0F8 +:40790000042A06D001239B02D21AEBD1FDF7F9FE10BDFDF79FFE10BDFDF72AFE10BDFDF7F7FE10BDFDF797FE10BDFDF7FDFE10BDFDF7A0FF10BD00007C0C0000030C00001C +:40794000FAFBFFFF05F8FFFF890300007BFCFFFF70B50C460146304E01208B1B0546B1424ED01DDC2D4E8B1BB14238D00CDC2C4BC91839D017293DD02A4BC91803D111468D +:40798000204600F055F870BD2A2B23D0602B3DD0782BF8D115701146204600F091F870BD214D591BAB4213D007DC204959180FD001290DD00229F2D10AE0042908D001236D +:4079C0009B02C91AEBD11146204600F088F870BD002070BD1146204600F085F870BD1146204600F088F870BD15701146204600F05BF870BD15701146204600F078F870BD72 +:407A000015701146204600F082F870BD1146204600F036F870BD00007C0C0000030C0000FAFBFFFF05F8FFFF890300007BFCFFFF10B5104B0422597A3024114059720E4AFE +:407A40000168114001600D4A416811404160026850080843810A2140C00D422420400143587A120989242240104301435972002010BD0000A021000890880002008000205B +:407A8000084AFB23517A1940517201230168DB0519400160507A490D042319400843507200207047A021000870B50C460546FDF70CFF002803D121462846F1F7E1FD70BD76 +:407AC00070B50C460021217005462146FEF762F8002803D121462846F1F700FF70BD10B5FEF764F810BD10B5FEF76AF810BD10B5F1F740FF10BD70B50C460546FEF770F8D3 +:407B0000002803D121462846EFF76CFD70BD70B50C460021217005462146FEF763F8002803D121462846F2F7A3F870BD10B5F0F74FF910BD10B5F0F7B7F910BD10B5F0F7B5 +:407B400051F910BD10B5F0F7F9F910BD7047000010B50C460088044948430449EAF7D8FFBD21081A208010BD4B2800001027000010B50C460088AE214843034940180A2171 +:407B8000EBF7B0F8208010BD91FCFFFF70B5094C054621780648002909D1074A0321074800F0C2F9002802D102212170656070BD02001600740200086D7D011004080000E7 +:407BC00070B50A4C05462178074800290AD10F21074A0902074800F041FA002802D101212170656070BD00000200160074020008A17C01103B08000001484078704700006E +:407C000074020008F8B506461920694608702020487001248C700220C8706846EAF704FB002805D01449884202D013481230F8BD022000F0FFF8114F2F253D630A20EAF7BC +:407C400053FE304600F08EFC0D4E304600F018F9802188430146304600F026F900F076FC00F040FA3D6307488460012000F0D8F900F07EF9F8BD00000300160040F03D4096 +:407C80000E1E000040003C4010B5EAF76DFA10BD10B5400701D500F08BF910BD7047000010B5034A0321034800F03EF910BD0000B97C01100408000010B5034A08210348DB +:407CC00000F01CF910BD0000D17C01100608000010B5034A0821034800F026F910BD0000E97C01100608000010B5034A0721034800F01AF910BD0000017D01103C08000038 +:407D000010B5034A0221034800F0A8F910BD0000197D01103A08000010B50249024800F063F910BD2D7D01101B0A000010B5C80704D00549054800F057F910BD00210846AA +:407D4000FFF7EAFF10BD0000517D01101A0A000010B5054CC9B26268002A01D00020904700206060207010BD7402000810B5034A0821034800F0C2F810BD0000857D01103C +:407D80000608000010B5034A0821034800F0CCF810BD00009D7D011006080000032110B58902034B0A46034800F090F810BD0000B97D01103D08000010B5034A01210348C8 +:407DC00000F04CF910BD0000D17D01103A08000010B50249024800F007F910BDE57D01101B0A000010B5880704D50549054800F0FBF810BD00210846FFF7DEFF10BD0000AA +:407E0000097E01101A0A000010B5054C090A6268002A01D00120904700206060207010BD7402000802480168490049080160704700003C4070B50446002500F091F80128CE +:407E400002D1002000F0ECF80B4A11680B48012301433F20400381431B039943012C08D960033F24640300194003400B0843184301461160284670BD00003C40040A00806D +:407E80000121C9030843074A0004D061054840300168C907FCD00168012319430160D06A80B2704700003C404004400808430649C861054840300168C907FCD001680122BB +:407EC000114301607047000000003C4070B5094C054626780648002E08D1032020706360218162810449284600F07EF870BD00000200160090280008A980011030B5084B4F +:407F000004461D780548002D07D1022018705A6059810449204600F067F830BD0200160090280008A980011010B5074B1C78002C01D0064810BD01241C705A60598104497C +:407F400000F052F810BD00009028000802001600A980011001490120087070477C02000802480068C007C00F7047000000013C4000B50023FFF7F4FF012801D0084B0CE052 +:407F800008490C20086188610748012101700021064A4160116051609160184600BD00000200160000013C407C020008902800080A48C16901610A480A0701D5416802E053 +:407FC0004A0700D50168074A0123137088B25268090C002A00D010477047000000013C4040013C407C02000810B50A4A034614780020012C01D0084810BD022414705160A5 +:4080000006494B60054A403A116808231943116010BD00007C0200080200160040013C400D490A68D207D20F824205D001220028086802D0104308607047022318430860E2 +:408040000868C007FCD10869104308610248C038016811430160704700013C4010B50A4B090401431C780020012C01D0074810BD02241C705A60064A1160054940390A689C +:4080800004231A430A6010BD7C0200080200160040013C4003480078012801D001207047002070477C020008F0B50D4C012622465389277800259E405268012F0AD0022FB8 +:4080C0000BD0032F05D12689B1431943FFF7C6FF2570F0BD0E43B1B2F8E7B143F6E700009028000810B517493820886116484860144A1648C03210611648154A4260174B31 +:40810000154A9A61164A0260144B164A803B9A63154A13680124640223431360134A022313630269082492B222430424CC601A4319030A4381158A4341210A43026100F0B7 +:4081400017F810BDC0103C4037D70000308A000058480000001E3C40FF0F000040123C400524000020FF000040503D40C0F03D4070B51849002548681C2210434860154886 +:408180004038416A826AC9B2D2B2C06A51180002000E4018001DC10700D0401C01264408B6020A2C12D90A212046EAF7B1FCC0B2072800D907200A214143A14204D2611AB6 +:4081C000CDB21F2D00D31F2544012C4302483443846370BDC0F03D4080103C4010B5FFF7BFFE012802D10020FFF71AFF044C2046FFF746FE8104890C2046FFF755FE10BDB2 +:40820000021E00000248416B022291434163704740F03D400248416B022211434163704740F03D40014909680180704780F03D4010B50C4C2F202063FFF754FF9A20E0629E +:40824000FFF78EFE002809D107480068002802DB0220FFF7EFFD0120FFF7E2FEFFF788FE10BD000040F03D4000003C40F0B58C4600881749884202D11648006880B28104D8 +:408280000C0D0004800F10D0012810D0862600202F230246262C10D30F4FD018400841007D5AA54205D140B207E05726EFE77026EDE7991A012905DC50B22030801B614643 +:4082C0000870F0BDA54201D20246E6E70346E4E7FFFF000080F03D40E05000100449002802D0012008567047002008567047000084020008F1B51B4FFD6A1A484030406B17 +:40830000C0072DD0386BC0072AD0FFF7C3FE012826D0102128468843F86200211248FFF763FE124C20690007FCD5104840304068060C08206061FFF70DFE0320400386434F +:40834000009800224003304381B20748FFF786FE20694007FCD504206061FFF7FBFDFD62F8BD000040F03D400F1E000000013C40F8B52449496BC90743D022494039096BA9 +:40838000C9073ED04178002912D01F4D1F492C1D002282560527FF43931D0026BA4214D00CDC0E331ED0042B17D0082B0AD10FE0154D1649083D2C1D491EE9E7002A01D035 +:4083C000042A14D00E70042714E00F70032711E00B22D2430A7002270CE00F22D2430A70012707E01322D2430A70002702E004220A70052700214156084600F01BF82F6063 +:408400002660F8BD80F03D40B8113C408502000810B5FFF7A5FD012802D10020FFF700FE03492F2008630220FFF704FD10BD000040F03D40F8B5314C0646E56AFFF72AFE57 +:40844000012859D01021284688432146C8622B484030006A2A4C2B4F00072BD52A48A178042E02D0042913D043E0042941D0A188802291430722120211430022FFF7EEFD38 +:4084800038694007FCD504207861FFF763FD1CE0A1880F22D20191430322520289180022FFF7DCFD38694007FCD504207861FFF751FD0FE0A078042E02D0042807D018E0A8 +:4084C000042816D00720EAF78DFAB02103E00320EAF788FA98210C4800220930FFF7BEFD38694007FCD50420786104498862FFF731FD0248A670C562F8BD000040F03D408E +:408500008402000800013C40071E000070B5084980200860074C0025E562FFF779FFFFF75DFE262020636563FFF77CFC70BD000000103C4040F03D4010B503490020C8624F +:40854000E9F766FE10BD000040F03D4010B50348FFF796FC0249888010BD0000071E00008402000810B5044600F0D4FC204600F035F900F015F80849012000F0E5FB074CED +:40858000FF214131204601F025F865218901204601F020F810BD000088090000021E0000F8B5002469462046009400F0F9FF00980321C008C000084381B20090002001F0F3 +:4085C00009F80126760269463046009400F0E8FF009902200143009189B2304600F0FAFF4C494D4800F0F6FF4B4D6946ED1E2846009400F0D5FF3F210098C9018843FF214D +:408600008131084381B20090284600F0E3FF424F6946843F3846009400F0C2FF00980125284381B20090384600F0D4FF3A486946801F009400F0B4FF03210098890288432E +:4086400081B200903448801F00F0C4FF6946B81C009400F0A5FF0098A84381B20090B81C00F0B8FF6946B81C009400F099FF0098284381B20090B81C00F0ACFF2648012199 +:40868000001F00F0A7FF00946946244800F088FF0098C007F8D0FF200021013000F09AFF1D480021813800F095FF69463046009400F076FF00980221884381B2009030461E +:4086C00000F088FF69460020009400F069FF00980721C008C000084381B20090002000F079FF0F4E45218901304600F073FF65218901304600F06EFF69463846009400F0B1 +:408700004FFF009938462943009189B200F062FFF8BD0000665E000088080000110A0000021E000038B50B21002000F053FF012464020721204600F04DFF1421224800F0A8 +:4087400049FF214D2049AD1C0939284600F042FFE91F284600F03EFF1B481C49483000F039FF19480121343000F034FF164801213D3000F02FFF21200121800100F02AFF13 +:40878000114813494A3000F025FF0021114D00916946284600F004FF00994907F8D50021204600F017FF0F21002000F013FF0A4C45218901204600F00DFF652189012046A3 +:4087C00000F008FF38BD00000408000042020000BD6E0000110A0000021E0000F1B58AB00A98012842D110216846E9F737FF00283CD168460088A249884237D16A46518873 +:4088000048409188D288514048406A46118948405189484091894840D189814226D1FFF781FF68464188974800F0D4FE684681889448401E00F0CEFE6846C1889148801E91 +:4088400000F0C8FE684601898E48C01E00F0C2FE684641898B48001F00F0BCFE684681898320400100F0B6FE0BB0F0BD8648069086480990EAF734F8012810D04120C001E7 +:408880000790834869465A380882012065244002E4014882401088827D4D662015E0EAF721F8002803D07A4D7A4C2D1D02E0F925794CED0079480790794869460882FF2062 +:4088C000C3304882C82088827020C8827548066A00273007002811DA08A97348089700F05FFE0F210898C901884307210902084381B208906C4800F06DFE02E00720EAF752 +:4089000071F8694808A90930089700F049FE0898782188433821084381B208906248093000F058FEC820E9F7DFFF2946204600F0EBFC544D6C466D1EA11C284600F030FE48 +:4089400068464088810602D1401C69464880E9F7C9FF002808D16846408880090A2803D98320800069464880300712D54E4E08A93046089700F014FE0F210898C90188431D +:4089800003214902084381B20890304600F022FE02E00320EAF726F8434E08A909363046089700F0FDFD0898782188431821084381B20890304600F00DFEC820E9F794FF09 +:4089C0000699079800F0A0FC211D284600F0E8FD68468288900602D1521C6846828004A8099900F063F8A11D264C204600F0D8FD02A9284600F0D4FD02A9A61E0231304607 +:408A000000F0CEFDE71E03A9384600F0C9FD68464188204600F0DEFD68468188284600F0D9FD6846C188304600F0D4FD68460189384600F0CFFD68464189201F00F0CAFDF5 +:408A400068468189601F00F0C5FD0A98012800D00AE70B486A461080518848409188D288514048406A46118948405189484091894840D08110216846E9F720FFF4E6000022 +:408A800082030000651000008202000082040000C6070000D4300000952E0000841C0000DC05000080F03D40071E0000F3B581B00024054669462046009400F071FD0098A4 +:408AC0000321C008C000084381B20090002000F081FD012069464002009400F061FD00980721C008C000084381B200900120400200F070FD834F69463846009400F050FD54 +:408B000000980126304381B20090384600F062FD69463846009400F043FD00980221084381B20090384600F055FD69463846009400F036FD00980421084381B200903846CC +:408B400000F048FD69463846009400F029FD00981021084381B20090384600F03BFD6946B81C009400F01CFD00980627B84381B200906448801C00F02DFD62486946801C72 +:408B8000009400F00DFD0098B843384381B200905C48801C00F01EFD5A4F694648373846009400F0FDFC00980221084381B20090384600F00FFD69463846009400F0F0FC59 +:408BC00000984021084381B20090384600F002FD69463846009400F0E3FC00987102084381B20090384600F0F5FC464F694634373846009400F0D4FC0098304381B20090AA +:408C0000384600F0E7FC3F4F69463D373846009400F0C6FC0098304381B20090384600F0D9FC7F1E69463846009400F0B9FC0098304381B20090384600F0CCFC3148FF21BD +:408C4000CA31623000F0C6FC2E480299643000F0C1FC2C4829885D3000F0BCFC294869885E3000F0B7FC2748A9885F3000F0B2FC2448E988603000F0ADFC224822494A3054 +:408C800000F0A8FC214D00946946284600F088FC00994907F8D51B480221633000F09AFC00946946284600F07BFC00998907F8D501256D0269462846009400F071FC0098EF +:408CC000C108C900009189B2284600F083FC69460020009400F064FC00980721C008C000084381B20090002000F074FC084C45218901204600F06EFC65218901204600F046 +:408D000069FCFEBD04080000BD6E0000110A0000021E000010B50A4A02280AD0012807D1084808188001C01C81B2104600F052FC10BD7D200001081A80013D30F4E7000099 +:408D40004E0800002FF8FFFFF3B5002583B000287DD0FF240026163401A92046019600F01FFC0198022180088000084381B20190204600F02FFC614F01A93846019600F00B +:408D80000FFC032101980903884381B20190384600F020FC01A92046019600F001FC0198302188431021084381B20190204600F011FC534E002402200499FFF7ABFF002096 +:408DC000019001A9304600F0EBFB01984006F8D54B486946083000F0E3FB68460088641C2D180A2CE7D3E9F77BFD07006AD00A212846E9F78DFE6946088068460188FF20E3 +:408E0000143000F0E7FB0020FF241634019001A9204600F0C5FB019830218843084381B20190204600F0D6FB00252C4602200499FFF770FF0020019001A9304600F0B0FB2C +:408E400001984006F8D52E486946083000E037E000F0A6FB68460088641C2D180A2CE5D3002F3DD00A212846E9F752FE6946088068460188FF20153000F0ACFBFF240025C2 +:408E8000163401A92046019500F08AFB019902208143019189B2204600F09CFB01A92046019500F07DFB019930208143019189B2204600F08FFB65218901124800F08AFBCB +:408EC00005B0F0BD2846EBF757F90F4A0F4BEAF74FFB00220E4BEAF735F8E9F755FF8AE72846EBF749F9084A084BEAF741FB0022074BEAF727F8E9F747FFB7E703020000D3 +:408F00001D0A0000021E00009A9999999999244000005940F8B5E9F7E3FCE94D0746002469462846009400F03BFB03210098890388430121C903084381B20090284600F0FF +:408F400049FB6E1C69463046009400F029FB032500986D03A843284381B20090304600F039FB69463046009400F01AFB00981C2188430421084381B20090304600F02AFB57 +:408F800069463046009400F00BFB0098022180088000084381B20090304600F01BFBC84E694609363046009400F0FAFA0098A84381B20090304600F00DFBB021701C00F0C2 +:408FC00009FBBF4865218901001F00F003FBFF25173569462846009400F0E2FA00981021084381B20090284600F0F4FAB54DFF202946313000F0EEFAFF202946323000F090 +:40900000E9FAFF208021333000F0E4FAB1218900012000F0DFFAAC49052000F0DBFA8125ED00AA4E002F7DD0C1218900022000F0D1FA3146032000F0CDFA3C210B2000F020 +:40904000C9FA2946072000F0C5FAA0490820FF3900F0C0FA39210C2000F0BCFA00210A2000F0B8FA40210D2000F0B4FAFF207021133000F0AFFAFF262D211636C901304625 +:4090800000F0A8FAFF27FF2134370902384600F0A1FA8F498F4800F09DFA8E488E49401C00F098FA8B488D49801C00F093FA272181200901800000F08DFA41208849C000FA +:4090C00000F088FA83488749001D00F083FAFF25804801352946401D00F07CFA03203A21400200F077FA78497F480E3100F072FA7D487E49401C00F06DFA7B480621801C7C +:4091000000F068FA78480321401D00F063FA61207749000100F05EFA7348FF21103000F059FA00E0B5E07048C821083000F052FA6D480121093000F04DFA6B483C21113045 +:4091400000F048FA684801210C3000F043FA664868490D3000F03EFA634867490E3000F039FA41206946C000009400F019FA0721009889028843E900084381B2009041202D +:40918000C00000F027FA5D49384600F023FA69463046009400F004FA0F21009809028843084381B20090304600F014FA0421880200F010FA1021524800F00CFA50480E21B5 +:4091C000401C00F007FA4E4840210F3000F002FA4B488021103000F0FDF949488621113000F0F8F93B486946401C009400F0D8F90098382188432021084381B200903548E1 +:40920000401C00F0E7F9812069468000009400F0C7F903210098090388436901084381B200908120800000F0D5F9812069468000009400F0B5F903210098890288430843A5 +:4092400081B200908120800000F0C4F921486946001D009400F0A4F90721009809028843284381B200901B48001D00F0B3F919486946001D009400F093F900980121000927 +:409280000001084381B200901248001D00F0A2F9F8BD2946022000F09DF93146032000F099F93B210B2000F095F90E4907200A3900F090F91349082000F08CF93321CAE679 +:4092C000061E0000808000000DB00000013E000030480000010200009426000043430000D4D20000190800000106000036790000FF0D00008CC800004698000034CA0000DA +:4093000001100000023A0000F3B581B0002469462046009400F044F900980321C008C000084381B20090002000F054F901277F0269463846009400F033F900980625C0084D +:40934000C000284381B20090384600F043F969468E48009400F024F900980126304381B200908A4800F036F969468848009400F017F900980221084381B20090834800F0B2 +:4093800029F969468148009400F00AF900980421084381B200907D4800F01CF969467B48009400F0FDF800981021084381B20090764800F00FF975486946801C009400F0F3 +:4093C000EFF80098A84381B200907048801C00F001F96E486946801C009400F0E1F80098A843284381B200906848801C00F0F2F8664D694648352846009400F0D1F800989B +:409400000221084381B20090284600F0E3F869462846009400F0C4F800984021084381B20090284600F0D6F869462846009400F0B7F80098384381B20090284600F0CAF8EC +:40944000BD1D69462846009400F0AAF80098304381B20090284600F0BDF84C48632149017E3000F0B7F849480521343000F0B2F8474E69463046009400F092F80098032106 +:4094800080088000084381B20090304600F0A2F83E484049623000F09DF83C480299643000F098F8394801995E3000F093F8374800215D3000F08EF8344800215F3000F05A +:4094C00089F832480021603000F084F82F4832494A3000F07FF800946946304800F060F800984006F8D529480221633000F072F800942A4869460C3800F052F80098800700 +:40950000F7D569463846009400F04AF80098C008C00081B20090384600F05CF869460020009400F03DF800980721C008C000084381B20090002000F04DF8154F45217F1F2C +:409540008901384600F046F865218901384600F041F869463046009400F022F80098022180088000084381B20090304600F032F869462846009400F013F800984108490004 +:40958000009189B2284600F025F8FEBD04080000071E0000C9050000BD6E00001D0A000010B50C4601210903FF22411A0232914208D201460548FEF777FC0121C802FEF7D9 +:4095C00073FC0348FEF75CFC208010BD01080000080A000010B5FEF767FC10BDE897FE7F010000000000001000000008C000000004960110C0000008B804000028190008A5 +:40960000740F000000127A0000127A0000093D0000093D0000093D0004000000A00F00000000D0070700000002000000030000000F00000000000000000000000300000015 +:409640000000000000000000000000000000000000000000030000000000000000000000000000000000000000000000000000000000000019000050A0000000E4450010A5 +:40968000DC450010404600100000614002FF0000891F00100100000006000000841E00080000000000000000000000000000000000000000000000000000000020000000B8 +:4096C00000FFF40100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076 +:40970000000000000000000000000000000000000001000000000000000000000000000000000000FF0000000000000000000000A84700100000000000000000000000002A +:4097400050480010000000000000000098480010000000000000000021000000C04800103C4D0010C04D0010444E0010000000009145011091450110084F0010D95E011043 +:40978000DB5E0110744F0010804F0010E1610110DD610110E04F001035660110D1660110585000100000000000000000000000000000000000000000000000000000000020 +:4097C00000000000000000000000000000000000E9000010C100001000000000F7B50D00019000F04BF9060003281FD12D4B1B69002B19DB002000F051F92B4FB84213D034 +:4098000000232A4A1900012000F020F9041E0BD1002000F043F9264BB84203D09C4203D00134F5E79C4201D1224D39E000F02EF9214A04000121214800F010F900282DD19C +:40984000019B002B16D1ADB2ED0001D11C4D18E03E221C4B06211A601B4A1C4B1A60A3221B4BD20099501B4A9D50995899580029FCDAEBE7114A1369002BFCDB00F016F94A +:409880000500032E03D0200000F0D8F808E00121002000F0EBF80028F9D1F4E7054DF0E72800FEBDC00023400101880048010008F049020005005200401E00080000234090 +:4098C00001005000040126401E1F000008012640000026401C05000010B54378FF2B0DD100F0D4F8064BDB685A68012311681943116011681942FCD100F0A0F810BDC04679 +:409900008000234070B52B490A682A4B002AFBDA0221DA680A43DA60DA68D2071BD5264D264CD9682A69266889B2360A36060E43FF21120209040A4032439026DA602969FD +:409940001F4A360111403143296121680A40324322602A692268002204241A495A605A680A6922430A61012801D030BF00E020BF1A68104D002AFBDAEA68D20712D5FF24EA +:409980000D4E0F4A3069E9682402090A1040214001430A4831610668E9683240090C0C40224302600221DA688A43DA6000225A6070BDC046E000234000002140900021408E +:4099C000FF00FFFF00ED00E00421134A13690B431361012801D030BF00E020BF0F4A1368002BFCDA0E4B19691A00002910D10D490D4B196006210D4B19600D4B3831196008 +:409A00000C4B0631196019680029FCDA0A4B13610022024B5A60704700ED00E0E0002340FC0025401E1F00000801264018052640040126401C052640AAAAAAAA01B40248BD +:409A4000844601BC604700BF531F001001B40248844601BC604700BF1911001001B40248844601BC604700BF890E001001B40248844601BC604700BFA90F001001B402480B +:409A8000844601BC604700BF0504001001B40248844601BC604700BF4B1F001001B40248844601BC604700BF2110001001B40248844601BC604700BF611700100000000099 +:409AC0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000066 +:409B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025 +:409B400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E5 +:409B800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000A5 +:409BC0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000065 +:0200000490303A +:02000000C887AF +:0200000490501A +:0C0000000005E20721002101E296E987DB +:00000001FF \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.01.hex Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,150 @@ +:020000041000EA +:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC +:4000400091010010F10700109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010FA +:400080009101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001020 +:4000C00010B5064C2378002B07D1054B002B02D0044800E000BF0123237010BD4804000800000000541F0010084B10B5002B03D00749084800E000BF07480368002B00D1AD +:4001000010BD064B002BFBD09847F9E7000000004C040008541F001044010008000000007047EFF3108072B6704780F310887047FFF7F6FF72B6104C104DAC4209DA2168D4 +:400140006268A368043B02DBC858D050FAE70C34F3E70B490B4A0020521A02DD043A8850FCDC094809490860BFF34F8F00F0ECF800F01EF8FEE70000581F0010701F0010D1 +:4001800048040008380700080000000808ED00E0FEE7FEE700B504207146084202D0EFF3098001E0EFF30880043001F08DFAFEE710B500F0A5F962B6064B5B689B0301D517 +:4001C00001F044FA044800F02FF9002001F090F9FBE7C0460000264000000810F8B5E023504C9B00E2580F231340D022990092000919885807224C4D0240032A05D0042A73 +:4002000005D0002A0FD0494811E028680FE0C022920089581F220A40112A01D0132A04D18020000203E0424801E0FA20C001002B27D1B223B1210322DB00C900E65863588A +:4002400067581B0F3F0F1340174205D0354F7958090F0A40012A01D1F20701D4032B3AD1B023344ADB00E658A158E758C904C90C01F050FDB603F901B60BC90F7043013158 +:4002800027E0012B27D1C823C0210322DB00C900E658635867583F0F174205D0214F7958090F0A40012A01D1F20703D49B009B0F032B10D1C0227F23D200A758A1583B40BD +:4002C0001F27A658090A3940584301F023FD310C394001F01FFDE0239B00E3589B069B0FD840154B68601C691969240A090E013101F010FDE1B2A860013101F00BFD0F4BBF +:40030000E860286104000E49C01801F003FDFA210C4B28758900E01801F0FCFCA861C003E861F8BD00002640C000000800366E0100127A0084050000000021403F420F00AC +:4003400040420F00E7030000B021E02010B530241F4BC9005A588000520052085A501A58A2431A50802252045A501A491A4A80209950A021043289019950FF21174AC005FA +:40038000995081315A5892009208024380205A505A580006024301205A505A5882435A5000F054FAFFF71AFF00F02AFA00F032FA00F0B8FEB0235B055A78002A02D05B7855 +:4003C000212B03D10022064BDA605A6010BDC0460000264001000200840500008C050000E0002340024BD86F032318407047C0460400214010B5FFF794FE074A074BD16F79 +:400400000B4007490B43D367102306490A681A42FCD0FFF78AFE10BD04002140FCFF00000100FA058800214070B50F4C0600FFF778FEE36F0500DB439B0701D1FFF7DAFF3F +:40044000B0230A4A9B00D650E26F094B09491340094A1343E36710230A681A42FCD02800FFF763FE70BDC0460400214000002140FCFF0000880021400300FA0510B5040063 +:40048000007B00F0F3F8606010BD10B50400007B216900F0B5F8606010BD10B5037B0169180000F0CDF810BD10B50400C06800F009F9606010BD10B5C06800F017F910BDF0 +:4004C00010B50400C06800F023F9606010BD10B5C06800F037F910BD10B504000C23C05E00F056F8606010BD10B50C23C05E00F06FF810BD10B5C06800F036F910BD0000A8 +:4005000010B500221849042000F0A4FC01221749042000F09FFC02221549042000F09AFC03221449042000F095FC04221249100000F090FC05221149042000F08BFC0622E9 +:400540000F49042000F086FC07220E49042000F081FC08220C49042000F07CFC09220B49042000F077FC10BD7D0400108B0400109B040010A9040010B7040010C104001062 +:40058000CF040010D9040010E9040010F504001070B507260512EDB206400D2D11D801F0F8F80A4901224B5D1C003441144003D1B24013434B5501E00124644201F0EDF8D2 +:4005C00001E001246442200070BDC0466404000870B50412E4B20D2C0FD80725054001F0D8F8064901220B5D1E002E41164202D0AA4093430B5501F0D0F870BD6404000862 +:40060000F8B50C00050001F0C4F80C2301225D431300A3401A00094E71198F683A4008D13B43AD598B60631C4B60AB4202D94A6000E0FF2401F0B1F82000F8BDE0000008BD +:4006400070B50C00050001F0A4F801210C23A1406B43054AD3189A680A4201D08A439A6001F09BF870BDC046E0000008F0B50C2485B0019001F08DF8019B114D5C432B192A +:400680005B68029003932E1971680198FFF7B8FF0700FF280DD173682A59934201D9002373602A1953680399994202D001335360E9E7029801F071F8380005B0F0BDC04648 +:4006C000E000000810B5040007280AD801F061F8054B0E331A5D002A01D101321A5501F05CF80120404210BD6404000810B5040007280AD801F04DF8044B0E331A5D012AE1 +:4007000001D100221A5501F048F810BD6404000870B505001F280ED801F03BF8084B30335C5D002C02D101225A5501E00124644201F033F801E001246442200070BDC04666 +:40074000E000000810B504001F280AD801F021F8044B30331A5D012A01D100221A5501F01CF810BDE000000870B5B024C025144B144A15496405ED00E35CA25C615C665D18 +:400780003F251F242A400C4024039201224311002B407F2219430B003240520413430B4A1C0A110050310B701B0C8B7000234C7011005031595CC1540133062BF8D170BDDB +:4007C000040600000506000003060000E000000810B50248583000F051FB10BDFC04000810B50248B03000F049FB10BDFC04000810B5024800F042FB10BDC046FC0400083C +:4008000010B5034A80216032042000F001FA10BDFC05000870B500F0BCFF0500094800F08BFA094C200000F0B9FA2000343000F0B5FA2000683000F0B1FA280000F0ADFFA1 +:4008400070BDC046FC040008881E0010F0B5962191B0002000F050FF00F026FF002801D100F014FF012000F09FFDE821724C734B626C89011A400A436264626C0193120A04 +:40088000D2B23A2A04D1636C6D4A13400B4363643422002103A801F0D2FA03AA0021694800F06EFC3422002103A801F0C8FA03AA0121644800F064FC082204262368624DA7 +:4008C000134323602369334207D1002D04D0012000F0D2FE013DF5E701E0002D00D1FEE7A02603220127594CF600A35903AD93433B43A351D2195649280001F097FA280088 +:4009000000F0FAFF534901980B68534A03400B608021136949041B021B0A0B4313611369019902200B401361E0230F219B00E2588A433A43E250E25821318A438021E250C6 +:40094000E25809060A43E250002100F0D3FA0021032000F0CFFA0021042000F0CBFA0321002000F0C7FA0321380000F0C3FA384B0522191D280001F059FA2900380000F03F +:40098000DBFA002800D0FEE73449380000F026FB002800D0FEE7324B324AE1580A403A43E250E158304A0A408021E250E25809060A43E250A2592D4B1340A351A2592C4BF3 +:4009C00013408022920113438022A351A35912021343A351184B1A68264B1340164A136000F0DEFEC0235B00E3583B4204D1224AA3585B005B08A3506421002000F07CFEEF +:400A000024220021280001F01AFA29000D4800F031FC2A000E4B0C3313CB13C213CB13C213CB13C22900154800F024FC144A154B1A6011B0F0BDC04600002740FF00FFFF06 +:400A4000FFC5FFDF0000324020A1070000002640241F001090002140000021401027000004050000FEFCFFFFFFFF00FFFFF0FFFFFF8FFFFFFFFCFFFF0C0500000003324062 +:400A800001001180000E1F41030010B5FF24800882009B1ADB009C409940E243214007282DD8174B01F02CF904090E13181D2227186A02401143196221E0586A0240114332 +:400AC00059621CE0986A02401143996217E0D86A02401143D96212E0186B0240114319630DE0586B02401143596308E0986B02401143996303E0D86B02401143D96310BDD7 +:400B000000002140064B10309A68064B9A4203D183009858995002E0034B8000C058704700ED00E00000000800000010F7B5051E01913DD00023C05E002802DBA978FFF735 +:400B4000A3FF6A680023E85E9201002812DB1A4B81088900C918FF2303271C00C0250740FF00BC401A40BA40AD004E59A64332434A5113E003250F2381B20B402940A9404B +:400B8000FC352F002A408F408A40083B9B080B4C9B001B19DE69BE433243DA61074B00259A68074B9A4204D10199FFF7ABFF00E0044D2800FEBDC04600E100E000ED00E070 +:400BC00000000008010056000369002B03DA89B24160002000E001487047C04601008A000368002B01DB034803E089B2C26081600020704701008A000369002B03DAC368D6 +:400C000000200B6000E001487047C04601008A0070B5040010000F2C2BD8002A07D1002927D1154B6401E418144B1C6022E000291FD01F260E401CD1104D0F4B6401E418D0 +:400C40006960AA60CA0831002C6001F0F8F831002000FFF7B9FF31002A1D2868FFF7C0FF011E04D12868FFF7AFFF011E02D0044900E00449080070BD00002340EC06000850 +:400C800001018A0003018A00194BF7B51A680193D76804003B680E00834223D90025A94202D100F076FD0500019B18680368002B01DB104C10E063095A01A41A0122A24090 +:400CC00079689B00CB18196811420DD00024914319600021FFF778FF002E07D1280000F05CFD03E0044C01E0044CF2E72000FEBDEC0600080301880004018A0002018800B6 +:400D00000A4B1B68DA68136883420DD9430999005B01C31A0120984052688B581840431E9841034BC01800E002487047EC0600080001880004018A00024B1A68002A00D14A +:400D400018607047F8060008F0B52C246043104C1E0024681F0A2018FF2426403C400D4F06607601F61906610B4E1B0C44606401A4191E04836033434461A3600023059D5D +:400D8000C261016283619D4201D02B888381F0BDF80600080000234000102340F0B5038985B002AD2B800368066A1933AB704368476A0095826AC16A040003930369C068A1 +:400DC000FFF7C2FF00213B000A0000913000FFF7BBFF216B2800FFF7A9FE0023EA5E002A05DB1F231A401E3B9340024A136005B0F0BDC04600E100E0F7B52C25124C6843E9 +:400E0000276801933C182669002E08D04D4379198869002805D13568002D02DA03E00B4811E00B480FE06768012425004B689D4013882D041D431560F2608C61BC40019B65 +:400E4000A4B24B62B460FEBDF806000804028A0007028A002C235843064B1B681818C369934204D9036A9200D150002000E002487047C046F80600080A028A0073B500269A +:400E800042690400D56801962B0CB3421CD01B040069136013680369B34215DA01A9FFF7ABFEB0420CD10198E26903681E0C0378934205D2226A9B009B58002B00D0984725 +:400EC00031002069FFF780FEADB2002D0ED063691D6000251B68636AAB4202D09847656203E0A36A002B00D09847A56163691B6873BD0000042819D804290FD94B1EFF3B13 +:400F0000132B13D81F231940094B8000C018C02304229B00C1504033C25005E00723D0301940034B8000C150002000E0014870470000264001004A00F0B5012819D1C02275 +:400F4000224BD2009A58002A0CDB8A78901E0E280FD84C78601E11280BD8C8780D7800282FD101E01A4830E07026152D01D9AE4201D2184829E00E79022E14D0F82124020C +:400F80004901F8270C4021007F2412047F033A4011432C4021438024C022C006240520400143D2009950C020C0248005360706403200E4001D590849002029400A431A51C4 +:400FC00003E03826122DD4D9D1E7F0BD0000264003004A0001004A00FFFFFFCFF8B50D00012819D1C02180240D4BC9005A582406C826224307001C005A50F600A3593B42B7 +:4010000006D1002D0AD0012000F036FB013DF5E70020002D03D101E0024800E00248F8BD0000264001004A0002004A001E4A0300904238D010D840282ED005D8002831D0B5 +:4010400010282DD119482EE0802827D08021100049008B4227D023E0154A904214D008D8A022120690421DD0124AA020934211D016E0114A904209D0104A904208D0104AB1 +:4010800090420DD10F480EE0A42003E00E480AE00E4808E0C00306E00D4804E00D4802E00D4800E0002070470600520001005000010000F0090000A0040000F0050000F0C5 +:4010C000030000F00100520002005200030052000200500005005200FF0052000B4B10B51B69002B10DB0A4B0A4C1868FFF79EFF0121094B094A995099580029FCD10649AC +:4011000009590029F8D100E0054810BD00002340FC0600088C040000000025400C0400000200500010B5022202490020FFF792FE10BDC046450200080F4B30B5C0180F4B30 +:40114000C009C01800011F23032909D81D00C9008D4013408B400468AC432343036009E01D000439C9008D4013408B404468AC432343436030BDC0460000CEBF0010030457 +:40118000F7B504000E00150000286ED0002A6CD0012312688B40002A01D1436000E08360B30001930F231900B0008140A26A8A4369680B4083401343A3622A7A31002000BA +:4011C000FFF7BAFF0320710088400322636A83431800EB6813408B400343636201231F00B7400097FF43BC462F6962461F40B740A0691031104038436F69A0611F40B740A9 +:40120000E06A10403843E062A86903221840B0400600E869276B10408A408840009930430A4397436A6A384356000222206304201640AA6A616B92000240286A3243034017 +:401240001A43EB6AD80018230340FF2013432A6B019D520102401343FE2292002A40934081430B436363002000E00148FEBDC04601005A0000281BD0002919D00D4B0E4AD2 +:40128000C318DB099B180A681B010260CA6882620A69C2624A6902638A6842624A6882618A694263CA6900201A600A6A5A6000E0024870470000CEBF0010030401005A0069 +:4012C00010B50F2402200649064BCA58A2430243CA50F02212028B58A34303438B5010BD0000214004F0000010B50F2403200649064BCA58A2430243CA50F02212028B5872 +:40130000A34303438B5010BD0000214004F000000449054A054B88580340C020C00103438B5070470000214004F00000FF8FFFFF0449054A054B885803408020C001034365 +:401340008B5070470000214004F00000FF8FFFFF031E03D1084B5869C00F0CE00020012B09D1054918008A69920F1A4201D18869C00F01231840704700002640072370B540 +:40138000084CA2691A4090420BD0A5699D4303402B43A361002904D0904202D9C82000F06BF970BD00002640F7B5060000F0F1F9B022E8211F27244D244C01902B595205B1 +:4013C000C900525C3B409B1A5A1E9341B34236D0002E13D180211E4A490493690B439361FFF76EFF0B222B59BB4313432B51FFF78FFFB023E8225B05D2000CE00B222B5945 +:401400000920BB4313432B5100F036F9FFF790FFB022104B5205D35C2959DAB21F23994313400B432B51012E09D1092000F024F9FFF75AFF064A084B91690B409361019810 +:4014400000F0ABF9F7BDC046000026401CFF000000F0254041070000FFFFFFFEF0B5060085B00D00204F042901D001291AD100207C68002C35D01D4B984232D02379B3428C +:401480000ED1A368002B01D02B4209D1E36801A85A689B6842608360057023689847BC606469E6E7BC68022902D1002C00D024690020002C15D00D4B984212D02379B342AB +:4014C0000DD1A368002B01D02B4208D1E36801A85A689B68426083600570236898472469E7E705B0F0BDC0460C070008FF004200F7B5484C06002368002B0AD100F049F97C +:4015000023680700002B10D004210120FFF7A6FF0BE001210800FFF7A1FF0028EED002210120FFF79BFF3C4C72E03C4D2B680195DB061AD5F2223A4BD2019A58E260F022BA +:40154000D2019A582261374A9A586261364A9A58A261364A9A58E261354A9A582262354A9A586262344A9B58A362B02252055378002B02D05378212B03D1300000F07CFCAF +:401580001DE02E4B2E492F4859588C46E821C900515CC9B20091196809020AD41F2165460D402900009DA94203D0274952581A5002E00023214A1350300000F055FC019B2F +:4015C0001B68DB0619D5F0222169154BD20199506169144A9950A169134A9950E169134A9950216A124A9950616A124A9950A16A114A9950E168E8329950380000F0CDF888 +:4016000023680024A34203D008210120FFF726FF2000FEBD0C070008FF004200E00001400000344004780000087800000C7800001078000014780000187800000000264088 +:401640001CFF0000307F00001018000010B5E82400F09FF8064B07495A68A4010A4022435A605A68114059605B6800F096F810BD00002640FF00FC0F10B5034B1B78584324 +:4016800000F07EF810BDC046D400000880220020034B12069A649B6C834200DA0148704700002740030046008022054B120198585B68DBB2002B02D08023DB0218437047C5 +:4016C00000002640FEE7000002680A4B10B51A6042685A6082689A60C268DA6002691A6142695A6182699A61C269DA61FFF7EAFF10BDC04628040008F0B51922002800D19E +:401700004B32E82403258A429241194E640033595242AB43134333513359164F3B403351154B5C68AC4322435A605A6817405F60002808D00023102913D921338B429B4167 +:401740005B4201330DE003001D290AD901233A2907D9DB18572904D976338B4240410422131A0F21054A1068884303431360F0BD00002140FFFCFFFFFC002140000025403A +:401780000230800803D001300238FCD1C046C0467047EFF3108072B6704780F310887047094B042803D11A68104318600BE0C02200069204104090220449920088500421A6 +:4017C0001A688A431A60704710E000E000002140F8B58023FA250C0001271B0218430D4E0004F061AD00326C0A4B01203A4205D1002D0CD0013DFFF73FFFF4E7002D06D001 +:401800001A6C10431864DB6A0020238000E00248F8BDC04600003C400400160070B5FA2401260D4B000418400C4D0143E961A4002B6C0A4A0120334205D1002C0AD0013C8D +:40184000FFF71AFFF4E7002C04D0136C18431064002000E0024870BD0000FF7F00003C400400160030B524259DB02A00002101A800F0E5FA154B164C0493164B2A00002162 +:401880000AA808930993069400F0D9FA124B2A000D93124B00211193114B13A812930F9400F0CDFA0F4B01A916930F4B0F481A931894FFF7DFFC0AA90D48FFF7DBFC13A96A +:4018C0000C48FFF7D7FC1DB030BDC046666666660000FFFF1C1C1C1C66E6EE661C1A1A1A1A1A000066E666661A1A001C000132408001324000023240F0B585B000900028F3 +:4019000000D147E1BE4F7B689B0301D5FFF79EFE0122BC4BBC4C1D001959114204D0BB495B58134200D037E1FFF79CFFB84AB94BEA508022009BD2021B781343B64AAB5016 +:40194000B64AB74BEA50B74B5A6801231A4200D024E1B54A116F08220A4008D1B34BB44918681300884202D900F0D4F9431E2A68002B03D0AF485B03034300E0AE4B13439B +:401980002B607B699F499E4E01275B000DD539000320FFF7F3FC73699B0F3B420AD08022B369D2051343B36104E00320A34A8B5803438B502B5940200193019AA04BA14E7D +:4019C00013432B51FFF758FE0123AA598D4F1A4208D1BB514020FFF74FFE03234020BB51FFF74AFEFA27019A974B984E1A4016430192FF002E51964A964BD3581022134257 +:401A000007D1002F00D1CBE00120013FFFF734FEF1E7002F00D1C3E008218F4A0120AB580B43AB50FFF794FC002802D18B4E019B1E438B4B1E4001231E432E511E00894C2E +:401A4000724BEB58334207D1002C00D1A8E00120013CFFF711FEF3E7002C00D1A0E00B27C02181484901FFF7D9FE041E05D102AB991D7D48FFF7ACFE0400013F002F00D1E3 +:401A800096E0002C25D1C02202AB9E1D338852019342E5D131007548FFF79AFE041E18D180233288DB001A4200D083E00B27019380216E48C900FFF7B1FE041E04D13100AA +:401AC0006A48FFF785FE0400013F002F70D0002C68D0B0256D056B78002B44D06B78212B41D0634FEB5B002B3DD0002C00D0FEE002AB9E1D31005F48FFF76AFE041E00D061 +:401B0000F5E0C021E85B3488084060398C434008594920430140F020EA5BC000EB5BD201024011439B05554A9B0F1140DB02194350483180FFF772FE041E00D0D7E03100F2 +:401B40004F48FFF745FE041E00D0D0E0C022EB5B31889B069B0F9B019143194348483180FFF75CFE0400002C00D0C0E0009B454859781D78444B49001943FFF74FFE041EA3 +:401B800004D142494248FFF749FE04006801FFF773FDACE03F4CAAE03F4CA8E03F4CA6E03F4CA4E03388019A934200D080E701E03B4C8EE731003B48FFF70AFE041E00D074 +:401BC00087E732883F2310009843009B36499F78DB78012F0ED10222012B04D89FB2D21B92B2019201E0170001947022104330802E4A66E0002B5BD0019401275BE0C04668 +:401C00000000264000003C40A0F00100B4F0010006000001A4F00100A8F0010001000100ACF00100FC003C4000F03D40C800000800093D00041A0080040A0080C4F00100DC +:401C400030000300B0F00100EFFFFEFF20000200000032401040000068F0010028000200FFFFFBFFF07E0E00021E0000031E000016180000071E00007FF8FFFFFFE7FFFFDD +:401C8000061E0000081E000001100000376800000F1E000001001600030016000200160004001600091E0000C00000080048E80101201F0001907F2082436F3802433280A8 +:401CC0000C4ADA400A6031880B4839433180FFF7A5FD009B0400DB78DF1B03231F40019B9B001F43054BBFB23780EF50F1E6200005B0F0BD0024F400091E000064F001008B +:401D000002B4714649084900095C49008E4402BC7047C046002243088B4274D303098B425FD3030A8B4244D3030B8B4228D3030C8B420DD3FF22090212BA030C8B4202D3E9 +:401D40001212090265D0030B8B4219D300E0090AC30B8B4201D3CB03C01A5241830B8B4201D38B03C01A5241430B8B4201D34B03C01A5241030B8B4201D30B03C01A52419D +:401D8000C30A8B4201D3CB02C01A5241830A8B4201D38B02C01A5241430A8B4201D34B02C01A5241030A8B4201D30B02C01A5241CDD2C3098B4201D3CB01C01A52418309B2 +:401DC0008B4201D38B01C01A524143098B4201D34B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524183088B4201D38B00C01A524143088B4201D3C9 +:401E00004B00C01A5241411A00D20146524110467047FFE701B5002000F006F802BDC0460029F7D076E770477047C046002310B59A4203D0CC5CC4540133F9E710BD0300EB +:401E40008218934202D019700133FAE770470000F8B5C046F8BC08BC9E467047F8B5C046F8BC08BC9E46704701B40248844601BC604700BF3503000801B40248844601BC8E +:401E8000604700BF7102000803000000010000000100000000000000050360000400000001000000000000000100000006046000080000006C060008F107001008000000D2 +:401EC000010000000200000002000000080800030900000001000000000000000300000009090003080000008C060008D10700100A0000000100000004000000040000000B +:401F00000A0A000C0B0000000100000000000000050000000B0B000C10000000AC060008E1070010192001021901020000000000000000000000000000000000000000BA7A +:401F40000000000000000000000000000000000000001D1D000000000000001000000008C0000000781F0010C00000086803000048040008F002000000127A0000127A0017 +:401F800000093D0000093D0000093D0004000000A00F00000000D0070700000002000000030000000F000000000000000000000003000000000000000000000000000000A7 +:401FC0000000000000000000030000000000000000000000000000000000000000000000000000000000000019000050A000000002FF0000E9000010C1000010000000000A +:40200000F7B50D00019000F04BF9060003281FD12D4B1B69002B19DB002000F021F92B4FB84213D000232A4A1900012000F048F9041E0BD1002000F013F9264BB84203D00B +:402040009C4203D00134F5E79C4201D1224D39E000F01EF9214A04000121214800F028F900282DD1019B002B16D1ADB2ED0001D11C4D18E03E221C4B06211A601B4A1C4BCD +:402080001A60A3221B4BD20099501B4A9D50995899580029FCDAEBE7114A1369002BFCDB00F0E6F80500032E03D0200000F010F908E00121002000F0E3F80028F9D1F4E730 +:4020C000054DF0E72800FEBDC00023400101880038010008F049020005005200FC0600080000234001005000040126401E1F000008012640000026401C05000010B5437878 +:40210000FF2B0DD100F0C4F8064BDB685A68012311681943116011681942FCD100F0D8F810BDC0468000234070B52B490A682A4B002AFBDA0221DA680A43DA60DA68D2078E +:402140001BD5264D264CD9682A69266889B2360A36060E43FF21120209040A4032439026DA6029691F4A360111403143296121680A40324322602A692268002204241A491B +:402180005A605A680A6922430A61012801D030BF00E020BF1A68104D002AFBDAEA68D20712D5FF240D4E0F4A3069E9682402090A1040214001430A4831610668E9683240C4 +:4021C000090C0C40224302600221DA688A43DA6000225A6070BDC046E00023400000214090002140FF00FFFF00ED00E00421134A13690B431361012801D030BF00E020BF75 +:402200000F4A1368002BFCDA0E4B19691A00002910D10D490D4B196006210D4B19600D4B383119600C4B0631196019680029FCDA0A4B13610022024B5A60704700ED00E074 +:40224000E0002340FC0025401E1F00000801264018052640040126401C052640AAAAAAAA01B40248844601BC604700BF010D001001B40248844601BC604700BFDD100010FE +:4022800001B40248844601BC604700BF890C001001B40248844601BC604700BF9317001001B40248844601BC604700BFE503001001B40248844601BC604700BFE10B00101B +:4022C00001B40248844601BC604700BFF90D001001B40248844601BC604700BF9B17001000000000000000000000000000000000000000000000000000000000000000002E +:40230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009D +:40234000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005D +:40238000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001D +:4023C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000DD +:0200000490303A +:02000000121CD0 +:0200000490501A +:0C0000000005E20721002101E212331C80 +:00000001FF \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/ipc_rpc.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,108 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ipc_rpc.h"
+#include "Mutex.h"
+#include "Semaphore.h"
+#include "mbed_assert.h"
+#include "cy_ipc_config.h"
+#include "ipc/cy_ipc_pipe.h"
+#include <stdarg.h>
+#include "platform/SingletonPtr.h"
+
+using namespace rtos;
+
+
+static SingletonPtr<Mutex> msg_mutex;
+static SingletonPtr<Semaphore> msg_semaphore;
+
+
+#define RPC_GEN RPC_GEN_INTERFACE_IDS
+#include "rpc_api.h"
+#undef RPC_GEN
+
+// This function uses a "C" linkage as it is a callback called from Cypress library
+// which is C-only.
+extern "C" void ipcrpc_release(void);
+void ipcrpc_release(void)
+{
+ // Just signal on semaphore that we are done with a call.
+ msg_semaphore->release();
+}
+
+// Encapsulate call arguments and send a message over IPC pipe to the
+// other core for execution.
+uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...)
+{
+ va_list ap;
+ static IpcRpcMessage message;
+ cy_en_ipc_pipe_status_t status;
+ ScopedMutexLock lock(*msg_mutex.get());
+
+ // Make sure semaphore is initialized.
+ (void)msg_semaphore.get();
+
+ // Copy data to the buffer.
+ message.client_id = call_id;
+ message.args_num = args_num;
+ message.result = 0; // default result
+
+ va_start(ap, args_num);
+ for (uint32_t i = 0; i < args_num; ++i) {
+ message.args[i] = va_arg (ap, uint32_t);
+ }
+ va_end (ap);
+
+ // send message
+ status = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_RPCPIPE_DEST,
+ CY_IPC_EP_RPCPIPE_ADDR,
+ &message,
+ ipcrpc_release);
+ // We are using dedicated IPC channel here and have locked global mutex
+ // so this had to succeed.
+ MBED_ASSERT(status == CY_IPC_PIPE_SUCCESS);
+
+ // Now wait for the response;
+ msg_semaphore->wait();
+
+ return message.result;
+}
+
+extern "C" {
+
+ void ipcrpc_init(void)
+ {
+ uint32_t rpc_counter = 0;
+#define RPC_GEN RPC_GEN_INTERFACE_IDS_INIT
+#include "rpc_api.h"
+#undef RPC_GEN
+ }
+
+
+#define RPC_GEN RPC_GEN_INTERFACE
+#include "rpc_api.h"
+#undef RPC_GEN
+
+
+#define RPC_GEN RPC_GEN_IMPLEMENTATION
+#include "rpc_api.h"
+#undef RPC_GEN
+
+
+} /* extern "C" */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,461 @@
+/***************************************************************************//**
+* \file system_psoc63_cm4.c
+* \version 2.10
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2017-2018, Future Electronics
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "device.h"
+#include "system_psoc63.h"
+#include "cy_device_headers.h"
+#include "ipc_rpc.h"
+#include "psoc6_utils.h"
+
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "ipc/cy_ipc_drv.h"
+ #include "flash/cy_flash.h"
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ
+
+
+/*
+* Holds the FastClk system core clock, which is the system clock frequency
+* supplied to the SysTick timer and the processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
+ /** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
+ uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
+#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
+
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+/* WDT lock bits */
+#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u)
+#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u)
+
+#if (__CM0P_PRESENT == 0)
+ /* CLK_FLL_CONFIG default values */
+ #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+ #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+ #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+ #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+#endif /* (__CM0P_PRESENT == 0) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
+ CY_DELAY_1K_THRESHOLD;
+
+uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
+ CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+ ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
+
+#define CY_ROOT_PATH_SRC_IMO (0UL)
+#define CY_ROOT_PATH_SRC_EXT (1UL)
+#if (SRSS_ECO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ECO (2UL)
+#endif /* (SRSS_ECO_PRESENT == 1U) */
+#if (SRSS_ALTHF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_ALTHF (3UL)
+#endif /* (SRSS_ALTHF_PRESENT == 1U) */
+#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
+#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
+#if (SRSS_ALTLF_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
+#endif /* (SRSS_ALTLF_PRESENT == 1U) */
+#if (SRSS_PILO_PRESENT == 1U)
+ #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
+#endif /* (SRSS_PILO_PRESENT == 1U) */
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+* \cond
+* Initializes the system:
+* - Restores FLL registers to the default state for single core devices.
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+* \endcond
+*******************************************************************************/
+void SystemInit(void)
+{
+#if (__CM0P_PRESENT == 0)
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+#endif /* (__CM0P_PRESENT == 0) */
+
+ /* Unlock and disable WDT */
+ SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0);
+ SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1);
+ SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk);
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+}
+
+
+/*******************************************************************************
+* Function Name: mbed_sdk_init
+****************************************************************************//**
+*
+* Mbed's post-memory-initialization function.
+* Used here to initialize common parts of the Cypress libraries.
+*
+*******************************************************************************/
+void mbed_sdk_init(void)
+{
+ /* Initialize shared resource manager */
+ cy_srm_initialize();
+ /* Initialize system and clocks. */
+ /* Placed here as it must be done after proper LIBC initialization. */
+ SystemInit();
+ /* Allocate and initialize semaphores for the system operations. */
+ Cy_IPC_SystemSemaInit();
+ Cy_IPC_SystemPipeInit();
+ Cy_Flash_Init();
+ ipcrpc_init();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t srcFreqHz;
+ uint32_t pathFreqHz;
+ uint32_t fastClkDiv;
+ uint32_t periClkDiv;
+ uint32_t rootPath;
+ uint32_t srcClk;
+
+ /* Get root path clock for the high-frequency clock # 0 */
+ rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
+
+ /* Get source of the root path clock */
+ srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
+
+ /* Get frequency of the source */
+ switch (srcClk)
+ {
+ case CY_ROOT_PATH_SRC_IMO:
+ srcFreqHz = CY_CLK_IMO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_EXT:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+
+ #if (SRSS_ECO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ECO:
+ srcFreqHz = CY_CLK_ECO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ECO_PRESENT == 1U) */
+
+#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_ALTHF:
+ srcFreqHz = cy_BleEcoClockFreqHz;
+ break;
+#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
+
+ case CY_ROOT_PATH_SRC_DSI_MUX:
+ {
+ uint32_t dsi_src;
+ dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
+ switch (dsi_src)
+ {
+ case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+
+ case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
+ srcFreqHz = CY_CLK_WCO_FREQ_HZ;
+ break;
+
+ #if (SRSS_ALTLF_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
+ srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
+ break;
+ #endif /* (SRSS_ALTLF_PRESENT == 1U) */
+
+ #if (SRSS_PILO_PRESENT == 1U)
+ case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
+ srcFreqHz = CY_CLK_PILO_FREQ_HZ;
+ break;
+ #endif /* (SRSS_PILO_PRESENT == 1U) */
+
+ default:
+ srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
+ break;
+ }
+ }
+ break;
+
+ default:
+ srcFreqHz = CY_CLK_EXT_FREQ_HZ;
+ break;
+ }
+
+ if (rootPath == 0UL)
+ {
+ /* FLL */
+ bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
+ bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
+ bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
+ (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
+ if ((fllOutputAuto && fllLocked) || fllOutputOutput)
+ {
+ uint32_t fllMult;
+ uint32_t refDiv;
+ uint32_t outputDiv;
+
+ fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
+ refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
+ outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
+
+ pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else if (rootPath == 1UL)
+ {
+ /* PLL */
+ bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL]));
+ bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]));
+ bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) ||
+ (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])));
+ if ((pllOutputAuto && pllLocked) || pllOutputOutput)
+ {
+ uint32_t feedbackDiv;
+ uint32_t referenceDiv;
+ uint32_t outputDiv;
+
+ feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+ referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+ outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
+
+ pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
+
+ }
+ else
+ {
+ pathFreqHz = srcFreqHz;
+ }
+ }
+ else
+ {
+ /* Direct */
+ pathFreqHz = srcFreqHz;
+ }
+
+ /* Get frequency after hf_clk pre-divider */
+ pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
+ cy_Hfclk0FreqHz = pathFreqHz;
+
+ /* Fast Clock Divider */
+ fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
+
+ /* Peripheral Clock Divider */
+ periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
+ cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
+
+ pathFreqHz = pathFreqHz / fastClkDiv;
+ SystemCoreClock = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqHz = SystemCoreClock;
+ cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+ cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInitFpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void Cy_SystemInitFpuEnable(void)
+{
+ #if defined (__FPU_USED) && (__FPU_USED == 1U)
+ uint32_t interruptState;
+ interruptState = Cy_SaveIRQ();
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+ __DSB();
+ __ISB();
+ Cy_RestoreIRQ(interruptState);
+ #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,81 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/*----------------------------------------------------------------------------*/ +/** Config options. */ +/*----------------------------------------------------------------------------*/ +/** ALTHF (BLE ECO) frequency in Hz */ +#define CYDEV_CLK_ALTHF__HZ ( 8000000UL) + +/*----------------------------------------------------------------------------*/ + +#include "cmsis.h" +#include "objects.h" + +/* + * Board clocks. + */ +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ ( 8000000UL) +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ ( 32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ ( 32768UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ ( 32000UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ ( 32768UL) + +/** Default HFClk frequency in Hz */ +#ifndef CY_CLK_HFCLK0_FREQ_HZ +#define CY_CLK_HFCLK0_FREQ_HZ (100000000UL) +#endif + +/** Default PeriClk frequency in Hz */ +#ifndef CY_CLK_PERICLK_FREQ_HZ +#define CY_CLK_PERICLK_FREQ_HZ (CY_CLK_HFCLK0_FREQ_HZ / 2) +#endif + +/** Default SlowClk system core frequency in Hz */ +#ifndef CY_CLK_SYSTEM_FREQ_HZ +#define CY_CLK_SYSTEM_FREQ_HZ (CY_CLK_PERICLK_FREQ_HZ) +#endif + + +/** Interrupt assignment for CM0+ core. + * On PSoC6 CM0+ core physical interrupt are routed into NVIC through a programmable + * multiplexer. This requires that we define which of the 32 NVIC channels is used + * by which interrupt. This is done here. + */ +#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)0) +#define CY_M0_CORE_IRQ_CHANNEL_SERIAL ((IRQn_Type)4) +#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)3) + +/** Identifiers used in allocation of NVIC channels. + */ +#define CY_US_TICKER_IRQN_ID (0x100) +#define CY_SERIAL_IRQN_ID (0x200) +#define CY_BLE_IRQN_ID (0x300) +#define CY_GPIO_IRQN_ID (0x400) +#define CY_LP_TICKER_IRQN_ID (0x500) +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "cy_device_headers.h" +#undef BLE + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1280 @@
+/***************************************************************************//**
+* \file cy8c6347bzi_bld53.h
+*
+* \brief
+* CY8C6347BZI-BLD53 device header
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CY8C6347BZI_BLD53_H_
+#define _CY8C6347BZI_BLD53_H_
+
+/**
+* \addtogroup group_device CY8C6347BZI-BLD53
+* \{
+*/
+
+/**
+* \addtogroup Configuration_of_CMSIS
+* \{
+*/
+
+/*******************************************************************************
+* Interrupt Number Definition
+*******************************************************************************/
+
+typedef enum {
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+ /* ARM Cortex-M0+ Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */
+ NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */
+ NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */
+ NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */
+ NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */
+ NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */
+ NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */
+ NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */
+ NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */
+ NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */
+ NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */
+ NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */
+ NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */
+ NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */
+ NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */
+ NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */
+ NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */
+ NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */
+ NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */
+ NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */
+ NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */
+ NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */
+ NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */
+ NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */
+ NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */
+ NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */
+ NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */
+ NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */
+ NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */
+ NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */
+ NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */
+ NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */
+ NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#else
+ /* ARM Cortex-M4 Core Interrupt Numbers */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ /* CY8C6347BZI-BLD53 Peripheral Interrupt Numbers */
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ unconnected_IRQn = 240 /*!< 240 Unconnected */
+#endif
+} IRQn_Type;
+
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* CY8C6347BZI-BLD53 interrupts that can be routed to the CM0+ NVIC */
+typedef enum {
+ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
+ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
+ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
+ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
+ ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
+ ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
+ ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
+ ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
+ ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
+ ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
+ ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
+ ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
+ ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
+ ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
+ ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
+ ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
+ ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
+ lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
+ scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
+ srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+ srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
+ srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
+ bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
+ cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
+ cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
+ cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
+ cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
+ cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
+ cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
+ cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
+ cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
+ cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
+ cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
+ cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
+ cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
+ cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
+ cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
+ cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
+ cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
+ scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
+ scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
+ scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
+ scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
+ scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
+ scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
+ scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
+ scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
+ csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
+ cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
+ cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
+ cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
+ cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
+ cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
+ cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
+ cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
+ cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
+ cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
+ cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
+ cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
+ cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
+ cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
+ cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
+ cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
+ cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
+ cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
+ cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
+ cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
+ cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
+ cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
+ cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
+ cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
+ cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
+ cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
+ cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
+ cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
+ cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
+ cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
+ cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
+ cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
+ cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
+ cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
+ cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
+ cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
+ cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
+ cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
+ cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
+ cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
+ cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
+ tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
+ tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
+ tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
+ tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
+ tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
+ tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
+ tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
+ tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
+ tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
+ tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
+ tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
+ tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
+ tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
+ tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
+ tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
+ tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
+ tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
+ tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
+ tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
+ tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
+ tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
+ tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
+ tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
+ tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
+ tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
+ tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
+ tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
+ tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
+ tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
+ tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
+ tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
+ tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
+ udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
+ udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
+ udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
+ udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
+ udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
+ udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
+ udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
+ udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
+ udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
+ udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
+ udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
+ udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
+ udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
+ udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
+ udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
+ udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
+ pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
+ audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
+ audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
+ profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
+ smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
+ usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
+ usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
+ usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
+ pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
+ disconnected_IRQn = 240 /*!< 240 Disconnected */
+} cy_en_intr_t;
+
+#endif
+
+/*******************************************************************************
+* Processor and Core Peripheral Section
+*******************************************************************************/
+
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
+ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
+
+/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
+#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
+#include "system_psoc63.h" /*!< PSoC 63 System */
+
+#else
+
+/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __CM0P_PRESENT 1 /*!< CM0P present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_psoc63.h" /*!< PSoC 63 System */
+
+#endif
+
+#include "psoc63_config.h"
+#include "gpio_psoc63_116_bga_ble.h"
+
+/* Memory Blocks */
+#define CY_ROM_BASE 0x00000000UL
+#define CY_ROM_SIZE 0x00020000UL
+#define CY_SRAM0_BASE 0x08000000UL
+#define CY_SRAM0_SIZE 0x00048000UL
+#define CY_FLASH_BASE 0x10000000UL
+#define CY_FLASH_SIZE 0x00100000UL
+#define CY_EM_EEPROM_BASE 0x14000000UL
+#define CY_EM_EEPROM_SIZE 0x00008000UL
+#define CY_XIP_BASE 0x18000000UL
+#define CY_XIP_SIZE 0x08000000UL
+#define CY_SFLASH_BASE 0x16000000UL
+#define CY_SFLASH_SIZE 0x00008000UL
+#define CY_EFUSE_BASE 0x402C0800UL
+#define CY_EFUSE_SIZE 0x000000C8UL
+
+#define CY_DEVICE_PSOC6ABLE2
+#define CY_SILICON_ID 0xE2072100UL
+#define CY_HF_CLK_MAX_FREQ 150000000UL
+
+#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
+#define SCB_GET_EZ_DATA_NR(base) 256u
+#define SCB_IS_I2C_SLAVE_CAPABLE(base) true
+#define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8)
+#define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8)
+#define SCB_IS_SPI_SLAVE_CAPABLE(base) true
+#define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8)
+#define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8)
+#define SCB_IS_UART_CAPABLE(base) ((base) != SCB8)
+
+/* IP List */
+#define CY_IP_MXTCPWM 1u
+#define CY_IP_MXTCPWM_INSTANCES 2u
+#define CY_IP_MXTCPWM_VERSION 1u
+#define CY_IP_MXCSDV2 1u
+#define CY_IP_MXCSDV2_INSTANCES 1u
+#define CY_IP_MXCSDV2_VERSION 1u
+#define CY_IP_MXLCD 1u
+#define CY_IP_MXLCD_INSTANCES 1u
+#define CY_IP_MXLCD_VERSION 1u
+#define CY_IP_MXS40SRSS 1u
+#define CY_IP_MXS40SRSS_INSTANCES 1u
+#define CY_IP_MXS40SRSS_VERSION 1u
+#define CY_IP_MXS40SRSS_RTC 1u
+#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
+#define CY_IP_MXS40SRSS_RTC_VERSION 1u
+#define CY_IP_MXS40SRSS_MCWDT 1u
+#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
+#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
+#define CY_IP_MXSCB 1u
+#define CY_IP_MXSCB_INSTANCES 9u
+#define CY_IP_MXSCB_VERSION 1u
+#define CY_IP_MXPERI 1u
+#define CY_IP_MXPERI_INSTANCES 1u
+#define CY_IP_MXPERI_VERSION 1u
+#define CY_IP_MXPERI_TR 1u
+#define CY_IP_MXPERI_TR_INSTANCES 1u
+#define CY_IP_MXPERI_TR_VERSION 1u
+#define CY_IP_M4CPUSS 1u
+#define CY_IP_M4CPUSS_INSTANCES 1u
+#define CY_IP_M4CPUSS_VERSION 1u
+#define CY_IP_M4CPUSS_DMA 1u
+#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
+#define CY_IP_M4CPUSS_DMA_VERSION 1u
+#define CY_IP_MXCRYPTO 1u
+#define CY_IP_MXCRYPTO_INSTANCES 1u
+#define CY_IP_MXCRYPTO_VERSION 1u
+#define CY_IP_MXBLESS 1u
+#define CY_IP_MXBLESS_INSTANCES 1u
+#define CY_IP_MXBLESS_VERSION 1u
+#define CY_IP_MXAUDIOSS 1u
+#define CY_IP_MXAUDIOSS_INSTANCES 1u
+#define CY_IP_MXAUDIOSS_VERSION 1u
+#define CY_IP_MXLPCOMP 1u
+#define CY_IP_MXLPCOMP_INSTANCES 1u
+#define CY_IP_MXLPCOMP_VERSION 1u
+#define CY_IP_MXS40PASS 1u
+#define CY_IP_MXS40PASS_INSTANCES 1u
+#define CY_IP_MXS40PASS_VERSION 1u
+#define CY_IP_MXS40PASS_SAR 1u
+#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
+#define CY_IP_MXS40PASS_SAR_VERSION 1u
+#define CY_IP_MXS40PASS_CTDAC 1u
+#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
+#define CY_IP_MXS40PASS_CTB 1u
+#define CY_IP_MXS40PASS_CTB_INSTANCES 1u
+#define CY_IP_MXS40PASS_CTB_VERSION 1u
+#define CY_IP_MXSMIF 1u
+#define CY_IP_MXSMIF_INSTANCES 1u
+#define CY_IP_MXSMIF_VERSION 1u
+#define CY_IP_MXS40IOSS 1u
+#define CY_IP_MXS40IOSS_INSTANCES 1u
+#define CY_IP_MXS40IOSS_VERSION 1u
+#define CY_IP_MXEFUSE 1u
+#define CY_IP_MXEFUSE_INSTANCES 1u
+#define CY_IP_MXEFUSE_VERSION 1u
+#define CY_IP_MXUDB 1u
+#define CY_IP_MXUDB_INSTANCES 1u
+#define CY_IP_MXUDB_VERSION 1u
+#define CY_IP_MXPROFILE 1u
+#define CY_IP_MXPROFILE_INSTANCES 1u
+#define CY_IP_MXPROFILE_VERSION 1u
+
+/* Include IP definitions */
+#include "cyip_sflash.h"
+#include "cyip_peri.h"
+#include "cyip_crypto.h"
+#include "cyip_cpuss.h"
+#include "cyip_fault.h"
+#include "cyip_ipc.h"
+#include "cyip_prot.h"
+#include "cyip_flashc.h"
+#include "cyip_srss.h"
+#include "cyip_backup.h"
+#include "cyip_dw.h"
+#include "cyip_efuse.h"
+#include "cyip_efuse_data.h"
+#include "cyip_profile.h"
+#include "cyip_hsiom.h"
+#include "cyip_gpio.h"
+#include "cyip_smartio.h"
+#include "cyip_udb.h"
+#include "cyip_lpcomp.h"
+#include "cyip_csd.h"
+#include "cyip_tcpwm.h"
+#include "cyip_lcd.h"
+#include "cyip_ble.h"
+#include "cyip_smif.h"
+#include "cyip_scb.h"
+#include "cyip_ctbm.h"
+#include "cyip_ctdac.h"
+#include "cyip_sar.h"
+#include "cyip_pass.h"
+#include "cyip_i2s.h"
+#include "cyip_pdm.h"
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_BASE 0x16000000UL
+#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_BASE 0x40010000UL
+#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
+#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
+#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
+#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
+#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
+#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
+#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
+#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
+#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
+#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
+#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
+#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
+#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
+#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
+#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
+#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
+#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
+#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
+#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
+#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
+#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
+#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
+#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
+#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
+#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
+#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
+#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
+#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
+#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
+#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
+#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
+#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
+#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
+#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
+#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
+#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
+#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
+#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
+#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
+#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
+#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
+#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
+#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
+#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
+#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
+#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
+#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
+#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
+#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
+#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
+#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
+#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
+#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
+#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
+#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
+#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
+#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
+#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
+#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
+#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
+#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
+#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
+#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
+#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
+#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
+#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
+#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
+#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
+#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
+#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
+#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
+#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
+#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
+#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
+#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
+#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
+#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
+#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
+#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
+#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
+#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
+#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
+#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
+#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
+#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
+#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
+#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
+#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
+#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
+#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
+#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
+#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
+#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
+#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
+#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
+#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
+#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
+#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
+#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
+#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
+#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
+#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
+#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
+#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
+#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
+#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
+#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
+#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
+#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
+#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
+#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
+#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
+#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
+#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
+#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
+#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
+#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
+#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
+#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
+#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
+#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
+#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
+#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
+#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
+#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
+#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
+#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
+#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
+#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
+#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
+#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
+#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
+#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
+#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
+#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
+#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
+#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
+#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
+#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
+#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
+#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
+#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
+#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
+#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
+#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
+#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
+#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
+#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
+#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
+#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
+#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
+#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
+#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
+#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
+#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
+#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
+#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
+#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
+#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
+#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
+#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
+#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
+#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
+#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
+#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
+#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
+#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
+#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
+#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
+#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
+#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
+#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
+#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
+#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
+#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
+#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
+#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
+#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
+#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
+
+/*******************************************************************************
+* CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_BASE 0x40110000UL
+#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_BASE 0x40210000UL
+#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_BASE 0x40220000UL
+#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
+#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
+#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_BASE 0x40230000UL
+#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
+#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
+#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
+#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
+#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
+#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
+#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
+#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
+#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
+#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
+#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
+#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
+#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
+#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
+#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
+#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
+#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
+#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
+#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
+#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
+#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
+#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
+#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
+#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
+#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
+#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
+#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
+#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
+#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
+#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
+#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
+#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
+#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_BASE 0x40240000UL
+#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
+#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
+#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
+#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
+#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
+#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
+#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
+#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
+#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
+#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
+#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
+#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
+#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
+#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
+#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
+#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
+#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
+#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
+#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
+#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
+#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
+#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
+#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
+#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
+#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
+#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
+#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
+#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
+#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
+#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
+#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
+#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
+#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
+#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
+#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
+#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
+#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
+#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
+#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
+#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
+#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
+#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
+#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
+#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
+#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
+#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
+#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
+#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
+#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
+#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_BASE 0x40250000UL
+#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
+#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
+
+/*******************************************************************************
+* SRSS
+*******************************************************************************/
+
+#define SRSS_BASE 0x40260000UL
+#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
+#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
+#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_BASE 0x40270000UL
+#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW0_BASE 0x40280000UL
+#define DW1_BASE 0x40281000UL
+#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
+#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
+#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
+#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
+#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
+#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
+#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
+#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
+#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
+#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
+#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
+#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
+#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
+#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
+#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
+#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
+#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
+#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
+#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
+#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
+#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
+#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
+#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
+#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
+#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
+#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
+#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
+#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
+#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
+#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
+#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
+#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
+#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
+#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
+
+/*******************************************************************************
+* EFUSE
+*******************************************************************************/
+
+#define EFUSE_BASE 0x402C0000UL
+#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define PROFILE_BASE 0x402D0000UL
+#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
+#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
+#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
+#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
+#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
+#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
+#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
+#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
+#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_BASE 0x40310000UL
+#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
+#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
+#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
+#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
+#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
+#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
+#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
+#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
+#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
+#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
+#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
+#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
+#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
+#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
+#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
+#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_BASE 0x40320000UL
+#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
+#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
+#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
+#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
+#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
+#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
+#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
+#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
+#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
+#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
+#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
+#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
+#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
+#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
+#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
+#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_BASE 0x40330000UL
+#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
+#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
+#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
+
+/*******************************************************************************
+* UDB
+*******************************************************************************/
+
+#define UDB_BASE 0x40340000UL
+#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */
+#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */
+#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */
+#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */
+#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */
+#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */
+#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */
+#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */
+#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */
+#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */
+#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */
+#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */
+#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */
+#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */
+#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */
+#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */
+#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */
+#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */
+#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */
+#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */
+#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */
+#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */
+#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */
+#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */
+#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */
+#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */
+#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */
+#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */
+#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */
+#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */
+#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */
+#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */
+#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */
+#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */
+#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */
+#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */
+#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */
+#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */
+#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */
+#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */
+#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */
+#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */
+#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */
+#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */
+#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */
+#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */
+#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */
+#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */
+#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */
+#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */
+#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */
+#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */
+#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_BASE 0x40350000UL
+#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
+
+/*******************************************************************************
+* CSD
+*******************************************************************************/
+
+#define CSD0_BASE 0x40360000UL
+#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM0_BASE 0x40380000UL
+#define TCPWM1_BASE 0x40390000UL
+#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
+#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
+#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
+#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
+#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
+#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
+#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
+#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
+#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
+#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
+#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
+#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
+#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
+#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
+#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
+#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
+#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
+#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
+#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
+#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
+#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
+#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
+#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
+#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
+#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
+#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
+#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
+#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
+#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
+#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
+#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
+#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
+#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
+#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD0_BASE 0x403B0000UL
+#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
+
+/*******************************************************************************
+* BLE
+*******************************************************************************/
+
+#define BLE_BASE 0x403C0000UL
+#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */
+#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */
+#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */
+#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */
+#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF0_BASE 0x40420000UL
+#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
+#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
+#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
+#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
+#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB0_BASE 0x40610000UL
+#define SCB1_BASE 0x40620000UL
+#define SCB2_BASE 0x40630000UL
+#define SCB3_BASE 0x40640000UL
+#define SCB4_BASE 0x40650000UL
+#define SCB5_BASE 0x40660000UL
+#define SCB6_BASE 0x40670000UL
+#define SCB7_BASE 0x40680000UL
+#define SCB8_BASE 0x40690000UL
+#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
+#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
+#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
+#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
+#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
+#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
+#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
+#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
+#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
+
+/*******************************************************************************
+* CTBM
+*******************************************************************************/
+
+#define CTBM0_BASE 0x41100000UL
+#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC0_BASE 0x41140000UL
+#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_BASE 0x411D0000UL
+#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
+
+/*******************************************************************************
+* PASS
+*******************************************************************************/
+
+#define PASS_BASE 0x411F0000UL
+#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
+#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define I2S0_BASE 0x42A10000UL
+#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM0_BASE 0x42A20000UL
+#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
+
+/* Backward compabitility definitions */
+#define I2S I2S0
+#define PDM PDM0
+
+/** \} CY8C6347BZI-BLD53 */
+
+#endif /* _CY8C6347BZI_BLD53_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,69 @@ +/***************************************************************************//** +* \file cy_device_headers.h +* +* \brief +* Common header file to be included by the drivers. +* +* \note +* Generator version: 1.2.0.117 +* Database revision: rev#1034984 +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _CY_DEVICE_HEADERS_H_ +#define _CY_DEVICE_HEADERS_H_ + +#if defined (CY8C6336BZI_BLF03) + #include "cy8c6336bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF03) + #include "cy8c6316bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF53) + #include "cy8c6316bzi_blf53.h" +#elif defined (CY8C6336BZI_BLD13) + #include "cy8c6336bzi_bld13.h" +#elif defined (CY8C6347BZI_BLD43) + #include "cy8c6347bzi_bld43.h" +#elif defined (CY8C6347BZI_BLD33) + #include "cy8c6347bzi_bld33.h" +#elif defined (CY8C6347BZI_BLD53) + #include "cy8c6347bzi_bld53.h" +#elif defined (CY8C6347FMI_BLD13) + #include "cy8c6347fmi_bld13.h" +#elif defined (CY8C6347FMI_BLD43) + #include "cy8c6347fmi_bld43.h" +#elif defined (CY8C6347FMI_BLD33) + #include "cy8c6347fmi_bld33.h" +#elif defined (CY8C6347FMI_BLD53) + #include "cy8c6347fmi_bld53.h" +#elif defined (CY8C637BZI_MD76) + #include "cy8c637bzi_md76.h" +#elif defined (CY8C637BZI_BLD74) + #include "cy8c637bzi_bld74.h" +#elif defined (CY8C637FMI_BLD73) + #include "cy8c637fmi_bld73.h" +#elif defined (CY8C68237BZ_BLE) + #include "cy8c68237bz_ble.h" +#elif defined (CY8C68237FM_BLE) + #include "cy8c68237fm_ble.h" +#elif defined (CY8C6336BZI_BUD13) + #include "cy8c6336bzi_bud13.h" +#elif defined (CY8C6347BZI_BUD43) + #include "cy8c6347bzi_bud43.h" +#elif defined (CY8C6347BZI_BUD33) + #include "cy8c6347bzi_bud33.h" +#elif defined (CY8C6347BZI_BUD53) + #include "cy8c6347bzi_bud53.h" +#elif defined (CY8C6337BZI_BLF13) + #include "cy8c6337bzi_blf13.h" +#else + #error Undefined part number +#endif + +#endif /* _CY_DEVICE_HEADERS_H_ */ + + +/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,190 @@
+/***************************************************************************//**
+* \file cy_ipc_config.c
+* \version 1.10.1
+*
+* Description:
+* This C file is not intended to be part of the IPC driver. It is the code
+* required to configure the device specific IPC channels for semaphores
+* and pipes.
+*
+********************************************************************************
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "ipc/cy_ipc_drv.h"
+#include "ipc/cy_ipc_pipe.h"
+#include "ipc/cy_ipc_sema.h"
+
+#include "cy_ipc_config.h"
+
+/* Create an array of endpoint structures */
+static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS];
+
+#define CY_CYPIPE_DEFAULT_CONFIG \
+{\
+ /* .ep0ConfigData */ {\
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,\
+ /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP0,\
+ /* .ipcNotifierMuxNumber */ CY_IPC_INTR_CYPIPE_MUX_EP0,\
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,\
+ /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP0\
+ },\
+ /* .ep1ConfigData */ {\
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,\
+ /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP1,\
+ /* .ipcNotifierMuxNumber */ 0u,\
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,\
+ /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP1\
+ },\
+ /* .endpointClientsCount */ CY_IPC_CYPIPE_CLIENT_CNT,\
+ /* .endpointsCallbacksArray */ cy_ipc_pipe_sysCbArray,\
+ /* .userPipeIsrHandler */ &Cy_IPC_SystemPipeIsr\
+}
+
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_SystemSemaInit
+****************************************************************************//**
+*
+* Initializes the system semaphores. The system semaphores are used by Flash.
+*
+* This function is called in the SystemInit() function. If the default startup
+* file is not used, or SystemInit() is not called in your project,
+* call the following three functions prior to executing any flash or EmEEPROM
+* write or erase operation:
+* -# Cy_IPC_SystemSemaInit()
+* -# Cy_IPC_SystemPipeInit()
+* -# Cy_Flash_Init()
+*
+*******************************************************************************/
+void Cy_IPC_SystemSemaInit(void)
+{
+/* Create array used for semaphores */
+#if !(CY_CPU_CORTEX_M0P)
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+#else
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+#endif
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_UserPipeIsr
+****************************************************************************//**
+*
+* This is the interrupt service routine for the user pipe.
+*
+*******************************************************************************/
+void Cy_IPC_UserPipeIsr(void)
+{
+ Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_USRPIPE_ADDR]);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_RpcPipeIsr
+****************************************************************************//**
+*
+* This is the interrupt service routine for the RPC pipe.
+*
+*******************************************************************************/
+void Cy_IPC_RpcPipeIsr(void)
+{
+ Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_RPCPIPE_ADDR]);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_SystemPipeInit
+****************************************************************************//**
+*
+* Initializes the system pipes. The system pipes are used by BLE and Flash.
+* \note The function should be called on all CPUs.
+*
+* This function is called in the SystemInit() function. If the default startup
+* file is not used, or SystemInit() is not called in your project,
+* call the following three functions prior to executing any flash or EmEEPROM
+* write or erase operation:
+* -# Cy_IPC_SystemSemaInit()
+* -# Cy_IPC_SystemPipeInit()
+* -# Cy_Flash_Init()
+*
+* Also this function is called to support BLE host/controller communication.
+*
+*******************************************************************************/
+void Cy_IPC_SystemPipeInit(void)
+{
+ uint32_t intr;
+
+ intr = Cy_SysLib_EnterCriticalSection();
+
+ static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_sysCbArray[CY_IPC_CYPIPE_CLIENT_CNT];
+ static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_userCbArray[CY_IPC_USRPIPE_CLIENT_CNT];
+ static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_rpcCbArray[CY_IPC_RPCPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemPipeConfig = CY_CYPIPE_DEFAULT_CONFIG;
+ static const cy_stc_ipc_pipe_config_t userPipeConfig = {
+ .ep0ConfigData = {
+ .ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM0,
+ .ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP0,
+ .ipcNotifierMuxNumber = CY_IPC_INTR_USRPIPE_MUX_EP0,
+ .epAddress = CY_IPC_EP_USRPIPE_CM0_ADDR,
+ .epConfig = CY_IPC_USRPIPE_CONFIG_EP0
+ },
+ .ep1ConfigData = {
+ .ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM4,
+ .ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP1,
+ .ipcNotifierMuxNumber = 0u,
+ .epAddress = CY_IPC_EP_USRPIPE_CM4_ADDR,
+ .epConfig = CY_IPC_USRPIPE_CONFIG_EP1
+ },
+ .endpointClientsCount = CY_IPC_USRPIPE_CLIENT_CNT,
+ .endpointsCallbacksArray = cy_ipc_pipe_userCbArray,
+ .userPipeIsrHandler = &Cy_IPC_UserPipeIsr
+ };
+ static const cy_stc_ipc_pipe_config_t rpcPipeConfig = {
+ .ep0ConfigData = {
+ .ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM0,
+ .ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP0,
+ .ipcNotifierMuxNumber = CY_IPC_INTR_RPCPIPE_MUX_EP0,
+ .epAddress = CY_IPC_EP_RPCPIPE_CM0_ADDR,
+ .epConfig = CY_IPC_RPCPIPE_CONFIG_EP0
+ },
+ .ep1ConfigData = {
+ .ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM4,
+ .ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP1,
+ .ipcNotifierMuxNumber = 0u,
+ .epAddress = CY_IPC_EP_RPCPIPE_CM4_ADDR,
+ .epConfig = CY_IPC_RPCPIPE_CONFIG_EP1
+ },
+ .endpointClientsCount = CY_IPC_RPCPIPE_CLIENT_CNT,
+ .endpointsCallbacksArray = cy_ipc_pipe_rpcCbArray,
+ .userPipeIsrHandler = &Cy_IPC_RpcPipeIsr
+ };
+
+ Cy_IPC_Pipe_Config(cy_ipc_pipe_sysEpArray);
+
+ Cy_IPC_Pipe_Init(&systemPipeConfig);
+ Cy_IPC_Pipe_Init(&userPipeConfig);
+ Cy_IPC_Pipe_Init(&rpcPipeConfig);
+
+ Cy_SysLib_ExitCriticalSection(intr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_SystemPipeIsr
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_IPC_SystemPipeIsr(void)
+{
+ Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]);
+}
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,219 @@
+/***************************************************************************//**
+* \file cy_ipc_config.h
+* \version 1.10.1
+*
+* \brief
+* This header file is not intended to be part of the IPC driver since it defines
+* a device specific configuration for the IPC channels and pipes.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef CY_IPC_CONFIG_H
+#define CY_IPC_CONFIG_H
+
+/* IPC Resources */
+#define CY_IPC_CHANNELS (uint32_t)(CPUSS_IPC_IPC_NR)
+#define CY_IPC_INTERRUPTS (uint32_t)(CPUSS_IPC_IPC_IRQ_NR)
+
+/* IPC channel definitions */
+#define CY_IPC_CHAN_SYSCALL_CM0 (0u) /* System calls for the CM0 processor */
+#define CY_IPC_CHAN_SYSCALL_CM4 (1u) /* System calls for the 1st non-CM0 processor */
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM0
+ #define Cy_IPC_SystemPipeIsr NvicMux1_IRQHandler
+#else
+ #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM4
+ #define Cy_IPC_SystemPipeIsr cpuss_interrupts_ipc_4_IRQHandler
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+#define CY_IPC_CHAN_SYSCALL_DAP (uint32_t)(2u) /**< System calls for the DAP */
+#define CY_IPC_CHAN_CRYPTO (uint32_t)(3u) /**< IPC data channel for the Crypto */
+#define CY_IPC_CHAN_SEMA (uint32_t)(4u) /**< IPC data channel for the Semaphores */
+
+#define CY_IPC_CHAN_CYPIPE_EP0 (uint32_t)(5u) /**< IPC data channel for CYPIPE EP0 */
+#define CY_IPC_CHAN_CYPIPE_EP1 (uint32_t)(6u) /**< IPC data channel for CYPIPE EP1 */
+
+/* IPC Notify interrupts definitions */
+#define CY_IPC_INTR_SYSCALL1 (uint32_t)(0u)
+
+#define CY_IPC_INTR_CRYPTO_SRV (uint32_t)(1u) /**< IPC interrupt structure for the Crypto server */
+#define CY_IPC_INTR_CRYPTO_CLI (uint32_t)(2u) /**< IPC interrupt structure for the Crypto client */
+
+#define CY_IPC_INTR_SPARE (uint32_t)(7u)
+
+/* IPC Semaphores allocation
+ This will allow 128 (4*32) semaphores */
+#define CY_IPC_SEMA_COUNT (uint32_t)(128u)
+
+/* IPC Pipe definitions */
+#define CY_IPC_MAX_ENDPOINTS (uint32_t)(8u)
+
+/*******************************************************************************
+** CY_PIPE default configuration
+*******************************************************************************/
+#define CY_IPC_CYPIPE_CLIENT_CNT (uint32_t)(8u)
+#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u)
+#define CY_IPC_RPCPIPE_CLIENT_CNT (uint32_t)(16u)
+
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR
+#else
+ #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM4_ADDR
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+#define CY_IPC_INTR_CYPIPE_MUX_EP0 (uint32_t)(1u) /* IPC CYPRESS PIPE */
+#define CY_IPC_INTR_CYPIPE_EP0 (uint32_t)(3u) /* Notifier EP0 */
+#define CY_IPC_INTR_CYPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_INTR_CYPIPE_EP1 (uint32_t)(4u) /* Notifier EP1 */
+#define CY_IPC_INTR_CYPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_CYPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_IPC_CYPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP1)
+
+/* Endpoint indexes in the pipe array */
+#define CY_IPC_EP_CYPIPE_CM0_ADDR (uint32_t)(0u)
+#define CY_IPC_EP_CYPIPE_CM4_ADDR (uint32_t)(1u)
+
+/******************************************************************************/
+
+/*
+ * The System pipe configuration defines the IPC channel number, interrupt
+ * number, and the pipe interrupt mask for the endpoint.
+ *
+ * The format of the endPoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+
+/* System Pipe addresses */
+/* CyPipe defines */
+
+#define CY_IPC_CYPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_IPC_CYPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP1)
+#define CY_IPC_CYPIPE_INTR_MASK (uint32_t)( CY_IPC_CYPIPE_CHAN_MASK_EP0 | CY_IPC_CYPIPE_CHAN_MASK_EP1 )
+
+/******************************************************************************/
+#define CY_IPC_CHAN_USRPIPE_CM0 (uint32_t)(8u)
+#define CY_IPC_CHAN_USRPIPE_CM4 (uint32_t)(9u)
+
+#define CY_IPC_INTR_USRPIPE_CM0 (uint32_t)(8u)
+#define CY_IPC_INTR_USRPIPE_CM4 (uint32_t)(9u)
+
+#define CY_IPC_EP_USRPIPE_ADDR_EP0 (uint32_t)(2u)
+#define CY_IPC_EP_USRPIPE_ADDR_EP1 (uint32_t)(3u)
+
+/* Endpoint indexes in the pipe array */
+#define CY_IPC_EP_USRPIPE_CM0_ADDR (uint32_t)(2u)
+#define CY_IPC_EP_USRPIPE_CM4_ADDR (uint32_t)(3u)
+
+
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM0_ADDR
+ #define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM4_ADDR
+#else
+ #define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM4_ADDR
+ #define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM0_ADDR
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+#define CY_IPC_INTR_USRPIPE_MUX_EP0 (uint32_t)(2u)
+#define CY_IPC_INTR_USRPIPE_EP0 CY_IPC_INTR_USRPIPE_CM0
+#define CY_IPC_INTR_USRPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_INTR_USRPIPE_EP1 CY_IPC_INTR_USRPIPE_CM4
+#define CY_IPC_INTR_USRPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_USRPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM0)
+#define CY_IPC_USRPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM4)
+
+
+#define CY_IPC_USRPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_USRPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_USRPIPE_CM0)
+#define CY_IPC_USRPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_USRPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_USRPIPE_CM4)
+#define CY_IPC_USRPIPE_INTR_MASK (uint32_t)( CY_IPC_USRPIPE_CHAN_MASK_EP0 | CY_IPC_USRPIPE_CHAN_MASK_EP1 )
+
+
+/******************************************************************************/
+#define CY_IPC_CHAN_RPCPIPE_CM0 (uint32_t)(10u)
+#define CY_IPC_CHAN_RPCPIPE_CM4 (uint32_t)(11u)
+
+#define CY_IPC_INTR_RPCPIPE_CM0 (uint32_t)(10u)
+#define CY_IPC_INTR_RPCPIPE_CM4 (uint32_t)(11u)
+
+#define CY_IPC_EP_RPCPIPE_ADDR_EP0 (uint32_t)(4u)
+#define CY_IPC_EP_RPCPIPE_ADDR_EP1 (uint32_t)(5u)
+
+/* Endpoint indexes in the pipe array */
+#define CY_IPC_EP_RPCPIPE_CM0_ADDR (uint32_t)(4u)
+#define CY_IPC_EP_RPCPIPE_CM4_ADDR (uint32_t)(5u)
+
+
+#if (CY_CPU_CORTEX_M0P)
+ #define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM0_ADDR
+ #define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM4_ADDR
+#else
+ #define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM4_ADDR
+ #define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM0_ADDR
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+#define CY_IPC_INTR_RPCPIPE_MUX_EP0 (uint32_t)(4u)
+#define CY_IPC_INTR_RPCPIPE_EP0 CY_IPC_INTR_RPCPIPE_CM0
+#define CY_IPC_INTR_RPCPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_INTR_RPCPIPE_EP1 CY_IPC_INTR_RPCPIPE_CM4
+#define CY_IPC_INTR_RPCPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */
+
+#define CY_IPC_RPCPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM0)
+#define CY_IPC_RPCPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM4)
+
+
+#define CY_IPC_RPCPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_RPCPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_RPCPIPE_CM0)
+#define CY_IPC_RPCPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_RPCPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_RPCPIPE_CM4)
+#define CY_IPC_RPCPIPE_INTR_MASK (uint32_t)( CY_IPC_RPCPIPE_CHAN_MASK_EP0 | CY_IPC_RPCPIPE_CHAN_MASK_EP1 )
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/*
+* \addtogroup group_ipc_configuration_sema
+* \{
+*/
+void Cy_IPC_SystemSemaInit(void);
+/* \} group_ipc_configuration_sema */
+
+/*
+* \addtogroup group_ipc_configuration_cypipe
+* \{
+*/
+void Cy_IPC_SystemPipeInit(void);
+/* \} group_ipc_configuration_cypipe */
+
+void Cy_IPC_SystemPipeIsr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_IPC_CONFIG_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,56 @@
+/*******************************************************************************
+* File Name: cymetadata.c
+*
+* PSoC Creator 4.1
+*
+* Description:
+* This file defines all extra memory spaces that need to be included.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+********************************************************************************/
+
+
+#include "stdint.h"
+
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+#ifndef CY_META_SECTION
+#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used))
+#endif
+CY_META_SECTION
+#elif defined(__ICCARM__)
+
+#pragma location=".cymeta"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8_t cy_metadata[] = {
+#if defined(CY8C637BZI_BLD74)
+ 0x00u, 0x05u, 0xE2u, 0x01u, 0x11u, 0x00u, 0x00u, 0x01u,
+ 0x00u, 0x00u, 0x00u, 0x00u
+#elif defined(CY8C6347BZI_BLD53)
+ 0x00u, 0x05u, 0xE2u, 0x07u, 0x21u, 0x00u, 0x21u, 0x01u,
+ 0x00u, 0x00u, 0x00u, 0x00u
+#else
+#error "Unknown target device"
+#endif
+};
+
+#if defined(CY8C637BZI_BLD74)
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+#ifndef CY_CHIP_PROT_SECTION
+#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used))
+#endif
+CY_CHIP_PROT_SECTION
+#elif defined(__ICCARM__)
+#pragma location=".cychipprotect"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8_t cy_meta_chipprotect[] = {
+ 0x01u
+};
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1884 @@
+/***************************************************************************//**
+* \file gpio_psoc63_116_bga_ble.h
+*
+* \brief
+* PSoC 63 device GPIO header for 116-BGA-BLE package
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _GPIO_PSOC63_116_BGA_BLE_H_
+#define _GPIO_PSOC63_116_BGA_BLE_H_
+
+/* Package type */
+enum
+{
+ CY_GPIO_PACKAGE_QFN,
+ CY_GPIO_PACKAGE_BGA,
+ CY_GPIO_PACKAGE_CSP,
+ CY_GPIO_PACKAGE_WLCSP,
+ CY_GPIO_PACKAGE_LQFP,
+};
+
+#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA
+
+/* Port List */
+/* PORT 0 (GPIO) */
+#define P0_0_PORT GPIO_PRT0
+#define P0_0_PIN 0u
+#define P0_0_NUM 0u
+#define P0_1_PORT GPIO_PRT0
+#define P0_1_PIN 1u
+#define P0_1_NUM 1u
+#define P0_2_PORT GPIO_PRT0
+#define P0_2_PIN 2u
+#define P0_2_NUM 2u
+#define P0_3_PORT GPIO_PRT0
+#define P0_3_PIN 3u
+#define P0_3_NUM 3u
+#define P0_4_PORT GPIO_PRT0
+#define P0_4_PIN 4u
+#define P0_4_NUM 4u
+#define P0_5_PORT GPIO_PRT0
+#define P0_5_PIN 5u
+#define P0_5_NUM 5u
+
+/* PORT 1 (GPIO_OVT) */
+#define P1_0_PORT GPIO_PRT1
+#define P1_0_PIN 0u
+#define P1_0_NUM 0u
+#define P1_1_PORT GPIO_PRT1
+#define P1_1_PIN 1u
+#define P1_1_NUM 1u
+#define P1_2_PORT GPIO_PRT1
+#define P1_2_PIN 2u
+#define P1_2_NUM 2u
+#define P1_3_PORT GPIO_PRT1
+#define P1_3_PIN 3u
+#define P1_3_NUM 3u
+#define P1_4_PORT GPIO_PRT1
+#define P1_4_PIN 4u
+#define P1_4_NUM 4u
+#define P1_5_PORT GPIO_PRT1
+#define P1_5_PIN 5u
+#define P1_5_NUM 5u
+
+/* PORT 5 (GPIO) */
+#define P5_0_PORT GPIO_PRT5
+#define P5_0_PIN 0u
+#define P5_0_NUM 0u
+#define P5_1_PORT GPIO_PRT5
+#define P5_1_PIN 1u
+#define P5_1_NUM 1u
+#define P5_2_PORT GPIO_PRT5
+#define P5_2_PIN 2u
+#define P5_2_NUM 2u
+#define P5_3_PORT GPIO_PRT5
+#define P5_3_PIN 3u
+#define P5_3_NUM 3u
+#define P5_4_PORT GPIO_PRT5
+#define P5_4_PIN 4u
+#define P5_4_NUM 4u
+#define P5_5_PORT GPIO_PRT5
+#define P5_5_PIN 5u
+#define P5_5_NUM 5u
+#define P5_6_PORT GPIO_PRT5
+#define P5_6_PIN 6u
+#define P5_6_NUM 6u
+
+/* PORT 6 (GPIO) */
+#define P6_0_PORT GPIO_PRT6
+#define P6_0_PIN 0u
+#define P6_0_NUM 0u
+#define P6_1_PORT GPIO_PRT6
+#define P6_1_PIN 1u
+#define P6_1_NUM 1u
+#define P6_2_PORT GPIO_PRT6
+#define P6_2_PIN 2u
+#define P6_2_NUM 2u
+#define P6_3_PORT GPIO_PRT6
+#define P6_3_PIN 3u
+#define P6_3_NUM 3u
+#define P6_4_PORT GPIO_PRT6
+#define P6_4_PIN 4u
+#define P6_4_NUM 4u
+#define P6_5_PORT GPIO_PRT6
+#define P6_5_PIN 5u
+#define P6_5_NUM 5u
+#define P6_6_PORT GPIO_PRT6
+#define P6_6_PIN 6u
+#define P6_6_NUM 6u
+#define P6_7_PORT GPIO_PRT6
+#define P6_7_PIN 7u
+#define P6_7_NUM 7u
+
+/* PORT 7 (GPIO) */
+#define P7_0_PORT GPIO_PRT7
+#define P7_0_PIN 0u
+#define P7_0_NUM 0u
+#define P7_1_PORT GPIO_PRT7
+#define P7_1_PIN 1u
+#define P7_1_NUM 1u
+#define P7_2_PORT GPIO_PRT7
+#define P7_2_PIN 2u
+#define P7_2_NUM 2u
+#define P7_3_PORT GPIO_PRT7
+#define P7_3_PIN 3u
+#define P7_3_NUM 3u
+#define P7_4_PORT GPIO_PRT7
+#define P7_4_PIN 4u
+#define P7_4_NUM 4u
+#define P7_5_PORT GPIO_PRT7
+#define P7_5_PIN 5u
+#define P7_5_NUM 5u
+#define P7_6_PORT GPIO_PRT7
+#define P7_6_PIN 6u
+#define P7_6_NUM 6u
+#define P7_7_PORT GPIO_PRT7
+#define P7_7_PIN 7u
+#define P7_7_NUM 7u
+
+/* PORT 8 (GPIO) */
+#define P8_0_PORT GPIO_PRT8
+#define P8_0_PIN 0u
+#define P8_0_NUM 0u
+#define P8_1_PORT GPIO_PRT8
+#define P8_1_PIN 1u
+#define P8_1_NUM 1u
+#define P8_2_PORT GPIO_PRT8
+#define P8_2_PIN 2u
+#define P8_2_NUM 2u
+#define P8_3_PORT GPIO_PRT8
+#define P8_3_PIN 3u
+#define P8_3_NUM 3u
+#define P8_4_PORT GPIO_PRT8
+#define P8_4_PIN 4u
+#define P8_4_NUM 4u
+#define P8_5_PORT GPIO_PRT8
+#define P8_5_PIN 5u
+#define P8_5_NUM 5u
+#define P8_6_PORT GPIO_PRT8
+#define P8_6_PIN 6u
+#define P8_6_NUM 6u
+#define P8_7_PORT GPIO_PRT8
+#define P8_7_PIN 7u
+#define P8_7_NUM 7u
+
+/* PORT 9 (GPIO) */
+#define P9_0_PORT GPIO_PRT9
+#define P9_0_PIN 0u
+#define P9_0_NUM 0u
+#define P9_1_PORT GPIO_PRT9
+#define P9_1_PIN 1u
+#define P9_1_NUM 1u
+#define P9_2_PORT GPIO_PRT9
+#define P9_2_PIN 2u
+#define P9_2_NUM 2u
+#define P9_3_PORT GPIO_PRT9
+#define P9_3_PIN 3u
+#define P9_3_NUM 3u
+#define P9_4_PORT GPIO_PRT9
+#define P9_4_PIN 4u
+#define P9_4_NUM 4u
+#define P9_5_PORT GPIO_PRT9
+#define P9_5_PIN 5u
+#define P9_5_NUM 5u
+#define P9_6_PORT GPIO_PRT9
+#define P9_6_PIN 6u
+#define P9_6_NUM 6u
+#define P9_7_PORT GPIO_PRT9
+#define P9_7_PIN 7u
+#define P9_7_NUM 7u
+
+/* PORT 10 (GPIO) */
+#define P10_0_PORT GPIO_PRT10
+#define P10_0_PIN 0u
+#define P10_0_NUM 0u
+#define P10_1_PORT GPIO_PRT10
+#define P10_1_PIN 1u
+#define P10_1_NUM 1u
+#define P10_2_PORT GPIO_PRT10
+#define P10_2_PIN 2u
+#define P10_2_NUM 2u
+#define P10_3_PORT GPIO_PRT10
+#define P10_3_PIN 3u
+#define P10_3_NUM 3u
+#define P10_4_PORT GPIO_PRT10
+#define P10_4_PIN 4u
+#define P10_4_NUM 4u
+#define P10_5_PORT GPIO_PRT10
+#define P10_5_PIN 5u
+#define P10_5_NUM 5u
+#define P10_6_PORT GPIO_PRT10
+#define P10_6_PIN 6u
+#define P10_6_NUM 6u
+
+/* PORT 11 (GPIO) */
+#define P11_0_PORT GPIO_PRT11
+#define P11_0_PIN 0u
+#define P11_0_NUM 0u
+#define P11_1_PORT GPIO_PRT11
+#define P11_1_PIN 1u
+#define P11_1_NUM 1u
+#define P11_2_PORT GPIO_PRT11
+#define P11_2_PIN 2u
+#define P11_2_NUM 2u
+#define P11_3_PORT GPIO_PRT11
+#define P11_3_PIN 3u
+#define P11_3_NUM 3u
+#define P11_4_PORT GPIO_PRT11
+#define P11_4_PIN 4u
+#define P11_4_NUM 4u
+#define P11_5_PORT GPIO_PRT11
+#define P11_5_PIN 5u
+#define P11_5_NUM 5u
+#define P11_6_PORT GPIO_PRT11
+#define P11_6_PIN 6u
+#define P11_6_NUM 6u
+#define P11_7_PORT GPIO_PRT11
+#define P11_7_PIN 7u
+#define P11_7_NUM 7u
+
+/* PORT 12 (GPIO) */
+#define P12_0_PORT GPIO_PRT12
+#define P12_0_PIN 0u
+#define P12_0_NUM 0u
+#define P12_1_PORT GPIO_PRT12
+#define P12_1_PIN 1u
+#define P12_1_NUM 1u
+#define P12_2_PORT GPIO_PRT12
+#define P12_2_PIN 2u
+#define P12_2_NUM 2u
+#define P12_3_PORT GPIO_PRT12
+#define P12_3_PIN 3u
+#define P12_3_NUM 3u
+#define P12_4_PORT GPIO_PRT12
+#define P12_4_PIN 4u
+#define P12_4_NUM 4u
+#define P12_5_PORT GPIO_PRT12
+#define P12_5_PIN 5u
+#define P12_5_NUM 5u
+#define P12_6_PORT GPIO_PRT12
+#define P12_6_PIN 6u
+#define P12_6_NUM 6u
+#define P12_7_PORT GPIO_PRT12
+#define P12_7_PIN 7u
+#define P12_7_NUM 7u
+
+/* PORT 13 (GPIO) */
+#define P13_0_PORT GPIO_PRT13
+#define P13_0_PIN 0u
+#define P13_0_NUM 0u
+#define P13_1_PORT GPIO_PRT13
+#define P13_1_PIN 1u
+#define P13_1_NUM 1u
+#define P13_6_PORT GPIO_PRT13
+#define P13_6_PIN 6u
+#define P13_6_NUM 6u
+#define P13_7_PORT GPIO_PRT13
+#define P13_7_PIN 7u
+#define P13_7_NUM 7u
+
+/* Analog Connections */
+#define CSD_CMODPADD_PORT 7u
+#define CSD_CMODPADD_PIN 1u
+#define CSD_CMODPADS_PORT 7u
+#define CSD_CMODPADS_PIN 1u
+#define CSD_CSH_TANKPADD_PORT 7u
+#define CSD_CSH_TANKPADD_PIN 2u
+#define CSD_CSH_TANKPADS_PORT 7u
+#define CSD_CSH_TANKPADS_PIN 2u
+#define CSD_CSHIELDPADS_PORT 7u
+#define CSD_CSHIELDPADS_PIN 7u
+#define CSD_VREF_EXT_PORT 7u
+#define CSD_VREF_EXT_PIN 3u
+#define IOSS_ADFT0_NET_PORT 10u
+#define IOSS_ADFT0_NET_PIN 0u
+#define IOSS_ADFT1_NET_PORT 10u
+#define IOSS_ADFT1_NET_PIN 1u
+#define LPCOMP_INN_COMP1_PORT 6u
+#define LPCOMP_INN_COMP1_PIN 3u
+#define LPCOMP_INP_COMP0_PORT 5u
+#define LPCOMP_INP_COMP0_PIN 6u
+#define LPCOMP_INP_COMP1_PORT 6u
+#define LPCOMP_INP_COMP1_PIN 2u
+#define PASS_AREF_EXT_VREF_PORT 9u
+#define PASS_AREF_EXT_VREF_PIN 7u
+#define PASS_CTB_OA0_OUT_10X_PORT 9u
+#define PASS_CTB_OA0_OUT_10X_PIN 2u
+#define PASS_CTB_OA1_OUT_10X_PORT 9u
+#define PASS_CTB_OA1_OUT_10X_PIN 3u
+#define PASS_CTB_PADS0_PORT 9u
+#define PASS_CTB_PADS0_PIN 0u
+#define PASS_CTB_PADS1_PORT 9u
+#define PASS_CTB_PADS1_PIN 1u
+#define PASS_CTB_PADS2_PORT 9u
+#define PASS_CTB_PADS2_PIN 2u
+#define PASS_CTB_PADS3_PORT 9u
+#define PASS_CTB_PADS3_PIN 3u
+#define PASS_CTB_PADS4_PORT 9u
+#define PASS_CTB_PADS4_PIN 4u
+#define PASS_CTB_PADS5_PORT 9u
+#define PASS_CTB_PADS5_PIN 5u
+#define PASS_CTB_PADS6_PORT 9u
+#define PASS_CTB_PADS6_PIN 6u
+#define PASS_CTB_PADS7_PORT 9u
+#define PASS_CTB_PADS7_PIN 7u
+#define PASS_SARMUX_PADS0_PORT 10u
+#define PASS_SARMUX_PADS0_PIN 0u
+#define PASS_SARMUX_PADS1_PORT 10u
+#define PASS_SARMUX_PADS1_PIN 1u
+#define PASS_SARMUX_PADS2_PORT 10u
+#define PASS_SARMUX_PADS2_PIN 2u
+#define PASS_SARMUX_PADS3_PORT 10u
+#define PASS_SARMUX_PADS3_PIN 3u
+#define PASS_SARMUX_PADS4_PORT 10u
+#define PASS_SARMUX_PADS4_PIN 4u
+#define PASS_SARMUX_PADS5_PORT 10u
+#define PASS_SARMUX_PADS5_PIN 5u
+#define PASS_SARMUX_PADS6_PORT 10u
+#define PASS_SARMUX_PADS6_PIN 6u
+#define SRSS_ADFT_PIN0_PORT 10u
+#define SRSS_ADFT_PIN0_PIN 0u
+#define SRSS_ADFT_PIN1_PORT 10u
+#define SRSS_ADFT_PIN1_PIN 1u
+#define SRSS_ECO_IN_PORT 12u
+#define SRSS_ECO_IN_PIN 6u
+#define SRSS_ECO_OUT_PORT 12u
+#define SRSS_ECO_OUT_PIN 7u
+#define SRSS_WCO_IN_PORT 0u
+#define SRSS_WCO_IN_PIN 0u
+#define SRSS_WCO_OUT_PORT 0u
+#define SRSS_WCO_OUT_PIN 1u
+
+/* HSIOM Connections */
+typedef enum
+{
+ /* Generic HSIOM connections */
+ HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */
+ HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */
+ HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */
+ HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */
+ HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */
+ HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */
+ HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */
+ HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */
+ HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */
+ HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */
+ HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */
+ HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */
+ HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */
+ HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */
+ HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */
+ HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */
+ HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */
+ HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */
+ HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */
+ HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */
+ HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */
+ HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */
+ HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */
+ HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */
+ HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */
+ HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */
+ HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */
+
+ /* P0.0 */
+ P0_0_GPIO = 0, /* GPIO controls 'out' */
+ P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_0_AMUXA = 4, /* Analog mux bus A */
+ P0_0_AMUXB = 5, /* Analog mux bus B */
+ P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */
+ P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */
+ P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */
+ P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */
+ P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */
+ P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */
+ P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */
+ P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */
+ P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */
+
+ /* P0.1 */
+ P0_1_GPIO = 0, /* GPIO controls 'out' */
+ P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_1_AMUXA = 4, /* Analog mux bus A */
+ P0_1_AMUXB = 5, /* Analog mux bus B */
+ P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */
+ P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */
+ P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */
+ P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */
+ P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */
+ P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */
+ P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */
+ P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */
+ P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */
+
+ /* P0.2 */
+ P0_2_GPIO = 0, /* GPIO controls 'out' */
+ P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_2_AMUXA = 4, /* Analog mux bus A */
+ P0_2_AMUXB = 5, /* Analog mux bus B */
+ P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */
+ P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */
+ P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */
+ P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */
+ P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */
+ P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */
+ P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */
+ P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */
+ P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */
+
+ /* P0.3 */
+ P0_3_GPIO = 0, /* GPIO controls 'out' */
+ P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_3_AMUXA = 4, /* Analog mux bus A */
+ P0_3_AMUXB = 5, /* Analog mux bus B */
+ P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */
+ P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */
+ P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */
+ P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */
+ P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */
+ P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */
+ P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */
+ P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */
+ P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */
+
+ /* P0.4 */
+ P0_4_GPIO = 0, /* GPIO controls 'out' */
+ P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_4_AMUXA = 4, /* Analog mux bus A */
+ P0_4_AMUXB = 5, /* Analog mux bus B */
+ P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */
+ P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */
+ P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */
+ P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */
+ P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */
+ P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */
+ P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */
+ P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */
+ P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */
+
+ /* P0.5 */
+ P0_5_GPIO = 0, /* GPIO controls 'out' */
+ P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P0_5_AMUXA = 4, /* Analog mux bus A */
+ P0_5_AMUXB = 5, /* Analog mux bus B */
+ P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */
+ P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */
+ P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */
+ P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */
+ P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */
+ P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */
+ P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */
+ P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */
+ P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */
+ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */
+
+ /* P1.0 */
+ P1_0_GPIO = 0, /* GPIO controls 'out' */
+ P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_0_AMUXA = 4, /* Analog mux bus A */
+ P1_0_AMUXB = 5, /* Analog mux bus B */
+ P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */
+ P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */
+ P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */
+ P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */
+ P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */
+ P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */
+ P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */
+ P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */
+ P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */
+ P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */
+
+ /* P1.1 */
+ P1_1_GPIO = 0, /* GPIO controls 'out' */
+ P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_1_AMUXA = 4, /* Analog mux bus A */
+ P1_1_AMUXB = 5, /* Analog mux bus B */
+ P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */
+ P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */
+ P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */
+ P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */
+ P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */
+ P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */
+ P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */
+ P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */
+ P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */
+ P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */
+
+ /* P1.2 */
+ P1_2_GPIO = 0, /* GPIO controls 'out' */
+ P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_2_AMUXA = 4, /* Analog mux bus A */
+ P1_2_AMUXB = 5, /* Analog mux bus B */
+ P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */
+ P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */
+ P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */
+ P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */
+ P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */
+ P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */
+ P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */
+ P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */
+
+ /* P1.3 */
+ P1_3_GPIO = 0, /* GPIO controls 'out' */
+ P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_3_AMUXA = 4, /* Analog mux bus A */
+ P1_3_AMUXB = 5, /* Analog mux bus B */
+ P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */
+ P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */
+ P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */
+ P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */
+ P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */
+ P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */
+ P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */
+ P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */
+
+ /* P1.4 */
+ P1_4_GPIO = 0, /* GPIO controls 'out' */
+ P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_4_AMUXA = 4, /* Analog mux bus A */
+ P1_4_AMUXB = 5, /* Analog mux bus B */
+ P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */
+ P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */
+ P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */
+ P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */
+ P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */
+ P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */
+ P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */
+
+ /* P1.5 */
+ P1_5_GPIO = 0, /* GPIO controls 'out' */
+ P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P1_5_AMUXA = 4, /* Analog mux bus A */
+ P1_5_AMUXB = 5, /* Analog mux bus B */
+ P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */
+ P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */
+ P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */
+ P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */
+ P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */
+ P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */
+ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */
+
+ /* P5.0 */
+ P5_0_GPIO = 0, /* GPIO controls 'out' */
+ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_0_AMUXA = 4, /* Analog mux bus A */
+ P5_0_AMUXB = 5, /* Analog mux bus B */
+ P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */
+ P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */
+ P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */
+ P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */
+ P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */
+ P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */
+ P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */
+ P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */
+ P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */
+ P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */
+ P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */
+
+ /* P5.1 */
+ P5_1_GPIO = 0, /* GPIO controls 'out' */
+ P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_1_AMUXA = 4, /* Analog mux bus A */
+ P5_1_AMUXB = 5, /* Analog mux bus B */
+ P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */
+ P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */
+ P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */
+ P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */
+ P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */
+ P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */
+ P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */
+ P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */
+ P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */
+ P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */
+ P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */
+
+ /* P5.2 */
+ P5_2_GPIO = 0, /* GPIO controls 'out' */
+ P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_2_AMUXA = 4, /* Analog mux bus A */
+ P5_2_AMUXB = 5, /* Analog mux bus B */
+ P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */
+ P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */
+ P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */
+ P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */
+ P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */
+ P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */
+ P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */
+ P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */
+ P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */
+
+ /* P5.3 */
+ P5_3_GPIO = 0, /* GPIO controls 'out' */
+ P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_3_AMUXA = 4, /* Analog mux bus A */
+ P5_3_AMUXB = 5, /* Analog mux bus B */
+ P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */
+ P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */
+ P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */
+ P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */
+ P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */
+ P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */
+ P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */
+ P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */
+ P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */
+
+ /* P5.4 */
+ P5_4_GPIO = 0, /* GPIO controls 'out' */
+ P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_4_AMUXA = 4, /* Analog mux bus A */
+ P5_4_AMUXB = 5, /* Analog mux bus B */
+ P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */
+ P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */
+ P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */
+ P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */
+ P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */
+ P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */
+ P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */
+ P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */
+
+ /* P5.5 */
+ P5_5_GPIO = 0, /* GPIO controls 'out' */
+ P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_5_AMUXA = 4, /* Analog mux bus A */
+ P5_5_AMUXB = 5, /* Analog mux bus B */
+ P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */
+ P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */
+ P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */
+ P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */
+ P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */
+ P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */
+ P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */
+ P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */
+
+ /* P5.6 */
+ P5_6_GPIO = 0, /* GPIO controls 'out' */
+ P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P5_6_AMUXA = 4, /* Analog mux bus A */
+ P5_6_AMUXB = 5, /* Analog mux bus B */
+ P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */
+ P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */
+ P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */
+ P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */
+ P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */
+ P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */
+ P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */
+ P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */
+
+ /* P6.0 */
+ P6_0_GPIO = 0, /* GPIO controls 'out' */
+ P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_0_AMUXA = 4, /* Analog mux bus A */
+ P6_0_AMUXB = 5, /* Analog mux bus B */
+ P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */
+ P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */
+ P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */
+ P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */
+ P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */
+ P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */
+ P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */
+ P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */
+ P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */
+ P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */
+ P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */
+ P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */
+
+ /* P6.1 */
+ P6_1_GPIO = 0, /* GPIO controls 'out' */
+ P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_1_AMUXA = 4, /* Analog mux bus A */
+ P6_1_AMUXB = 5, /* Analog mux bus B */
+ P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */
+ P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */
+ P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */
+ P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */
+ P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */
+ P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */
+ P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */
+ P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */
+ P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */
+ P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */
+ P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */
+ P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */
+
+ /* P6.2 */
+ P6_2_GPIO = 0, /* GPIO controls 'out' */
+ P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_2_AMUXA = 4, /* Analog mux bus A */
+ P6_2_AMUXB = 5, /* Analog mux bus B */
+ P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */
+ P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */
+ P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */
+ P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */
+ P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */
+ P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */
+ P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */
+ P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */
+ P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */
+
+ /* P6.3 */
+ P6_3_GPIO = 0, /* GPIO controls 'out' */
+ P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_3_AMUXA = 4, /* Analog mux bus A */
+ P6_3_AMUXB = 5, /* Analog mux bus B */
+ P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */
+ P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */
+ P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */
+ P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */
+ P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */
+ P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */
+ P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */
+ P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */
+ P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */
+
+ /* P6.4 */
+ P6_4_GPIO = 0, /* GPIO controls 'out' */
+ P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_4_AMUXA = 4, /* Analog mux bus A */
+ P6_4_AMUXB = 5, /* Analog mux bus B */
+ P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */
+ P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */
+ P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */
+ P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */
+ P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */
+ P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */
+ P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */
+ P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */
+ P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */
+ P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */
+ P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */
+ P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */
+ P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */
+ P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */
+ P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */
+
+ /* P6.5 */
+ P6_5_GPIO = 0, /* GPIO controls 'out' */
+ P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_5_AMUXA = 4, /* Analog mux bus A */
+ P6_5_AMUXB = 5, /* Analog mux bus B */
+ P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */
+ P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */
+ P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */
+ P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */
+ P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */
+ P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */
+ P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */
+ P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */
+ P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */
+ P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */
+ P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */
+ P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */
+ P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */
+ P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */
+ P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */
+
+ /* P6.6 */
+ P6_6_GPIO = 0, /* GPIO controls 'out' */
+ P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_6_AMUXA = 4, /* Analog mux bus A */
+ P6_6_AMUXB = 5, /* Analog mux bus B */
+ P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */
+ P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */
+ P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */
+ P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */
+ P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */
+ P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */
+ P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */
+ P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */
+ P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */
+ P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */
+
+ /* P6.7 */
+ P6_7_GPIO = 0, /* GPIO controls 'out' */
+ P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P6_7_AMUXA = 4, /* Analog mux bus A */
+ P6_7_AMUXB = 5, /* Analog mux bus B */
+ P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */
+ P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */
+ P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */
+ P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */
+ P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */
+ P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */
+ P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */
+ P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */
+ P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */
+ P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */
+
+ /* P7.0 */
+ P7_0_GPIO = 0, /* GPIO controls 'out' */
+ P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_0_AMUXA = 4, /* Analog mux bus A */
+ P7_0_AMUXB = 5, /* Analog mux bus B */
+ P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */
+ P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */
+ P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */
+ P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */
+ P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */
+ P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */
+ P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */
+ P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */
+ P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */
+ P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */
+ P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */
+
+ /* P7.1 */
+ P7_1_GPIO = 0, /* GPIO controls 'out' */
+ P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_1_AMUXA = 4, /* Analog mux bus A */
+ P7_1_AMUXB = 5, /* Analog mux bus B */
+ P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */
+ P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */
+ P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */
+ P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */
+ P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */
+ P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */
+ P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */
+ P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */
+ P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */
+ P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */
+
+ /* P7.2 */
+ P7_2_GPIO = 0, /* GPIO controls 'out' */
+ P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_2_AMUXA = 4, /* Analog mux bus A */
+ P7_2_AMUXB = 5, /* Analog mux bus B */
+ P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */
+ P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */
+ P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */
+ P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */
+ P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */
+ P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */
+ P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */
+ P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */
+
+ /* P7.3 */
+ P7_3_GPIO = 0, /* GPIO controls 'out' */
+ P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_3_AMUXA = 4, /* Analog mux bus A */
+ P7_3_AMUXB = 5, /* Analog mux bus B */
+ P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */
+ P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */
+ P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */
+ P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */
+ P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */
+ P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */
+ P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */
+ P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */
+
+ /* P7.4 */
+ P7_4_GPIO = 0, /* GPIO controls 'out' */
+ P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_4_AMUXA = 4, /* Analog mux bus A */
+ P7_4_AMUXB = 5, /* Analog mux bus B */
+ P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */
+ P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */
+ P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */
+ P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */
+ P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */
+ P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */
+ P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */
+ P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */
+ P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */
+
+ /* P7.5 */
+ P7_5_GPIO = 0, /* GPIO controls 'out' */
+ P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_5_AMUXA = 4, /* Analog mux bus A */
+ P7_5_AMUXB = 5, /* Analog mux bus B */
+ P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */
+ P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */
+ P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */
+ P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */
+ P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */
+ P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */
+ P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */
+ P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */
+ P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */
+
+ /* P7.6 */
+ P7_6_GPIO = 0, /* GPIO controls 'out' */
+ P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_6_AMUXA = 4, /* Analog mux bus A */
+ P7_6_AMUXB = 5, /* Analog mux bus B */
+ P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */
+ P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */
+ P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */
+ P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */
+ P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */
+ P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */
+ P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */
+ P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */
+ P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */
+
+ /* P7.7 */
+ P7_7_GPIO = 0, /* GPIO controls 'out' */
+ P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P7_7_AMUXA = 4, /* Analog mux bus A */
+ P7_7_AMUXB = 5, /* Analog mux bus B */
+ P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */
+ P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */
+ P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */
+ P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */
+ P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */
+ P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */
+ P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */
+ P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */
+ P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */
+
+ /* P8.0 */
+ P8_0_GPIO = 0, /* GPIO controls 'out' */
+ P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_0_AMUXA = 4, /* Analog mux bus A */
+ P8_0_AMUXB = 5, /* Analog mux bus B */
+ P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */
+ P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */
+ P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */
+ P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */
+ P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */
+ P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */
+ P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */
+ P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */
+ P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */
+ P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */
+
+ /* P8.1 */
+ P8_1_GPIO = 0, /* GPIO controls 'out' */
+ P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_1_AMUXA = 4, /* Analog mux bus A */
+ P8_1_AMUXB = 5, /* Analog mux bus B */
+ P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */
+ P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */
+ P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */
+ P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */
+ P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */
+ P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */
+ P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */
+ P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */
+ P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */
+ P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */
+
+ /* P8.2 */
+ P8_2_GPIO = 0, /* GPIO controls 'out' */
+ P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_2_AMUXA = 4, /* Analog mux bus A */
+ P8_2_AMUXB = 5, /* Analog mux bus B */
+ P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */
+ P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */
+ P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */
+ P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */
+ P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */
+ P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */
+ P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */
+ P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */
+ P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */
+
+ /* P8.3 */
+ P8_3_GPIO = 0, /* GPIO controls 'out' */
+ P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_3_AMUXA = 4, /* Analog mux bus A */
+ P8_3_AMUXB = 5, /* Analog mux bus B */
+ P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */
+ P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */
+ P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */
+ P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */
+ P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */
+ P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */
+ P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */
+ P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */
+ P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */
+
+ /* P8.4 */
+ P8_4_GPIO = 0, /* GPIO controls 'out' */
+ P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_4_AMUXA = 4, /* Analog mux bus A */
+ P8_4_AMUXB = 5, /* Analog mux bus B */
+ P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */
+ P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */
+ P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */
+ P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */
+ P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */
+ P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */
+ P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */
+
+ /* P8.5 */
+ P8_5_GPIO = 0, /* GPIO controls 'out' */
+ P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_5_AMUXA = 4, /* Analog mux bus A */
+ P8_5_AMUXB = 5, /* Analog mux bus B */
+ P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */
+ P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */
+ P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */
+ P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */
+ P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */
+ P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */
+ P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */
+
+ /* P8.6 */
+ P8_6_GPIO = 0, /* GPIO controls 'out' */
+ P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_6_AMUXA = 4, /* Analog mux bus A */
+ P8_6_AMUXB = 5, /* Analog mux bus B */
+ P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */
+ P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */
+ P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */
+ P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */
+ P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */
+ P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */
+ P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */
+
+ /* P8.7 */
+ P8_7_GPIO = 0, /* GPIO controls 'out' */
+ P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P8_7_AMUXA = 4, /* Analog mux bus A */
+ P8_7_AMUXB = 5, /* Analog mux bus B */
+ P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */
+ P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */
+ P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */
+ P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */
+ P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */
+ P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */
+ P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */
+
+ /* P9.0 */
+ P9_0_GPIO = 0, /* GPIO controls 'out' */
+ P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_0_AMUXA = 4, /* Analog mux bus A */
+ P9_0_AMUXB = 5, /* Analog mux bus B */
+ P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */
+ P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */
+ P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */
+ P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */
+ P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */
+ P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */
+ P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */
+ P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */
+ P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */
+ P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */
+ P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */
+
+ /* P9.1 */
+ P9_1_GPIO = 0, /* GPIO controls 'out' */
+ P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_1_AMUXA = 4, /* Analog mux bus A */
+ P9_1_AMUXB = 5, /* Analog mux bus B */
+ P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */
+ P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */
+ P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */
+ P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */
+ P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */
+ P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */
+ P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */
+ P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */
+ P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */
+ P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */
+ P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */
+ P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */
+
+ /* P9.2 */
+ P9_2_GPIO = 0, /* GPIO controls 'out' */
+ P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_2_AMUXA = 4, /* Analog mux bus A */
+ P9_2_AMUXB = 5, /* Analog mux bus B */
+ P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */
+ P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */
+ P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */
+ P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */
+ P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */
+ P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */
+ P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */
+ P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */
+ P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */
+ P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */
+
+ /* P9.3 */
+ P9_3_GPIO = 0, /* GPIO controls 'out' */
+ P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_3_AMUXA = 4, /* Analog mux bus A */
+ P9_3_AMUXB = 5, /* Analog mux bus B */
+ P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */
+ P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */
+ P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */
+ P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */
+ P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */
+ P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */
+ P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */
+ P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */
+ P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */
+ P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */
+ P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */
+
+ /* P9.4 */
+ P9_4_GPIO = 0, /* GPIO controls 'out' */
+ P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_4_AMUXA = 4, /* Analog mux bus A */
+ P9_4_AMUXB = 5, /* Analog mux bus B */
+ P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */
+ P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */
+ P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */
+ P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */
+ P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */
+ P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */
+ P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */
+
+ /* P9.5 */
+ P9_5_GPIO = 0, /* GPIO controls 'out' */
+ P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_5_AMUXA = 4, /* Analog mux bus A */
+ P9_5_AMUXB = 5, /* Analog mux bus B */
+ P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */
+ P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */
+ P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */
+ P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */
+ P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */
+ P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */
+ P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */
+
+ /* P9.6 */
+ P9_6_GPIO = 0, /* GPIO controls 'out' */
+ P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_6_AMUXA = 4, /* Analog mux bus A */
+ P9_6_AMUXB = 5, /* Analog mux bus B */
+ P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */
+ P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */
+ P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */
+ P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */
+ P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */
+ P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */
+ P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */
+
+ /* P9.7 */
+ P9_7_GPIO = 0, /* GPIO controls 'out' */
+ P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P9_7_AMUXA = 4, /* Analog mux bus A */
+ P9_7_AMUXB = 5, /* Analog mux bus B */
+ P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */
+ P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */
+ P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */
+ P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */
+ P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */
+ P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */
+
+ /* P10.0 */
+ P10_0_GPIO = 0, /* GPIO controls 'out' */
+ P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_0_AMUXA = 4, /* Analog mux bus A */
+ P10_0_AMUXB = 5, /* Analog mux bus B */
+ P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */
+ P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */
+ P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */
+ P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */
+ P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */
+ P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */
+ P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */
+ P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */
+ P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */
+ P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */
+ P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */
+
+ /* P10.1 */
+ P10_1_GPIO = 0, /* GPIO controls 'out' */
+ P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_1_AMUXA = 4, /* Analog mux bus A */
+ P10_1_AMUXB = 5, /* Analog mux bus B */
+ P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */
+ P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */
+ P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */
+ P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */
+ P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */
+ P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */
+ P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */
+ P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */
+ P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */
+ P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */
+ P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */
+
+ /* P10.2 */
+ P10_2_GPIO = 0, /* GPIO controls 'out' */
+ P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_2_AMUXA = 4, /* Analog mux bus A */
+ P10_2_AMUXB = 5, /* Analog mux bus B */
+ P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */
+ P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */
+ P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */
+ P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */
+ P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */
+ P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */
+ P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */
+ P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */
+ P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */
+
+ /* P10.3 */
+ P10_3_GPIO = 0, /* GPIO controls 'out' */
+ P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_3_AMUXA = 4, /* Analog mux bus A */
+ P10_3_AMUXB = 5, /* Analog mux bus B */
+ P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */
+ P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */
+ P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */
+ P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */
+ P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */
+ P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */
+ P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */
+ P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */
+ P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */
+
+ /* P10.4 */
+ P10_4_GPIO = 0, /* GPIO controls 'out' */
+ P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_4_AMUXA = 4, /* Analog mux bus A */
+ P10_4_AMUXB = 5, /* Analog mux bus B */
+ P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */
+ P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */
+ P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */
+ P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */
+ P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */
+ P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */
+ P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */
+ P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */
+
+ /* P10.5 */
+ P10_5_GPIO = 0, /* GPIO controls 'out' */
+ P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_5_AMUXA = 4, /* Analog mux bus A */
+ P10_5_AMUXB = 5, /* Analog mux bus B */
+ P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */
+ P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */
+ P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */
+ P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */
+ P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */
+ P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */
+ P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */
+ P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */
+
+ /* P10.6 */
+ P10_6_GPIO = 0, /* GPIO controls 'out' */
+ P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P10_6_AMUXA = 4, /* Analog mux bus A */
+ P10_6_AMUXB = 5, /* Analog mux bus B */
+ P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */
+ P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */
+ P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */
+ P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */
+ P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */
+ P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */
+ P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */
+
+ /* P11.0 */
+ P11_0_GPIO = 0, /* GPIO controls 'out' */
+ P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_0_AMUXA = 4, /* Analog mux bus A */
+ P11_0_AMUXB = 5, /* Analog mux bus B */
+ P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */
+ P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */
+ P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */
+ P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */
+ P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */
+ P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */
+ P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */
+ P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */
+ P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */
+ P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */
+ P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */
+
+ /* P11.1 */
+ P11_1_GPIO = 0, /* GPIO controls 'out' */
+ P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_1_AMUXA = 4, /* Analog mux bus A */
+ P11_1_AMUXB = 5, /* Analog mux bus B */
+ P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */
+ P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */
+ P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */
+ P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */
+ P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */
+ P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */
+ P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */
+ P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */
+ P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */
+ P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */
+ P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */
+
+ /* P11.2 */
+ P11_2_GPIO = 0, /* GPIO controls 'out' */
+ P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_2_AMUXA = 4, /* Analog mux bus A */
+ P11_2_AMUXB = 5, /* Analog mux bus B */
+ P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */
+ P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */
+ P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */
+ P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */
+ P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */
+ P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */
+ P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */
+ P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */
+ P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */
+
+ /* P11.3 */
+ P11_3_GPIO = 0, /* GPIO controls 'out' */
+ P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_3_AMUXA = 4, /* Analog mux bus A */
+ P11_3_AMUXB = 5, /* Analog mux bus B */
+ P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */
+ P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */
+ P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */
+ P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */
+ P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */
+ P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */
+ P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */
+ P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */
+ P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */
+ P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */
+
+ /* P11.4 */
+ P11_4_GPIO = 0, /* GPIO controls 'out' */
+ P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_4_AMUXA = 4, /* Analog mux bus A */
+ P11_4_AMUXB = 5, /* Analog mux bus B */
+ P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */
+ P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */
+ P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */
+ P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */
+ P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */
+ P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */
+ P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */
+ P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */
+ P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */
+
+ /* P11.5 */
+ P11_5_GPIO = 0, /* GPIO controls 'out' */
+ P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_5_AMUXA = 4, /* Analog mux bus A */
+ P11_5_AMUXB = 5, /* Analog mux bus B */
+ P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */
+ P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */
+ P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */
+ P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */
+ P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */
+ P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */
+ P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */
+ P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */
+
+ /* P11.6 */
+ P11_6_GPIO = 0, /* GPIO controls 'out' */
+ P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_6_AMUXA = 4, /* Analog mux bus A */
+ P11_6_AMUXB = 5, /* Analog mux bus B */
+ P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */
+ P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */
+ P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */
+ P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */
+ P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */
+ P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */
+
+ /* P11.7 */
+ P11_7_GPIO = 0, /* GPIO controls 'out' */
+ P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P11_7_AMUXA = 4, /* Analog mux bus A */
+ P11_7_AMUXB = 5, /* Analog mux bus B */
+ P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */
+
+ /* P12.0 */
+ P12_0_GPIO = 0, /* GPIO controls 'out' */
+ P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_0_AMUXA = 4, /* Analog mux bus A */
+ P12_0_AMUXB = 5, /* Analog mux bus B */
+ P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */
+ P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */
+ P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */
+ P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */
+ P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */
+ P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */
+ P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */
+ P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */
+ P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */
+ P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */
+ P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */
+
+ /* P12.1 */
+ P12_1_GPIO = 0, /* GPIO controls 'out' */
+ P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_1_AMUXA = 4, /* Analog mux bus A */
+ P12_1_AMUXB = 5, /* Analog mux bus B */
+ P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */
+ P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */
+ P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */
+ P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */
+ P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */
+ P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */
+ P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */
+ P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */
+ P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */
+ P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */
+ P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */
+
+ /* P12.2 */
+ P12_2_GPIO = 0, /* GPIO controls 'out' */
+ P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_2_AMUXA = 4, /* Analog mux bus A */
+ P12_2_AMUXB = 5, /* Analog mux bus B */
+ P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */
+ P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */
+ P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */
+ P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */
+ P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */
+ P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */
+ P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */
+ P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */
+ P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */
+
+ /* P12.3 */
+ P12_3_GPIO = 0, /* GPIO controls 'out' */
+ P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_3_AMUXA = 4, /* Analog mux bus A */
+ P12_3_AMUXB = 5, /* Analog mux bus B */
+ P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */
+ P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */
+ P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */
+ P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */
+ P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */
+ P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */
+ P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */
+ P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */
+ P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */
+
+ /* P12.4 */
+ P12_4_GPIO = 0, /* GPIO controls 'out' */
+ P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_4_AMUXA = 4, /* Analog mux bus A */
+ P12_4_AMUXB = 5, /* Analog mux bus B */
+ P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */
+ P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */
+ P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */
+ P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */
+ P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */
+ P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */
+ P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */
+ P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */
+ P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */
+
+ /* P12.5 */
+ P12_5_GPIO = 0, /* GPIO controls 'out' */
+ P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_5_AMUXA = 4, /* Analog mux bus A */
+ P12_5_AMUXB = 5, /* Analog mux bus B */
+ P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */
+ P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */
+ P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */
+ P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */
+ P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */
+ P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */
+ P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */
+ P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */
+
+ /* P12.6 */
+ P12_6_GPIO = 0, /* GPIO controls 'out' */
+ P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_6_AMUXA = 4, /* Analog mux bus A */
+ P12_6_AMUXB = 5, /* Analog mux bus B */
+ P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */
+ P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */
+ P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */
+ P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */
+ P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */
+ P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */
+ P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */
+
+ /* P12.7 */
+ P12_7_GPIO = 0, /* GPIO controls 'out' */
+ P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P12_7_AMUXA = 4, /* Analog mux bus A */
+ P12_7_AMUXB = 5, /* Analog mux bus B */
+ P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */
+ P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */
+ P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */
+ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */
+ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */
+ P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */
+
+ /* P13.0 */
+ P13_0_GPIO = 0, /* GPIO controls 'out' */
+ P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_0_AMUXA = 4, /* Analog mux bus A */
+ P13_0_AMUXB = 5, /* Analog mux bus B */
+ P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */
+ P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */
+ P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */
+ P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */
+ P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */
+ P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */
+ P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */
+ P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */
+ P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */
+ P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */
+
+ /* P13.1 */
+ P13_1_GPIO = 0, /* GPIO controls 'out' */
+ P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_1_AMUXA = 4, /* Analog mux bus A */
+ P13_1_AMUXB = 5, /* Analog mux bus B */
+ P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */
+ P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */
+ P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */
+ P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */
+ P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */
+ P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */
+ P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */
+ P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */
+ P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */
+ P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */
+
+ /* P13.6 */
+ P13_6_GPIO = 0, /* GPIO controls 'out' */
+ P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_6_AMUXA = 4, /* Analog mux bus A */
+ P13_6_AMUXB = 5, /* Analog mux bus B */
+ P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */
+ P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */
+ P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */
+ P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */
+ P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */
+ P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */
+ P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */
+
+ /* P13.7 */
+ P13_7_GPIO = 0, /* GPIO controls 'out' */
+ P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */
+ P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */
+ P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */
+ P13_7_AMUXA = 4, /* Analog mux bus A */
+ P13_7_AMUXB = 5, /* Analog mux bus B */
+ P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */
+ P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */
+ P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */
+ P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */
+ P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */
+ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */
+ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */
+ P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */
+} en_hsiom_sel_t;
+
+#endif /* _GPIO_PSOC63_116_BGA_BLE_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,3000 @@
+/***************************************************************************//**
+* \file psoc63_config.h
+*
+* \brief
+* PSoC 63 device configuration header
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _PSOC63_CONFIG_H_
+#define _PSOC63_CONFIG_H_
+
+/* Clock Connections */
+typedef enum
+{
+ PCLK_SCB0_CLOCK = 0, /* scb[0].clock */
+ PCLK_SCB1_CLOCK = 1, /* scb[1].clock */
+ PCLK_SCB2_CLOCK = 2, /* scb[2].clock */
+ PCLK_SCB3_CLOCK = 3, /* scb[3].clock */
+ PCLK_SCB4_CLOCK = 4, /* scb[4].clock */
+ PCLK_SCB5_CLOCK = 5, /* scb[5].clock */
+ PCLK_SCB6_CLOCK = 6, /* scb[6].clock */
+ PCLK_SCB7_CLOCK = 7, /* scb[7].clock */
+ PCLK_SCB8_CLOCK = 8, /* scb[8].clock */
+ PCLK_UDB_CLOCKS0 = 9, /* udb.clocks[0] */
+ PCLK_UDB_CLOCKS1 = 10, /* udb.clocks[1] */
+ PCLK_UDB_CLOCKS2 = 11, /* udb.clocks[2] */
+ PCLK_UDB_CLOCKS3 = 12, /* udb.clocks[3] */
+ PCLK_UDB_CLOCKS4 = 13, /* udb.clocks[4] */
+ PCLK_UDB_CLOCKS5 = 14, /* udb.clocks[5] */
+ PCLK_UDB_CLOCKS6 = 15, /* udb.clocks[6] */
+ PCLK_UDB_CLOCKS7 = 16, /* udb.clocks[7] */
+ PCLK_SMARTIO8_CLOCK = 17, /* smartio[8].clock */
+ PCLK_SMARTIO9_CLOCK = 18, /* smartio[9].clock */
+ PCLK_TCPWM0_CLOCKS0 = 19, /* tcpwm[0].clocks[0] */
+ PCLK_TCPWM0_CLOCKS1 = 20, /* tcpwm[0].clocks[1] */
+ PCLK_TCPWM0_CLOCKS2 = 21, /* tcpwm[0].clocks[2] */
+ PCLK_TCPWM0_CLOCKS3 = 22, /* tcpwm[0].clocks[3] */
+ PCLK_TCPWM0_CLOCKS4 = 23, /* tcpwm[0].clocks[4] */
+ PCLK_TCPWM0_CLOCKS5 = 24, /* tcpwm[0].clocks[5] */
+ PCLK_TCPWM0_CLOCKS6 = 25, /* tcpwm[0].clocks[6] */
+ PCLK_TCPWM0_CLOCKS7 = 26, /* tcpwm[0].clocks[7] */
+ PCLK_TCPWM1_CLOCKS0 = 27, /* tcpwm[1].clocks[0] */
+ PCLK_TCPWM1_CLOCKS1 = 28, /* tcpwm[1].clocks[1] */
+ PCLK_TCPWM1_CLOCKS2 = 29, /* tcpwm[1].clocks[2] */
+ PCLK_TCPWM1_CLOCKS3 = 30, /* tcpwm[1].clocks[3] */
+ PCLK_TCPWM1_CLOCKS4 = 31, /* tcpwm[1].clocks[4] */
+ PCLK_TCPWM1_CLOCKS5 = 32, /* tcpwm[1].clocks[5] */
+ PCLK_TCPWM1_CLOCKS6 = 33, /* tcpwm[1].clocks[6] */
+ PCLK_TCPWM1_CLOCKS7 = 34, /* tcpwm[1].clocks[7] */
+ PCLK_TCPWM1_CLOCKS8 = 35, /* tcpwm[1].clocks[8] */
+ PCLK_TCPWM1_CLOCKS9 = 36, /* tcpwm[1].clocks[9] */
+ PCLK_TCPWM1_CLOCKS10 = 37, /* tcpwm[1].clocks[10] */
+ PCLK_TCPWM1_CLOCKS11 = 38, /* tcpwm[1].clocks[11] */
+ PCLK_TCPWM1_CLOCKS12 = 39, /* tcpwm[1].clocks[12] */
+ PCLK_TCPWM1_CLOCKS13 = 40, /* tcpwm[1].clocks[13] */
+ PCLK_TCPWM1_CLOCKS14 = 41, /* tcpwm[1].clocks[14] */
+ PCLK_TCPWM1_CLOCKS15 = 42, /* tcpwm[1].clocks[15] */
+ PCLK_TCPWM1_CLOCKS16 = 43, /* tcpwm[1].clocks[16] */
+ PCLK_TCPWM1_CLOCKS17 = 44, /* tcpwm[1].clocks[17] */
+ PCLK_TCPWM1_CLOCKS18 = 45, /* tcpwm[1].clocks[18] */
+ PCLK_TCPWM1_CLOCKS19 = 46, /* tcpwm[1].clocks[19] */
+ PCLK_TCPWM1_CLOCKS20 = 47, /* tcpwm[1].clocks[20] */
+ PCLK_TCPWM1_CLOCKS21 = 48, /* tcpwm[1].clocks[21] */
+ PCLK_TCPWM1_CLOCKS22 = 49, /* tcpwm[1].clocks[22] */
+ PCLK_TCPWM1_CLOCKS23 = 50, /* tcpwm[1].clocks[23] */
+ PCLK_CSD_CLOCK = 51, /* csd.clock */
+ PCLK_LCD_CLOCK = 52, /* lcd.clock */
+ PCLK_PROFILE_CLOCK_PROFILE = 53, /* profile.clock_profile */
+ PCLK_CPUSS_CLOCK_TRACE_IN = 54, /* cpuss.clock_trace_in */
+ PCLK_PASS_CLOCK_CTDAC = 55, /* pass.clock_ctdac */
+ PCLK_PASS_CLOCK_PUMP_PERI = 56, /* pass.clock_pump_peri */
+ PCLK_PASS_CLOCK_SAR = 57, /* pass.clock_sar */
+ PCLK_USB_CLOCK_DEV_BRS = 58 /* usb.clock_dev_brs */
+} en_clk_dst_t;
+
+/* Trigger Group */
+/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver.
+* The constants are divided into four types because each signal of the TrigMux driver has a path
+* through two multiplexers: the reduction multiplexer and the distribution multiplexer. This
+* requires two calls for Cy_TrigMux_Connect() function. The first call - for the reduction
+* multiplexer, the second call - for the distribution multiplexer.
+*
+* The four types of inputs/output parameters:
+* 1) Parameters for reduction multiplexer's inputs (input signals of TrigMux)
+* 2) Parameters for reduction multiplexer's outputs (intermediate signals);
+* 3) Parameters for distribution multiplexer's inputs (intermediate signals);
+* 4) Parameters for distribution multiplexer's outputs (output signals of TrigMux).
+*
+* The Cy_TrigMux_Connect() inTrig parameter can have 1) and 3) types parameters. The outTrig
+* parameter can have 2) and 4) types parameters.
+* The names of the constants for these parameters have the following format:
+*
+* 1) For reduction multiplexer's inputs:
+* TRIG<REDMULT>_IN_<IPSOURCE><IPNUM>
+* <REDMULT> the reduction multiplexer number;
+* <IPSOURCE> - the name of the IP block which is the source of the signal;
+* <IPNUM> - the source signal number in the IP block.
+*
+* Example:
+* TRIG11_IN_TCPWM0_TR_OVERFLOW3 - the TCPWM0 tr_overflow[3] input of reduction multiplexer#11.
+*
+* 2) For reduction multiplexer's outputs:
+* TRIG<REDMULT>_OUT_TR_GROUP<DISTMULT >_INPUT<DISTMULTINPUT>
+* <REDMULT> - the reduction multiplexer number;
+* <DISTMULT> - the distribution multiplexer number;
+* <DISTMULTINPUT> - the input number of the distribution multiplexer.
+*
+* Example:
+* TRIG11_OUT_TR_GROUP0_INPUT23 - Input#23 of the distribution multiplexer#0 is the destination
+* of the reduction multiplexer#11.
+*
+* 3) For distribution multiplexer's inputs:
+* TRIG<DISTMULT>_IN_TR_GROUP<REDMULT >_OUTPUT<REDMULTOUTPUT>
+* <REDMULT> - the reduction multiplexer number;
+* <DISTMULT> - the distribution multiplexer number;
+* <REDMULTOUTPUT> - the output number of the reduction multiplexer;
+*
+* Example:
+* TRIG0_IN_TR_GROUP11_OUTPUT15 - Output#15 of the reduction multiplexer#11 is the source of the
+* distribution multiplexer#0.
+*
+* 4) For distribution multiplexer's outputs:
+* TRIG<DISTMULT>_OUT_<IPDEST><IPNUM>
+* <REDMULT> - the distribution multiplexer number;
+* <IPDEST> - the name of the IP block which is the destination of the signal;
+* <IPNUM> - the input signal number in the IP block.
+*
+* Example:
+* TRIG0_OUT_CPUSS_DW0_TR_IN3 - the DW0 tr_out[3] ouput of the distribution multiplexer 0.*/
+/* Trigger Group Inputs */
+/* Trigger Input Group 0 - DMA Request Assignments */
+typedef enum
+{
+ TRIG0_IN_CPUSS_ZERO = 0x00000000u, /* cpuss.zero */
+ TRIG0_IN_TR_GROUP10_OUTPUT0 = 0x00000001u, /* tr_group[10].output[0] */
+ TRIG0_IN_TR_GROUP10_OUTPUT1 = 0x00000002u, /* tr_group[10].output[1] */
+ TRIG0_IN_TR_GROUP10_OUTPUT2 = 0x00000003u, /* tr_group[10].output[2] */
+ TRIG0_IN_TR_GROUP10_OUTPUT3 = 0x00000004u, /* tr_group[10].output[3] */
+ TRIG0_IN_TR_GROUP10_OUTPUT4 = 0x00000005u, /* tr_group[10].output[4] */
+ TRIG0_IN_TR_GROUP10_OUTPUT5 = 0x00000006u, /* tr_group[10].output[5] */
+ TRIG0_IN_TR_GROUP10_OUTPUT6 = 0x00000007u, /* tr_group[10].output[6] */
+ TRIG0_IN_TR_GROUP10_OUTPUT7 = 0x00000008u, /* tr_group[10].output[7] */
+ TRIG0_IN_TR_GROUP11_OUTPUT0 = 0x00000009u, /* tr_group[11].output[0] */
+ TRIG0_IN_TR_GROUP11_OUTPUT1 = 0x0000000Au, /* tr_group[11].output[1] */
+ TRIG0_IN_TR_GROUP11_OUTPUT2 = 0x0000000Bu, /* tr_group[11].output[2] */
+ TRIG0_IN_TR_GROUP11_OUTPUT3 = 0x0000000Cu, /* tr_group[11].output[3] */
+ TRIG0_IN_TR_GROUP11_OUTPUT4 = 0x0000000Du, /* tr_group[11].output[4] */
+ TRIG0_IN_TR_GROUP11_OUTPUT5 = 0x0000000Eu, /* tr_group[11].output[5] */
+ TRIG0_IN_TR_GROUP11_OUTPUT6 = 0x0000000Fu, /* tr_group[11].output[6] */
+ TRIG0_IN_TR_GROUP11_OUTPUT7 = 0x00000010u, /* tr_group[11].output[7] */
+ TRIG0_IN_TR_GROUP11_OUTPUT8 = 0x00000011u, /* tr_group[11].output[8] */
+ TRIG0_IN_TR_GROUP11_OUTPUT9 = 0x00000012u, /* tr_group[11].output[9] */
+ TRIG0_IN_TR_GROUP11_OUTPUT10 = 0x00000013u, /* tr_group[11].output[10] */
+ TRIG0_IN_TR_GROUP11_OUTPUT11 = 0x00000014u, /* tr_group[11].output[11] */
+ TRIG0_IN_TR_GROUP11_OUTPUT12 = 0x00000015u, /* tr_group[11].output[12] */
+ TRIG0_IN_TR_GROUP11_OUTPUT13 = 0x00000016u, /* tr_group[11].output[13] */
+ TRIG0_IN_TR_GROUP11_OUTPUT14 = 0x00000017u, /* tr_group[11].output[14] */
+ TRIG0_IN_TR_GROUP11_OUTPUT15 = 0x00000018u, /* tr_group[11].output[15] */
+ TRIG0_IN_TR_GROUP12_OUTPUT8 = 0x00000019u, /* tr_group[12].output[8] */
+ TRIG0_IN_TR_GROUP12_OUTPUT9 = 0x0000001Au, /* tr_group[12].output[9] */
+ TRIG0_IN_TR_GROUP13_OUTPUT0 = 0x0000001Bu, /* tr_group[13].output[0] */
+ TRIG0_IN_TR_GROUP13_OUTPUT1 = 0x0000001Cu, /* tr_group[13].output[1] */
+ TRIG0_IN_TR_GROUP13_OUTPUT2 = 0x0000001Du, /* tr_group[13].output[2] */
+ TRIG0_IN_TR_GROUP13_OUTPUT3 = 0x0000001Eu, /* tr_group[13].output[3] */
+ TRIG0_IN_TR_GROUP13_OUTPUT4 = 0x0000001Fu, /* tr_group[13].output[4] */
+ TRIG0_IN_TR_GROUP13_OUTPUT5 = 0x00000020u, /* tr_group[13].output[5] */
+ TRIG0_IN_TR_GROUP13_OUTPUT6 = 0x00000021u, /* tr_group[13].output[6] */
+ TRIG0_IN_TR_GROUP13_OUTPUT7 = 0x00000022u, /* tr_group[13].output[7] */
+ TRIG0_IN_TR_GROUP13_OUTPUT8 = 0x00000023u, /* tr_group[13].output[8] */
+ TRIG0_IN_TR_GROUP13_OUTPUT9 = 0x00000024u, /* tr_group[13].output[9] */
+ TRIG0_IN_TR_GROUP13_OUTPUT10 = 0x00000025u, /* tr_group[13].output[10] */
+ TRIG0_IN_TR_GROUP13_OUTPUT11 = 0x00000026u, /* tr_group[13].output[11] */
+ TRIG0_IN_TR_GROUP13_OUTPUT12 = 0x00000027u, /* tr_group[13].output[12] */
+ TRIG0_IN_TR_GROUP13_OUTPUT13 = 0x00000028u, /* tr_group[13].output[13] */
+ TRIG0_IN_TR_GROUP13_OUTPUT14 = 0x00000029u, /* tr_group[13].output[14] */
+ TRIG0_IN_TR_GROUP13_OUTPUT15 = 0x0000002Au, /* tr_group[13].output[15] */
+ TRIG0_IN_TR_GROUP14_OUTPUT0 = 0x0000002Bu, /* tr_group[14].output[0] */
+ TRIG0_IN_TR_GROUP14_OUTPUT1 = 0x0000002Cu, /* tr_group[14].output[1] */
+ TRIG0_IN_TR_GROUP14_OUTPUT2 = 0x0000002Du, /* tr_group[14].output[2] */
+ TRIG0_IN_TR_GROUP14_OUTPUT3 = 0x0000002Eu, /* tr_group[14].output[3] */
+ TRIG0_IN_TR_GROUP14_OUTPUT4 = 0x0000002Fu, /* tr_group[14].output[4] */
+ TRIG0_IN_TR_GROUP14_OUTPUT5 = 0x00000030u, /* tr_group[14].output[5] */
+ TRIG0_IN_TR_GROUP14_OUTPUT6 = 0x00000031u, /* tr_group[14].output[6] */
+ TRIG0_IN_TR_GROUP14_OUTPUT7 = 0x00000032u /* tr_group[14].output[7] */
+} en_trig_input_grp0_t;
+
+/* Trigger Input Group 1 - DMA Request Assignments */
+typedef enum
+{
+ TRIG1_IN_CPUSS_ZERO = 0x00000100u, /* cpuss.zero */
+ TRIG1_IN_TR_GROUP10_OUTPUT0 = 0x00000101u, /* tr_group[10].output[0] */
+ TRIG1_IN_TR_GROUP10_OUTPUT1 = 0x00000102u, /* tr_group[10].output[1] */
+ TRIG1_IN_TR_GROUP10_OUTPUT2 = 0x00000103u, /* tr_group[10].output[2] */
+ TRIG1_IN_TR_GROUP10_OUTPUT3 = 0x00000104u, /* tr_group[10].output[3] */
+ TRIG1_IN_TR_GROUP10_OUTPUT4 = 0x00000105u, /* tr_group[10].output[4] */
+ TRIG1_IN_TR_GROUP10_OUTPUT5 = 0x00000106u, /* tr_group[10].output[5] */
+ TRIG1_IN_TR_GROUP10_OUTPUT6 = 0x00000107u, /* tr_group[10].output[6] */
+ TRIG1_IN_TR_GROUP10_OUTPUT7 = 0x00000108u, /* tr_group[10].output[7] */
+ TRIG1_IN_TR_GROUP11_OUTPUT0 = 0x00000109u, /* tr_group[11].output[0] */
+ TRIG1_IN_TR_GROUP11_OUTPUT1 = 0x0000010Au, /* tr_group[11].output[1] */
+ TRIG1_IN_TR_GROUP11_OUTPUT2 = 0x0000010Bu, /* tr_group[11].output[2] */
+ TRIG1_IN_TR_GROUP11_OUTPUT3 = 0x0000010Cu, /* tr_group[11].output[3] */
+ TRIG1_IN_TR_GROUP11_OUTPUT4 = 0x0000010Du, /* tr_group[11].output[4] */
+ TRIG1_IN_TR_GROUP11_OUTPUT5 = 0x0000010Eu, /* tr_group[11].output[5] */
+ TRIG1_IN_TR_GROUP11_OUTPUT6 = 0x0000010Fu, /* tr_group[11].output[6] */
+ TRIG1_IN_TR_GROUP11_OUTPUT7 = 0x00000110u, /* tr_group[11].output[7] */
+ TRIG1_IN_TR_GROUP11_OUTPUT8 = 0x00000111u, /* tr_group[11].output[8] */
+ TRIG1_IN_TR_GROUP11_OUTPUT9 = 0x00000112u, /* tr_group[11].output[9] */
+ TRIG1_IN_TR_GROUP11_OUTPUT10 = 0x00000113u, /* tr_group[11].output[10] */
+ TRIG1_IN_TR_GROUP11_OUTPUT11 = 0x00000114u, /* tr_group[11].output[11] */
+ TRIG1_IN_TR_GROUP11_OUTPUT12 = 0x00000115u, /* tr_group[11].output[12] */
+ TRIG1_IN_TR_GROUP11_OUTPUT13 = 0x00000116u, /* tr_group[11].output[13] */
+ TRIG1_IN_TR_GROUP11_OUTPUT14 = 0x00000117u, /* tr_group[11].output[14] */
+ TRIG1_IN_TR_GROUP11_OUTPUT15 = 0x00000118u, /* tr_group[11].output[15] */
+ TRIG1_IN_TR_GROUP12_OUTPUT8 = 0x00000119u, /* tr_group[12].output[8] */
+ TRIG1_IN_TR_GROUP12_OUTPUT9 = 0x0000011Au, /* tr_group[12].output[9] */
+ TRIG1_IN_TR_GROUP13_OUTPUT0 = 0x0000011Bu, /* tr_group[13].output[0] */
+ TRIG1_IN_TR_GROUP13_OUTPUT1 = 0x0000011Cu, /* tr_group[13].output[1] */
+ TRIG1_IN_TR_GROUP13_OUTPUT2 = 0x0000011Du, /* tr_group[13].output[2] */
+ TRIG1_IN_TR_GROUP13_OUTPUT3 = 0x0000011Eu, /* tr_group[13].output[3] */
+ TRIG1_IN_TR_GROUP13_OUTPUT4 = 0x0000011Fu, /* tr_group[13].output[4] */
+ TRIG1_IN_TR_GROUP13_OUTPUT5 = 0x00000120u, /* tr_group[13].output[5] */
+ TRIG1_IN_TR_GROUP13_OUTPUT6 = 0x00000121u, /* tr_group[13].output[6] */
+ TRIG1_IN_TR_GROUP13_OUTPUT7 = 0x00000122u, /* tr_group[13].output[7] */
+ TRIG1_IN_TR_GROUP13_OUTPUT8 = 0x00000123u, /* tr_group[13].output[8] */
+ TRIG1_IN_TR_GROUP13_OUTPUT9 = 0x00000124u, /* tr_group[13].output[9] */
+ TRIG1_IN_TR_GROUP13_OUTPUT10 = 0x00000125u, /* tr_group[13].output[10] */
+ TRIG1_IN_TR_GROUP13_OUTPUT11 = 0x00000126u, /* tr_group[13].output[11] */
+ TRIG1_IN_TR_GROUP13_OUTPUT12 = 0x00000127u, /* tr_group[13].output[12] */
+ TRIG1_IN_TR_GROUP13_OUTPUT13 = 0x00000128u, /* tr_group[13].output[13] */
+ TRIG1_IN_TR_GROUP13_OUTPUT14 = 0x00000129u, /* tr_group[13].output[14] */
+ TRIG1_IN_TR_GROUP13_OUTPUT15 = 0x0000012Au, /* tr_group[13].output[15] */
+ TRIG1_IN_TR_GROUP14_OUTPUT0 = 0x0000012Bu, /* tr_group[14].output[0] */
+ TRIG1_IN_TR_GROUP14_OUTPUT1 = 0x0000012Cu, /* tr_group[14].output[1] */
+ TRIG1_IN_TR_GROUP14_OUTPUT2 = 0x0000012Du, /* tr_group[14].output[2] */
+ TRIG1_IN_TR_GROUP14_OUTPUT3 = 0x0000012Eu, /* tr_group[14].output[3] */
+ TRIG1_IN_TR_GROUP14_OUTPUT4 = 0x0000012Fu, /* tr_group[14].output[4] */
+ TRIG1_IN_TR_GROUP14_OUTPUT5 = 0x00000130u, /* tr_group[14].output[5] */
+ TRIG1_IN_TR_GROUP14_OUTPUT6 = 0x00000131u, /* tr_group[14].output[6] */
+ TRIG1_IN_TR_GROUP14_OUTPUT7 = 0x00000132u /* tr_group[14].output[7] */
+} en_trig_input_grp1_t;
+
+/* Trigger Input Group 2 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG2_IN_CPUSS_ZERO = 0x00000200u, /* cpuss.zero */
+ TRIG2_IN_TR_GROUP10_OUTPUT0 = 0x00000201u, /* tr_group[10].output[0] */
+ TRIG2_IN_TR_GROUP10_OUTPUT1 = 0x00000202u, /* tr_group[10].output[1] */
+ TRIG2_IN_TR_GROUP10_OUTPUT2 = 0x00000203u, /* tr_group[10].output[2] */
+ TRIG2_IN_TR_GROUP10_OUTPUT3 = 0x00000204u, /* tr_group[10].output[3] */
+ TRIG2_IN_TR_GROUP10_OUTPUT4 = 0x00000205u, /* tr_group[10].output[4] */
+ TRIG2_IN_TR_GROUP10_OUTPUT5 = 0x00000206u, /* tr_group[10].output[5] */
+ TRIG2_IN_TR_GROUP10_OUTPUT6 = 0x00000207u, /* tr_group[10].output[6] */
+ TRIG2_IN_TR_GROUP10_OUTPUT7 = 0x00000208u, /* tr_group[10].output[7] */
+ TRIG2_IN_TR_GROUP11_OUTPUT0 = 0x00000209u, /* tr_group[11].output[0] */
+ TRIG2_IN_TR_GROUP11_OUTPUT1 = 0x0000020Au, /* tr_group[11].output[1] */
+ TRIG2_IN_TR_GROUP11_OUTPUT2 = 0x0000020Bu, /* tr_group[11].output[2] */
+ TRIG2_IN_TR_GROUP11_OUTPUT3 = 0x0000020Cu, /* tr_group[11].output[3] */
+ TRIG2_IN_TR_GROUP11_OUTPUT4 = 0x0000020Du, /* tr_group[11].output[4] */
+ TRIG2_IN_TR_GROUP11_OUTPUT5 = 0x0000020Eu, /* tr_group[11].output[5] */
+ TRIG2_IN_TR_GROUP11_OUTPUT6 = 0x0000020Fu, /* tr_group[11].output[6] */
+ TRIG2_IN_TR_GROUP11_OUTPUT7 = 0x00000210u, /* tr_group[11].output[7] */
+ TRIG2_IN_TR_GROUP11_OUTPUT8 = 0x00000211u, /* tr_group[11].output[8] */
+ TRIG2_IN_TR_GROUP11_OUTPUT9 = 0x00000212u, /* tr_group[11].output[9] */
+ TRIG2_IN_TR_GROUP11_OUTPUT10 = 0x00000213u, /* tr_group[11].output[10] */
+ TRIG2_IN_TR_GROUP11_OUTPUT11 = 0x00000214u, /* tr_group[11].output[11] */
+ TRIG2_IN_TR_GROUP11_OUTPUT12 = 0x00000215u, /* tr_group[11].output[12] */
+ TRIG2_IN_TR_GROUP11_OUTPUT13 = 0x00000216u, /* tr_group[11].output[13] */
+ TRIG2_IN_TR_GROUP11_OUTPUT14 = 0x00000217u, /* tr_group[11].output[14] */
+ TRIG2_IN_TR_GROUP11_OUTPUT15 = 0x00000218u, /* tr_group[11].output[15] */
+ TRIG2_IN_TR_GROUP12_OUTPUT0 = 0x00000219u, /* tr_group[12].output[0] */
+ TRIG2_IN_TR_GROUP12_OUTPUT1 = 0x0000021Au, /* tr_group[12].output[1] */
+ TRIG2_IN_TR_GROUP12_OUTPUT2 = 0x0000021Bu, /* tr_group[12].output[2] */
+ TRIG2_IN_TR_GROUP12_OUTPUT3 = 0x0000021Cu, /* tr_group[12].output[3] */
+ TRIG2_IN_TR_GROUP12_OUTPUT4 = 0x0000021Du, /* tr_group[12].output[4] */
+ TRIG2_IN_TR_GROUP12_OUTPUT5 = 0x0000021Eu, /* tr_group[12].output[5] */
+ TRIG2_IN_TR_GROUP12_OUTPUT6 = 0x0000021Fu, /* tr_group[12].output[6] */
+ TRIG2_IN_TR_GROUP12_OUTPUT7 = 0x00000220u, /* tr_group[12].output[7] */
+ TRIG2_IN_TR_GROUP13_OUTPUT16 = 0x00000221u, /* tr_group[13].output[16] */
+ TRIG2_IN_TR_GROUP13_OUTPUT17 = 0x00000222u, /* tr_group[13].output[17] */
+ TRIG2_IN_TR_GROUP14_OUTPUT8 = 0x00000223u, /* tr_group[14].output[8] */
+ TRIG2_IN_TR_GROUP14_OUTPUT9 = 0x00000224u, /* tr_group[14].output[9] */
+ TRIG2_IN_TR_GROUP14_OUTPUT10 = 0x00000225u, /* tr_group[14].output[10] */
+ TRIG2_IN_TR_GROUP14_OUTPUT11 = 0x00000226u, /* tr_group[14].output[11] */
+ TRIG2_IN_TR_GROUP14_OUTPUT12 = 0x00000227u, /* tr_group[14].output[12] */
+ TRIG2_IN_TR_GROUP14_OUTPUT13 = 0x00000228u, /* tr_group[14].output[13] */
+ TRIG2_IN_TR_GROUP14_OUTPUT14 = 0x00000229u, /* tr_group[14].output[14] */
+ TRIG2_IN_TR_GROUP14_OUTPUT15 = 0x0000022Au /* tr_group[14].output[15] */
+} en_trig_input_grp2_t;
+
+/* Trigger Input Group 3 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG3_IN_CPUSS_ZERO = 0x00000300u, /* cpuss.zero */
+ TRIG3_IN_TR_GROUP10_OUTPUT0 = 0x00000301u, /* tr_group[10].output[0] */
+ TRIG3_IN_TR_GROUP10_OUTPUT1 = 0x00000302u, /* tr_group[10].output[1] */
+ TRIG3_IN_TR_GROUP10_OUTPUT2 = 0x00000303u, /* tr_group[10].output[2] */
+ TRIG3_IN_TR_GROUP10_OUTPUT3 = 0x00000304u, /* tr_group[10].output[3] */
+ TRIG3_IN_TR_GROUP10_OUTPUT4 = 0x00000305u, /* tr_group[10].output[4] */
+ TRIG3_IN_TR_GROUP10_OUTPUT5 = 0x00000306u, /* tr_group[10].output[5] */
+ TRIG3_IN_TR_GROUP10_OUTPUT6 = 0x00000307u, /* tr_group[10].output[6] */
+ TRIG3_IN_TR_GROUP10_OUTPUT7 = 0x00000308u, /* tr_group[10].output[7] */
+ TRIG3_IN_TR_GROUP11_OUTPUT0 = 0x00000309u, /* tr_group[11].output[0] */
+ TRIG3_IN_TR_GROUP11_OUTPUT1 = 0x0000030Au, /* tr_group[11].output[1] */
+ TRIG3_IN_TR_GROUP11_OUTPUT2 = 0x0000030Bu, /* tr_group[11].output[2] */
+ TRIG3_IN_TR_GROUP11_OUTPUT3 = 0x0000030Cu, /* tr_group[11].output[3] */
+ TRIG3_IN_TR_GROUP11_OUTPUT4 = 0x0000030Du, /* tr_group[11].output[4] */
+ TRIG3_IN_TR_GROUP11_OUTPUT5 = 0x0000030Eu, /* tr_group[11].output[5] */
+ TRIG3_IN_TR_GROUP11_OUTPUT6 = 0x0000030Fu, /* tr_group[11].output[6] */
+ TRIG3_IN_TR_GROUP11_OUTPUT7 = 0x00000310u, /* tr_group[11].output[7] */
+ TRIG3_IN_TR_GROUP11_OUTPUT8 = 0x00000311u, /* tr_group[11].output[8] */
+ TRIG3_IN_TR_GROUP11_OUTPUT9 = 0x00000312u, /* tr_group[11].output[9] */
+ TRIG3_IN_TR_GROUP11_OUTPUT10 = 0x00000313u, /* tr_group[11].output[10] */
+ TRIG3_IN_TR_GROUP11_OUTPUT11 = 0x00000314u, /* tr_group[11].output[11] */
+ TRIG3_IN_TR_GROUP11_OUTPUT12 = 0x00000315u, /* tr_group[11].output[12] */
+ TRIG3_IN_TR_GROUP11_OUTPUT13 = 0x00000316u, /* tr_group[11].output[13] */
+ TRIG3_IN_TR_GROUP11_OUTPUT14 = 0x00000317u, /* tr_group[11].output[14] */
+ TRIG3_IN_TR_GROUP11_OUTPUT15 = 0x00000318u, /* tr_group[11].output[15] */
+ TRIG3_IN_TR_GROUP12_OUTPUT0 = 0x00000319u, /* tr_group[12].output[0] */
+ TRIG3_IN_TR_GROUP12_OUTPUT1 = 0x0000031Au, /* tr_group[12].output[1] */
+ TRIG3_IN_TR_GROUP12_OUTPUT2 = 0x0000031Bu, /* tr_group[12].output[2] */
+ TRIG3_IN_TR_GROUP12_OUTPUT3 = 0x0000031Cu, /* tr_group[12].output[3] */
+ TRIG3_IN_TR_GROUP12_OUTPUT4 = 0x0000031Du, /* tr_group[12].output[4] */
+ TRIG3_IN_TR_GROUP12_OUTPUT5 = 0x0000031Eu, /* tr_group[12].output[5] */
+ TRIG3_IN_TR_GROUP12_OUTPUT6 = 0x0000031Fu, /* tr_group[12].output[6] */
+ TRIG3_IN_TR_GROUP12_OUTPUT7 = 0x00000320u, /* tr_group[12].output[7] */
+ TRIG3_IN_TR_GROUP13_OUTPUT16 = 0x00000321u, /* tr_group[13].output[16] */
+ TRIG3_IN_TR_GROUP13_OUTPUT17 = 0x00000322u, /* tr_group[13].output[17] */
+ TRIG3_IN_TR_GROUP14_OUTPUT8 = 0x00000323u, /* tr_group[14].output[8] */
+ TRIG3_IN_TR_GROUP14_OUTPUT9 = 0x00000324u, /* tr_group[14].output[9] */
+ TRIG3_IN_TR_GROUP14_OUTPUT10 = 0x00000325u, /* tr_group[14].output[10] */
+ TRIG3_IN_TR_GROUP14_OUTPUT11 = 0x00000326u, /* tr_group[14].output[11] */
+ TRIG3_IN_TR_GROUP14_OUTPUT12 = 0x00000327u, /* tr_group[14].output[12] */
+ TRIG3_IN_TR_GROUP14_OUTPUT13 = 0x00000328u, /* tr_group[14].output[13] */
+ TRIG3_IN_TR_GROUP14_OUTPUT14 = 0x00000329u, /* tr_group[14].output[14] */
+ TRIG3_IN_TR_GROUP14_OUTPUT15 = 0x0000032Au /* tr_group[14].output[15] */
+} en_trig_input_grp3_t;
+
+/* Trigger Input Group 4 - PROFILE trigger multiplexer */
+typedef enum
+{
+ TRIG4_IN_CPUSS_ZERO = 0x00000400u, /* cpuss.zero */
+ TRIG4_IN_TR_GROUP10_OUTPUT0 = 0x00000401u, /* tr_group[10].output[0] */
+ TRIG4_IN_TR_GROUP10_OUTPUT1 = 0x00000402u, /* tr_group[10].output[1] */
+ TRIG4_IN_TR_GROUP10_OUTPUT2 = 0x00000403u, /* tr_group[10].output[2] */
+ TRIG4_IN_TR_GROUP10_OUTPUT3 = 0x00000404u, /* tr_group[10].output[3] */
+ TRIG4_IN_TR_GROUP10_OUTPUT4 = 0x00000405u, /* tr_group[10].output[4] */
+ TRIG4_IN_TR_GROUP10_OUTPUT5 = 0x00000406u, /* tr_group[10].output[5] */
+ TRIG4_IN_TR_GROUP10_OUTPUT6 = 0x00000407u, /* tr_group[10].output[6] */
+ TRIG4_IN_TR_GROUP10_OUTPUT7 = 0x00000408u, /* tr_group[10].output[7] */
+ TRIG4_IN_TR_GROUP11_OUTPUT0 = 0x00000409u, /* tr_group[11].output[0] */
+ TRIG4_IN_TR_GROUP11_OUTPUT1 = 0x0000040Au, /* tr_group[11].output[1] */
+ TRIG4_IN_TR_GROUP11_OUTPUT2 = 0x0000040Bu, /* tr_group[11].output[2] */
+ TRIG4_IN_TR_GROUP11_OUTPUT3 = 0x0000040Cu, /* tr_group[11].output[3] */
+ TRIG4_IN_TR_GROUP11_OUTPUT4 = 0x0000040Du, /* tr_group[11].output[4] */
+ TRIG4_IN_TR_GROUP11_OUTPUT5 = 0x0000040Eu, /* tr_group[11].output[5] */
+ TRIG4_IN_TR_GROUP11_OUTPUT6 = 0x0000040Fu, /* tr_group[11].output[6] */
+ TRIG4_IN_TR_GROUP11_OUTPUT7 = 0x00000410u, /* tr_group[11].output[7] */
+ TRIG4_IN_TR_GROUP11_OUTPUT8 = 0x00000411u, /* tr_group[11].output[8] */
+ TRIG4_IN_TR_GROUP11_OUTPUT9 = 0x00000412u, /* tr_group[11].output[9] */
+ TRIG4_IN_TR_GROUP11_OUTPUT10 = 0x00000413u, /* tr_group[11].output[10] */
+ TRIG4_IN_TR_GROUP11_OUTPUT11 = 0x00000414u, /* tr_group[11].output[11] */
+ TRIG4_IN_TR_GROUP11_OUTPUT12 = 0x00000415u, /* tr_group[11].output[12] */
+ TRIG4_IN_TR_GROUP11_OUTPUT13 = 0x00000416u, /* tr_group[11].output[13] */
+ TRIG4_IN_TR_GROUP11_OUTPUT14 = 0x00000417u, /* tr_group[11].output[14] */
+ TRIG4_IN_TR_GROUP11_OUTPUT15 = 0x00000418u, /* tr_group[11].output[15] */
+ TRIG4_IN_TR_GROUP12_OUTPUT0 = 0x00000419u, /* tr_group[12].output[0] */
+ TRIG4_IN_TR_GROUP12_OUTPUT1 = 0x0000041Au, /* tr_group[12].output[1] */
+ TRIG4_IN_TR_GROUP12_OUTPUT2 = 0x0000041Bu, /* tr_group[12].output[2] */
+ TRIG4_IN_TR_GROUP12_OUTPUT3 = 0x0000041Cu, /* tr_group[12].output[3] */
+ TRIG4_IN_TR_GROUP12_OUTPUT4 = 0x0000041Du, /* tr_group[12].output[4] */
+ TRIG4_IN_TR_GROUP12_OUTPUT5 = 0x0000041Eu, /* tr_group[12].output[5] */
+ TRIG4_IN_TR_GROUP12_OUTPUT6 = 0x0000041Fu, /* tr_group[12].output[6] */
+ TRIG4_IN_TR_GROUP12_OUTPUT7 = 0x00000420u, /* tr_group[12].output[7] */
+ TRIG4_IN_TR_GROUP13_OUTPUT16 = 0x00000421u, /* tr_group[13].output[16] */
+ TRIG4_IN_TR_GROUP13_OUTPUT17 = 0x00000422u, /* tr_group[13].output[17] */
+ TRIG4_IN_TR_GROUP14_OUTPUT8 = 0x00000423u, /* tr_group[14].output[8] */
+ TRIG4_IN_TR_GROUP14_OUTPUT9 = 0x00000424u, /* tr_group[14].output[9] */
+ TRIG4_IN_TR_GROUP14_OUTPUT10 = 0x00000425u, /* tr_group[14].output[10] */
+ TRIG4_IN_TR_GROUP14_OUTPUT11 = 0x00000426u, /* tr_group[14].output[11] */
+ TRIG4_IN_TR_GROUP14_OUTPUT12 = 0x00000427u, /* tr_group[14].output[12] */
+ TRIG4_IN_TR_GROUP14_OUTPUT13 = 0x00000428u, /* tr_group[14].output[13] */
+ TRIG4_IN_TR_GROUP14_OUTPUT14 = 0x00000429u, /* tr_group[14].output[14] */
+ TRIG4_IN_TR_GROUP14_OUTPUT15 = 0x0000042Au /* tr_group[14].output[15] */
+} en_trig_input_grp4_t;
+
+/* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */
+typedef enum
+{
+ TRIG5_IN_CPUSS_ZERO = 0x00000500u, /* cpuss.zero */
+ TRIG5_IN_TR_GROUP10_OUTPUT0 = 0x00000501u, /* tr_group[10].output[0] */
+ TRIG5_IN_TR_GROUP10_OUTPUT1 = 0x00000502u, /* tr_group[10].output[1] */
+ TRIG5_IN_TR_GROUP10_OUTPUT2 = 0x00000503u, /* tr_group[10].output[2] */
+ TRIG5_IN_TR_GROUP10_OUTPUT3 = 0x00000504u, /* tr_group[10].output[3] */
+ TRIG5_IN_TR_GROUP10_OUTPUT4 = 0x00000505u, /* tr_group[10].output[4] */
+ TRIG5_IN_TR_GROUP10_OUTPUT5 = 0x00000506u, /* tr_group[10].output[5] */
+ TRIG5_IN_TR_GROUP10_OUTPUT6 = 0x00000507u, /* tr_group[10].output[6] */
+ TRIG5_IN_TR_GROUP10_OUTPUT7 = 0x00000508u, /* tr_group[10].output[7] */
+ TRIG5_IN_TR_GROUP11_OUTPUT0 = 0x00000509u, /* tr_group[11].output[0] */
+ TRIG5_IN_TR_GROUP11_OUTPUT1 = 0x0000050Au, /* tr_group[11].output[1] */
+ TRIG5_IN_TR_GROUP11_OUTPUT2 = 0x0000050Bu, /* tr_group[11].output[2] */
+ TRIG5_IN_TR_GROUP11_OUTPUT3 = 0x0000050Cu, /* tr_group[11].output[3] */
+ TRIG5_IN_TR_GROUP11_OUTPUT4 = 0x0000050Du, /* tr_group[11].output[4] */
+ TRIG5_IN_TR_GROUP11_OUTPUT5 = 0x0000050Eu, /* tr_group[11].output[5] */
+ TRIG5_IN_TR_GROUP11_OUTPUT6 = 0x0000050Fu, /* tr_group[11].output[6] */
+ TRIG5_IN_TR_GROUP11_OUTPUT7 = 0x00000510u, /* tr_group[11].output[7] */
+ TRIG5_IN_TR_GROUP11_OUTPUT8 = 0x00000511u, /* tr_group[11].output[8] */
+ TRIG5_IN_TR_GROUP11_OUTPUT9 = 0x00000512u, /* tr_group[11].output[9] */
+ TRIG5_IN_TR_GROUP11_OUTPUT10 = 0x00000513u, /* tr_group[11].output[10] */
+ TRIG5_IN_TR_GROUP11_OUTPUT11 = 0x00000514u, /* tr_group[11].output[11] */
+ TRIG5_IN_TR_GROUP11_OUTPUT12 = 0x00000515u, /* tr_group[11].output[12] */
+ TRIG5_IN_TR_GROUP11_OUTPUT13 = 0x00000516u, /* tr_group[11].output[13] */
+ TRIG5_IN_TR_GROUP11_OUTPUT14 = 0x00000517u, /* tr_group[11].output[14] */
+ TRIG5_IN_TR_GROUP11_OUTPUT15 = 0x00000518u, /* tr_group[11].output[15] */
+ TRIG5_IN_TR_GROUP12_OUTPUT0 = 0x00000519u, /* tr_group[12].output[0] */
+ TRIG5_IN_TR_GROUP12_OUTPUT1 = 0x0000051Au, /* tr_group[12].output[1] */
+ TRIG5_IN_TR_GROUP12_OUTPUT2 = 0x0000051Bu, /* tr_group[12].output[2] */
+ TRIG5_IN_TR_GROUP12_OUTPUT3 = 0x0000051Cu, /* tr_group[12].output[3] */
+ TRIG5_IN_TR_GROUP12_OUTPUT4 = 0x0000051Du, /* tr_group[12].output[4] */
+ TRIG5_IN_TR_GROUP12_OUTPUT5 = 0x0000051Eu, /* tr_group[12].output[5] */
+ TRIG5_IN_TR_GROUP12_OUTPUT6 = 0x0000051Fu, /* tr_group[12].output[6] */
+ TRIG5_IN_TR_GROUP12_OUTPUT7 = 0x00000520u, /* tr_group[12].output[7] */
+ TRIG5_IN_TR_GROUP13_OUTPUT16 = 0x00000521u, /* tr_group[13].output[16] */
+ TRIG5_IN_TR_GROUP13_OUTPUT17 = 0x00000522u, /* tr_group[13].output[17] */
+ TRIG5_IN_TR_GROUP14_OUTPUT8 = 0x00000523u, /* tr_group[14].output[8] */
+ TRIG5_IN_TR_GROUP14_OUTPUT9 = 0x00000524u, /* tr_group[14].output[9] */
+ TRIG5_IN_TR_GROUP14_OUTPUT10 = 0x00000525u, /* tr_group[14].output[10] */
+ TRIG5_IN_TR_GROUP14_OUTPUT11 = 0x00000526u, /* tr_group[14].output[11] */
+ TRIG5_IN_TR_GROUP14_OUTPUT12 = 0x00000527u, /* tr_group[14].output[12] */
+ TRIG5_IN_TR_GROUP14_OUTPUT13 = 0x00000528u, /* tr_group[14].output[13] */
+ TRIG5_IN_TR_GROUP14_OUTPUT14 = 0x00000529u, /* tr_group[14].output[14] */
+ TRIG5_IN_TR_GROUP14_OUTPUT15 = 0x0000052Au /* tr_group[14].output[15] */
+} en_trig_input_grp5_t;
+
+/* Trigger Input Group 6 - PASS trigger multiplexer */
+typedef enum
+{
+ TRIG6_IN_CPUSS_ZERO = 0x00000600u, /* cpuss.zero */
+ TRIG6_IN_TR_GROUP10_OUTPUT0 = 0x00000601u, /* tr_group[10].output[0] */
+ TRIG6_IN_TR_GROUP10_OUTPUT1 = 0x00000602u, /* tr_group[10].output[1] */
+ TRIG6_IN_TR_GROUP10_OUTPUT2 = 0x00000603u, /* tr_group[10].output[2] */
+ TRIG6_IN_TR_GROUP10_OUTPUT3 = 0x00000604u, /* tr_group[10].output[3] */
+ TRIG6_IN_TR_GROUP10_OUTPUT4 = 0x00000605u, /* tr_group[10].output[4] */
+ TRIG6_IN_TR_GROUP10_OUTPUT5 = 0x00000606u, /* tr_group[10].output[5] */
+ TRIG6_IN_TR_GROUP10_OUTPUT6 = 0x00000607u, /* tr_group[10].output[6] */
+ TRIG6_IN_TR_GROUP10_OUTPUT7 = 0x00000608u, /* tr_group[10].output[7] */
+ TRIG6_IN_TR_GROUP11_OUTPUT0 = 0x00000609u, /* tr_group[11].output[0] */
+ TRIG6_IN_TR_GROUP11_OUTPUT1 = 0x0000060Au, /* tr_group[11].output[1] */
+ TRIG6_IN_TR_GROUP11_OUTPUT2 = 0x0000060Bu, /* tr_group[11].output[2] */
+ TRIG6_IN_TR_GROUP11_OUTPUT3 = 0x0000060Cu, /* tr_group[11].output[3] */
+ TRIG6_IN_TR_GROUP11_OUTPUT4 = 0x0000060Du, /* tr_group[11].output[4] */
+ TRIG6_IN_TR_GROUP11_OUTPUT5 = 0x0000060Eu, /* tr_group[11].output[5] */
+ TRIG6_IN_TR_GROUP11_OUTPUT6 = 0x0000060Fu, /* tr_group[11].output[6] */
+ TRIG6_IN_TR_GROUP11_OUTPUT7 = 0x00000610u, /* tr_group[11].output[7] */
+ TRIG6_IN_TR_GROUP11_OUTPUT8 = 0x00000611u, /* tr_group[11].output[8] */
+ TRIG6_IN_TR_GROUP11_OUTPUT9 = 0x00000612u, /* tr_group[11].output[9] */
+ TRIG6_IN_TR_GROUP11_OUTPUT10 = 0x00000613u, /* tr_group[11].output[10] */
+ TRIG6_IN_TR_GROUP11_OUTPUT11 = 0x00000614u, /* tr_group[11].output[11] */
+ TRIG6_IN_TR_GROUP11_OUTPUT12 = 0x00000615u, /* tr_group[11].output[12] */
+ TRIG6_IN_TR_GROUP11_OUTPUT13 = 0x00000616u, /* tr_group[11].output[13] */
+ TRIG6_IN_TR_GROUP11_OUTPUT14 = 0x00000617u, /* tr_group[11].output[14] */
+ TRIG6_IN_TR_GROUP11_OUTPUT15 = 0x00000618u, /* tr_group[11].output[15] */
+ TRIG6_IN_TR_GROUP12_OUTPUT0 = 0x00000619u, /* tr_group[12].output[0] */
+ TRIG6_IN_TR_GROUP12_OUTPUT1 = 0x0000061Au, /* tr_group[12].output[1] */
+ TRIG6_IN_TR_GROUP12_OUTPUT2 = 0x0000061Bu, /* tr_group[12].output[2] */
+ TRIG6_IN_TR_GROUP12_OUTPUT3 = 0x0000061Cu, /* tr_group[12].output[3] */
+ TRIG6_IN_TR_GROUP12_OUTPUT4 = 0x0000061Du, /* tr_group[12].output[4] */
+ TRIG6_IN_TR_GROUP12_OUTPUT5 = 0x0000061Eu, /* tr_group[12].output[5] */
+ TRIG6_IN_TR_GROUP12_OUTPUT6 = 0x0000061Fu, /* tr_group[12].output[6] */
+ TRIG6_IN_TR_GROUP12_OUTPUT7 = 0x00000620u, /* tr_group[12].output[7] */
+ TRIG6_IN_TR_GROUP13_OUTPUT16 = 0x00000621u, /* tr_group[13].output[16] */
+ TRIG6_IN_TR_GROUP13_OUTPUT17 = 0x00000622u, /* tr_group[13].output[17] */
+ TRIG6_IN_TR_GROUP14_OUTPUT8 = 0x00000623u, /* tr_group[14].output[8] */
+ TRIG6_IN_TR_GROUP14_OUTPUT9 = 0x00000624u, /* tr_group[14].output[9] */
+ TRIG6_IN_TR_GROUP14_OUTPUT10 = 0x00000625u, /* tr_group[14].output[10] */
+ TRIG6_IN_TR_GROUP14_OUTPUT11 = 0x00000626u, /* tr_group[14].output[11] */
+ TRIG6_IN_TR_GROUP14_OUTPUT12 = 0x00000627u, /* tr_group[14].output[12] */
+ TRIG6_IN_TR_GROUP14_OUTPUT13 = 0x00000628u, /* tr_group[14].output[13] */
+ TRIG6_IN_TR_GROUP14_OUTPUT14 = 0x00000629u, /* tr_group[14].output[14] */
+ TRIG6_IN_TR_GROUP14_OUTPUT15 = 0x0000062Au /* tr_group[14].output[15] */
+} en_trig_input_grp6_t;
+
+/* Trigger Input Group 7 - UDB general purpose trigger multiplexer */
+typedef enum
+{
+ TRIG7_IN_CPUSS_ZERO = 0x00000700u, /* cpuss.zero */
+ TRIG7_IN_TR_GROUP10_OUTPUT0 = 0x00000701u, /* tr_group[10].output[0] */
+ TRIG7_IN_TR_GROUP10_OUTPUT1 = 0x00000702u, /* tr_group[10].output[1] */
+ TRIG7_IN_TR_GROUP10_OUTPUT2 = 0x00000703u, /* tr_group[10].output[2] */
+ TRIG7_IN_TR_GROUP10_OUTPUT3 = 0x00000704u, /* tr_group[10].output[3] */
+ TRIG7_IN_TR_GROUP10_OUTPUT4 = 0x00000705u, /* tr_group[10].output[4] */
+ TRIG7_IN_TR_GROUP10_OUTPUT5 = 0x00000706u, /* tr_group[10].output[5] */
+ TRIG7_IN_TR_GROUP10_OUTPUT6 = 0x00000707u, /* tr_group[10].output[6] */
+ TRIG7_IN_TR_GROUP10_OUTPUT7 = 0x00000708u, /* tr_group[10].output[7] */
+ TRIG7_IN_TR_GROUP11_OUTPUT0 = 0x00000709u, /* tr_group[11].output[0] */
+ TRIG7_IN_TR_GROUP11_OUTPUT1 = 0x0000070Au, /* tr_group[11].output[1] */
+ TRIG7_IN_TR_GROUP11_OUTPUT2 = 0x0000070Bu, /* tr_group[11].output[2] */
+ TRIG7_IN_TR_GROUP11_OUTPUT3 = 0x0000070Cu, /* tr_group[11].output[3] */
+ TRIG7_IN_TR_GROUP11_OUTPUT4 = 0x0000070Du, /* tr_group[11].output[4] */
+ TRIG7_IN_TR_GROUP11_OUTPUT5 = 0x0000070Eu, /* tr_group[11].output[5] */
+ TRIG7_IN_TR_GROUP11_OUTPUT6 = 0x0000070Fu, /* tr_group[11].output[6] */
+ TRIG7_IN_TR_GROUP11_OUTPUT7 = 0x00000710u, /* tr_group[11].output[7] */
+ TRIG7_IN_TR_GROUP11_OUTPUT8 = 0x00000711u, /* tr_group[11].output[8] */
+ TRIG7_IN_TR_GROUP11_OUTPUT9 = 0x00000712u, /* tr_group[11].output[9] */
+ TRIG7_IN_TR_GROUP11_OUTPUT10 = 0x00000713u, /* tr_group[11].output[10] */
+ TRIG7_IN_TR_GROUP11_OUTPUT11 = 0x00000714u, /* tr_group[11].output[11] */
+ TRIG7_IN_TR_GROUP11_OUTPUT12 = 0x00000715u, /* tr_group[11].output[12] */
+ TRIG7_IN_TR_GROUP11_OUTPUT13 = 0x00000716u, /* tr_group[11].output[13] */
+ TRIG7_IN_TR_GROUP11_OUTPUT14 = 0x00000717u, /* tr_group[11].output[14] */
+ TRIG7_IN_TR_GROUP11_OUTPUT15 = 0x00000718u, /* tr_group[11].output[15] */
+ TRIG7_IN_TR_GROUP12_OUTPUT0 = 0x00000719u, /* tr_group[12].output[0] */
+ TRIG7_IN_TR_GROUP12_OUTPUT1 = 0x0000071Au, /* tr_group[12].output[1] */
+ TRIG7_IN_TR_GROUP12_OUTPUT2 = 0x0000071Bu, /* tr_group[12].output[2] */
+ TRIG7_IN_TR_GROUP12_OUTPUT3 = 0x0000071Cu, /* tr_group[12].output[3] */
+ TRIG7_IN_TR_GROUP12_OUTPUT4 = 0x0000071Du, /* tr_group[12].output[4] */
+ TRIG7_IN_TR_GROUP12_OUTPUT5 = 0x0000071Eu, /* tr_group[12].output[5] */
+ TRIG7_IN_TR_GROUP12_OUTPUT6 = 0x0000071Fu, /* tr_group[12].output[6] */
+ TRIG7_IN_TR_GROUP12_OUTPUT7 = 0x00000720u, /* tr_group[12].output[7] */
+ TRIG7_IN_TR_GROUP13_OUTPUT16 = 0x00000721u, /* tr_group[13].output[16] */
+ TRIG7_IN_TR_GROUP13_OUTPUT17 = 0x00000722u, /* tr_group[13].output[17] */
+ TRIG7_IN_TR_GROUP14_OUTPUT8 = 0x00000723u, /* tr_group[14].output[8] */
+ TRIG7_IN_TR_GROUP14_OUTPUT9 = 0x00000724u, /* tr_group[14].output[9] */
+ TRIG7_IN_TR_GROUP14_OUTPUT10 = 0x00000725u, /* tr_group[14].output[10] */
+ TRIG7_IN_TR_GROUP14_OUTPUT11 = 0x00000726u, /* tr_group[14].output[11] */
+ TRIG7_IN_TR_GROUP14_OUTPUT12 = 0x00000727u, /* tr_group[14].output[12] */
+ TRIG7_IN_TR_GROUP14_OUTPUT13 = 0x00000728u, /* tr_group[14].output[13] */
+ TRIG7_IN_TR_GROUP14_OUTPUT14 = 0x00000729u, /* tr_group[14].output[14] */
+ TRIG7_IN_TR_GROUP14_OUTPUT15 = 0x0000072Au /* tr_group[14].output[15] */
+} en_trig_input_grp7_t;
+
+/* Trigger Input Group 8 - Trigger multiplexer to pins */
+typedef enum
+{
+ TRIG8_IN_CPUSS_ZERO = 0x00000800u, /* cpuss.zero */
+ TRIG8_IN_TR_GROUP10_OUTPUT0 = 0x00000801u, /* tr_group[10].output[0] */
+ TRIG8_IN_TR_GROUP10_OUTPUT1 = 0x00000802u, /* tr_group[10].output[1] */
+ TRIG8_IN_TR_GROUP10_OUTPUT2 = 0x00000803u, /* tr_group[10].output[2] */
+ TRIG8_IN_TR_GROUP10_OUTPUT3 = 0x00000804u, /* tr_group[10].output[3] */
+ TRIG8_IN_TR_GROUP10_OUTPUT4 = 0x00000805u, /* tr_group[10].output[4] */
+ TRIG8_IN_TR_GROUP10_OUTPUT5 = 0x00000806u, /* tr_group[10].output[5] */
+ TRIG8_IN_TR_GROUP10_OUTPUT6 = 0x00000807u, /* tr_group[10].output[6] */
+ TRIG8_IN_TR_GROUP10_OUTPUT7 = 0x00000808u, /* tr_group[10].output[7] */
+ TRIG8_IN_TR_GROUP11_OUTPUT0 = 0x00000809u, /* tr_group[11].output[0] */
+ TRIG8_IN_TR_GROUP11_OUTPUT1 = 0x0000080Au, /* tr_group[11].output[1] */
+ TRIG8_IN_TR_GROUP11_OUTPUT2 = 0x0000080Bu, /* tr_group[11].output[2] */
+ TRIG8_IN_TR_GROUP11_OUTPUT3 = 0x0000080Cu, /* tr_group[11].output[3] */
+ TRIG8_IN_TR_GROUP11_OUTPUT4 = 0x0000080Du, /* tr_group[11].output[4] */
+ TRIG8_IN_TR_GROUP11_OUTPUT5 = 0x0000080Eu, /* tr_group[11].output[5] */
+ TRIG8_IN_TR_GROUP11_OUTPUT6 = 0x0000080Fu, /* tr_group[11].output[6] */
+ TRIG8_IN_TR_GROUP11_OUTPUT7 = 0x00000810u, /* tr_group[11].output[7] */
+ TRIG8_IN_TR_GROUP11_OUTPUT8 = 0x00000811u, /* tr_group[11].output[8] */
+ TRIG8_IN_TR_GROUP11_OUTPUT9 = 0x00000812u, /* tr_group[11].output[9] */
+ TRIG8_IN_TR_GROUP11_OUTPUT10 = 0x00000813u, /* tr_group[11].output[10] */
+ TRIG8_IN_TR_GROUP11_OUTPUT11 = 0x00000814u, /* tr_group[11].output[11] */
+ TRIG8_IN_TR_GROUP11_OUTPUT12 = 0x00000815u, /* tr_group[11].output[12] */
+ TRIG8_IN_TR_GROUP11_OUTPUT13 = 0x00000816u, /* tr_group[11].output[13] */
+ TRIG8_IN_TR_GROUP11_OUTPUT14 = 0x00000817u, /* tr_group[11].output[14] */
+ TRIG8_IN_TR_GROUP11_OUTPUT15 = 0x00000818u, /* tr_group[11].output[15] */
+ TRIG8_IN_TR_GROUP12_OUTPUT0 = 0x00000819u, /* tr_group[12].output[0] */
+ TRIG8_IN_TR_GROUP12_OUTPUT1 = 0x0000081Au, /* tr_group[12].output[1] */
+ TRIG8_IN_TR_GROUP12_OUTPUT2 = 0x0000081Bu, /* tr_group[12].output[2] */
+ TRIG8_IN_TR_GROUP12_OUTPUT3 = 0x0000081Cu, /* tr_group[12].output[3] */
+ TRIG8_IN_TR_GROUP12_OUTPUT4 = 0x0000081Du, /* tr_group[12].output[4] */
+ TRIG8_IN_TR_GROUP12_OUTPUT5 = 0x0000081Eu, /* tr_group[12].output[5] */
+ TRIG8_IN_TR_GROUP12_OUTPUT6 = 0x0000081Fu, /* tr_group[12].output[6] */
+ TRIG8_IN_TR_GROUP12_OUTPUT7 = 0x00000820u, /* tr_group[12].output[7] */
+ TRIG8_IN_TR_GROUP13_OUTPUT16 = 0x00000821u, /* tr_group[13].output[16] */
+ TRIG8_IN_TR_GROUP13_OUTPUT17 = 0x00000822u, /* tr_group[13].output[17] */
+ TRIG8_IN_TR_GROUP14_OUTPUT8 = 0x00000823u, /* tr_group[14].output[8] */
+ TRIG8_IN_TR_GROUP14_OUTPUT9 = 0x00000824u, /* tr_group[14].output[9] */
+ TRIG8_IN_TR_GROUP14_OUTPUT10 = 0x00000825u, /* tr_group[14].output[10] */
+ TRIG8_IN_TR_GROUP14_OUTPUT11 = 0x00000826u, /* tr_group[14].output[11] */
+ TRIG8_IN_TR_GROUP14_OUTPUT12 = 0x00000827u, /* tr_group[14].output[12] */
+ TRIG8_IN_TR_GROUP14_OUTPUT13 = 0x00000828u, /* tr_group[14].output[13] */
+ TRIG8_IN_TR_GROUP14_OUTPUT14 = 0x00000829u, /* tr_group[14].output[14] */
+ TRIG8_IN_TR_GROUP14_OUTPUT15 = 0x0000082Au /* tr_group[14].output[15] */
+} en_trig_input_grp8_t;
+
+/* Trigger Input Group 9 - Feedback mux to USB DMA interface */
+typedef enum
+{
+ TRIG9_IN_CPUSS_ZERO = 0x00000900u, /* cpuss.zero */
+ TRIG9_IN_CPUSS_DW0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */
+ TRIG9_IN_CPUSS_DW0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT0 = 0x00000911u, /* cpuss.dw1_tr_out[0] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT1 = 0x00000912u, /* cpuss.dw1_tr_out[1] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT2 = 0x00000913u, /* cpuss.dw1_tr_out[2] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT3 = 0x00000914u, /* cpuss.dw1_tr_out[3] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT4 = 0x00000915u, /* cpuss.dw1_tr_out[4] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT5 = 0x00000916u, /* cpuss.dw1_tr_out[5] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT6 = 0x00000917u, /* cpuss.dw1_tr_out[6] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT7 = 0x00000918u, /* cpuss.dw1_tr_out[7] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT8 = 0x00000919u, /* cpuss.dw1_tr_out[8] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT9 = 0x0000091Au, /* cpuss.dw1_tr_out[9] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT10 = 0x0000091Bu, /* cpuss.dw1_tr_out[10] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT11 = 0x0000091Cu, /* cpuss.dw1_tr_out[11] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT12 = 0x0000091Du, /* cpuss.dw1_tr_out[12] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT13 = 0x0000091Eu, /* cpuss.dw1_tr_out[13] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT14 = 0x0000091Fu, /* cpuss.dw1_tr_out[14] */
+ TRIG9_IN_CPUSS_DW1_TR_OUT15 = 0x00000920u /* cpuss.dw1_tr_out[15] */
+} en_trig_input_grp9_t;
+
+/* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
+typedef enum
+{
+ TRIG10_IN_CPUSS_ZERO = 0x00000A00u, /* cpuss.zero */
+ TRIG10_IN_CPUSS_DW0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */
+ TRIG10_IN_CPUSS_DW0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT0 = 0x00000A11u, /* cpuss.dw1_tr_out[0] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT1 = 0x00000A12u, /* cpuss.dw1_tr_out[1] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT2 = 0x00000A13u, /* cpuss.dw1_tr_out[2] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT3 = 0x00000A14u, /* cpuss.dw1_tr_out[3] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT4 = 0x00000A15u, /* cpuss.dw1_tr_out[4] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT5 = 0x00000A16u, /* cpuss.dw1_tr_out[5] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT6 = 0x00000A17u, /* cpuss.dw1_tr_out[6] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT7 = 0x00000A18u, /* cpuss.dw1_tr_out[7] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT8 = 0x00000A19u, /* cpuss.dw1_tr_out[8] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT9 = 0x00000A1Au, /* cpuss.dw1_tr_out[9] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT10 = 0x00000A1Bu, /* cpuss.dw1_tr_out[10] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT11 = 0x00000A1Cu, /* cpuss.dw1_tr_out[11] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT12 = 0x00000A1Du, /* cpuss.dw1_tr_out[12] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT13 = 0x00000A1Eu, /* cpuss.dw1_tr_out[13] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT14 = 0x00000A1Fu, /* cpuss.dw1_tr_out[14] */
+ TRIG10_IN_CPUSS_DW1_TR_OUT15 = 0x00000A20u /* cpuss.dw1_tr_out[15] */
+} en_trig_input_grp10_t;
+
+/* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
+typedef enum
+{
+ TRIG11_IN_CPUSS_ZERO = 0x00000B00u, /* cpuss.zero */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW0 = 0x00000B01u, /* tcpwm[0].tr_overflow[0] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW1 = 0x00000B02u, /* tcpwm[0].tr_overflow[1] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW2 = 0x00000B03u, /* tcpwm[0].tr_overflow[2] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW3 = 0x00000B04u, /* tcpwm[0].tr_overflow[3] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW4 = 0x00000B05u, /* tcpwm[0].tr_overflow[4] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW5 = 0x00000B06u, /* tcpwm[0].tr_overflow[5] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW6 = 0x00000B07u, /* tcpwm[0].tr_overflow[6] */
+ TRIG11_IN_TCPWM0_TR_OVERFLOW7 = 0x00000B08u, /* tcpwm[0].tr_overflow[7] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x00000B09u, /* tcpwm[0].tr_compare_match[0] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[1] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x00000B0Bu, /* tcpwm[0].tr_compare_match[2] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x00000B0Cu, /* tcpwm[0].tr_compare_match[3] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x00000B0Eu, /* tcpwm[0].tr_compare_match[5] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x00000B0Fu, /* tcpwm[0].tr_compare_match[6] */
+ TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x00000B10u, /* tcpwm[0].tr_compare_match[7] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW0 = 0x00000B11u, /* tcpwm[0].tr_underflow[0] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW1 = 0x00000B12u, /* tcpwm[0].tr_underflow[1] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW2 = 0x00000B13u, /* tcpwm[0].tr_underflow[2] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW3 = 0x00000B14u, /* tcpwm[0].tr_underflow[3] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW4 = 0x00000B15u, /* tcpwm[0].tr_underflow[4] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW5 = 0x00000B16u, /* tcpwm[0].tr_underflow[5] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW6 = 0x00000B17u, /* tcpwm[0].tr_underflow[6] */
+ TRIG11_IN_TCPWM0_TR_UNDERFLOW7 = 0x00000B18u, /* tcpwm[0].tr_underflow[7] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW0 = 0x00000B19u, /* tcpwm[1].tr_overflow[0] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW1 = 0x00000B1Au, /* tcpwm[1].tr_overflow[1] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW2 = 0x00000B1Bu, /* tcpwm[1].tr_overflow[2] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW3 = 0x00000B1Cu, /* tcpwm[1].tr_overflow[3] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW4 = 0x00000B1Du, /* tcpwm[1].tr_overflow[4] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW5 = 0x00000B1Eu, /* tcpwm[1].tr_overflow[5] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW6 = 0x00000B1Fu, /* tcpwm[1].tr_overflow[6] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW7 = 0x00000B20u, /* tcpwm[1].tr_overflow[7] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW8 = 0x00000B21u, /* tcpwm[1].tr_overflow[8] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW9 = 0x00000B22u, /* tcpwm[1].tr_overflow[9] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW10 = 0x00000B23u, /* tcpwm[1].tr_overflow[10] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW11 = 0x00000B24u, /* tcpwm[1].tr_overflow[11] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW12 = 0x00000B25u, /* tcpwm[1].tr_overflow[12] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW13 = 0x00000B26u, /* tcpwm[1].tr_overflow[13] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW14 = 0x00000B27u, /* tcpwm[1].tr_overflow[14] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW15 = 0x00000B28u, /* tcpwm[1].tr_overflow[15] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW16 = 0x00000B29u, /* tcpwm[1].tr_overflow[16] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW17 = 0x00000B2Au, /* tcpwm[1].tr_overflow[17] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW18 = 0x00000B2Bu, /* tcpwm[1].tr_overflow[18] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW19 = 0x00000B2Cu, /* tcpwm[1].tr_overflow[19] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW20 = 0x00000B2Du, /* tcpwm[1].tr_overflow[20] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW21 = 0x00000B2Eu, /* tcpwm[1].tr_overflow[21] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW22 = 0x00000B2Fu, /* tcpwm[1].tr_overflow[22] */
+ TRIG11_IN_TCPWM1_TR_OVERFLOW23 = 0x00000B30u, /* tcpwm[1].tr_overflow[23] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x00000B31u, /* tcpwm[1].tr_compare_match[0] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x00000B32u, /* tcpwm[1].tr_compare_match[1] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x00000B33u, /* tcpwm[1].tr_compare_match[2] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x00000B34u, /* tcpwm[1].tr_compare_match[3] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x00000B35u, /* tcpwm[1].tr_compare_match[4] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x00000B36u, /* tcpwm[1].tr_compare_match[5] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x00000B37u, /* tcpwm[1].tr_compare_match[6] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x00000B38u, /* tcpwm[1].tr_compare_match[7] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x00000B39u, /* tcpwm[1].tr_compare_match[8] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x00000B3Au, /* tcpwm[1].tr_compare_match[9] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x00000B3Bu, /* tcpwm[1].tr_compare_match[10] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x00000B3Cu, /* tcpwm[1].tr_compare_match[11] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x00000B3Du, /* tcpwm[1].tr_compare_match[12] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x00000B3Eu, /* tcpwm[1].tr_compare_match[13] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x00000B3Fu, /* tcpwm[1].tr_compare_match[14] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x00000B40u, /* tcpwm[1].tr_compare_match[15] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x00000B41u, /* tcpwm[1].tr_compare_match[16] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x00000B42u, /* tcpwm[1].tr_compare_match[17] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x00000B43u, /* tcpwm[1].tr_compare_match[18] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x00000B44u, /* tcpwm[1].tr_compare_match[19] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x00000B45u, /* tcpwm[1].tr_compare_match[20] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x00000B46u, /* tcpwm[1].tr_compare_match[21] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x00000B47u, /* tcpwm[1].tr_compare_match[22] */
+ TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x00000B48u, /* tcpwm[1].tr_compare_match[23] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW0 = 0x00000B49u, /* tcpwm[1].tr_underflow[0] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW1 = 0x00000B4Au, /* tcpwm[1].tr_underflow[1] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW2 = 0x00000B4Bu, /* tcpwm[1].tr_underflow[2] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW3 = 0x00000B4Cu, /* tcpwm[1].tr_underflow[3] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW4 = 0x00000B4Du, /* tcpwm[1].tr_underflow[4] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW5 = 0x00000B4Eu, /* tcpwm[1].tr_underflow[5] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW6 = 0x00000B4Fu, /* tcpwm[1].tr_underflow[6] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW7 = 0x00000B50u, /* tcpwm[1].tr_underflow[7] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW8 = 0x00000B51u, /* tcpwm[1].tr_underflow[8] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW9 = 0x00000B52u, /* tcpwm[1].tr_underflow[9] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x00000B53u, /* tcpwm[1].tr_underflow[10] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x00000B54u, /* tcpwm[1].tr_underflow[11] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x00000B55u, /* tcpwm[1].tr_underflow[12] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x00000B56u, /* tcpwm[1].tr_underflow[13] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x00000B57u, /* tcpwm[1].tr_underflow[14] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x00000B58u, /* tcpwm[1].tr_underflow[15] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x00000B59u, /* tcpwm[1].tr_underflow[16] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x00000B5Au, /* tcpwm[1].tr_underflow[17] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x00000B5Bu, /* tcpwm[1].tr_underflow[18] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x00000B5Cu, /* tcpwm[1].tr_underflow[19] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x00000B5Du, /* tcpwm[1].tr_underflow[20] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x00000B5Eu, /* tcpwm[1].tr_underflow[21] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x00000B5Fu, /* tcpwm[1].tr_underflow[22] */
+ TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x00000B60u /* tcpwm[1].tr_underflow[23] */
+} en_trig_input_grp11_t;
+
+/* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
+typedef enum
+{
+ TRIG12_IN_CPUSS_ZERO = 0x00000C00u, /* cpuss.zero */
+ TRIG12_IN_PERI_TR_IO_INPUT0 = 0x00000C01u, /* peri.tr_io_input[0] */
+ TRIG12_IN_PERI_TR_IO_INPUT1 = 0x00000C02u, /* peri.tr_io_input[1] */
+ TRIG12_IN_PERI_TR_IO_INPUT2 = 0x00000C03u, /* peri.tr_io_input[2] */
+ TRIG12_IN_PERI_TR_IO_INPUT3 = 0x00000C04u, /* peri.tr_io_input[3] */
+ TRIG12_IN_PERI_TR_IO_INPUT4 = 0x00000C05u, /* peri.tr_io_input[4] */
+ TRIG12_IN_PERI_TR_IO_INPUT5 = 0x00000C06u, /* peri.tr_io_input[5] */
+ TRIG12_IN_PERI_TR_IO_INPUT6 = 0x00000C07u, /* peri.tr_io_input[6] */
+ TRIG12_IN_PERI_TR_IO_INPUT7 = 0x00000C08u, /* peri.tr_io_input[7] */
+ TRIG12_IN_PERI_TR_IO_INPUT8 = 0x00000C09u, /* peri.tr_io_input[8] */
+ TRIG12_IN_PERI_TR_IO_INPUT9 = 0x00000C0Au, /* peri.tr_io_input[9] */
+ TRIG12_IN_PERI_TR_IO_INPUT10 = 0x00000C0Bu, /* peri.tr_io_input[10] */
+ TRIG12_IN_PERI_TR_IO_INPUT11 = 0x00000C0Cu, /* peri.tr_io_input[11] */
+ TRIG12_IN_PERI_TR_IO_INPUT12 = 0x00000C0Du, /* peri.tr_io_input[12] */
+ TRIG12_IN_PERI_TR_IO_INPUT13 = 0x00000C0Eu, /* peri.tr_io_input[13] */
+ TRIG12_IN_PERI_TR_IO_INPUT14 = 0x00000C0Fu, /* peri.tr_io_input[14] */
+ TRIG12_IN_PERI_TR_IO_INPUT15 = 0x00000C10u, /* peri.tr_io_input[15] */
+ TRIG12_IN_PERI_TR_IO_INPUT16 = 0x00000C11u, /* peri.tr_io_input[16] */
+ TRIG12_IN_PERI_TR_IO_INPUT17 = 0x00000C12u, /* peri.tr_io_input[17] */
+ TRIG12_IN_PERI_TR_IO_INPUT18 = 0x00000C13u, /* peri.tr_io_input[18] */
+ TRIG12_IN_PERI_TR_IO_INPUT19 = 0x00000C14u, /* peri.tr_io_input[19] */
+ TRIG12_IN_PERI_TR_IO_INPUT20 = 0x00000C15u, /* peri.tr_io_input[20] */
+ TRIG12_IN_PERI_TR_IO_INPUT21 = 0x00000C16u, /* peri.tr_io_input[21] */
+ TRIG12_IN_PERI_TR_IO_INPUT22 = 0x00000C17u, /* peri.tr_io_input[22] */
+ TRIG12_IN_PERI_TR_IO_INPUT23 = 0x00000C18u, /* peri.tr_io_input[23] */
+ TRIG12_IN_PERI_TR_IO_INPUT24 = 0x00000C19u, /* peri.tr_io_input[24] */
+ TRIG12_IN_PERI_TR_IO_INPUT25 = 0x00000C1Au, /* peri.tr_io_input[25] */
+ TRIG12_IN_PERI_TR_IO_INPUT26 = 0x00000C1Bu, /* peri.tr_io_input[26] */
+ TRIG12_IN_PERI_TR_IO_INPUT27 = 0x00000C1Cu /* peri.tr_io_input[27] */
+} en_trig_input_grp12_t;
+
+/* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
+typedef enum
+{
+ TRIG13_IN_CPUSS_ZERO = 0x00000D00u, /* cpuss.zero */
+ TRIG13_IN_SCB0_TR_TX_REQ = 0x00000D01u, /* scb[0].tr_tx_req */
+ TRIG13_IN_SCB0_TR_RX_REQ = 0x00000D02u, /* scb[0].tr_rx_req */
+ TRIG13_IN_SCB1_TR_TX_REQ = 0x00000D03u, /* scb[1].tr_tx_req */
+ TRIG13_IN_SCB1_TR_RX_REQ = 0x00000D04u, /* scb[1].tr_rx_req */
+ TRIG13_IN_SCB2_TR_TX_REQ = 0x00000D05u, /* scb[2].tr_tx_req */
+ TRIG13_IN_SCB2_TR_RX_REQ = 0x00000D06u, /* scb[2].tr_rx_req */
+ TRIG13_IN_SCB3_TR_TX_REQ = 0x00000D07u, /* scb[3].tr_tx_req */
+ TRIG13_IN_SCB3_TR_RX_REQ = 0x00000D08u, /* scb[3].tr_rx_req */
+ TRIG13_IN_SCB4_TR_TX_REQ = 0x00000D09u, /* scb[4].tr_tx_req */
+ TRIG13_IN_SCB4_TR_RX_REQ = 0x00000D0Au, /* scb[4].tr_rx_req */
+ TRIG13_IN_SCB5_TR_TX_REQ = 0x00000D0Bu, /* scb[5].tr_tx_req */
+ TRIG13_IN_SCB5_TR_RX_REQ = 0x00000D0Cu, /* scb[5].tr_rx_req */
+ TRIG13_IN_SCB6_TR_TX_REQ = 0x00000D0Du, /* scb[6].tr_tx_req */
+ TRIG13_IN_SCB6_TR_RX_REQ = 0x00000D0Eu, /* scb[6].tr_rx_req */
+ TRIG13_IN_SCB7_TR_TX_REQ = 0x00000D0Fu, /* scb[7].tr_tx_req */
+ TRIG13_IN_SCB7_TR_RX_REQ = 0x00000D10u, /* scb[7].tr_rx_req */
+ TRIG13_IN_SCB8_TR_TX_REQ = 0x00000D11u, /* scb[8].tr_tx_req */
+ TRIG13_IN_SCB8_TR_RX_REQ = 0x00000D12u, /* scb[8].tr_rx_req */
+ TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x00000D13u, /* audioss.tr_pdm_rx_req */
+ TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x00000D14u, /* audioss.tr_i2s_tx_req */
+ TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x00000D15u, /* audioss.tr_i2s_rx_req */
+ TRIG13_IN_SMIF_TR_TX_REQ = 0x00000D16u, /* smif.tr_tx_req */
+ TRIG13_IN_SMIF_TR_RX_REQ = 0x00000D17u, /* smif.tr_rx_req */
+ TRIG13_IN_USB_DMA_REQ0 = 0x00000D18u, /* usb.dma_req[0] */
+ TRIG13_IN_USB_DMA_REQ1 = 0x00000D19u, /* usb.dma_req[1] */
+ TRIG13_IN_USB_DMA_REQ2 = 0x00000D1Au, /* usb.dma_req[2] */
+ TRIG13_IN_USB_DMA_REQ3 = 0x00000D1Bu, /* usb.dma_req[3] */
+ TRIG13_IN_USB_DMA_REQ4 = 0x00000D1Cu, /* usb.dma_req[4] */
+ TRIG13_IN_USB_DMA_REQ5 = 0x00000D1Du, /* usb.dma_req[5] */
+ TRIG13_IN_USB_DMA_REQ6 = 0x00000D1Eu, /* usb.dma_req[6] */
+ TRIG13_IN_USB_DMA_REQ7 = 0x00000D1Fu, /* usb.dma_req[7] */
+ TRIG13_IN_CSD_TR_ADC_DONE = 0x00000D20u, /* csd.tr_adc_done */
+ TRIG13_IN_CSD_DSI_SENSE_OUT = 0x00000D21u /* csd.dsi_sense_out */
+} en_trig_input_grp13_t;
+
+/* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
+typedef enum
+{
+ TRIG14_IN_CPUSS_ZERO = 0x00000E00u, /* cpuss.zero */
+ TRIG14_IN_UDB_TR_UDB0 = 0x00000E01u, /* udb.tr_udb[0] */
+ TRIG14_IN_UDB_TR_UDB1 = 0x00000E02u, /* udb.tr_udb[1] */
+ TRIG14_IN_UDB_TR_UDB2 = 0x00000E03u, /* udb.tr_udb[2] */
+ TRIG14_IN_UDB_TR_UDB3 = 0x00000E04u, /* udb.tr_udb[3] */
+ TRIG14_IN_UDB_TR_UDB4 = 0x00000E05u, /* udb.tr_udb[4] */
+ TRIG14_IN_UDB_TR_UDB5 = 0x00000E06u, /* udb.tr_udb[5] */
+ TRIG14_IN_UDB_TR_UDB6 = 0x00000E07u, /* udb.tr_udb[6] */
+ TRIG14_IN_UDB_TR_UDB7 = 0x00000E08u, /* udb.tr_udb[7] */
+ TRIG14_IN_UDB_TR_UDB8 = 0x00000E09u, /* udb.tr_udb[8] */
+ TRIG14_IN_UDB_TR_UDB9 = 0x00000E0Au, /* udb.tr_udb[9] */
+ TRIG14_IN_UDB_TR_UDB10 = 0x00000E0Bu, /* udb.tr_udb[10] */
+ TRIG14_IN_UDB_TR_UDB11 = 0x00000E0Cu, /* udb.tr_udb[11] */
+ TRIG14_IN_UDB_TR_UDB12 = 0x00000E0Du, /* udb.tr_udb[12] */
+ TRIG14_IN_UDB_TR_UDB13 = 0x00000E0Eu, /* udb.tr_udb[13] */
+ TRIG14_IN_UDB_TR_UDB14 = 0x00000E0Fu, /* udb.tr_udb[14] */
+ TRIG14_IN_UDB_TR_UDB15 = 0x00000E10u, /* udb.tr_udb[15] */
+ TRIG14_IN_UDB_DSI_OUT_TR0 = 0x00000E11u, /* udb.dsi_out_tr[0] */
+ TRIG14_IN_UDB_DSI_OUT_TR1 = 0x00000E12u, /* udb.dsi_out_tr[1] */
+ TRIG14_IN_CPUSS_CTI_TR_OUT0 = 0x00000E13u, /* cpuss.cti_tr_out[0] */
+ TRIG14_IN_CPUSS_CTI_TR_OUT1 = 0x00000E14u, /* cpuss.cti_tr_out[1] */
+ TRIG14_IN_PASS_TR_SAR_OUT = 0x00000E15u, /* pass.tr_sar_out */
+ TRIG14_IN_PASS_TR_CTDAC_EMPTY = 0x00000E16u, /* pass.tr_ctdac_empty */
+ TRIG14_IN_PASS_DSI_CTB_CMP0 = 0x00000E17u, /* pass.dsi_ctb_cmp0 */
+ TRIG14_IN_PASS_DSI_CTB_CMP1 = 0x00000E18u, /* pass.dsi_ctb_cmp1 */
+ TRIG14_IN_LPCOMP_DSI_COMP0 = 0x00000E19u, /* lpcomp.dsi_comp0 */
+ TRIG14_IN_LPCOMP_DSI_COMP1 = 0x00000E1Au, /* lpcomp.dsi_comp1 */
+ TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x00000E1Bu, /* scb[0].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x00000E1Cu, /* scb[1].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x00000E1Du, /* scb[2].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x00000E1Eu, /* scb[3].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x00000E1Fu, /* scb[4].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x00000E20u, /* scb[5].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x00000E21u, /* scb[6].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x00000E22u, /* scb[7].tr_i2c_scl_filtered */
+ TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x00000E23u, /* scb[8].tr_i2c_scl_filtered */
+ TRIG14_IN_CPUSS_TR_FAULT0 = 0x00000E24u, /* cpuss.tr_fault[0] */
+ TRIG14_IN_CPUSS_TR_FAULT1 = 0x00000E25u /* cpuss.tr_fault[1] */
+} en_trig_input_grp14_t;
+
+/* Trigger Group Outputs */
+/* Trigger Output Group 0 - DMA Request Assignments */
+typedef enum
+{
+ TRIG0_OUT_CPUSS_DW0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */
+ TRIG0_OUT_CPUSS_DW0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */
+} en_trig_output_grp0_t;
+
+/* Trigger Output Group 1 - DMA Request Assignments */
+typedef enum
+{
+ TRIG1_OUT_CPUSS_DW1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN7 = 0x40000107u, /* cpuss.dw1_tr_in[7] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN8 = 0x40000108u, /* cpuss.dw1_tr_in[8] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN9 = 0x40000109u, /* cpuss.dw1_tr_in[9] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN10 = 0x4000010Au, /* cpuss.dw1_tr_in[10] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN11 = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN12 = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN13 = 0x4000010Du, /* cpuss.dw1_tr_in[13] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN14 = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */
+ TRIG1_OUT_CPUSS_DW1_TR_IN15 = 0x4000010Fu /* cpuss.dw1_tr_in[15] */
+} en_trig_output_grp1_t;
+
+/* Trigger Output Group 2 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG2_OUT_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */
+ TRIG2_OUT_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */
+ TRIG2_OUT_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */
+ TRIG2_OUT_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */
+ TRIG2_OUT_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */
+ TRIG2_OUT_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */
+ TRIG2_OUT_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */
+ TRIG2_OUT_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */
+ TRIG2_OUT_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */
+ TRIG2_OUT_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */
+ TRIG2_OUT_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */
+ TRIG2_OUT_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */
+ TRIG2_OUT_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */
+ TRIG2_OUT_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */
+} en_trig_output_grp2_t;
+
+/* Trigger Output Group 3 - TCPWM trigger inputs */
+typedef enum
+{
+ TRIG3_OUT_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */
+ TRIG3_OUT_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */
+ TRIG3_OUT_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */
+ TRIG3_OUT_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */
+ TRIG3_OUT_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */
+ TRIG3_OUT_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */
+ TRIG3_OUT_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */
+ TRIG3_OUT_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */
+ TRIG3_OUT_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */
+ TRIG3_OUT_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */
+ TRIG3_OUT_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */
+ TRIG3_OUT_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */
+ TRIG3_OUT_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */
+ TRIG3_OUT_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */
+} en_trig_output_grp3_t;
+
+/* Trigger Output Group 4 - PROFILE trigger multiplexer */
+typedef enum
+{
+ TRIG4_OUT_PROFILE_TR_START = 0x40000400u, /* profile.tr_start */
+ TRIG4_OUT_PROFILE_TR_STOP = 0x40000401u /* profile.tr_stop */
+} en_trig_output_grp4_t;
+
+/* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */
+typedef enum
+{
+ TRIG5_OUT_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */
+ TRIG5_OUT_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */
+} en_trig_output_grp5_t;
+
+/* Trigger Output Group 6 - PASS trigger multiplexer */
+typedef enum
+{
+ TRIG6_OUT_PASS_TR_SAR_IN = 0x40000600u /* pass.tr_sar_in */
+} en_trig_output_grp6_t;
+
+/* Trigger Output Group 7 - UDB general purpose trigger multiplexer */
+typedef enum
+{
+ TRIG7_OUT_UDB_TR_IN0 = 0x40000700u, /* udb.tr_in[0] */
+ TRIG7_OUT_UDB_TR_IN1 = 0x40000701u /* udb.tr_in[1] */
+} en_trig_output_grp7_t;
+
+/* Trigger Output Group 8 - Trigger multiplexer to pins */
+typedef enum
+{
+ TRIG8_OUT_PERI_TR_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */
+ TRIG8_OUT_PERI_TR_IO_OUTPUT1 = 0x40000801u /* peri.tr_io_output[1] */
+} en_trig_output_grp8_t;
+
+/* Trigger Output Group 9 - Feedback mux to USB DMA interface */
+typedef enum
+{
+ TRIG9_OUT_USB_DMA_BURSTEND0 = 0x40000900u, /* usb.dma_burstend[0] */
+ TRIG9_OUT_USB_DMA_BURSTEND1 = 0x40000901u, /* usb.dma_burstend[1] */
+ TRIG9_OUT_USB_DMA_BURSTEND2 = 0x40000902u, /* usb.dma_burstend[2] */
+ TRIG9_OUT_USB_DMA_BURSTEND3 = 0x40000903u, /* usb.dma_burstend[3] */
+ TRIG9_OUT_USB_DMA_BURSTEND4 = 0x40000904u, /* usb.dma_burstend[4] */
+ TRIG9_OUT_USB_DMA_BURSTEND5 = 0x40000905u, /* usb.dma_burstend[5] */
+ TRIG9_OUT_USB_DMA_BURSTEND6 = 0x40000906u, /* usb.dma_burstend[6] */
+ TRIG9_OUT_USB_DMA_BURSTEND7 = 0x40000907u /* usb.dma_burstend[7] */
+} en_trig_output_grp9_t;
+
+/* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
+typedef enum
+{
+ TRIG10_OUT_UDB_TR_DW_ACK0 = 0x40000A00u, /* udb.tr_dw_ack[0] */
+ TRIG10_OUT_TR_GROUP0_INPUT1 = 0x40000A00u, /* tr_group[0].input[1] */
+ TRIG10_OUT_TR_GROUP1_INPUT1 = 0x40000A00u, /* tr_group[1].input[1] */
+ TRIG10_OUT_TR_GROUP2_INPUT1 = 0x40000A00u, /* tr_group[2].input[1] */
+ TRIG10_OUT_TR_GROUP3_INPUT1 = 0x40000A00u, /* tr_group[3].input[1] */
+ TRIG10_OUT_TR_GROUP4_INPUT1 = 0x40000A00u, /* tr_group[4].input[1] */
+ TRIG10_OUT_TR_GROUP5_INPUT1 = 0x40000A00u, /* tr_group[5].input[1] */
+ TRIG10_OUT_TR_GROUP6_INPUT1 = 0x40000A00u, /* tr_group[6].input[1] */
+ TRIG10_OUT_TR_GROUP7_INPUT1 = 0x40000A00u, /* tr_group[7].input[1] */
+ TRIG10_OUT_TR_GROUP8_INPUT1 = 0x40000A00u, /* tr_group[8].input[1] */
+ TRIG10_OUT_UDB_TR_DW_ACK1 = 0x40000A01u, /* udb.tr_dw_ack[1] */
+ TRIG10_OUT_TR_GROUP0_INPUT2 = 0x40000A01u, /* tr_group[0].input[2] */
+ TRIG10_OUT_TR_GROUP1_INPUT2 = 0x40000A01u, /* tr_group[1].input[2] */
+ TRIG10_OUT_TR_GROUP2_INPUT2 = 0x40000A01u, /* tr_group[2].input[2] */
+ TRIG10_OUT_TR_GROUP3_INPUT2 = 0x40000A01u, /* tr_group[3].input[2] */
+ TRIG10_OUT_TR_GROUP4_INPUT2 = 0x40000A01u, /* tr_group[4].input[2] */
+ TRIG10_OUT_TR_GROUP5_INPUT2 = 0x40000A01u, /* tr_group[5].input[2] */
+ TRIG10_OUT_TR_GROUP6_INPUT2 = 0x40000A01u, /* tr_group[6].input[2] */
+ TRIG10_OUT_TR_GROUP7_INPUT2 = 0x40000A01u, /* tr_group[7].input[2] */
+ TRIG10_OUT_TR_GROUP8_INPUT2 = 0x40000A01u, /* tr_group[8].input[2] */
+ TRIG10_OUT_UDB_TR_DW_ACK2 = 0x40000A02u, /* udb.tr_dw_ack[2] */
+ TRIG10_OUT_TR_GROUP0_INPUT3 = 0x40000A02u, /* tr_group[0].input[3] */
+ TRIG10_OUT_TR_GROUP1_INPUT3 = 0x40000A02u, /* tr_group[1].input[3] */
+ TRIG10_OUT_TR_GROUP2_INPUT3 = 0x40000A02u, /* tr_group[2].input[3] */
+ TRIG10_OUT_TR_GROUP3_INPUT3 = 0x40000A02u, /* tr_group[3].input[3] */
+ TRIG10_OUT_TR_GROUP4_INPUT3 = 0x40000A02u, /* tr_group[4].input[3] */
+ TRIG10_OUT_TR_GROUP5_INPUT3 = 0x40000A02u, /* tr_group[5].input[3] */
+ TRIG10_OUT_TR_GROUP6_INPUT3 = 0x40000A02u, /* tr_group[6].input[3] */
+ TRIG10_OUT_TR_GROUP7_INPUT3 = 0x40000A02u, /* tr_group[7].input[3] */
+ TRIG10_OUT_TR_GROUP8_INPUT3 = 0x40000A02u, /* tr_group[8].input[3] */
+ TRIG10_OUT_UDB_TR_DW_ACK3 = 0x40000A03u, /* udb.tr_dw_ack[3] */
+ TRIG10_OUT_TR_GROUP0_INPUT4 = 0x40000A03u, /* tr_group[0].input[4] */
+ TRIG10_OUT_TR_GROUP1_INPUT4 = 0x40000A03u, /* tr_group[1].input[4] */
+ TRIG10_OUT_TR_GROUP2_INPUT4 = 0x40000A03u, /* tr_group[2].input[4] */
+ TRIG10_OUT_TR_GROUP3_INPUT4 = 0x40000A03u, /* tr_group[3].input[4] */
+ TRIG10_OUT_TR_GROUP4_INPUT4 = 0x40000A03u, /* tr_group[4].input[4] */
+ TRIG10_OUT_TR_GROUP5_INPUT4 = 0x40000A03u, /* tr_group[5].input[4] */
+ TRIG10_OUT_TR_GROUP6_INPUT4 = 0x40000A03u, /* tr_group[6].input[4] */
+ TRIG10_OUT_TR_GROUP7_INPUT4 = 0x40000A03u, /* tr_group[7].input[4] */
+ TRIG10_OUT_TR_GROUP8_INPUT4 = 0x40000A03u, /* tr_group[8].input[4] */
+ TRIG10_OUT_UDB_TR_DW_ACK4 = 0x40000A04u, /* udb.tr_dw_ack[4] */
+ TRIG10_OUT_TR_GROUP0_INPUT5 = 0x40000A04u, /* tr_group[0].input[5] */
+ TRIG10_OUT_TR_GROUP1_INPUT5 = 0x40000A04u, /* tr_group[1].input[5] */
+ TRIG10_OUT_TR_GROUP2_INPUT5 = 0x40000A04u, /* tr_group[2].input[5] */
+ TRIG10_OUT_TR_GROUP3_INPUT5 = 0x40000A04u, /* tr_group[3].input[5] */
+ TRIG10_OUT_TR_GROUP4_INPUT5 = 0x40000A04u, /* tr_group[4].input[5] */
+ TRIG10_OUT_TR_GROUP5_INPUT5 = 0x40000A04u, /* tr_group[5].input[5] */
+ TRIG10_OUT_TR_GROUP6_INPUT5 = 0x40000A04u, /* tr_group[6].input[5] */
+ TRIG10_OUT_TR_GROUP7_INPUT5 = 0x40000A04u, /* tr_group[7].input[5] */
+ TRIG10_OUT_TR_GROUP8_INPUT5 = 0x40000A04u, /* tr_group[8].input[5] */
+ TRIG10_OUT_UDB_TR_DW_ACK5 = 0x40000A05u, /* udb.tr_dw_ack[5] */
+ TRIG10_OUT_TR_GROUP0_INPUT6 = 0x40000A05u, /* tr_group[0].input[6] */
+ TRIG10_OUT_TR_GROUP1_INPUT6 = 0x40000A05u, /* tr_group[1].input[6] */
+ TRIG10_OUT_TR_GROUP2_INPUT6 = 0x40000A05u, /* tr_group[2].input[6] */
+ TRIG10_OUT_TR_GROUP3_INPUT6 = 0x40000A05u, /* tr_group[3].input[6] */
+ TRIG10_OUT_TR_GROUP4_INPUT6 = 0x40000A05u, /* tr_group[4].input[6] */
+ TRIG10_OUT_TR_GROUP5_INPUT6 = 0x40000A05u, /* tr_group[5].input[6] */
+ TRIG10_OUT_TR_GROUP6_INPUT6 = 0x40000A05u, /* tr_group[6].input[6] */
+ TRIG10_OUT_TR_GROUP7_INPUT6 = 0x40000A05u, /* tr_group[7].input[6] */
+ TRIG10_OUT_TR_GROUP8_INPUT6 = 0x40000A05u, /* tr_group[8].input[6] */
+ TRIG10_OUT_UDB_TR_DW_ACK6 = 0x40000A06u, /* udb.tr_dw_ack[6] */
+ TRIG10_OUT_TR_GROUP0_INPUT7 = 0x40000A06u, /* tr_group[0].input[7] */
+ TRIG10_OUT_TR_GROUP1_INPUT7 = 0x40000A06u, /* tr_group[1].input[7] */
+ TRIG10_OUT_TR_GROUP2_INPUT7 = 0x40000A06u, /* tr_group[2].input[7] */
+ TRIG10_OUT_TR_GROUP3_INPUT7 = 0x40000A06u, /* tr_group[3].input[7] */
+ TRIG10_OUT_TR_GROUP4_INPUT7 = 0x40000A06u, /* tr_group[4].input[7] */
+ TRIG10_OUT_TR_GROUP5_INPUT7 = 0x40000A06u, /* tr_group[5].input[7] */
+ TRIG10_OUT_TR_GROUP6_INPUT7 = 0x40000A06u, /* tr_group[6].input[7] */
+ TRIG10_OUT_TR_GROUP7_INPUT7 = 0x40000A06u, /* tr_group[7].input[7] */
+ TRIG10_OUT_TR_GROUP8_INPUT7 = 0x40000A06u, /* tr_group[8].input[7] */
+ TRIG10_OUT_UDB_TR_DW_ACK7 = 0x40000A07u, /* udb.tr_dw_ack[7] */
+ TRIG10_OUT_TR_GROUP0_INPUT8 = 0x40000A07u, /* tr_group[0].input[8] */
+ TRIG10_OUT_TR_GROUP1_INPUT8 = 0x40000A07u, /* tr_group[1].input[8] */
+ TRIG10_OUT_TR_GROUP2_INPUT8 = 0x40000A07u, /* tr_group[2].input[8] */
+ TRIG10_OUT_TR_GROUP3_INPUT8 = 0x40000A07u, /* tr_group[3].input[8] */
+ TRIG10_OUT_TR_GROUP4_INPUT8 = 0x40000A07u, /* tr_group[4].input[8] */
+ TRIG10_OUT_TR_GROUP5_INPUT8 = 0x40000A07u, /* tr_group[5].input[8] */
+ TRIG10_OUT_TR_GROUP6_INPUT8 = 0x40000A07u, /* tr_group[6].input[8] */
+ TRIG10_OUT_TR_GROUP7_INPUT8 = 0x40000A07u, /* tr_group[7].input[8] */
+ TRIG10_OUT_TR_GROUP8_INPUT8 = 0x40000A07u /* tr_group[8].input[8] */
+} en_trig_output_grp10_t;
+
+/* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
+typedef enum
+{
+ TRIG11_OUT_TR_GROUP0_INPUT9 = 0x40000B00u, /* tr_group[0].input[9] */
+ TRIG11_OUT_TR_GROUP1_INPUT9 = 0x40000B00u, /* tr_group[1].input[9] */
+ TRIG11_OUT_TR_GROUP2_INPUT9 = 0x40000B00u, /* tr_group[2].input[9] */
+ TRIG11_OUT_TR_GROUP3_INPUT9 = 0x40000B00u, /* tr_group[3].input[9] */
+ TRIG11_OUT_TR_GROUP4_INPUT9 = 0x40000B00u, /* tr_group[4].input[9] */
+ TRIG11_OUT_TR_GROUP5_INPUT9 = 0x40000B00u, /* tr_group[5].input[9] */
+ TRIG11_OUT_TR_GROUP6_INPUT9 = 0x40000B00u, /* tr_group[6].input[9] */
+ TRIG11_OUT_TR_GROUP7_INPUT9 = 0x40000B00u, /* tr_group[7].input[9] */
+ TRIG11_OUT_TR_GROUP8_INPUT9 = 0x40000B00u, /* tr_group[8].input[9] */
+ TRIG11_OUT_TR_GROUP0_INPUT10 = 0x40000B01u, /* tr_group[0].input[10] */
+ TRIG11_OUT_TR_GROUP1_INPUT10 = 0x40000B01u, /* tr_group[1].input[10] */
+ TRIG11_OUT_TR_GROUP2_INPUT10 = 0x40000B01u, /* tr_group[2].input[10] */
+ TRIG11_OUT_TR_GROUP3_INPUT10 = 0x40000B01u, /* tr_group[3].input[10] */
+ TRIG11_OUT_TR_GROUP4_INPUT10 = 0x40000B01u, /* tr_group[4].input[10] */
+ TRIG11_OUT_TR_GROUP5_INPUT10 = 0x40000B01u, /* tr_group[5].input[10] */
+ TRIG11_OUT_TR_GROUP6_INPUT10 = 0x40000B01u, /* tr_group[6].input[10] */
+ TRIG11_OUT_TR_GROUP7_INPUT10 = 0x40000B01u, /* tr_group[7].input[10] */
+ TRIG11_OUT_TR_GROUP8_INPUT10 = 0x40000B01u, /* tr_group[8].input[10] */
+ TRIG11_OUT_TR_GROUP0_INPUT11 = 0x40000B02u, /* tr_group[0].input[11] */
+ TRIG11_OUT_TR_GROUP1_INPUT11 = 0x40000B02u, /* tr_group[1].input[11] */
+ TRIG11_OUT_TR_GROUP2_INPUT11 = 0x40000B02u, /* tr_group[2].input[11] */
+ TRIG11_OUT_TR_GROUP3_INPUT11 = 0x40000B02u, /* tr_group[3].input[11] */
+ TRIG11_OUT_TR_GROUP4_INPUT11 = 0x40000B02u, /* tr_group[4].input[11] */
+ TRIG11_OUT_TR_GROUP5_INPUT11 = 0x40000B02u, /* tr_group[5].input[11] */
+ TRIG11_OUT_TR_GROUP6_INPUT11 = 0x40000B02u, /* tr_group[6].input[11] */
+ TRIG11_OUT_TR_GROUP7_INPUT11 = 0x40000B02u, /* tr_group[7].input[11] */
+ TRIG11_OUT_TR_GROUP8_INPUT11 = 0x40000B02u, /* tr_group[8].input[11] */
+ TRIG11_OUT_TR_GROUP0_INPUT12 = 0x40000B03u, /* tr_group[0].input[12] */
+ TRIG11_OUT_TR_GROUP1_INPUT12 = 0x40000B03u, /* tr_group[1].input[12] */
+ TRIG11_OUT_TR_GROUP2_INPUT12 = 0x40000B03u, /* tr_group[2].input[12] */
+ TRIG11_OUT_TR_GROUP3_INPUT12 = 0x40000B03u, /* tr_group[3].input[12] */
+ TRIG11_OUT_TR_GROUP4_INPUT12 = 0x40000B03u, /* tr_group[4].input[12] */
+ TRIG11_OUT_TR_GROUP5_INPUT12 = 0x40000B03u, /* tr_group[5].input[12] */
+ TRIG11_OUT_TR_GROUP6_INPUT12 = 0x40000B03u, /* tr_group[6].input[12] */
+ TRIG11_OUT_TR_GROUP7_INPUT12 = 0x40000B03u, /* tr_group[7].input[12] */
+ TRIG11_OUT_TR_GROUP8_INPUT12 = 0x40000B03u, /* tr_group[8].input[12] */
+ TRIG11_OUT_TR_GROUP0_INPUT13 = 0x40000B04u, /* tr_group[0].input[13] */
+ TRIG11_OUT_TR_GROUP1_INPUT13 = 0x40000B04u, /* tr_group[1].input[13] */
+ TRIG11_OUT_TR_GROUP2_INPUT13 = 0x40000B04u, /* tr_group[2].input[13] */
+ TRIG11_OUT_TR_GROUP3_INPUT13 = 0x40000B04u, /* tr_group[3].input[13] */
+ TRIG11_OUT_TR_GROUP4_INPUT13 = 0x40000B04u, /* tr_group[4].input[13] */
+ TRIG11_OUT_TR_GROUP5_INPUT13 = 0x40000B04u, /* tr_group[5].input[13] */
+ TRIG11_OUT_TR_GROUP6_INPUT13 = 0x40000B04u, /* tr_group[6].input[13] */
+ TRIG11_OUT_TR_GROUP7_INPUT13 = 0x40000B04u, /* tr_group[7].input[13] */
+ TRIG11_OUT_TR_GROUP8_INPUT13 = 0x40000B04u, /* tr_group[8].input[13] */
+ TRIG11_OUT_TR_GROUP0_INPUT14 = 0x40000B05u, /* tr_group[0].input[14] */
+ TRIG11_OUT_TR_GROUP1_INPUT14 = 0x40000B05u, /* tr_group[1].input[14] */
+ TRIG11_OUT_TR_GROUP2_INPUT14 = 0x40000B05u, /* tr_group[2].input[14] */
+ TRIG11_OUT_TR_GROUP3_INPUT14 = 0x40000B05u, /* tr_group[3].input[14] */
+ TRIG11_OUT_TR_GROUP4_INPUT14 = 0x40000B05u, /* tr_group[4].input[14] */
+ TRIG11_OUT_TR_GROUP5_INPUT14 = 0x40000B05u, /* tr_group[5].input[14] */
+ TRIG11_OUT_TR_GROUP6_INPUT14 = 0x40000B05u, /* tr_group[6].input[14] */
+ TRIG11_OUT_TR_GROUP7_INPUT14 = 0x40000B05u, /* tr_group[7].input[14] */
+ TRIG11_OUT_TR_GROUP8_INPUT14 = 0x40000B05u, /* tr_group[8].input[14] */
+ TRIG11_OUT_TR_GROUP0_INPUT15 = 0x40000B06u, /* tr_group[0].input[15] */
+ TRIG11_OUT_TR_GROUP1_INPUT15 = 0x40000B06u, /* tr_group[1].input[15] */
+ TRIG11_OUT_TR_GROUP2_INPUT15 = 0x40000B06u, /* tr_group[2].input[15] */
+ TRIG11_OUT_TR_GROUP3_INPUT15 = 0x40000B06u, /* tr_group[3].input[15] */
+ TRIG11_OUT_TR_GROUP4_INPUT15 = 0x40000B06u, /* tr_group[4].input[15] */
+ TRIG11_OUT_TR_GROUP5_INPUT15 = 0x40000B06u, /* tr_group[5].input[15] */
+ TRIG11_OUT_TR_GROUP6_INPUT15 = 0x40000B06u, /* tr_group[6].input[15] */
+ TRIG11_OUT_TR_GROUP7_INPUT15 = 0x40000B06u, /* tr_group[7].input[15] */
+ TRIG11_OUT_TR_GROUP8_INPUT15 = 0x40000B06u, /* tr_group[8].input[15] */
+ TRIG11_OUT_TR_GROUP0_INPUT16 = 0x40000B07u, /* tr_group[0].input[16] */
+ TRIG11_OUT_TR_GROUP1_INPUT16 = 0x40000B07u, /* tr_group[1].input[16] */
+ TRIG11_OUT_TR_GROUP2_INPUT16 = 0x40000B07u, /* tr_group[2].input[16] */
+ TRIG11_OUT_TR_GROUP3_INPUT16 = 0x40000B07u, /* tr_group[3].input[16] */
+ TRIG11_OUT_TR_GROUP4_INPUT16 = 0x40000B07u, /* tr_group[4].input[16] */
+ TRIG11_OUT_TR_GROUP5_INPUT16 = 0x40000B07u, /* tr_group[5].input[16] */
+ TRIG11_OUT_TR_GROUP6_INPUT16 = 0x40000B07u, /* tr_group[6].input[16] */
+ TRIG11_OUT_TR_GROUP7_INPUT16 = 0x40000B07u, /* tr_group[7].input[16] */
+ TRIG11_OUT_TR_GROUP8_INPUT16 = 0x40000B07u, /* tr_group[8].input[16] */
+ TRIG11_OUT_TR_GROUP0_INPUT17 = 0x40000B08u, /* tr_group[0].input[17] */
+ TRIG11_OUT_TR_GROUP1_INPUT17 = 0x40000B08u, /* tr_group[1].input[17] */
+ TRIG11_OUT_TR_GROUP2_INPUT17 = 0x40000B08u, /* tr_group[2].input[17] */
+ TRIG11_OUT_TR_GROUP3_INPUT17 = 0x40000B08u, /* tr_group[3].input[17] */
+ TRIG11_OUT_TR_GROUP4_INPUT17 = 0x40000B08u, /* tr_group[4].input[17] */
+ TRIG11_OUT_TR_GROUP5_INPUT17 = 0x40000B08u, /* tr_group[5].input[17] */
+ TRIG11_OUT_TR_GROUP6_INPUT17 = 0x40000B08u, /* tr_group[6].input[17] */
+ TRIG11_OUT_TR_GROUP7_INPUT17 = 0x40000B08u, /* tr_group[7].input[17] */
+ TRIG11_OUT_TR_GROUP8_INPUT17 = 0x40000B08u, /* tr_group[8].input[17] */
+ TRIG11_OUT_TR_GROUP0_INPUT18 = 0x40000B09u, /* tr_group[0].input[18] */
+ TRIG11_OUT_TR_GROUP1_INPUT18 = 0x40000B09u, /* tr_group[1].input[18] */
+ TRIG11_OUT_TR_GROUP2_INPUT18 = 0x40000B09u, /* tr_group[2].input[18] */
+ TRIG11_OUT_TR_GROUP3_INPUT18 = 0x40000B09u, /* tr_group[3].input[18] */
+ TRIG11_OUT_TR_GROUP4_INPUT18 = 0x40000B09u, /* tr_group[4].input[18] */
+ TRIG11_OUT_TR_GROUP5_INPUT18 = 0x40000B09u, /* tr_group[5].input[18] */
+ TRIG11_OUT_TR_GROUP6_INPUT18 = 0x40000B09u, /* tr_group[6].input[18] */
+ TRIG11_OUT_TR_GROUP7_INPUT18 = 0x40000B09u, /* tr_group[7].input[18] */
+ TRIG11_OUT_TR_GROUP8_INPUT18 = 0x40000B09u, /* tr_group[8].input[18] */
+ TRIG11_OUT_TR_GROUP0_INPUT19 = 0x40000B0Au, /* tr_group[0].input[19] */
+ TRIG11_OUT_TR_GROUP1_INPUT19 = 0x40000B0Au, /* tr_group[1].input[19] */
+ TRIG11_OUT_TR_GROUP2_INPUT19 = 0x40000B0Au, /* tr_group[2].input[19] */
+ TRIG11_OUT_TR_GROUP3_INPUT19 = 0x40000B0Au, /* tr_group[3].input[19] */
+ TRIG11_OUT_TR_GROUP4_INPUT19 = 0x40000B0Au, /* tr_group[4].input[19] */
+ TRIG11_OUT_TR_GROUP5_INPUT19 = 0x40000B0Au, /* tr_group[5].input[19] */
+ TRIG11_OUT_TR_GROUP6_INPUT19 = 0x40000B0Au, /* tr_group[6].input[19] */
+ TRIG11_OUT_TR_GROUP7_INPUT19 = 0x40000B0Au, /* tr_group[7].input[19] */
+ TRIG11_OUT_TR_GROUP8_INPUT19 = 0x40000B0Au, /* tr_group[8].input[19] */
+ TRIG11_OUT_TR_GROUP0_INPUT20 = 0x40000B0Bu, /* tr_group[0].input[20] */
+ TRIG11_OUT_TR_GROUP1_INPUT20 = 0x40000B0Bu, /* tr_group[1].input[20] */
+ TRIG11_OUT_TR_GROUP2_INPUT20 = 0x40000B0Bu, /* tr_group[2].input[20] */
+ TRIG11_OUT_TR_GROUP3_INPUT20 = 0x40000B0Bu, /* tr_group[3].input[20] */
+ TRIG11_OUT_TR_GROUP4_INPUT20 = 0x40000B0Bu, /* tr_group[4].input[20] */
+ TRIG11_OUT_TR_GROUP5_INPUT20 = 0x40000B0Bu, /* tr_group[5].input[20] */
+ TRIG11_OUT_TR_GROUP6_INPUT20 = 0x40000B0Bu, /* tr_group[6].input[20] */
+ TRIG11_OUT_TR_GROUP7_INPUT20 = 0x40000B0Bu, /* tr_group[7].input[20] */
+ TRIG11_OUT_TR_GROUP8_INPUT20 = 0x40000B0Bu, /* tr_group[8].input[20] */
+ TRIG11_OUT_TR_GROUP0_INPUT21 = 0x40000B0Cu, /* tr_group[0].input[21] */
+ TRIG11_OUT_TR_GROUP1_INPUT21 = 0x40000B0Cu, /* tr_group[1].input[21] */
+ TRIG11_OUT_TR_GROUP2_INPUT21 = 0x40000B0Cu, /* tr_group[2].input[21] */
+ TRIG11_OUT_TR_GROUP3_INPUT21 = 0x40000B0Cu, /* tr_group[3].input[21] */
+ TRIG11_OUT_TR_GROUP4_INPUT21 = 0x40000B0Cu, /* tr_group[4].input[21] */
+ TRIG11_OUT_TR_GROUP5_INPUT21 = 0x40000B0Cu, /* tr_group[5].input[21] */
+ TRIG11_OUT_TR_GROUP6_INPUT21 = 0x40000B0Cu, /* tr_group[6].input[21] */
+ TRIG11_OUT_TR_GROUP7_INPUT21 = 0x40000B0Cu, /* tr_group[7].input[21] */
+ TRIG11_OUT_TR_GROUP8_INPUT21 = 0x40000B0Cu, /* tr_group[8].input[21] */
+ TRIG11_OUT_TR_GROUP0_INPUT22 = 0x40000B0Du, /* tr_group[0].input[22] */
+ TRIG11_OUT_TR_GROUP1_INPUT22 = 0x40000B0Du, /* tr_group[1].input[22] */
+ TRIG11_OUT_TR_GROUP2_INPUT22 = 0x40000B0Du, /* tr_group[2].input[22] */
+ TRIG11_OUT_TR_GROUP3_INPUT22 = 0x40000B0Du, /* tr_group[3].input[22] */
+ TRIG11_OUT_TR_GROUP4_INPUT22 = 0x40000B0Du, /* tr_group[4].input[22] */
+ TRIG11_OUT_TR_GROUP5_INPUT22 = 0x40000B0Du, /* tr_group[5].input[22] */
+ TRIG11_OUT_TR_GROUP6_INPUT22 = 0x40000B0Du, /* tr_group[6].input[22] */
+ TRIG11_OUT_TR_GROUP7_INPUT22 = 0x40000B0Du, /* tr_group[7].input[22] */
+ TRIG11_OUT_TR_GROUP8_INPUT22 = 0x40000B0Du, /* tr_group[8].input[22] */
+ TRIG11_OUT_TR_GROUP0_INPUT23 = 0x40000B0Eu, /* tr_group[0].input[23] */
+ TRIG11_OUT_TR_GROUP1_INPUT23 = 0x40000B0Eu, /* tr_group[1].input[23] */
+ TRIG11_OUT_TR_GROUP2_INPUT23 = 0x40000B0Eu, /* tr_group[2].input[23] */
+ TRIG11_OUT_TR_GROUP3_INPUT23 = 0x40000B0Eu, /* tr_group[3].input[23] */
+ TRIG11_OUT_TR_GROUP4_INPUT23 = 0x40000B0Eu, /* tr_group[4].input[23] */
+ TRIG11_OUT_TR_GROUP5_INPUT23 = 0x40000B0Eu, /* tr_group[5].input[23] */
+ TRIG11_OUT_TR_GROUP6_INPUT23 = 0x40000B0Eu, /* tr_group[6].input[23] */
+ TRIG11_OUT_TR_GROUP7_INPUT23 = 0x40000B0Eu, /* tr_group[7].input[23] */
+ TRIG11_OUT_TR_GROUP8_INPUT23 = 0x40000B0Eu, /* tr_group[8].input[23] */
+ TRIG11_OUT_TR_GROUP0_INPUT24 = 0x40000B0Fu, /* tr_group[0].input[24] */
+ TRIG11_OUT_TR_GROUP1_INPUT24 = 0x40000B0Fu, /* tr_group[1].input[24] */
+ TRIG11_OUT_TR_GROUP2_INPUT24 = 0x40000B0Fu, /* tr_group[2].input[24] */
+ TRIG11_OUT_TR_GROUP3_INPUT24 = 0x40000B0Fu, /* tr_group[3].input[24] */
+ TRIG11_OUT_TR_GROUP4_INPUT24 = 0x40000B0Fu, /* tr_group[4].input[24] */
+ TRIG11_OUT_TR_GROUP5_INPUT24 = 0x40000B0Fu, /* tr_group[5].input[24] */
+ TRIG11_OUT_TR_GROUP6_INPUT24 = 0x40000B0Fu, /* tr_group[6].input[24] */
+ TRIG11_OUT_TR_GROUP7_INPUT24 = 0x40000B0Fu, /* tr_group[7].input[24] */
+ TRIG11_OUT_TR_GROUP8_INPUT24 = 0x40000B0Fu /* tr_group[8].input[24] */
+} en_trig_output_grp11_t;
+
+/* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
+typedef enum
+{
+ TRIG12_OUT_TR_GROUP2_INPUT25 = 0x40000C00u, /* tr_group[2].input[25] */
+ TRIG12_OUT_TR_GROUP3_INPUT25 = 0x40000C00u, /* tr_group[3].input[25] */
+ TRIG12_OUT_TR_GROUP4_INPUT25 = 0x40000C00u, /* tr_group[4].input[25] */
+ TRIG12_OUT_TR_GROUP5_INPUT25 = 0x40000C00u, /* tr_group[5].input[25] */
+ TRIG12_OUT_TR_GROUP6_INPUT25 = 0x40000C00u, /* tr_group[6].input[25] */
+ TRIG12_OUT_TR_GROUP7_INPUT25 = 0x40000C00u, /* tr_group[7].input[25] */
+ TRIG12_OUT_TR_GROUP8_INPUT25 = 0x40000C00u, /* tr_group[8].input[25] */
+ TRIG12_OUT_TR_GROUP2_INPUT26 = 0x40000C01u, /* tr_group[2].input[26] */
+ TRIG12_OUT_TR_GROUP3_INPUT26 = 0x40000C01u, /* tr_group[3].input[26] */
+ TRIG12_OUT_TR_GROUP4_INPUT26 = 0x40000C01u, /* tr_group[4].input[26] */
+ TRIG12_OUT_TR_GROUP5_INPUT26 = 0x40000C01u, /* tr_group[5].input[26] */
+ TRIG12_OUT_TR_GROUP6_INPUT26 = 0x40000C01u, /* tr_group[6].input[26] */
+ TRIG12_OUT_TR_GROUP7_INPUT26 = 0x40000C01u, /* tr_group[7].input[26] */
+ TRIG12_OUT_TR_GROUP8_INPUT26 = 0x40000C01u, /* tr_group[8].input[26] */
+ TRIG12_OUT_TR_GROUP2_INPUT27 = 0x40000C02u, /* tr_group[2].input[27] */
+ TRIG12_OUT_TR_GROUP3_INPUT27 = 0x40000C02u, /* tr_group[3].input[27] */
+ TRIG12_OUT_TR_GROUP4_INPUT27 = 0x40000C02u, /* tr_group[4].input[27] */
+ TRIG12_OUT_TR_GROUP5_INPUT27 = 0x40000C02u, /* tr_group[5].input[27] */
+ TRIG12_OUT_TR_GROUP6_INPUT27 = 0x40000C02u, /* tr_group[6].input[27] */
+ TRIG12_OUT_TR_GROUP7_INPUT27 = 0x40000C02u, /* tr_group[7].input[27] */
+ TRIG12_OUT_TR_GROUP8_INPUT27 = 0x40000C02u, /* tr_group[8].input[27] */
+ TRIG12_OUT_TR_GROUP2_INPUT28 = 0x40000C03u, /* tr_group[2].input[28] */
+ TRIG12_OUT_TR_GROUP3_INPUT28 = 0x40000C03u, /* tr_group[3].input[28] */
+ TRIG12_OUT_TR_GROUP4_INPUT28 = 0x40000C03u, /* tr_group[4].input[28] */
+ TRIG12_OUT_TR_GROUP5_INPUT28 = 0x40000C03u, /* tr_group[5].input[28] */
+ TRIG12_OUT_TR_GROUP6_INPUT28 = 0x40000C03u, /* tr_group[6].input[28] */
+ TRIG12_OUT_TR_GROUP7_INPUT28 = 0x40000C03u, /* tr_group[7].input[28] */
+ TRIG12_OUT_TR_GROUP8_INPUT28 = 0x40000C03u, /* tr_group[8].input[28] */
+ TRIG12_OUT_TR_GROUP2_INPUT29 = 0x40000C04u, /* tr_group[2].input[29] */
+ TRIG12_OUT_TR_GROUP3_INPUT29 = 0x40000C04u, /* tr_group[3].input[29] */
+ TRIG12_OUT_TR_GROUP4_INPUT29 = 0x40000C04u, /* tr_group[4].input[29] */
+ TRIG12_OUT_TR_GROUP5_INPUT29 = 0x40000C04u, /* tr_group[5].input[29] */
+ TRIG12_OUT_TR_GROUP6_INPUT29 = 0x40000C04u, /* tr_group[6].input[29] */
+ TRIG12_OUT_TR_GROUP7_INPUT29 = 0x40000C04u, /* tr_group[7].input[29] */
+ TRIG12_OUT_TR_GROUP8_INPUT29 = 0x40000C04u, /* tr_group[8].input[29] */
+ TRIG12_OUT_TR_GROUP2_INPUT30 = 0x40000C05u, /* tr_group[2].input[30] */
+ TRIG12_OUT_TR_GROUP3_INPUT30 = 0x40000C05u, /* tr_group[3].input[30] */
+ TRIG12_OUT_TR_GROUP4_INPUT30 = 0x40000C05u, /* tr_group[4].input[30] */
+ TRIG12_OUT_TR_GROUP5_INPUT30 = 0x40000C05u, /* tr_group[5].input[30] */
+ TRIG12_OUT_TR_GROUP6_INPUT30 = 0x40000C05u, /* tr_group[6].input[30] */
+ TRIG12_OUT_TR_GROUP7_INPUT30 = 0x40000C05u, /* tr_group[7].input[30] */
+ TRIG12_OUT_TR_GROUP8_INPUT30 = 0x40000C05u, /* tr_group[8].input[30] */
+ TRIG12_OUT_TR_GROUP2_INPUT31 = 0x40000C06u, /* tr_group[2].input[31] */
+ TRIG12_OUT_TR_GROUP3_INPUT31 = 0x40000C06u, /* tr_group[3].input[31] */
+ TRIG12_OUT_TR_GROUP4_INPUT31 = 0x40000C06u, /* tr_group[4].input[31] */
+ TRIG12_OUT_TR_GROUP5_INPUT31 = 0x40000C06u, /* tr_group[5].input[31] */
+ TRIG12_OUT_TR_GROUP6_INPUT31 = 0x40000C06u, /* tr_group[6].input[31] */
+ TRIG12_OUT_TR_GROUP7_INPUT31 = 0x40000C06u, /* tr_group[7].input[31] */
+ TRIG12_OUT_TR_GROUP8_INPUT31 = 0x40000C06u, /* tr_group[8].input[31] */
+ TRIG12_OUT_TR_GROUP2_INPUT32 = 0x40000C07u, /* tr_group[2].input[32] */
+ TRIG12_OUT_TR_GROUP3_INPUT32 = 0x40000C07u, /* tr_group[3].input[32] */
+ TRIG12_OUT_TR_GROUP4_INPUT32 = 0x40000C07u, /* tr_group[4].input[32] */
+ TRIG12_OUT_TR_GROUP5_INPUT32 = 0x40000C07u, /* tr_group[5].input[32] */
+ TRIG12_OUT_TR_GROUP6_INPUT32 = 0x40000C07u, /* tr_group[6].input[32] */
+ TRIG12_OUT_TR_GROUP7_INPUT32 = 0x40000C07u, /* tr_group[7].input[32] */
+ TRIG12_OUT_TR_GROUP8_INPUT32 = 0x40000C07u, /* tr_group[8].input[32] */
+ TRIG12_OUT_TR_GROUP0_INPUT25 = 0x40000C08u, /* tr_group[0].input[25] */
+ TRIG12_OUT_TR_GROUP1_INPUT25 = 0x40000C08u, /* tr_group[1].input[25] */
+ TRIG12_OUT_TR_GROUP0_INPUT26 = 0x40000C09u, /* tr_group[0].input[26] */
+ TRIG12_OUT_TR_GROUP1_INPUT26 = 0x40000C09u /* tr_group[1].input[26] */
+} en_trig_output_grp12_t;
+
+/* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
+typedef enum
+{
+ TRIG13_OUT_TR_GROUP0_INPUT27 = 0x40000D00u, /* tr_group[0].input[27] */
+ TRIG13_OUT_TR_GROUP1_INPUT27 = 0x40000D00u, /* tr_group[1].input[27] */
+ TRIG13_OUT_TR_GROUP0_INPUT28 = 0x40000D01u, /* tr_group[0].input[28] */
+ TRIG13_OUT_TR_GROUP1_INPUT28 = 0x40000D01u, /* tr_group[1].input[28] */
+ TRIG13_OUT_TR_GROUP0_INPUT29 = 0x40000D02u, /* tr_group[0].input[29] */
+ TRIG13_OUT_TR_GROUP1_INPUT29 = 0x40000D02u, /* tr_group[1].input[29] */
+ TRIG13_OUT_TR_GROUP0_INPUT30 = 0x40000D03u, /* tr_group[0].input[30] */
+ TRIG13_OUT_TR_GROUP1_INPUT30 = 0x40000D03u, /* tr_group[1].input[30] */
+ TRIG13_OUT_TR_GROUP0_INPUT31 = 0x40000D04u, /* tr_group[0].input[31] */
+ TRIG13_OUT_TR_GROUP1_INPUT31 = 0x40000D04u, /* tr_group[1].input[31] */
+ TRIG13_OUT_TR_GROUP0_INPUT32 = 0x40000D05u, /* tr_group[0].input[32] */
+ TRIG13_OUT_TR_GROUP1_INPUT32 = 0x40000D05u, /* tr_group[1].input[32] */
+ TRIG13_OUT_TR_GROUP0_INPUT33 = 0x40000D06u, /* tr_group[0].input[33] */
+ TRIG13_OUT_TR_GROUP1_INPUT33 = 0x40000D06u, /* tr_group[1].input[33] */
+ TRIG13_OUT_TR_GROUP0_INPUT34 = 0x40000D07u, /* tr_group[0].input[34] */
+ TRIG13_OUT_TR_GROUP1_INPUT34 = 0x40000D07u, /* tr_group[1].input[34] */
+ TRIG13_OUT_TR_GROUP0_INPUT35 = 0x40000D08u, /* tr_group[0].input[35] */
+ TRIG13_OUT_TR_GROUP1_INPUT35 = 0x40000D08u, /* tr_group[1].input[35] */
+ TRIG13_OUT_TR_GROUP0_INPUT36 = 0x40000D09u, /* tr_group[0].input[36] */
+ TRIG13_OUT_TR_GROUP1_INPUT36 = 0x40000D09u, /* tr_group[1].input[36] */
+ TRIG13_OUT_TR_GROUP0_INPUT37 = 0x40000D0Au, /* tr_group[0].input[37] */
+ TRIG13_OUT_TR_GROUP1_INPUT37 = 0x40000D0Au, /* tr_group[1].input[37] */
+ TRIG13_OUT_TR_GROUP0_INPUT38 = 0x40000D0Bu, /* tr_group[0].input[38] */
+ TRIG13_OUT_TR_GROUP1_INPUT38 = 0x40000D0Bu, /* tr_group[1].input[38] */
+ TRIG13_OUT_TR_GROUP0_INPUT39 = 0x40000D0Cu, /* tr_group[0].input[39] */
+ TRIG13_OUT_TR_GROUP1_INPUT39 = 0x40000D0Cu, /* tr_group[1].input[39] */
+ TRIG13_OUT_TR_GROUP0_INPUT40 = 0x40000D0Du, /* tr_group[0].input[40] */
+ TRIG13_OUT_TR_GROUP1_INPUT40 = 0x40000D0Du, /* tr_group[1].input[40] */
+ TRIG13_OUT_TR_GROUP0_INPUT41 = 0x40000D0Eu, /* tr_group[0].input[41] */
+ TRIG13_OUT_TR_GROUP1_INPUT41 = 0x40000D0Eu, /* tr_group[1].input[41] */
+ TRIG13_OUT_TR_GROUP0_INPUT42 = 0x40000D0Fu, /* tr_group[0].input[42] */
+ TRIG13_OUT_TR_GROUP1_INPUT42 = 0x40000D0Fu, /* tr_group[1].input[42] */
+ TRIG13_OUT_TR_GROUP2_INPUT33 = 0x40000D10u, /* tr_group[2].input[33] */
+ TRIG13_OUT_TR_GROUP3_INPUT33 = 0x40000D10u, /* tr_group[3].input[33] */
+ TRIG13_OUT_TR_GROUP4_INPUT33 = 0x40000D10u, /* tr_group[4].input[33] */
+ TRIG13_OUT_TR_GROUP5_INPUT33 = 0x40000D10u, /* tr_group[5].input[33] */
+ TRIG13_OUT_TR_GROUP6_INPUT33 = 0x40000D10u, /* tr_group[6].input[33] */
+ TRIG13_OUT_TR_GROUP7_INPUT33 = 0x40000D10u, /* tr_group[7].input[33] */
+ TRIG13_OUT_TR_GROUP8_INPUT33 = 0x40000D10u, /* tr_group[8].input[33] */
+ TRIG13_OUT_TR_GROUP2_INPUT34 = 0x40000D11u, /* tr_group[2].input[34] */
+ TRIG13_OUT_TR_GROUP3_INPUT34 = 0x40000D11u, /* tr_group[3].input[34] */
+ TRIG13_OUT_TR_GROUP4_INPUT34 = 0x40000D11u, /* tr_group[4].input[34] */
+ TRIG13_OUT_TR_GROUP5_INPUT34 = 0x40000D11u, /* tr_group[5].input[34] */
+ TRIG13_OUT_TR_GROUP6_INPUT34 = 0x40000D11u, /* tr_group[6].input[34] */
+ TRIG13_OUT_TR_GROUP7_INPUT34 = 0x40000D11u, /* tr_group[7].input[34] */
+ TRIG13_OUT_TR_GROUP8_INPUT34 = 0x40000D11u /* tr_group[8].input[34] */
+} en_trig_output_grp13_t;
+
+/* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
+typedef enum
+{
+ TRIG14_OUT_TR_GROUP0_INPUT43 = 0x40000E00u, /* tr_group[0].input[43] */
+ TRIG14_OUT_TR_GROUP1_INPUT43 = 0x40000E00u, /* tr_group[1].input[43] */
+ TRIG14_OUT_TR_GROUP0_INPUT44 = 0x40000E01u, /* tr_group[0].input[44] */
+ TRIG14_OUT_TR_GROUP1_INPUT44 = 0x40000E01u, /* tr_group[1].input[44] */
+ TRIG14_OUT_TR_GROUP0_INPUT45 = 0x40000E02u, /* tr_group[0].input[45] */
+ TRIG14_OUT_TR_GROUP1_INPUT45 = 0x40000E02u, /* tr_group[1].input[45] */
+ TRIG14_OUT_TR_GROUP0_INPUT46 = 0x40000E03u, /* tr_group[0].input[46] */
+ TRIG14_OUT_TR_GROUP1_INPUT46 = 0x40000E03u, /* tr_group[1].input[46] */
+ TRIG14_OUT_TR_GROUP0_INPUT47 = 0x40000E04u, /* tr_group[0].input[47] */
+ TRIG14_OUT_TR_GROUP1_INPUT47 = 0x40000E04u, /* tr_group[1].input[47] */
+ TRIG14_OUT_TR_GROUP0_INPUT48 = 0x40000E05u, /* tr_group[0].input[48] */
+ TRIG14_OUT_TR_GROUP1_INPUT48 = 0x40000E05u, /* tr_group[1].input[48] */
+ TRIG14_OUT_TR_GROUP0_INPUT49 = 0x40000E06u, /* tr_group[0].input[49] */
+ TRIG14_OUT_TR_GROUP1_INPUT49 = 0x40000E06u, /* tr_group[1].input[49] */
+ TRIG14_OUT_TR_GROUP0_INPUT50 = 0x40000E07u, /* tr_group[0].input[50] */
+ TRIG14_OUT_TR_GROUP1_INPUT50 = 0x40000E07u, /* tr_group[1].input[50] */
+ TRIG14_OUT_TR_GROUP2_INPUT35 = 0x40000E08u, /* tr_group[2].input[35] */
+ TRIG14_OUT_TR_GROUP3_INPUT35 = 0x40000E08u, /* tr_group[3].input[35] */
+ TRIG14_OUT_TR_GROUP4_INPUT35 = 0x40000E08u, /* tr_group[4].input[35] */
+ TRIG14_OUT_TR_GROUP5_INPUT35 = 0x40000E08u, /* tr_group[5].input[35] */
+ TRIG14_OUT_TR_GROUP6_INPUT35 = 0x40000E08u, /* tr_group[6].input[35] */
+ TRIG14_OUT_TR_GROUP7_INPUT35 = 0x40000E08u, /* tr_group[7].input[35] */
+ TRIG14_OUT_TR_GROUP8_INPUT35 = 0x40000E08u, /* tr_group[8].input[35] */
+ TRIG14_OUT_TR_GROUP2_INPUT36 = 0x40000E09u, /* tr_group[2].input[36] */
+ TRIG14_OUT_TR_GROUP3_INPUT36 = 0x40000E09u, /* tr_group[3].input[36] */
+ TRIG14_OUT_TR_GROUP4_INPUT36 = 0x40000E09u, /* tr_group[4].input[36] */
+ TRIG14_OUT_TR_GROUP5_INPUT36 = 0x40000E09u, /* tr_group[5].input[36] */
+ TRIG14_OUT_TR_GROUP6_INPUT36 = 0x40000E09u, /* tr_group[6].input[36] */
+ TRIG14_OUT_TR_GROUP7_INPUT36 = 0x40000E09u, /* tr_group[7].input[36] */
+ TRIG14_OUT_TR_GROUP8_INPUT36 = 0x40000E09u, /* tr_group[8].input[36] */
+ TRIG14_OUT_TR_GROUP2_INPUT37 = 0x40000E0Au, /* tr_group[2].input[37] */
+ TRIG14_OUT_TR_GROUP3_INPUT37 = 0x40000E0Au, /* tr_group[3].input[37] */
+ TRIG14_OUT_TR_GROUP4_INPUT37 = 0x40000E0Au, /* tr_group[4].input[37] */
+ TRIG14_OUT_TR_GROUP5_INPUT37 = 0x40000E0Au, /* tr_group[5].input[37] */
+ TRIG14_OUT_TR_GROUP6_INPUT37 = 0x40000E0Au, /* tr_group[6].input[37] */
+ TRIG14_OUT_TR_GROUP7_INPUT37 = 0x40000E0Au, /* tr_group[7].input[37] */
+ TRIG14_OUT_TR_GROUP8_INPUT37 = 0x40000E0Au, /* tr_group[8].input[37] */
+ TRIG14_OUT_TR_GROUP2_INPUT38 = 0x40000E0Bu, /* tr_group[2].input[38] */
+ TRIG14_OUT_TR_GROUP3_INPUT38 = 0x40000E0Bu, /* tr_group[3].input[38] */
+ TRIG14_OUT_TR_GROUP4_INPUT38 = 0x40000E0Bu, /* tr_group[4].input[38] */
+ TRIG14_OUT_TR_GROUP5_INPUT38 = 0x40000E0Bu, /* tr_group[5].input[38] */
+ TRIG14_OUT_TR_GROUP6_INPUT38 = 0x40000E0Bu, /* tr_group[6].input[38] */
+ TRIG14_OUT_TR_GROUP7_INPUT38 = 0x40000E0Bu, /* tr_group[7].input[38] */
+ TRIG14_OUT_TR_GROUP8_INPUT38 = 0x40000E0Bu, /* tr_group[8].input[38] */
+ TRIG14_OUT_TR_GROUP2_INPUT39 = 0x40000E0Cu, /* tr_group[2].input[39] */
+ TRIG14_OUT_TR_GROUP3_INPUT39 = 0x40000E0Cu, /* tr_group[3].input[39] */
+ TRIG14_OUT_TR_GROUP4_INPUT39 = 0x40000E0Cu, /* tr_group[4].input[39] */
+ TRIG14_OUT_TR_GROUP5_INPUT39 = 0x40000E0Cu, /* tr_group[5].input[39] */
+ TRIG14_OUT_TR_GROUP6_INPUT39 = 0x40000E0Cu, /* tr_group[6].input[39] */
+ TRIG14_OUT_TR_GROUP7_INPUT39 = 0x40000E0Cu, /* tr_group[7].input[39] */
+ TRIG14_OUT_TR_GROUP8_INPUT39 = 0x40000E0Cu, /* tr_group[8].input[39] */
+ TRIG14_OUT_TR_GROUP2_INPUT40 = 0x40000E0Du, /* tr_group[2].input[40] */
+ TRIG14_OUT_TR_GROUP3_INPUT40 = 0x40000E0Du, /* tr_group[3].input[40] */
+ TRIG14_OUT_TR_GROUP4_INPUT40 = 0x40000E0Du, /* tr_group[4].input[40] */
+ TRIG14_OUT_TR_GROUP5_INPUT40 = 0x40000E0Du, /* tr_group[5].input[40] */
+ TRIG14_OUT_TR_GROUP6_INPUT40 = 0x40000E0Du, /* tr_group[6].input[40] */
+ TRIG14_OUT_TR_GROUP7_INPUT40 = 0x40000E0Du, /* tr_group[7].input[40] */
+ TRIG14_OUT_TR_GROUP8_INPUT40 = 0x40000E0Du, /* tr_group[8].input[40] */
+ TRIG14_OUT_TR_GROUP2_INPUT41 = 0x40000E0Eu, /* tr_group[2].input[41] */
+ TRIG14_OUT_TR_GROUP3_INPUT41 = 0x40000E0Eu, /* tr_group[3].input[41] */
+ TRIG14_OUT_TR_GROUP4_INPUT41 = 0x40000E0Eu, /* tr_group[4].input[41] */
+ TRIG14_OUT_TR_GROUP5_INPUT41 = 0x40000E0Eu, /* tr_group[5].input[41] */
+ TRIG14_OUT_TR_GROUP6_INPUT41 = 0x40000E0Eu, /* tr_group[6].input[41] */
+ TRIG14_OUT_TR_GROUP7_INPUT41 = 0x40000E0Eu, /* tr_group[7].input[41] */
+ TRIG14_OUT_TR_GROUP8_INPUT41 = 0x40000E0Eu, /* tr_group[8].input[41] */
+ TRIG14_OUT_TR_GROUP2_INPUT42 = 0x40000E0Fu, /* tr_group[2].input[42] */
+ TRIG14_OUT_TR_GROUP3_INPUT42 = 0x40000E0Fu, /* tr_group[3].input[42] */
+ TRIG14_OUT_TR_GROUP4_INPUT42 = 0x40000E0Fu, /* tr_group[4].input[42] */
+ TRIG14_OUT_TR_GROUP5_INPUT42 = 0x40000E0Fu, /* tr_group[5].input[42] */
+ TRIG14_OUT_TR_GROUP6_INPUT42 = 0x40000E0Fu, /* tr_group[6].input[42] */
+ TRIG14_OUT_TR_GROUP7_INPUT42 = 0x40000E0Fu, /* tr_group[7].input[42] */
+ TRIG14_OUT_TR_GROUP8_INPUT42 = 0x40000E0Fu /* tr_group[8].input[42] */
+} en_trig_output_grp14_t;
+
+/* Level or edge detection setting for a trigger mux */
+typedef enum
+{
+ /* The trigger is a simple level output */
+ TRIGGER_TYPE_LEVEL = 0u,
+ /* The trigger is synchronized to the consumer blocks clock
+ and a two cycle pulse is generated on this clock */
+ TRIGGER_TYPE_EDGE = 1u
+} en_trig_type_t;
+
+/* Trigger Type Defines */
+/* TCPWM Trigger Types */
+#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE
+/* CSD Trigger Types */
+#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE
+/* SCB Trigger Types */
+#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL
+/* PERI Trigger Types */
+#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE
+/* CPUSS Trigger Types */
+#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE
+/* AUDIOSS Trigger Types */
+#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL
+/* LPCOMP Trigger Types */
+#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL
+/* PASS Trigger Types */
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE
+/* SMIF Trigger Types */
+#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL
+/* USB Trigger Types */
+#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE
+/* UDB Trigger Types */
+#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE
+/* PROFILE Trigger Types */
+#define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE
+/* TR_GROUP Trigger Types */
+#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE
+#define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL
+#define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE
+
+/* Monitor Signal Defines */
+typedef enum
+{
+ PROFILE_ONE = 0, /* profile.one */
+ CPUSS_MONITOR_CM0 = 1, /* cpuss.monitor_cm0 */
+ CPUSS_MONITOR_CM4 = 2, /* cpuss.monitor_cm4 */
+ CPUSS_MONITOR_FLASH = 3, /* cpuss.monitor_flash */
+ CPUSS_MONITOR_DW0_AHB = 4, /* cpuss.monitor_dw0_ahb */
+ CPUSS_MONITOR_DW1_AHB = 5, /* cpuss.monitor_dw1_ahb */
+ CPUSS_MONITOR_CRYPTO = 6, /* cpuss.monitor_crypto */
+ USB_MONITOR_AHB = 7, /* usb.monitor_ahb */
+ SCB0_MONITOR_AHB = 8, /* scb[0].monitor_ahb */
+ SCB1_MONITOR_AHB = 9, /* scb[1].monitor_ahb */
+ SCB2_MONITOR_AHB = 10, /* scb[2].monitor_ahb */
+ SCB3_MONITOR_AHB = 11, /* scb[3].monitor_ahb */
+ SCB4_MONITOR_AHB = 12, /* scb[4].monitor_ahb */
+ SCB5_MONITOR_AHB = 13, /* scb[5].monitor_ahb */
+ SCB6_MONITOR_AHB = 14, /* scb[6].monitor_ahb */
+ SCB7_MONITOR_AHB = 15, /* scb[7].monitor_ahb */
+ SCB8_MONITOR_AHB = 16, /* scb[8].monitor_ahb */
+ UDB_MONITOR_UDB0 = 17, /* udb.monitor_udb[0] */
+ UDB_MONITOR_UDB1 = 18, /* udb.monitor_udb[1] */
+ UDB_MONITOR_UDB2 = 19, /* udb.monitor_udb[2] */
+ UDB_MONITOR_UDB3 = 20, /* udb.monitor_udb[3] */
+ SMIF_MONITOR_SMIF_SPI_SELECT0 = 21, /* smif.monitor_smif_spi_select[0] */
+ SMIF_MONITOR_SMIF_SPI_SELECT1 = 22, /* smif.monitor_smif_spi_select[1] */
+ SMIF_MONITOR_SMIF_SPI_SELECT2 = 23, /* smif.monitor_smif_spi_select[2] */
+ SMIF_MONITOR_SMIF_SPI_SELECT3 = 24, /* smif.monitor_smif_spi_select[3] */
+ SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25, /* smif.monitor_smif_spi_select_any */
+ BLESS_EXT_LNA_RX_CTL_OUT = 26, /* bless.ext_lna_rx_ctl_out */
+ BLESS_EXT_PA_TX_CTL_OUT = 27 /* bless.ext_pa_tx_ctl_out */
+} en_ep_mon_sel_t;
+
+/* Total count of Energy Profiler monitor signal connections */
+#define EP_MONITOR_COUNT 28u
+
+/* Bus masters */
+typedef enum
+{
+ CPUSS_MS_ID_CM0 = 0,
+ CPUSS_MS_ID_CRYPTO = 1,
+ CPUSS_MS_ID_DW0 = 2,
+ CPUSS_MS_ID_DW1 = 3,
+ CPUSS_MS_ID_CM4 = 14,
+ CPUSS_MS_ID_TC = 15
+} en_prot_master_t;
+
+/* Parameter Defines */
+/* Number of regulator modules instantiated within SRSS */
+#define SRSS_NUM_ACTREG_PWRMOD 2u
+/* Number of shorting switches between vccd and vccact */
+#define SRSS_NUM_ACTIVE_SWITCH 3u
+/* ULP linear regulator system is present */
+#define SRSS_ULPLINREG_PRESENT 1u
+/* HT linear regulator system is present */
+#define SRSS_HTLINREG_PRESENT 0u
+/* SIMO buck core regulator is present. Only compatible with ULP linear regulator
+ system (ULPLINREG_PRESENT==1). */
+#define SRSS_SIMOBUCK_PRESENT 1u
+/* Precision ILO (PILO) is present */
+#define SRSS_PILO_PRESENT 1u
+/* External Crystal Oscillator is present (high frequency) */
+#define SRSS_ECO_PRESENT 1u
+/* System Buck-Boost is present */
+#define SRSS_SYSBB_PRESENT 0u
+/* Number of clock paths. Must be > 0 */
+#define SRSS_NUM_CLKPATH 5u
+/* Number of PLLs present. Must be <= NUM_CLKPATH */
+#define SRSS_NUM_PLL 1u
+/* Number of HFCLK roots present. Must be > 0 */
+#define SRSS_NUM_HFROOT 5u
+/* Number of PWR_HIB_DATA registers */
+#define SRSS_NUM_HIBDATA 1u
+/* Backup domain is present */
+#define SRSS_BACKUP_PRESENT 1u
+/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of
+ mask indicates presence of a CSV. */
+#define SRSS_MASK_HFCSV 0u
+/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */
+#define SRSS_WCOCSV_PRESENT 0u
+/* Number of software watchdog timers. */
+#define SRSS_NUM_MCWDT 2u
+/* Number of DSI inputs into clock muxes. This is used for logic optimization. */
+#define SRSS_NUM_DSI 2u
+/* Alternate high-frequency clock is present. This is used for logic optimization. */
+#define SRSS_ALTHF_PRESENT 1u
+/* Alternate low-frequency clock is present. This is used for logic optimization. */
+#define SRSS_ALTLF_PRESENT 0u
+/* Use the hardened clkactfllmux block */
+#define SRSS_USE_HARD_CLKACTFLLMUX 1u
+/* Number of clock paths, including direct paths in hardened clkactfllmux block
+ (Must be >= NUM_CLKPATH) */
+#define SRSS_HARD_CLKPATH 6u
+/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >=
+ NUM_PLL+1) */
+#define SRSS_HARD_CLKPATHMUX 6u
+/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */
+#define SRSS_HARD_HFROOT 6u
+/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */
+#define SRSS_HARD_ECOMUX_PRESENT 1u
+/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */
+#define SRSS_HARD_ALTHFMUX_PRESENT 1u
+/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT
+ or SIMOBUCK_PRESENT. */
+#define SRSS_BUCKCTL_PRESENT 1u
+/* Low-current SISO buck core regulator is present. Only compatible with ULP
+ linear regulator system (ULPLINREG_PRESENT==1). */
+#define SRSS_S40S_SISOBUCKLC_PRESENT 0u
+/* Backup memory is present (only used when BACKUP_PRESENT==1) */
+#define SRSS_BACKUP_BMEM_PRESENT 0u
+/* Number of Backup registers to include (each is 32b). Only used when
+ BACKUP_PRESENT==1. */
+#define SRSS_BACKUP_NUM_BREG 16u
+/* Number of AMUX splitter cells */
+#define IOSS_HSIOM_AMUX_SPLIT_NR 9u
+/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */
+#define IOSS_HSIOM_HSIOM_PORT_NR 15u
+/* Number of GPIO ports in range 0..31 */
+#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u
+/* Number of GPIO ports in range 32..63 */
+#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u
+/* Number of GPIO ports in range 64..95 */
+#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u
+/* Number of GPIO ports in range 96..127 */
+#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u
+/* Number of ports in device */
+#define IOSS_GPIO_GPIO_PORT_NR 15u
+/* Mask of SMARTIO instances presence */
+#define IOSS_SMARTIO_SMARTIO_MASK 768u
+/* The number of protection contexts ([2, 16]). */
+#define PERI_PC_NR 8u
+/* Master interface presence mask (4 bits) */
+#define PERI_MS_PRESENT 15u
+/* Master interface PPU combinatorial (1) or registerd (0) */
+#define PERI_MS_PPU_COMBINATORIAL 1u
+/* The number of programmable PPU structures for PERI (all peripherals) */
+#define PERI_MS_PPU_PROG_STRUCT_NR 16u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Presence of a timeout functionality (1: Yes, 0:No) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u
+/* Slave present (0:No, 1:Yes) */
+#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u
+/* Number of programmable clocks (outputs) */
+#define PERI_CLOCK_NR 59u
+/* Number of 8.0 dividers */
+#define PERI_DIV_8_NR 8u
+/* Number of 16.0 dividers */
+#define PERI_DIV_16_NR 16u
+/* Number of 16.5 (fractional) dividers */
+#define PERI_DIV_16_5_NR 4u
+/* Number of 24.5 (fractional) dividers */
+#define PERI_DIV_24_5_NR 1u
+/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */
+#define PERI_DIV_ADDR_WIDTH 4u
+/* Trigger module present (0=No, 1=Yes) */
+#define PERI_TR 1u
+/* Number of trigger groups */
+#define PERI_TR_GROUP_NR 15u
+/* The number of protection contexts minus 1 ([1, 15]). */
+#define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u
+/* The number of protection contexts minus 1 ([1, 15]). */
+#define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u
+/* UDB present or not ('0': no, '1': yes) */
+#define CPUSS_UDB_PRESENT 1u
+/* System RAM 0 size in kilobytes */
+#define CPUSS_SRAM0_SIZE 288u
+/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System
+ SRAM0 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC0_MACRO_NR 9u
+/* System RAM 1 present or not (0=No, 1=Yes) */
+#define CPUSS_RAMC1_PRESENT 0u
+/* System RAM 1 size in kilobytes */
+#define CPUSS_SRAM1_SIZE 32u
+/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System
+ RAM 1 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC1_MACRO_NR 1u
+/* System RAM 2 present or not (0=No, 1=Yes) */
+#define CPUSS_RAMC2_PRESENT 0u
+/* System RAM 2 size in kilobytes */
+#define CPUSS_SRAM2_SIZE 256u
+/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System
+ RAM 2 is implemented with 8 32KB macros. */
+#define CPUSS_RAMC2_MACRO_NR 16u
+/* System ROM size in KB */
+#define CPUSS_ROM_SIZE 128u
+/* Flash main region size in KB */
+#define CPUSS_FLASH_SIZE 1024u
+/* Flash work region size in KB (EEPROM emulation, data) */
+#define CPUSS_WFLASH_SIZE 32u
+/* Flash supervisory region size in KB */
+#define CPUSS_SFLASH_SIZE 32u
+/* Flash data output size (in Bytes) */
+#define CPUSS_FLASHC_WORD_SIZE 16u
+/* Flash row address width */
+#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u
+/* Flash column address width */
+#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u
+/* Number of external slaves directly connected to slow AHB-Lite infrastructure.
+ Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
+ 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
+ 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK
+ parameters (for the slaves present) should be derived from the Memory Map. */
+#define CPUSS_SLOW_SL_PRESENT 1u
+/* Number of external slaves directly connected to fast AHB-Lite infrastructure.
+ Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
+ 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
+ 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK
+ parameters (for the slaves present) should be derived from the Memory Map. */
+#define CPUSS_FAST_SL_PRESENT 1u
+/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum
+ number of masters supported is 2. Width of this parameter is 2-bits. 1-bit
+ mask for each master indicating present or not. Example: 2'b01 - master 0 is
+ present. */
+#define CPUSS_SLOW_MS_PRESENT 0u
+/* Number of total interrupt request inputs to CPUSS */
+#define CPUSS_IRQ_NR 147u
+/* Number of DeepSleep wakeup interrupt inputs to CPUSS */
+#define CPUSS_DPSLP_IRQ_NR 41u
+/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */
+#define CPUSS_CM0_DPSLP_IRQ_NR 8u
+/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8
+ levels of priority 8 = 256 levels of priority */
+#define CPUSS_CM4_LVL_WIDTH 3u
+/* CM4 Floating point unit present or not (0=No, 1=Yes) */
+#define CPUSS_CM4_FPU_PRESENT 1u
+/* Debug level. Legal range [0,3] */
+#define CPUSS_DEBUG_LVL 3u
+/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3
+ for trace level is not supported in CPUSS. */
+#define CPUSS_TRACE_LVL 2u
+/* Embedded Trace Buffer present or not (0=No, 1=Yes) */
+#define CPUSS_ETB_PRESENT 0u
+/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
+#define CPUSS_MTB_SRAM_SIZE 4u
+/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
+#define CPUSS_ETB_SRAM_SIZE 16u
+/* PTM interface present (0=No, 1=Yes) */
+#define CPUSS_PTM_PRESENT 1u
+/* Width of the PTM interface in bits ([2,32]) */
+#define CPUSS_PTM_WIDTH 8u
+/* Width of the TPIU interface in bits ([1,32]) */
+#define CPUSS_TPIU_WIDTH 4u
+/* CoreSight Part Identification Number */
+#define CPUSS_JEPID 52u
+/* CoreSight Part Identification Number */
+#define CPUSS_JEPCONTINUATION 0u
+/* CoreSight Part Identification Number */
+#define CPUSS_FAMILYID 256u
+/* Cryptography IP present or not (0=No, 1=Yes) */
+#define CPUSS_CRYPTO_PRESENT 1u
+/* DataWire 0 present or not (0=No, 1=Yes) */
+#define CPUSS_DW0_PRESENT 1u
+/* Number of DataWire 0 channels (8, 16 or 32) */
+#define CPUSS_DW0_CH_NR 16u
+/* DataWire 1 present or not (0=No, 1=Yes) */
+#define CPUSS_DW1_PRESENT 1u
+/* Number of DataWire 1 channels (8, 16 or 32) */
+#define CPUSS_DW1_CH_NR 16u
+/* Number of Flash BIST_DATA registers */
+#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u
+/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */
+#define CPUSS_FLASHC_PA_SIZE 128u
+/* AES cipher support (0 = no support, 1 = support */
+#define CPUSS_CRYPTO_AES 1u
+/* (Tripple) DES cipher support (0 = no support, 1 = support */
+#define CPUSS_CRYPTO_DES 1u
+/* Pseudo random number generation support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_PR 1u
+/* SHA support included */
+#define CPUSS_CRYPTO_SHA 1u
+/* SHA1 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA1 1u
+/* SHA256 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA256 1u
+/* SHA512 hash support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_SHA512 1u
+/* Cyclic Redundancy Check support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_CRC 1u
+/* Vector unit support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_VU 1u
+/* True random number generation support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_TR 1u
+/* String support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_STR 1u
+/* AHB-Lite master interface support (0 = no support, 1 = support) */
+#define CPUSS_CRYPTO_MASTER_IF 1u
+/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128,
+ 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8
+ kB and 16 kB memory buffer) */
+#define CPUSS_CRYPTO_BUFF_SIZE 1024u
+/* Number of fault structures. Legal range [1, 4] */
+#define CPUSS_FAULT_FAULT_NR 2u
+/* Number of IPC structures. Legal range [1, 16] */
+#define CPUSS_IPC_IPC_NR 16u
+/* Number of IPC interrupt structures. Legal range [1, 16] */
+#define CPUSS_IPC_IPC_IRQ_NR 16u
+/* Master 0 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u
+/* Master 1 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u
+/* Master 2 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u
+/* Master 3 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u
+/* Master 4 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u
+/* Master 5 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u
+/* Master 6 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u
+/* Master 7 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u
+/* Master 8 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u
+/* Master 9 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u
+/* Master 10 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u
+/* Master 11 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u
+/* Master 12 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u
+/* Master 13 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u
+/* Master 14 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u
+/* Master 15 protect contexts minus one */
+#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u
+/* Number of SMPU protection structures */
+#define CPUSS_PROT_SMPU_STRUCT_NR 16u
+/* Number of protection contexts supported minus 1. Legal range [1,16] */
+#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u
+/* Number of DataWire controllers present (max 2) */
+#define CPUSS_DW_NR 2u
+/* Number of channels in each DataWire controller (must be the same for now) */
+#define CPUSS_DW_CH_NR 16u
+/* Number of profiling counters. Legal range [1, 32] */
+#define PROFILE_PRFL_CNT_NR 8u
+/* Number of monitor event signals. Legal range [1, 128] */
+#define PROFILE_PRFL_MONITOR_NR 128u
+/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */
+#define EFUSE_EFUSE_NR 4u
+/* SONOS Flash is used or not ('0': no, '1': yes) */
+#define SFLASH_FLASHC_IS_SONOS 1u
+/* Number of UDB Interrupts */
+#define UDB_NUMINT 16u
+/* Number of triggers */
+#define UDB_NUMTR 16u
+/* Number of UDB array rows (must be multiple of 2) */
+#define UDB_NUMROW 2u
+/* Number of UDB array columns */
+#define UDB_NUMCOL 6u
+/* DSI on bottom (1) or on bottom and top (2) of UDB array */
+#define UDB_DSISIDES 2u
+/* Number of UDBs = NUMROW * NUMCOL */
+#define UDB_NUMUDB 12u
+/* Number of UDB pairs = NUMUDB / 2 */
+#define UDB_NUMUDBPAIR 6u
+/* Number of DSIs = NUMCOL * DSISIDES */
+#define UDB_NUMDSI 12u
+/* Number of quad clocks */
+#define UDB_NUMQCLK 3u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB0_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB0_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB0_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB0_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB0_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB0_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB0_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB0_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB0_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB0_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB0_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB0_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB0_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB0_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB0_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB0_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB0_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB0_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB0_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB0_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB0_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB0_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB0_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB1_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB1_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB1_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB1_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB1_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB1_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB1_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB1_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB1_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB1_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB1_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB1_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB1_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB1_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB1_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB1_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB1_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB1_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB1_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB1_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB1_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB1_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB1_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB2_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB2_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB2_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB2_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB2_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB2_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB2_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB2_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB2_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB2_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB2_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB2_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB2_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB2_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB2_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB2_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB2_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB2_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB2_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB2_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB2_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB2_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB2_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB3_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB3_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB3_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB3_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB3_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB3_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB3_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB3_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB3_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB3_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB3_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB3_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB3_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB3_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB3_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB3_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB3_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB3_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB3_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB3_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB3_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB3_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB3_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB4_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB4_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB4_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB4_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB4_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB4_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB4_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB4_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB4_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB4_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB4_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB4_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB4_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB4_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB4_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB4_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB4_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB4_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB4_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB4_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB4_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB4_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB4_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB5_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB5_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB5_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB5_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB5_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB5_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB5_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB5_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB5_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB5_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB5_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB5_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB5_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB5_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB5_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB5_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB5_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB5_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB5_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB5_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB5_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB5_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB5_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB6_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB6_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB6_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB6_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB6_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB6_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB6_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB6_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB6_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB6_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB6_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB6_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB6_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB6_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB6_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB6_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB6_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB6_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB6_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB6_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB6_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB6_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB6_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB7_DEEPSLEEP 0u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB7_EC 0u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB7_I2C_M 1u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB7_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB7_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB7_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB7_I2C_EC 0u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB7_I2C_M_S 1u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB7_I2C_S_EC 0u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB7_SPI_M 1u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB7_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB7_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB7_SPI_EC 0u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB7_SPI_S_EC 0u
+/* UART support? ('0': no, '1': yes) */
+#define SCB7_UART 1u
+/* SPI or UART (SPI | UART) */
+#define SCB7_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB7_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB7_CMD_RESP 0u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB7_EZ 0u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB7_EZ_CMD_RESP 0u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB7_I2C_S_EZ 0u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB7_SPI_S_EZ 0u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB7_I2C_FAST_PLUS 1u
+/* DeepSleep support ('0':no, '1': yes) */
+#define SCB8_DEEPSLEEP 1u
+/* Externally clocked support? ('0': no, '1': yes) */
+#define SCB8_EC 1u
+/* I2C master support? ('0': no, '1': yes) */
+#define SCB8_I2C_M 0u
+/* I2C slave support? ('0': no, '1': yes) */
+#define SCB8_I2C_S 1u
+/* I2C support? (I2C_M | I2C_S) */
+#define SCB8_I2C 1u
+/* I2C glitch filters present? ('0': no, '1': yes) */
+#define SCB8_I2C_GLITCH 1u
+/* I2C externally clocked support? ('0': no, '1': yes) */
+#define SCB8_I2C_EC 1u
+/* I2C master and slave support? (I2C_M & I2C_S) */
+#define SCB8_I2C_M_S 0u
+/* I2C slave with EC? (I2C_S & I2C_EC) */
+#define SCB8_I2C_S_EC 1u
+/* SPI master support? ('0': no, '1': yes) */
+#define SCB8_SPI_M 0u
+/* SPI slave support? ('0': no, '1': yes) */
+#define SCB8_SPI_S 1u
+/* SPI support? (SPI_M | SPI_S) */
+#define SCB8_SPI 1u
+/* SPI externally clocked support? ('0': no, '1': yes) */
+#define SCB8_SPI_EC 1u
+/* SPI slave with EC? (SPI_S & SPI_EC) */
+#define SCB8_SPI_S_EC 1u
+/* UART support? ('0': no, '1': yes) */
+#define SCB8_UART 0u
+/* SPI or UART (SPI | UART) */
+#define SCB8_SPI_UART 1u
+/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
+ CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
+ 256 B are used. This is because the EZ mode uses 8-bit addresses. */
+#define SCB8_EZ_DATA_NR 256u
+/* Command/response mode support? ('0': no, '1': yes) */
+#define SCB8_CMD_RESP 1u
+/* EZ mode support? ('0': no, '1': yes) */
+#define SCB8_EZ 1u
+/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
+#define SCB8_EZ_CMD_RESP 1u
+/* I2C slave with EZ mode (I2C_S & EZ) */
+#define SCB8_I2C_S_EZ 1u
+/* SPI slave with EZ mode (SPI_S & EZ) */
+#define SCB8_SPI_S_EZ 1u
+/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
+#define SCB8_I2C_FAST_PLUS 1u
+/* Number of counters per IP (1..8) */
+#define TCPWM0_CNT_NR 8u
+/* Counter width (in number of bits) */
+#define TCPWM0_CNT_CNT_WIDTH 32u
+/* Number of counters per IP (1..8) */
+#define TCPWM1_CNT_NR 24u
+/* Counter width (in number of bits) */
+#define TCPWM1_CNT_CNT_WIDTH 16u
+/* Max number of LCD commons supported */
+#define LCD_COM_NR 8u
+/* Max number of LCD pins (total) supported */
+#define LCD_PIN_NR 62u
+/* Number of ports supoprting up to 4 COMs */
+#define LCD_NUMPORTS 8u
+/* Number of ports supporting up to 8 COMs */
+#define LCD_NUMPORTS8 8u
+/* Number of ports supporting up to 16 COMs */
+#define LCD_NUMPORTS16 0u
+/* Number of IREF outputs from AREF */
+#define PASS_NR_IREFS 4u
+/* Number of CTBs in the Subsystem */
+#define PASS_NR_CTBS 1u
+/* Number of CTDACs in the Subsystem */
+#define PASS_NR_CTDACS 1u
+/* CTB0 Exists */
+#define PASS_CTB0_EXISTS 1u
+/* CTB1 Exists */
+#define PASS_CTB1_EXISTS 0u
+/* CTB2 Exists */
+#define PASS_CTB2_EXISTS 0u
+/* CTB3 Exists */
+#define PASS_CTB3_EXISTS 0u
+/* CTDAC0 Exists */
+#define PASS_CTDAC0_EXISTS 1u
+/* CTDAC1 Exists */
+#define PASS_CTDAC1_EXISTS 0u
+/* CTDAC2 Exists */
+#define PASS_CTDAC2_EXISTS 0u
+/* CTDAC3 Exists */
+#define PASS_CTDAC3_EXISTS 0u
+/* Number of SAR channels */
+#define PASS_SAR_SAR_CHANNELS 16u
+/* Averaging logic present in SAR */
+#define PASS_SAR_SAR_AVERAGE 1u
+/* Range detect logic present in SAR */
+#define PASS_SAR_SAR_RANGEDET 1u
+/* Support for UAB sampling */
+#define PASS_SAR_SAR_UAB 0u
+#define PASS_CTBM_CTDAC_PRESENT 1u
+/* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */
+#define SMIF_MASTER_WIDTH 8u
+/* Base address of the SMIF XIP memory region. This address must be a multiple of
+ the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This
+ address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP
+ memory region should NOT overlap with other memory regions. */
+#define SMIF_SMIF_XIP_ADDR 402653184u
+/* Capacity of the SMIF XIP memory region. The more significant bits of this
+ parameter must be '1' and the lesser significant bits of this paramter must
+ be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are
+ {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000,
+ 0xffe0:0000, ..., 0xe000:0000}. */
+#define SMIF_SMIF_XIP_MASK 4160749568u
+/* Cryptography (AES) support ('0' = no support, '1' = support) */
+#define SMIF_CRYPTO 1u
+/* Number of external devices supported ([1,4]) */
+#define SMIF_DEVICE_NR 4u
+/* External device write support. This is a 4-bit field. Each external device has
+ a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */
+#define SMIF_DEVICE_WR_EN 15u
+/* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */
+#define SMIF_SPARE_EN 1u
+/* I2S capable? (0=No,1=Yes) */
+#define AUDIOSS_I2S 1u
+/* PDM capable? (0=No,1=Yes) */
+#define AUDIOSS_PDM 1u
+
+/* MMIO Targets Defines */
+#define CY_MMIO_CRYPTO_GROUP_NR 1u
+#define CY_MMIO_CRYPTO_SLAVE_NR 1u
+#define CY_MMIO_CPUSS_GROUP_NR 2u
+#define CY_MMIO_CPUSS_SLAVE_NR 1u
+#define CY_MMIO_FAULT_GROUP_NR 2u
+#define CY_MMIO_FAULT_SLAVE_NR 2u
+#define CY_MMIO_IPC_GROUP_NR 2u
+#define CY_MMIO_IPC_SLAVE_NR 3u
+#define CY_MMIO_PROT_GROUP_NR 2u
+#define CY_MMIO_PROT_SLAVE_NR 4u
+#define CY_MMIO_FLASHC_GROUP_NR 2u
+#define CY_MMIO_FLASHC_SLAVE_NR 5u
+#define CY_MMIO_SRSS_GROUP_NR 2u
+#define CY_MMIO_SRSS_SLAVE_NR 6u
+#define CY_MMIO_BACKUP_GROUP_NR 2u
+#define CY_MMIO_BACKUP_SLAVE_NR 7u
+#define CY_MMIO_DW_GROUP_NR 2u
+#define CY_MMIO_DW_SLAVE_NR 8u
+#define CY_MMIO_EFUSE_GROUP_NR 2u
+#define CY_MMIO_EFUSE_SLAVE_NR 12u
+#define CY_MMIO_PROFILE_GROUP_NR 2u
+#define CY_MMIO_PROFILE_SLAVE_NR 13u
+#define CY_MMIO_HSIOM_GROUP_NR 3u
+#define CY_MMIO_HSIOM_SLAVE_NR 1u
+#define CY_MMIO_GPIO_GROUP_NR 3u
+#define CY_MMIO_GPIO_SLAVE_NR 2u
+#define CY_MMIO_SMARTIO_GROUP_NR 3u
+#define CY_MMIO_SMARTIO_SLAVE_NR 3u
+#define CY_MMIO_UDB_GROUP_NR 3u
+#define CY_MMIO_UDB_SLAVE_NR 4u
+#define CY_MMIO_LPCOMP_GROUP_NR 3u
+#define CY_MMIO_LPCOMP_SLAVE_NR 5u
+#define CY_MMIO_CSD0_GROUP_NR 3u
+#define CY_MMIO_CSD0_SLAVE_NR 6u
+#define CY_MMIO_TCPWM0_GROUP_NR 3u
+#define CY_MMIO_TCPWM0_SLAVE_NR 8u
+#define CY_MMIO_TCPWM1_GROUP_NR 3u
+#define CY_MMIO_TCPWM1_SLAVE_NR 9u
+#define CY_MMIO_LCD0_GROUP_NR 3u
+#define CY_MMIO_LCD0_SLAVE_NR 10u
+#define CY_MMIO_BLE_GROUP_NR 3u
+#define CY_MMIO_BLE_SLAVE_NR 11u
+#define CY_MMIO_USBFS0_GROUP_NR 3u
+#define CY_MMIO_USBFS0_SLAVE_NR 12u
+#define CY_MMIO_SMIF0_GROUP_NR 4u
+#define CY_MMIO_SMIF0_SLAVE_NR 2u
+#define CY_MMIO_SCB0_GROUP_NR 6u
+#define CY_MMIO_SCB0_SLAVE_NR 1u
+#define CY_MMIO_SCB1_GROUP_NR 6u
+#define CY_MMIO_SCB1_SLAVE_NR 2u
+#define CY_MMIO_SCB2_GROUP_NR 6u
+#define CY_MMIO_SCB2_SLAVE_NR 3u
+#define CY_MMIO_SCB3_GROUP_NR 6u
+#define CY_MMIO_SCB3_SLAVE_NR 4u
+#define CY_MMIO_SCB4_GROUP_NR 6u
+#define CY_MMIO_SCB4_SLAVE_NR 5u
+#define CY_MMIO_SCB5_GROUP_NR 6u
+#define CY_MMIO_SCB5_SLAVE_NR 6u
+#define CY_MMIO_SCB6_GROUP_NR 6u
+#define CY_MMIO_SCB6_SLAVE_NR 7u
+#define CY_MMIO_SCB7_GROUP_NR 6u
+#define CY_MMIO_SCB7_SLAVE_NR 8u
+#define CY_MMIO_SCB8_GROUP_NR 6u
+#define CY_MMIO_SCB8_SLAVE_NR 9u
+#define CY_MMIO_PASS_GROUP_NR 9u
+#define CY_MMIO_PASS_SLAVE_NR 1u
+#define CY_MMIO_I2S0_GROUP_NR 10u
+#define CY_MMIO_I2S0_SLAVE_NR 1u
+#define CY_MMIO_PDM0_GROUP_NR 10u
+#define CY_MMIO_PDM0_SLAVE_NR 2u
+
+#endif /* _PSOC63_CONFIG_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,556 @@
+/***************************************************************************//**
+* \file system_psoc63.h
+* \version 2.10
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_PSOC63_H_
+#define _SYSTEM_PSOC63_H_
+
+/**
+* \defgroup group_system_config System Configuration Files (Startup)
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - See \ref group_system_config_device_initialization for the:
+* * \ref group_system_config_dual_core_device_initialization
+* * \ref group_system_config_single_core_device_initialization
+* - \ref group_system_config_device_memory_definition
+* - \ref group_system_config_heap_stack_config
+* - \ref group_system_config_merge_apps
+* - Default interrupt handlers definition
+* - \ref group_system_config_device_vector_table
+* - \ref group_system_config_cm4_functions
+*
+* \section group_system_config_configuration Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition Device Memory Definition
+* The flash and RAM allocation for each CPU is defined by the linker scripts.
+* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
+* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
+* For Single-Core devices the system reserves additional 80 bytes of RAM.
+* Using the reserved memory area for other purposes will lead to unexpected behavior.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
+* \endcode
+* - 'xx_cm4_dual.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
+* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
+* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
+* by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>ARM MDK</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10000000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08000000
+* #define RAM_SIZE 0x00024000
+* \endcode
+* - 'xx_cm4_dual.scat', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10080000
+* #define FLASH_SIZE 0x00080000
+* #define RAM_START 0x08024000
+* #define RAM_SIZE 0x00023800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
+* value in the 'xx_cm4_dual.scat' file,
+* where 'xx' is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
+* \endcode
+* - 'xx_cm4_dual.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
+* is the device group. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
+*
+* \subsection group_system_config_device_initialization Device Initialization
+* After a power-on-reset (POR), the boot process is handled by the boot code
+* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
+* code passes the control to the Cortex-M0+ startup code located in flash.
+*
+* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
+* The Cortex-M0+ startup code performs the device initialization by a call to
+* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
+* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
+* See \ref group_system_config_cm4_functions for more details.
+* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
+* The function has a separate implementation on each core.
+* Both function implementations unlock and disable the WDT.
+* Therefore enable the WDT after both cores have been initialized.
+*
+* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
+* The Cortex-M0+ core is not user-accessible on these devices. In this case the
+* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
+*
+* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
+* There are two ways to adjust heap and stack configurations:
+* -# Editing source code files
+* -# Specifying via command line
+*
+* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files:
+* 'startup_xx_yy.S', where 'xx' is the device family, and 'yy' is the target CPU;
+* for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code .equ Stack_Size, 0x00001000 \endcode
+* \code .equ Heap_Size, 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the compiler:\n
+* \code -D __STACK_SIZE=0x000000400 \endcode
+* \code -D __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files:
+* 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the target
+* CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the assembler:\n
+* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
+* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar IAR
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the
+* linker (including quotation marks):\n
+* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
+* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
+* The CM0+ project and linker script build the CM0+ application image. Similarly,
+* the CM4 linker script builds the CM4 application image. Each specifies
+* locations, sizes, and contents of sections in memory. See
+* \ref group_system_config_device_memory_definition for the symbols and default
+* values.
+*
+* The cymcuelftool is invoked by a post-build command. The precise project
+* setting is IDE-specific.
+*
+* The cymcuelftool combines the two executables. The tool examines the
+* executables to ensure that memory regions either do not overlap, or contain
+* identical bytes (shared). If there are no problems, it creates a new ELF file
+* with the merged image, without changing any of the addresses or data.
+*
+* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
+* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
+* It defines sections and locations in memory.\n
+* Copy interrupt vectors from flash to RAM: \n
+* From: \code LONG (__Vectors) \endcode
+* To: \code LONG (__ram_vectors_start__) \endcode
+* Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files: 'startup_xx_yy.S', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.S and
+* startup_psoc63_cm4.S. The code in these files copies the vector table from
+* Flash to RAM.
+* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
+* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
+* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the assembler startup
+* files: 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the
+* target CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s.
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar IAR
+* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* This file defines the .intvec_ram section and its location.
+* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files: 'startup_xx_yy.s', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.s and
+* startup_psoc63_cm4.s. The code in these files copies the vector table
+* from Flash to RAM.
+*
+* \section group_system_config_more_information More Information
+* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
+* more details.
+*
+* \section group_system_config_MISRA MISRA Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>R</td>
+* <td>The character sequence // shall not be used within a comment.</td>
+* <td>The comments provide a useful WEB link to the documentation.</td>
+* </tr>
+* </table>
+*
+* \section group_system_config_changelog Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.10</td>
+* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
+* Removed $Sub$$main symbol for ARM MDK compiler.
+* </td>
+* <td>uVision Debugger support.</td>
+* </tr>
+* <tr>
+* <td>Updated description of the Startup behavior for Single-Core Devices. \n
+* Added note about WDT disabling by SystemInit() function.
+* </td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
+* Single core device support.
+* </td>
+* </tr>
+* <tr>
+* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
+* Renamed 'wflash' memory region to 'em_eeprom'.
+* </td>
+* <td>Linker scripts usability improvement.</td>
+* </tr>
+* <tr>
+* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
+* <td>Reserved system resources for internal operations.</td>
+* </tr>
+* <tr>
+* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
+* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro Macro
+* \{
+* \defgroup group_system_config_system_macro System
+* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
+* \defgroup group_system_config_user_settings_macro User Settings
+* \}
+* \defgroup group_system_config_functions Functions
+* \{
+* \defgroup group_system_config_system_functions System
+* \defgroup group_system_config_cm4_functions Cortex-M4 Control
+* \}
+* \defgroup group_system_config_globals Global Variables
+*
+* \}
+*/
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+* \details
+* The following system functions implement CMSIS Core functions.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* \}
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
+ #define CY_SYSTEM_CPU_CM0P 1UL
+#else
+ #define CY_SYSTEM_CPU_CM0P 0UL
+#endif
+
+#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
+ #include "cyfitter.h"
+#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
+
+
+/*******************************************************************************
+*
+* START OF USER SETTINGS HERE
+* ===========================
+*
+* All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_user_settings_macro
+* \{
+*/
+
+
+#if defined (CYDEV_CLK_EXTCLK__HZ)
+ #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
+#else
+ /***************************************************************************//**
+ * External Clock Frequency (in Hz, [value]UL). If compiled within
+ * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
+ * Otherwise, edit the value below.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
+#endif /* (CYDEV_CLK_EXTCLK__HZ) */
+
+
+#if defined (CYDEV_CLK_ECO__HZ)
+ #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
+#else
+ /***************************************************************************//**
+ * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
+ * within PSoC Creator and the clock is enabled in the DWR, the value from DWR
+ * used.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
+#endif /* (CYDEV_CLK_ECO__HZ) */
+
+
+#if defined (CYDEV_CLK_ALTHF__HZ)
+ #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
+#else
+ /***************************************************************************//**
+ * \brief Alternate high frequency (in Hz, [value]UL). If compiled within
+ * PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
+ * Otherwise, edit the value below.
+ * <i>(USER SETTING)</i>
+ *******************************************************************************/
+ #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
+#endif /* (CYDEV_CLK_ALTHF__HZ) */
+
+
+/***************************************************************************//**
+* \brief Start address of the Cortex-M4 application ([address]UL)
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_CORTEX_M4_APPL_ADDR (0x10080000UL) /* <<< 512 KB reserved for the Cortex-M0+ application */
+
+
+/*******************************************************************************
+*
+* END OF USER SETTINGS HERE
+* =========================
+*
+*******************************************************************************/
+
+/** \} group_system_config_user_settings_macro */
+
+
+/**
+* \addtogroup group_system_config_system_macro
+* \{
+*/
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M0+ startup driver identifier */
+ #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u))
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M4 startup driver identifier */
+ #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0Fu) & 0x3FFFu) << 18u))
+#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
+
+/** \} group_system_config_system_macro */
+
+
+/**
+* \addtogroup group_system_config_system_functions
+* \{
+*/
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/** \} group_system_config_system_functions */
+
+
+/**
+* \addtogroup group_system_config_cm4_functions
+* \{
+*/
+extern uint32_t Cy_SysGetCM4Status(void);
+extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
+extern void Cy_SysDisableCM4(void);
+extern void Cy_SysRetainCM4(void);
+extern void Cy_SysResetCM4(void);
+/** \} group_system_config_cm4_functions */
+
+
+/** \cond */
+extern void Default_Handler (void);
+extern uint32_t Cy_SaveIRQ(void);
+extern void Cy_RestoreIRQ(uint32_t saved);
+
+extern void Cy_SystemInit(void);
+extern void Cy_SystemInitFpuEnable(void);
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+extern uint32_t cy_delay32kMs;
+/** \endcond */
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/**
+* \addtogroup group_system_config_cm4_status_macro
+* \{
+*/
+#define CY_SYS_CM4_STATUS_ENABLED (3u) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM4_STATUS_DISABLED (0u) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM4_STATUS_RETAINED (2u) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM4_STATUS_RESET (1u) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+/** \} group_system_config_cm4_status_macro */
+
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+/** \addtogroup group_system_config_globals
+* \{
+*/
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_BleEcoClockFreqHz;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+
+/** \} group_system_config_globals */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_PSOC63_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/ipc_rpc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,77 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IPC_RPC_H
+#define IPC_RPC_H
+
+#include <stdint.h>
+
+#if defined(__MBED__)
+#define IPCPIPE_ASSERT MBED_ASSERT
+#include "mbed_assert.h"
+#else
+#include "project.h"
+#define IPCPIPE_ASSERT CY_ASSERT
+#endif
+
+#define IPCRPC_MAX_ARGUMENTS 8
+
+/** IPC RPC message data structure
+ * Used to pass RPC call arguments to M0 core for execution
+ */
+typedef struct {
+ uint32_t client_id; ///< Client ID of the RPC client
+ uint32_t result; ///< Function execution result returned from callee to caller
+ uint32_t args_num; ///< Number of arguments to RPC function call
+ uint32_t args[IPCRPC_MAX_ARGUMENTS]; ///< Arguments of RPC function call
+} IpcRpcMessage;
+
+
+/** IPC RPC message buffer
+ * Used to hold and transfer RPC message
+ */
+typedef struct {
+ volatile uint8_t busy_flag; ///< Indicates whether the RPC call using this buffer is in progress
+ IpcRpcMessage message; ///< RPC message associated with a call
+} IpcRpcBuffer;
+
+
+/** Function handling the RPC call
+ * It packs its arguments into the RPC message buffer, initializes transfer
+ * and waits for completion.
+ *
+ * @param call_id unique identifier of the RPC API function to be executed
+ * @param args_num number of call arguments
+ * @param ... call arguments
+ *
+ * @return call result (as returned by executed function)
+ */
+uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...);
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/** Initialization function for RPC mechanism.
+ * Generated automatically during wrapper generation; needs to be called from startup code.
+ */
+void ipcrpc_init(void);
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* IPC_RPC_H */
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,74 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + + */ + +/* + * This file defines hardware resources statically allocated to M0 core + * when static resource managemnt is used. + * + * There are 4 classes of resources that must be declared here: + * - M0_ASSIGNED_PORTS macro defines which ports and pins are reserved + * for M0 core use. + * You define these as a colon separated list of ports and pins reserved + * using macro SRM_PORT(port_num, pins), one time for each reserved port. + * SRM_PORT macro arguments are port number, in the range 0 .. 14 and + * pins is a hex value with a bit set for each reserved pin on a port. + * + * - M0_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved + * for M0 core use. + * You define these as a colon separated list of dividers reserved + * using macro SRM_DIVIDER(type, reservations), one time for each required + * devider type. + * SRM_DIVIDER arguments are divider type, one of cy_en_divider_types_t + * values and reservations is a hex mask value with a bit set for each + * reserved divider of a given type. + * + * - M0_ASSIGNED_SCBS macro defines which SCB blocks are reserved + * for M0 core use. + * You define these as a colon separated list of SCBs reserved using + * macro SRM_SCB(n), which argument is SCB number in a range 0 .. 7. + * + * - M0_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved + * for M0 core use. + * You define these as a colon separated list of TCPWMs reserved using + * macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 .. 31. + * + * If a particular resource class is not used at all by M0 core you can + * skip defining relevant M0_ASSIGNED_* macro or define it as an empty one. + * + * Examples: + * #define M0_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03) + * + * #define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01) + * + * #define M0_ASSIGNED_SCBS SRM_SCB(2) + * + * #define M0_ASSIGNED_TCPWMS + * + */ + +// Reservations below apply to default M0 hex image. + +// P0_0 and p0_1 reserved for WCO, P6-6 and P6_7 reserved for SWD +#define M0_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(6, 0xc0), SRM_PORT(11, 0x02) +// 8-bit divider 0 reserved for us ticker. +#define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01), \ + SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01) +#define M0_ASSIGNED_SCBS +#define M0_ASSIGNED_TCPWMS + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,253 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+#include "PortNames.h"
+
+#if PSOC6_ENABLE_M0_M4_DEBUG
+
+#define CY_STDIO_UART_RX P9_0
+#define CY_STDIO_UART_TX P9_1
+#define CY_STDIO_UART_CTS P9_2
+#define CY_STDIO_UART_RTS P9_3
+#else
+
+#define CY_STDIO_UART_RX P5_0
+#define CY_STDIO_UART_TX P5_1
+#define CY_STDIO_UART_CTS P5_2
+#define CY_STDIO_UART_RTS P5_3
+
+#endif // PSOC6_ENABLE_M0_M4_DEBUG
+
+// PinName[15-0] = Port[15-8] + Pin[7-0]
+typedef enum {
+ P0_0 = (Port0 << 8) + 0x00,
+ P0_1 = (Port0 << 8) + 0x01,
+ P0_2 = (Port0 << 8) + 0x02,
+ P0_3 = (Port0 << 8) + 0x03,
+ P0_4 = (Port0 << 8) + 0x04,
+ P0_5 = (Port0 << 8) + 0x05,
+ P0_6 = (Port0 << 8) + 0x06,
+ P0_7 = (Port0 << 8) + 0x07,
+
+ P1_0 = (Port1 << 8) + 0x00,
+ P1_1 = (Port1 << 8) + 0x01,
+ P1_2 = (Port1 << 8) + 0x02,
+ P1_3 = (Port1 << 8) + 0x03,
+ P1_4 = (Port1 << 8) + 0x04,
+ P1_5 = (Port1 << 8) + 0x05,
+ P1_6 = (Port1 << 8) + 0x06,
+ P1_7 = (Port1 << 8) + 0x07,
+
+ P2_0 = (Port2 << 8) + 0x00,
+ P2_1 = (Port2 << 8) + 0x01,
+ P2_2 = (Port2 << 8) + 0x02,
+ P2_3 = (Port2 << 8) + 0x03,
+ P2_4 = (Port2 << 8) + 0x04,
+ P2_5 = (Port2 << 8) + 0x05,
+ P2_6 = (Port2 << 8) + 0x06,
+ P2_7 = (Port2 << 8) + 0x07,
+
+ P3_0 = (Port3 << 8) + 0x00,
+ P3_1 = (Port3 << 8) + 0x01,
+ P3_2 = (Port3 << 8) + 0x02,
+ P3_3 = (Port3 << 8) + 0x03,
+ P3_4 = (Port3 << 8) + 0x04,
+ P3_5 = (Port3 << 8) + 0x05,
+ P3_6 = (Port3 << 8) + 0x06,
+ P3_7 = (Port3 << 8) + 0x07,
+
+ P4_0 = (Port4 << 8) + 0x00,
+ P4_1 = (Port4 << 8) + 0x01,
+ P4_2 = (Port4 << 8) + 0x02,
+ P4_3 = (Port4 << 8) + 0x03,
+ P4_4 = (Port4 << 8) + 0x04,
+ P4_5 = (Port4 << 8) + 0x05,
+ P4_6 = (Port4 << 8) + 0x06,
+ P4_7 = (Port4 << 8) + 0x07,
+
+ P5_0 = (Port5 << 8) + 0x00,
+ P5_1 = (Port5 << 8) + 0x01,
+ P5_2 = (Port5 << 8) + 0x02,
+ P5_3 = (Port5 << 8) + 0x03,
+ P5_4 = (Port5 << 8) + 0x04,
+ P5_5 = (Port5 << 8) + 0x05,
+ P5_6 = (Port5 << 8) + 0x06,
+ P5_7 = (Port5 << 8) + 0x07,
+
+ P6_0 = (Port6 << 8) + 0x00,
+ P6_1 = (Port6 << 8) + 0x01,
+ P6_2 = (Port6 << 8) + 0x02,
+ P6_3 = (Port6 << 8) + 0x03,
+ P6_4 = (Port6 << 8) + 0x04,
+ P6_5 = (Port6 << 8) + 0x05,
+ P6_6 = (Port6 << 8) + 0x06,
+ P6_7 = (Port6 << 8) + 0x07,
+
+ P7_0 = (Port7 << 8) + 0x00,
+ P7_1 = (Port7 << 8) + 0x01,
+ P7_2 = (Port7 << 8) + 0x02,
+ P7_3 = (Port7 << 8) + 0x03,
+ P7_4 = (Port7 << 8) + 0x04,
+ P7_5 = (Port7 << 8) + 0x05,
+ P7_6 = (Port7 << 8) + 0x06,
+ P7_7 = (Port7 << 8) + 0x07,
+
+ P8_0 = (Port8 << 8) + 0x00,
+ P8_1 = (Port8 << 8) + 0x01,
+ P8_2 = (Port8 << 8) + 0x02,
+ P8_3 = (Port8 << 8) + 0x03,
+ P8_4 = (Port8 << 8) + 0x04,
+ P8_5 = (Port8 << 8) + 0x05,
+ P8_6 = (Port8 << 8) + 0x06,
+ P8_7 = (Port8 << 8) + 0x07,
+
+ P9_0 = (Port9 << 8) + 0x00,
+ P9_1 = (Port9 << 8) + 0x01,
+ P9_2 = (Port9 << 8) + 0x02,
+ P9_3 = (Port9 << 8) + 0x03,
+ P9_4 = (Port9 << 8) + 0x04,
+ P9_5 = (Port9 << 8) + 0x05,
+ P9_6 = (Port9 << 8) + 0x06,
+ P9_7 = (Port9 << 8) + 0x07,
+
+ P10_0 = (Port10 << 8) + 0x00,
+ P10_1 = (Port10 << 8) + 0x01,
+ P10_2 = (Port10 << 8) + 0x02,
+ P10_3 = (Port10 << 8) + 0x03,
+ P10_4 = (Port10 << 8) + 0x04,
+ P10_5 = (Port10 << 8) + 0x05,
+ P10_6 = (Port10 << 8) + 0x06,
+ P10_7 = (Port10 << 8) + 0x07,
+
+ P11_0 = (Port11 << 8) + 0x00,
+ P11_1 = (Port11 << 8) + 0x01,
+ P11_2 = (Port11 << 8) + 0x02,
+ P11_3 = (Port11 << 8) + 0x03,
+ P11_4 = (Port11 << 8) + 0x04,
+ P11_5 = (Port11 << 8) + 0x05,
+ P11_6 = (Port11 << 8) + 0x06,
+ P11_7 = (Port11 << 8) + 0x07,
+
+ P12_0 = (Port12 << 8) + 0x00,
+ P12_1 = (Port12 << 8) + 0x01,
+ P12_2 = (Port12 << 8) + 0x02,
+ P12_3 = (Port12 << 8) + 0x03,
+ P12_4 = (Port12 << 8) + 0x04,
+ P12_5 = (Port12 << 8) + 0x05,
+ P12_6 = (Port12 << 8) + 0x06,
+ P12_7 = (Port12 << 8) + 0x07,
+
+ P13_0 = (Port13 << 8) + 0x00,
+ P13_1 = (Port13 << 8) + 0x01,
+ P13_2 = (Port13 << 8) + 0x02,
+ P13_3 = (Port13 << 8) + 0x03,
+ P13_4 = (Port13 << 8) + 0x04,
+ P13_5 = (Port13 << 8) + 0x05,
+ P13_6 = (Port13 << 8) + 0x06,
+ P13_7 = (Port13 << 8) + 0x07,
+
+ P14_0 = (Port14 << 8) + 0x00,
+ P14_1 = (Port14 << 8) + 0x01,
+ P14_2 = (Port14 << 8) + 0x02,
+ P14_3 = (Port14 << 8) + 0x03,
+ P14_4 = (Port14 << 8) + 0x04,
+ P14_5 = (Port14 << 8) + 0x05,
+ P14_6 = (Port14 << 8) + 0x06,
+ P14_7 = (Port14 << 8) + 0x07,
+
+ // Arduino connector namings
+ A0 = P10_4,
+ A1 = P10_5,
+ A2 = P10_2,
+ A3 = P10_3,
+ A4 = P10_1,
+ A5 = P10_0,
+
+ D0 = P6_4,
+ D1 = P6_5,
+ D2 = P10_6,
+ D3 = P12_6,
+ D4 = P12_7,
+ D5 = P6_2,
+ D6 = P6_3,
+ D7 = P7_2,
+ D8 = P7_1,
+ D9 = P7_7,
+ D10 = P9_4,
+ D11 = P9_0,
+ D12 = P9_1,
+ D13 = P9_2,
+ D14 = P10_1,
+ D15 = P10_0,
+
+ // Generic signal names
+
+ I2C_SCL = P10_0,
+ I2C_SDA = P10_1,
+ SPI_MOSI = P9_0,
+ SPI_MISO = P9_1,
+ SPI_CLK = P9_2,
+ SPI_CS = P9_3,
+ UART_RX = P6_4,
+ UART_TX = P6_5,
+
+ SWITCH2 = P0_4,
+ LED1 = P6_2,
+ LED2 = P6_3,
+ LED3 = P7_2,
+ LED4 = P6_2,
+ LED_RED = LED1,
+
+ USER_BUTTON = SWITCH2,
+ BUTTON1 = USER_BUTTON,
+
+ // Standardized interfaces names
+ STDIO_UART_TX = CY_STDIO_UART_TX,
+ STDIO_UART_RX = CY_STDIO_UART_RX,
+ STDIO_UART_CTS = CY_STDIO_UART_CTS,
+ STDIO_UART_RTS = CY_STDIO_UART_RTS,
+ USBTX = CY_STDIO_UART_TX,
+ USBRX = CY_STDIO_UART_RX,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+// PinName[15-0] = Port[15-8] + Pin[4-0]
+static inline unsigned CY_PIN(PinName pin)
+{
+ return pin & 0x07;
+}
+
+static inline unsigned CY_PORT(PinName pin)
+{
+ return (pin >> 8) & 0xFF;
+}
+
+// Because MBED pin mapping API does not allow to map multiple instances of the PWM
+// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit
+// usage instead of standard 16-bit PWM.
+
+#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin)
+
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,330 @@
+
+/*******************************************************************************
+* File Name: board_config.c (formerly cyfitter_cfg.c)
+*
+* PSoC Creator 4.2
+*
+* Description:
+* This file contains device initialization code.
+* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2017-2018, Future Electronics
+* SPDX-License-Identifier: Apache-2.0
+********************************************************************************/
+
+#include <string.h>
+#include "device.h"
+#include "gpio/cy_gpio.h"
+#include "syslib/cy_syslib.h"
+#include "sysclk/cy_sysclk.h"
+#include "systick/cy_systick.h"
+#include "sysanalog/cy_sysanalog.h"
+
+#if FEATURE_BLE
+#include "ble/cy_ble_clk.h"
+#endif // FEATURE_BLE
+
+#define CY_NEED_CYCLOCKSTARTUPERROR 1
+#include "syspm/cy_syspm.h"
+
+#include "psoc6_utils.h"
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+#define CYPACKED
+#define CYPACKED_ATTR __attribute__ ((packed))
+#define CYALIGNED __attribute__ ((aligned))
+#define CY_CFG_UNUSED __attribute__ ((unused))
+#ifndef CY_CFG_SECTION
+#define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
+#endif
+
+#if defined(__ARMCC_VERSION)
+#define CY_CFG_MEMORY_BARRIER() __memory_changed()
+#else
+#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
+#endif
+
+#elif defined(__ICCARM__)
+#include <intrinsics.h>
+
+#define CYPACKED __packed
+#define CYPACKED_ATTR
+#define CYALIGNED _Pragma("data_alignment=4")
+#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
+#define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
+
+#define CY_CFG_MEMORY_BARRIER() __DMB()
+
+#else
+#error Unsupported toolchain
+#endif
+
+#ifndef CYCODE
+#define CYCODE
+#endif
+#ifndef CYDATA
+#define CYDATA
+#endif
+#ifndef CYFAR
+#define CYFAR
+#endif
+#ifndef CYXDATA
+#define CYXDATA
+#endif
+
+
+CY_CFG_UNUSED
+static void CYMEMZERO(void *s, size_t n);
+CY_CFG_UNUSED
+static void CYMEMZERO(void *s, size_t n)
+{
+ (void)memset(s, 0, n);
+}
+CY_CFG_UNUSED
+static void CYCONFIGCPY(void *dest, const void *src, size_t n);
+CY_CFG_UNUSED
+static void CYCONFIGCPY(void *dest, const void *src, size_t n)
+{
+ (void)memcpy(dest, src, n);
+}
+CY_CFG_UNUSED
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
+CY_CFG_UNUSED
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
+{
+ (void)memcpy(dest, src, n);
+}
+
+
+
+
+/* Clock startup error codes */
+#define CYCLOCKSTART_NO_ERROR 0u
+#define CYCLOCKSTART_XTAL_ERROR 1u
+#define CYCLOCKSTART_32KHZ_ERROR 2u
+#define CYCLOCKSTART_PLL_ERROR 3u
+#define CYCLOCKSTART_FLL_ERROR 4u
+#define CYCLOCKSTART_WCO_ERROR 5u
+
+#ifdef CY_NEED_CYCLOCKSTARTUPERROR
+/*******************************************************************************
+* Function Name: CyClockStartupError
+********************************************************************************
+* Summary:
+* If an error is encountered during clock configuration (crystal startup error,
+* PLL lock error, etc.), the system will end up here. Unless reimplemented by
+* the customer, this function will stop in an infinite loop.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+CY_CFG_UNUSED
+static void CyClockStartupError(uint8 errorCode);
+CY_CFG_UNUSED
+static void CyClockStartupError(uint8 errorCode)
+{
+ /* To remove the compiler warning if errorCode not used. */
+ errorCode = errorCode;
+
+ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
+ /* we will end up here to allow the customer to implement something to */
+ /* deal with the clock condition. */
+
+#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
+ CY_CFG_Clock_Startup_ErrorCallback();
+#else
+ while(1) {}
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
+}
+#endif
+
+static void ClockInit(void)
+{
+ uint32_t status;
+
+ /* Enable all source clocks */
+ status = Cy_SysClk_WcoEnable(500000u);
+ if (CY_RET_SUCCESS != status) {
+ CyClockStartupError(CYCLOCKSTART_WCO_ERROR);
+ }
+ Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+
+#if FEATURE_BLE
+ {
+ cy_stc_ble_bless_eco_cfg_params_t bleCfg = {
+ .ecoXtalStartUpTime = (785 / 31.25),
+ .loadCap = ((9.9 - 7.5) / 0.075),
+ .ecoFreq = CY_BLE_BLESS_ECO_FREQ_32MHZ,
+ .ecoSysDiv = CY_BLE_SYS_ECO_CLK_DIV_4
+ };
+ Cy_BLE_EcoStart(&bleCfg);
+ }
+#endif // FEATURE_BLE
+
+ /* Configure CPU clock dividers */
+ Cy_SysClk_ClkFastSetDivider(0u);
+ Cy_SysClk_ClkPeriSetDivider((CY_CLK_HFCLK0_FREQ_HZ / CY_CLK_PERICLK_FREQ_HZ) - 1);
+ Cy_SysClk_ClkSlowSetDivider((CY_CLK_PERICLK_FREQ_HZ / CY_CLK_SYSTEM_FREQ_HZ) - 1);
+
+ /* Configure LF & HF clocks */
+ Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(0u);
+
+ /* Configure Path Clocks */
+ /* PLL path is used to clock HF domain from BLE ECO */
+ Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkPathSetSource(3, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkPathSetSource(4, CY_SYSCLK_CLKPATH_IN_IMO);
+#if FEATURE_BLE
+ Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_ALTHF);
+ Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_ALTHF);
+ {
+ const cy_stc_pll_config_t pllConfig = {
+ .inputFreq = CY_CLK_ALTHF_FREQ_HZ,
+ .outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+ };
+#else
+ Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO);
+ {
+ const cy_stc_pll_config_t pllConfig = {
+ .inputFreq = CY_CLK_IMO_FREQ_HZ,
+ .outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+ };
+#endif // FEATURE_BLE
+ status = Cy_SysClk_PllConfigure(1u, &pllConfig);
+ if (CY_SYSCLK_SUCCESS != status) {
+ CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
+ }
+ }
+ status = Cy_SysClk_PllEnable(1u, 10000u);
+ if (CY_SYSCLK_SUCCESS != status) {
+ CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
+ }
+
+ /* Configure miscellaneous clocks */
+ Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
+ Cy_SysClk_ClkTimerSetDivider(0);
+ Cy_SysClk_ClkTimerEnable();
+ Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
+ Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
+ Cy_SysClk_ClkPumpEnable();
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
+
+ /* Disable unused clocks started by default */
+ Cy_SysClk_IloDisable();
+
+ /* Set memory wait states based on HFClk[0] */
+ Cy_SysLib_SetWaitStates(false, (CY_CLK_HFCLK0_FREQ_HZ + 990000) / 1000000UL);
+}
+
+
+/* Analog API Functions */
+
+
+/*******************************************************************************
+* Function Name: AnalogSetDefault
+********************************************************************************
+*
+* Summary:
+* Sets up the analog portions of the chip to default values based on chip
+* configuration options from the project.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+static void AnalogSetDefault(void)
+{
+ const cy_stc_sysanalog_config_t config = {
+ .startup = CY_SYSANALOG_STARTUP_NORMAL,
+ .iztat = CY_SYSANALOG_IZTAT_SOURCE_LOCAL,
+ .vref = CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V,
+ .deepSleep = CY_SYSANALOG_DEEPSLEEP_IPTAT_1
+ };
+ Cy_SysAnalog_Init(&config);
+ Cy_SysAnalog_Enable();
+}
+
+
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+********************************************************************************
+* Summary:
+* This function is called by the start-up code for the selected device. It
+* performs all of the necessary device configuration based on the design
+* settings. This includes settings from the Design Wide Resources (DWR) such
+* as Clocks and Pins as well as any component configuration that is necessary.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+
+void Cy_SystemInit(void)
+{
+ /* Set worst case memory wait states (150 MHz), ClockInit() will update */
+ Cy_SysLib_SetWaitStates(false, 150);
+
+ if(0u == Cy_SysLib_GetResetReason()) { /* POR, XRES, or BOD */
+ Cy_SysLib_ResetBackupDomain();
+ }
+
+ /* Power Mode */
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V);
+
+ /* PMIC Control */
+ Cy_SysPm_UnlockPmic();
+ Cy_SysPm_DisablePmicOutput();
+
+ /* Pin0_0 and Pin0_1 drive WCO, configure as analog before configuring clock */
+ cy_reserve_io_pin(P0_0);
+ cy_reserve_io_pin(P0_1);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0, CY_GPIO_DM_ANALOG, 0, P0_0_GPIO);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1, CY_GPIO_DM_ANALOG, 0, P0_1_GPIO);
+
+ /* Clock */
+ ClockInit();
+
+ /******* Pre-defined port configuration section ********/
+ {
+ /* RGB LED is P_0_3 (R), P_1_1 (G) and P_11_1 (B) */
+ const uint32_t led_off = 1;
+ Cy_GPIO_Pin_FastInit(GPIO_PRT0, 3, CY_GPIO_DM_STRONG_IN_OFF, led_off, P0_3_GPIO);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT1, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P1_1_GPIO);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT11, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P11_1_GPIO);
+
+ /* USER BUTTON is P_0_4 */
+ Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4, CY_GPIO_DM_PULLUP, 1, P0_4_GPIO);
+
+ /* Configure hw debug interface on port 6 */
+ cy_reserve_io_pin(P6_6);
+ cy_reserve_io_pin(P6_7);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT6, 6, CY_GPIO_DM_PULLUP, 0, P6_6_CPUSS_SWJ_SWDIO_TMS);
+ Cy_GPIO_Pin_FastInit(GPIO_PRT6, 7, CY_GPIO_DM_PULLDOWN, 0, P6_7_CPUSS_SWJ_SWCLK_TCLK);
+ }
+
+ /* Perform basic analog initialization to defaults */
+ AnalogSetDefault();
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/stdio_init.cpp Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,30 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" + +/* + * This makes sure, stdio serial is initialized on M4 core at the very beginning + * and outside of any critical context, so printf is usable anywhere, including + * interrupt and fault handlers. + * Hardware devices cannot be initialized in the interrupt or critical section context + * on PSoC 6 M4 core. + */ + +#if DEVICE_STDIO_MESSAGES && !defined(TARGET_MCU_PSOC6_M0) +Serial _stdio_uart_object(STDIO_UART_TX, STDIO_UART_RX); +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,171 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "analogin_api.h"
+#include "cy_sar.h"
+#include "psoc6_utils.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "platform/mbed_error.h"
+
+#if DEVICE_ANALOGIN
+
+const uint16_t ADC_MAX_VALUE = 0x0fff;
+
+const uint32_t SAR_BASE_CLOCK_HZ = 18000000; // 18 MHz or less
+
+/** Default SAR channel configuration.
+ * Notice, that because dynamic SAR MUX switching is disabled,
+ * per-channel MUX configuration is ignored, thus not configured here.
+ */
+#define DEFAULT_CHANNEL_CONFIG ( \
+ CY_SAR_CHAN_SINGLE_ENDED | \
+ CY_SAR_CHAN_AVG_ENABLE | \
+ CY_SAR_CHAN_SAMPLE_TIME_0 \
+)
+
+
+/** Global SAR configuration data, modified as channels are configured.
+ */
+static cy_stc_sar_config_t sar_config = {
+ .ctrl = CY_SAR_VREF_SEL_VDDA_DIV_2 |
+ CY_SAR_NEG_SEL_VREF |
+ CY_SAR_CTRL_COMP_DLY_12 |
+ CY_SAR_COMP_PWR_50 |
+ CY_SAR_SARSEQ_SWITCH_DISABLE, /**< Control register */
+ .sampleCtrl = CY_SAR_RIGHT_ALIGN |
+ CY_SAR_SINGLE_ENDED_UNSIGNED |
+ CY_SAR_AVG_CNT_16 |
+ CY_SAR_AVG_MODE_SEQUENTIAL_FIXED |
+ CY_SAR_TRIGGER_MODE_FW_ONLY, /**< Sample control register */
+ .sampleTime01 = (4uL << CY_SAR_SAMPLE_TIME0_SHIFT) |
+ (4uL << CY_SAR_SAMPLE_TIME1_SHIFT), /**< Sample time in ADC clocks for ST0 and ST1 */
+ .sampleTime23 = (4uL << CY_SAR_SAMPLE_TIME2_SHIFT) |
+ (4uL << CY_SAR_SAMPLE_TIME3_SHIFT), /**< Sample time in ADC clocks for ST2 and ST3 */
+ .rangeThres = 0, /**< Range detect threshold register for all channels (unused)*/
+ .rangeCond = 0, /**< Range detect mode for all channels (unused)*/
+ .chanEn = 0, /**< Enable bits for the channels */
+ .chanConfig = { /**< Channel configuration registers */
+ DEFAULT_CHANNEL_CONFIG, // chn 0
+ DEFAULT_CHANNEL_CONFIG, // chn 1
+ DEFAULT_CHANNEL_CONFIG, // chn 2
+ DEFAULT_CHANNEL_CONFIG, // chn 3
+ DEFAULT_CHANNEL_CONFIG, // chn 4
+ DEFAULT_CHANNEL_CONFIG, // chn 5
+ DEFAULT_CHANNEL_CONFIG, // chn 6
+ DEFAULT_CHANNEL_CONFIG, // chn 7
+ DEFAULT_CHANNEL_CONFIG, // chn 8
+ DEFAULT_CHANNEL_CONFIG, // chn 9
+ DEFAULT_CHANNEL_CONFIG, // chn 10
+ DEFAULT_CHANNEL_CONFIG, // chn 11
+ DEFAULT_CHANNEL_CONFIG, // chn 12
+ DEFAULT_CHANNEL_CONFIG, // chn 13
+ DEFAULT_CHANNEL_CONFIG, // chn 14
+ DEFAULT_CHANNEL_CONFIG, // chn 15
+ },
+ .intrMask = 0, /**< Interrupt enable mask */
+ .satIntrMask = 0, /**< Saturate interrupt mask register */
+ .rangeIntrMask = 0, /**< Range interrupt mask register */
+ .muxSwitch = 0, /**< SARMUX firmware switches to connect analog signals to SAR */
+ .muxSwitchSqCtrl = 0, /**< SARMUX Switch SAR sequencer control */
+ .configRouting = false, /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */
+ .vrefMvValue = 0, /**< Reference voltage in millivolts used in counts to volts conversion */
+};
+
+static bool sar_initialized = false;
+
+
+static void sar_init(analogin_t *obj)
+{
+ if (!sar_initialized) {
+ uint32_t sar_clock_divider = CY_INVALID_DIVIDER;
+
+ sar_initialized = true;
+ // Allocate and setup clock.
+ sar_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
+ if (sar_clock_divider == CY_INVALID_DIVIDER) {
+ error("SAR clock divider allocation failed.");
+ return;
+ }
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
+ sar_clock_divider,
+ ((CY_CLK_PERICLK_FREQ_HZ + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
+ Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
+
+ Cy_SAR_Init(obj->base, &sar_config);
+ Cy_SAR_Enable(obj->base);
+ }
+}
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ uint32_t sar = 0;
+ uint32_t sar_function = 0;
+
+ MBED_ASSERT(obj);
+ MBED_ASSERT(pin != (PinName)NC);
+
+
+ sar = pinmap_peripheral(pin, PinMap_ADC);
+ if (sar != (uint32_t)NC) {
+ if (cy_reserve_io_pin(pin)) {
+ error("ANALOG IN pin reservation conflict.");
+ }
+ obj->base = (SAR_Type*)CY_PERIPHERAL_BASE(sar);
+ obj->pin = pin;
+ obj->channel_mask = 1 << CY_PIN(pin);
+
+ // Configure clock.
+ sar_function = pinmap_function(pin, PinMap_ADC);
+ obj->clock = CY_PIN_CLOCK(sar_function);
+ sar_init(obj);
+ pin_function(pin, sar_function);
+ } else {
+ error("ANALOG IN pinout mismatch.");
+ }
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t result = analogin_read_u16(obj);
+
+ return (float)result * (1.0 / ADC_MAX_VALUE);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint32_t result = 0;
+
+ Cy_SAR_SetChanMask(obj->base, obj->channel_mask);
+ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE);
+ Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_SINGLE_SHOT);
+ if (Cy_SAR_IsEndConversion(obj->base, CY_SAR_WAIT_FOR_RESULT) == CY_SAR_SUCCESS) {
+ result = Cy_SAR_GetResult32(obj->base, CY_PIN(obj->pin));
+ } else {
+ error("ANALOG IN: measurement failed!");
+ }
+ Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN);
+ // We are running 16x oversampling extending results to 16 bits.
+ return (uint16_t)(result);
+}
+
+#endif // DEVICE_ANALOGIN
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,150 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "analogout_api.h"
+#include "cy_ctdac.h"
+#include "psoc6_utils.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "platform/mbed_error.h"
+
+#if DEVICE_ANALOGOUT
+
+#define CTDAC_NUM_BITS 12
+const uint16_t CTDAC_MAX_VALUE = (uint16_t)((1UL << CTDAC_NUM_BITS) - 1);
+
+const uint32_t CTDAC_BASE_CLOCK_HZ = 500000; // 500 kHz or less
+
+#define CTDAC_DEGLITCH_CYCLES 35
+
+
+
+/** Global CTDAC configuration data.
+ */
+static cy_stc_ctdac_config_t ctdac_config = {
+ .refSource = CY_CTDAC_REFSOURCE_VDDA, /**< Reference source: Vdda or externally through Opamp1 of CTB */
+ .formatMode = CY_CTDAC_FORMAT_UNSIGNED, /**< Format of DAC value: signed or unsigned */
+ .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE, /**< Update mode: direct or buffered writes or hardware, edge or level */
+ .deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED, /**< Deglitch mode: disabled, buffered, unbuffered, or both */
+ .outputMode = CY_CTDAC_OUTPUT_VALUE, /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */
+ .outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED, /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */
+ .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE, /**< Enable or disable the CTDAC during Deep Sleep */
+ .deglitchCycles = CTDAC_DEGLITCH_CYCLES, /**< Number of deglitch cycles from 0 to 63 */
+ .value = 0, /**< Current DAC value */
+ .nextValue = 0, /**< Next DAC value for double buffering */
+ .enableInterrupt = false, /**< If true, enable interrupt when next value register is transferred to value register */
+ .configClock = false, /**< Configure or ignore clock information */
+};
+
+
+static bool ctdac_initialized = 0;
+
+static void ctdac_init(dac_t *obj)
+{
+ if (!ctdac_initialized) {
+ uint32_t dac_clock_divider = CY_INVALID_DIVIDER;
+
+ ctdac_initialized = true;
+ // Allocate and setup clock.
+ dac_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
+ if (dac_clock_divider == CY_INVALID_DIVIDER) {
+ error("CTDAC clock divider allocation failed.");
+ return;
+ }
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
+ dac_clock_divider,
+ ((CY_CLK_PERICLK_FREQ_HZ + CTDAC_BASE_CLOCK_HZ / 2) / CTDAC_BASE_CLOCK_HZ) - 1);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
+ Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, dac_clock_divider);
+
+ Cy_CTDAC_Init(obj->base, &ctdac_config);
+ Cy_CTDAC_Enable(obj->base);
+ }
+}
+
+
+void analogout_init(dac_t *obj, PinName pin)
+{
+ uint32_t dac = 0;
+ uint32_t dac_function = 0;
+
+ MBED_ASSERT(obj);
+ MBED_ASSERT(pin != (PinName)NC);
+
+ dac = pinmap_peripheral(pin, PinMap_DAC);
+ if (dac != (uint32_t)NC) {
+ if (cy_reserve_io_pin(pin)) {
+ error("ANALOG OUT pin reservation conflict.");
+ }
+ obj->base = (CTDAC_Type*)CY_PERIPHERAL_BASE(dac);
+ obj->pin = pin;
+
+ // Configure clock.
+ dac_function = pinmap_function(pin, PinMap_DAC);
+ obj->clock = CY_PIN_CLOCK(dac_function);
+ pin_function(pin, dac_function);
+ ctdac_init(obj);
+ } else {
+ error("ANALOG OUT pinout mismatch.");
+ }
+}
+
+void analogout_free(dac_t *obj)
+{
+ // Not supported yet.
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+ uint32_t val = 0;
+
+ if (value > 1.0) {
+ val = CTDAC_MAX_VALUE;
+ } else if (value > 0.0) {
+ val = value * CTDAC_MAX_VALUE;
+ }
+ Cy_CTDAC_SetValueBuffered(obj->base, val);
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+ uint32_t val = 0;
+
+ val = (value >> (16 - CTDAC_NUM_BITS)); // Convert from 16-bit range.
+
+ Cy_CTDAC_SetValueBuffered(obj->base, val);
+}
+
+float analogout_read(dac_t *obj)
+{
+ return (float)analogout_read_u16(obj) / 0xffff;
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+ uint16_t value = (obj->base->CTDAC_VAL_NXT >> CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk;
+
+ value <<= (16 - CTDAC_NUM_BITS); // Convert to 16-bit range.
+
+ return value;
+}
+
+#endif // DEVICE_ANALOGIN
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/PDL_Version.txt Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,2 @@ +version 3.0.1 +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1355 @@
+/***************************************************************************//**
+* \file cy_ctb.c
+* \version 1.0
+*
+* \brief
+* Provides the public functions for the CTB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "ctb/cy_ctb.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Fast Config Selections
+***************************************/
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused =
+{
+ /*.oa0Power */ CY_CTB_POWER_OFF,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_COMP,
+ /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa0SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_POS_PIN0_MASK | (uint32_t) CY_CTB_SW_OA0_NEG_PIN1_MASK,
+ /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK,
+ /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK,
+};
+
+const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH =
+{
+ /*.oa0Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa0Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK,
+ /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused =
+{
+ /*.oa1Power */ CY_CTB_POWER_OFF,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_COMP,
+ /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa1SwitchCtrl */ CY_CTB_DEINIT,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP10X,
+ /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_POS_PIN7_MASK | (uint32_t) CY_CTB_SW_OA1_NEG_PIN4_MASK,
+ /*.ctdSwitchCtrl */ CY_CTB_DEINIT,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_AREF_MASK,
+ /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK,
+};
+
+const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 =
+{
+ /*.oa1Power */ CY_CTB_POWER_MEDIUM,
+ /*.oa1Mode */ CY_CTB_MODE_OPAMP1X,
+ /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_PIN5_MASK,
+ /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK,
+};
+
+/*******************************************************************************
+* Function Name: Cy_CTB_Init
+****************************************************************************//**
+*
+* Initialize or restore the CTB and both opamps according to the
+* provided settings. Parameters are usually set only once, at initialization.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param config
+* Pointer to structure containing configuration data for entire CTB
+*
+* \return
+* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
+*
+* \funcusage
+*
+* The following code snippet configures Opamp0 as a comparator
+* and Opamp1 as an opamp follower with 10x drive. The terminals
+* are routed to external pins by closing the switches shown.
+*
+* \image html ctb_init_funcusage.png
+* \image latex ctb_init_funcusage.png
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_CTBINIT
+*
+*******************************************************************************/
+cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_ctb_status_t result;
+
+ if ((NULL == base) || (NULL == config))
+ {
+ result = CY_CTB_BAD_PARAM;
+ }
+ else
+ {
+ CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep));
+
+ /* Enum checks for Opamp0 config */
+ CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power));
+ CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode));
+ CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump));
+ CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge));
+ CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel));
+ CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass));
+ CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa0CompHyst));
+
+ /* Enum checks for Opamp0 config */
+ CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa1Power));
+ CY_ASSERT_L3(CY_CTB_OAMODE(config->oa1Mode));
+ CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa1Pump));
+ CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa1CompEdge));
+ CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa1CompLevel));
+ CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa1CompBypass));
+ CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa1CompHyst));
+
+ /* Boundary checks for analog routing switch masks */
+ CY_ASSERT_L2(CY_CTB_OA0SWITCH(config->oa0SwitchCtrl));
+ CY_ASSERT_L2(CY_CTB_OA1SWITCH(config->oa1SwitchCtrl));
+ CY_ASSERT_L2(CY_CTB_CTDSWITCH(config->ctdSwitchCtrl));
+
+ base->CTB_CTRL = (uint32_t) config->deepSleep;
+ base->OA_RES0_CTRL = (uint32_t) config->oa0Power \
+ | (uint32_t) config->oa0Mode \
+ | (uint32_t) config->oa0Pump \
+ | (uint32_t) config->oa0CompEdge \
+ | (uint32_t) config->oa0CompLevel \
+ | (uint32_t) config->oa0CompBypass \
+ | (uint32_t) config->oa0CompHyst \
+ | ((CY_CTB_MODE_OPAMP1X == config->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
+
+ base->OA_RES1_CTRL = (uint32_t) config->oa1Power \
+ | (uint32_t) config->oa1Mode \
+ | (uint32_t) config->oa1Pump \
+ | (uint32_t) config->oa1CompEdge \
+ | (uint32_t) config->oa1CompLevel \
+ | (uint32_t) config->oa1CompBypass \
+ | (uint32_t) config->oa1CompHyst \
+ | ((CY_CTB_MODE_OPAMP1X == config->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
+
+ base->INTR_MASK = (config->oa0CompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT) \
+ | (config->oa1CompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT);
+
+ base->OA0_COMP_TRIM = (uint32_t) ((config->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+ base->OA1_COMP_TRIM = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+
+ if (config->configRouting)
+ {
+ base->OA0_SW = config->oa0SwitchCtrl;
+ base->OA1_SW = config->oa1SwitchCtrl;
+ base->CTD_SW = config->ctdSwitchCtrl;
+ }
+
+ result = CY_CTB_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpampInit
+****************************************************************************//**
+*
+* Initialize each opamp separately without impacting analog routing.
+* Intended for use by automatic analog routing and configuration tools
+* to configure each opamp without having to integrate the settings with
+* those of the other opamp first.
+*
+* Can also be used to configure both opamps to have the same settings.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param config
+* Pointer to structure containing configuration data
+*
+* \return
+* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_OPAMPINIT
+*
+*******************************************************************************/
+cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_ctb_status_t result;
+ uint32_t oaResCtrl;
+
+ if ((NULL == base) || (NULL == config))
+ {
+ result = CY_CTB_BAD_PARAM;
+ }
+ else
+ {
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
+ CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep));
+ CY_ASSERT_L3(CY_CTB_OAPOWER(config->oaPower));
+ CY_ASSERT_L3(CY_CTB_OAMODE(config->oaMode));
+ CY_ASSERT_L3(CY_CTB_OAPUMP(config->oaPump));
+ CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oaCompEdge));
+ CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oaCompLevel));
+ CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass));
+ CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst));
+
+ base->CTB_CTRL = (uint32_t) config->deepSleep;
+
+ /* The two opamp control registers are symmetrical */
+ oaResCtrl = (uint32_t) config->oaPower \
+ | (uint32_t) config->oaMode \
+ | (uint32_t) config->oaPump \
+ | (uint32_t) config->oaCompEdge \
+ | (uint32_t) config->oaCompLevel \
+ | (uint32_t) config->oaCompBypass \
+ | (uint32_t) config->oaCompHyst \
+ | ((CY_CTB_MODE_OPAMP1X == config->oaMode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
+
+ if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA_RES0_CTRL = oaResCtrl;
+ base->OA0_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+
+ /* The INTR_MASK register is shared between the two opamps */
+ base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT);
+ }
+
+ if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA_RES1_CTRL = oaResCtrl;
+ base->OA1_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+
+ /* The INTR_MASK register is shared between the two opamps */
+ base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT);
+ }
+
+ result = CY_CTB_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_DeInit
+****************************************************************************//**
+*
+* Reset CTB registers back to power on reset defaults.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deInitRouting
+* If true, all analog routing switches are reset to their default state.
+* If false, analog switch registers are untouched.
+*
+* \return
+* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting)
+{
+ CY_ASSERT_L1(NULL != base);
+
+ cy_en_ctb_status_t result;
+
+ if (NULL == base)
+ {
+ result = CY_CTB_BAD_PARAM;
+ }
+ else
+ {
+ base->CTB_CTRL = CY_CTB_DEINIT;
+ base->OA_RES0_CTRL = CY_CTB_DEINIT;
+ base->OA_RES1_CTRL = CY_CTB_DEINIT;
+ base->INTR_MASK = CY_CTB_DEINIT;
+
+ if (deInitRouting)
+ {
+ base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW;
+ base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW;
+ base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW;
+ }
+
+ result = CY_CTB_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_FastInit
+****************************************************************************//**
+*
+* Initialize each opamp of the CTB to one of the common use modes.
+*
+* This function provides a quick and easy method of configuring the CTB
+* using pre-defined configurations.
+* Only routing switches required for the selected mode are configured, leaving final input and output connections
+* to the user.
+* Additional use modes that relate to the \ref group_ctdac "CTDAC"
+* are provided to support easy configuration of the CTDAC output buffer and input
+* reference buffer.
+*
+* The fast configuration structures define the opamp power, mode, and routing.
+* This function sets the other configuration options of the CTB to:
+* - .deepSleep = CY_CTB_DEEPSLEEP_DISABLE
+* - .oaPump = \ref CY_CTB_PUMP_ENABLE
+* - .oaCompEdge = \ref CY_CTB_COMP_EDGE_BOTH
+* - .oaCompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
+* - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
+* - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV
+* - .oaCompIntrEn = true
+
+* \param base
+* Pointer to structure describing registers
+*
+* \param config0
+* Pointer to structure containing configuration data for quick initialization
+* of Opamp0. Defined your own or use one of the provided structures:
+* - \ref Cy_CTB_Fast_Opamp0_Unused
+* - \ref Cy_CTB_Fast_Opamp0_Comp
+* - \ref Cy_CTB_Fast_Opamp0_Opamp1x
+* - \ref Cy_CTB_Fast_Opamp0_Opamp10x
+* - \ref Cy_CTB_Fast_Opamp0_Diffamp
+* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out
+* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH
+*
+* \param config1
+* Pointer to structure containing configuration data for quick initialization
+* of Opamp1. Defined your own or use one of the provided structures:
+* - \ref Cy_CTB_Fast_Opamp1_Unused
+* - \ref Cy_CTB_Fast_Opamp1_Comp
+* - \ref Cy_CTB_Fast_Opamp1_Opamp1x
+* - \ref Cy_CTB_Fast_Opamp1_Opamp10x
+* - \ref Cy_CTB_Fast_Opamp1_Diffamp
+* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref
+* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
+*
+* \return
+* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_FASTINIT
+*
+*******************************************************************************/
+cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config0);
+ CY_ASSERT_L1(NULL != config1);
+
+ cy_en_ctb_status_t result;
+
+ if ((NULL == base) || (NULL == config0) || (NULL == config1))
+ {
+ result = CY_CTB_BAD_PARAM;
+ }
+ else
+ {
+ /* Enum and boundary checks for config0 */
+ CY_ASSERT_L3(CY_CTB_OAPOWER(config0->oa0Power));
+ CY_ASSERT_L3(CY_CTB_OAMODE(config0->oa0Mode));
+ CY_ASSERT_L2(CY_CTB_OA0SWITCH(config0->oa0SwitchCtrl));
+ CY_ASSERT_L2(CY_CTB_CTDSWITCH(config0->ctdSwitchCtrl));
+
+ /* Enum and boundary checks for config1 */
+ CY_ASSERT_L3(CY_CTB_OAPOWER(config1->oa1Power));
+ CY_ASSERT_L3(CY_CTB_OAMODE(config1->oa1Mode));
+ CY_ASSERT_L2(CY_CTB_OA1SWITCH(config1->oa1SwitchCtrl));
+ CY_ASSERT_L2(CY_CTB_CTDSWITCH(config1->ctdSwitchCtrl));
+
+ base->CTB_CTRL = (uint32_t) CY_CTB_DEEPSLEEP_DISABLE;
+
+ base->OA_RES0_CTRL = (uint32_t) config0->oa0Power \
+ | (uint32_t) config0->oa0Mode \
+ | (uint32_t) CY_CTB_PUMP_ENABLE \
+ | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
+ | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
+ | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
+ | (uint32_t) CY_CTB_COMP_HYST_10MV \
+ | ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
+
+ base->OA_RES1_CTRL = (uint32_t) config1->oa1Power \
+ | (uint32_t) config1->oa1Mode \
+ | (uint32_t) CY_CTB_PUMP_ENABLE \
+ | (uint32_t) CY_CTB_COMP_EDGE_BOTH \
+ | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \
+ | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \
+ | (uint32_t) CY_CTB_COMP_HYST_10MV \
+ | ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE);
+
+ base->INTR_MASK = CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk;
+
+ base->OA0_COMP_TRIM = (uint32_t) ((config0->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+ base->OA1_COMP_TRIM = (uint32_t) ((config1->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+
+ base->OA0_SW = config0->oa0SwitchCtrl;
+ base->OA1_SW = config1->oa1SwitchCtrl;
+ base->CTD_SW = config0->ctdSwitchCtrl | config1->ctdSwitchCtrl;
+
+ result = CY_CTB_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetCurrentMode
+****************************************************************************//**
+*
+* High level function to configure the current modes of the opamps.
+* This function configures all opamps of the CTB to the same current mode.
+* These modes are differentiated by the reference current level, the opamp
+* input range, and the Deep Sleep mode operation.
+*
+* - The reference current level is set using \ref Cy_CTB_SetIptatLevel
+* - When 1 uA current level is used in Deep Sleep,
+* - All generators in the AREF must be enabled in Deep Sleep. That is,
+* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
+* - When 100 nA current level is used,
+* - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference
+* to the opamp IZTAT and disable the opamps IPTAT.
+* - The IPTAT generator is enabled in Deep Sleep. That is,
+* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2
+* unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
+*
+* \note
+* The IPTAT level is a chip wide configuration so multiple
+* opamps cannot operate at different IPTAT levels.
+* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
+* it should be called for all other CTB instances as well.
+*
+* <table class="doxtable">
+* <tr>
+* <th>Current Mode</th>
+* <th>IPTAT Level</th>
+* <th>Input Range</th>
+* <th>Deep Sleep Operation</th>
+* </tr>
+* <tr>
+* <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE</td>
+* <td>1 uA</td>
+* <td>Rail-to-Rail (charge pump enabled)</td>
+* <td>Disabled in Deep Sleep</td>
+* </tr>
+* <tr>
+* <td>\ref CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP</td>
+* <td>1 uA</td>
+* <td>0 - VDDA-1.5 V (charge pump disabled)</td>
+* <td>Enabled in Deep Sleep</td>
+* </tr>
+* <tr>
+* <td>\ref CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP</td>
+* <td>100 nA</td>
+* <td>0 - VDDA-1.5 V (charge pump disabled)</td>
+* <td>Enabled in Deep Sleep</td>
+* </tr>
+* </table>
+*
+* \note
+* The output range of the opamp is 0.2 V to VDDA - 0.2 V (depending on output load).
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param currentMode
+* Current mode selection
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CURRENT_MODE
+*
+*******************************************************************************/
+void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode)
+{
+ CY_ASSERT_L3(CY_CTB_CURRENTMODE(currentMode));
+
+ cy_en_sysanalog_deep_sleep_t arefDeepSleep;
+
+ switch(currentMode)
+ {
+ case CY_CTB_CURRENT_HIGH_ACTIVE:
+
+ /* Does not disable AREF for Deep Sleep in case the AREF is used by other blocks */
+
+ /* Use a 1 uA IPTAT level and disable redirection */
+ Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
+ Cy_CTB_DisableRedirect();
+
+ /* Disable Deep Sleep mode for the CTB - not opamp specific */
+ Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE);
+
+ /* Enable Opamp0 pump */
+ base->OA_RES0_CTRL |= CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
+
+ /* Enable Opamp1 pump */
+ base->OA_RES1_CTRL |= CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
+
+ break;
+ case CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP:
+
+ /* All generators (IPTAT, IZTAT, and VREF) of the AREF block must be enabled for Deep Sleep */
+ Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF);
+
+ /* Use a 1 uA IPTAT level and disable redirection */
+ Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL);
+ Cy_CTB_DisableRedirect();
+
+ /* Enable Deep Sleep mode for the CTB - not opamp specific */
+ Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
+
+ /* Disable Opamp0 pump */
+ base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
+
+ /* Disable Opamp1 pump */
+ base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
+
+ break;
+ case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP:
+ default:
+
+ /* The AREF IPTAT output for the opamps must be enabled in Deep Sleep.
+ * This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */
+ arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode();
+ if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1))
+ {
+ Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_2);
+ }
+
+ /* Use a 100 nA IPTAT level and enable redirection */
+ Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW);
+ Cy_CTB_EnableRedirect();
+
+ /* Enable Deep Sleep mode for the CTB - not opamp specific */
+ Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE);
+
+ /* Disable Opamp0 pump */
+ base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk;
+
+ /* Disable Opamp1 pump */
+ base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetDeepSleepMode
+****************************************************************************//**
+*
+* Enable or disable the entire CTB (not per opamp) in Deep Sleep mode.
+*
+* If enabled, the AREF block must also be enabled for Deep Sleep to provide
+* the needed reference currents to the opamps (see \ref Cy_SysAnalog_SetDeepSleepMode).
+* Additionally, ensure that only internal CTB switches are used for routing.
+* Switches on AMUXBUSA and AMUXBUSB are not enabled in Deep Sleep.
+* See the \ref group_ctb_dependencies section for more information.
+*
+* \note
+* In Deep Sleep mode, the charge pumps are disabled so the input
+* range of the opamps is reduced to 0 V to VDDA - 1.5 V.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deepSleep
+* \ref CY_CTB_DEEPSLEEP_DISABLE or \ref CY_CTB_DEEPSLEEP_ENABLE from
+* \ref cy_en_ctb_deep_sleep_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_DEEPSLEEP_MODE
+*
+*******************************************************************************/
+void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep)
+{
+ CY_ASSERT_L3(CY_CTB_DEEPSLEEP(deepSleep));
+
+ uint32_t ctbCtrl;
+
+ ctbCtrl = base->CTB_CTRL & ~CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk;
+
+ base->CTB_CTRL = ctbCtrl | (uint32_t)deepSleep;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetOutputMode
+****************************************************************************//**
+*
+* Set the opamp output mode to 1x drive, 10x drive, or comparator mode.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param mode
+* Opamp mode selection. Select a value from \ref cy_en_ctb_mode_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OUTPUT_MODE
+*
+*******************************************************************************/
+void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
+ CY_ASSERT_L3(CY_CTB_OAMODE(mode));
+
+ uint32_t oaCtrlReg;
+
+ if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+
+ /* Clear the three affected bits before setting them */
+ oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk | CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk);
+ base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE);
+ base->OA0_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+ }
+
+ if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk | CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk);
+ base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE);
+ base->OA1_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN);
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetPower
+****************************************************************************//**
+*
+* Configure the power level and charge pump for a specific opamp.
+*
+* At higher power levels, the opamp consumes more current but provides more
+* gain bandwidth.
+* Enabling the charge pump increases current but provides
+* rail-to-rail input range. Disabling the charge pump limits the input range to
+* VDDA - 1.5 V.
+* See the device datasheet for performance specifications.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param power
+* Power mode selection. Select a value from \ref cy_en_ctb_power_t.
+*
+* \param pump
+* Enable or disable the charge pump. Select a value from \ref cy_en_ctb_pump_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_POWER
+*
+*******************************************************************************/
+void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
+ CY_ASSERT_L3(CY_CTB_OAPOWER(power));
+ CY_ASSERT_L3(CY_CTB_OAPUMP(pump));
+
+ uint32_t oaCtrlReg;
+
+ if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+
+ /* Clear the two affected bits before setting them */
+ oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk | CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk);
+ base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump;
+ }
+
+ if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk | CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk);
+ base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_DACSampleAndHold
+****************************************************************************//**
+*
+* Perform sampling and holding of the CTDAC output.
+* To perform a sample or a hold, a preparation step must first be executed to
+* open the required switches. Because of this, each sample or hold
+* requires three function calls:
+*
+* -# Call this function to prepare for a sample or hold
+* -# Enable or disable the CTDAC output
+* -# Call this function again to perform a sample or hold
+*
+* It takes 10 us to perform a sample of the CTDAC output to provide
+* time for the capacitor to settle to the new value.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param mode
+* Mode to prepare or perform a sample or hold, or disable the ability
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SAMPLE_CODE_SNIPPET
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_HOLD_CODE_SNIPPET
+*
+*******************************************************************************/
+void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode)
+{
+ CY_ASSERT_L3(CY_CTB_SAMPLEHOLD(mode));
+
+ switch(mode)
+ {
+ case CY_CTB_SH_DISABLE:
+ base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK /* Open ILR switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Open CHD switch */
+ base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */
+ break;
+ case CY_CTB_SH_PREPARE_SAMPLE:
+ base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Open ILR switch */
+ base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Close CHD switch */
+ break;
+ case CY_CTB_SH_SAMPLE:
+ base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */
+ break;
+ case CY_CTB_SH_PREPARE_HOLD:
+ base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK /* Open COS switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK; /* Open CIS switch */
+ break;
+ case CY_CTB_SH_HOLD:
+ default:
+ base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Close COB switch to reduce leakage through COS switch */
+ | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Close ILR switch to reduce leakage through CIS switch */
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpampSetOffset
+****************************************************************************//**
+*
+* Override the CTB opamp offset factory trim.
+* The trim is a six bit value and the MSB is a direction bit.
+*
+* <table class="doxtable">
+* <tr>
+* <th>Bit 5</th>
+* <th>Bits 4:0</th>
+* <th>Note</th>
+* </tr>
+* <tr>
+* <td>0</td>
+* <td>00000</td>
+* <td>Negative trim direction - minimum setting</td>
+* </tr>
+* <tr>
+* <td>0</td>
+* <td>11111</td>
+* <td>Negative trim direction - maximum setting</td>
+* </tr>
+* <tr>
+* <td>1</td>
+* <td>00000</td>
+* <td>Positive trim direction - minimum setting</td>
+* </tr>
+* <tr>
+* <td>1</td>
+* <td>11111</td>
+* <td>Positive trim direction - maximum setting</td>
+* </tr>
+* </table>
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param trim
+* Trim value from 0 to 63
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OFFSET_TRIM
+*
+*******************************************************************************/
+void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
+ CY_ASSERT_L2(CY_CTB_TRIM(trim));
+
+ if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA0_OFFSET_TRIM = (trim << CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos) & CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk;
+ }
+
+ if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA1_OFFSET_TRIM = (trim << CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos) & CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpampGetOffset
+****************************************************************************//**
+*
+* Return the current CTB opamp offset trim value.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
+*
+* \return Offset trim value
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_OFFSET_TRIM
+*
+*******************************************************************************/
+uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum));
+
+ uint32_t trimReg;
+
+ if (opampNum == CY_CTB_OPAMP_0)
+ {
+ trimReg = base->OA0_OFFSET_TRIM;
+ }
+ else
+ {
+ trimReg = base->OA1_OFFSET_TRIM;
+ }
+
+ return trimReg;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpampSetSlope
+****************************************************************************//**
+*
+* Override the CTB opamp slope factory trim.
+* The offset of the opamp will vary across temperature.
+* This trim compensates for the slope of the offset across temperature.
+* This compensation uses a bias current from the Analaog Reference block.
+* To disable it, set the trim to 0.
+*
+* The trim is a six bit value and the MSB is a direction bit.
+*
+* <table class="doxtable">
+* <tr>
+* <th>Bit 5</th>
+* <th>Bits 4:0</th>
+* <th>Note</th>
+* </tr>
+* <tr>
+* <td>0</td>
+* <td>00000</td>
+* <td>Negative trim direction - minimum setting</td>
+* </tr>
+* <tr>
+* <td>0</td>
+* <td>11111</td>
+* <td>Negative trim direction - maximum setting</td>
+* </tr>
+* <tr>
+* <td>1</td>
+* <td>00000</td>
+* <td>Positive trim direction - minimum setting</td>
+* </tr>
+* <tr>
+* <td>1</td>
+* <td>11111</td>
+* <td>Positive trim direction - maximum setting</td>
+* </tr>
+* </table>
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param trim
+* Trim value from 0 to 63
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_SLOPE_TRIM
+*
+*******************************************************************************/
+void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum));
+ CY_ASSERT_L2(CY_CTB_TRIM(trim));
+
+ if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA0_SLOPE_OFFSET_TRIM = (trim << CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk;
+ }
+
+ if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH))
+ {
+ base->OA1_SLOPE_OFFSET_TRIM = (trim << CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpampGetSlope
+****************************************************************************//**
+*
+* Return the CTB opamp slope trim value.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param opampNum
+* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
+*
+* \return Slope trim value
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_SLOPE_TRIM
+*
+*******************************************************************************/
+uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum));
+
+ uint32_t trimReg;
+
+ if (opampNum == CY_CTB_OPAMP_0)
+ {
+ trimReg = base->OA0_SLOPE_OFFSET_TRIM;
+ }
+ else
+ {
+ trimReg = base->OA1_SLOPE_OFFSET_TRIM;
+ }
+
+ return trimReg;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetAnalogSwitch
+****************************************************************************//**
+*
+* Provide firmware control of the CTB switches. Each call to this function
+* can open a set of switches or close a set of switches in one register.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchSelect
+* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch
+* register
+*
+* \param switchMask
+* The mask of the switches to either open or close.
+* The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t,
+* \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
+* Use the enum that is consistent with the provided register.
+*
+* \param state
+* \ref CY_CTB_SWITCH_OPEN or \ref CY_CTB_SWITCH_CLOSE
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH
+*
+*******************************************************************************/
+void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state)
+{
+ CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect));
+ CY_ASSERT_L2(CY_CTB_SWITCHMASK(switchSelect, switchMask));
+ CY_ASSERT_L3(CY_CTB_SWITCHSTATE(state));
+
+ __IOM uint32_t *switchReg;
+ __IOM uint32_t *switchClearReg;
+
+ switch(switchSelect)
+ {
+ case CY_CTB_SWITCH_OA0_SW:
+ switchReg = &base->OA0_SW;
+ switchClearReg = &base->OA0_SW_CLEAR;
+ break;
+ case CY_CTB_SWITCH_OA1_SW:
+ switchReg = &base->OA1_SW;
+ switchClearReg = &base->OA1_SW_CLEAR;
+ break;
+ case CY_CTB_SWITCH_CTD_SW:
+ default:
+ switchReg = &base->CTD_SW;
+ switchClearReg = &base->CTD_SW_CLEAR;
+ break;
+ }
+
+ switch(state)
+ {
+ case CY_CTB_SWITCH_CLOSE:
+ *switchReg = switchMask;
+ break;
+ case CY_CTB_SWITCH_OPEN:
+ default:
+ *switchClearReg = switchMask;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_GetAnalogSwitch
+****************************************************************************//**
+*
+* Return the open or closed state of the specified analog switch.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchSelect
+* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch
+* register
+*
+* \return
+* The state of the switches in the provided register.
+* Compare this value to the switch masks in the following enums:
+* \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t.
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_ANALOG_SWITCH
+*
+*******************************************************************************/
+uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect)
+{
+ CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect));
+
+ uint32_t switchRegValue;
+
+ switch(switchSelect)
+ {
+ case CY_CTB_SWITCH_OA0_SW:
+ switchRegValue = base->OA0_SW;
+ break;
+ case CY_CTB_SWITCH_OA1_SW:
+ switchRegValue = base->OA1_SW;
+ break;
+ case CY_CTB_SWITCH_CTD_SW:
+ default:
+ switchRegValue = base->CTD_SW;
+ break;
+ }
+
+ return switchRegValue;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_CompSetConfig
+****************************************************************************//**
+*
+* Configure the CTB comparator for pulse or level output, to bypass clock
+* synchronization, and to enable hysteresis.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param level
+* Configure output to produce a pulse or level output signal
+
+* \param bypass
+* Configure output to be clock synchronized or unsynchronized
+
+* \param hyst
+* Enable or disable input hysteresis
+
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_CONFIG
+*
+*******************************************************************************/
+void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+ CY_ASSERT_L3(CY_CTB_COMPLEVEL(level));
+ CY_ASSERT_L3(CY_CTB_COMPBYPASS(bypass));
+ CY_ASSERT_L3(CY_CTB_COMPHYST(hyst));
+
+ uint32_t opampCtrlReg;
+
+ if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH))
+ {
+ opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk);
+ base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst;
+ }
+
+ if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH))
+ {
+ opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk);
+ base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_CompGetConfig
+****************************************************************************//**
+*
+* Return the CTB comparator operating configuration as set by \ref Cy_CTB_CompSetConfig.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1
+*
+* \return
+* The comparator configuration.
+* Compare the register value with the masks in \ref cy_en_ctb_comp_level_t,
+* \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t.
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_CONFIG
+*
+*******************************************************************************/
+uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum));
+
+ uint32_t config;
+
+ if (compNum == CY_CTB_OPAMP_0)
+ {
+ config = base->OA_RES0_CTRL & (CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk);
+ }
+ else
+ {
+ config = base->OA_RES1_CTRL & (CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk);
+ }
+
+ return config;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_CompSetInterruptEdgeType
+****************************************************************************//**
+*
+* Configure the type of edge that will trigger a comparator interrupt.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \param edge
+* Edge type that will trigger an interrupt. Select a value from \ref cy_en_ctb_comp_edge_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_INTERRUPT_EDGE_TYPE
+*
+*******************************************************************************/
+void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+ CY_ASSERT_L3(CY_CTB_COMPEDGE(edge));
+
+ uint32_t opampCtrlReg;
+
+ if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH))
+ {
+ opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk);
+ base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) edge;
+ }
+
+ if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH))
+ {
+ opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk);
+ base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) edge;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_CompGetStatus
+****************************************************************************//**
+*
+* Return the comparator output status.
+* When the positive input voltage is greater than the negative input voltage,
+* the comparator status is high. Otherwise, the status is low.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1.
+* \ref CY_CTB_OPAMP_NONE and \ref CY_CTB_OPAMP_BOTH are invalid options.
+*
+* \return
+* The comparator status.
+* A value of 0 is returned if compNum is invalid.
+* - 0: Status is low
+* - 1: Status is high
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_STATUS
+*
+*******************************************************************************/
+uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum));
+
+ uint32_t compStatusResult;
+
+ if (CY_CTB_OPAMP_0 == compNum)
+ {
+ compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA0_COMP_Msk) >> CTBM_COMP_STAT_OA0_COMP_Pos;
+ }
+ else if (CY_CTB_OPAMP_1 == compNum)
+ {
+ compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA1_COMP_Msk) >> CTBM_COMP_STAT_OA1_COMP_Pos;
+ }
+ else
+ {
+ compStatusResult = 0uL;
+ }
+
+ return compStatusResult;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1508 @@
+/***************************************************************************//**
+* \file cy_ctb.h
+* \version 1.0
+*
+* Header file for the CTB driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_ctb Continuous Time Block (CTB)
+* \{
+* This driver provides API functions to configure and use the analog CTB.
+* The CTB comprises two identical opamps, a switch routing matrix,
+* and a sample and hold (SH) circuit. The high level features are:
+*
+* - Two highly configurable opamps
+* - Each opamp has programmable power and output drive strength
+* - Each opamp can be configured as a voltage follower using internal routing
+* - Each opamp can be configured as a comparator with optional 10 mV hysteresis
+* - Flexible input and output routing
+* - Works as a buffer or amplifier for SAR ADC inputs
+* - Works as a buffer, amplifier, or sample and hold (SH) for the CTDAC output
+* - Can operate in Deep Sleep power mode
+*
+* Each opamp, marked OA0 and OA1, has one input and three output stages,
+* all of which share the common input stage.
+* Note that only one output stage can be selected at a time.
+* The output stage can operate as a low-drive strength opamp for internal connections (1X), a high-drive strength
+* opamp for driving a device pin (10X), or a comparator.
+*
+* Using the switching matrix, the opamp inputs and outputs
+* can be connected to dedicated general-purpose I/Os or other internal analog
+* blocks. See the device datasheet for the dedicated CTB port.
+*
+* \image html ctb_block_diagram.png "CTB Switch Diagram" width=1000px
+* \image latex ctb_block_diagram.png
+*
+* \section group_ctb_init Initialization and Enable
+*
+* Before enabling the CTB, set up any external components (such as resistors)
+* that are needed for the design. To configure the entire hardware block, call \ref Cy_CTB_Init.
+* The base address of the CTB hardware can be found in the device specific header file.
+* Alternatively, to configure only one opamp without any routing, call \ref Cy_CTB_OpampInit.
+* The driver also provides a \ref Cy_CTB_FastInit function for fast and easy initialization of the CTB
+* based on commonly used configurations. They are pre-defined in the driver as:
+*
+* <b> Opamp0 </b>
+* - \ref Cy_CTB_Fast_Opamp0_Unused
+* - \ref Cy_CTB_Fast_Opamp0_Comp
+* - \ref Cy_CTB_Fast_Opamp0_Opamp1x
+* - \ref Cy_CTB_Fast_Opamp0_Opamp10x
+* - \ref Cy_CTB_Fast_Opamp0_Diffamp
+* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out
+* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH
+*
+* <b> Opamp1 </b>
+* - \ref Cy_CTB_Fast_Opamp1_Unused
+* - \ref Cy_CTB_Fast_Opamp1_Comp
+* - \ref Cy_CTB_Fast_Opamp1_Opamp1x
+* - \ref Cy_CTB_Fast_Opamp1_Opamp10x
+* - \ref Cy_CTB_Fast_Opamp1_Diffamp
+* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref
+* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
+*
+* After initialization, call \ref Cy_CTB_Enable to enable the hardware.
+*
+* \section group_ctb_io_connections Input/Output Connections
+*
+* The CTB has internal switches to support flexible input and output routing. If these switches
+* have not been configured during initialization, call \ref Cy_CTB_SetAnalogSwitch to
+* make the input and output connections.
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH
+*
+* As shown in the CTB switch diagram, the 10x output of OA0 and OA1 have dedicated
+* connections to Pin 2 and Pin 3, respectively, of the CTB port. If different output
+* connections are required, the other CTB switches and/or AMUXBUX A/B switches can be used.
+*
+* \section group_ctb_comparator Comparator Mode
+*
+* Each opamp can be configured as a comparator. Note that when used as a
+* comparator, the hardware shuts down the 1X and 10X output drivers.
+* Specific to the comparator mode, there is an optional 10 mV input hysteresis
+* and configurable edge detection interrupt handling.
+*
+* - Negative input terminal: This input is usually connected to the reference voltage.
+* - Positive input terminal: This input is usually connected to the voltage that is being compared.
+* - Comparator digital output: This output goes high when the positive input voltage
+* is greater than the negative input voltage.
+*
+* The comparator output can be routed to a pin or other components using HSIOM or trigger muxes.
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_OUT_ROUTING
+*
+* \subsection group_ctb_comparator_handling_interrupts Handling interrupts
+*
+* The comparator output is connected to an edge detector
+* block, which is used to detect the edge (rising, falling, both, or disabled)
+* for interrupt generation.
+*
+* The following code snippet demonstrates how to implement a routine to handle the interrupt.
+* The routine gets called when any comparator on the device generates an interrupt.
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_ISR
+*
+* The following code snippet demonstrates how to configure and enable the interrupt.
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_INTR_SETUP
+*
+* \section group_ctb_opamp_range Opamp Input and Output Range
+*
+* The input range of the opamp can be rail-to-rail if the charge pump is enabled.
+* Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range
+* of the opamp is typically 0.2 V to VDDA - 0.2 V and will depend on the load. See the
+* device datasheet for more detail.
+*
+* <table class="doxtable">
+* <tr>
+* <th>Charge Pump</th>
+* <th>Input Range</th></tr>
+* <th>Output Range</th></tr>
+* <tr>
+* <td>Enabled</td>
+* <td>0 V to VDDA</td>
+* <td>0.2 V to VDDA - 0.2 V</td>
+* </tr>
+* <tr>
+* <td>Disabled</td>
+* <td>0 V to VDDA - 1.5 V</td>
+* <td>0.2 V to VDDA - 0.2 V</td>
+* </tr>
+* </table>
+*
+* \section group_ctb_sample_hold Sample and Hold Mode
+*
+* The CTB has a sample and hold (SH) circuit at the non-inverting input of Opamp0.
+* The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD.
+* Sampling and holding the source voltage is performed
+* by closing and opening appropriate switches in the CTB using firmware.
+* If the SH circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function
+* should be called.
+*
+* \image html ctb_fast_config_vdac_sh.png
+* \image latex ctb_fast_config_vdac_sh.png
+*
+* \section group_ctb_dependencies Configuration Dependencies
+*
+* The CTB relies on other blocks to function properly. The dependencies
+* are documented here.
+*
+* \subsection group_ctb_dependencies_charge_pump Charge Pump Configuration
+*
+* Each opamp of the CTB has a charge pump that when enabled increases the
+* input range to the supply rails. When disabled, the opamp input range is 0 - VDDA - 1.5 V.
+* When enabled, the pump requires a clock.
+* Call the \ref Cy_CTB_SetClkPumpSource function in the \ref group_sysanalog driver to
+* set the clock source for all CTBs. This clock can come from one of two sources:
+*
+* -# A dedicated clock divider from one of the CLK_PATH in the SRSS
+*
+* Call the following functions to configure the pump clock from the SRSS:
+* - \ref Cy_SysClk_ClkPumpSetSource
+* - \ref Cy_SysClk_ClkPumpSetDivider
+* - \ref Cy_SysClk_ClkPumpEnable
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
+*
+* -# One of the Peri Clock dividers
+*
+* Call the following functions to configure a Peri Clock divider as the
+* pump clock:
+* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI
+* - \ref Cy_SysClk_PeriphSetDivider
+* - \ref Cy_SysClk_PeriphEnableDivider
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
+*
+* When the charge pump is enabled, the clock frequency should be set as follows:
+*
+* <table class="doxtable">
+* <tr><th>Opamp Power Level</th><th>Pump Clock Freq</th></tr>
+* <tr>
+* <td>Low or Medium</td>
+* <td>8 - 24 MHz</td>
+* </tr>
+* <tr>
+* <td>High</td>
+* <td>24 MHz</td>
+* </tr>
+* </table>
+*
+* The High power level of the opamp requires a 24 MHz pump clock.
+* In Deep Sleep mode, all high frequency clocks are
+* disabled and the charge pump will be disabled.
+*
+* \note
+* The same pump clock is used by all opamps on the device. Be aware of this
+* when configuring different opamps to different power levels.
+*
+* \subsection group_ctb_dependencies_reference_current Reference Current Configurations
+*
+* The CTB uses two reference current generators, IPTAT and IZTAT, from
+* the AREF block (see \ref group_sysanalog driver). The IPTAT current is
+* used to trim the slope of the opamp offset across temperature.
+* The AREF must be initialized and enabled for the CTB to function properly.
+*
+* If the CTB is configured to operate in Deep Sleep mode,
+* the appropriate reference current generators from the AREF block must be enabled in Deep Sleep.
+* When waking up from Deep Sleep,
+* the AREF block has a wakeup time that must be
+* considered. Note that configurations in the AREF block
+* are chip wide and affect all CTBs on the device.
+*
+* The following reference current configurations are supported:
+*
+* <table class="doxtable">
+* <tr><th>Reference Current Level</th><th>Supported Mode</th><th>Input Range</th></tr>
+* <tr>
+* <td>1 uA</td>
+* <td>Active/Low Power</td>
+* <td>Rail-to-Rail (charge pump enabled)</td>
+* </tr>
+* <tr>
+* <td>1 uA</td>
+* <td>Active/Low Power/Deep Sleep</td>
+* <td>0 - VDDA-1.5 V (charge pump disabled)</td>
+* </tr>
+* <tr>
+* <td>100 nA</td>
+* <td>Active/Low Power/Deep Sleep</td>
+* <td>0 - VDDA-1.5 V (charge pump disabled)</td>
+* </tr>
+* </table>
+*
+* The first configuration provides low offset and drift with maximum input range
+* while consuming the most current.
+* For Deep Sleep operation, use the other two configurations with the charge pump disabled.
+* For ultra low power, use the 100 nA current level.
+* To configure the opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode.
+*
+* \subsection group_ctb_dependencies_sample_hold Sample and Hold Switch Control
+*
+* If you are using rev-08 of the CY8CKIT-062, the following eight switches
+* in the CTB are enabled by the CTDAC IP block:
+*
+* - COS, CA0, CHD, CH6, COB, COR, CRS, and CRD
+*
+* On the rev-08 board, if any of the above switches are used, you must call \ref Cy_CTDAC_Enable
+* to enable these switches.
+*
+* Additionally, on the rev-08 board, if any of the switches are used in Deep Sleep mode,
+* the CTDAC must also be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode).
+*
+* In later revisions of the board, the switches are enabled by the CTB block so
+* calls to the CTDAC IP block are not necessary.
+*
+* \section group_ctb_more_information More Information
+*
+* Refer to technical reference manual (TRM) and the device datasheet.
+*
+* \section group_ctb_MISRA MISRA-C Compliance]
+*
+* This driver does not have any specific deviations.
+*
+* \section group_ctb_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_ctb_macros Macros
+* \defgroup group_ctb_functions Functions
+* \{
+* \defgroup group_ctb_functions_init Initialization Functions
+* \defgroup group_ctb_functions_basic Basic Configuration Functions
+* \defgroup group_ctb_functions_comparator Comparator Functions
+* \defgroup group_ctb_functions_sample_hold Sample and Hold Functions
+* \defgroup group_ctb_functions_interrupts Interrupt Functions
+* \defgroup group_ctb_functions_switches Switch Control Functions
+* \defgroup group_ctb_functions_trim Offset and Slope Trim Functions
+* \defgroup group_ctb_functions_aref Reference Current Mode Functions
+* \}
+* \defgroup group_ctb_globals Global Variables
+* \defgroup group_ctb_data_structures Data Structures
+* \defgroup group_ctb_enums Enumerated Types
+*/
+
+#if !defined(CY_CTB_H)
+#define CY_CTB_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "sysanalog/cy_sysanalog.h"
+
+#ifndef CY_IP_MXS40PASS_CTB
+ #error "The CTB driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_ctb_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_CTB_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_CTB_DRV_VERSION_MINOR 0
+
+/** CTB driver identifier*/
+#define CY_CTB_ID CY_PDL_DRV_ID(0x0Bu)
+
+/** \cond INTERNAL */
+
+/**< De-init value for most CTB registers */
+#define CY_CTB_DEINIT (0uL)
+
+/**< De-init value for the opamp0 switch control register */
+#define CY_CTB_DEINIT_OA0_SW (CTBM_OA0_SW_CLEAR_OA0P_A00_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0P_A20_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0P_A30_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0M_A11_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0M_A81_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0O_D51_Msk \
+ | CTBM_OA0_SW_CLEAR_OA0O_D81_Msk)
+
+/**< De-init value for the opamp1 switch control register */
+#define CY_CTB_DEINIT_OA1_SW (CTBM_OA1_SW_CLEAR_OA1P_A03_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1P_A13_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1P_A43_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1P_A73_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1M_A22_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1M_A82_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1O_D52_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1O_D62_Msk \
+ | CTBM_OA1_SW_CLEAR_OA1O_D82_Msk)
+
+/**< De-init value for the CTDAC switch control register */
+#define CY_CTB_DEINIT_CTD_SW (CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDS_COR_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDO_COS_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDH_COB_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk \
+ | CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk)
+
+#define CY_CTB_TRIM_VALUE_MAX (63uL)
+
+/**< Macros for conditions used by CY_ASSERT calls */
+
+#define CY_CTB_OPAMPNUM(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1) || ((num) == CY_CTB_OPAMP_BOTH))
+#define CY_CTB_OPAMPNUM_0_1(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1))
+#define CY_CTB_OPAMPNUM_ALL(num) (((num) == CY_CTB_OPAMP_NONE) \
+ || ((num) == CY_CTB_OPAMP_0) \
+ || ((num) == CY_CTB_OPAMP_1) \
+ || ((num) == CY_CTB_OPAMP_BOTH))
+#define CY_CTB_IPTAT(iptat) (((iptat) == CY_CTB_IPTAT_NORMAL) || ((iptat) == CY_CTB_IPTAT_LOW))
+#define CY_CTB_CLKPUMP(clkPump) (((clkPump) == CY_CTB_CLK_PUMP_SRSS) || ((clkPump) == CY_CTB_CLK_PUMP_PERI))
+#define CY_CTB_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTB_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTB_DEEPSLEEP_ENABLE))
+#define CY_CTB_OAPOWER(power) ((power) <= CY_CTB_POWER_HIGH)
+#define CY_CTB_OAMODE(mode) (((mode) == CY_CTB_MODE_OPAMP1X) \
+ || ((mode) == CY_CTB_MODE_OPAMP10X) \
+ || ((mode) == CY_CTB_MODE_COMP))
+#define CY_CTB_OAPUMP(pump) (((pump) == CY_CTB_PUMP_DISABLE) || ((pump) == CY_CTB_PUMP_ENABLE))
+#define CY_CTB_COMPEDGE(edge) (((edge) == CY_CTB_COMP_EDGE_DISABLE) \
+ || ((edge) == CY_CTB_COMP_EDGE_RISING) \
+ || ((edge) == CY_CTB_COMP_EDGE_FALLING) \
+ || ((edge) == CY_CTB_COMP_EDGE_BOTH))
+#define CY_CTB_COMPLEVEL(level) (((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE) || ((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL))
+#define CY_CTB_COMPBYPASS(bypass) (((bypass) == CY_CTB_COMP_BYPASS_SYNC) || ((bypass) == CY_CTB_COMP_BYPASS_NO_SYNC))
+#define CY_CTB_COMPHYST(hyst) (((hyst) == CY_CTB_COMP_HYST_DISABLE) || ((hyst) == CY_CTB_COMP_HYST_10MV))
+#define CY_CTB_CURRENTMODE(mode) (((mode) == CY_CTB_CURRENT_HIGH_ACTIVE) \
+ || ((mode) == CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP) \
+ || ((mode) == CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP))
+#define CY_CTB_SAMPLEHOLD(mode) ((mode) <= CY_CTB_SH_HOLD)
+#define CY_CTB_TRIM(trim) ((trim) <= CY_CTB_TRIM_VALUE_MAX)
+#define CY_CTB_SWITCHSELECT(select) (((select) == CY_CTB_SWITCH_OA0_SW) \
+ || ((select) == CY_CTB_SWITCH_OA1_SW) \
+ || ((select) == CY_CTB_SWITCH_CTD_SW))
+#define CY_CTB_SWITCHSTATE(state) (((state) == CY_CTB_SWITCH_OPEN) || ((state) == CY_CTB_SWITCH_CLOSE))
+#define CY_CTB_OA0SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL)
+#define CY_CTB_OA1SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL)
+#define CY_CTB_CTDSWITCH(mask) (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL)
+#define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) : \
+ (((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) : \
+ (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL)))
+#define CY_CTB_SARSEQCTRL(mask) (((mask) == CY_CTB_SW_SEQ_CTRL_D51_MASK) \
+ || ((mask) == CY_CTB_SW_SEQ_CTRL_D52_D62_MASK) \
+ || ((mask) == CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK))
+
+/** \endcond */
+
+/** \} group_ctb_macros */
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_ctb_enums
+* \{
+*/
+
+/**
+* Most functions allow you to configure a single opamp or both opamps at once.
+* The \ref Cy_CTB_SetInterruptMask function can be called with \ref CY_CTB_OPAMP_NONE
+* and interrupts will be disabled.
+*/
+typedef enum{
+ CY_CTB_OPAMP_NONE = 0, /**< For disabling interrupts for both opamps. Used with \ref Cy_CTB_SetInterruptMask */
+ CY_CTB_OPAMP_0 = CTBM_INTR_COMP0_Msk, /**< For configuring Opamp0 */
+ CY_CTB_OPAMP_1 = CTBM_INTR_COMP1_Msk, /**< For configuring Opamp1 */
+ CY_CTB_OPAMP_BOTH = CTBM_INTR_COMP0_Msk | CTBM_INTR_COMP1_Msk, /**< For configuring both Opamp0 and Opamp1 */
+}cy_en_ctb_opamp_sel_t;
+
+/** Enable or disable CTB while in Deep Sleep mode.
+*/
+typedef enum {
+ CY_CTB_DEEPSLEEP_DISABLE = 0u, /**< CTB is disabled during Deep Sleep power mode */
+ CY_CTB_DEEPSLEEP_ENABLE = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk, /**< CTB remains enabled during Deep Sleep power mode */
+}cy_en_ctb_deep_sleep_t;
+
+/**
+* Configure the power mode of each opamp. Each power setting
+* consumes different levels of current and supports a different
+* input range and gain bandwidth.
+*
+* <table class="doxtable">
+* <tr><th>Opamp Power</th><th>IDD</th><th>Gain bandwidth</th></tr>
+* <tr>
+* <td>OFF</td>
+* <td>0</td>
+* <td>NA</td>
+* </tr>
+* <tr>
+* <td>LOW</td>
+* <td>350 uA</td>
+* <td>1 MHz</td>
+* </tr>
+* <tr>
+* <td>MEDIUM</td>
+* <td>600 uA</td>
+* <td>3 MHz for 1X, 2.5 MHz for 10x</td>
+* </tr>
+* <tr>
+* <td>HIGH</td>
+* <td>1.5 mA</td>
+* <td>8 MHz for 1X, 6 MHz for 10x</td>
+* </tr>
+* </table>
+*
+*/
+typedef enum {
+ CY_CTB_POWER_OFF = 0u, /**< Opamp is off */
+ CY_CTB_POWER_LOW = 1u, /**< Low power: IDD = 350 uA, GBW = 1 MHz for both 1x and 10x */
+ CY_CTB_POWER_MEDIUM = 2u, /**< Medium power: IDD = 600 uA, GBW = 3 MHz for 1x and 2.5 MHz for 10x */
+ CY_CTB_POWER_HIGH = 3u, /**< High power: IDD = 1500 uA, GBW = 8 MHz for 1x and 6 MHz for 10x */
+}cy_en_ctb_power_t;
+
+/**
+* The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits,
+* for high-drive strength (10X) to drive external circuits, or as a comparator.
+*/
+typedef enum {
+ CY_CTB_MODE_OPAMP1X = 0u, /**< Configure opamp for low drive strength for internal connections (1x) */
+ CY_CTB_MODE_OPAMP10X = 1u << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure opamp high drive strength for driving a device pin (10x) */
+ CY_CTB_MODE_COMP = 1u << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure opamp as a comparator */
+}cy_en_ctb_mode_t;
+
+/**
+* Each opamp has a charge pump to increase the input range to the rails.
+* When the charge pump is enabled, the input range is 0 to VDDA.
+* When disabled, the input range is 0 to VDDA - 1.5 V.
+*
+** <table class="doxtable">
+* <tr><th>Charge Pump</th><th>Input Range (V)</th></tr>
+* <tr>
+* <td>OFF</td>
+* <td>0 to VDDA-1.5</td>
+* </tr>
+* <tr>
+* <td>ON</td>
+* <td>0 to VDDA</td>
+* </tr>
+* </table>
+*
+* Note that in Deep Sleep mode, the charge pump is disabled so the input
+* range is reduced.
+*/
+typedef enum{
+ CY_CTB_PUMP_DISABLE = 0u, /**< Charge pump is disabled for an input range of 0 to VDDA - 1.5 V */
+ CY_CTB_PUMP_ENABLE = CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk, /**< Charge pump is enabled for an input range of 0 to VDDA */
+}cy_en_ctb_pump_t;
+
+/**
+* Configure the type of edge that will trigger a comparator interrupt or
+* disable the interrupt entirely.
+*/
+typedef enum
+{
+ CY_CTB_COMP_EDGE_DISABLE = 0u, /**< Disabled, no interrupts generated */
+ CY_CTB_COMP_EDGE_RISING = 1u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Rising edge generates an interrupt */
+ CY_CTB_COMP_EDGE_FALLING = 2u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Falling edge generates an interrupt */
+ CY_CTB_COMP_EDGE_BOTH = 3u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Both edges generate an interrupt */
+}cy_en_ctb_comp_edge_t;
+
+/** Configure the comparator DSI trigger output level when output is synchronized. */
+typedef enum
+{
+ CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE = 0u, /**< Send pulse on DSI for each edge of comparator output */
+ CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL = CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk, /**< DSI output is synchronized version of comparator output */
+}cy_en_ctb_comp_level_t;
+
+/** Bypass the comparator output synchronization for DSI trigger. */
+typedef enum
+{
+ CY_CTB_COMP_BYPASS_SYNC = 0u, /**< Comparator output is synchronized for DSI trigger */
+ CY_CTB_COMP_BYPASS_NO_SYNC = CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk, /**< Comparator output is not synchronized for DSI trigger */
+}cy_en_ctb_comp_bypass_t;
+
+/** Disable or enable the 10 mV hysteresis for the comparator. */
+typedef enum
+{
+ CY_CTB_COMP_HYST_DISABLE = 0u, /**< Disable hysteresis */
+ CY_CTB_COMP_HYST_10MV = CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk, /**< Enable the 10 mV hysteresis */
+}cy_en_ctb_comp_hyst_t;
+
+/** Switch state, either open or closed, to be used in \ref Cy_CTB_SetAnalogSwitch. */
+typedef enum
+{
+ CY_CTB_SWITCH_OPEN = 0uL, /**< Open the switch */
+ CY_CTB_SWITCH_CLOSE = 1uL /**< Close the switch */
+}cy_en_ctb_switch_state_t;
+
+/**
+* The switch register to be used in \ref Cy_CTB_SetAnalogSwitch.
+* The CTB has three registers for configuring the switch routing matrix.
+* */
+typedef enum
+{
+ CY_CTB_SWITCH_OA0_SW = 0u, /**< Switch register for Opamp0 */
+ CY_CTB_SWITCH_OA1_SW = 1u, /**< Switch register for Opamp1 */
+ CY_CTB_SWITCH_CTD_SW = 2u, /**< Switch register for CTDAC routing */
+}cy_en_ctb_switch_register_sel_t;
+
+/**
+* Switch masks for Opamp0 to be used in \ref Cy_CTB_SetAnalogSwitch.
+*/
+typedef enum
+{
+ CY_CTB_SW_OA0_POS_AMUXBUSA_MASK = CTBM_OA0_SW_OA0P_A00_Msk, /**< Switch A00: Opamp0 non-inverting input to AMUXBUS A */
+ CY_CTB_SW_OA0_POS_PIN0_MASK = CTBM_OA0_SW_OA0P_A20_Msk, /**< Switch A20: Opamp0 non-inverting input to Pin 0 of CTB device port */
+ CY_CTB_SW_OA0_POS_PIN6_MASK = CTBM_OA0_SW_OA0P_A30_Msk, /**< Switch A30: Opamp0 non-inverting input to Pin 6 of CTB device port */
+ CY_CTB_SW_OA0_NEG_PIN1_MASK = CTBM_OA0_SW_OA0M_A11_Msk, /**< Switch A11: Opamp0 inverting input to Pin 1 of CTB device port */
+ CY_CTB_SW_OA0_NEG_OUT_MASK = CTBM_OA0_SW_OA0M_A81_Msk, /**< Switch A81: Opamp0 inverting input to Opamp0 output */
+ CY_CTB_SW_OA0_OUT_SARBUS0_MASK = CTBM_OA0_SW_OA0O_D51_Msk, /**< Switch D51: Opamp0 output to sarbus0 */
+ CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK = CTBM_OA0_SW_OA0O_D81_Msk, /**< Switch D81: Short Opamp0 1x with 10x outputs */
+}cy_en_ctb_oa0_switches_t;
+
+/**
+* Switch masks for Opamp1 to be used in \ref Cy_CTB_SetAnalogSwitch.
+*/
+typedef enum
+{
+ CY_CTB_SW_OA1_POS_AMUXBUSB_MASK = CTBM_OA1_SW_OA1P_A03_Msk, /**< Switch A03: Opamp1 non-inverting input to AMUXBUS B */
+ CY_CTB_SW_OA1_POS_PIN5_MASK = CTBM_OA1_SW_OA1P_A13_Msk, /**< Switch A13: Opamp1 non-inverting input to Pin 5 of CTB device port */
+ CY_CTB_SW_OA1_POS_PIN7_MASK = CTBM_OA1_SW_OA1P_A43_Msk, /**< Switch A43: Opamp1 non-inverting input to Pin 7 of CTB device port */
+ CY_CTB_SW_OA1_POS_AREF_MASK = CTBM_OA1_SW_OA1P_A73_Msk, /**< Switch A73: Opamp1 non-inverting input to device Analog Reference (AREF) */
+ CY_CTB_SW_OA1_NEG_PIN4_MASK = CTBM_OA1_SW_OA1M_A22_Msk, /**< Switch A22: Opamp1 inverting input to Pin 4 of CTB device port */
+ CY_CTB_SW_OA1_NEG_OUT_MASK = CTBM_OA1_SW_OA1M_A82_Msk, /**< switch A82: Opamp1 inverting input to Opamp1 output */
+ CY_CTB_SW_OA1_OUT_SARBUS0_MASK = CTBM_OA1_SW_OA1O_D52_Msk, /**< Switch D52: Opamp1 output to sarbus0 */
+ CY_CTB_SW_OA1_OUT_SARBUS1_MASK = CTBM_OA1_SW_OA1O_D62_Msk, /**< Switch D62: Opamp1 output to sarbus1 */
+ CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK = CTBM_OA1_SW_OA1O_D82_Msk, /**< Switch D82: Short Opamp1 1x with 10x outputs */
+}cy_en_ctb_oa1_switches_t;
+
+/**
+* Switch masks for CTDAC to CTB routing to be used in \ref Cy_CTB_SetAnalogSwitch.
+*/
+typedef enum
+{
+ CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. */
+ CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. */
+ CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. */
+ CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. */
+ CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). */
+ CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. */
+ CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. */
+ CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. */
+ CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */
+ CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */
+}cy_en_ctb_ctd_switches_t;
+
+
+/**
+* Masks for CTB switches that can be controlled by the SAR sequencer.
+* These masks are used in \ref Cy_CTB_EnableSarSeqCtrl and \ref Cy_CTB_DisableSarSeqCtrl.
+*
+* The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1.
+* This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels:
+*
+* - D51: Connects the inverting terminal of OA0 to SARBUS0
+* - D52: Connects the inverting terminal of OA1 to SARBUS0
+* - D62: Connects the inverting terminal of OA1 to SARBUS1
+*/
+typedef enum
+{
+ CY_CTB_SW_SEQ_CTRL_D51_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D51 switch */
+ CY_CTB_SW_SEQ_CTRL_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D52 and D62 switches */
+ CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk | CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequency control of all three switches */
+}cy_en_ctb_switch_sar_seq_t;
+
+/**
+* Each opamp also has a programmable compensation capacitor block,
+* that optimizes the stability of the opamp performance based on output load.
+* The compensation cap will be set by the driver based on the opamp drive strength (1x or 10x) selection.
+*/
+typedef enum
+{
+ CY_CTB_OPAMP_COMPENSATION_CAP_OFF = 0u, /**< No compensation */
+ CY_CTB_OPAMP_COMPENSATION_CAP_MIN = 1u, /**< Minimum compensation - for 1x drive*/
+ CY_CTB_OPAMP_COMPENSATION_CAP_MED = 2u, /**< Medium compensation */
+ CY_CTB_OPAMP_COMPENSATION_CAP_MAX = 3u, /**< Maximum compensation - for 10x drive */
+}cy_en_ctb_compensation_cap_t;
+
+/** Enable or disable the gain booster.
+* The gain booster will be set by the driver based on the opamp drive strength (1x or 10x) selection.
+*/
+typedef enum
+{
+ CY_CTB_OPAMP_BOOST_DISABLE = 0u, /**< Disable gain booster - for 10x drive */
+ CY_CTB_OPAMP_BOOST_ENABLE = CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk, /**< Enable gain booster - for 1x drive */
+}cy_en_ctb_boost_en_t;
+
+/** Sample and hold modes for firmware sampling of the CTDAC output.
+*
+* To perform a sample or a hold, a preparation step must first be executed to
+* open the required switches.
+*
+* -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_PREPARE_SAMPLE or \ref CY_CTB_SH_PREPARE_HOLD
+* -# Enable or disable CTDAC output
+* -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_SAMPLE or \ref CY_CTB_SH_HOLD
+*/
+typedef enum
+{
+ CY_CTB_SH_DISABLE = 0u, /**< The hold capacitor is not connected - this disables sample and hold */
+ CY_CTB_SH_PREPARE_SAMPLE = 1u, /**< Prepares the required switches for a following sample */
+ CY_CTB_SH_SAMPLE = 2u, /**< Performs a sample of the voltage */
+ CY_CTB_SH_PREPARE_HOLD = 3u, /**< Prepares the required switches for a following hold */
+ CY_CTB_SH_HOLD = 4u, /**< Performs a hold of the previously sampled voltage */
+}cy_en_ctb_sample_hold_mode_t;
+
+/** AREF IPTAT bias current output for the CTB
+*
+* The CTB bias current can be 1 uA (normal) or 100 nA (low current).
+*/
+typedef enum
+{
+ CY_CTB_IPTAT_NORMAL = 0u, /**< 1 uA bias current to the CTB */
+ CY_CTB_IPTAT_LOW = 1u << PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos, /**< 100 nA bias current to the CTB */
+}cy_en_ctb_iptat_t;
+
+/** CTB charge pump clock sources
+*
+* The CTB pump clock can come from:
+* - a dedicated divider clock in the SRSS
+* - one of the CLK_PERI dividers
+*/
+typedef enum
+{
+ CY_CTB_CLK_PUMP_SRSS = 0u, /**< Use the dedicated pump clock from SRSSp */
+ CY_CTB_CLK_PUMP_PERI = 1u << PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos, /**< Use one of the CLK_PERI dividers */
+}cy_en_ctb_clk_pump_source_t;
+
+/** High level opamp current modes */
+typedef enum
+{
+ CY_CTB_CURRENT_HIGH_ACTIVE = 0u, /**< Uses 1 uA reference current with charge pump enabled. Available in Active and Low Power */
+ CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP = 1u, /**< Uses 1 uA reference current with charge pump disabled. Available in all power modes */
+ CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP = 2u, /**< Uses 100 nA reference current with charge pump disabled. Available in all power modes */
+}cy_en_ctb_current_mode_t;
+
+/** Return states for \ref Cy_CTB_Init, \ref Cy_CTB_OpampInit, \ref Cy_CTB_DeInit, and \ref Cy_CTB_FastInit */
+typedef enum {
+ CY_CTB_SUCCESS = 0x00uL, /**< Initialization completed successfully */
+ CY_CTB_BAD_PARAM = CY_CTB_ID | CY_PDL_STATUS_ERROR | 0x01uL, /**< Input pointers were NULL and initialization could not be completed */
+}cy_en_ctb_status_t;
+
+/** \} group_ctb_enums */
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_ctb_data_structures
+* \{
+*/
+
+/**
+* Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init.
+*/
+typedef struct {
+ cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
+
+ /* Opamp0 configuration */
+ cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */
+ cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */
+ cy_en_ctb_pump_t oa0Pump; /**< Opamp0 charge pump: enable to increase input range for rail-to-rail operation */
+ cy_en_ctb_comp_edge_t oa0CompEdge; /**< Opamp0 comparator edge detection: disable, rising, falling, or both */
+ cy_en_ctb_comp_level_t oa0CompLevel; /**< Opamp0 comparator DSI (trigger) output: pulse or level */
+ cy_en_ctb_comp_bypass_t oa0CompBypass; /**< Opamp0 comparator DSI (trigger) output synchronization */
+ cy_en_ctb_comp_hyst_t oa0CompHyst; /**< Opamp0 comparator hysteresis: enable for 10 mV hysteresis */
+ bool oa0CompIntrEn; /**< Opamp0 comparator interrupt enable */
+
+ /* Opamp1 configuration */
+ cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */
+ cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */
+ cy_en_ctb_pump_t oa1Pump; /**< Opamp1 charge pump: enable to increase input range for rail-to-rail operation */
+ cy_en_ctb_comp_edge_t oa1CompEdge; /**< Opamp1 comparator edge detection: disable, rising, falling, or both */
+ cy_en_ctb_comp_level_t oa1CompLevel; /**< Opamp1 comparator DSI (trigger) output: pulse or level */
+ cy_en_ctb_comp_bypass_t oa1CompBypass; /**< Opamp1 comparator DSI (trigger) output synchronization */
+ cy_en_ctb_comp_hyst_t oa1CompHyst; /**< Opamp1 comparator hysteresis: enable for 10 mV hysteresis */
+ bool oa1CompIntrEn; /**< Opamp1 comparator interrupt enable */
+
+ /* Switch analog routing configuration */
+ bool configRouting; /**< Configure or ignore routing related registers */
+ uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */
+ uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */
+ uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
+}cy_stc_ctb_config_t;
+
+/**
+* This configuration structure is used to initialize only one opamp of the CTB
+* without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit.
+*/
+typedef struct {
+ cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
+
+ /* Opamp configuration */
+ cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */
+ cy_en_ctb_mode_t oaMode; /**< Opamp usage mode: 1x drive, 10x drive, or as a comparator */
+ cy_en_ctb_pump_t oaPump; /**< Opamp charge pump: enable to increase input range for rail-to-rail operation */
+ cy_en_ctb_comp_edge_t oaCompEdge; /**< Opamp comparator edge detection: disable, rising, falling, or both */
+ cy_en_ctb_comp_level_t oaCompLevel; /**< Opamp comparator DSI (trigger) output: pulse or level */
+ cy_en_ctb_comp_bypass_t oaCompBypass; /**< Opamp comparator DSI (trigger) output synchronization */
+ cy_en_ctb_comp_hyst_t oaCompHyst; /**< Opamp comparator hysteresis: enable for 10 mV hysteresis */
+ bool oaCompIntrEn; /**< Opamp comparator interrupt enable */
+}cy_stc_ctb_opamp_config_t;
+
+/** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations.
+*
+* Other configuration options are set to:
+* - .oa0Pump = \ref CY_CTB_PUMP_ENABLE
+* - .oa0CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
+* - .oa0CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
+* - .oa0CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
+* - .oa0CompHyst = \ref CY_CTB_COMP_HYST_10MV
+* - .oa0CompIntrEn = true
+*/
+typedef struct
+{
+ cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */
+ cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */
+ uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */
+ uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
+}cy_stc_ctb_fast_config_oa0_t;
+
+/** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations.
+*
+* Other configuration options are set to:
+* - .oa1Pump = \ref CY_CTB_PUMP_ENABLE
+* - .oa1CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
+* - .oa1CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
+* - .oa1CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
+* - .oa1CompHyst = \ref CY_CTB_COMP_HYST_10MV
+* - .oa1CompIntrEn = true
+*/
+typedef struct
+{
+ cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */
+ cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */
+ uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */
+ uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
+}cy_stc_ctb_fast_config_oa1_t;
+
+/** \} group_ctb_data_structures */
+
+
+/** \addtogroup group_ctb_globals
+* \{
+*/
+/***************************************
+* Global Variables
+***************************************/
+
+/** Configure Opamp0 as unused - powered down. See \ref Cy_CTB_FastInit. */
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused;
+
+/** Configure Opamp0 as a comparator. No routing is configured.
+*
+* \image html ctb_fast_config_comp.png
+* \image latex ctb_fast_config_comp.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp;
+
+/** Configure Opamp0 as an opamp with 1x drive. No routing is configured.
+*
+* \image html ctb_fast_config_opamp1x.png
+* \image latex ctb_fast_config_opamp1x.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x;
+
+/** Configure Opamp0 as an opamp with 10x drive. No routing is configured.
+*
+* \image html ctb_fast_config_opamp10x.png
+* \image latex ctb_fast_config_opamp10x.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x;
+
+/** Configure Opamp0 as one stage of a differential amplifier.
+* The opamp is in 10x drive and the switches shown are closed.
+*
+* \image html ctb_fast_config_oa0_diffamp.png
+* \image latex ctb_fast_config_oa0_diffamp.png width=100px
+*
+* See the device datasheet for the dedicated CTB port.
+*
+* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp1_Diffamp.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp;
+
+/** Configure Opamp0 as a buffer for the CTDAC output.
+* The buffer is in 10x drive and the switches shown are closed.
+* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit
+* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
+*
+* \image html ctb_fast_config_vdac_output.png
+* \image latex ctb_fast_config_vdac_output.png
+*
+* See the device datasheet for the dedicated CTB port.
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out;
+
+/** Configure Opamp0 as a buffer for the CTDAC output with the sample and hold capacitor connected.
+* The buffer is in 10x drive and the switches shown are closed.
+* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit
+* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
+
+* \image html ctb_fast_config_vdac_sh.png
+* \image latex ctb_fast_config_vdac_sh.png
+*
+* See the device datasheet for the dedicated CTB port.
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH;
+
+/** Configure Opamp1 as unused - powered down. See \ref Cy_CTB_FastInit.*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused;
+
+/** Configure Opamp1 as a comparator. No routing is configured.
+*
+* \image html ctb_fast_config_comp.png
+* \image latex ctb_fast_config_comp.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp;
+
+/** Configure Opamp1 as an opamp with 1x drive. No routing is configured.
+*
+* \image html ctb_fast_config_opamp1x.png
+* \image latex ctb_fast_config_opamp1x.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x;
+
+/** Configure Opamp1 as an opamp with 10x drive. No routing is configured.
+*
+* \image html ctb_fast_config_opamp10x.png
+* \image latex ctb_fast_config_opamp10x.png width=100px
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x;
+
+/** Configure Opamp1 as one stage of a differential amplifier.
+* The opamp is in 10x drive and the switches shown are closed.
+*
+* \image html ctb_fast_config_oa1_diffamp.png
+* \image latex ctb_fast_config_oa1_diffamp.png width=100px
+*
+* See the device datasheet for the dedicated CTB port.
+*
+* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp0_Diffamp.
+*
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp;
+
+/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from the
+* internal analog reference block (AREF).
+* The buffer is in 1x drive and the switches shown are closed.
+* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit
+* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
+*
+* \image html ctb_fast_config_vdac_aref.png
+* \image latex ctb_fast_config_vdac_aref.png
+*
+* See \ref Cy_CTB_FastInit.
+*
+* Note the AREF block needs to be configured using a separate driver.
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref;
+
+/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from Pin 5.
+* The buffer is in 1x drive and the switches shown are closed.
+* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit
+* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
+*
+* \image html ctb_fast_config_vdac_pin5.png
+* \image latex ctb_fast_config_vdac_pin5.png
+*
+* See the device datasheet for the dedicated CTB port.
+*
+* See \ref Cy_CTB_FastInit.
+*/
+extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5;
+
+/** \} group_ctb_globals */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_ctb_functions
+* \{
+*/
+
+/**
+* \addtogroup group_ctb_functions_init
+* This set of functions are for initializing, enabling, and disabling the CTB.
+* \{
+*/
+cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config);
+cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config);
+cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting);
+cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1);
+__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base);
+__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_basic
+* This set of functions are for configuring basic usage of the CTB.
+* \{
+*/
+void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep);
+void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode);
+void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_sample_hold
+* This function enables sample and hold of the CTDAC output.
+* \{
+*/
+void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_comparator
+* This set of functions are specific to the comparator mode
+* \{
+*/
+void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst);
+uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge);
+uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_trim
+* These are advanced functions for trimming the offset and slope of the opamps.
+* Most users do not need to call these functions and can use the factory trimmed values.
+* \{
+*/
+void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim);
+uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum);
+void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim);
+uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_switches
+* This set of functions is for controlling routing switches.
+* \{
+*/
+void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state);
+uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect);
+__STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base);
+__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
+__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_interrupts
+* This set of functions is related to the comparator interrupts.
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+__STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_aref
+* This set of functions impacts all opamps on the chip.
+* Notice how some of these functions do not take a base address input.
+* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
+* it should be called for all other CTB instances as well. This is because
+* there is only one IPTAT level (1 uA or 100 nA) chip wide.
+* \{
+*/
+void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode);
+__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat);
+__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump);
+__STATIC_INLINE void Cy_CTB_EnableRedirect(void);
+__STATIC_INLINE void Cy_CTB_DisableRedirect(void);
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_init
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_CTB_Enable
+****************************************************************************//**
+*
+* Power up the CTB hardware block.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base)
+{
+ base->CTB_CTRL |= CTBM_CTB_CTRL_ENABLED_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_Disable
+****************************************************************************//**
+*
+* Power down the CTB hardware block.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base)
+{
+ base->CTB_CTRL &= (~CTBM_CTB_CTRL_ENABLED_Msk);
+}
+
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_switches
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_CTB_OpenAllSwitches
+****************************************************************************//**
+*
+* Open all the switches and disable all hardware (SAR Sequencer and DSI) control of the switches.
+* Primarily used as a quick method of re-configuring all analog connections
+* that are sparsely closed.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_OPEN_ALL_SWITCHES
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base)
+{
+ base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW;
+ base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW;
+ base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW;
+ base->CTB_SW_DS_CTRL = CY_CTB_DEINIT;
+ base->CTB_SW_SQ_CTRL = CY_CTB_DEINIT;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_EnableSarSeqCtrl
+****************************************************************************//**
+*
+* Enable SAR sequencer control of specified switch(es).
+*
+* This allows the SAR ADC to use routes through the CTB when configuring its channels.
+*
+* There are three switches in the CTB that can be enabled by the SAR sequencer.
+* - D51: This switch connects the negative input of Opamp0 to the SARBUS0
+* - D52: This switch connects the positive input of Opamp1 to the SARBUS0
+* - D62: This switch connects the positive input of Opamp1 to the SARBUS1
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchMask
+* The switch or switches in which to enable SAR sequencer control.
+* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_SAR_SEQ_CTRL
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
+{
+ CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
+
+ base->CTB_SW_SQ_CTRL |= (uint32_t) switchMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_DisableSarSeqCtrl
+****************************************************************************//**
+*
+* Disable SAR sequencer control of specified switch(es).
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchMask
+* The switch or switches in which to disable SAR sequencer control.
+* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_DISABLE_SAR_SEQ_CTRL
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
+{
+ CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
+
+ base->CTB_SW_SQ_CTRL &= ~((uint32_t) switchMask);
+}
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_interrupts
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_CTB_GetInterruptStatus
+****************************************************************************//**
+*
+* Return the status of the interrupt when the configured comparator
+* edge is detected.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \return
+* The interrupt status.
+* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned status
+* to \ref cy_en_ctb_opamp_sel_t to determine which comparator edge (or both)
+* was detected.
+* - 0: Edge was not detected
+* - Non-zero: Configured edge type was detected
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_GETINTERRUPTSTATUS
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+
+ return base->INTR & (uint32_t) compNum;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_ClearInterrupt
+****************************************************************************//**
+*
+* Clear the CTB comparator triggered interrupt.
+* The interrupt must be cleared with this function so that the hardware
+* can set subsequent interrupts and those interrupts can be forwarded
+* to the interrupt controller, if enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+
+ base->INTR = (uint32_t) compNum;
+
+ /* Dummy read for buffered writes. */
+ (void) base->INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetInterrupt
+****************************************************************************//**
+*
+* Force the CTB interrupt to trigger using software.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+
+ base->INTR_SET = (uint32_t) compNum;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetInterruptMask
+****************************************************************************//**
+*
+* Configure the CTB comparator edge interrupt to be forwarded to the
+* CPU interrupt controller.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_NONE, \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH.
+* Calling this function with CY_CTB_OPAMP_NONE will disable all interrupt requests.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM_ALL(compNum));
+
+ base->INTR_MASK = (uint32_t) compNum;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_GetInterruptMask
+****************************************************************************//**
+*
+* Return whether the CTB comparator edge interrupt output is
+* forwarded to the CPU interrupt controller as configured by
+* \ref Cy_CTB_SetInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \return
+* The interrupt mask.
+* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned mask
+* to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
+* output (or both) is forwarded.
+* - 0: Interrupt output not forwarded to interrupt controller
+* - Non-zero: Interrupt output forwarded to interrupt controller
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+
+ return base->INTR_MASK & (uint32_t) compNum;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the CTB comparator edge output interrupt state after being masked.
+* This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param compNum
+* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
+*
+* \return
+* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned value
+* to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
+* output (or both) is detected and masked.
+* - 0: Configured edge not detected or not masked
+* - Non-zero: Configured edge type detected and masked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
+{
+ CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
+
+ return base->INTR_MASKED & (uint32_t) compNum;
+}
+/** \} */
+
+/**
+* \addtogroup group_ctb_functions_aref
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetIptatLevel
+****************************************************************************//**
+*
+* Set the IPTAT reference level to 1 uA or 100 nA. The IPTAT generator is used by the CTB
+* for slope offset drift.
+*
+* \param iptat
+* Value from enum \ref cy_en_ctb_iptat_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_IPTAT_LEVEL
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)
+{
+ CY_ASSERT_L3(CY_CTB_IPTAT(iptat));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk) | (uint32_t) iptat;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_SetClkPumpSource
+****************************************************************************//**
+*
+* Set the clock source for both charge pumps in the CTB. Recall that each opamp
+* has its own charge pump. The clock can come from:
+*
+* - A dedicated divider off of one of the CLK_PATH in the SRSS.
+* Call the following functions to configure the pump clock from the SRSS:
+* - \ref Cy_SysClk_ClkPumpSetSource
+* - \ref Cy_SysClk_ClkPumpSetDivider
+* - \ref Cy_SysClk_ClkPumpEnable
+* - One of the Peri Clock dividers.
+* Call the following functions to configure a Peri Clock divider as the
+* pump clock:
+* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI
+* - \ref Cy_SysClk_PeriphSetDivider
+* - \ref Cy_SysClk_PeriphEnableDivider
+*
+* \param clkPump
+* Clock source selection (SRSS or PeriClk) for the pump. Select a value from
+* \ref cy_en_ctb_clk_pump_source_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump)
+{
+ CY_ASSERT_L3(CY_CTB_CLKPUMP(clkPump));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk) | (uint32_t) clkPump;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_EnableRedirect
+****************************************************************************//**
+*
+* Normally, the AREF IZTAT is routed to the CTB IZTAT and the AREF IPTAT
+* is routed to the CTB IPTAT:
+*
+* - CTB.IZTAT = AREF.IZTAT
+* - CTB.IPTAT = AREF.IPTAT
+*
+* However, the AREF IPTAT can be redirected to the CTB IZTAT and the CTB IPTAT
+* is off.
+*
+* - CTB.IZTAT = AREF.IPTAT
+* - CTB.IPTAT = HiZ
+*
+* The redirection applies to all opamps on the device and
+* should be used when the IPTAT bias level is set to 100 nA
+* (see \ref Cy_CTB_SetIptatLevel).
+*
+* When the CTB.IPTAT is HiZ, the CTB cannot compensate for the slope of
+* the offset across temperature.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_REDIRECT
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_EnableRedirect(void)
+{
+ PASS_AREF->AREF_CTRL |= PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTB_DisableRedirect
+****************************************************************************//**
+*
+* Disable the redirection of the AREF IPTAT to the CTB IZTAT for all opamps
+* on the device as enabled by \ref Cy_CTB_EnableRedirect.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTB_DisableRedirect(void)
+{
+ PASS_AREF->AREF_CTRL &= ~(PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk);
+}
+
+/** \} */
+
+/** \} group_ctb_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /** !defined(CY_CTB_H) */
+
+/** \} group_ctb */
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,721 @@
+/***************************************************************************//**
+* \file cy_ctdac.c
+* \version 1.0.1
+*
+* Provides the public functions for the API for the CTDAC driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "ctdac/cy_ctdac.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** Static function to configure the clock */
+static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType,
+ uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue);
+
+const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut =
+{
+ /*.refSource */ CY_CTDAC_REFSOURCE_VDDA,
+ /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED,
+};
+
+const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut =
+{
+ /*.refSource */ CY_CTDAC_REFSOURCE_VDDA,
+ /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED,
+};
+
+const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut =
+{
+ /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL,
+ /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED,
+};
+
+const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut =
+{
+ /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL,
+ /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED,
+};
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_Init
+****************************************************************************//**
+*
+* Initialize all CTDAC configuration registers
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param config
+* Pointer to structure containing configuration data
+*
+* \return
+* Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_INIT_CUSTOM
+*
+*******************************************************************************/
+cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_ctdac_status_t result;
+ uint32_t ctdacCtrl = CY_CTDAC_DEINIT;
+ uint32_t setSwitch = CY_CTDAC_DEINIT;
+ uint32_t clearSwitch = CY_CTDAC_DEINIT;
+
+ if ((NULL == base) || (NULL == config))
+ {
+ result = CY_CTDAC_BAD_PARAM;
+ }
+ else
+ {
+
+ CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource));
+ CY_ASSERT_L3(CY_CTDAC_FORMAT(config->formatMode));
+ CY_ASSERT_L3(CY_CTDAC_UPDATE(config->updateMode));
+ CY_ASSERT_L3(CY_CTDAC_DEGLITCH(config->deglitchMode));
+ CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(config->outputMode));
+ CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer));
+ CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(config->deepSleep));
+ CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(config->deglitchCycles));
+
+ /* Handle the deglitch counts */
+ ctdacCtrl |= (config->deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk;
+
+ /* Handle the deglitch mode */
+ ctdacCtrl |= (uint32_t)config->deglitchMode;
+
+ /* Handle the update mode */
+ if ((config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE) \
+ || (config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_SYNC) \
+ || (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL))
+ {
+ ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk;
+ }
+
+ if (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL)
+ {
+ ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk;
+ }
+
+ /* Handle the sign format */
+ ctdacCtrl |= (uint32_t)config->formatMode;
+
+ /* Handle the Deep Sleep mode */
+ ctdacCtrl |= (uint32_t)config->deepSleep;
+
+ /* Handle the output mode */
+ ctdacCtrl |= (uint32_t)config->outputMode;
+
+ /* Handle the reference source */
+ switch(config->refSource)
+ {
+ case CY_CTDAC_REFSOURCE_VDDA:
+
+ /* Close the CVD switch to use Vdda as the reference source */
+ setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk;
+ break;
+ case CY_CTDAC_REFSOURCE_EXTERNAL:
+ default:
+ clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk;
+ break;
+ }
+
+ /* Handle the output buffer switch CO6 */
+ switch(config->outputBuffer)
+ {
+ case CY_CTDAC_OUTPUT_UNBUFFERED:
+
+ /* Close the CO6 switch to send output to a direct pin unbuffered */
+ setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk;
+ break;
+ case CY_CTDAC_OUTPUT_BUFFERED:
+ default:
+ clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk;
+ break;
+ }
+
+ base->INTR_MASK = (uint32_t)config->enableInterrupt << CTDAC_INTR_VDAC_EMPTY_Pos;
+ base->CTDAC_SW = setSwitch;
+ base->CTDAC_SW_CLEAR = clearSwitch;
+ base->CTDAC_VAL = (((uint32_t)config->value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk;
+ base->CTDAC_VAL_NXT = (((uint32_t)config->nextValue) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk;
+
+ if (config->configClock)
+ {
+ Cy_CTDAC_ConfigureClock(config->updateMode, config->dividerType, config->dividerNum, config->dividerIntValue, config->dividerFracValue);
+ }
+
+ base->CTDAC_CTRL = ctdacCtrl;
+ result = CY_CTDAC_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_DeInit
+****************************************************************************//**
+*
+* Reset CTDAC registers back to power on reset defaults.
+*
+* \note
+* Does not disable the clock.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deInitRouting
+* If true, all switches are reset to their default state.
+* If false, switch registers are untouched.
+*
+* \return
+* Status of initialization, \ref CY_CTDAC_SUCCESS, or \ref CY_CTDAC_BAD_PARAM
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEINIT
+*
+*******************************************************************************/
+cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting)
+{
+ CY_ASSERT_L1(NULL != base);
+
+ cy_en_ctdac_status_t result;
+
+ if (NULL == base)
+ {
+ result = CY_CTDAC_BAD_PARAM;
+ }
+ else
+ {
+ base->CTDAC_CTRL = CY_CTDAC_DEINIT;
+ base->INTR_MASK = CY_CTDAC_DEINIT;
+ base->CTDAC_VAL = CY_CTDAC_DEINIT;
+ base->CTDAC_VAL_NXT = CY_CTDAC_DEINIT;
+
+ if (deInitRouting)
+ {
+ base->CTDAC_SW_CLEAR = CY_CTDAC_DEINIT;
+ }
+
+ result = CY_CTDAC_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_FastInit
+****************************************************************************//**
+*
+* Initialize the CTDAC to one of the common use modes.
+* This function provides a quick and easy method of configuring the CTDAC when using
+* the PDL driver for device configuration.
+*
+* The other configuration options are set to:
+* - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED
+* - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE
+* - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE
+* - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE
+* - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE
+* - .deglitchCycles = \ref CY_CTDAC_DEINIT
+* - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
+* - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
+* - .enableInterrupt = true
+* - .configClock = true
+* - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE
+* - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM
+* - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV
+* - .dividerFracValue = \ref CY_CTDAC_DEINIT
+*
+* A separate call to \ref Cy_CTDAC_Enable is needed to turn on the hardware.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param config
+* Pointer to structure containing configuration data for quick initialization.
+* Define your own or use one of the provided structures:
+* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut
+* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut
+* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut
+* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut
+*
+* \return
+* Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM
+*
+* \funcusage
+*
+* The following code snippets configures VDDA as the reference source and
+* routes the output directly to Pin 6 (unbuffered).
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT
+*
+* \funcusage
+*
+* The following code snippet shows how the CTDAC and CTB blocks can
+* quickly be configured to work together. The code
+* configures the CTDAC to use a buffered output,
+* a buffered reference source from the internal bandgap voltage, and closes
+* all required analog routing switches.
+*
+* \image html ctdac_fast_init_funcusage.png
+* \image latex ctdac_fast_init_funcusage.png
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT_CTB
+*
+*******************************************************************************/
+cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_ctdac_status_t result;
+ uint32_t ctdacCtrl;
+ uint32_t setSwitch = CY_CTDAC_DEINIT;
+ uint32_t clearSwitch = CY_CTDAC_DEINIT;
+
+ if ((NULL == base) || (NULL == config))
+ {
+ result = CY_CTDAC_BAD_PARAM;
+ }
+ else
+ {
+ CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource));
+ CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer));
+
+ ctdacCtrl = (uint32_t) CY_CTDAC_DEGLITCHMODE_NONE \
+ | (uint32_t) CY_CTDAC_UPDATE_BUFFERED_WRITE \
+ | (uint32_t) CY_CTDAC_FORMAT_UNSIGNED \
+ | (uint32_t) CY_CTDAC_DEEPSLEEP_DISABLE \
+ | (uint32_t) CY_CTDAC_OUTPUT_VALUE;
+
+ /* Handle the reference source */
+ switch(config->refSource)
+ {
+ case CY_CTDAC_REFSOURCE_VDDA:
+
+ /* Close the CVD switch to use Vdda as the reference source */
+ setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk;
+ break;
+ case CY_CTDAC_REFSOURCE_EXTERNAL:
+ default:
+ clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk;
+ break;
+ }
+
+ /* Handle the output buffer switch CO6 */
+ switch(config->outputBuffer)
+ {
+ case CY_CTDAC_OUTPUT_UNBUFFERED:
+
+ /* Close the CO6 switch to send output to a direct pin unbuffered */
+ setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk;
+ break;
+ case CY_CTDAC_OUTPUT_BUFFERED:
+ default:
+ clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk;
+ break;
+ }
+
+ base->INTR_MASK = CTDAC_INTR_VDAC_EMPTY_Msk;
+ base->CTDAC_SW = setSwitch;
+ base->CTDAC_SW_CLEAR = clearSwitch;
+ base->CTDAC_VAL = CY_CTDAC_UNSIGNED_MID_CODE_VALUE;
+ base->CTDAC_VAL_NXT = CY_CTDAC_UNSIGNED_MID_CODE_VALUE;
+
+ /* For fast configuration, the DAC clock is the Peri clock divided by 100. */
+ Cy_CTDAC_ConfigureClock(CY_CTDAC_UPDATE_BUFFERED_WRITE, CY_CTDAC_FAST_CLKCFG_TYPE, CY_CTDAC_FAST_CLKCFG_NUM, CY_CTDAC_FAST_CLKCFG_DIV, CY_CTDAC_DEINIT);
+
+ base->CTDAC_CTRL = ctdacCtrl;
+ result = CY_CTDAC_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_ConfigureClock
+****************************************************************************//**
+*
+* Private function for configuring the CTDAC clock based on the desired
+* update mode. This function is called by \ref Cy_CTDAC_Init.
+*
+* \param updateMode
+* Update mode value. See \ref cy_en_ctdac_update_t for values.
+*
+* \return None
+*
+*******************************************************************************/
+static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType,
+ uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue)
+{
+ if (updateMode == CY_CTDAC_UPDATE_DIRECT_WRITE)
+ { /* In direct mode, there is not a clock */
+ }
+ else if(updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE)
+ {
+
+ /* In this mode, the Peri Clock is divided by 1 to give a constant logic high on the CTDAC clock. */
+ (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum);
+
+ (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum);
+
+ if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT))
+ {
+ (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV);
+ }
+ else
+ {
+ (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC);
+ }
+
+ (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum);
+ }
+ else
+ {
+
+ /* All other modes, require a CTDAC clock configured to the desired user frequency */
+ (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum);
+
+ (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum);
+
+ if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT))
+ {
+ (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, dividerIntValue);
+ }
+ else
+ {
+ (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, dividerIntValue, dividerFracValue);
+ }
+ (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum);
+ }
+
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetSignMode
+****************************************************************************//**
+*
+* Set whether to interpret the DAC value as signed or unsigned.
+* In unsigned mode, the DAC value register is used without any decoding.
+* In signed mode, the MSB is inverted by adding 0x800 to the DAC value.
+* This converts the lowest signed number, 0x800, to the lowest unsigned
+* number, 0x000.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param formatMode
+* Mode can be signed or unsigned. See \ref cy_en_ctdac_format_t for values.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SIGN_MODE
+*
+*******************************************************************************/
+void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode)
+{
+ CY_ASSERT_L3(CY_CTDAC_FORMAT(formatMode));
+
+ uint32_t ctdacCtrl;
+
+ /* Clear the CTDAC_MODE bits */
+ ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk;
+
+ base->CTDAC_CTRL = ctdacCtrl | (uint32_t)formatMode;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetDeepSleepMode
+****************************************************************************//**
+*
+* Enable or disable the DAC hardware operation in Deep Sleep mode.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deepSleep
+* Enable or disable Deep Sleep operation. Select value from \ref cy_en_ctdac_deep_sleep_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEEPSLEEP_MODE
+*
+*******************************************************************************/
+void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep)
+{
+ CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(deepSleep));
+
+ uint32_t ctdacCtrl;
+
+ ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk;
+
+ base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deepSleep;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetOutputMode
+****************************************************************************//**
+*
+* Set the output mode of the CTDAC:
+* - \ref CY_CTDAC_OUTPUT_HIGHZ : Disable the output
+* - \ref CY_CTDAC_OUTPUT_VALUE : Enable the output and drive the value
+* stored in the CTDAC_VAL register.
+* - \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 : Enable the output and drive the
+* value stored in the CTDAC_VAL register plus 1.
+* - \ref CY_CTDAC_OUTPUT_VSSA : Output pulled to VSSA through 1.1 MOhm (typ) resistor.
+* - \ref CY_CTDAC_OUTPUT_VREF : Output pulled to VREF through 1.1 MOhm (typ) resistor.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param outputMode
+* Select a value from \ref cy_en_ctdac_output_mode_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_OUTPUT_MODE
+*
+*******************************************************************************/
+void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode)
+{
+ CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(outputMode));
+
+ uint32_t ctdacCtrl;
+
+ /* Clear out the three affected bits */
+ ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_OUT_EN_Msk | CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk);
+
+ base->CTDAC_CTRL = ctdacCtrl | (uint32_t)outputMode;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetDeglitchMode
+****************************************************************************//**
+*
+* Enable deglitching on the unbuffered path, buffered path, both, or
+* disable deglitching. The deglitch mode should match the configured output path.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deglitchMode
+* Deglitching mode selection. See \ref cy_en_ctdac_deglitch_t for values.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_MODE
+*
+*******************************************************************************/
+void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode)
+{
+ CY_ASSERT_L3(CY_CTDAC_DEGLITCH(deglitchMode));
+
+ uint32_t ctdacCtrl;
+
+ /* Clear out DEGLITCH_CO6 and DEGLITCH_C0S bits */
+ ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk);
+
+ base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deglitchMode;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetDeglitchCycles
+****************************************************************************//**
+*
+* Set the number of deglitch cycles (0 to 63) that will be used.
+* To calculate the deglitch time:
+*
+* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ
+*
+* The optimal deglitch time is 700 ns.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deglitchCycles
+* Number of cycles to deglitch
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_CYCLES
+*
+*******************************************************************************/
+void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles)
+{
+ CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(deglitchCycles));
+
+ uint32_t ctdacCtrl;
+
+ ctdacCtrl = (base->CTDAC_CTRL) & ~CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk;
+
+ base->CTDAC_CTRL = ctdacCtrl | ((deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk);
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetRef
+****************************************************************************//**
+*
+* Set the CTDAC reference source to Vdda or an external reference.
+* The external reference must come from Opamp1 of the CTB.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param refSource
+* The reference source. Select a value from \ref cy_en_ctdac_ref_source_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_REF
+*
+*******************************************************************************/
+void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource)
+{
+ CY_ASSERT_L3(CY_CTDAC_REFSOURCE(refSource));
+
+ switch(refSource)
+ {
+ case CY_CTDAC_REFSOURCE_VDDA:
+
+ /* Close the CVD switch to use Vdda as the reference source */
+ base->CTDAC_SW |= CTDAC_CTDAC_SW_CTDD_CVD_Msk;
+ break;
+ case CY_CTDAC_REFSOURCE_EXTERNAL:
+ default:
+ base->CTDAC_SW_CLEAR = CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetAnalogSwitch
+****************************************************************************//**
+*
+* Provide firmware control of the CTDAC switches. Each call to this function
+* can open a set of switches or close a set of switches.
+*
+* \note
+* The switches are configured by the reference
+* source and output mode selections during initialization.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchMask
+* The mask of the switches to either open or close.
+* Select one or more values from \ref cy_en_ctdac_switches_t and "OR" them together.
+*
+* \param state
+* Open or close the switche(s). Select a value from \ref cy_en_ctdac_switch_state_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_ANALOG_SWITCH
+*
+*******************************************************************************/
+void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state)
+{
+ CY_ASSERT_L2(CY_CTDAC_SWITCHMASK(switchMask));
+ CY_ASSERT_L3(CY_CTDAC_SWITCHSTATE(state));
+
+ switch(state)
+ {
+ case CY_CTDAC_SWITCH_CLOSE:
+ base->CTDAC_SW |= switchMask;
+ break;
+ case CY_CTDAC_SWITCH_OPEN:
+ default:
+
+ /* Unlike the close case, do not OR the register. Set 1 to clear.*/
+ base->CTDAC_SW_CLEAR = switchMask;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback to prepare the CTDAC before entering and after exiting Deep Sleep
+* mode. If deglitching is used, it is disabled before entering Deep Sleep
+* to ensure the deglitch switches are closed. This is needed only
+* if the CTDAC will be enabled in DeepSleep. Upon wakeup, deglitching will
+* be re-enabled if it was previously used.
+*
+* \param callbackParams
+* Pointer to structure of type \ref cy_stc_syspm_callback_params_t
+*
+* \return
+* See \ref cy_en_syspm_status_t
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEEP_SLEEP_CALLBACK
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ /* Static variable preserved between function calls.
+ * Tracks the state of the deglitch mode before sleep so that it can be re-enabled after wakeup */
+ static uint32_t deglitchModeBeforeSleep;
+
+ cy_en_syspm_status_t returnValue = CY_SYSPM_SUCCESS;
+
+ CTDAC_Type *ctdacBase = (CTDAC_Type *)callbackParams->base;
+
+ if (CY_SYSPM_BEFORE_TRANSITION == callbackParams->mode)
+ { /* Actions that should be done before entering the Deep Sleep mode */
+
+ /* Store the state of the deglitch switches before turning deglitch off */
+ deglitchModeBeforeSleep = ctdacBase->CTDAC_CTRL & (CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk);
+
+ /* Turn deglitch off before entering Deep Sleep */
+ ctdacBase->CTDAC_CTRL &= ~(CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk);
+ }
+ else if (CY_SYSPM_AFTER_TRANSITION == callbackParams->mode)
+ { /* Actions that should be done after exiting the Deep Sleep mode */
+
+ /* Re-enable the deglitch mode that was configured before Deep Sleep entry */
+ ctdacBase->CTDAC_CTRL |= deglitchModeBeforeSleep;
+ }
+ else
+ { /* Does nothing in other modes */
+ }
+
+ return returnValue;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1045 @@
+/***************************************************************************//**
+* \file cy_ctdac.h
+* \version 1.0.1
+*
+* Header file for the CTDAC driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_ctdac Continuous Time Digital to Analog Converter (CTDAC)
+* \{
+* The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC.
+*
+* - 12-bit continuous time output
+* - 2 us settling time for a 25 pF load when output buffered through Opamp0 of \ref group_ctb "CTB"
+* - Can be enabled in Deep Sleep power mode
+* - Selectable voltage reference:
+* - VDDA
+* - Internal analog reference buffered through Opamp1 of \ref group_ctb "CTB"
+* - External reference buffered through Opamp1 of \ref group_ctb "CTB"
+* - Selectable output paths:
+* - Direct DAC output to a pin
+* - Buffered DAC output through Opamp0 of \ref group_ctb "CTB"
+* - Sample and hold output path through Opamp0 of \ref group_ctb "CTB"
+* - Selectable input modes:
+* - Unsigned 12-bit mode
+* - Virtual signed 12-bit mode
+* - Configurable update rate using clock or strobe signal
+* - Double buffered DAC voltage control register
+* - Interrupt and DMA trigger on DAC buffer empty
+* - Configurable as PGA along with Opamp1 of the \ref group_ctb "CTB"
+*
+* The CTDAC generates a 12-bit DAC output voltage from the reference.
+* The DAC reference can come from VDDA or from any signal buffered through Opamp0
+* of the CTB. This can be an external signal through a GPIO or from the internal
+* AREF. The CTDAC is closely integrated with the CTB block,
+* which provides easy buffering of the DAC output voltage,
+* buffered input reference voltage, and sample and hold for the DAC output.
+* The CTDAC control interface provides control of the DAC output through CPU or DMA.
+* This includes a double-buffered DAC voltage control register, clock input for programmable
+* update rate, interrupt on DAC buffer empty, and trigger to DMA.
+*
+* \image html ctdac_block_diagram.png
+* \image latex ctdac_block_diagram.png
+*
+* The CTDAC has two switches, CO6 for configuring the output path and
+* CVD for the reference source.
+*
+* \image html ctdac_switches.png
+* \image latex ctdac_switches.png
+*
+* \section group_ctdac_init Initialization
+*
+* Configure the CTDAC hardware block by calling \ref Cy_CTDAC_Init.
+* The base address of the CTDAC hardware can be found in the device-specific header file.
+* If the buffers in the CTB are used for the reference source or the output,
+* initialize the CTB hardware block. After both blocks are initialized,
+* enable the CTB block before enabling the CTDAC block.
+*
+* The driver also provides a \ref Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC.
+* The driver has pre-defined configuration structures for the four combinations of the reference and output buffers.
+*
+* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut
+* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut
+* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut
+* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut
+*
+* After initialization, call \ref Cy_CTDAC_Enable to enable the hardware.
+*
+* \section group_ctdac_updatemode Update Modes
+* The CTDAC contains two registers:
+* -# CTDAC_VAL
+*
+* For direct firmware writes to update the current DAC value immediately.
+* This register is written with \ref Cy_CTDAC_SetValue.
+* -# CTDAC_VAL_NXT
+*
+* For buffered writes to update the DAC value at a
+* periodic rate or with a strobe trigger input.
+* This register is written with \ref Cy_CTDAC_SetValueBuffered.
+*
+* The update mode is
+* selected during initialization with the \ref cy_stc_ctdac_config_t.updateMode.
+* Four of these modes require a dedicated clock resource and the driver
+* can configure the clock during initialization (see \ref cy_stc_ctdac_config_t).
+*
+* Three of these modes use a strobe signal through the digital signal interface (DSI).
+* This allows control of the buffered update timing from an external source, for example, by another
+* chip peripheral or from an off-chip source.
+*
+* \subsection group_ctdac_updatemode_direct_write Direct write
+*
+* In this mode, the user writes directly into the CTDAC_VAL register
+* using \ref Cy_CTDAC_SetValue. The action of writing to this register
+* will update the DAC output. This mode does not generate an interrupt
+* or trigger signal.
+* In this mode, a clock must not be configured. Additionally, calling \ref
+* Cy_CTDAC_SetValueBuffered does not update the DAC output.
+*
+* \image html ctdac_update_mode_direct_write.png
+* \image latex ctdac_update_mode_direct_write.png
+*
+* \subsection group_ctdac_updatemode_buffered_write Buffered write
+*
+* In this mode, the user writes to the CTDAC_VAL_NXT register using
+* \ref Cy_CTDAC_SetValueBuffered. The rising edge of the clock
+* will update the DAC output and generate the interrupt and trigger signals.
+*
+* Whenever data is transferred from the CTDAC_VAL_NXT register,
+* an interrupt is asserted the same time as the trigger. But while
+* the trigger is automatically cleared after two PeriClk cycles, the
+* user must clear the interrupt with \ref Cy_CTDAC_ClearInterrupt.
+*
+* \image html ctdac_update_mode_buffered_write.png
+* \image latex ctdac_update_mode_buffered_write.png
+*
+* \subsection group_ctdac_updatemode_strobe_edge_sync Strobe edge sync
+*
+* In this mode, the user writes to the CTDAC_VAL_NXT register using
+* \ref Cy_CTDAC_SetValueBuffered.
+* Each rising edge of the DSI strobe input enables
+* one subsequent update from the next rising edge of the clock. The DSI
+* input must remain high for two PeriClk cycles and go low for
+* another two PeriClk cycles to allow for the next update.
+* This restricts the DSI strobe input frequency to the PeriClk frequency divided by four.
+*
+* \image html ctdac_update_mode_strobe_edge_sync.png
+* \image latex ctdac_update_mode_strobe_edge_sync.png
+*
+* \subsection group_ctdac_updatemode_strobe_edge_immediate Strobe edge immediate
+*
+* In this mode, the user writes to the CTDAC_VAL_NXT register using
+* \ref Cy_CTDAC_SetValueBuffered.
+* The clock resource is used but set to a logic high.
+* Therefore, each rising edge of the DSI strobe input immediately
+* updates the DAC output.
+*
+* \image html ctdac_update_mode_strobe_edge_immediate.png
+* \image latex ctdac_update_mode_strobe_edge_immediate.png
+*
+* \subsection group_ctdac_updatemode_strobe_level Strobe level
+*
+* In this mode, the user writes to the CTDAC_VAL_NXT register using
+* \ref Cy_CTDAC_SetValueBuffered.
+* The DSI strobe input acts as a hardware enable signal.
+* While the DSI strobe input is high, the mode behaves
+* like the Buffered write mode. When the DSI strobe input is low,
+* updates are disabled.
+*
+* \image html ctdac_update_mode_strobe_level.png
+* \image latex ctdac_update_mode_strobe_level.png
+*
+* \section group_ctdac_dacmode DAC Modes
+*
+* The format of code stored in the CTDAC_VAL register can either be unsigned
+* or signed two's complemented.
+* Only the first 12 bits of the register are used by the DAC so there is
+* no need for sign extension. With the signed format, the DAC decodes
+* the code in the register by adding 0x800.
+* The DAC can output the register value or the register value plus 1 (see \ref Cy_CTDAC_SetOutputMode).
+*
+* <table class="doxtable">
+* <tr>
+* <th>12-bit unsigned code</th>
+* <th>12-bit two's complement signed code</th>
+* <th>Vout (for \ref CY_CTDAC_OUTPUT_VALUE )</th>
+* <th>Vout (for \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 )</th>
+* </tr>
+* <tr>
+* <td>0x000</td>
+* <td>0x800</td>
+* <td>0</td>
+* <td>Vref/4096</td>
+* </tr>
+* <tr>
+* <td>0x800</td>
+* <td>0x000</td>
+* <td>0.5 * Vref</td>
+* <td>Vref * 2049 / 4096</td>
+* </tr>
+* <tr>
+* <td>0xFFF</td>
+* <td>0x7FF</td>
+* <td>Vref * 4095 / 4096</td>
+* <td>Vref</td>
+* </tr>
+* </table>
+*
+* The expressions in the above table are based on an unbuffered DAC output.
+* When the output is buffered, the input and output range of the buffer will affect the
+* output voltage. See \ref group_ctb_opamp_range in the CTB driver for more information.
+*
+* \section group_ctdac_trigger Interrupts and Trigger
+*
+* When data from the CTDAC_VAL_NXT is transferred to the CTDAC_VAL register,
+* an interrupt and trigger output are generated. The trigger output can be
+* used with a DMA block to update the CTDAC value register at high speeds without any CPU intervention.
+* Alternatively, the interrupt output can be used when DMA is not available
+* to update the CTDAC value register, but at a slower speed.
+*
+* Recall with the \ref group_ctdac_updatemode, the interrupt and trigger output are available in all modes except
+* \ref group_ctdac_updatemode_direct_write.
+*
+* \subsection group_ctdac_dma_trigger DMA Trigger
+*
+* The CTDAC trigger output signal can be routed to a DMA block using the \ref group_trigmux
+* to trigger an update to the CTDAC_VAL_NXT register.
+* When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY
+* and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY.
+*
+* \subsection group_ctdac_handling_interrupts Handling Interrupts
+*
+* The following code snippet demonstrates how to implement a routine to handle the interrupt.
+* The routine gets called when any CTDAC on the device generates an interrupt.
+*
+* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_ISR
+*
+* The following code snippet demonstrates how to configure and enable the interrupt.
+*
+* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_INTR_SETUP
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DMA_TRIGGER
+*
+* \section group_ctdac_deglitch Deglitch
+*
+* The hardware has the ability to deglitch the output value every time it is updated.
+* This prevents small glitches in the DAC output during an update to propagate to
+* the pin or opamp input. When deglitch is enabled, a switch on the output path
+* is forced open for a configurable number of PeriClk cycles. This deglitch time
+* is calculated as:
+*
+* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ
+*
+* The optimal and recommended deglitch time is 700 ns. Call \ref Cy_CTDAC_SetDeglitchCycles to set DEGLITCH_CNT.
+*
+* There are two switches used for deglitching.
+* - Switch COS in the CTB between the DAC output and the Opamp0 input
+* - Switch CO6 in the CTDAC between the DAC output and external pin
+*
+* Call \ref Cy_CTDAC_SetDeglitchMode to set the deglitch path. Match this with the output buffer selection.
+* If the output is buffered through the CTB, select \ref CY_CTDAC_DEGLITCHMODE_BUFFERED.
+* If the output is unbuffered to a direct pin, select \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED.
+*
+* \note
+* If deglitching is enabled, the hardware does not force the deglitch switches into a closed
+* state during Deep Sleep mode. Therefore, there is a chance that the device enters
+* Deep Sleep mode while the hardware is deglitching and the switches on the output path remain open.
+* To ensure the DAC will operate properly in Deep Sleep when enabled, make sure to
+* register the \ref Cy_CTDAC_DeepSleepCallback before entering Deep Sleep mode.
+*
+* \section group_ctdac_sample_hold Sample and Hold
+*
+* When buffering the DAC output, the CTB has a Sample and Hold (SH) feature that can be used for saving power.
+* The DAC output voltage is retained on an internal capacitor for a duration of time while the
+* DAC output can be turned off. The DAC hardware needs to be turned on in a periodic fashion
+* to recharge the hold capacitor. This feature is firmware controlled using a sequence of function calls.
+* See \ref Cy_CTB_DACSampleAndHold in the \ref group_ctb_sample_hold "CTB" driver.
+*
+* The hold time depends on the supply and reference voltages. The following hold times are based on the
+* time it takes for the buffered output to change by 1 LSB.
+*
+* - Hold time = 750 us @ Vref = VDDA , VDDA = 1.7 V
+* - Hold time = 525 us @ Vref = VDDA , VDDA = 3.6 V
+* - Hold time = 200 us @ Vref = 1.2 V, VDDA = 3.6 V
+*
+* \section group_ctdac_low_power Low Power Support
+*
+* The CTDAC driver provides a callback function to handle power mode transitions.
+* If the CTDAC is configured for Deep Sleep operation and \ref group_ctdac_deglitch "deglitching" is enabled,
+* the callback \ref Cy_CTDAC_DeepSleepCallback must be registered before calling
+* \ref Cy_SysPm_DeepSleep.
+* Refer to \ref group_syspm driver for more information about power mode transitions and
+* callback registration.
+*
+* \section group_ctdac_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_ctdac_MISRA MISRA-C Compliance]
+*
+* This driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>Advisory</td>
+* <td>A cast should not be performed between a pointer to object type and a different pointer to object type.</td>
+* <td>The cy_syspm driver defines the pointer to void in the \ref cy_stc_syspm_callback_params_t.base field.
+* This CTDAC driver implements a Deep Sleep callback conforming to the cy_syspm driver requirements.
+* When the callback is called, the base is cast to a pointer to CTDAC_Type.
+* </td>
+* </tr>
+* </table>
+*
+* \section group_ctdac_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Added low power support section. Minor documentation edits.</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_ctdac_macros Macros
+* \defgroup group_ctdac_functions Functions
+* \{
+* \defgroup group_ctdac_functions_init Initialization Functions
+* \defgroup group_ctdac_functions_basic Basic Configuration Functions
+* \defgroup group_ctdac_functions_switches Switch Control Functions
+* \defgroup group_ctdac_functions_interrupts Interrupt Functions
+* \defgroup group_ctdac_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_ctdac_globals Global Variables
+* \defgroup group_ctdac_data_structures Data Structures
+* \defgroup group_ctdac_enums Enumerated Types
+*/
+
+#if !defined(CY_CTDAC_H)
+#define CY_CTDAC_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syspm/cy_syspm.h"
+#include "syslib/cy_syslib.h"
+#include "sysclk/cy_sysclk.h"
+
+#ifndef CY_IP_MXS40PASS_CTDAC
+ #error "The CTDAC driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_ctdac_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_CTDAC_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_CTDAC_DRV_VERSION_MINOR 0
+
+/** CTDAC driver identifier */
+#define CY_CTDAC_ID CY_PDL_DRV_ID(0x19u)
+
+#define CY_CTDAC_DEINIT (0uL) /**< De-init value for CTDAC registers */
+#define CY_CTDAC_UNSIGNED_MID_CODE_VALUE (0x800uL) /**< Middle code value for unsigned values */
+#define CY_CTDAC_UNSIGNED_MAX_CODE_VALUE (0xFFFuL) /**< Maximum code value for unsigned values */
+#define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT /**< Clock divider type for quick clock setup */
+#define CY_CTDAC_FAST_CLKCFG_NUM (0uL) /**< Clock divider number for quick clock setup */
+#define CY_CTDAC_FAST_CLKCFG_DIV (99uL) /**< Clock divider integer value for quick clock setup. Divides PERI clock by 100. */
+
+/** \cond INTERNAL */
+#define CY_CTDAC_DEINT_CTDAC_SW (CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk | CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk) /**< Mask for de-initializing the CTDAC switch control register */
+#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV (0uL) /**< Clock divider value for the Strobe Edge Immediate update mode */
+#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC (0uL) /**< Clock fractional divider value for the Strobe Edge Immediate update mode */
+#define CY_CTDAC_DEGLITCH_CYCLES_MAX (63uL)
+
+/**< Macros for conditions used by CY_ASSERT calls */
+#define CY_CTDAC_REFSOURCE(source) (((source) == CY_CTDAC_REFSOURCE_EXTERNAL) || ((source) == CY_CTDAC_REFSOURCE_VDDA))
+#define CY_CTDAC_FORMAT(mode) (((mode) == CY_CTDAC_FORMAT_UNSIGNED) || ((mode) == CY_CTDAC_FORMAT_SIGNED))
+#define CY_CTDAC_UPDATE(mode) ((mode) <= CY_CTDAC_UPDATE_STROBE_LEVEL)
+#define CY_CTDAC_DEGLITCH(mode) (((mode) == CY_CTDAC_DEGLITCHMODE_NONE) \
+ || ((mode) == CY_CTDAC_DEGLITCHMODE_UNBUFFERED) \
+ || ((mode) == CY_CTDAC_DEGLITCHMODE_BUFFERED) \
+ || ((mode) == CY_CTDAC_DEGLITCHMODE_BOTH))
+#define CY_CTDAC_OUTPUTMODE(mode) (((mode) == CY_CTDAC_OUTPUT_HIGHZ) \
+ || ((mode) == CY_CTDAC_OUTPUT_VALUE) \
+ || ((mode) == CY_CTDAC_OUTPUT_VALUE_PLUS1) \
+ || ((mode) == CY_CTDAC_OUTPUT_VSSA) \
+ || ((mode) == CY_CTDAC_OUTPUT_VREF))
+#define CY_CTDAC_OUTPUTBUFFER(buffer) (((buffer) == CY_CTDAC_OUTPUT_UNBUFFERED) || ((buffer) == CY_CTDAC_OUTPUT_BUFFERED))
+#define CY_CTDAC_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTDAC_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTDAC_DEEPSLEEP_ENABLE))
+#define CY_CTDAC_DEGLITCHCYCLES(cycles) ((cycles) <= CY_CTDAC_DEGLITCH_CYCLES_MAX)
+#define CY_CTDAC_SWITCHMASK(mask) ((mask) <= (uint32_t) (CY_CTDAC_SWITCH_CVD_MASK | CY_CTDAC_SWITCH_CO6_MASK))
+#define CY_CTDAC_SWITCHSTATE(state) (((state) == CY_CTDAC_SWITCH_OPEN) || ((state) == CY_CTDAC_SWITCH_CLOSE))
+#define CY_CTDAC_INTRMASK(mask) (((mask) == 0uL) || ((mask) == 1uL))
+/** \endcond */
+
+/** \} group_ctdac_macros */
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_ctdac_enums
+* \{
+*/
+
+/**
+* Configure the mode for how the DAC value is updated.
+* All the modes require a CTDAC clock except for \ref group_ctdac_updatemode_direct_write.
+*/
+typedef enum {
+ CY_CTDAC_UPDATE_DIRECT_WRITE = 0uL, /**< DAC value is updated with a direct write by calling to \ref Cy_CTDAC_SetValue */
+ CY_CTDAC_UPDATE_BUFFERED_WRITE = 1uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge */
+ CY_CTDAC_UPDATE_STROBE_EDGE_SYNC = 2uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge after a rising edge of the strobe */
+ CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE = 3uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the rising edge of the strobe input */
+ CY_CTDAC_UPDATE_STROBE_LEVEL = 4uL /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on every CTDAC clock edge while the strobe line is high */
+}cy_en_ctdac_update_t;
+
+/**
+* Configure the format in which the DAC value register is decoded.
+*/
+typedef enum {
+ CY_CTDAC_FORMAT_UNSIGNED = 0uL, /**< Unsigned 12-bit DAC. No value decoding */
+ CY_CTDAC_FORMAT_SIGNED = 1uL << CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos /**< Virtual signed. Add 0x800 to the 12-bit DAC value */
+}cy_en_ctdac_format_t;
+
+/**
+* Enable or disable the CTDAC hardware during Deep Sleep.
+*/
+typedef enum {
+ CY_CTDAC_DEEPSLEEP_DISABLE = 0uL, /**< DAC is disabled during Deep Sleep power mode */
+ CY_CTDAC_DEEPSLEEP_ENABLE = CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk /**< DAC remains enabled during Deep Sleep power mode */
+}cy_en_ctdac_deep_sleep_t;
+
+/**
+* Configure the output state of the CTDAC.
+*/
+typedef enum {
+ CY_CTDAC_OUTPUT_HIGHZ = 0uL, /**< DAC output is tri-state */
+ CY_CTDAC_OUTPUT_VALUE = CTDAC_CTDAC_CTRL_OUT_EN_Msk, /**< DAC Output is enabled and drives the programmed value */
+ CY_CTDAC_OUTPUT_VALUE_PLUS1 = CTDAC_CTDAC_CTRL_OUT_EN_Msk \
+ | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk, /**< DAC Output enabled and drives the programmed value plus 1 */
+ CY_CTDAC_OUTPUT_VSSA = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk, /**< Output is pulled to Vssa through a 1.1 MOhm (typ) resistor */
+ CY_CTDAC_OUTPUT_VREF = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk \
+ | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk /**< Output is pulled to Vref through a 1.1 MOhm (typ) resistor */
+}cy_en_ctdac_output_mode_t;
+
+/**
+* Configure the deglitch mode. See the \ref group_ctdac_deglitch section for
+* more information on how deglitching works.
+*/
+typedef enum {
+ CY_CTDAC_DEGLITCHMODE_NONE = 0uL, /**< Disable deglitch */
+ CY_CTDAC_DEGLITCHMODE_UNBUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk, /**< Deglitch through the CO6 switch */
+ CY_CTDAC_DEGLITCHMODE_BUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk, /**< Deglitch through the CTB COS switch */
+ CY_CTDAC_DEGLITCHMODE_BOTH = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk \
+ | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk /**< Deglitch through both CO6 and CTB COS switches */
+}cy_en_ctdac_deglitch_t;
+
+/**
+* Configure the reference source for the CTDAC
+*
+* The CVD switch is closed when Vdda is the reference source.
+*/
+typedef enum {
+ CY_CTDAC_REFSOURCE_EXTERNAL = 0uL, /**< Use an external source from Opamp1 of the CTB as the reference. CVD switch is open. */
+ CY_CTDAC_REFSOURCE_VDDA = 1uL /**< Use Vdda as the reference. CVD switch is closed. */
+}cy_en_ctdac_ref_source_t;
+
+/** Configure the output to be buffered or unbuffered
+*
+* The CO6 switch is closed when the output is unbuffered to Pin 6 of the CTDAC port.
+* See the device datasheet for the CTDAC port.
+*/
+typedef enum {
+ CY_CTDAC_OUTPUT_BUFFERED = 0uL, /**< Buffer the output through the CTB OA0 */
+ CY_CTDAC_OUTPUT_UNBUFFERED = 1uL /**< Send output to a direct pin */
+}cy_en_ctdac_output_buffer_t;
+
+/** Switch state, either open or closed, to be used in \ref Cy_CTDAC_SetAnalogSwitch. */
+typedef enum
+{
+ CY_CTDAC_SWITCH_OPEN = 0uL, /**< Open the switch */
+ CY_CTDAC_SWITCH_CLOSE = 1uL /**< Close the switch */
+}cy_en_ctdac_switch_state_t;
+
+/** Switch mask to be used in \ref Cy_CTDAC_SetAnalogSwitch */
+typedef enum
+{
+ CY_CTDAC_SWITCH_CVD_MASK = CTDAC_CTDAC_SW_CTDD_CVD_Msk, /**< Switch for the reference source, Vdda or external */
+ CY_CTDAC_SWITCH_CO6_MASK = CTDAC_CTDAC_SW_CTDO_CO6_Msk /**< Switch for the output, buffered or direct */
+}cy_en_ctdac_switches_t;
+
+/** Return states for \ref Cy_CTDAC_Init, \ref Cy_CTDAC_DeInit, and \ref Cy_CTDAC_FastInit */
+typedef enum {
+ CY_CTDAC_SUCCESS = 0x00uL, /**< Initialization completed successfully */
+ CY_CTDAC_BAD_PARAM = CY_CTDAC_ID | CY_PDL_STATUS_ERROR | 0x01uL /**< Input pointers were NULL and Initialization could not be completed */
+}cy_en_ctdac_status_t;
+
+/** \} group_ctdac_enums */
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_ctdac_data_structures
+* \{
+*/
+
+/** Configuration structure to set up the entire CTDAC block to be used with \ref Cy_CTDAC_Init
+*/
+typedef struct
+{
+ cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */
+ cy_en_ctdac_format_t formatMode; /**< Format of DAC value: signed or unsigned */
+ cy_en_ctdac_update_t updateMode; /**< Update mode: direct or buffered writes or hardware, edge or level */
+ cy_en_ctdac_deglitch_t deglitchMode; /**< Deglitch mode: disabled, buffered, unbuffered, or both */
+ cy_en_ctdac_output_mode_t outputMode; /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */
+ cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */
+ cy_en_ctdac_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */
+ uint32_t deglitchCycles; /**< Number of deglitch cycles from 0 to 63 */
+ int32_t value; /**< Current DAC value */
+ int32_t nextValue; /**< Next DAC value for double buffering */
+ bool enableInterrupt; /**< If true, enable interrupt when next value register is transferred to value register */
+
+ /* Configuring the clock */
+ bool configClock; /**< Configure or ignore clock information */
+ cy_en_divider_types_t dividerType; /**< Specifies which type of divider to use. Can be integer or fractional divider. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */
+ uint32_t dividerNum; /**< Specifies which divider of the selected type to configure. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */
+ uint32_t dividerIntValue; /**< The integer divider value. The divider value causes integer division of (divider value + 1). Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */
+ uint32_t dividerFracValue; /**< The fractional divider value if using a fractional clock. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */
+}cy_stc_ctdac_config_t;
+
+/** Configuration structure to quickly set up the CTDAC to be used with \ref Cy_CTDAC_FastInit
+* This structure provides a selection for the CTDAC reference source and output path.
+*
+* The other configuration options are set to:
+* - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED
+* - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE
+* - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE
+* - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE
+* - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE
+* - .deglitchCycles = \ref CY_CTDAC_DEINIT
+* - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
+* - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE
+* - .enableInterrupt = true
+* - .configClock = true
+* - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE
+* - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM
+* - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV
+* - .dividerFracValue = \ref CY_CTDAC_DEINIT
+*/
+typedef struct
+{
+ cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */
+ cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */
+}cy_stc_ctdac_fast_config_t;
+
+/** \} group_ctdac_data_structures */
+
+/** \addtogroup group_ctdac_globals
+* \{
+*/
+/***************************************
+* Global Variables
+***************************************/
+
+/** Configure CTDAC to use Vdda reference and output unbuffered. See \ref Cy_CTDAC_FastInit. */
+extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut;
+
+/** Configure CTDAC to use Vdda reference and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit.
+*
+* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit
+* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH.
+*/
+extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut;
+
+/** Configure CTDAC to use a buffered reference from Opamp1 of CTB
+* and output unbuffered. See \ref Cy_CTDAC_FastInit.
+*
+* To use the reference from the Analog Reference (AREF),
+* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref.
+*
+* To use an external reference from a GPIO,
+* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
+* for Pin 5 on the CTB port.
+*/
+extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut;
+
+/** Configure CTDAC to use a buffered reference from Opamp1 of CTB
+* and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit.
+*
+* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit
+* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH.
+*
+* To use the reference from the Analog Reference (AREF),
+* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref.
+*
+* To use an external reference from a GPIO,
+* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
+* for Pins 5 on the CTB port.
+*/
+extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut;
+
+/** \} group_ctdac_globals */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_ctdac_functions
+* \{
+*/
+
+/**
+* \addtogroup group_ctdac_functions_init
+* This set of functions are for initializing, enabling, and disabling the CTDAC.
+* \{
+*/
+cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config);
+cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting);
+cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config);
+__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base);
+__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base);
+/** \} */
+
+/**
+* \addtogroup group_ctdac_functions_basic
+* This set of functions are for configuring basic usage of the CTDAC.
+* \{
+*/
+__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value);
+__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value);
+void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode);
+void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep);
+void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode);
+void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode);
+void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles);
+void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource);
+/** \} */
+
+/** \addtogroup group_ctdac_functions_switches
+*
+* This set of functions is for controlling the two CTDAC analog switches, CVD, and CO6.
+* These are advanced functions. The switches will be managed by the reference
+* source and output mode selections when initializing the hardware.
+* \{
+*/
+void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state);
+__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base);
+__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state);
+__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base);
+/** \} */
+
+/** \addtogroup group_ctdac_functions_interrupts
+* This set of functions is related to the CTDAC interrupt
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base);
+__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base);
+__STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base);
+__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask);
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base);
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base);
+/** \} */
+
+/** \addtogroup group_ctdac_functions_syspm_callback
+* This driver supports one SysPm callback for Deep Sleep transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} */
+
+/**
+* \addtogroup group_ctdac_functions_init
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_CTDAC_Enable
+****************************************************************************//**
+*
+* Power up the CTDAC hardware block.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base)
+{
+ base->CTDAC_CTRL |= CTDAC_CTDAC_CTRL_ENABLED_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_Disable
+****************************************************************************//**
+*
+* Turn off the hardware block.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base)
+{
+ base->CTDAC_CTRL &= ~CTDAC_CTDAC_CTRL_ENABLED_Msk;
+}
+/** \} */
+
+/**
+* \addtogroup group_ctdac_functions_basic
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetValue
+****************************************************************************//**
+*
+* Set the CTDAC_VAL register (DAC hardware is
+* updated on the next PeriClk cycle). Only the least significant 12 bits
+* have an effect. Sign extension of negative values is unnecessary and is
+* ignored by the hardware. The way in which the CTDAC interprets the 12-bit
+* data is controlled by \ref Cy_CTDAC_SetSignMode.
+*
+* \note
+* Call this function only when the update mode is set to \ref group_ctdac_updatemode_direct_write.
+* Calling this function for any other update mode will not have the intended effect.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param value
+* Value to write into the CTDAC_VAL register
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value)
+{
+ base->CTDAC_VAL = (((uint32_t)value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetValueBuffered
+****************************************************************************//**
+*
+* Set the CTDAC_VAL_NEXT register. The value is transferred
+* to the CTDAC_VAL register on the next edge of the CTDAC clock.
+* Only the least significant 12 bits
+* have an effect. Sign extension of negative values is unnecessary and is
+* ignored by the hardware. The way in which the CTDAC interprets the 12-bit
+* data is controlled by \ref Cy_CTDAC_SetSignMode.
+*
+* \note
+* Calling this function in \ref group_ctdac_updatemode_direct_write mode will not update the DAC output.
+* Call this function for all modes that use buffered values (i.e. uses a clock).
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param value
+* Value to write into the CTDAC_VAL_NEXT register
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE_BUFFERED
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value)
+{
+ base->CTDAC_VAL_NXT = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk;
+}
+/** \} */
+
+/**
+* \addtogroup group_ctdac_functions_switches
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_CTDAC_GetAnalogSwitch
+****************************************************************************//**
+*
+* Return the state (open or close) of the CTDAC switches.
+*
+* \note
+* The switches will be managed by the reference
+* source and output mode selections when initializing the hardware.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Switch state. Compare this value to the masks found in \ref cy_en_ctdac_switches_t.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base)
+{
+ return base->CTDAC_SW;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetSwitchCO6
+****************************************************************************//**
+*
+* Open or close switch CO6 that controls whether the output gets routed
+* directly to a pin or through Opamp0 of the CTB. This function calls
+* \ref Cy_CTDAC_SetAnalogSwitch with the switchMask set to \ref CY_CTDAC_SWITCH_CO6_MASK.
+*
+* \note
+* The switches is configured by the output mode selections during initialization.
+*
+* \note
+* This switch will temporarily
+* be opened for deglitching if the degitch mode is \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED or
+* \ref CY_CTDAC_DEGLITCHMODE_BOTH.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param state
+* State of the switch, open or close.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SWITCH_CO6
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state)
+{
+ Cy_CTDAC_SetAnalogSwitch(base, (uint32_t) CY_CTDAC_SWITCH_CO6_MASK, state);
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_OpenAllSwitches
+****************************************************************************//**
+*
+* Open all switches in the CTDAC (CO6 and CVD).
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_OPEN_ALL_SWITCHES
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base)
+{
+ base->CTDAC_SW_CLEAR = CY_CTDAC_DEINT_CTDAC_SW;
+}
+
+/** \} */
+
+/**
+* \addtogroup group_ctdac_functions_interrupts
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_CTDAC_GetInterruptStatus
+****************************************************************************//**
+*
+* Return the interrupt status which gets set by the hardware
+* when the CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register.
+* Once set, the CTDAC_VAL_NXT register is ready to accept a new value.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL
+* - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_GET_INTERRUPT_STATUS
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base)
+{
+ return (base->INTR & CTDAC_INTR_VDAC_EMPTY_Msk) >> CTDAC_INTR_VDAC_EMPTY_Pos;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_ClearInterrupt
+****************************************************************************//**
+*
+* Clear the interrupt that was set by the hardware when the
+* CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register.
+* The interrupt must be cleared with this function so that
+* the hardware can set subsequent interrupts and those interrupts
+* can be forwarded to the interrupt controller, if enabled.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base)
+{
+ base->INTR = CTDAC_INTR_VDAC_EMPTY_Msk;
+
+ /* Dummy read for buffered writes. */
+ (void) base->INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetInterrupt
+****************************************************************************//**
+*
+* Force the CTDAC interrupt to trigger using software.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base)
+{
+ base->INTR_SET = CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_SetInterruptMask
+****************************************************************************//**
+*
+* Configure the CTDAC interrupt to be forwarded to the CPU interrupt
+* controller.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param mask
+* The CTDAC only has one interrupt so the mask is one bit.
+* - 0: Disable CTDAC interrupt request (will not be forwarded to CPU interrupt controller)
+* - 1: Enable CTDAC interrupt request (will be forwarded to CPU interrupt controller)
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_SET_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask)
+{
+ CY_ASSERT_L2(CY_CTDAC_INTRMASK(mask));
+
+ base->INTR_MASK = mask & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_GetInterruptMask
+****************************************************************************//**
+*
+* Return whether the CTDAC interrupt is
+* forwarded to the CPU interrupt controller
+* as configured by \ref Cy_CTDAC_SetInterruptMask.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* The CTDAC only has one interrupt so the return value is either 0 or 1.
+* - 0: Interrupt output not forwarded to CPU interrupt controller
+* - 1: Interrupt output forwarded to CPU interrupt controller
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base)
+{
+ return (base->INTR_MASK & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk) >> CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos;
+}
+
+/*******************************************************************************
+* Function Name: Cy_CTDAC_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the bitwise AND of \ref Cy_CTDAC_GetInterruptStatus and
+* \ref Cy_CTDAC_SetInterruptMask. When high, the DAC interrupt is
+* asserted and the interrupt is forwarded to the CPU interrupt
+* controller.
+*
+* \note
+* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL or not masked
+* - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL and masked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base){
+ return (base->INTR_MASKED & CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk) >> CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos;
+}
+
+/** \} */
+
+/** \} group_ctdac_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /** !defined(CY_CTDAC_H) */
+
+/** \} group_ctdac */
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,353 @@
+/***************************************************************************//**
+* \file cy_dma.c
+* \version 2.0.1
+*
+* \brief
+* The source code file for the DMA driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_dma.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_Init
+****************************************************************************//**
+*
+* Initializes the descriptor structure in SRAM from a pre-initialized
+* configuration structure.
+* This function initializes only the descriptor and not the channel.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param config
+* This is a configuration structure that has all initialization information for
+* the descriptor.
+*
+* \return
+* The status /ref cy_en_dma_status_t.
+*
+*******************************************************************************/
+cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, const cy_stc_dma_descriptor_config_t * config)
+{
+ cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM;
+
+ if ((NULL != descriptor) && (NULL != config))
+ {
+ CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(config->retrigger));
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->interruptType));
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerOutType));
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerInType));
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->srcTransferSize));
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->dstTransferSize));
+ CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState));
+ CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize));
+ CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(config->descriptorType));
+
+ descriptor->ctl =
+ _VAL2FLD(CY_DMA_CTL_RETRIG, config->retrigger) |
+ _VAL2FLD(CY_DMA_CTL_INTR_TYPE, config->interruptType) |
+ _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, config->triggerOutType) |
+ _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, config->triggerInType) |
+ _VAL2FLD(CY_DMA_CTL_SRC_SIZE, config->srcTransferSize) |
+ _VAL2FLD(CY_DMA_CTL_DST_SIZE, config->dstTransferSize) |
+ _VAL2FLD(CY_DMA_CTL_CH_DISABLE, config->channelState) |
+ _VAL2FLD(CY_DMA_CTL_DATA_SIZE, config->dataSize) |
+ _VAL2FLD(CY_DMA_CTL_TYPE, config->descriptorType);
+
+ descriptor->src = (uint32_t)config->srcAddress;
+
+ descriptor->dst = (uint32_t)config->dstAddress;
+
+ switch(config->descriptorType)
+ {
+ case CY_DMA_SINGLE_TRANSFER:
+ {
+ descriptor->xCtl = (uint32_t)config->nextDescriptor;
+ break;
+ }
+ case CY_DMA_1D_TRANSFER:
+ {
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement));
+ CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount));
+
+ descriptor->xCtl =
+ _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
+ _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
+
+ descriptor->yCtl = (uint32_t)config->nextDescriptor;
+ break;
+ }
+ case CY_DMA_2D_TRANSFER:
+ {
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement));
+ CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcYincrement));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstYincrement));
+ CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->yCount));
+
+ descriptor->xCtl =
+ _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
+ _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
+
+ descriptor->yCtl =
+ _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) |
+ _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) |
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ _VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL);
+
+ descriptor->nextPtr = (uint32_t)config->nextDescriptor;
+ break;
+ }
+ default:
+ {
+ /* An unsupported type of a descriptor */
+ break;
+ }
+ }
+
+ retVal = CY_DMA_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_DeInit
+****************************************************************************//**
+*
+* Clears the content of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+*******************************************************************************/
+void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor)
+{
+ descriptor->ctl = 0UL;
+ descriptor->src = 0UL;
+ descriptor->dst = 0UL;
+ descriptor->xCtl = 0UL;
+ descriptor->yCtl = 0UL;
+ descriptor->nextPtr = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_Init
+****************************************************************************//**
+*
+* Initializes the DMA channel with a descriptor and other parameters.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* A channel number.
+*
+* \param channelConfig
+* The structure that has the initialization information for the
+* channel.
+*
+* \return
+* The status /ref cy_en_dma_status_t.
+*
+*******************************************************************************/
+cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig)
+{
+ cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM;
+
+ if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor)))
+ {
+ CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority));
+
+ /* Set the current descriptor */
+ base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor;
+
+ /* Set the channel configuration */
+ base->CH_STRUCT[channel].CH_CTL = _BOOL2FLD(DW_CH_STRUCT_CH_CTL_PREEMPTABLE, channelConfig->preemptable) |
+ _VAL2FLD(DW_CH_STRUCT_CH_CTL_PRIO, channelConfig->priority) |
+ _BOOL2FLD(DW_CH_STRUCT_CH_CTL_ENABLED, channelConfig->enable) |
+ _BOOL2FLD(DW_CH_STRUCT_CH_CTL_B, channelConfig->bufferable);
+ retVal = CY_DMA_SUCCESS;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_DeInit
+****************************************************************************//**
+*
+* Clears the content of registers corresponding to the channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* A channel number.
+*
+*******************************************************************************/
+void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ base->CH_STRUCT[channel].CH_CTL = 0UL;
+ base->CH_STRUCT[channel].CH_IDX = 0UL;
+ base->CH_STRUCT[channel].CH_CURR_PTR = 0UL;
+ base->CH_STRUCT[channel].INTR_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetNextDescriptor
+****************************************************************************//**
+*
+* Sets a Next Descriptor parameter for the specified descriptor.
+*
+* Based on the descriptor type, the offset of the address for the next descriptor may
+* vary. For the single-transfer descriptor type, this register is at offset 0x0c.
+* For the 1D-transfer descriptor type, this register is at offset 0x10.
+* For the 2D-transfer descriptor type, this register is at offset 0x14.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param nextDescriptor
+* The pointer to the next descriptor.
+*
+*******************************************************************************/
+void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl))
+ {
+ case CY_DMA_SINGLE_TRANSFER:
+ descriptor->xCtl = (uint32_t)nextDescriptor;
+ break;
+
+ case CY_DMA_1D_TRANSFER:
+ descriptor->yCtl = (uint32_t)nextDescriptor;
+ break;
+
+ case CY_DMA_2D_TRANSFER:
+ descriptor->nextPtr = (uint32_t)nextDescriptor;
+ break;
+
+ default:
+ /* Unsupported type of descriptor */
+ break;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetNextDescriptor
+****************************************************************************//**
+*
+* Returns a next descriptor address of the specified descriptor.
+*
+* Based on the descriptor type, the offset of the address for the next descriptor may
+* vary. For a single-transfer descriptor type, this register is at offset 0x0c.
+* For the 1D-transfer descriptor type, this register is at offset 0x10.
+* For the 2D-transfer descriptor type, this register is at offset 0x14.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The pointer to the next descriptor.
+*
+*******************************************************************************/
+cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descriptor_t const * descriptor)
+{
+ cy_stc_dma_descriptor_t * retVal = NULL;
+
+ CY_ASSERT_L1(NULL != descriptor);
+
+ switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl))
+ {
+ case CY_DMA_SINGLE_TRANSFER:
+ retVal = (cy_stc_dma_descriptor_t*) descriptor->xCtl;
+ break;
+
+ case CY_DMA_1D_TRANSFER:
+ retVal = (cy_stc_dma_descriptor_t*) descriptor->yCtl;
+ break;
+
+ case CY_DMA_2D_TRANSFER:
+ retVal = (cy_stc_dma_descriptor_t*) descriptor->nextPtr;
+ break;
+
+ default:
+ /* An unsupported type of the descriptor */
+ break;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDescriptorType
+****************************************************************************//**
+*
+* Sets the descriptor's type for the specified descriptor.
+* Moves the next descriptor register value into the proper place in accordance
+* to the actual descriptor type.
+* During the descriptor's type changing, the Xloop and Yloop settings, such as
+* data count and source/destination increment (i.e. the content of the
+* xCtl and yCtl descriptor registers) might be lost (overriden by the
+* next descriptor value) because of the different descriptor registers structures
+* for different descriptor types. Set up carefully the Xloop
+* (and Yloop, if used) data count and source/destination increment if the
+* descriptor type is changed from a simpler to a more complicated type
+* ("single transfer" -> "1D", "1D" -> "2D", etc.).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param descriptorType
+* The descriptor type \ref cy_en_dma_descriptor_type_t.
+*
+*******************************************************************************/
+void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType));
+
+ if (descriptorType != Cy_DMA_Descriptor_GetDescriptorType(descriptor)) /* Don't perform if the type is not changed */
+ {
+ /* Store the current nextDescriptor pointer. */
+ cy_stc_dma_descriptor_t * locNextDescriptor = Cy_DMA_Descriptor_GetNextDescriptor(descriptor);
+ /* Change the descriptor type. */
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType);
+ /* Restore the nextDescriptor pointer into the proper place. */
+ Cy_DMA_Descriptor_SetNextDescriptor(descriptor, locNextDescriptor);
+ }
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1810 @@
+/***************************************************************************//**
+* \file cy_dma.h
+* \version 2.0.1
+*
+* \brief
+* The header file of the DMA driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_dma Direct Memory Access (DMA)
+* \{
+* Configures a DMA channel and its descriptor(s).
+*
+* The DMA channel can be used in any project to transfer data
+* without CPU intervention basing on a hardware trigger signal from another component.
+*
+* A device may support more than one DMA hardware block. Each block has a set of
+* registers, a base hardware address, and supports multiple channels.
+* Many API functions for the DMA driver require a base hardware address and
+* channel number. Ensure that you use the correct hardware address for the DMA block in use.
+*
+* Features:
+* * Devices support up to two DMA hardware blocks
+* * Each DMA block supports up to 16 DMA channels
+* * Supports channel descriptors in SRAM
+* * Four priority levels for each channel
+* * Byte, half-word (2-byte), and word (4-byte) transfers
+* * Configurable source and destination addresses
+*
+* \section group_dma_configuration Configuration Considerations
+*
+* To set up a DMA driver, initialize a descriptor,
+* intialize and enable a channel, and enable the DMA block.
+*
+* To set up a descriptor, provide the configuration parameters for the
+* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
+* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
+* modify the source and destination addresses dynamically by calling
+* \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress.
+*
+* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
+* structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel
+* number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel.
+*
+* Call \ref Cy_DMA_Channel_Enable for each DMA channel in use.
+*
+* When configured, another peripheral typically triggers the DMA. The trigger is
+* connected to the DMA using the trigger multiplexer. The trigger multiplexer
+* driver has a software trigger you can use in firmware to trigger the DMA. See the
+* <a href="group__group__trigmux.html">Trigger Multiplexer</a> documentation.
+*
+* The following is a simplified structure of the DMA driver API interdependencies
+* in a typical user application:
+* \image html dma.png
+*
+* <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
+* the DMA block is enabled using function \ref Cy_DMA_Enable.\n
+* <B>NOTE:</B> if the DMA descriptor is configured to generate an interrupt,
+* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
+* function for each DMA channel.
+*
+* For example:
+* \snippet dma/dma_v2_0_sut_00.cydsn/main_cm4.c Cy_DMA_Snippet
+*
+* \section group_dma_more_information More Information.
+* See: the DMA chapter of the device technical reference manual (TRM);
+* the DMA Component datasheet;
+* CE219940 - PSoC 6 MCU Multiple DMA Concatenation.
+*
+* \section group_dma_MISRA MISRA-C Compliance
+* The DMA driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite expression of the "essentially unsigned" type is being
+* cast to a different type category.</td>
+* <td>The value got from the bitfield physically cannot exceed the enumeration
+* that describes this bitfield. So, the code is safe by design.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements will either:
+* a) have at least one-side effect however executed;
+* b) cause the control flow to change</td>
+* <td>A Read operation result is ignored when this read is just intended
+* to ensure the previous Write operation is flushed out to the hardware.</td>
+* </tr>
+* </table>
+*
+* \section group_dma_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.0.1</td>
+* <td>Changed \ref CY_DMA_BWC macro values from Boolean to numeric</td>
+* <td>Improvements made based on usability feedback</td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>* All the API is refactored to be consistent within itself and with the
+* rest of the PDL content.
+* * The descriptor API is updated as follows:
+* The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor
+* settings, and the rest of the descriptor API is a get/set interface
+* to each of the descriptor settings.
+* * There is a group of macros to support the backward compatibility with most
+* of the driver version 1.0 API. But, it is strongly recommended to use
+* the new v2.0 interface in new designs (do not just copy-paste from old
+* projects). To enable the backward compatibility support, the CY_DMA_BWC
+* definition should be changed to "1".</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+
+* \defgroup group_dma_macros Macros
+* \defgroup group_dma_functions Functions
+* \{
+* \defgroup group_dma_block_functions Block Functions
+* \defgroup group_dma_descriptor_functions Descriptor Functions
+* \defgroup group_dma_channel_functions Channel Functions
+* \}
+* \defgroup group_dma_data_structures Data Structures
+* \defgroup group_dma_enums Enumerated Types
+*/
+
+#if !defined(CY_DMA_H)
+#define CY_DMA_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+
+#ifndef CY_IP_M4CPUSS_DMA
+ #error "The DMA driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+
+/**
+* \addtogroup group_dma_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_DMA_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_DMA_DRV_VERSION_MINOR 0
+
+/** The DMA driver identifier */
+#define CY_DMA_ID (CY_PDL_DRV_ID(0x13U))
+
+/** The DMA channel interrupt mask */
+#define CY_DMA_INTR_MASK (0x01UL)
+
+/** The backward compatibility flag. Enables a group of macros which provide
+* the backward compatibility with most of the DMA driver version 1.0 interface. */
+#ifndef CY_DMA_BWC
+ #define CY_DMA_BWC (0U)
+#endif
+
+/** \} group_dma_macros */
+
+
+/**
+* \addtogroup group_dma_enums
+* \{
+*/
+
+/** Contains the possible interrupt cause values */
+typedef enum
+{
+ CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt */
+ CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion */
+ CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error */
+ CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error */
+ CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned */
+ CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned */
+ CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descripror pointer is NULL */
+ CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled */
+ CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error */
+} cy_en_dma_intr_cause_t;
+
+/** Contains the options for the descriptor type */
+typedef enum
+{
+ CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */
+ CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */
+ CY_DMA_2D_TRANSFER = 2UL /**< 2D transfer. */
+} cy_en_dma_descriptor_type_t;
+
+/** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */
+typedef enum
+{
+ CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */
+ CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */
+ CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */
+ CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */
+} cy_en_dma_trigger_type_t;
+
+/** This enum has the options for the data size */
+typedef enum
+{
+ CY_DMA_BYTE = 0UL, /**< One byte */
+ CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes) */
+ CY_DMA_WORD = 2UL /**< Full word (four bytes) */
+} cy_en_dma_data_size_t;
+
+/** This enum has the options for descriptor retriggering */
+typedef enum
+{
+ CY_DMA_RETRIG_IM = 0UL, /**< Retrigger immediatelly */
+ CY_DMA_RETRIG_4CYC = 1UL, /**< Retrigger after 4 Clk_Slow cycles */
+ CY_DMA_RETRIG_16CYC = 2UL, /**< Retrigger after 16 Clk_Slow cycles */
+ CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation */
+} cy_en_dma_retrigger_t;
+
+/** This enum has the options for the transfer size */
+typedef enum
+{
+ CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */
+ CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */
+} cy_en_dma_transfer_size_t;
+
+/** This enum has the options for the state of the channel when the descriptor is completed */
+typedef enum
+{
+ CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled */
+ CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled */
+} cy_en_dma_channel_state_t;
+
+/** This enum has the return values of the DMA driver */
+typedef enum
+{
+ CY_DMA_SUCCESS = 0x00UL, /**< Success. */
+ CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */
+} cy_en_dma_status_t;
+
+/** \} group_dma_enums */
+
+
+/** \cond Macros for the conditions used by CY_ASSERT calls */
+
+#define CY_DMA_IS_COUNT_VALID(count) (((count) >= 1UL) && ((count) <= 256UL))
+#define CY_DMA_IS_INCR_VALID(incr) (((incr) >= -2048L) && ((incr) <= 2047L))
+#define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL)
+#define CY_DMA_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_DMA_INTR_MASK)))
+
+#define CY_DMA_IS_RETRIGGER_VALID(retrigger) ((CY_DMA_RETRIG_IM == (retrigger)) || \
+ (CY_DMA_RETRIG_4CYC == (retrigger)) || \
+ (CY_DMA_RETRIG_16CYC == (retrigger)) || \
+ (CY_DMA_WAIT_FOR_REACT == (retrigger)))
+
+#define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \
+ (CY_DMA_X_LOOP == (trigType)) || \
+ (CY_DMA_DESCR == (trigType)) || \
+ (CY_DMA_DESCR_CHAIN == (trigType)))
+
+#define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \
+ (CY_DMA_TRANSFER_SIZE_WORD == (xferSize)))
+
+#define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \
+ (CY_DMA_CHANNEL_DISABLED == (state)))
+
+#define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \
+ (CY_DMA_HALFWORD == (dataSize)) || \
+ (CY_DMA_WORD == (dataSize)))
+
+#define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \
+ (CY_DMA_1D_TRANSFER == (descrType)) || \
+ (CY_DMA_2D_TRANSFER == (descrType)))
+
+#define CY_DMA_IS_DW_CH_NR_VALID(dwNr, chNr) (((0U != CPUSS_DW0_PRESENT) && (DW0 == (dwNr)) && ((chNr) < CPUSS_DW0_CH_NR)) || \
+ ((0U != CPUSS_DW1_PRESENT) && (DW1 == (dwNr)) && ((chNr) < CPUSS_DW1_CH_NR)))
+
+/* The descriptor structure bit-filed definitions */
+#define CY_DMA_CTL_RETRIG_Pos 0UL
+#define CY_DMA_CTL_RETRIG_Msk 0x3UL
+#define CY_DMA_CTL_INTR_TYPE_Pos 2UL
+#define CY_DMA_CTL_INTR_TYPE_Msk 0xCUL
+#define CY_DMA_CTL_TR_OUT_TYPE_Pos 4UL
+#define CY_DMA_CTL_TR_OUT_TYPE_Msk 0x30UL
+#define CY_DMA_CTL_TR_IN_TYPE_Pos 6UL
+#define CY_DMA_CTL_TR_IN_TYPE_Msk 0xC0UL
+#define CY_DMA_CTL_CH_DISABLE_Pos 24UL
+#define CY_DMA_CTL_CH_DISABLE_Msk 0x1000000UL
+#define CY_DMA_CTL_SRC_SIZE_Pos 26UL
+#define CY_DMA_CTL_SRC_SIZE_Msk 0x4000000UL
+#define CY_DMA_CTL_DST_SIZE_Pos 27UL
+#define CY_DMA_CTL_DST_SIZE_Msk 0x8000000UL
+#define CY_DMA_CTL_DATA_SIZE_Pos 28UL
+#define CY_DMA_CTL_DATA_SIZE_Msk 0x30000000UL
+#define CY_DMA_CTL_TYPE_Pos 30UL
+#define CY_DMA_CTL_TYPE_Msk 0xC0000000UL
+
+#define CY_DMA_CTL_SRC_INCR_Pos 0UL
+#define CY_DMA_CTL_SRC_INCR_Msk 0xFFFUL
+#define CY_DMA_CTL_DST_INCR_Pos 12UL
+#define CY_DMA_CTL_DST_INCR_Msk 0xFFF000UL
+#define CY_DMA_CTL_COUNT_Pos 24UL
+#define CY_DMA_CTL_COUNT_Msk 0xFF000000UL
+
+/** \endcond */
+
+
+/**
+* \addtogroup group_dma_data_structures
+* \{
+*/
+
+/**
+* DMA descriptor structure type. It is a user/component-declared structure
+* allocated in RAM. The DMA HW requires a pointer to this structure to work with it.
+*
+* For advanced users: the descriptor can be allocated even in Flash, then the user
+* manually predefines all the structure items with constants,
+* bacause most of the driver's API (especially functions modifying
+* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
+* read-only descriptors.
+*/
+typedef struct
+{
+ uint32_t ctl; /*!< 0x00000000 Descriptor control */
+ uint32_t src; /*!< 0x00000004 Descriptor source */
+ uint32_t dst; /*!< 0x00000008 Descriptor destination */
+ uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */
+ uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */
+ uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */
+} cy_stc_dma_descriptor_t;
+
+/**
+* This structure is a configuration structure pre-initialized by the user and
+* passed as a parameter to the \ref Cy_DMA_Descriptor_Init().
+* It can be allocated in RAM/Flash (on user's choice).
+* In case of Flash allocation there is a possibility to reinitialize the descriptor in runtime.
+* This structure has all the parameters of the descriptor as separate parameters.
+* Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bit fields.
+*/
+typedef struct
+{
+ cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */
+ cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt, see \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output, see \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_channel_state_t channelState; /**< Specifies if the channel is enabled or disabled on completion of descriptor see \ref cy_en_dma_channel_state_t. */
+ cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered, see \ref cy_en_dma_trigger_type_t. */
+ cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer, see \ref cy_en_dma_data_size_t. */
+ cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */
+ cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */
+ cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor see \ref cy_en_dma_descriptor_type_t. */
+ void * srcAddress; /**< The source address of the transfer. */
+ void * dstAddress; /**< The destination address of the transfer. */
+ int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048...2047. */
+ int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048...2047. */
+ uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1...256. */
+ int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048...2047. */
+ int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048...2047. */
+ uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1...256. */
+ cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion, a NULL value will signify no chaining. */
+} cy_stc_dma_descriptor_config_t;
+
+/** This structure holds the initialization values for the DMA channel */
+typedef struct
+{
+ cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized */
+ bool preemptable; /**< Specifies if the channel is preemptable by another higher-priority channel */
+ uint32_t priority; /**< This parameter specifies the channel's priority */
+ bool enable; /**< This parameter specifies if the channel is enabled after initializing */
+ bool bufferable; /**< This parameter specifies whether a write transaction can complete
+ without waiting for the destination to accept the write transaction data. */
+} cy_stc_dma_channel_config_t;
+
+/** \} group_dma_data_structures */
+
+
+/**
+* \addtogroup group_dma_functions
+* \{
+*/
+
+__STATIC_INLINE void Cy_DMA_Enable (DW_Type * base);
+__STATIC_INLINE void Cy_DMA_Disable (DW_Type * base);
+__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base);
+__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base);
+__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base);
+
+
+/**
+* \addtogroup group_dma_descriptor_functions
+* \{
+*/
+
+ cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config);
+ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor);
+
+ void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor);
+ void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger);
+__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState);
+
+ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor);
+
+/** \} group_dma_descriptor_functions */
+
+
+/**
+* \addtogroup group_dma_channel_functions
+* \{
+*/
+
+ cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig);
+ void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor);
+__STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel);
+__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel);
+
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel);
+__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel);
+
+/** \} group_dma_channel_functions */
+
+
+/***************************************
+* In-line Function Implementation
+***************************************/
+
+
+/**
+* \addtogroup group_dma_block_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Enable
+****************************************************************************//**
+*
+* Enables the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Enable(DW_Type * base)
+{
+ base->CTL |= DW_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Disable
+****************************************************************************//**
+*
+* Disables the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Disable(DW_Type * base)
+{
+ base->CTL &= (uint32_t) ~DW_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveChannel
+****************************************************************************//**
+*
+* Returns the status of the active/pending channels.
+* the DMA block.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns a bit-field with all of the currently active/pending channels in the
+* DMA block.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base)
+{
+ return(_FLD2VAL(DW_STATUS_CH_IDX, base->STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveSrcAddress
+****************************************************************************//**
+*
+* Returns the source address being used for the current transfer.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns the pointer to the source of transfer.
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base)
+{
+ return ((void *)base->ACT_DESCR_SRC);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_GetActiveDstAddress
+****************************************************************************//**
+*
+* Returns the destination address being used for the current transfer.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \return
+* Returns the pointer to the destination of transfer.
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base)
+{
+ return ((void *) base->ACT_DESCR_DST);
+}
+
+/** \} group_dma_block_functions */
+
+
+/**
+* \addtogroup group_dma_descriptor_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetSrcAddress
+****************************************************************************//**
+*
+* Sets the source address parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcAddress
+* The source address value for the descriptor.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress)
+{
+ descriptor->src = (uint32_t) srcAddress;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetSrcAddress
+****************************************************************************//**
+*
+* Returns the source address parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The source address value of the descriptor.
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return ((void *) descriptor->src);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDstAddress
+****************************************************************************//**
+*
+* Sets the destination address parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstAddress
+* The destination address value for the descriptor.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress)
+{
+ descriptor->dst = (uint32_t) dstAddress;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDstAddress
+****************************************************************************//**
+*
+* Returns the destination address parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The destination address value of the descriptor.
+*
+*******************************************************************************/
+__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)
+{
+ return ((void *) descriptor->dst);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetInterruptType
+****************************************************************************//**
+*
+* Sets the interrupt type parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param interruptType
+* The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetInterruptType
+****************************************************************************//**
+*
+* Returns the Interrupt-Type of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Interrupt-Type \ref cy_en_dma_trigger_type_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetTriggerInType
+****************************************************************************//**
+*
+* Sets the Trigger-In-Type parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param triggerInType
+* The Trigger In Type parameter \ref cy_en_dma_trigger_type_t
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetTriggerInType
+****************************************************************************//**
+*
+* Returns the Trigger-In-Type parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Trigger-In-Type \ref cy_en_dma_trigger_type_t
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetTriggerOutType
+****************************************************************************//**
+*
+* Sets the Trigger-Out-Type parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param triggerOutType
+* The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetTriggerOutType
+****************************************************************************//**
+*
+* Returns the Trigger-Out-Type parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDataSize
+****************************************************************************//**
+*
+* Sets the Data Element Size parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dataSize
+* The Data Element Size \ref cy_en_dma_data_size_t
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDataSize
+****************************************************************************//**
+*
+* Returns the Data Element Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Data Element Size \ref cy_en_dma_data_size_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetSrcTransferSize
+****************************************************************************//**
+*
+* Sets the Source Transfer Size parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcTransferSize
+* The Source Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetSrcTransferSize
+****************************************************************************//**
+*
+* Returns the Source Transfer Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Source Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetDstTransferSize
+****************************************************************************//**
+*
+* Sets the Destination Transfer Size parameter for the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstTransferSize
+* The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDstTransferSize
+****************************************************************************//**
+*
+* Returns the Destination Transfer Size parameter of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Destination Transfer Size \ref cy_en_dma_transfer_size_t
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetRetrigger
+****************************************************************************//**
+*
+* Sets the retrigger value which specifies whether the controller should
+* wait for the input trigger to be deactivated.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param retrigger
+* The \ref cy_en_dma_retrigger_t parameter specifies whether the controller
+* should wait for the input trigger to be deactivated.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(retrigger));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetRetrigger
+****************************************************************************//**
+*
+* Returns a value which specifies whether the controller should
+* wait for the input trigger to be deactivated.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Retrigger setting \ref cy_en_dma_retrigger_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetDescriptorType
+****************************************************************************//**
+*
+* Returns the descriptor's type of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The descriptor type \ref cy_en_dma_descriptor_type_t
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetChannelState
+****************************************************************************//**
+*
+* Sets the channel state on completion of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param channelState
+* The channel state \ref cy_en_dma_channel_state_t.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState));
+
+ descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetChannelState
+****************************************************************************//**
+*
+* Returns the channel state on completion of the specified descriptor.
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The Channel State setting \ref cy_en_dma_channel_state_t
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+
+ return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopDataCount
+****************************************************************************//**
+*
+* Sets the number of data elements to transfer in the X loop
+* for the specified descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param xCount
+* The number of data elements to transfer in the X loop.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(xCount));
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopDataCount
+****************************************************************************//**
+*
+* Returns the number of data elements for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The number of data elements to transfer in the X loop.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
+ return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl) + 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement
+****************************************************************************//**
+*
+* Sets the source increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcXincrement
+* The value of the source increment. The valid range is -2048 ... 2047.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcXincrement));
+
+ descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement
+****************************************************************************//**
+*
+* Returns the source increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the source increment.
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement
+****************************************************************************//**
+*
+* Sets the destination increment parameter for the X loop for the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstXincrement
+* The value of the destination increment. The valid range is -2048 ... 2047.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstXincrement));
+
+ descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement
+****************************************************************************//**
+*
+* Returns the destination increment parameter for the X loop of the specified
+* descriptor (for 1D or 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the destination increment.
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopDataCount
+****************************************************************************//**
+*
+* Sets the number of data elements for the Y loop of the specified descriptor
+* (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param yCount
+* The number of X loops to execute in the Y loop.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(yCount));
+ /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
+ descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopDataCount
+****************************************************************************//**
+*
+* Returns the number of X loops to execute in the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The number of X loops to execute in the Y loop.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
+ return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl) + 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement
+****************************************************************************//**
+*
+* Sets the source increment parameter for the Y loop for the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param srcYincrement
+* The value of the source increment. The valid range is -2048 ... 2047.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcYincrement));
+
+ descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement
+****************************************************************************//**
+*
+* Returns the source increment parameter for the outer Y of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of source increment.
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement
+****************************************************************************//**
+*
+* Sets the destination increment parameter for the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \param dstYincrement
+* The value of the destination increment. Valid range is -2048 ... 2047.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+ CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstYincrement));
+
+ descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement
+****************************************************************************//**
+*
+* Returns the destination increment parameter for the Y loop of the specified
+* descriptor (for 2D descriptors only).
+*
+* \param descriptor
+* The descriptor structure instance declared by the user/component.
+*
+* \return
+* The value of the destination increment.
+*
+*******************************************************************************/
+__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(NULL != descriptor);
+ CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
+
+ return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl));
+}
+
+
+/** \} group_dma_descriptor_functions */
+
+
+/**
+* \addtogroup group_dma_channel_functions
+* \{
+*/
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetDescriptor
+****************************************************************************//**
+*
+* Sets a descriptor as current for the specified DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param descriptor
+* This is the descriptor to be associated with the channel.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+ CY_ASSERT_L1(NULL != descriptor);
+
+ base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)descriptor;
+ base->CH_STRUCT[channel].CH_IDX &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_Enable
+****************************************************************************//**
+*
+* The function is used to enable a DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ base->CH_STRUCT[channel].CH_CTL |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_Disable
+****************************************************************************//**
+*
+* The function is used to disable a DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ base->CH_STRUCT[channel].CH_CTL &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetPriority
+****************************************************************************//**
+*
+* The function is used to set a priority for the DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param priority
+* The priority to be set for the DMA channel. The allowed values are 0,1,2,3.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+ CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority));
+
+ base->CH_STRUCT[channel].CH_CTL = _CLR_SET_FLD32U(base->CH_STRUCT[channel].CH_CTL, DW_CH_STRUCT_CH_CTL_PRIO, priority);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetPriority
+****************************************************************************//**
+*
+* Returns the priority of the DMA channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The priority of the channel.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return ((uint32_t) _FLD2VAL(DW_CH_STRUCT_CH_CTL_PRIO, base->CH_STRUCT[channel].CH_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetCurrentDescriptor
+****************************************************************************//**
+*
+* Returns the descriptor that is active in the channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The pointer to the descriptor assocaited with the channel.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return ((cy_stc_dma_descriptor_t*)(base->CH_STRUCT[channel].CH_CURR_PTR));
+}
+
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns the interrupt status of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The status of an interrupt for the specified channel.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return (base->CH_STRUCT[channel].INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetStatus
+****************************************************************************//**
+*
+* Returns the interrupt reason of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The cause \ref cy_en_dma_intr_cause_t of the interrupt.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, base->CH_STRUCT[channel].CH_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_ClearInterrupt
+****************************************************************************//**
+*
+* Clears the interrupt status of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ base->CH_STRUCT[channel].INTR = CY_DMA_INTR_MASK;
+ (void) base->CH_STRUCT[channel].INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetInterrupt
+****************************************************************************//**
+*
+* Sets the interrupt for the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ base->CH_STRUCT[channel].INTR_SET = CY_DMA_INTR_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the interrupt mask value of the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \return
+* The interrupt mask value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return (base->CH_STRUCT[channel].INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_SetInterruptMask
+****************************************************************************//**
+*
+* Sets an interrupt mask value for the specified channel.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+* \param interrupt
+* The interrupt mask:
+* CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+ CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt));
+ base->CH_STRUCT[channel].INTR_MASK = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Channel_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the logical AND of the corresponding INTR and INTR_MASK fields
+* in a single-load operation.
+*
+* \param base
+* The pointer to the hardware DMA block.
+*
+* \param channel
+* The channel number.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel)
+{
+ CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
+
+ return (base->CH_STRUCT[channel].INTR_MASKED);
+}
+
+/** \} group_dma_channel_functions */
+
+/** \} group_dma_functions */
+
+
+/** \cond The definitions to support the backward compatibility, do not use them in new designs */
+
+#if(CY_DMA_BWC)
+
+ /* Type definitions */
+ #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t
+ #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t
+ #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t
+ #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t
+
+ /* Structure items */
+ #define DMA_Descriptor descriptor
+ #define deact retrigger
+ #define intrType interruptType
+ #define chStateAtCmplt channelState
+ #define srcTxfrSize srcTransferSize
+ #define destTxfrSize dstTransferSize
+ #define trigoutType triggerOutType
+ #define triginType triggerInType
+ #define descrType descriptorType
+ #define srcAddr srcAddress
+ #define destAddr dstAddress
+ #define srcXincr srcXincrement
+ #define srcYincr srcYincrement
+ #define destXincr dstXincrement
+ #define destYincr dstYincrement
+ #define descrNext nextDescriptor
+
+ /* Constants */
+ #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED)
+ #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED)
+
+ #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA)
+ #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD)
+
+ #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
+ #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP)
+ #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR)
+ #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
+ #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP)
+ #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR)
+ #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT)
+ #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP)
+ #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR)
+ #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN)
+
+ #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM)
+
+ #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM)
+ #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC)
+ #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC)
+
+ /* Descriptor structure items */
+ #define DESCR_CTL ctl
+ #define DESCR_SRC src
+ #define DESCR_DST dst
+ #define DESCR_X_CTL xCtl
+ #define DESCR_Y_CTL yCtl
+ #define DESCR_NEXT_PTR nextPtr
+
+ /* Descriptor structure bit-fields */
+ #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL
+ #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL
+ #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
+ #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL
+ #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL
+ #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL
+ #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
+
+ /* Functions */
+ #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel
+ #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress
+ #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress
+ #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init
+ #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit
+ #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress
+ #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress
+ #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor
+ #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType
+ #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType
+ #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType
+ #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init
+ #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit
+ #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor
+ #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable
+ #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable
+ #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor
+ #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority
+ #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority
+ #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus
+ #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus
+ #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt
+ #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt
+ #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask
+ #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked
+ #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK))
+
+
+/*******************************************************************************
+* Function Name: Cy_DMA_Descr_SetTxfrWidth
+****************************************************************************//**
+* This is a legacy API function, it is left here just for the backward compatibility
+* Do not use it in new designs.
+*******************************************************************************/
+ __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,
+ uint32_t dataElementSize,
+ uint32_t srcTxfrWidth,
+ uint32_t dstTxfrWidth)
+ {
+ uint32_t regValue;
+ regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk |
+ DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk |
+ DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk)));
+
+ descriptor->ctl = regValue |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) |
+ _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth);
+ }
+
+#endif /* CY_DMA_BWC */
+
+/** \endcond */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* (CY_DMA_H) */
+
+/** \} group_dma */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,225 @@
+/***************************************************************************//**
+* \file cy_efuse.c
+* \version 1.0
+*
+* \brief
+* Provides API implementation of the eFuse driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_efuse.h"
+#include "ipc/cy_ipc_drv.h"
+
+/** \cond INTERNAL */
+#define CY_EFUSE_OPCODE_SUCCESS (0xA0000000UL) /**< The command completed with no errors */
+#define CY_EFUSE_OPCODE_STS_Msk (0xF0000000UL) /**< The status mask of the SROM API return value */
+#define CY_EFUSE_OPCODE_INV_PROT (0xF0000001UL) /**< The API is not available in the current protection state */
+#define CY_EFUSE_OPCODE_INV_ADDR (0xF0000002UL) /**< An attempt to read byte from the out-of-bond or protected eFuse region */
+#define CY_EFUSE_OPCODE_READ_FUSE_BYTE (0x03000000UL) /**< The SROM API opcode for Read fuse byte operation */
+#define CY_EFUSE_OPCODE_OFFSET_Pos (8UL) /**< A fuse byte offset position in an opcode */
+#define CY_EFUSE_OPCODE_DATA_Msk (0xFFUL) /**< The mask for extracting data from the SROM API return value */
+#define CY_EFUSE_IPC_STRUCT (Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) /**< IPC structure to be used */
+#define CY_EFUSE_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1) /**< IPC notify bit for IPC_STRUCT0 (dedicated to System Call) */
+/** \endcond */
+
+static volatile uint32_t opcode;
+
+static cy_en_efuse_status_t ProcessOpcode(void);
+
+/*******************************************************************************
+* Function Name: Cy_EFUSE_GetEfuseBit
+****************************************************************************//**
+*
+* Reports the current state of a given eFuse bit-number. Consult the device TRM
+* to determine the target fuse bit number.
+*
+* \note An attempt to read an eFuse data from a protected memory region
+* will generate a HardFault.
+*
+* \param bitNum
+* The number of the bit to read. The valid range of the bit number is
+* from 0 to EFUSE_EFUSE_NR * 32 * 8 - 1 where:
+* - EFUSE_EFUSE_NR is number of efuse macros in the selected device series,
+* - 32 is a number of fuse bytes in one efuse macro,
+* - 8 is a number of fuse bits in the byte.
+*
+* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g
+* \e \<PDL_DIR\>/devices/psoc6/psoc63/include/psoc63_config.\e h
+*
+* \param bitVal
+* The pointer to the location to store the bit value.
+*
+* \return
+* \ref cy_en_efuse_status_t
+*
+* \funcusage
+* The example below shows how to read device life-cycle register bits in
+* PSoC 6:
+* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_BIT
+*
+*******************************************************************************/
+cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal)
+{
+ cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
+
+ if (bitVal != NULL)
+ {
+ uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE;
+ uint8_t byteVal;
+ *bitVal = false;
+
+ /* Read the eFuse byte */
+ result = Cy_EFUSE_GetEfuseByte(offset, &byteVal);
+
+ if (result == CY_EFUSE_SUCCESS)
+ {
+ uint32_t bitPos = bitNum % CY_EFUSE_BITS_PER_BYTE;
+ /* Extract the bit from the byte */
+ *bitVal = (((byteVal >> bitPos) & 0x01U) != 0U);
+ }
+ }
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_EFUSE_GetEfuseByte
+****************************************************************************//**
+*
+* Reports the current state of the eFuse byte.
+* If the offset parameter is beyond the available quantities,
+* zeroes will be stored to the byteVal parameter. Consult the device TRM
+* to determine the target fuse byte offset.
+*
+* \note An attempt to read an eFuse data from a protected memory region
+* will generate a HardFault.
+*
+* \param offset
+* The offset of the byte to read. The valid range of the byte offset is
+* from 0 to EFUSE_EFUSE_NR * 32 - 1 where:
+* - EFUSE_EFUSE_NR is a number of efuse macros in the selected device series,
+* - 32 is a number of fuse bytes in one efuse macro.
+*
+* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g
+* \e \<PDL_DIR\>/devices/psoc6/psoc63/include/psoc63_config.\e h
+*
+* \param byteVal
+* The pointer to the location to store eFuse data.
+*
+* \return
+* \ref cy_en_efuse_status_t
+*
+* \funcusage
+* The example below shows how to read a device life-cycle stage register in
+* PSoC 6:
+* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_LIFECYCLE
+*
+*******************************************************************************/
+cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal)
+{
+ cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
+
+ if (byteVal != NULL)
+ {
+ /* Prepare opcode before calling the SROM API */
+ opcode = CY_EFUSE_OPCODE_READ_FUSE_BYTE | (offset << CY_EFUSE_OPCODE_OFFSET_Pos);
+
+ /* Send the IPC message */
+ if (Cy_IPC_Drv_SendMsgPtr(CY_EFUSE_IPC_STRUCT, CY_EFUSE_IPC_NOTIFY_STRUCT0, (void*)&opcode) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Wait until the IPC structure is locked */
+ while(Cy_IPC_Drv_IsLockAcquired(CY_EFUSE_IPC_STRUCT) != false)
+ {
+ }
+
+ /* The result of the SROM API call is returned to the opcode variable */
+ if ((opcode & CY_EFUSE_OPCODE_STS_Msk) == CY_EFUSE_OPCODE_SUCCESS)
+ {
+ *byteVal = (uint8_t)(opcode & CY_EFUSE_OPCODE_DATA_Msk);
+ result = CY_EFUSE_SUCCESS;
+ }
+ else
+ {
+ result = ProcessOpcode();
+ *byteVal = 0U;
+ }
+ }
+ else
+ {
+ result = CY_EFUSE_IPC_BUSY;
+ }
+ }
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_EFUSE_GetExternalStatus
+****************************************************************************//**
+*
+* This function handles the case where a module such as a security image captures
+* a system call from this driver and reports its own status or error code,
+* for example, protection violation. In that case, a function from this
+* driver returns an unknown error (see \ref cy_en_efuse_status_t). After receipt
+* of an unknown error, the user may call this function to get the status
+* of the capturing module.
+*
+* The user is responsible for parsing the content of the returned value
+* and casting it to the appropriate enumeration.
+*
+* \return
+* The error code of the previous efuse operation.
+*
+*******************************************************************************/
+uint32_t Cy_EFUSE_GetExternalStatus(void)
+{
+ return (opcode);
+}
+
+
+/*******************************************************************************
+* Function Name: ProcessOpcode
+****************************************************************************//**
+*
+* Converts System Call returns to the eFuse driver return defines. If
+* an unknown error was returned, the error code can be accessed via the
+* Cy_EFUSE_GetExternalStatus() function.
+*
+* \param opcode The value returned by a System Call.
+*
+* \return
+* \ref cy_en_efuse_status_t
+*
+*******************************************************************************/
+static cy_en_efuse_status_t ProcessOpcode(void)
+{
+ cy_en_efuse_status_t result;
+
+ switch(opcode)
+ {
+ case CY_EFUSE_OPCODE_INV_PROT :
+ {
+ result = CY_EFUSE_INVALID_PROTECTION;
+ break;
+ }
+ case CY_EFUSE_OPCODE_INV_ADDR :
+ {
+ result = CY_EFUSE_INVALID_FUSE_ADDR;
+ break;
+ }
+ default :
+ {
+ result = CY_EFUSE_ERR_UNC;
+ break;
+ }
+ }
+
+ return (result);
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,178 @@
+/***************************************************************************//**
+* \file cy_efuse.h
+* \version 1.0
+*
+* Provides the API declarations of the eFuse driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_EFUSE_H)
+#define CY_EFUSE_H
+
+/**
+* \defgroup group_efuse Electronic Fuses (eFuse)
+* \{
+*
+* Electronic Fuses (eFuses) - non-volatile memory whose
+* each bit is one-time programmable (OTP). One eFuse macro consists of
+* 256 bits (32 * 8). The PSoC devices have up to 16 eFuse macros; consult the
+* device-specific datasheet to determine how many macros for a particular device.
+* These are implemented as a regular Advanced High-performance Bus (AHB)
+* peripheral with the following characteristics:
+* - eFuses are used to control the device life-cycle stage (NORMAL, SECURE,
+* and SECURE_WITH_DEBUG) and the protection settings;
+* - eFuse memory can be programmed (eFuse bit value changed from '0' to '1')
+* only once; if an eFuse bit is blown, it cannot be cleared again;
+* - programming fuses requires the associated I/O supply to be at a specific
+* level: the VDDIO0 (or VDDIO if only one VDDIO is present in the package)
+* supply of the device should be set to 2.5 V (±5%);
+* - fuses are programmed via the PSoC Programmer tool that parses the hex file
+* and extracts the necessary information; the fuse data must be located at the
+* dedicated section in the hex file. For more details see
+* [PSoC 6 Programming Specifications](http://www.cypress.com/documentation/programming-specifications/psoc-6-programming-specifications)
+*
+* \section group_efuse_configuration Configuration Considerations
+*
+* Efuse memory can have different organization depending on the selected device.
+* Consult the device TRM to determine the efuse memory organization and
+* registers bitmap on the selected device.
+*
+* To read fuse data use the driver [functions] (\ref group_efuse_functions).
+*
+* To blow fuses, define a data structure of \ref cy_stc_efuse_data_t type in the
+* firmware. The structure must be placed in the special memory section, for
+* this use a compiler attribute.
+* Each byte in the structure corresponds to the one fuse bit in the
+* device. It allows the PSoC Programmer tool to distinguish bytes that are
+* being set from bytes we don't care about or with unknown values. Fill the
+* structure with the following values:
+* - 0x00 - Not blown;
+* - 0x01 - Blown;
+* - 0xFF - Ignore.
+*
+* After the structure is defined and the values are set, build the project and
+* download the firmware. To blow fuses, the firmware must be downloaded by the
+* PSoC Programmer tool. Before you download firmware, ensure that the
+* conditions from the PSoC 6 Programming Specification are met.
+*
+* The code below shows an example of the efuse data structure
+* definition to blow SECURE bit of the life-cycle stage register.
+* The bits to blow are set to the EFUSE_STATE_SET value.
+* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_DATA_STC
+*
+* \section group_efuse_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_efuse_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>R</td>
+* <td>The character sequence // shall not be used within a comment.</td>
+* <td>The comments provide a useful WEB link to the documentation.</td>
+* </tr>
+* <tr>
+* <td>11.5</td>
+* <td>R</td>
+* <td>Dangerous pointer cast results in loss of volatile qualification.</td>
+* <td>The removal of the volatile qualification inside the function has no
+* side effects.</td>
+* </tr>
+* </table>
+*
+* \section group_efuse_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_efuse_macros Macros
+* \defgroup group_efuse_functions Functions
+* \defgroup group_efuse_data_structures Data Structures
+* \defgroup group_efuse_enumerated_types Enumerated Types
+*/
+
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+
+/***************************************
+* Macro Definitions
+***************************************/
+/**
+* \addtogroup group_efuse_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_EFUSE_DRV_VERSION_MAJOR 1
+/** The driver minor version */
+#define CY_EFUSE_DRV_VERSION_MINOR 0
+/** The eFuse driver identifier */
+#define CY_EFUSE_ID (CY_PDL_DRV_ID(0x1AUL))
+/** The number of bits in the byte */
+#define CY_EFUSE_BITS_PER_BYTE (8UL)
+/** \} group_efuse_macros */
+
+/***************************************
+* Enumerated Types
+***************************************/
+/**
+* \addtogroup group_efuse_enumerated_types
+* \{
+*/
+/** This enum has the return values of the eFuse driver */
+typedef enum
+{
+ CY_EFUSE_SUCCESS = 0x00UL, /**< Success */
+ CY_EFUSE_INVALID_PROTECTION = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Invalid access in the current protection state */
+ CY_EFUSE_INVALID_FUSE_ADDR = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< Invalid eFuse address */
+ CY_EFUSE_BAD_PARAM = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< One or more invalid parameters */
+ CY_EFUSE_IPC_BUSY = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x04UL, /**< The IPC structure is already locked by another process */
+ CY_EFUSE_ERR_UNC = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown error code. See Cy_EFUSE_GetExternalStatus() */
+} cy_en_efuse_status_t;
+
+/** \} group_efuse_data_structure */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_efuse_functions
+* \{
+*/
+cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal);
+cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal);
+uint32_t Cy_EFUSE_GetExternalStatus(void);
+/** \} group_efuse_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* #if !defined(CY_EFUSE_H) */
+
+/** \} group_efuse */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1271 @@
+/***************************************************************************//**
+* \file cy_flash.c
+* \version 3.0
+*
+* \brief
+* Provides the public functions for the API for the PSoC 6 Flash Driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "flash/cy_flash.h"
+#include "sysclk/cy_sysclk.h"
+#include "sysint/cy_sysint.h"
+#include "ipc/cy_ipc_drv.h"
+#include "ipc/cy_ipc_sema.h"
+#include "ipc/cy_ipc_pipe.h"
+
+/***************************************
+* Data Structure definitions
+***************************************/
+
+/* Flash driver context */
+typedef struct
+{
+ uint32_t opcode; /**< Specifies the code of flash operation */
+ uint32_t arg1; /**< Specifies the configuration of flash operation */
+ uint32_t arg2; /**< Specifies the configuration of flash operation */
+ uint32_t arg3; /**< Specifies the configuration of flash operation */
+} cy_stc_flash_context_t;
+
+
+/***************************************
+* Macro definitions
+***************************************/
+
+/** \cond INTERNAL */
+/** Set SROM API in blocking mode */
+#define CY_FLASH_BLOCKING_MODE ((0x01UL) << 8UL)
+/** Set SROM API in non blocking mode */
+#define CY_FLASH_NON_BLOCKING_MODE (0UL)
+
+/** SROM API flash region ID shift for flash row information */
+#define CY_FLASH_REGION_ID_SHIFT (16U)
+#define CY_FLASH_REGION_ID_MASK (3U)
+#define CY_FLASH_ROW_ID_MASK (0xFFFFU)
+/** SROM API flash region IDs */
+#define CY_FLASH_REGION_ID_MAIN (0UL)
+#define CY_FLASH_REGION_ID_EM_EEPROM (1UL)
+#define CY_FLASH_REGION_ID_SFLASH (2UL)
+
+/** SROM API opcode mask */
+#define CY_FLASH_OPCODE_Msk ((0xFFUL) << 24UL)
+/** SROM API opcode for flash write operation */
+#define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24UL)
+/** SROM API opcode for flash program operation */
+#define CY_FLASH_OPCODE_PROGRAM_ROW ((0x06UL) << 24UL)
+/** SROM API opcode for row erase operation */
+#define CY_FLASH_OPCODE_ERASE_ROW ((0x1CUL) << 24UL)
+/** SROM API opcode for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24UL)
+/** SROM API opcode for flash hash operation */
+#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24UL)
+/** SROM API flash row shift for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8UL)
+/** SROM API flash row shift for flash checksum operation */
+#define CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT (22UL)
+/** SROM API flash data size parameter for flash write operation */
+#define CY_FLASH_CONFIG_DATASIZE (CPUSS_FLASHC_PA_SIZE_LOG2 - 1UL)
+/** Data to be programmed to flash is located in SRAM memory region */
+#define CY_FLASH_DATA_LOC_SRAM (0x100UL)
+/** SROM API flash verification option for flash write operation */
+#define CY_FLASH_CONFIG_VERIFICATION_EN ((0x01UL) << 16u)
+
+/** Command completed with no errors */
+#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL)
+/** Invalid device protection state */
+#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL)
+/** Invalid flash page latch address */
+#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL)
+/** Invalid flash address */
+#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL)
+/** Row is write protected */
+#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL)
+/** Comparison between Page Latches and FM row failed */
+#define CY_FLASH_ROMCODE_PL_ROW_COMP_FA (0xF0000022UL)
+/** Command in progress; no error */
+#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL)
+/** Flash operation is successfully initiated */
+#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL)
+/** Flash is under operation */
+#define CY_FLASH_IS_BUSY (0x00000040UL)
+/** IPC structure is already locked by another process */
+#define CY_FLASH_IS_IPC_BUSY (0x00000080UL)
+/** Input parameters passed to Flash API are not valid */
+#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL)
+
+/** Result mask */
+#define CY_FLASH_RESULT_MASK (0x0FFFFFFFUL)
+/** Error shift */
+#define CY_FLASH_ERROR_SHIFT (28UL)
+/** No error */
+#define CY_FLASH_ERROR_NO_ERROR (0xAUL)
+
+/** CM4 Flash Proxy address */
+#define CY_FLASH_CM4_FLASH_PROXY_ADDR (*(Cy_Flash_Proxy *)(0x00000D1CUL))
+typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *context);
+
+/** IPC notify bit for IPC_STRUCT0 (dedicated to flash operation) */
+#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1)
+
+/** Disable delay */
+#define CY_FLASH_NO_DELAY (0U)
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /** Number of ticks to wait 1 uS */
+ #define CY_FLASH_TICKS_FOR_1US (8U)
+ /** Slow control register */
+ #define CY_FLASH_TST_DDFT_SLOW_CTL_REG (*(reg32 *) 0x40260108U)
+ /** Slow control register */
+ #define CY_FLASH_TST_DDFT_FAST_CTL_REG (*(reg32 *) 0x40260104U)
+ /** Define to set the IMO to perform a delay after the flash operation started */
+ #define CY_FLASH_TST_DDFT_SLOW_CTL_MASK (0x00001F1EUL)
+ /** Fast control register */
+ #define CY_FLASH_TST_DDFT_FAST_CTL_MASK (62U)
+ /** Slow output register - output disabled */
+ #define CY_FLASH_CLK_OUTPUT_DISABLED (0U)
+
+ /* The default delay time value */
+ #define CY_FLASH_DEFAULT_DELAY (150UL)
+ /* Calculates the time in microseconds to wait for the number of the CM0P ticks */
+ #define CY_FLASH_DELAY_CORRECTIVE(ticks) ((((uint32)Cy_SysClk_ClkPeriGetDivider() + 1UL) * \
+ (Cy_SysClk_ClkSlowGetDivider() + 1UL) * (ticks) * 1000UL)\
+ / ((uint32_t)cy_Hfclk0FreqHz / 1000UL))
+
+ /* Number of the CM0P ticks for StartProgram function delay corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY_TICKS (6000UL)
+ /* Delay time for StartProgram function in us */
+ #define CY_FLASH_START_PROGRAM_DELAY_TIME (900UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_DELAY_TICKS))
+ /* Number of the CM0P ticks for StartErase function delay corrective time */
+ #define CY_FLASH_START_ERASE_DELAY_TICKS (9500UL)
+ /* Delay time for StartErase function in us */
+ #define CY_FLASH_START_ERASE_DELAY_TIME (2200UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_ERASE_DELAY_TICKS))
+ /* Number of the CM0P ticks for StartWrite function delay corrective time */
+ #define CY_FLASH_START_WRITE_DELAY_TICKS (19000UL)
+ /* Delay time for StartWrite function in us */
+ #define CY_FLASH_START_WRITE_DELAY_TIME (9800UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_WRITE_DELAY_TICKS))
+
+ /** Delay time for Start Write function in us with corrective time */
+ #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_START_WRITE_DELAY_TIME)
+ /** Delay time for Start Program function in us with corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_START_PROGRAM_DELAY_TIME)
+ /** Delay time for Start Erase function in uS with corrective time */
+ #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_START_ERASE_DELAY_TIME)
+
+ #define CY_FLASH_ENTER_WAIT_LOOP (0xFFU)
+ #define CY_FLASH_IPC_CLIENT_ID (2U)
+
+ /** Semaphore number reserved for flash driver */
+ #define CY_FLASH_WAIT_SEMA (0UL)
+ /* Semaphore check timeout (in tries) */
+ #define CY_FLASH_SEMA_WAIT_MAX_TRIES (150000UL)
+
+ typedef struct
+ {
+ uint8_t clientID;
+ uint8_t pktType;
+ uint16_t intrRelMask;
+ } cy_flash_notify_t;
+
+ static void Cy_Flash_NotifyHandler(uint32_t * msgPtr);
+ static void Cy_Flash_RAMDelay(uint32_t microseconds);
+
+ #if (CY_CPU_CORTEX_M0P)
+ #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP1)))
+ #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM4_ADDR, CY_IPC_EP_CYPIPE_CM0_ADDR, (a), NULL)
+ #else
+ #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0)))
+ #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM0_ADDR, CY_IPC_EP_CYPIPE_CM4_ADDR, (a), NULL)
+ #endif
+
+ #if (CY_CPU_CORTEX_M4)
+ static void Cy_Flash_ResumeIrqHandler(void);
+ #endif
+#else /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+ /** Delay time for Start Write function in us with corrective time */
+ #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_NO_DELAY)
+ /** Delay time for Start Program function in us with corrective time */
+ #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_NO_DELAY)
+ /** Delay time fot Start Erase function in uS with corrective time */
+ #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_NO_DELAY)
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+/** \endcond */
+
+
+/* Static functions */
+static bool Cy_Flash_BoundsCheck(uint32_t flashAddr);
+static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr);
+static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode);
+static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void);
+static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds);
+
+static volatile cy_stc_flash_context_t flashContext;
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /*******************************************************************************
+ * Function Name: Cy_Flash_NotifyHandler
+ ****************************************************************************//**
+ *
+ * This is the interrupt service routine for the pipe notifications.
+ *
+ *******************************************************************************/
+ typedef struct
+ {
+ uint32_t maxSema; /* Maximum semaphores in system */
+ uint32_t *arrayPtr; /* Pointer to semaphores array */
+ } cy_stc_ipc_sema_t;
+
+ #if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+ #else
+ CY_SECTION(".cy_ramfunc")
+ #endif
+ static void Cy_Flash_NotifyHandler(uint32_t * msgPtr)
+ {
+ uint32_t intr;
+ static uint32_t semaIndex;
+ static uint32_t semaMask;
+ static volatile uint32_t *semaPtr;
+ static cy_stc_ipc_sema_t *semaStruct;
+
+ cy_flash_notify_t *ipcMsgPtr = (cy_flash_notify_t *)msgPtr;
+
+ if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType)
+ {
+ intr = Cy_SysLib_EnterCriticalSection();
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress( CY_IPC_CHAN_SEMA));
+
+ /* Get the index into the semaphore array and calculate the mask */
+ semaIndex = CY_FLASH_WAIT_SEMA / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (CY_FLASH_WAIT_SEMA - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+ semaPtr = &semaStruct->arrayPtr[semaIndex];
+
+ /* Notification to the Flash driver to start the current operation */
+ *semaPtr |= semaMask;
+
+ /* Check a notification from other core to end of waiting */
+ while (((*semaPtr) & semaMask) != 0ul)
+ {
+ }
+
+ Cy_SysLib_ExitCriticalSection(intr);
+ }
+ }
+ #if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+ #endif
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_Flash_Init
+****************************************************************************//**
+*
+* Initiates all needed prerequisites to support flash erase/write.
+* Should be called from each core.
+*
+* Requires a call to Cy_IPC_SystemSemaInit() and Cy_IPC_SystemPipeInit() functions
+* before use.
+*
+* This function is called in the SystemInit() function, for proper flash write
+* and erase operations. If the default startup file is not used, or the function
+* SystemInit() is not called in your project, call the following three functions
+* prior to executing any flash or EmEEPROM write or erase operations:
+* -# Cy_IPC_SystemSemaInit()
+* -# Cy_IPC_SystemPipeInit()
+* -# Cy_Flash_Init()
+*
+*******************************************************************************/
+void Cy_Flash_Init(void)
+{
+ #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ #if (CY_CPU_CORTEX_M4)
+ cy_stc_sysint_t flashIntConfig =
+ {
+ cpuss_interrupt_fm_IRQn, /* .intrSrc */
+ 0 /* .intrPriority */
+ };
+
+ (void)Cy_SysInt_Init(&flashIntConfig, &Cy_Flash_ResumeIrqHandler);
+ NVIC_EnableIRQ(flashIntConfig.intrSrc);
+ #endif
+
+ (void)Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_CYPIPE_ADDR, &Cy_Flash_NotifyHandler,
+ (uint32_t)CY_FLASH_IPC_CLIENT_ID);
+ #endif
+}
+
+/*******************************************************************************
+* Function Name: Cy_Flash_SendCmd
+****************************************************************************//**
+*
+* Sends a command to the SROM via the IPC channel. The function is placed to the
+* SRAM memory to guarantee successful operation. After an IPC message is sent,
+* the function waits for a defined time before exiting the function.
+*
+* \param mode
+* Sets the blocking or non-blocking Flash operation.
+*
+* \param microseconds
+* The number of microseconds to wait before exiting the functions
+* in range 0-65535 us.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+#if defined(CY_DEVICE_PSOC6ABLE2) \
+ && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) \
+ && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ #if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+ #else
+ CY_SECTION(".cy_ramfunc")
+ #endif
+#endif
+static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_IPC_BUSY;
+ IPC_STRUCT_Type *ipcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL);
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+
+ uint32_t semaTryCount = 0uL;
+ uint32_t intr;
+
+ CY_ALIGN(4) static cy_flash_notify_t ipcWaitMessage =
+ {
+ /* .clientID */ CY_FLASH_IPC_CLIENT_ID,
+ /* .pktType */ CY_FLASH_ENTER_WAIT_LOOP,
+ /* .intrRelMask */ 0
+ };
+
+ #if (CY_CPU_CORTEX_M0P)
+ bool isCM4Powered = (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status());
+
+ if (!isCM4Powered)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ }
+ else
+ {
+ #endif
+ if (IS_CY_PIPE_FREE())
+ {
+ if (CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA))
+ {
+ if (CY_IPC_PIPE_SUCCESS == NOTIFY_PEER_CORE(&ipcWaitMessage))
+ {
+ /* Wait for SEMA lock by peer core */
+ while ((CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) && ((semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES)))
+ {
+ /* check for timeout (as maximum tries count) */
+ ++semaTryCount;
+ }
+
+ if (semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ }
+ }
+ }
+ }
+ #if (CY_CPU_CORTEX_M0P)
+ }
+ #endif
+
+ if (CY_FLASH_DRV_SUCCESS == result)
+ {
+ /* Notifier is ready, start of the operation */
+ intr = Cy_SysLib_EnterCriticalSection();
+
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0,
+ (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ if (mode == CY_FLASH_NON_BLOCKING_MODE)
+ {
+ #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ Cy_Flash_RAMDelay(microseconds);
+ #endif
+
+ /* The Flash operation is successfully initiated */
+ result = CY_FLASH_DRV_OPERATION_STARTED;
+ }
+ else
+ {
+ while (0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, ipcBase->LOCK_STATUS))
+ {
+ /* Polls whether the IPC is released and the Flash operation is performed */
+ }
+
+ result = Cy_Flash_OperationStatus();
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ #if (CY_CPU_CORTEX_M0P)
+ if (isCM4Powered)
+ {
+ #endif
+ while (CY_IPC_SEMA_SUCCESS != Cy_IPC_Sema_Clear(CY_FLASH_WAIT_SEMA, true))
+ {
+ /* Clear SEMA lock */
+ }
+ #if (CY_CPU_CORTEX_M0P)
+ }
+ #endif
+
+ Cy_SysLib_ExitCriticalSection(intr);
+ /* End of the flash operation */
+ }
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+ return (result);
+}
+#if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+#endif
+
+
+#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED)
+ /*******************************************************************************
+ * Function Name: Cy_Flash_RAMDelay
+ ****************************************************************************//**
+ *
+ * Wait for a defined time in the SRAM memory region.
+ *
+ * \param microseconds
+ * Delay time in microseconds in range 0-65535 us.
+ *
+ *******************************************************************************/
+ #if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+ #else
+ CY_SECTION(".cy_ramfunc")
+ #endif
+ static void Cy_Flash_RAMDelay(uint32_t microseconds)
+ {
+ uint32_t ticks = (microseconds & 0xFFFFUL) * CY_FLASH_TICKS_FOR_1US;
+ if (ticks != CY_FLASH_NO_DELAY)
+ {
+ CY_FLASH_TST_DDFT_FAST_CTL_REG = CY_FLASH_TST_DDFT_FAST_CTL_MASK;
+ CY_FLASH_TST_DDFT_SLOW_CTL_REG = CY_FLASH_TST_DDFT_SLOW_CTL_MASK;
+
+ SRSS->CLK_OUTPUT_SLOW = _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, CY_SYSCLK_MEAS_CLK_IMO) |
+ _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, CY_FLASH_CLK_OUTPUT_DISABLED);
+
+ /* Load the down-counter without status bit value */
+ SRSS->CLK_CAL_CNT1 = _VAL2FLD(SRSS_CLK_CAL_CNT1_CAL_COUNTER1, ticks);
+
+ /* Make sure that the counter is started */
+ ticks = _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1);
+
+ while (0UL == _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1))
+ {
+ /* Wait until the counter stops counting */
+ }
+ }
+ }
+ #if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+ #endif
+
+ #if (CY_CPU_CORTEX_M4)
+
+ /* Based on bookmark codes of mxs40srompsoc BROS,002-03298 */
+ #define CY_FLASH_PROGRAM_ROW_BOOKMARK (0x00000001UL)
+ #define CY_FLASH_ERASE_ROW_BOOKMARK (0x00000002UL)
+ #define CY_FLASH_WRITE_ROW_ERASE_BOOKMARK (0x00000003UL)
+ #define CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK (0x00000004UL)
+
+ /* Number of the CM0P ticks for function delay corrective time at final stage */
+ #define CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS (1000UL)
+ #define CY_FLASH_PROGRAM_ROW_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS))
+ #define CY_FLASH_ERASE_ROW_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS))
+ #define CY_FLASH_WRITE_ROW_ERASE_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS))
+ #define CY_FLASH_WRITE_ROW_PROGRAM_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS))
+
+
+ /*******************************************************************************
+ * Function Name: Cy_Flash_ResumeIrqHandler
+ ****************************************************************************//**
+ *
+ * This is the interrupt service routine to make additional processing of the
+ * flash operations resume phase.
+ *
+ *******************************************************************************/
+ #if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+ #else
+ CY_SECTION(".cy_ramfunc")
+ #endif
+ static void Cy_Flash_ResumeIrqHandler(void)
+ {
+ IPC_STRUCT_Type *ipcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0);
+
+ uint32_t bookmark;
+ bookmark = FLASHC->FM_CTL.BOOKMARK & 0xffffUL;
+
+ uint32_t cm0s = CPUSS->CM0_STATUS;
+
+ switch (bookmark)
+ {
+ case CY_FLASH_PROGRAM_ROW_BOOKMARK:
+ if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk))
+ {
+ ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0));
+ }
+ Cy_Flash_RAMDelay(CY_FLASH_PROGRAM_ROW_DELAY);
+ break;
+ case CY_FLASH_ERASE_ROW_BOOKMARK:
+ if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk))
+ {
+ ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0));
+ }
+ Cy_Flash_RAMDelay(CY_FLASH_ERASE_ROW_DELAY); /* Delay when erase row is finished */
+ break;
+ case CY_FLASH_WRITE_ROW_ERASE_BOOKMARK:
+ if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk))
+ {
+ ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0));
+ }
+ Cy_Flash_RAMDelay(CY_FLASH_WRITE_ROW_ERASE_DELAY); /* Delay when erase phase for row is finished */
+ break;
+ case CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK:
+ if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk))
+ {
+ ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0));
+ }
+ Cy_Flash_RAMDelay(CY_FLASH_WRITE_ROW_PROGRAM_DELAY);
+ break;
+ default:
+ break;
+ }
+ }
+ #if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+ #endif
+ #endif /* (CY_CPU_CORTEX_M4) */
+#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_EraseRow
+****************************************************************************//**
+*
+* This function erases a single row of flash. Reports success or
+* a reason for failure. Does not return until the Write operation is
+* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in
+* the case when another process is writing to flash or erasing the row.
+*
+* User firmware should not enter the Hibernate or Deep-Sleep mode until flash
+* Erase is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Prepares arguments to be passed to SROM API */
+ if (Cy_Flash_BoundsCheck(rowAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = rowAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_ProgramRow
+****************************************************************************//**
+*
+* This function writes an array of data to a single row of flash. Before calling
+* this function, the target flash region must be erased by the
+* Cy_Flash_StartErase() or Cy_Flash_EraseRow() function.
+*
+* Reports success or a reason for failure. Does not return until the Program
+* operation is complete. Returns immediately and reports a
+* \ref CY_FLASH_DRV_IPC_BUSY error in the case when another process is writing
+* to flash.
+*
+* User firmware should not enter the Hibernate or Deep-sleep mode until flash
+* Program is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \param data The pointer to the data which has to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = CY_FLASH_CONFIG_DATASIZE | CY_FLASH_DATA_LOC_SRAM;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_WriteRow
+****************************************************************************//**
+*
+* This function writes an array of data to a single row of flash. This is done
+* in two steps - erase and then program flash row with the input data.
+* Reports success or a reason for failure. Does not return until the Write
+* operation is complete.
+* Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case
+* when another process is writing to flash.
+*
+* User firmware should not enter the Hibernate or Deep-sleep mode until flash
+* Write is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \param data The pointer to the data which has to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_WRITE_ROW | CY_FLASH_BLOCKING_MODE;
+ flashContext.arg1 = 0UL;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_WRITE_DELAY);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartWrite
+****************************************************************************//**
+*
+* Erase flash row and performs programming of the row with the input data.
+* Returns immediately and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when another process is
+* writing to flash.
+*
+* User firmware should not enter the Hibernate or Deep-Sleep mode until flash
+* Write is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash write operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \param data The pointer to the data to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ result = Cy_Flash_StartErase(rowAddr);
+
+ if (CY_FLASH_DRV_OPERATION_STARTED == result)
+ {
+ /* Polls whether the IPC is released and the Flash operation is performed */
+ do
+ {
+ result = Cy_Flash_OperationStatus();
+ }
+ while (result == CY_FLASH_DRV_OPCODE_BUSY);
+
+ if (CY_FLASH_DRV_SUCCESS == result)
+ {
+ result = Cy_Flash_StartProgram(rowAddr, data);
+ }
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_IsOperationComplete
+****************************************************************************//**
+*
+* Reports a successful operation result, reason of failure or busy status
+* ( \ref CY_FLASH_DRV_OPCODE_BUSY ).
+*
+* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t).
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void)
+{
+ return (Cy_Flash_OperationStatus());
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartErase
+****************************************************************************//**
+*
+* Starts erasing a single row of flash. Returns immediately and reports a
+* successful start or reason for failure. Reports a \ref CY_FLASH_DRV_IPC_BUSY
+* error in the case when IPC structure is locked by another process.
+*
+* User firmware should not enter the Hibernate or Deep-Sleep mode until
+* flash Erase is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the flash read operation is
+* initiated in the same flash sector where the flash erase operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if (Cy_Flash_BoundsCheck(rowAddr) != false)
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW;
+ flashContext.arg1 = rowAddr;
+ flashContext.arg2 = 0UL;
+ flashContext.arg3 = 0UL;
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_StartProgram
+****************************************************************************//**
+*
+* Starts writing an array of data to a single row of flash. Before calling this
+* function, the target flash region must be erased by the Cy_Flash_StartErase()
+* or Cy_Flash_EraseRow() function.
+*
+* Returns immediately and reports a successful start or reason for failure.
+* Reports a \ref CY_FLASH_DRV_IPC_BUSY error if another process is writing
+* to flash.
+*
+* The user firmware should not enter Hibernate or Deep-Sleep mode until flash
+* Program is complete.
+* For all safe execution conditions see \ref group_flash_configuration
+* documentation section.
+*
+* Data to be programmed must be located in the SRAM memory region.
+* \note Before reading data from previously programmed/erased flash rows, the
+* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer()
+* function.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+* The Read-while-Write violation occurs when the Flash Write operation is
+* performing. Refer to the device datasheet for the details.
+*
+* \param data The pointer to the data to be written to flash. The size
+* of the data array must be equal to the flash row size. The flash row size for
+* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to
+* the device datasheet for the details.
+*
+* \return Returns the status of the Flash operation,
+* see \ref cy_en_flashdrv_status_t.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+
+ if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data))
+ {
+ SystemCoreClockUpdate();
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_NON_BLOCKING_MODE;
+ flashContext.arg1 = CY_FLASH_CONFIG_DATASIZE | CY_FLASH_DATA_LOC_SRAM;
+ flashContext.arg2 = rowAddr;
+ flashContext.arg3 = (uint32_t)data;
+
+ result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_RowChecksum
+****************************************************************************//**
+*
+* Returns a checksum value of the specified flash row.
+*
+* \note Now Cy_Flash_RowChecksum() requires the row <b>address</b> (rowAddr)
+* as a parameter. In previous versions of the driver, this function used
+* the row <b>number</b> (rowNum) for this parameter.
+*
+* \param rowAddr Address of the flash row.
+* Address must match row start address otherwise API returns \ref
+* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows
+* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device.
+*
+* \param checksumPtr The pointer to the address where checksum is to be stored
+*
+* \return Returns the status of the Flash operation.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowAddr, uint32_t* checksumPtr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ uint32_t resTmp;
+ uint32_t rowID;
+
+ /* Checks whether the input parameters are valid */
+ if ((Cy_Flash_BoundsCheck(rowAddr)) && (NULL != checksumPtr))
+ {
+ rowID = Cy_Flash_GetRowNum(rowAddr);
+
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_CHECKSUM |
+ (((rowID >> CY_FLASH_REGION_ID_SHIFT) & CY_FLASH_REGION_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT) |
+ ((rowID & CY_FLASH_ROW_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT);
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0,
+ (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Polls whether IPC is released and the Flash operation is performed */
+ while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false)
+ {
+ /* Wait till IPC is released */
+ }
+
+ resTmp = flashContext.opcode;
+
+ if ((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ *checksumPtr = flashContext.opcode & CY_FLASH_RESULT_MASK;
+ }
+ else
+ {
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_CalculateHash
+****************************************************************************//**
+*
+* Returns a hash value of the specified region of flash. Hash calculation
+* algorithm provided by SROM code.
+*
+* \param data Start the data address. API returns invalid address status if
+* called on out of bound FLASH region.
+*
+* \param numberOfBytes The hash value is calculated for the number of bytes
+* after the start data address (0 - 1 byte, 1- 2 bytes etc).
+*
+* \param hashPtr The pointer to the address where hash is to be stored
+*
+* \return Returns the status of the Flash operation.
+*
+*******************************************************************************/
+cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ volatile uint32_t resTmp;
+
+ /* Checks whether the input parameters are valid */
+ if ((data != NULL) && (0ul != numberOfBytes))
+ {
+ /* Prepares arguments to be passed to SROM API */
+ flashContext.opcode = CY_FLASH_OPCODE_HASH;
+ flashContext.arg1 = (uint32_t)data;
+ flashContext.arg2 = numberOfBytes;
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API */
+ if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0,
+ (void*)&flashContext) == CY_IPC_DRV_SUCCESS)
+ {
+ /* Polls whether IPC is released and the Flash operation is performed */
+ while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false)
+ {
+ /* Wait till IPC is released */
+ }
+
+ resTmp = flashContext.opcode;
+
+ if ((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR)
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ *hashPtr = flashContext.opcode & CY_FLASH_RESULT_MASK;
+ }
+ else
+ {
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+ }
+ }
+ else
+ {
+ /* The IPC structure is already locked by another process */
+ result = CY_FLASH_DRV_IPC_BUSY;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_GetRowNum
+****************************************************************************//**
+*
+* Returns flash region ID and row number of the Flash address.
+*
+* \param flashAddr Address to be checked
+*
+* \return
+* The valid return value is encoded as follows (or 0xFFFFFFFFUL for invalid
+* address)
+* <table>
+* <tr><th>Field <th>Value
+* <tr><td>Flash row number <td>[15:0] bits
+* <tr><td>Flash region ID <td>[31:16] bits
+* </table>
+*
+*******************************************************************************/
+static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr)
+{
+ uint32_t result;
+
+ if ((flashAddr >= CY_FLASH_BASE) && (flashAddr < (CY_FLASH_BASE + CY_FLASH_SIZE)))
+ {
+ result = (CY_FLASH_REGION_ID_MAIN << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - CY_FLASH_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+ else
+ if ((flashAddr >= CY_EM_EEPROM_BASE) && (flashAddr < (CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE)))
+ {
+ result = (CY_FLASH_REGION_ID_EM_EEPROM << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - CY_EM_EEPROM_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+ else
+ if ((flashAddr >= SFLASH_BASE) && (flashAddr < (SFLASH_BASE + SFLASH_SECTION_SIZE)))
+ {
+ result = (CY_FLASH_REGION_ID_SFLASH << CY_FLASH_REGION_ID_SHIFT) |
+ ((flashAddr - SFLASH_BASE) / CY_FLASH_SIZEOF_ROW);
+ }
+ else
+ {
+ result = 0xFFFFFFFFUL;
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_BoundsCheck
+****************************************************************************//**
+*
+* Returns false if Flash address is out of boundary, otherwise returns true.
+*
+* \param flashAddr Address to be checked
+*
+* \return false - out of bound, true - in flash bounds
+*
+*******************************************************************************/
+static bool Cy_Flash_BoundsCheck(uint32_t flashAddr)
+{
+ return ((Cy_Flash_GetRowNum(flashAddr) != 0xFFFFFFFFUL) && ((flashAddr % CY_FLASH_SIZEOF_ROW) == 0UL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_ProcessOpcode
+****************************************************************************//**
+*
+* Converts System Call returns to the Flash driver return defines.
+*
+* \param opcode The value returned by the System Call.
+*
+* \return Flash driver return.
+*
+*******************************************************************************/
+static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode)
+{
+ cy_en_flashdrv_status_t result;
+
+ switch (opcode)
+ {
+ case 0UL:
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ break;
+ }
+ case CY_FLASH_ROMCODE_SUCCESS:
+ {
+ result = CY_FLASH_DRV_SUCCESS;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_PROTECTION:
+ {
+ result = CY_FLASH_DRV_INV_PROT;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_FM_PL:
+ {
+ result = CY_FLASH_DRV_INVALID_FM_PL;
+ break;
+ }
+ case CY_FLASH_ROMCODE_INVALID_FLASH_ADDR:
+ {
+ result = CY_FLASH_DRV_INVALID_FLASH_ADDR;
+ break;
+ }
+ case CY_FLASH_ROMCODE_ROW_PROTECTED:
+ {
+ result = CY_FLASH_DRV_ROW_PROTECTED;
+ break;
+ }
+ case CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR:
+ {
+ result = CY_FLASH_DRV_PROGRESS_NO_ERROR;
+ break;
+ }
+ case (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS:
+ {
+ result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ break;
+ }
+ case CY_FLASH_IS_OPERATION_STARTED :
+ {
+ result = CY_FLASH_DRV_OPERATION_STARTED;
+ break;
+ }
+ case CY_FLASH_IS_BUSY :
+ {
+ result = CY_FLASH_DRV_OPCODE_BUSY;
+ break;
+ }
+ case CY_FLASH_IS_IPC_BUSY :
+ {
+ result = CY_FLASH_DRV_IPC_BUSY;
+ break;
+ }
+ case CY_FLASH_IS_INVALID_INPUT_PARAMETERS :
+ {
+ result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS;
+ break;
+ }
+ default:
+ {
+ result = CY_FLASH_DRV_ERR_UNC;
+ break;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_OperationStatus
+****************************************************************************//**
+*
+* Checks the status of the Flash Operation, and returns it.
+*
+* \return Returns the status of the Flash operation
+* (see \ref cy_en_flashdrv_status_t).
+*
+*******************************************************************************/
+static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void)
+{
+ cy_en_flashdrv_status_t result = CY_FLASH_DRV_OPCODE_BUSY;
+
+ /* Checks if the IPC structure is not locked */
+ if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) == false)
+ {
+ /* The result of SROM API calling is returned to the driver context */
+ result = Cy_Flash_ProcessOpcode(flashContext.opcode);
+
+ /* Clear pre-fetch cache after flash operation */
+#if (CY_CPU_CORTEX_M0P)
+ FLASHC->CM0_CA_CMD = FLASHC_CM0_CA_CMD_INV_Msk;
+#else
+ FLASHC->CM4_CA_CMD = FLASHC_CM4_CA_CMD_INV_Msk;
+#endif /* (CY_CPU_CORTEX_M0P) */
+
+ while ((FLASHC->CM0_CA_CMD != 0U) || (FLASHC->CM4_CA_CMD != 0U))
+ {
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Flash_GetExternalStatus
+****************************************************************************//**
+*
+* This function handles the case where a module such as security image captures
+* a system call from this driver and reports its own status or error code,
+* for example protection violation. In that case, a function from this
+* driver returns an unknown error (see \ref cy_en_flashdrv_status_t). After receipt
+* of an unknown error, the user may call this function to get the status
+* of the capturing module.
+*
+* The user is responsible for parsing the content of the returned value
+* and casting it to the appropriate enumeration.
+*
+* \return
+* The error code that was stored in the opcode variable.
+*
+*******************************************************************************/
+uint32_t Cy_Flash_GetExternalStatus(void)
+{
+ return (flashContext.opcode);
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,405 @@
+/***************************************************************************//**
+* \file cy_flash.h
+* \version 3.0
+*
+* Provides the API declarations of the Flash driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_FLASH_H)
+#define CY_FLASH_H
+
+/**
+* \defgroup group_flash Flash System Routine (Flash)
+* \{
+* Internal flash memory programming
+*
+* Flash memory in PSoC devices provides non-volatile storage for user firmware,
+* user configuration data, and bulk data storage.
+*
+* Flash operations are implemented as system calls. System calls are executed
+* out of SROM in the privileged mode of operation. Users have no access to read
+* or modify the SROM code. The driver API requests the system call by acquiring
+* the Inter-processor communication (IPC) and writing the SROM function opcode
+* and parameters to its input registers. As a result, an NMI interrupt is invoked
+* and the requested SROM API is executed. The operation status is returned to the
+* driver context and a release interrupt is triggered.
+*
+* Writing to flash can take up to 20 milliseconds. During this time,
+* the device should not be reset (including XRES pin, software reset, and
+* watchdog) or unexpected changes may be made to portions of the flash.
+* Also, the low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+*
+* A Read while Write violation occurs when a flash Read operation is initiated
+* in the same or neighboring flash sector where the flash Write, Erase, or
+* Program operation is working. This violation may cause a HardFault exception.
+* To avoid the Read while Write violation, the user must carefully split the
+* Read and Write operation on flash sectors which are not neighboring,
+* considering both cores in the multi-processor device. The flash is divided
+* into four equal sectors. You may edit the linker script to place the code
+* into neighboring sectors. For example, use sectors number 0 and 1 for code
+* and sectors 2 and 3 for data storage.
+*
+* \section group_flash_configuration Configuration Considerations
+*
+* \subsection group_flash_config_intro Introduction:
+* The PSoC 6 MCU user-programmable Flash consists of:
+* - Up to four User Flash sectors (0 through 3) - 256KB each.
+* - EEPROM emulation sector - 32KB.
+*
+* Write operations are performed on a per-sector basis and may be done as
+* Blocking or Partially Blocking, defined as follows:
+*
+* \subsection group_flash_config_blocking Blocking:
+* In this case, the entire Flash block is not available for the duration of the
+* Write (up to 20 milliseconds). Therefore, no Flash accesses
+* (from any Bus Master) can occur during that time. CPU execution can be
+* performed from SRAM. All pre-fetching must be disabled. Application code
+* execution from Flash is blocked for the Flash Write duration for both cores.
+*
+* \subsection group_flash_config_block_const Constraints for Blocking Flash operations:
+* -# During write to flash, the device should not be reset (including XRES pin,
+* software reset, and watchdog), or unexpected changes may be made to portions
+* of the flash.
+* -# The low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+* -# Flash write operation is allowed only in one of the following CM4 states:
+* -# CM4 is Active and initialized:<br>
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
+* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
+* after calling Cy_SysEnableCM4().
+* -# CM4 is Off:<br>
+* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
+* supported.
+* .
+* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode.
+* -# Interrupts must be enabled on both active cores. Do not enter a critical
+* section during flash operation.
+* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
+* have the highest priority, or at least that pipe interrupts are not
+* interrupted or in a pending state for more than 700 µs.
+* -# User must guarantee that during flash write operation no flash read
+* operations are performed by bus masters other than CM0+ and CM4 (DMA and
+* Crypto).
+* -# If you do not use the default startup, ensure that firmware calls the
+* following functions before any flash write/erase operations:
+* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization
+*
+* \subsection group_flash_config_rww Partially Blocking:
+* This method has a much shorter time window during which Flash accesses are not
+* allowed. Application code execution from Flash is blocked for only a part of
+* Flash Write duration, for both cores. Blocking duration depends upon the API
+* sequence used.
+*
+* For API sequence Cy_Flash_StartErase() + Cy_Flash_StartProgram() there are
+* four block-out regions during which the read is blocked using the software
+* driver (PDL). See <b>Figure 1</b>.
+*
+* <center>
+* <table class="doxtable">
+* <caption>Table 1 - Block-out periods</caption>
+* <tr>
+* <th>Block-out</th>
+* <th>Phase</th>
+* <th>Duration</th>
+* </tr>
+* <tr>
+* <td>A</td>
+* <td>The beginning of the Erase operation</td>
+* <td>2ms + 9500 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>B</td>
+* <td>The end of the Erase operation</td>
+* <td>0.13ms + 1000 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>C</td>
+* <td>The beginning of the Program operation</td>
+* <td>0.8ms + 6000 SlowClk cycles</td>
+* </tr>
+* <tr>
+* <td>D</td>
+* <td>The end of the Program operation</td>
+* <td>0.13ms + 1000 SlowClk cycles</td>
+* </tr>
+* </table>
+* </center>
+*
+* This allows both cores to execute an application for about 80% of Flash Write
+* operation - see <b>Figure 1</b>.
+* This capability is important for communication protocols that rely on fast
+* response.
+*
+* \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation" width=70%
+*
+* For the Cy_Flash_StartWrite() function, the block-out period is different for
+* the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for
+* two periods:
+* - From start of Erase operation (start of A on Figure 1) till the start of
+* Program operation (end of C on Figure 1).
+* - During D period on <b>Figure 1</b>.
+*
+* The core that performs read/execute is blocked identically to the
+* Cy_Flash_StartErase() + Cy_Flash_StartProgram() sequence - see <b>Figure 1</b>.
+*
+* This allows the core that initiates Cy_Flash_StartWrite() to execute an
+* application for about 20% of the Flash Write operation. The other core executes
+* the application for about 80% of the Flash Write operation.
+*
+* Some constraints must be planned for in the Partially Blocking mode which are
+* described in detail below.
+*
+* \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations:
+* -# During write to flash, the device should not be reset (including XRES pin,
+* software reset, and watchdog) or unexpected changes may be made to portions
+* of the flash.
+* -# The low-voltage detect circuits should be configured to generate an
+* interrupt instead of a reset.
+* -# During write to flash, application code should not change the clock
+* settings. Use Cy_Flash_IsOperationComplete() to ensure flash write
+* operation is finished.
+* -# Flash write operation is allowed only in one of the following CM4 states:
+* -# CM4 is Active and initialized:<br>
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)".
+* <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time
+* after calling Cy_SysEnableCM4().
+* -# CM4 is Off:<br>
+* call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not
+* supported.
+* .
+* -# Use the following rules for split by sectors. (In this context, read means
+* read of any bus master: CM0+, CM4, DMA, Crypto, etc.)
+* -# Do not write to and read/execute from the same flash sector at the same
+* time. This is true for all sectors.
+* -# Writing rules in User Flash:
+* -# Any bus master can read/execute from UFLASH S0 and/or S1, during
+* flash write to UFLASH S2 or S3.
+* -# Any bus master can read/execute from UFLASH S2 and/or S3, during
+* flash write to UFLASH S0 or S1.
+*
+* <b>Suggestion:</b> in case of bootloading, it is recommended to place
+* code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data
+* to S2 and S3 sections.
+* .
+* -# Flash write cannot be performed in ULP mode (core voltage 0.9V).
+* -# Interrupts must be enabled on both active cores. Do not enter a critical
+* section during flash operation.
+* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4)
+* have the highest priority, or at least that pipe interrupts are not
+* interrupted or in a pending state for more than 700 µs.
+* -# User must guarantee that during flash write operation no flash read
+* operations are performed by bus masters other than CM0+ and CM4
+* (DMA and Crypto).
+* -# If you do not use the default startup, ensure that firmware calls the
+* following functions before any flash write/erase operations:
+* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization
+*
+* \subsection group_flash_config_emeeprom EEPROM section use:
+* If you plan to use "cy_em_eeprom" section for different purposes for both of
+* device cores or use <b>Em_EEPROM Middleware</b> together with flash driver
+* write operations you must modify the linker scripts.<br>
+* For more information, refer to the <b>Middleware/Cypress Em_EEPROM Middleware
+* Library</b> section of the PDL documentation.
+*
+* \section group_flash_more_information More Information
+*
+* See the technical reference manual (TRM) for more information about the Flash
+* architecture.
+*
+* \section group_flash_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th style="width: 50%;">Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>Casting to different object pointer type.</td>
+* <td>The cast of the uint32_t pointer to pipe message structure pointer
+* is used to get transmitted data via the \ref group_ipc channel.
+* We cast only one pointer, so there is no way to avoid this cast.</td>
+* </tr>
+* <tr>
+* <td>11.5</td>
+* <td>R</td>
+* <td>Not performed, the cast that removes any const or volatile qualification from the type addressed by a pointer.</td>
+* <td>The removal of the volatile qualification inside the function has no side effects.</td>
+* </tr>
+* </table>
+*
+* \section group_flash_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th style="width: 52%;">Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>3.0</td>
+* <td>New function - Cy_Flash_ProgramRow();<br>
+* Updated Cy_Flash_RowChecksum(): changed input parameter to take the
+* <b>row address</b> (rowAddr) instead of the <b>row number</b>
+* (rowNum);<br>
+* Renamed macro for disabling RWW support in driver to
+* <b>CY_FLASH_RWW_DRV_SUPPORT_DISABLED</b>.<br>
+* Updated \ref group_flash_configuration documentation section with
+* flash usage constraints.</td>
+* <td>Improvements made based on usability feedback to use a common
+* interface</td>
+* </tr>
+* <tr>
+* <td rowspan="3">2.0</td>
+* <td>Added non-blocking erase function - Cy_Flash_StartErase().
+* Removed the clear cache function call.</td>
+* <td>The clear cache operation is removed from the blocking Write/Erase
+* function because in this case it is performed by the hardware.
+* Otherwise it is documented that it is the user's responsibility to
+* clear the cache after executing the non-blocking Write/Erase flash
+* operation.</td>
+* </tr>
+* <tr>
+* <td>Added new Cy_Flash_IsOperationComplete() function to check completeness.
+* Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(),
+* and Cy_Flash_IsEraseComplete() functions.<br>
+* Added Cy_Flash_GetExternalStatus() function to get unparsed status where
+* flash driver will be used in security applications with other modules
+* as SecureImage.<br>
+* Added Cy_Flash_Init() function to initialize all needed prerequisites
+* for Erase/Write operations.</td>
+* <td>Updated driver design to improve user experience.</td>
+* </tr>
+* <tr>
+* <td>Updated driver implementation to remove MISRA rules deviations.</td>
+* <td>Driver implementation quality improvement.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_flash_macros Macros
+* \{
+* \defgroup group_flash_general_macros Flash general parameters
+* Provides general information about flash
+* \}
+* \defgroup group_flash_functions Functions
+* \defgroup group_flash_enumerated_types Enumerated Types
+*/
+
+#include <cy_device_headers.h>
+#include "syslib/cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Macro definitions
+***************************************/
+/**
+* \addtogroup group_flash_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_FLASH_DRV_VERSION_MAJOR 3
+
+/** Driver minor version */
+#define CY_FLASH_DRV_VERSION_MINOR 0
+
+#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */
+
+#define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */
+#define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */
+#define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */
+
+/** \} group_flash_macros */
+
+
+/**
+* \addtogroup group_flash_general_macros
+* \{
+*/
+
+/** Flash row size */
+#define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u)
+/** Number of flash rows */
+#define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW)
+/** Long words flash row size */
+#define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t))
+
+/** \} group_flash_general_macros */
+
+
+/**
+* \addtogroup group_flash_enumerated_types
+* \{
+*/
+
+/** This enum has the return values of the Flash driver */
+typedef enum cy_en_flashdrv_status
+{
+ CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */
+ CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */
+ CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */
+ CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */
+ CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */
+ CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */
+ CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */
+ CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */
+ CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */
+ CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */
+ CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */
+ CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */
+} cy_en_flashdrv_status_t;
+
+/** \} group_flash_enumerated_types */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_flash_functions
+* \{
+*/
+void Cy_Flash_Init(void);
+cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr);
+cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data);
+cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr);
+cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void);
+cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr);
+cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr);
+uint32_t Cy_Flash_GetExternalStatus(void);
+/** \} group_flash_functions */
+
+/** \cond INTERNAL */
+/* Macros to backward compatibility */
+#define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete()
+#define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete()
+#define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete()
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* #if !defined(CY_FLASH_H) */
+
+/** \} group_flash */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,262 @@
+/***************************************************************************//**
+* \file cy_gpio.c
+* \version 1.10.1
+*
+* \brief
+* Provides an API implementation of the GPIO driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_gpio.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Pin_Init
+****************************************************************************//**
+*
+* \brief Initializes all pin configuration settings for the specified pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param config
+* Pointer to the pin config structure base address
+*
+* \return
+* Initialization status
+*
+* \note
+* This function modifies port registers in read-modify-write operations. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_Init
+*
+*******************************************************************************/
+cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
+{
+ cy_en_gpio_status_t status = CY_GPIO_SUCCESS;
+ uint32_t maskCfgOut;
+ uint32_t tempReg;
+
+ if((NULL != base) && (NULL != config))
+ {
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
+ CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
+ CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
+ CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
+
+ Cy_GPIO_Write(base, pinNum, config->outVal);
+ Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
+ Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
+
+ Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge);
+ Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask);
+ Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
+
+ /* Slew rate and Driver strength */
+ maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
+ | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
+ tempReg = base->CFG_OUT & ~(maskCfgOut);
+ base->CFG_OUT = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
+ | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
+
+ /* SIO specific configuration */
+ tempReg = base->CFG_SIO & ~(CY_GPIO_SIO_PIN_MASK);
+ base->CFG_SIO = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK)
+ | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT)
+ | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT)
+ | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT)
+ | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT))
+ << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET));
+ }
+ else
+ {
+ status = CY_GPIO_BAD_PARAM;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Port_Init
+****************************************************************************//**
+*
+* \brief Initialize a complete port of pins from a single init structure.
+*
+* The configuration structure used in this function has a 1:1 mapping to the
+* GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM)
+* for the register details on how to populate them.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param config
+* Pointer to the pin config structure base address
+*
+* \return
+* Initialization status
+*
+* \note
+* If using the PSoC Creator IDE, there is no need to initialize the pins when
+* using the GPIO component on the schematic. Ports are configured in
+* Cy_SystemInit() before main() entry.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Init
+*
+*******************************************************************************/
+cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config)
+{
+ cy_en_gpio_status_t status = CY_GPIO_SUCCESS;
+ uint32_t portNum;
+ HSIOM_PRT_Type* baseHSIOM;
+
+ if((NULL != base) && (NULL != config))
+ {
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out));
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn));
+ CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg));
+ CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
+ CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
+ CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
+
+ portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ baseHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ base->OUT = config->out;
+ base->CFG = config->cfg;
+ base->CFG_IN = config->cfgIn;
+ base->CFG_OUT = config->cfgOut;
+ base->INTR_CFG = config->intrCfg;
+ base->INTR_MASK = config->intrMask;
+ base->CFG_SIO = config->cfgSIO;
+ baseHSIOM->PORT_SEL0 = config->sel0Active;
+ baseHSIOM->PORT_SEL1 = config->sel1Active;
+ }
+ else
+ {
+ status = CY_GPIO_BAD_PARAM;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Pin_FastInit
+****************************************************************************//**
+*
+* \brief Initialize the most common configuration settings for all pin types.
+*
+* These include, drive mode, initial output value, and HSIOM connection.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param driveMode
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \param outVal
+* Logic state of the output buffer driven to the pin (1 or 0)
+*
+* \param hsiom
+* HSIOM input selection
+*
+* \return
+* void
+*
+* \note
+* This function modifies port registers in read-modify-write operations. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_FastInit
+*
+*******************************************************************************/
+void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode,
+ uint32_t outVal, en_hsiom_sel_t hsiom)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom));
+
+ tempReg = (base->OUT & ~(CY_GPIO_OUT_MASK << pinNum));
+ base->OUT = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum);
+
+ tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)));
+ base->CFG = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET));
+
+ Cy_GPIO_SetHSIOM(base, pinNum, hsiom);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Port_Deinit
+****************************************************************************//**
+*
+* \brief Reset a complete port of pins back to power on reset defaults.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Deinit
+*
+*******************************************************************************/
+void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base)
+{
+ uint32_t portNum;
+ HSIOM_PRT_Type* portAddrHSIOM;
+
+ portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ base->OUT = CY_GPIO_PRT_DEINIT;
+ base->CFG = CY_GPIO_PRT_DEINIT;
+ base->CFG_IN = CY_GPIO_PRT_DEINIT;
+ base->CFG_OUT = CY_GPIO_PRT_DEINIT;
+ base->INTR_CFG = CY_GPIO_PRT_DEINIT;
+ base->INTR_MASK = CY_GPIO_PRT_DEINIT;
+ base->CFG_SIO = CY_GPIO_PRT_DEINIT;
+ portAddrHSIOM->PORT_SEL0 = CY_GPIO_PRT_DEINIT;
+ portAddrHSIOM->PORT_SEL1 = CY_GPIO_PRT_DEINIT;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1958 @@
+/***************************************************************************//**
+* \file cy_gpio.h
+* \version 1.10.1
+*
+* \brief
+* Provides an API declaration of the GPIO driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_gpio General Purpose Input Output (GPIO)
+* \{
+* The GPIO driver provides an API to configure and access device Input/Output pins.
+* IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and
+* their variants.
+*
+* Initialization can be performed either at the port level or by configuring the
+* individual pins. For efficient use of code space, port
+* configuration should be used in the field. Refer to the product device header files
+* for the list of supported ports and pins.
+*
+* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
+* (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
+* cy_stc_gpio_pin_config_t structure).
+* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
+* cy_stc_gpio_prt_config_t structure. The values in the structure are
+* bitfields representing the desired value for each pin in the port.
+* - Pin configuration and management is based on the port address and pin number.
+* \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
+* address from the port number at run-time.
+*
+* Once the pin/port initialization is complete, each pin can be accessed by
+* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
+* functions.
+*
+* \section group_gpio_configuration Configuration Considerations
+*
+* 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection.
+* This allows the pin to connect to signal sources/sinks throughout the device,
+* as defined by the pin HSIOM selection options (en_hsiom_sel_t).
+* 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW
+* control digital pin only) at Power-On-Reset(POR).
+* 3. Some API functions perform read-modify-write operations on shared port
+* registers. These functions are not thread safe and care must be taken when
+* called by the application.
+*
+* Multiple pins on a port can be updated using direct port register writes with an
+* appropriate port mask. An example is shown below, highlighting the different ways of
+* configuring Port 1 pins using,
+*
+* - Port output data register
+* - Port output data set register
+* - Port output data clear register
+*
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c Cy_GPIO_Snippet
+*
+* \section group_gpio_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_gpio_MISRA MISRA-C Compliance]
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>A pointer parameter in a function prototype should be declared as pointer
+* to const if the pointer is not used to modify the addressed object.</td>
+* <td>The objects pointed to by the base addresses of the GPIO port are not always modified.
+* While a const qualifier can be used in select scenarios, it brings little benefit
+* in adding this to the affected functions. </td>
+* </tr>
+* </table>
+*
+* \section group_gpio_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
+* \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
+* Minor documentation edits.
+* </td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added input parameter validation to the API functions</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_gpio_macros Macros
+* \defgroup group_gpio_functions Functions
+* \{
+* \defgroup group_gpio_functions_init Initialization Functions
+* \defgroup group_gpio_functions_gpio GPIO Functions
+* \defgroup group_gpio_functions_sio SIO Functions
+* \defgroup group_gpio_functions_interrupt Port Interrupt Functions
+* \}
+* \defgroup group_gpio_data_structures Data Structures
+* \defgroup group_gpio_enums Enumerated Types
+*/
+
+#if !defined(CY_GPIO_H)
+#define CY_GPIO_H
+
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_gpio_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_GPIO_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_GPIO_DRV_VERSION_MINOR 10
+
+/** GPIO driver ID */
+#define CY_GPIO_ID CY_PDL_DRV_ID(0x16u)
+
+/** \} group_gpio_macros */
+
+
+/***************************************
+* Enumerations
+***************************************/
+/**
+* \addtogroup group_gpio_enums
+* \{
+*/
+
+/**
+* GPIO Driver error codes
+*/
+typedef enum
+{
+ CY_GPIO_SUCCESS = 0x00u, /**< Returned successful */
+ CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
+} cy_en_gpio_status_t;
+
+/** \} group_gpio_enums */
+
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_gpio_data_structures
+* \{
+*/
+
+/** This structure is used to initialize a port of GPIO pins */
+typedef struct {
+ uint32_t out; /**< Initial output data for the IO pins in the port */
+ uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */
+ uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */
+ uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */
+ uint32_t cfgIn; /**< Port pin input buffer configuration */
+ uint32_t cfgOut; /**< Port pin output buffer configuration */
+ uint32_t cfgSIO; /**< Port SIO pins configuration */
+ uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */
+ uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */
+} cy_stc_gpio_prt_config_t;
+
+/** This structure is used to initialize a single GPIO pin */
+typedef struct {
+ uint32_t outVal; /**< Pin output state */
+ uint32_t driveMode; /**< Drive mode */
+ en_hsiom_sel_t hsiom; /**< HSIOM selection */
+ uint32_t intEdge; /**< Interrupt Edge type */
+ uint32_t intMask; /**< Interrupt enable mask */
+ uint32_t vtrip; /**< Input buffer voltage trip type */
+ uint32_t slewRate; /**< Output buffer slew rate */
+ uint32_t driveSel; /**< Drive strength */
+ uint32_t vregEn; /**< SIO pair output buffer mode */
+ uint32_t ibufMode; /**< SIO pair input buffer mode */
+ uint32_t vtripSel; /**< SIO pair input buffer trip point */
+ uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */
+ uint32_t vohSel; /**< SIO pair regulated voltage output level */
+} cy_stc_gpio_pin_config_t;
+
+/** \} group_gpio_data_structures */
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* General Constants */
+#define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */
+#define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */
+
+/* GPIO Masks */
+#define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */
+#define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */
+#define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */
+#define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */
+#define CY_GPIO_CFG_IN_VTRIP_SEL_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */
+#define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */
+#define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */
+#define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
+#define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
+#define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */
+#define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */
+#define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */
+#define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */
+
+/* SIO Masks */
+#define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */
+#define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */
+#define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */
+#define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */
+#define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */
+#define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */
+#define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */
+#define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */
+#define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */
+
+/* Special mask for SIO pin pair setting */
+#define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */
+#define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */
+
+/* Offsets */
+#define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */
+#define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */
+#define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */
+#define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */
+#define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */
+#define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */
+#define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */
+
+/* Parameter validation constants */
+#define CY_GPIO_PINS_MAX (8UL) /**< Number of pins in the port */
+#define CY_GPIO_PRT_PINS_MASK (0x0000000FFUL)
+#define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
+#define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
+ GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
+ GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
+#define CY_GPIO_PRT_INT_MASK_MASK (0x0000001FFUL)
+#define CY_GPIO_PRT_SEL_ACTIVE_MASK (0x1FFFFFFFUL)
+
+/* Parameter validation macros */
+#define CY_GPIO_IS_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX > (pinNum))
+#define CY_GPIO_IS_FILTER_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX >= (pinNum))
+#define CY_GPIO_IS_VALUE_VALID(outVal) (1UL >= (outVal))
+#define CY_GPIO_IS_DM_VALID(driveMode) (0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK))
+
+#define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))
+
+#define CY_GPIO_IS_INT_EDGE_VALID(intEdge) ((CY_GPIO_INTR_DISABLE == (intEdge)) || \
+ (CY_GPIO_INTR_RISING == (intEdge)) || \
+ (CY_GPIO_INTR_FALLING == (intEdge)) || \
+ (CY_GPIO_INTR_BOTH == (intEdge)))
+
+#define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) ((CY_GPIO_DRIVE_FULL == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_2 == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_4 == (driveSel)) || \
+ (CY_GPIO_DRIVE_1_8 == (driveSel)))
+
+#define CY_GPIO_IS_VREF_SEL_VALID(vrefSel) ((CY_SIO_VREF_PINREF == (vrefSel)) || \
+ (CY_SIO_VREF_1_2V == (vrefSel)) || \
+ (CY_SIO_VREF_AMUX_A == (vrefSel)) || \
+ (CY_SIO_VREF_AMUX_B == (vrefSel)))
+
+#define CY_GPIO_IS_VOH_SEL_VALID(vrefSel) ((CY_SIO_VOH_1_00 == (vrefSel)) || \
+ (CY_SIO_VOH_1_25 == (vrefSel)) || \
+ (CY_SIO_VOH_1_49 == (vrefSel)) || \
+ (CY_SIO_VOH_1_67 == (vrefSel)) || \
+ (CY_SIO_VOH_2_08 == (vrefSel)) || \
+ (CY_SIO_VOH_2_50 == (vrefSel)) || \
+ (CY_SIO_VOH_2_78 == (vrefSel)) || \
+ (CY_SIO_VOH_4_16 == (vrefSel)))
+
+#define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
+#define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
+#define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
+#define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
+
+/** \endcond */
+
+
+/***************************************
+* Function Constants
+***************************************/
+
+/**
+* \addtogroup group_gpio_macros
+* \{
+*/
+
+/**
+* \defgroup group_gpio_driveModes Pin drive mode
+* \{
+* Constants to be used for setting the drive mode of the pin.
+*/
+#define CY_GPIO_DM_ANALOG (0x00UL) /**< \brief Analog High-Z. Input buffer off */
+#define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< \brief Resistive Pull-Up. Input buffer off */
+#define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< \brief Resistive Pull-Down. Input buffer off */
+#define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< \brief Open Drain, Drives Low. Input buffer off */
+#define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< \brief Open Drain, Drives High. Input buffer off */
+#define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< \brief Strong Drive. Input buffer off */
+#define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< \brief Resistive Pull-Up/Down. Input buffer off */
+#define CY_GPIO_DM_HIGHZ (0x08UL) /**< \brief Digital High-Z. Input buffer on */
+#define CY_GPIO_DM_PULLUP (0x0AUL) /**< \brief Resistive Pull-Up. Input buffer on */
+#define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< \brief Resistive Pull-Down. Input buffer on */
+#define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< \brief Open Drain, Drives Low. Input buffer on */
+#define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< \brief Open Drain, Drives High. Input buffer on */
+#define CY_GPIO_DM_STRONG (0x0EUL) /**< \brief Strong Drive. Input buffer on */
+#define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< \brief Resistive Pull-Up/Down. Input buffer on */
+/** \} */
+
+/**
+* \defgroup group_gpio_vtrip Voltage trip mode
+* \{
+* Constants to be used for setting the voltage trip type on the pin.
+*/
+#define CY_GPIO_VTRIP_CMOS (0x00UL) /**< \brief Input buffer compatible with CMOS and I2C interfaces */
+#define CY_GPIO_VTRIP_TTL (0x01UL) /**< \brief Input buffer compatible with TTL and MediaLB interfaces */
+/** \} */
+
+/**
+* \defgroup group_gpio_slewRate Slew Rate Mode
+* \{
+* Constants to be used for setting the slew rate of the pin.
+*/
+#define CY_GPIO_SLEW_FAST (0x00UL) /**< \brief Fast slew rate */
+#define CY_GPIO_SLEW_SLOW (0x01UL) /**< \brief Slow slew rate */
+/** \} */
+
+/**
+* \defgroup group_gpio_driveStrength Pin drive strength
+* \{
+* Constants to be used for setting the drive strength of the pin.
+*/
+#define CY_GPIO_DRIVE_FULL (0x00UL) /**< \brief Full drive strength: Max drive current */
+#define CY_GPIO_DRIVE_1_2 (0x01UL) /**< \brief 1/2 drive strength: 1/2 drive current */
+#define CY_GPIO_DRIVE_1_4 (0x02UL) /**< \brief 1/4 drive strength: 1/4 drive current */
+#define CY_GPIO_DRIVE_1_8 (0x03UL) /**< \brief 1/8 drive strength: 1/8 drive current */
+/** \} */
+
+/**
+* \defgroup group_gpio_interruptTrigger Interrupt trigger type
+* \{
+* Constants to be used for setting the interrupt trigger type on the pin.
+*/
+#define CY_GPIO_INTR_DISABLE (0x00UL) /**< \brief Disable the pin interrupt generation */
+#define CY_GPIO_INTR_RISING (0x01UL) /**< \brief Rising-Edge interrupt */
+#define CY_GPIO_INTR_FALLING (0x02UL) /**< \brief Falling-Edge interrupt */
+#define CY_GPIO_INTR_BOTH (0x03UL) /**< \brief Both-Edge interrupt */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVreg SIO output buffer mode
+* \{
+* Constants to be used for setting the SIO output buffer mode on the pin.
+*/
+#define CY_SIO_VREG_UNREGULATED (0x00UL) /**< \brief Unregulated output buffer */
+#define CY_SIO_VREG_REGULATED (0x01UL) /**< \brief Regulated output buffer */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioIbuf SIO input buffer mode
+* \{
+* Constants to be used for setting the SIO input buffer mode on the pin.
+*/
+#define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< \brief Single ended input buffer */
+#define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< \brief Differential input buffer */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVtrip SIO input buffer trip-point
+* \{
+* Constants to be used for setting the SIO input buffer trip-point of the pin.
+*/
+#define CY_SIO_VTRIP_CMOS (0x00UL) /**< \brief CMOS input buffer (single-ended) */
+#define CY_SIO_VTRIP_TTL (0x01UL) /**< \brief TTL input buffer (single-ended) */
+#define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< \brief 0.5xVddio or 0.5xVoh (differential) */
+#define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< \brief 0.4xVddio or 0.4xVoh (differential) */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point
+* \{
+* Constants to be used for setting the reference voltage of SIO input buffer trip-point.
+*/
+#define CY_SIO_VREF_PINREF (0x00UL) /**< \brief Vref from analog pin */
+#define CY_SIO_VREF_1_2V (0x01UL) /**< \brief Vref from internal 1.2V reference */
+#define CY_SIO_VREF_AMUX_A (0x02UL) /**< \brief Vref from AMUXBUS_A */
+#define CY_SIO_VREF_AMUX_B (0x03UL) /**< \brief Vref from AMUXBUS_B */
+/** \} */
+
+/**
+* \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair
+* \{
+* Constants to be used for setting the Voh and input buffer trip-point of an SIO pair
+*/
+#define CY_SIO_VOH_1_00 (0x00UL) /**< \brief Voh = 1 x Reference */
+#define CY_SIO_VOH_1_25 (0x01UL) /**< \brief Voh = 1.25 x Reference */
+#define CY_SIO_VOH_1_49 (0x02UL) /**< \brief Voh = 1.49 x Reference */
+#define CY_SIO_VOH_1_67 (0x03UL) /**< \brief Voh = 1.67 x Reference */
+#define CY_SIO_VOH_2_08 (0x04UL) /**< \brief Voh = 2.08 x Reference */
+#define CY_SIO_VOH_2_50 (0x05UL) /**< \brief Voh = 2.50 x Reference */
+#define CY_SIO_VOH_2_78 (0x06UL) /**< \brief Voh = 2.78 x Reference */
+#define CY_SIO_VOH_4_16 (0x07UL) /**< \brief Voh = 4.16 x Reference */
+/** \} */
+
+/** \} group_gpio_macros */
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_gpio_functions
+* \{
+*/
+
+/**
+* \addtogroup group_gpio_functions_init
+* \{
+*/
+
+cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config);
+cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config);
+void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
+void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base);
+__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
+__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum);
+
+/** \} group_gpio_functions_init */
+
+/**
+* \addtogroup group_gpio_functions_gpio
+* \{
+*/
+
+__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum);
+
+/** \} group_gpio_functions_gpio */
+
+/**
+* \addtogroup group_gpio_functions_sio
+* \{
+*/
+
+__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum);
+
+/** \} group_gpio_functions_sio */
+
+/**
+* \addtogroup group_gpio_functions_interrupt
+* \{
+*/
+
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum);
+__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value);
+__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base);
+
+#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN)
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void);
+#endif /* (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) */
+
+#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN)
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void);
+#endif /* (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) */
+
+#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN)
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void);
+#endif /* (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) */
+
+#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN)
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
+#endif /* (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) */
+
+/** \} group_gpio_functions_interrupt */
+
+
+/**
+* \addtogroup group_gpio_functions_init
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetHSIOM
+****************************************************************************//**
+*
+* \brief Configures the HSIOM connection to the pin.
+*
+* Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection
+* to the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* HSIOM input selection
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetHSIOM
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value)
+{
+ uint32_t portNum;
+ uint32_t tempReg;
+ HSIOM_PRT_Type* portAddrHSIOM;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
+
+ portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ if(pinNum < CY_GPIO_PRT_HALF)
+ {
+ tempReg = portAddrHSIOM->PORT_SEL0 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ portAddrHSIOM->PORT_SEL0 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ }
+ else
+ {
+ pinNum -= CY_GPIO_PRT_HALF;
+ tempReg = portAddrHSIOM->PORT_SEL1 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ portAddrHSIOM->PORT_SEL1 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetHSIOM
+****************************************************************************//**
+*
+* \brief Returns the current HSIOM multiplexer connection to the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* HSIOM input selection
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetHSIOM
+*
+*******************************************************************************/
+__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ uint32_t returnValue;
+ uint32_t portNum;
+ HSIOM_PRT_Type* portAddrHSIOM;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
+ portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
+
+ if(pinNum < CY_GPIO_PRT_HALF)
+ {
+ returnValue = (portAddrHSIOM->PORT_SEL0 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
+ }
+ else
+ {
+ pinNum -= CY_GPIO_PRT_HALF;
+ returnValue = (portAddrHSIOM->PORT_SEL1 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK;
+ }
+
+ return (en_hsiom_sel_t)returnValue;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_PortToAddr
+****************************************************************************//**
+*
+* \brief Retrieves the port address based on the given port number.
+*
+* This is a helper function to calculate the port base address when given a port
+* number. It is to be used when pin access needs to be calculated at runtime.
+*
+* \param portNum
+* Port number
+*
+* \return
+* Base address of the port register structure
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_PortToAddr
+*
+*******************************************************************************/
+__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
+{
+ GPIO_PRT_Type* base;
+
+ if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
+ {
+ base = (GPIO_PRT_Type *)(GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
+ }
+ else
+ {
+ /* Error: Return default base address */
+ base = (GPIO_PRT_Type *)(GPIO_BASE);
+ }
+
+ return (base);
+}
+
+/** \} group_gpio_functions_init */
+
+/**
+* \addtogroup group_gpio_functions_gpio
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Read
+****************************************************************************//**
+*
+* \brief Reads the current logic level on the input buffer of the pin.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* Logic level present on the pin
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Read
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (base->IN >> (pinNum)) & CY_GPIO_IN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Write
+****************************************************************************//**
+*
+* \brief Write a logic 0 or logic 1 state to the output driver.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Logic level to drive out on the pin
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Write
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ /* Thread-safe: Directly access the pin registers instead of base->OUT */
+ if(0UL == value)
+ {
+ base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum;
+ }
+ else
+ {
+ base->OUT_SET = CY_GPIO_OUT_MASK << pinNum;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_ReadOut
+****************************************************************************//**
+*
+* \brief Reads the current logic level on the pin output driver.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Logic level on the pin output driver
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_ReadOut
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->OUT >> pinNum) & CY_GPIO_OUT_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Set
+****************************************************************************//**
+*
+* \brief Set a pin output to logic state high.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ base->OUT_SET = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Clr
+****************************************************************************//**
+*
+* \brief Set a pin output to logic state Low.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Clr
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_Inv
+****************************************************************************//**
+*
+* \brief Set a pin output logic state to the inverse of the current output
+* logic state.
+*
+* This function should be used only for software driven pins. It does not have
+* any effect on peripheral driven pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Inv
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ base->OUT_INV = CY_GPIO_OUT_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetDrivemode
+****************************************************************************//**
+*
+* \brief Configures the pin output buffer drive mode and input buffer enable.
+*
+* The output buffer drive mode and input buffer enable are combined into a single
+* parameter. The drive mode controls the behavior of the pin in general.
+* Enabling the input buffer allows the digital pin state to be read but also
+* contributes to extra current consumption.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDrivemode
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value));
+
+ pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET;
+ tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << pinLoc));
+ base->CFG = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetDrivemode
+****************************************************************************//**
+*
+* \brief Returns the pin output buffer drive mode and input buffer enable state.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDrivemode
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVtrip
+****************************************************************************//**
+*
+* \brief Configures the GPIO pin input buffer voltage threshold mode.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtrip
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg = base->CFG_IN & ~(CY_GPIO_CFG_IN_VTRIP_SEL_MASK << pinNum);
+ base->CFG_IN = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVtrip
+****************************************************************************//**
+*
+* \brief Returns the pin input buffer voltage threshold mode.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtrip
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_IN >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetSlewRate
+****************************************************************************//**
+*
+* \brief Configures the pin output buffer slew rate.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSlewRate
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum);
+ base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetSlewRate
+****************************************************************************//**
+*
+* \brief Returns the pin output buffer slew rate.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSlewRate
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_OUT >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetDriveSel
+****************************************************************************//**
+*
+* \brief Configures the pin output buffer drive strength.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDriveSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value));
+
+ pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET;
+ tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
+ base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetDriveSel
+****************************************************************************//**
+*
+* \brief Returns the pin output buffer drive strength.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDriveSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return ((base->CFG_OUT >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
+ & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK);
+}
+
+/** \} group_gpio_functions_gpio */
+
+/**
+* \addtogroup group_gpio_functions_sio
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVregEn
+****************************************************************************//**
+*
+* \brief Configures the SIO pin pair output buffer regulation mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVregEn
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET;
+ tempReg = base->CFG_SIO & ~(CY_GPIO_VREG_EN_MASK << pinLoc);
+ base->CFG_SIO = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVregEn
+****************************************************************************//**
+*
+* \brief Returns the SIO pin pair output buffer regulation mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVregEn
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_SIO >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetIbufMode
+****************************************************************************//**
+*
+* \brief Configures the SIO pin pair input buffer mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetIbufMode
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT;
+ tempReg = (base->CFG_SIO & ~(CY_GPIO_IBUF_MASK << pinLoc));
+ base->CFG_SIO = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetIbufMode
+****************************************************************************//**
+*
+* \brief Returns the SIO pin pair input buffer mode.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetIbufMode
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVtripSel
+****************************************************************************//**
+*
+* \brief Configures the SIO pin pair input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtripSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT;
+ tempReg = (base->CFG_SIO & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc));
+ base->CFG_SIO = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVtripSel
+****************************************************************************//**
+*
+* \brief Returns the SIO pin pair input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtripSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVrefSel
+****************************************************************************//**
+*
+* \brief Configures the SIO reference voltage for the input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVrefSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT;
+ tempReg = (base->CFG_SIO & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
+ base->CFG_SIO = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVrefSel
+****************************************************************************//**
+*
+* \brief Returns the SIO reference voltage for the input buffer trip point.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVrefSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetVohSel
+****************************************************************************//**
+*
+* \brief Configures the regulated output reference multiplier for the SIO pin pair.
+*
+* The regulated output reference controls both the output level of digital output
+* pin and the input trip point of digital input pin in the SIO pair.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \param value
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVohSel
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(value));
+
+ pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT;
+ tempReg = (base->CFG_SIO & ~(CY_GPIO_VOH_SEL_MASK << pinLoc));
+ base->CFG_SIO = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetVohSel
+****************************************************************************//**
+*
+* \brief Returns the regulated output reference multiplier for the SIO pin pair.
+*
+* Note that this function has no effect on non-SIO pins.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+*
+* \return
+* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVohSel
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
+
+ return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK;
+}
+
+/** \} group_gpio_functions_sio */
+
+/**
+* \addtogroup group_gpio_functions_interrupt
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptStatus
+****************************************************************************//**
+*
+* \brief Returns the current unmasked interrupt state of the pin.
+*
+* The core processor's NVIC is triggered by the masked interrupt bits. This
+* function allows reading the unmasked interrupt state. Whether the bit
+* positions actually trigger the interrupt are defined by the interrupt mask bits.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt condition not detected
+* 1 = Pin interrupt condition detected
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (base->INTR >> pinNum) & CY_GPIO_INTR_STATUS_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_ClearInterrupt
+****************************************************************************//**
+*
+* \brief Clears the triggered pin interrupt.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
+ (void)base->INTR;
+
+ base->INTR = CY_GPIO_INTR_STATUS_MASK << pinNum;
+
+ /* This read ensures that the initial write has been flushed out to the hardware */
+ (void)base->INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetInterruptMask
+****************************************************************************//**
+*
+* \brief Configures the pin interrupt to be forwarded to the CPU NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \param value
+* 0 = Pin interrupt not forwarded to CPU interrupt controller
+* 1 = Pin interrupt masked and forwarded to CPU interrupt controller
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value));
+
+ tempReg= base->INTR_MASK & ~(CY_GPIO_INTR_EN_MASK << pinNum);
+ base->INTR_MASK = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptMask
+****************************************************************************//**
+*
+* \brief Returns the state of the pin interrupt mask.
+*
+* This mask is used to determine whether the pin is configured to be forwarded
+* to the CPU NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt not forwarded to CPU interrupt controller
+* 1 = Pin interrupt masked and forwarded to CPU interrupt controller
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (base->INTR_MASK >> pinNum) & CY_GPIO_INTR_EN_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* \brief Return the pin's current interrupt state after being masked.
+*
+* The core processor's NVIC is triggered by the masked interrupt bits. This
+* function allows reading this masked interrupt state. Note that the bits that
+* are not masked will not be forwarded to the NVIC.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller
+* 1 = Pin interrupt detected and forwarded to CPU interrupt controller
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (base->INTR_MASKED >> pinNum) & CY_GPIO_INTR_MASKED_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetSwInterrupt
+****************************************************************************//**
+*
+* \brief Force a pin interrupt to trigger.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* void
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSwInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ base->INTR_SET = CY_GPIO_INTR_SET_MASK << pinNum;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetInterruptEdge
+****************************************************************************//**
+*
+* \brief Configures the type of edge that will trigger a pin interrupt.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \param value
+* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptEdge
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
+{
+ uint32_t tempReg;
+ uint32_t pinLoc;
+
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+ CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(value));
+
+ pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET;
+ tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc);
+ base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptEdge
+****************************************************************************//**
+*
+* \brief Returns the current pin interrupt edge type.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param pinNum
+* Position of the pin bit-field within the port register.
+* Bit position 8 is the routed pin through the port glitch filter.
+*
+* \return
+* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptEdge
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum)
+{
+ CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
+
+ return (base->INTR_CFG >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_SetFilter
+****************************************************************************//**
+*
+* \brief Configures which pin on the port connects to the port-specific glitch filter.
+*
+* Each port contains a single 50ns glitch filter. Any of the pins on the port
+* can be routed to this filter such that the input signal is filtered before
+* reaching the edge-detect interrupt circuitry. The state of the filterred pin
+* can also be read by calling the Cy_GPIO_Read() function.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \param value
+* The number of the port pin to route to the port filter (0...7)
+*
+* \return
+* void
+*
+* \note
+* This function modifies a port register in a read-modify-write operation. It is
+* not thread safe as the resource is shared among multiple pins on a port.
+*
+* \note
+* The filtered pin does not have an associated HSIOM connection. Therefore
+* it cannot be routed directly to other peripherals in hardware.
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetFilter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value)
+{
+ uint32_t tempReg;
+
+ CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value));
+
+ tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
+ base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetFilter
+****************************************************************************//**
+*
+* \brief Returns which pin is currently configured to connect to the port-specific
+* glitch filter.
+*
+* Each port contains a single 50ns glitch filter. Any of the pins on the port
+* can be routed to this filter such that the input signal is filtered before
+* reaching the edge-detect interrupt circuitry. The state of the filterred pin
+* can also be read by calling the Cy_GPIO_Read() function.
+*
+* \param base
+* Pointer to the pin's port register base address
+*
+* \return
+* The number of the port pin routed to the port filter (0...7)
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetFilter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base)
+{
+ return (base->INTR_CFG >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK;
+}
+
+
+#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause0
+****************************************************************************//**
+*
+* \brief Returns the interrupt status for ports 0 to 31.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected and sent to CPU interrupt controller on port
+*
+* \funcusage
+* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptCause0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void)
+{
+ return GPIO->INTR_CAUSE0;
+}
+
+#endif
+
+#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause1
+****************************************************************************//**
+*
+* \brief Returns the interrupt status for ports 32 to 63.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected and sent to CPU interrupt controller on port
+*
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void)
+{
+ return GPIO->INTR_CAUSE1;
+}
+
+#endif
+
+#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause2
+****************************************************************************//**
+*
+* \brief Returns the interrupt status for ports 64 to 95.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected and sent to CPU interrupt controller on port
+*
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void)
+{
+ return GPIO->INTR_CAUSE2;
+}
+
+#endif
+
+#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_GPIO_GetInterruptCause3
+****************************************************************************//**
+*
+* \brief Returns the interrupt status for ports 96 to 127.
+*
+* \return
+* 0 = Interrupt not detected on port
+* 1 = Interrupt detected and sent to CPU interrupt controller on port
+*
+* \funcusage
+* Refer to the Cy_GPIO_GetInterruptCause0() example.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void)
+{
+ return GPIO->INTR_CAUSE3;
+}
+
+#endif
+
+/** \} group_gpio_functions_interrupt */
+
+/** \} group_gpio_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_GPIO_H */
+
+/** \} group_gpio */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,287 @@
+/***************************************************************************//**
+* \file cy_i2s.c
+* \version 2.0.1
+*
+* The source code file for the I2S driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_i2s.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_Init
+****************************************************************************//**
+*
+* Initializes the I2S module in accordance with a configuration structure.
+*
+* \pre If the I2S module is initialized previously, the \ref Cy_I2S_DeInit()
+* must be called before calling this function.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \param config The pointer to a configuration structure.
+*
+* \return error / status code. See \ref cy_en_i2s_status_t.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init
+*
+*******************************************************************************/
+cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config)
+{
+ cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM;
+
+ if((NULL != base) && (NULL != config))
+ {
+ cy_en_i2s_ws_pw_t wsPulseWidth;
+ cy_en_i2s_len_t channelLength;
+ uint32_t channels;
+ uint32_t clockDiv = (uint32_t)config->clkDiv - 1U;
+
+ CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv));
+
+ /* The clock setting */
+ base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) |
+ _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk);
+
+ /* The Tx setting */
+ if (config->txEnabled)
+ {
+ CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment));
+ CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue));
+
+ if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment))
+ {
+ channels = (uint32_t)config->txChannels - 1UL;
+ wsPulseWidth = config->txWsPulseWidth;
+ channelLength = CY_I2S_LEN32;
+
+ CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
+ CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
+ CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength));
+ }
+ else
+ {
+ channels = 1UL;
+ wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
+ channelLength = config->txChannelLength;
+
+ CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength));
+ }
+
+ CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels));
+
+ base->TX_WATCHDOG = config->txWatchdogValue;
+
+ base->TX_CTL = _VAL2FLD(I2S_TX_CTL_I2S_MODE, config->txAlignment) |
+ _BOOL2FLD(I2S_TX_CTL_B_CLOCK_INV, config->txSdoLatchingTime) |
+ _VAL2FLD(I2S_TX_CTL_CH_NR, channels) |
+ _BOOL2FLD(I2S_TX_CTL_MS, config->txMasterMode) |
+ _VAL2FLD(I2S_TX_CTL_WS_PULSE, wsPulseWidth) |
+ _BOOL2FLD(I2S_TX_CTL_WD_EN, config->txWatchdogEnable) |
+ _BOOL2FLD(I2S_TX_CTL_SCKO_POL, config->txSckoInversion) |
+ _BOOL2FLD(I2S_TX_CTL_SCKI_POL, config->txSckiInversion) |
+ _VAL2FLD(I2S_TX_CTL_CH_LEN, channelLength) |
+ _VAL2FLD(I2S_TX_CTL_WORD_LEN, config->txWordLength) |
+ _VAL2FLD(I2S_TX_CTL_OVHDATA, config->txOverheadValue);
+ }
+
+ /* The Rx setting */
+ if (config->rxEnabled)
+ {
+ CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment));
+
+ if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment))
+ {
+ channels = (uint32_t)config->rxChannels - 1UL;
+ wsPulseWidth = config->rxWsPulseWidth;
+ channelLength = CY_I2S_LEN32;
+
+ CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
+ CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
+ CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength));
+ }
+ else
+ {
+ channels = 1UL;
+ wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
+ channelLength = config->rxChannelLength;
+
+ CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength));
+ }
+
+ CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels));
+
+ base->RX_WATCHDOG = config->rxWatchdogValue;
+
+ base->RX_CTL = _VAL2FLD(I2S_RX_CTL_I2S_MODE, config->rxAlignment) |
+ _BOOL2FLD(I2S_RX_CTL_B_CLOCK_INV, config->rxSdiLatchingTime) |
+ _VAL2FLD(I2S_RX_CTL_CH_NR, channels) |
+ _BOOL2FLD(I2S_RX_CTL_MS, config->rxMasterMode) |
+ _VAL2FLD(I2S_RX_CTL_WS_PULSE, wsPulseWidth) |
+ _BOOL2FLD(I2S_RX_CTL_WD_EN, config->rxWatchdogEnable) |
+ _BOOL2FLD(I2S_RX_CTL_SCKO_POL, config->rxSckoInversion) |
+ _BOOL2FLD(I2S_RX_CTL_SCKI_POL, config->rxSckiInversion) |
+ _VAL2FLD(I2S_RX_CTL_CH_LEN, channelLength) |
+ _VAL2FLD(I2S_RX_CTL_WORD_LEN, config->rxWordLength) |
+ _BOOL2FLD(I2S_RX_CTL_BIT_EXTENSION, config->rxSignExtension);
+ }
+
+ /* The I2S enable setting */
+ if (config->txEnabled)
+ {
+ base->CTL |= I2S_CTL_TX_ENABLED_Msk;
+ }
+
+ if (config->rxEnabled)
+ {
+ base->CTL |= I2S_CTL_RX_ENABLED_Msk;
+ }
+
+ /* The FIFO setting */
+ if (config->txEnabled)
+ {
+ base->TX_FIFO_CTL = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel);
+
+ base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_TX_REQ_EN, config->txDmaTrigger);
+ }
+
+ if (config->rxEnabled)
+ {
+ base->RX_FIFO_CTL = _VAL2FLD(I2S_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel);
+
+ base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger);
+ }
+
+ ret = CY_I2S_SUCCESS;
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_DeInit
+****************************************************************************//**
+*
+* Uninitializes the I2S module (reverts default register values).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeInit
+*
+*******************************************************************************/
+void Cy_I2S_DeInit(I2S_Type * base)
+{
+ base->INTR_MASK = 0UL; /* Disable interrupts prior to stopping the operation */
+ base->CMD = 0UL;
+ base->TR_CTL = 0UL;
+ base->TX_FIFO_CTL = 0UL;
+ base->RX_FIFO_CTL = 0UL;
+ base->CTL = 0UL;
+ base->TX_CTL = CY_I2S_TX_CTL_DEFAULT;
+ base->RX_CTL = CY_I2S_RX_CTL_DEFAULT;
+ base->TX_WATCHDOG = 0UL;
+ base->RX_WATCHDOG = 0UL;
+ base->CLOCK_CTL = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_DeepSleepCallback
+****************************************************************************//**
+*
+* This is a callback function to be used at the application layer to
+* manage an I2S operation during the Deep-Sleep cycle. It stores the I2S state
+* (Tx/Rx enabled/disabled/paused) into the context structure and stops the
+* communication before entering into Deep-Sleep power mode and restores the I2S
+* state after waking up.
+*
+* \param
+* callbackParams - The pointer to the callback parameters structure,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \return the SysPm callback status \ref cy_en_syspm_status_t.
+*
+* \note Use the \ref cy_stc_i2s_context_t data type for definition of the
+* *context element of the \ref cy_stc_syspm_callback_params_t strusture.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeepSleepCallback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams)
+{
+ cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS;
+ CY_ASSERT_L1(NULL != callbackParams->context);
+ I2S_Type * locBase = (I2S_Type*) callbackParams->base;
+ uint32_t * locInterruptMask = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->interruptMask);
+ uint32_t * locState = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->enableState);
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ case CY_SYSPM_CHECK_FAIL:
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ *locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */
+ *locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */
+ if (0UL != (*locState & I2S_CMD_TX_START_Msk))
+ {
+ Cy_I2S_DisableTx(locBase); /* Stop TX operation */
+ }
+ if (0UL != (*locState & I2S_CMD_RX_START_Msk))
+ {
+ Cy_I2S_DisableRx(locBase); /* Stop RX operation */
+ }
+ Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */
+ /* Unload FIFOs in order not to lose data (if needed) */
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ if (0UL != (*locState & I2S_CMD_RX_START_Msk))
+ {
+ Cy_I2S_ClearRxFifo(locBase); /* Clear the RX FIFO */
+ Cy_I2S_EnableRx(locBase); /* Start RX operation */
+ }
+ if (0UL != (*locState & I2S_CMD_TX_START_Msk))
+ {
+ Cy_I2S_ClearTxFifo(locBase); /* Clear the TX FIFO */
+ Cy_I2S_WriteTxData(locBase, 0UL); /* Fill at least one TX frame */
+ Cy_I2S_WriteTxData(locBase, 0UL);
+ if (0UL != (*locState & I2S_CMD_TX_PAUSE_Msk))
+ {
+ Cy_I2S_PauseTx(locBase); /* Restore the TX paused state */
+ }
+ Cy_I2S_EnableTx(locBase); /* Start TX operation */
+ }
+ Cy_I2S_ClearInterrupt(locBase, *locInterruptMask); /* Clear possible pending I2S interrupts */
+ Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */
+ break;
+
+ default:
+ ret = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return(ret);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1087 @@
+/***************************************************************************//**
+* \file cy_i2s.h
+* \version 2.0.1
+*
+* The header file of the I2S driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_i2s Inter-IC Sound (I2S)
+* \{
+* The I2S driver provides a function API to manage Inter-IC Sound. I2S is used
+* to send digital audio streaming data to external I2S devices, such as audio
+* codecs or simple DACs. It can also receive digital audio streaming data.
+*
+* Features:
+* * An industry standard NXP I2S interface.
+* * Supports master/slave TX/RX operation.
+* * Programmable Channel/Word Lengths.
+* * Supports External Clock operation.
+*
+* The I2S bus is an industry standard. The hardware interface was
+* developed by Philips Semiconductors (now NXP Semiconductors).
+*
+* \section group_i2s_configuration_considerations Configuration Considerations
+*
+* To set up an I2S, provide the configuration parameters in the
+* \ref cy_stc_i2s_config_t structure.
+*
+* For example, for Tx configuration, set txEnabled to true, configure
+* txDmaTrigger (depending on whether DMA is going to be used or not), set
+* extClk (if an external clock is used), provide clkDiv, txMasterMode,
+* txAlignment, txChannels (only 2 is supported in I2S and Left Justified modes)
+* txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength,
+* txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue
+* (both for Slave mode only, and when the watchdog interrupt will be used),
+* either txSckoInversion or txSckiInversion (based on txMasterMode setting),
+* txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue
+* (only when the word length is less than channel length).
+* A similar setup is for the Rx configuration.
+*
+* To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the
+* filled \ref cy_stc_i2s_config_t structure.
+* Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then
+* fill the first Tx data frame by calling \ref Cy_I2S_WriteTxData once for each
+* channel (e.g. twice for I2S mode with only two channels) with zero data. Then
+* call the \ref Cy_I2S_EnableTx itself.
+* For the reception the sequence is the same except for filling the first data
+* frame, just RX FIFO clearing is enough.
+*
+* For example:
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init
+*
+* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts
+* (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask.
+*
+* For example, if the trigger interrupt is used, during operation the ISR
+* should call the \ref Cy_I2S_WriteTxData as many times as required for your
+* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt
+* with appropriate parameters.
+*
+* The I2S/Left Justified data formats always contains two data channels.
+* They are ordered one-by-one in the FIFOs, left always goes first.
+* So in case of mono audio stream transmission, each sample can be put twice
+* into the TX FIFO (in this case both channels will sound the same),
+* or combined with zeroes: sample1-zero-sample2-zero (in this case only the
+* left channel will finally sound, for right-only case zero should go first).
+* The TDM frame word order in FIFOs is similar, one-by-one.
+*
+* If a DMA is used and the DMA channel is properly configured - no CPU activity
+* (or any application code) is needed for I2S operation.
+*
+* The I2S frame appears as:
+* \image html i2s_frame.png
+* This is an example for the channel length = 32. A similar is for all the rest
+* channel lengths, with one limitation: the word length could be less or equal
+* to the channel length. See the device Technical Reference Manual (TRM)
+* for more details.
+*
+* \section group_i2s_more_information More Information
+* See: the the I2S chapter of the device technical reference manual (TRM);
+* I2S_PDL Component datasheet;
+* CE218636 - PSOC 6 MCU INTER-IC SOUND (I2S) EXAMPLE.
+*
+* \section group_i2s_MISRA MISRA-C Compliance
+* The I2S driver has the following specific deviations:
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to the object type and
+* a different pointer to the object type.</td>
+* <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in this
+* function becomes the user responsibility because the pointer is
+* initialized when a callback is registered in the SysPm driver.</td>
+* </tr>
+* </table>
+*
+* \section group_i2s_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.0.1</td>
+* <td>Added Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>The slave operation is added, Left Justified and TDM modes are added</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_i2s_macros Macros
+* \defgroup group_i2s_functions Functions
+* \{
+* \defgroup group_i2s_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_i2s_data_structures Data Structures
+* \defgroup group_i2s_enums Enumerated Types
+*/
+
+
+#if !defined CY_I2S_H
+#define CY_I2S_H
+
+#include <stddef.h>
+#include <stdbool.h>
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXAUDIOSS
+ #error "The I2S driver is not supported on this device"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \addtogroup group_i2s_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_I2S_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_I2S_DRV_VERSION_MINOR 0
+
+/** The I2S driver identifier */
+#define CY_I2S_ID (CY_PDL_DRV_ID(0x20U))
+
+/**
+* \defgroup group_i2s_macros_intrerrupt_masks Interrupt Masks
+* \{
+*/
+
+/** Bit 0: Less entries in the TX FIFO than specified by Trigger Level. */
+#define CY_I2S_INTR_TX_TRIGGER (I2S_INTR_TX_TRIGGER_Msk)
+/** Bit 1: TX FIFO is not full. */
+#define CY_I2S_INTR_TX_NOT_FULL (I2S_INTR_TX_NOT_FULL_Msk)
+/** Bit 4: TX FIFO is empty, i.e. it has 0 entries. */
+#define CY_I2S_INTR_TX_EMPTY (I2S_INTR_TX_EMPTY_Msk)
+/** Bit 5: Attempt to write to a full TX FIFO. */
+#define CY_I2S_INTR_TX_OVERFLOW (I2S_INTR_TX_OVERFLOW_Msk)
+/** Bit 6: Attempt to read from an empty TX FIFO.
+* This happens when the IP is ready to transfer data and TX_EMPTY is '1'. */
+#define CY_I2S_INTR_TX_UNDERFLOW (I2S_INTR_TX_UNDERFLOW_Msk)
+/** Bit 8: Tx watchdog event occurs. */
+#define CY_I2S_INTR_TX_WD (I2S_INTR_TX_WD_Msk)
+/** Bit 16: More entries in the RX FIFO than specified by Trigger Level. */
+#define CY_I2S_INTR_RX_TRIGGER (I2S_INTR_RX_TRIGGER_Msk)
+/** Bit 18: RX FIFO is not empty. */
+#define CY_I2S_INTR_RX_NOT_EMPTY (I2S_INTR_RX_NOT_EMPTY_Msk)
+/** Bit 19: RX FIFO is full. */
+#define CY_I2S_INTR_RX_FULL (I2S_INTR_RX_FULL_Msk)
+/** Bit 21: Attempt to write to a full RX FIFO. */
+#define CY_I2S_INTR_RX_OVERFLOW (I2S_INTR_RX_OVERFLOW_Msk)
+/** Bit 22: Attempt to read from an empty RX FIFO. */
+#define CY_I2S_INTR_RX_UNDERFLOW (I2S_INTR_RX_UNDERFLOW_Msk)
+/** Bit 24: Rx watchdog event occurs. */
+#define CY_I2S_INTR_RX_WD (I2S_INTR_RX_WD_Msk)
+
+/** \} group_i2s_macros_intrerrupt_masks */
+
+
+/**
+* \defgroup group_i2s_macros_current_state Current State
+* \{
+*/
+
+/** Transmission is active */
+#define CY_I2S_TX_START (I2S_CMD_TX_START_Msk)
+/** Transmission is paused */
+#define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk)
+/** Reception is active */
+#define CY_I2S_RX_START (I2S_CMD_RX_START_Msk)
+
+/** \} group_i2s_macros_current_state */
+
+/** \} group_i2s_macros */
+
+/**
+* \addtogroup group_i2s_enums
+* \{
+*/
+
+/**
+* I2S status definitions.
+*/
+
+typedef enum
+{
+ CY_I2S_SUCCESS = 0x00UL, /**< Successful. */
+ CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */
+} cy_en_i2s_status_t;
+
+
+/**
+* I2S data alignment.
+*/
+typedef enum
+{
+ CY_I2S_LEFT_JUSTIFIED = 0U, /**< Left justified. */
+ CY_I2S_I2S_MODE = 1U, /**< I2S mode. */
+ CY_I2S_TDM_MODE_A = 2U, /**< TDM mode A. */
+ CY_I2S_TDM_MODE_B = 3U /**< TDM mode B. */
+} cy_en_i2s_alignment_t;
+
+/**
+* I2S channel/word length.
+*/
+typedef enum
+{
+ CY_I2S_LEN8 = 0U, /**< Channel/word length: 8 bit. */
+ CY_I2S_LEN16 = 1U, /**< Channel/Word length: 16 bit. */
+ CY_I2S_LEN18 = 2U, /**< Channel/Word length: 18 bit. */
+ CY_I2S_LEN20 = 3U, /**< Channel/Word length: 20 bit. */
+ CY_I2S_LEN24 = 4U, /**< Channel/Word length: 24 bit. */
+ CY_I2S_LEN32 = 5U /**< Channel/Word length: 32 bit. */
+} cy_en_i2s_len_t;
+
+/**
+* I2S TX overhead value.
+*/
+typedef enum
+{
+ CY_I2S_OVHDATA_ZERO = 0U, /**< Fill overhead bits by zeroes. */
+ CY_I2S_OVHDATA_ONE = 1U, /**< Fill overhead bits by ones. */
+} cy_en_i2s_overhead_t;
+
+/**
+* I2S WS pulse width.
+*/
+typedef enum
+{
+ CY_I2S_WS_ONE_SCK_CYCLE = 0U, /**< WS pulse width is one SCK cycle. */
+ CY_I2S_WS_ONE_CHANNEL_LENGTH = 1U, /**< WS pulse width is one channel length. */
+} cy_en_i2s_ws_pw_t;
+
+/** \} group_i2s_enums */
+
+/**
+* \addtogroup group_i2s_data_structures
+* \{
+*/
+
+/**
+* I2S initialization configuration.
+*/
+typedef struct
+{
+ bool txEnabled; /**< Enables the I2S TX component: 'false': disabled. 'true': enabled. */
+ bool rxEnabled; /**< Enables the I2S RX component: 'false': disabled. 'true': enabled. */
+ bool txDmaTrigger; /**< 'false': TX DMA trigger disable, 'true': TX DMA trigger enable. */
+ bool rxDmaTrigger; /**< 'false': RX DMA trigger disable, 'true': RX DMA trigger enable. */
+ uint8_t clkDiv; /**< CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. */
+ bool extClk; /**< 'false': internal clock, 'true': external clock. */
+ bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */
+ cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */
+ cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width.
+ The value of this parameter is ignored in I2S and Left Justified modes
+ the WS pulse width is always "one channel length" in these modes. */
+ bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */
+ uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */
+ bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S
+ Standard, if txSckoInversion is false),
+ 'true': SDO bit starts at rising edge which goes before the above
+ mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK
+ period (if txSckoInversion is false).
+ If txSckoInversion is true - the rising/falling edges just swaps
+ in above explanations.
+ Effective only in slave mode, must be false in master mode.*/
+ bool txSckoInversion; /**< TX SCKO polarity:
+ 'false': When transmitter is in master mode, serial data is
+ transmitted off the falling bit clock edge (accordingly to
+ the I2S Standard);
+ 'true': When transmitter is in master mode, serial data is
+ transmitted off the rising bit clock edge.
+ Effective only in master mode. */
+ bool txSckiInversion; /**< TX SCKI polarity:
+ 'false': When transmitter is in slave mode, serial data is
+ transmitted off the falling bit clock edge (accordingly to
+ the I2S Standard);
+ 'true': When transmitter is in slave mode, serial data is
+ transmitted off the rising bit clock edge.
+ Effective only in slave mode. */
+ uint8_t txChannels; /**< Number of TX channels, valid range is 1...8 for TDM modes.
+ In the I2S and Left Justified modes the value of this parameter is
+ ignored - the real number of channels is always 2 in these modes. */
+ cy_en_i2s_len_t txChannelLength; /**< TX channel length, see #cy_en_i2s_len_t,
+ the value of this parameter is ignored in TDM modes, the real
+ channel length is 32 bit in these modes. */
+ cy_en_i2s_len_t txWordLength; /**< TX word length, see #cy_en_i2s_len_t,
+ must be less or equal to txChannelLength. */
+ cy_en_i2s_overhead_t txOverheadValue; /**< TX overhead bits value
+ when the word length is less than the channel length. */
+ uint8_t txFifoTriggerLevel; /**< TX FIFO interrupt trigger level (0, 1, ..., 255). */
+ bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */
+ cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */
+ cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width.
+ The value of this parameter is ignored in I2S and Left Justified modes
+ the WS pulse width is always "one channel length" in these modes. */
+ bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */
+ uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */
+ bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S
+ Standard if rxSckoInversion is false),
+ 'true': SDI bit starts at rising edge which goes after the above
+ mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK
+ period (if rxSckoInversion is false).
+ If rxSckoInversion is true - the rising/falling edges just swaps
+ in above explanations.
+ Effective only in master mode, must be false in slave mode. */
+ bool rxSckoInversion; /**< RX SCKO polarity:
+ 'false': When receiver is in master mode, serial data is
+ captured by the rising bit clock edge (accordingly to the
+ I2S Standard);
+ 'true': When receiver is in master mode, serial data is
+ captured by the falling bit clock edge.
+ Effective only in master mode. */
+ bool rxSckiInversion; /**< RX SCKI polarity:
+ 'false': When receiver is in slave mode, serial data is
+ captured by the rising bit clock edge (accordingly to the
+ I2S Standard);
+ 'true': When receiver is in slave mode, serial data is
+ captured by the falling bit clock edge.
+ Effective only in slave mode. */
+ uint8_t rxChannels; /**< Number of RX channels, valid range is 1...8 for TDM modes.
+ In the I2S and Left Justified modes the value of this parameter is
+ ignored - the real number of channels is always 2 in these modes. */
+ cy_en_i2s_len_t rxChannelLength; /**< RX channel length, see #cy_en_i2s_len_t,
+ the value of this parameter is ignored in TDM modes, the real
+ channel length is 32 bit in these modes. */
+ cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t,
+ must be less or equal to rxChannelLength. */
+ bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits),
+ 'false': all MSB are filled by zeroes,
+ 'true': all MSB are filled by the original sign bit value. */
+ uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level
+ (0, 1, ..., (255 - (number of channels))). */
+} cy_stc_i2s_config_t;
+
+
+/**
+ * The I2S backup structure type to be used for the SysPm callback.
+ * \ref Cy_I2S_DeepSleepCallback context definition.
+ *
+ * \cond Also can be used for other purposes to store the current Tx/Rx
+ * operation state and interrupt settings - the factors that are usually
+ * changed on the fly. \endcond
+ */
+typedef struct
+{
+ uint32_t enableState; /**< Stores the I2S state */
+ uint32_t interruptMask; /**< Stores the I2S interrupt mask */
+} cy_stc_i2s_context_t;
+
+/** \} group_i2s_data_structures */
+
+/** \cond INTERNAL */
+/******************************************************************************
+ * Local definitions
+*******************************************************************************/
+
+#define CY_I2S_INTR_MASK (CY_I2S_INTR_TX_TRIGGER | \
+ CY_I2S_INTR_TX_NOT_FULL | \
+ CY_I2S_INTR_TX_EMPTY | \
+ CY_I2S_INTR_TX_OVERFLOW | \
+ CY_I2S_INTR_TX_UNDERFLOW | \
+ CY_I2S_INTR_TX_WD | \
+ CY_I2S_INTR_RX_TRIGGER | \
+ CY_I2S_INTR_RX_NOT_EMPTY | \
+ CY_I2S_INTR_RX_FULL | \
+ CY_I2S_INTR_RX_OVERFLOW | \
+ CY_I2S_INTR_RX_UNDERFLOW | \
+ CY_I2S_INTR_RX_WD)
+
+/* Non-zero default values */
+#define CY_I2S_TX_CTL_CH_NR_DEFAULT (0x1U)
+#define CY_I2S_TX_CTL_I2S_MODE_DEFAULT (0x2U)
+#define CY_I2S_TX_CTL_WS_PULSE_DEFAULT (0x1U)
+#define CY_I2S_TX_CTL_CH_LEN_DEFAULT (0x4U)
+#define CY_I2S_TX_CTL_WORD_LEN_DEFAULT (0x4U)
+
+#define CY_I2S_TX_CTL_DEFAULT (_VAL2FLD(I2S_TX_CTL_CH_NR, CY_I2S_TX_CTL_CH_NR_DEFAULT) | \
+ _VAL2FLD(I2S_TX_CTL_I2S_MODE, CY_I2S_TX_CTL_I2S_MODE_DEFAULT) | \
+ _VAL2FLD(I2S_TX_CTL_WS_PULSE, CY_I2S_TX_CTL_WS_PULSE_DEFAULT) | \
+ _VAL2FLD(I2S_TX_CTL_CH_LEN, CY_I2S_TX_CTL_CH_LEN_DEFAULT) | \
+ _VAL2FLD(I2S_TX_CTL_WORD_LEN, CY_I2S_TX_CTL_WORD_LEN_DEFAULT))
+
+#define CY_I2S_RX_CTL_CH_NR_DEFAULT (0x1U)
+#define CY_I2S_RX_CTL_I2S_MODE_DEFAULT (0x2U)
+#define CY_I2S_RX_CTL_WS_PULSE_DEFAULT (0x1U)
+#define CY_I2S_RX_CTL_CH_LEN_DEFAULT (0x4U)
+#define CY_I2S_RX_CTL_WORD_LEN_DEFAULT (0x4U)
+
+#define CY_I2S_RX_CTL_DEFAULT (_VAL2FLD(I2S_RX_CTL_CH_NR, CY_I2S_RX_CTL_CH_NR_DEFAULT) | \
+ _VAL2FLD(I2S_RX_CTL_I2S_MODE, CY_I2S_RX_CTL_I2S_MODE_DEFAULT) | \
+ _VAL2FLD(I2S_RX_CTL_WS_PULSE, CY_I2S_RX_CTL_WS_PULSE_DEFAULT) | \
+ _VAL2FLD(I2S_RX_CTL_CH_LEN, CY_I2S_RX_CTL_CH_LEN_DEFAULT) | \
+ _VAL2FLD(I2S_RX_CTL_WORD_LEN, CY_I2S_RX_CTL_WORD_LEN_DEFAULT))
+
+/* Macros for conditions used by CY_ASSERT calls */
+#define CY_I2S_IS_ALIGNMENT_VALID(alignment) ((CY_I2S_LEFT_JUSTIFIED == (alignment)) || \
+ (CY_I2S_I2S_MODE == (alignment)) || \
+ (CY_I2S_TDM_MODE_A == (alignment)) || \
+ (CY_I2S_TDM_MODE_B == (alignment)))
+
+#define CY_I2S_IS_LEN_VALID(length) ((CY_I2S_LEN8 == (length)) || \
+ (CY_I2S_LEN16 == (length)) || \
+ (CY_I2S_LEN18 == (length)) || \
+ (CY_I2S_LEN20 == (length)) || \
+ (CY_I2S_LEN24 == (length)) || \
+ (CY_I2S_LEN32 == (length)))
+
+#define CY_I2S_IS_OVHDATA_VALID(overhead) ((CY_I2S_OVHDATA_ZERO == (overhead)) || \
+ (CY_I2S_OVHDATA_ONE == (overhead)))
+
+#define CY_I2S_IS_WSPULSE_VALID(wsPulse) ((CY_I2S_WS_ONE_SCK_CYCLE == (wsPulse)) || \
+ (CY_I2S_WS_ONE_CHANNEL_LENGTH == (wsPulse)))
+
+#define CY_I2S_IS_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 63U)
+#define CY_I2S_IS_CHANNELS_VALID(channels) ((channels) <= 7UL)
+#define CY_I2S_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_I2S_INTR_MASK)))
+
+#define CY_I2S_IS_CHAN_WORD_VALID(channel, word) ((CY_I2S_IS_LEN_VALID(channel)) && \
+ (CY_I2S_IS_LEN_VALID(word)) && \
+ ((channel) >= (word)))
+#define CY_I2S_IS_TRIG_LEVEL_VALID(trigLevel, channels) ((trigLevel) <= (255U - (channels)))
+
+/** \endcond */
+
+
+/**
+* \addtogroup group_i2s_functions
+* \{
+*/
+
+ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config);
+ void Cy_I2S_DeInit(I2S_Type * base);
+
+/** \addtogroup group_i2s_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
+/** \} */
+
+__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base);
+__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base);
+
+__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base);
+__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base);
+__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data);
+__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base);
+__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base);
+__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base);
+
+__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base);
+__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base);
+__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base);
+__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base);
+__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base);
+__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base);
+__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base);
+__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base);
+
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base);
+__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt);
+__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base);
+__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base);
+
+/*******************************************************************************
+* Function Name: Cy_I2S_EnableTx
+****************************************************************************//**
+*
+* Starts an I2S transmission. Interrupts enabling (by the
+* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
+* if any I2S interrupts are used in the application.
+*
+* \pre Cy_I2S_Init() must be called before.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableTx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base)
+{
+ base->CMD |= I2S_CMD_TX_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_PauseTx
+****************************************************************************//**
+*
+* Pauses an I2S transmission.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_PauseTx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base)
+{
+ base->CMD |= I2S_CMD_TX_PAUSE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ResumeTx
+****************************************************************************//**
+*
+* Resumes an I2S transmission.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ResumeTx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base)
+{
+ base->CMD &= (uint32_t) ~I2S_CMD_TX_PAUSE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_DisableTx
+****************************************************************************//**
+*
+* Stops an I2S transmission.
+*
+* \pre TX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required
+* prior to this function call, in case if any TX I2S interrupts are used.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableTx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base)
+{
+ base->CMD &= (uint32_t) ~I2S_CMD_TX_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_EnableRx
+****************************************************************************//**
+*
+* Starts an I2S reception. Interrupts enabling (by the
+* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
+* if any I2S interrupts are used in the application.
+*
+* \pre \ref Cy_I2S_Init() must be called before.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableRx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base)
+{
+ base->CMD |= I2S_CMD_RX_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_DisableRx
+****************************************************************************//**
+*
+* Stops an I2S reception.
+*
+* \pre RX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required
+* prior to this function call, in case if any RX I2S interrupts are used.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableRx
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base)
+{
+ base->CMD &= (uint32_t) ~I2S_CMD_RX_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetCurrentState
+****************************************************************************//**
+*
+* Returns the current I2S state (TX/RX running/paused/stopped).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current state \ref group_i2s_macros_current_state.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetCurrentState
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base)
+{
+ return (base->CMD & (I2S_CMD_TX_START_Msk | I2S_CMD_TX_PAUSE_Msk | I2S_CMD_RX_START_Msk));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ClearTxFifo
+****************************************************************************//**
+*
+* Clears the TX FIFO (resets the Read/Write FIFO pointers).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearTxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base)
+{
+ base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_CLEAR_Msk;
+ base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_CLEAR_Msk;
+ (void) base->TX_FIFO_CTL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetNumInTxFifo
+****************************************************************************//**
+*
+* Gets the number of used words in the TX FIFO.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current number of used words in the TX FIFO.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInTxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base)
+{
+ return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_WriteTxData
+****************************************************************************//**
+*
+* Writes data to the TX FIFO. Increases the TX FIFO level.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \param data Data to be written to the TX FIFO.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_WriteTxData
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data)
+{
+ base->TX_FIFO_WR = data;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetTxReadPointer
+****************************************************************************//**
+*
+* Gets the TX FIFO Read pointer. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current TX Read pointer value.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxReadPointer
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base)
+{
+ return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_RD_PTR, base->TX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetTxWritePointer
+****************************************************************************//**
+*
+* Gets the TX FIFO Write pointer. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current TX Write pointer value.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxWritePointer
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base)
+{
+ return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_WR_PTR, base->TX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_FreezeTxFifo
+****************************************************************************//**
+*
+* Freezes the TX FIFO. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeTxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base)
+{
+ base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_UnfreezeTxFifo
+****************************************************************************//**
+*
+* Unfreezes the TX FIFO. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeTxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base)
+{
+ base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ClearRxFifo
+****************************************************************************//**
+*
+* Clears the RX FIFO (resets the Read/Write FIFO pointers).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearRxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base)
+{
+ base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_CLEAR_Msk;
+ base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_CLEAR_Msk;
+ (void) base->RX_FIFO_CTL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetNumInRxFifo
+****************************************************************************//**
+*
+* Gets the number of used words in the RX FIFO.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current number of used words in rge RX FIFO.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInRxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base)
+{
+ return (_FLD2VAL(I2S_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ReadRxData
+****************************************************************************//**
+*
+* Reads data from the RX FIFO. Decreases the RX FIFO level.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The read data.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxData
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base)
+{
+ return (base->RX_FIFO_RD);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ReadRxDataSilent
+****************************************************************************//**
+*
+* Reads data from the RX FIFO without updating the RX FIFO read pointer.
+* This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The read data.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxDataSilent
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base)
+{
+ return (base->RX_FIFO_RD_SILENT);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetRxReadPointer
+****************************************************************************//**
+*
+* Gets the RX FIFO Read pointer. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current RX Read pointer value.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxReadPointer
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base)
+{
+ return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_RD_PTR, base->RX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetRxWritePointer
+****************************************************************************//**
+*
+* Gets the RX FIFO Write pointer. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The current RX Write pointer value.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxWritePointer
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base)
+{
+ return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_WR_PTR, base->RX_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_FreezeRxFifo
+****************************************************************************//**
+*
+* Freezes the RX FIFO. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeRxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base)
+{
+ base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_UnfreezeRxFifo
+****************************************************************************//**
+*
+* Unfreezes the RX FIFO. This function is rather for debug purposes.
+*
+* \param base The pointer to the I2S instance address.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeRxFifo
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base)
+{
+ base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetInterruptStatus
+****************************************************************************//**
+*
+* Gets an interrupt status (returns a content of the INTR register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base)
+{
+ return (base->INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_ClearInterrupt
+****************************************************************************//**
+*
+* Clears one or more interrupt factors (sets the INTR register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
+ base->INTR = interrupt;
+ (void) base->INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_SetInterrupt
+****************************************************************************//**
+*
+* Sets one or more interrupt factors (sets the INTR_SET register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
+ base->INTR_SET = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the interrupt mask (a content of the INTR_MASK register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base)
+{
+ return (base->INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_SetInterruptMask
+****************************************************************************//**
+*
+* Sets one or more interrupt factor masks (the INTR_MASK register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
+ base->INTR_MASK = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_I2S_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the interrupt status masked (a content of the INTR_MASKED register).
+*
+* \param base The pointer to the I2S instance address.
+*
+* \return The interrupt bit mask(s) \ref group_i2s_macros_intrerrupt_masks.
+*
+* \funcusage
+* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base)
+{
+ return (base->INTR_MASKED);
+}
+
+/** \} group_i2s_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_I2S_H */
+
+
+/** \} group_i2s */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,170 @@
+/***************************************************************************//**
+* \file cy_ipc_drv.c
+* \version 1.10.1
+*
+* \breif
+* IPC Driver - This source file contains the low-level driver code for
+* the IPC hardware.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_ipc_drv.h"
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_LockRelease
+****************************************************************************//**
+*
+* The function is used to release an IPC channel from the locked state.
+* The function also has a way to specify through a parameter which IPC
+* interrupts must be notified during the release event.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param releaseEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a release event.
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC channel
+* was released.
+* \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the
+* function call.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ /* Check to make sure the IPC is Acquired */
+ if( Cy_IPC_Drv_IsLockAcquired(base) )
+ {
+ /* The IPC was acquired, release the IPC channel */
+ Cy_IPC_Drv_ReleaseNotify(base, releaseEventIntr);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else /* The IPC channel was already released (not acquired) */
+ {
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SendMsgWord
+****************************************************************************//**
+*
+* This function is used to send a 32-bit word message through an IPC channel.
+* The function also has an associated notification field that will let the
+* message notify one or multiple IPC interrupts. The IPC channel is locked and
+* remains locked after the function returns. The receiver of the message should
+* release the channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a notification.
+*
+* \param message
+* The message word that is the data placed in the IPC data register.
+*
+* \return Status of the operation:
+* \retval CY_IPC_DRV_SUCCESS: The send operation was successful.
+* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(base) )
+ {
+ /* If the channel was acquired, send the message. */
+ Cy_IPC_Drv_WriteDataValue(base, message);
+
+ Cy_IPC_Drv_AcquireNotify(base, notifyEventIntr);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else
+ {
+ /* Channel was already acquired, return Error */
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadMsgWord
+****************************************************************************//**
+*
+* This function is used to read a 32-bit word message through an IPC channel.
+* This function assumes that the channel is locked (for a valid message).
+* If the channel is not locked, the message is invalid. The user must call
+* Cy_IPC_Drv_Release() function after reading the message to release the
+* IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param message
+* A variable where the read data is copied.
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC
+* was acquired.
+* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC
+* channel was already in a released state, meaning the data
+* may be invalid.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord
+*
+*******************************************************************************/
+cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message)
+{
+ cy_en_ipcdrv_status_t retStatus;
+
+ CY_ASSERT_L1(NULL != message);
+
+ if ( Cy_IPC_Drv_IsLockAcquired(base) )
+ {
+ /* The channel is locked; message is valid. */
+ *message = Cy_IPC_Drv_ReadDataValue(base);
+
+ retStatus = CY_IPC_DRV_SUCCESS;
+ }
+ else
+ {
+ /* The channel is not locked so channel is invalid. */
+ retStatus = CY_IPC_DRV_ERROR;
+ }
+ return(retStatus);
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,930 @@
+/***************************************************************************//**
+* \file cy_ipc_drv.h
+* \version 1.10.1
+*
+* Provides an API declaration of the IPC driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef CY_IPC_DRV_H
+#define CY_IPC_DRV_H
+
+
+/**
+* \defgroup group_ipc Inter Process Communication (IPC)
+* \{
+* The inter-processor communication (IPC) driver provides a safe and reliable
+* method to transfer data between CPUs. Hardware locking ensures that only one
+* device can acquire and transfer data at a time so no data is lost or
+* overwritten by asynchronous processes or CPUs.
+*
+* There are three parts to the API:
+* - Driver-level (DRV) API - used internally by Semaphore and Pipe levels
+* - Pipe-level (PIPE) API - establishes a communication channel between
+* processors
+* - Semaphore-level (SEMA) API - enables users to set and clear flags to
+* synchronize operations.
+*
+* Firmware does not need to use the DRV API. It can implement IPC functionality
+* entirely with the PIPE and SEMA APIs.
+*
+* \section group_ipc_background Background
+*
+* IPC is implemented in hardware as a collection of individual communication
+* channels, each with a set of 32-bit registers. The IPC design implements a set
+* of interrupts that enable each processor to notify the other that data is
+* available, or has been processed. There is also a locking mechanism that
+* allows only one CPU to gain access at a time.
+*
+* The Driver-level API manages each channel's registers to implement IPC
+* functionality. For information on the IPC registers, see the IPC chapter of
+* the Technical Reference Manual (TRM).
+*
+* At the hardware level, communication is a five-step process.
+* -# The sending processor acquires a channel
+* -# It puts data into the channel
+* -# The sender generates a notify event (interrupt)
+* -# The receiving processor identifies the sender and retrieves the data
+* -# The receiving processor generates a release event (interrupt)
+*
+* \image html ipc_driver.png
+*
+* These transactions are handled transparently by the DRV-level API. Use the
+* PIPE and SEMA layers of the API to implement communication in your application.
+* The data transferred is limited to a single 32-bit value. As implemented by
+* the PIPE API, that value is a pointer to a data structure of arbitrary size
+* and complexity.
+*
+* \section group_ipc_overview Overview
+*
+* The Pipe is the key element in the PDL design. A pipe is typically a
+* full-duplex communication channel between CPU cores. A pipe allows a single
+* conduit to transfer messages or data to and from multiple processes or CPUs.
+*
+* A pipe has two endpoints, one on each core. Each endpoint contains a dedicated
+* IPC channel and an interrupt. IPC channels 0-7 and IPC interrupts 0-7 are
+* reserved for system use.
+*
+* The pipe also contains the number of clients it supports, and for each client
+* a callback function. So the pipe can service a number of clients, each with a
+* separate callback function, on either endpoint. The number of clients a pipe
+* supports is the sum of each endpoint's clients.
+*
+* This design enables any number of processes on the sending core to put
+* arbitrary data into a single pipe. The first element of that data is the
+* client ID of the client that should handle the data.
+*
+* An interrupt notifies the receiving core that data is available. The receiving
+* core parses the data to identify the client, and then dispatches the event to
+* the appropriate client via the client callback function. An interrupt notifies
+* the sending core that the receiver is finished. In this way a single pipe can
+* manage arbitrary data transfers between cores with data flowing in either
+* direction.
+*
+* \image html ipc_ints.png
+*
+* The application can use semaphores to control access to shared resources, as
+* required by the application's logic.
+*
+* The PDL provides two specific files that set up default IPC functionality.
+* They are cy_ipc_config.h and cy_ipc_config.c. You can modify these files based
+* on the requirements of your design. If you use PSoC Creator as a development
+* environment, it will not overwrite your changes when you generate the
+* application or build your code.
+*
+* \section group_ipc_pipe_layer PIPE layer
+*
+* A pipe is a communication channel between two endpoints. PSoC 6 devices support
+* 16 IPC channels, and 16 IPC interrupts, each numbered 0-15. IPC Channels 0-7
+* and IPC interrupts 0-7 are reserved for system use. Channels 8-15 and
+* interrupts 8-15 are available for application use.
+*
+* A full duplex pipe uses two IPC channels, one per endpoint. Each endpoint
+* specifies all the information required to process a message (either sent or
+* received). Each endpoint is configured to use an IPC channel, and an IPC
+* interrupt. Common practice is to use the interrupt with the same number as
+* the IPC channel. However, IPC Interrupts are not directly associated with the
+* IPC channels, so any channel can use any interrupt. Any IPC channel can
+* trigger 0, 1 or all the IPC interrupts at once, depending on the Notify or
+* Release masks used.
+*
+* It is also possible to set up a one-directional pipe, using a single IPC
+* channel. In this design one processor is always the sender, and the other is
+* always the receiver. However, there are still two endpoints.
+*
+* A pipe supports an arbitrary number of clients with an array of callback
+* functions, one per client. The client ID is the index number into the array
+* for the client. After a pipe is configured and initialized, the application
+* calls Cy_IPC_Pipe_RegisterCallback() once per client to register each client's
+* callback function. Multiple clients can use the same callback function. The
+* endpoints in a pipe share the callback array.
+*
+* Use Cy_IPC_Pipe_SendMessage() to send data. You specify both the "to" and
+* "from" endpoints, and a callback function to be used when the data transfer is
+* complete. The data is a 32-bit void pointer. The data pointed to is arbitrary,
+* and can be an array, a structure, or a location in memory. The only limitation
+* is that the first element of the data must be a 32-bit unsigned word containing
+* a client ID number. The ID number is the index into the callback array.
+*
+* When a message is sent, the receiving endpoint's interrupt handler is called.
+* The ISR can perform any task required by the design. However, as part of its
+* function it calls \ref Cy_IPC_Pipe_ExecCallback. This function retrieves the
+* client ID from the data and calls the associated callback function.
+* The user-supplied callback function handles the data in whatever way is
+* appropriate based on the application logic.
+*
+* After the callback function is returned by the receiver, it invokes the release
+* callback function defined by the sender of the message.
+*
+* \section group_ipc_sema_layer SEMA Layer
+*
+* A semaphore is a flag the application uses to control access to a shared
+* resource. The SEMA-level API uses an IPC channel to implement
+* semaphores. Startup code sets up a default semaphore system. The
+* default system creates an array of 128 semaphores (four 32-bit values).
+* Semaphores 0-15 are reserved for system use. See
+* Configuration Considerations - SEMA.
+*
+* Functions are available to initialize the semaphore system, to set or
+* clear a semaphore, or to get the semaphore's current status. Application
+* logic uses SEMA functions to relate a particular semaphore to a particular
+* shared resource, and set, clear, or check the flag when accessing the
+* shared resource.
+*
+* \section group_ipc_configuration_cypipe Configuration Considerations - CYPIPE
+*
+* There are none. The cy_ipc_config files set up the required CYPIPE for system
+* use. Do not modify the CYPIPE. It uses IPC channels 5 and 6 to implement full
+* duplex communication between cores. On the CM0+ the notify interrupt is
+* assigned to NVIC IRQn 27. See System Interrupt (SysInt) for background.
+*
+* To create your own pipe you should make 3 steps:
+* -# Define pipe callbacks processing interrupt handler
+* -# Define your pipe configuration by cy_stc_ipc_pipe_config_t type structure
+* -# Call Cy_IPC_Pipe_Init() to initialize your pipe on both cores
+*
+* \section group_ipc_configuration_sema Configuration Considerations - SEMA
+*
+* Startup code calls Cy_IPC_SystemSemaInit() (in cy_ipc_config.c) to set up
+* semaphore functionality. This function calls the PDL init function
+* Cy_IPC_Sema_Init() with default values. By default the semaphore system
+* uses IPC channel 4, and creates 128 semaphores. Do <b>not</b> change the IPC
+* channel. You can change the number of semaphores.
+*
+* To change the number of semaphores, modify this line of code in cy_ipc_config.h.
+*
+* \code
+* #define CY_IPC_SEMA_COUNT (uint32_t)(128u)
+* \endcode
+*
+* The file cy_ipc_config.c declares array ipcSemaArray to hold the semaphore
+* flags based on the size defined for this symbol. Use increments of 32. You
+* must have at least 32 semaphores. Semaphores 0-15 are reserved for
+* system use. Your application can use semaphores greater than 15.
+*
+* \section group_ipc_more_information More Information
+*
+* Cy_IPC_SystemSemaInit() and Cy_IPC_SystemPipeInit() functions are called in the
+* SystemInit function. If the default startup file is not used, or SystemInit is
+* not called in your project, call the following three functions prior to
+* executing any flash or EmEEPROM write or erase operation. For example:
+* -# Cy_IPC_SystemSemaInit()
+* -# Cy_IPC_SystemPipeInit()
+* -# Cy_Flash_Init()
+*
+* Also Cy_IPC_SystemPipeInit function is called to support BLE host/controller
+* communication.
+*
+* See the technical reference manual(TRM) for more information on the IPC.
+*
+* \section group_ipc_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th style="width: 50%;">Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>The value of a complex expression of integer type shall be cast
+* only to a type of the same signedness that is no wider than the underlying
+* type of the expression.</td>
+* <td>The cast from integer to enumeration value is used to calculate
+* the interrupt vector source from the integer number of the IPC interrupt
+* structure, so there is no way to avoid this cast.</td>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to the void to a
+* pointer to the object type.</td>
+* <td>The cast from the void to pointer and vice versa is used to transmit
+* data via the \ref group_ipc channel by exchanging the pointer. We
+* exchange only one pointer, so there is no way to avoid this cast.</td>
+* </tr>
+* </table>
+*
+* \section group_ipc_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description of the \ref Cy_IPC_Pipe_Init,
+* \ref Cy_IPC_Pipe_EndpointInit, \ref Cy_IPC_Sema_Set functions.
+* Added / updated code snippets.
+* </td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added support for more IPC structures</td>
+* <td>New device support</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_ipc_drv IPC driver layer (IPC_DRV)
+* \{
+* The functions of this layer are used in the higher IPC levels
+* (Semaphores and Pipes).
+* Users should not call any of these IPC functions directly.
+*
+* \defgroup group_ipc_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_data_structures Data Structures
+* Data structures are used in the driver
+*
+* \defgroup group_ipc_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+* \defgroup group_ipc_sema IPC semaphores layer (IPC_SEMA)
+* \defgroup group_ipc_pipe IPC pipes layer (IPC_PIPE)
+*
+*/
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+#include "cy_ipc_config.h"
+#include <stddef.h>
+
+/**
+* \addtogroup group_ipc_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_IPC_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_IPC_DRV_VERSION_MINOR 10
+
+/** Defines a value to indicate that no notification events are needed */
+#define CY_IPC_NO_NOTIFICATION (uint32_t)(0x00000000ul)
+
+/* Error Code constants */
+#define CY_IPC_ID CY_PDL_DRV_ID(0x22u) /**< Software PDL driver ID for IPC */
+
+/** Return prefix for IPC driver function status codes */
+#define CY_IPC_ID_INFO (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_INFO )
+/** Return prefix for IPC driver function warning return values */
+#define CY_IPC_ID_WARNING (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_WARNING)
+/** Return prefix for IPC driver function error return values */
+#define CY_IPC_ID_ERROR (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_ERROR)
+
+/** Converts the IPC interrupt channel number to interrupt vector */
+#define CY_IPC_INTR_NUM_TO_VECT(x) ((int32_t)cpuss_interrupts_ipc_0_IRQn + (x))
+
+/** \} group_ipc_macros */
+
+/* end of definition in device.h */
+
+
+/**
+* \addtogroup group_ipc_enums
+* \{
+*/
+
+/**
+* This is a list of ENUMs used for function return status.
+*/
+typedef enum
+{
+ /** Function was successfully executed */
+ CY_IPC_DRV_SUCCESS = (0x00u),
+ /** Function was not executed due to an error.
+ Typical conditions for the error explained
+ in the function description */
+ CY_IPC_DRV_ERROR = ( CY_IPC_ID_ERROR + 1ul),
+} cy_en_ipcdrv_status_t;
+
+/** \} group_ipc_enums */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \cond INTERNAL */
+
+__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base);
+
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask);
+
+/** \endcond */
+
+/**
+* \addtogroup group_ipc_functions
+* \{
+*/
+
+__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex);
+__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex);
+
+__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
+__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr);
+
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base);
+cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr);
+__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base);
+
+cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type * base, uint32_t notifyEventIntr, uint32_t message);
+cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message);
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr);
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr);
+
+__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcNotifyMask);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus (IPC_INTR_STRUCT_Type const * base);
+__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcNotifyMask);
+__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base,
+ uint32_t ipcReleaseMask, uint32_t ipcNotifyMask);
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetIpcBaseAddress
+****************************************************************************//**
+*
+* This function takes an IPC channel index as a parameter and returns the base
+* address the IPC registers corresponding to the IPC channel.
+*
+* \note The user is responsible for ensuring that ipcIndex does not exceed the
+* limits.
+*
+* \param ipcIndex
+* Represents the number of IPC structure. This is converted to the base address of
+* the IPC channel registers.
+*
+* \return
+* Returns a pointer to the base of the IPC registers.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord
+*
+*******************************************************************************/
+__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex)
+{
+ CY_ASSERT_L1((uint32_t)CY_IPC_CHANNELS > ipcIndex);
+ return ( (IPC_STRUCT_Type*) ( &IPC->STRUCT[ipcIndex] ) );
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetIntrBaseAddr
+****************************************************************************//**
+*
+* This function takes an IPC interrupt structure index and returns the base
+* address of the IPC interrupt registers corresponding to the IPC Interrupt.
+*
+* \note The user is responsible for ensuring that ipcIntrIndex does not exceed the
+* limits.
+*
+* \param ipcIntrIndex
+* Represents the number of IPC interrupt structure. This is converted to the
+* base address of the IPC interrupt registers.
+*
+* \return
+* Returns a pointer to the base of the IPC interrupt registers.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex)
+{
+ CY_ASSERT_L1((uint32_t)CY_IPC_INTERRUPTS > ipcIntrIndex);
+ return ( (IPC_INTR_STRUCT_Type*) ( &IPC->INTR_STRUCT[ipcIntrIndex] ) );
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SetInterruptMask
+****************************************************************************//**
+*
+* This function is used to set the interrupt mask for an IPC Interrupt.
+* The mask sets release or acquire notification events for all IPC channels.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcNotifyMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base,
+ uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
+{
+ CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ base->INTR_MASK = _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_NOTIFY, ipcNotifyMask) |
+ _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_RELEASE, ipcReleaseMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptMask
+****************************************************************************//**
+*
+* This function is used to read the interrupt mask.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from
+* the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base)
+{
+ return (base->INTR_MASK);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* This function is used to read the active unmasked interrupt. This function
+* can be used in the interrupt service routine to find which source triggered
+* the interrupt.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base)
+{
+ return (base->INTR_MASKED);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetInterruptStatus
+****************************************************************************//**
+*
+* This function is used to read the pending interrupts. Note that this read is
+* an unmasked read of the interrupt status. Interrupt sources read as active by
+* this function would generate interrupts only if they were not masked.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \return
+* The return value is encoded as follows
+* <table>
+* <tr><th>Interrupt sources <th>Value
+* <tr><td>Ipc_PORTX_RELEASE <td>Xth bit set
+* <tr><td>Ipc_PORTX_NOTIFY <td>X+16th bit set
+* </table>
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base)
+{
+ return (base->INTR);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SetInterrupt
+****************************************************************************//**
+*
+* This function is used to set the interrupt source. This function can be used
+* to activate interrupts through software.
+* \note That interrupt sources set using this interrupt would generate interrupts
+* only if they are not masked.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcNotifyMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SetInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
+{
+ CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ base->INTR_SET = _VAL2FLD( IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask ) |
+ _VAL2FLD( IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask );
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ClearInterrupt
+****************************************************************************//**
+*
+* This function is used to clear the interrupt source. Use this function to clear
+* a pending interrupt source in the interrupt status.
+*
+* \param base
+* This is a handle to the IPC interrupt. This handle can be calculated from the
+* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr.
+*
+* \param ipcReleaseMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* release event.
+*
+* \param ipcNotifyMask
+* An encoded list of all IPC channels that can trigger the interrupt on a
+* notify event.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask)
+{
+ CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk)));
+ base->INTR = _VAL2FLD(IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask) |
+ _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask);
+ (void)base->INTR; /* Read the register to flush the cache */
+}
+
+/** \} group_ipc_functions */
+
+/** \} group_ipc */
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_AcquireNotify
+****************************************************************************//**
+*
+* The function generates a notify event by IPC interrupt structures.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt structures that are triggered
+* by a notification. Bit number correspond to number of the IPC interrupt
+* structure.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
+{
+ CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ base->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, notifyEventIntr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReleaseNotify
+****************************************************************************//**
+*
+* The function generates a notify event to an IPC interrupt structure.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered by a notification.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr)
+{
+ CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk)));
+ base->RELEASE = _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, notifyEventIntr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_WriteDataValue
+****************************************************************************//**
+*
+* The function writes a value to the DATA register of the IPC channel.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param dataValue
+* Value to be written.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue)
+{
+ base->DATA = dataValue;
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadDataValue
+****************************************************************************//**
+*
+* The function reads a value from the DATA register of the IPC channel.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Value from DATA register.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base)
+{
+ return (base->DATA);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_IsLockAcquired
+****************************************************************************//**
+*
+* The function is used to test the status of an IPC channel. The function
+* tells the reader if the IPC channel was in the locked or released state.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Status for the function:
+* true: The IPC channel is in the Locked state.
+* false: The IPC channel is in the Released state.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base)
+{
+ return ( 0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->LOCK_STATUS) );
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_GetLockStatus
+****************************************************************************//**
+*
+* The function is used to get the status of an IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \return
+* Value from LOCK_STATUS register.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetLockStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base)
+{
+ return (base->LOCK_STATUS);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ExtractAcquireMask
+****************************************************************************//**
+*
+* The function extracts an Acquire mask part from full interrupt mask value.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param intMask
+* Interrupt mask value to be processed.
+*
+* \return
+* Acquire mask value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask)
+{
+ return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_NOTIFY, intMask);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ExtractReleaseMask
+****************************************************************************//**
+*
+* The function extracts a Release mask part from full interrupt mask value.
+*
+* This function is internal and should not be called directly by user
+* software.
+*
+* \param intMask
+* Interrupt mask value to be processed.
+*
+* \return
+* Release mask value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask)
+{
+ return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_RELEASE, intMask);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_SendMsgPtr
+****************************************************************************//**
+*
+* This function is used to send a message pointer through an IPC channel.
+* The message structure may hold a generic pointer that may contain the address
+* of any user data type or structure. This parameter could be a pointer to a 32-bit
+* integer, an array, or even a data structure defined in the user code. This
+* function acts as a transfer engine for sending the pointer. Any memory
+* management of the pointer allocation and deallocation is up to the application
+* code.
+* The function also has an associated notification field that will let the
+* message notify one or multiple interrupts.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param notifyEventIntr
+* Bit encoded list of IPC interrupt lines that are triggered during the release
+* action.
+*
+* \param msgPtr
+* The message pointer that is being sent over the IPC channel.
+*
+* \return Status of the operation:
+* \retval CY_IPC_DRV_SUCCESS: The send operation was successful.
+* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because
+* it is already locked.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgPtr
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr)
+{
+ CY_ASSERT_L1(NULL != msgPtr);
+ return Cy_IPC_Drv_SendMsgWord(base, notifyEventIntr, (uint32_t)msgPtr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_ReadMsgPtr
+****************************************************************************//**
+*
+* This function is used to read a 32-bit pointer message through an IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress.
+*
+* \param msgPtr
+* Pointer variable to hold the data pointer that is being read from the IPC
+* channel.
+*
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC
+* was acquired.
+* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC
+* channel was already in a released state meaning the data
+* in it is invalid.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr)
+{
+ CY_ASSERT_L1(NULL != msgPtr);
+ return Cy_IPC_Drv_ReadMsgWord(base, (uint32_t *)msgPtr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Drv_LockAcquire
+****************************************************************************//**
+*
+* This function is used to acquire the IPC channel.
+*
+* \param base
+* This parameter is a handle that represents the base address of the registers
+* of the IPC channel.
+* The parameter is generally returned from a call to the \ref
+* Cy_IPC_Drv_GetIpcBaseAddress
+*
+* \return Status of the operation
+* \retval CY_IPC_DRV_SUCCESS: The IPC was successfully acquired
+* \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired
+* by another master
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base)
+{
+ return ( 0ul != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->ACQUIRE)) ? CY_IPC_DRV_SUCCESS : CY_IPC_DRV_ERROR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(CY_IPC_DRV_H) */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,565 @@
+/***************************************************************************//**
+* \file cy_ipc_pipe.c
+* \version 1.10.1
+*
+* Description:
+* IPC Pipe Driver - This source file includes code for the Pipe layer on top
+* of the IPC driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_ipc_pipe.h"
+
+/* Define a pointer to array of endPoints. */
+static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL;
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_Config
+****************************************************************************//**
+*
+* This function stores a copy of a pointer to the array of endpoints. All
+* access to endpoints will be via the index of the endpoint in this array.
+*
+* \note In general case, this function is called in the default startup code,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe customizations.
+*
+* \param theEpArray
+* This is the pointer to an array of endpoint structures that the designer
+* created and will be used to reference all endpoints.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Config
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray)
+{
+ /* Keep copy of this endpoint */
+ if (cy_ipc_pipe_epArray == NULL)
+ {
+ cy_ipc_pipe_epArray = theEpArray;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_Init
+****************************************************************************//**
+*
+* Initializes the system pipes. The system pipes are used by BLE.
+* \note The function should be called on all CPUs.
+*
+* \note In general case, this function is called in the default startup code,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe customizations.
+*
+* \param config
+* This is the pointer to the pipe configuration structure
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Init
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config)
+{
+ /* Create the interrupt structures and arrays needed */
+
+ cy_stc_sysint_t ipc_intr_cypipeConfig;
+
+ cy_stc_ipc_pipe_ep_config_t epConfigDataA;
+ cy_stc_ipc_pipe_ep_config_t epConfigDataB;
+
+ /* Parameters checking begin */
+ CY_ASSERT_L1(NULL != config);
+ #if (CY_CPU_CORTEX_M0P)
+ CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep0ConfigData.ipcNotifierPriority);
+ #else
+ CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep1ConfigData.ipcNotifierPriority);
+ #endif
+ CY_ASSERT_L1(NULL != config->endpointsCallbacksArray);
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep0ConfigData.epAddress);
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep1ConfigData.epAddress);
+ CY_ASSERT_L1(NULL != config->userPipeIsrHandler);
+ /* Parameters checking end */
+
+#if (CY_CPU_CORTEX_M0P)
+
+ /* Receiver endpoint = EP0, Sender endpoint = EP1 */
+ epConfigDataA = config->ep0ConfigData;
+ epConfigDataB = config->ep1ConfigData;
+
+ /* Configure CM0 interrupts */
+ ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)epConfigDataA.ipcNotifierMuxNumber;
+ ipc_intr_cypipeConfig.cm0pSrc = (cy_en_intr_t)((int32_t)cpuss_interrupts_ipc_0_IRQn + (int32_t)epConfigDataA.ipcNotifierNumber);
+ ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority;
+
+#else
+
+ /* Receiver endpoint = EP1, Sender endpoint = EP0 */
+ epConfigDataA = config->ep1ConfigData;
+ epConfigDataB = config->ep0ConfigData;
+
+ /* Configure interrupts */
+ ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc_0_IRQn + epConfigDataA.ipcNotifierNumber);
+ ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority;
+
+#endif
+
+ /* Initialize the pipe endpoints */
+ Cy_IPC_Pipe_EndpointInit(epConfigDataA.epAddress,
+ config->endpointsCallbacksArray,
+ config->endpointClientsCount,
+ epConfigDataA.epConfig,
+ &ipc_intr_cypipeConfig);
+
+ /* Create the endpoints for the CM4 just for reference */
+ Cy_IPC_Pipe_EndpointInit(epConfigDataB.epAddress, NULL, 0ul, epConfigDataB.epConfig, NULL);
+
+ (void)Cy_SysInt_Init(&ipc_intr_cypipeConfig, config->userPipeIsrHandler);
+
+ /* Enable the interrupts */
+ NVIC_EnableIRQ(ipc_intr_cypipeConfig.intrSrc);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointInit
+****************************************************************************//**
+*
+* This function initializes the endpoint of a pipe for the current CPU. The
+* current CPU is the CPU that is executing the code. An endpoint of a pipe
+* is for the IPC channel that receives a message for the current CPU.
+*
+* After this function is called, the callbackArray needs to be populated
+* with the callback functions for that endpoint using the
+* Cy_IPC_Pipe_RegisterCallback() function.
+*
+* \note In general case, this function is called within \ref Cy_IPC_Pipe_Init,
+* so user doesn't need to call it anywhere.
+* However, it may be useful in case of some pipe/endpoint customizations.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint you want to initialize.
+*
+* \param cbArray
+* This is a pointer to the callback function array. Based on the client ID, one
+* of the functions in this array is called to process the message.
+*
+* \param cbCnt
+* This is the size of the callback array, or the number of defined clients.
+*
+* \param epConfig
+* This value defines the IPC channel, IPC interrupt number, and the interrupt
+* mask for the entire pipe.
+* The format of the endpoint configuration
+* Bits[31:16] Interrupt Mask
+* Bits[15:8 ] IPC interrupt
+* Bits[ 7:0 ] IPC channel
+*
+* \param epInterrupt
+* This is a pointer to the endpoint interrupt description structure.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointInit
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray,
+ uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Extract the channel, interrupt and interrupt mask */
+ endpoint->ipcChan = _FLD2VAL(CY_IPC_PIPE_CFG_CHAN, epConfig);
+ endpoint->intrChan = _FLD2VAL(CY_IPC_PIPE_CFG_INTR, epConfig);
+ endpoint->pipeIntMask = _FLD2VAL(CY_IPC_PIPE_CFG_IMASK, epConfig);
+
+ /* Assign IPC channel to this endpoint */
+ endpoint->ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (endpoint->ipcChan);
+
+ /* Assign interrupt structure to endpoint and Initialize the interrupt mask for this endpoint */
+ endpoint->ipcIntrPtr = Cy_IPC_Drv_GetIntrBaseAddr(endpoint->intrChan);
+
+ /* Only allow notify and release interrupts from endpoints in this pipe. */
+ Cy_IPC_Drv_SetInterruptMask(endpoint->ipcIntrPtr, endpoint->pipeIntMask, endpoint->pipeIntMask);
+
+ /* Save the Client count and the callback array pointer */
+ endpoint->clientCount = cbCnt;
+ endpoint->callbackArray = cbArray;
+ endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY;
+
+ if (NULL != epInterrupt)
+ {
+ endpoint->pipeIntrSrc = epInterrupt->intrSrc;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_SendMessage
+****************************************************************************//**
+*
+* This function is used to send a message from one endpoint to another. It
+* generates an interrupt on the endpoint that receives the message and a
+* release interrupt to the sender to acknowledge the message has been processed.
+*
+* \param toAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* of the endpoint to which you are sending the message.
+*
+* \param fromAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* of the endpoint from which the message is being sent.
+*
+* \param msgPtr
+* Pointer to the message structure to be sent.
+*
+* \param callBackPtr
+* Pointer to the Release callback function.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Message was sent to the other end of the pipe
+* CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid
+* CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myReleaseCallback
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_SendMessage
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr,
+ void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
+{
+ cy_en_ipc_pipe_status_t returnStatus;
+ uint32_t releaseMask;
+ uint32_t notifyMask;
+
+ cy_stc_ipc_pipe_ep_t * fromEp;
+ cy_stc_ipc_pipe_ep_t * toEp;
+
+ CY_ASSERT_L1(NULL != msgPtr);
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > toAddr);
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > fromAddr);
+
+ toEp = &(cy_ipc_pipe_epArray[toAddr]);
+ fromEp = &cy_ipc_pipe_epArray[fromAddr];
+
+ /* Create the release mask for the "fromAddr" channel's interrupt channel */
+ releaseMask = (uint32_t)(1ul << (fromEp->intrChan));
+
+ /* Shift into position */
+ releaseMask = _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, releaseMask);
+
+ /* Create the notify mask for the "toAddr" channel's interrupt channel */
+ notifyMask = (uint32_t)(1ul << (toEp->intrChan));
+
+ /* Check if IPC channel valid */
+ if( toEp->ipcPtr != NULL)
+ {
+ if(fromEp->busy == CY_IPC_PIPE_ENDPOINT_NOTBUSY)
+ {
+ /* Attempt to acquire the channel */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(toEp->ipcPtr) )
+ {
+ /* Mask out the release mask area */
+ * (uint32_t *) msgPtr &= ~(CY_IPC_PIPE_MSG_RELEASE_Msk);
+
+ * (uint32_t *) msgPtr |= releaseMask;
+
+ /* If the channel was acquired, write the message. */
+ Cy_IPC_Drv_WriteDataValue(toEp->ipcPtr, (uint32_t) msgPtr);
+
+ /* Set the busy flag. The ISR clears this after the release */
+ fromEp->busy = CY_IPC_PIPE_ENDPOINT_BUSY;
+
+ /* Setup release callback function */
+ fromEp->releaseCallbackPtr = callBackPtr;
+
+ /* Cause notify event/interrupt */
+ Cy_IPC_Drv_AcquireNotify(toEp->ipcPtr, notifyMask);
+
+ returnStatus = CY_IPC_PIPE_SUCCESS;
+ }
+ else
+ {
+ /* Channel was already acquired, return Error */
+ returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY;
+ }
+ }
+ else
+ {
+ /* Channel may not be acquired, but the release interrupt has not executed yet */
+ returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY;
+ }
+ }
+ else
+ {
+ /* Null pipe handle. */
+ returnStatus = CY_IPC_PIPE_ERROR_BAD_HANDLE;
+ }
+ return (returnStatus);
+}
+
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_RegisterCallback
+****************************************************************************//**
+*
+* This function registers a callback that is called when a message is received
+* on a pipe.
+* The client_ID is the same as the index of the callback function array.
+* The callback may be a real function pointer or NULL if no callback is required.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to which you want to add callback functions.
+*
+* \param callBackPtr
+* Pointer to the callback function called when the endpoint has received a message.
+* If this parameters is NULL current callback will be unregistered.
+*
+* \param clientId
+* The index in the callback array (Client ID) where the function pointer is saved.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myAcquireCallback
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallback
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId)
+{
+ cy_en_ipc_pipe_status_t returnStatus;
+ cy_stc_ipc_pipe_ep_t * thisEp;
+
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
+
+ thisEp = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Check if clientId is between 0 and less than client count */
+ if (clientId < thisEp->clientCount)
+ {
+ /* Copy callback function into callback function pointer array */
+ thisEp->callbackArray[clientId] = callBackPtr;
+
+ returnStatus = CY_IPC_PIPE_SUCCESS;
+ }
+ else
+ {
+ returnStatus = CY_IPC_PIPE_ERROR_BAD_CLIENT;
+ }
+ return (returnStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_RegisterCallbackRel
+****************************************************************************//**
+*
+* This function registers a default callback if a release interrupt
+* is generated but the current release callback function is null.
+*
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to which you want to add a release callback function.
+*
+* \param callBackPtr
+* Pointer to the callback executed when the endpoint has received a message.
+* If this parameters is NULL current callback will be unregistered.
+*
+* \return
+* None
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myDefaultReleaseCallback
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallbackRel
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Copy callback function into callback function pointer array */
+ endpoint->defaultReleaseCallbackPtr = callBackPtr;
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_ExecCallback
+****************************************************************************//**
+*
+* This function is called by the ISR for a given pipe endpoint to dispatch
+* the appropriate callback function based on the client ID for that endpoint.
+*
+* \param endpoint
+* Pointer to endpoint structure.
+*
+* \return
+* None
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_ExecCallback
+*
+*******************************************************************************/
+void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint)
+{
+ uint32_t *msgPtr = NULL;
+ uint32_t clientID;
+ uint32_t shadowIntr;
+ uint32_t releaseMask = (uint32_t)0;
+
+ cy_ipc_pipe_callback_ptr_t callbackPtr;
+
+ /* Parameters checking begin */
+ CY_ASSERT_L1(NULL != endpoint);
+ CY_ASSERT_L1(NULL != endpoint->ipcPtr);
+ CY_ASSERT_L1(NULL != endpoint->ipcIntrPtr);
+ CY_ASSERT_L1(NULL != endpoint->callbackArray);
+ /* Parameters checking end */
+
+ shadowIntr = Cy_IPC_Drv_GetInterruptStatusMasked(endpoint->ipcIntrPtr);
+
+ /* Check to make sure the interrupt was a notify interrupt */
+ if (0ul != Cy_IPC_Drv_ExtractAcquireMask(shadowIntr))
+ {
+ /* Clear the notify interrupt. */
+ Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, CY_IPC_NO_NOTIFICATION, Cy_IPC_Drv_ExtractAcquireMask(shadowIntr));
+
+ if ( Cy_IPC_Drv_IsLockAcquired (endpoint->ipcPtr) )
+ {
+ /* Extract Client ID */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_ReadMsgPtr (endpoint->ipcPtr, (void **)&msgPtr))
+ {
+ /* Get release mask */
+ releaseMask = _FLD2VAL(CY_IPC_PIPE_MSG_RELEASE, *msgPtr);
+ clientID = _FLD2VAL(CY_IPC_PIPE_MSG_CLIENT, *msgPtr);
+
+ /* Make sure client ID is within valid range */
+ if (endpoint->clientCount > clientID)
+ {
+ callbackPtr = endpoint->callbackArray[clientID]; /* Get the callback function */
+
+ if (callbackPtr != NULL)
+ {
+ callbackPtr(msgPtr); /* Call the function pointer for "clientID" */
+ }
+ }
+ }
+
+ /* Must always release the IPC channel */
+ (void)Cy_IPC_Drv_LockRelease (endpoint->ipcPtr, releaseMask);
+ }
+ }
+
+ /* Check to make sure the interrupt was a release interrupt */
+ if (0ul != Cy_IPC_Drv_ExtractReleaseMask(shadowIntr)) /* Check for a Release interrupt */
+ {
+ /* Clear the release interrupt */
+ Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, Cy_IPC_Drv_ExtractReleaseMask(shadowIntr), CY_IPC_NO_NOTIFICATION);
+
+ if (endpoint->releaseCallbackPtr != NULL)
+ {
+ endpoint->releaseCallbackPtr();
+
+ /* Clear the pointer after it was called */
+ endpoint->releaseCallbackPtr = NULL;
+ }
+ else
+ {
+ if (endpoint->defaultReleaseCallbackPtr != NULL)
+ {
+ endpoint->defaultReleaseCallbackPtr();
+ }
+ }
+
+ /* Clear the busy flag when release is detected */
+ endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY;
+ }
+
+ (void)Cy_IPC_Drv_GetInterruptStatus(endpoint->ipcIntrPtr);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointPause
+****************************************************************************//**
+*
+* This function sets the receiver endpoint to paused state.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to pause.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Disable the interrupts */
+ NVIC_DisableIRQ(endpoint->pipeIntrSrc);
+
+ return (CY_IPC_PIPE_SUCCESS);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Pipe_EndpointResume
+****************************************************************************//**
+*
+* This function sets the receiver endpoint to active state.
+*
+* \param epAddr
+* This parameter is the address (or index in the array of endpoint structures)
+* that designates the endpoint to resume.
+*
+* \return
+* CY_IPC_PIPE_SUCCESS: Callback registered successfully
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume
+*
+*******************************************************************************/
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr)
+{
+ cy_stc_ipc_pipe_ep_t * endpoint;
+
+ CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr);
+
+ endpoint = &cy_ipc_pipe_epArray[epAddr];
+
+ /* Enable the interrupts */
+ NVIC_EnableIRQ(endpoint->pipeIntrSrc);
+
+ return (CY_IPC_PIPE_SUCCESS);
+}
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,265 @@
+/***************************************************************************//**
+* \file cy_ipc_pipe.h
+* \version 1.10.1
+*
+* Description:
+* IPC Pipe Driver - This header file contains all the function prototypes,
+* structure definitions, pipe constants, and pipe endpoint address definitions.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef CY_IPC_PIPE_H
+#define CY_IPC_PIPE_H
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "ipc/cy_ipc_drv.h"
+#include "syslib/cy_syslib.h"
+#include "sysint/cy_sysint.h"
+
+/**
+* \addtogroup group_ipc_pipe IPC pipes layer (IPC_PIPE)
+* \{
+* The Pipe functions provide a method to transfer one or more words of data
+* between CPUs or tasks. The data can be defined as a single 32-bit unsigned
+* word, an array of data, or a user-defined structure. The only limitation is
+* that the first word in the array or structure must be a 32-bit unsigned word
+* in which a client ID number is passed. The client ID dictates the callback
+* function that will be called by the receiver of the message. After the
+* callback function returns by the receiver, it will invoke a release callback
+* function defined by the sender of the message.
+*
+* A User Pipe is provided for the user to transfer data between CPUs and
+* tasks.
+*
+* \defgroup group_ipc_pipe_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_pipe_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_pipe_data_structures Data Structures
+* Data structures are used in the driver
+*
+* \defgroup group_ipc_pipe_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+*/
+
+/*
+ * This section defines the system level constants required to define
+ * callback arrays for the Cypress pipe and the user pipe. These defines
+ * are used for both the max callback count and maximum clients.
+*/
+
+/** Typedef for pipe callback function pointer */
+typedef void (* cy_ipc_pipe_callback_ptr_t)(uint32_t * msgPtr);
+
+/** Typedef for a pipe release callback function pointer */
+typedef void (* cy_ipc_pipe_relcallback_ptr_t)(void);
+
+/** Typedef for array of callback function pointers */
+typedef cy_ipc_pipe_callback_ptr_t *cy_ipc_pipe_callback_array_ptr_t;
+
+
+/**
+* \addtogroup group_ipc_pipe_macros
+* \{
+*/
+
+/*
+ * The System pipe address is what is used to send a message to one of the
+ * endpoints of a pipe. Currently the Cypress pipe and the User pipe
+ * are supported. For parts with extra IPC channels users may create
+ * their own custom pipes and create their own pipe addresses.
+ *
+ * The format of the endpoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+#define CY_IPC_PIPE_CFG_IMASK_Pos (16UL) /**< Interrupts shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_IMASK_Msk (0xFFFF0000UL) /**< Interrupts mask for endpoint address */
+#define CY_IPC_PIPE_CFG_INTR_Pos (8UL) /**< IPC Interrupt shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_INTR_Msk (0x0000FF00UL) /**< IPC Interrupt mask for endpoint address */
+#define CY_IPC_PIPE_CFG_CHAN_Pos (0UL) /**< IPC Channel shift value for endpoint address */
+#define CY_IPC_PIPE_CFG_CHAN_Msk (0x000000FFUL) /**< IPC Channel mask for endpoint address */
+
+
+
+#define CY_IPC_PIPE_MSG_CLIENT_Msk (0x000000FFul) /**< Client mask for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_CLIENT_Pos (0ul) /**< Client shift for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_USR_Msk (0x0000FF00ul) /**< User data mask for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_USR_Pos (8ul) /**< User data shift for first word of Pipe message */
+#define CY_IPC_PIPE_MSG_RELEASE_Msk (0xFFFF0000ul) /**< Mask for message release mask */
+#define CY_IPC_PIPE_MSG_RELEASE_Pos (16UL) /**< Shift require to line up mask to LSb */
+
+/** Use to set the busy flag when waiting for a release interrupt */
+#define CY_IPC_PIPE_ENDPOINT_BUSY (1UL)
+/** Denotes that a release interrupt is not pending */
+#define CY_IPC_PIPE_ENDPOINT_NOTBUSY (0UL)
+
+/** \} group_ipc_pipe_macros */
+
+/**
+* \addtogroup group_ipc_pipe_data_structures
+* \{
+*/
+
+/**
+* This is the definition of a pipe endpoint. There is one endpoint structure
+* for each CPU in a pipe. It contains all the information to process a message
+* send to other CPUs in the pipe.
+*/
+typedef struct
+{
+ uint32_t ipcChan; /**< IPC channel number used for this endpoint to receive messages */
+ uint32_t intrChan; /**< IPC interrupt channel number used for this endpoint to receive interrupts */
+ uint32_t pipeIntMask; /**< Release/Notify interrupt mask that includes all endpoints on pipe */
+ IRQn_Type pipeIntrSrc; /**< Interrupt vector number that includes all endpoints on pipe */
+
+ IPC_STRUCT_Type *ipcPtr; /**< Pointer to receive IPC channel ( If ipcPtr == NULL, cannot receive ) */
+ IPC_INTR_STRUCT_Type *ipcIntrPtr; /**< Pointer to IPC interrupt, needed to clear the interrupt */
+ uint32_t busy; /**< Endpoint busy flag. If sent no messages can be sent from this endpoint */
+ uint32_t clientCount; /**< Client count and size of MsgCallback array */
+
+ cy_ipc_pipe_callback_array_ptr_t callbackArray; /**< Pointer to array of callback functions, one for each Client */
+ cy_ipc_pipe_relcallback_ptr_t releaseCallbackPtr; /**< Pointer to release callback function */
+ cy_ipc_pipe_relcallback_ptr_t defaultReleaseCallbackPtr; /**< Pointer to default release callback function */
+} cy_stc_ipc_pipe_ep_t;
+
+/** The Pipe endpoint configuration structure. */
+typedef struct
+{
+ uint32_t ipcNotifierNumber; /**< Notifier */
+ uint32_t ipcNotifierPriority; /**< Notifier Priority */
+ uint32_t ipcNotifierMuxNumber; /**< CM0+ interrupt multiplexer number */
+
+ uint32_t epAddress; /**< Index in the array of endpoint structure */
+ uint32_t epConfig; /**< Configuration mask, contains IPC channel, IPC interrupt number,
+ and the interrupt mask */
+} cy_stc_ipc_pipe_ep_config_t;
+
+/** The Pipe channel configuration structure. */
+typedef struct
+{
+ /** Specifies the notify interrupt number for the first endpoint */
+ cy_stc_ipc_pipe_ep_config_t ep0ConfigData;
+
+ /** Specifies the notify interrupt number for the second endpoint */
+ cy_stc_ipc_pipe_ep_config_t ep1ConfigData;
+
+ /** Client count and size of MsgCallback array */
+ uint32_t endpointClientsCount;
+
+ /** Pipes callback function array. */
+ cy_ipc_pipe_callback_array_ptr_t endpointsCallbacksArray;
+
+ /** User IRQ handler function that is called when IPC receive data to process (interrupt was raised). */
+ cy_israddress userPipeIsrHandler;
+} cy_stc_ipc_pipe_config_t;
+
+/** \} goup_ipc_pipe_data_structures */
+
+/**
+* \addtogroup group_ipc_pipe_macros
+* \{
+*/
+/* Status and error types */
+#define CY_IPC_PIPE_RTN (0x0200ul) /**< Software PDL driver ID for IPC pipe functions */
+#define CY_IPC_PIPE_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function status codes */
+#define CY_IPC_PIPE_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function warning return values */
+#define CY_IPC_PIPE_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function error return values */
+
+/** \} group_ipc_pipe_macros */
+
+/**
+* \addtogroup group_ipc_pipe_enums
+* \{
+*/
+
+/** Return constants for IPC pipe functions. */
+typedef enum
+{
+ CY_IPC_PIPE_SUCCESS =(uint32_t)(0x00u), /**< Pipe API return for no error */
+ CY_IPC_PIPE_ERROR_NO_IPC =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 1ul), /**< Pipe API return for no valid IPC channel */
+ CY_IPC_PIPE_ERROR_NO_INTR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 2ul), /**< Pipe API return for no valid interrupt */
+ CY_IPC_PIPE_ERROR_BAD_PRIORITY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 3ul), /**< Pipe API return for bad priority parameter */
+ CY_IPC_PIPE_ERROR_BAD_HANDLE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 4ul), /**< Pipe API return for bad pipe handle */
+ CY_IPC_PIPE_ERROR_BAD_ID =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 5ul), /**< Pipe API return for bad pipe ID */
+ CY_IPC_PIPE_ERROR_DIR_ERROR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 6ul), /**< Pipe API return for invalid direction (Not used at this time) */
+ CY_IPC_PIPE_ERROR_SEND_BUSY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 7ul), /**< Pipe API return for pipe is currently busy */
+ CY_IPC_PIPE_ERROR_NO_MESSAGE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 8ul), /**< Pipe API return for no message indicated */
+ CY_IPC_PIPE_ERROR_BAD_CPU =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 9ul), /**< Pipe API return for invalid CPU value */
+ CY_IPC_PIPE_ERROR_BAD_CLIENT =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 10ul) /**< Pipe API return for client out of range */
+} cy_en_ipc_pipe_status_t;
+
+/** \} group_ipc_pipe_enums */
+
+/**
+* \addtogroup group_ipc_pipe_data_structures
+* \{
+*/
+
+/** \cond
+* NOTE: This doxygen comment must be placed before some code entity, or else
+* it will belong to a random entity that follows it, e.g. group_ipc_functions
+*
+* Client identifier for a message.
+* For a given pipe, traffic across the pipe can be multiplexed with multiple
+* senders on one end and multiple receivers on the other end.
+*
+* The first 32-bit word of the message is used to identify the client that owns
+* the message.
+*
+* The upper 16 bits are the client ID.
+*
+* The lower 16 bits are for use by the client in any way desired.
+*
+* The lower 16 bits are preserved (not modified) and not interpreted in any way.
+* \endcond
+*/
+
+/** \} group_ipc_pipe_data_structures */
+
+/******************************************************************************/
+/* Global function prototypes (definition in C source) */
+/******************************************************************************/
+
+/**
+* \addtogroup group_ipc_pipe_functions
+* \{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray,
+ uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, void *msgPtr,
+ cy_ipc_pipe_relcallback_ptr_t callBackPtr);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr,
+ cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId);
+void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint);
+void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr);
+void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray);
+void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config);
+
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr);
+cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** \} group_ipc_pipe_functions */
+
+#endif /* CY_IPC_PIPE_H */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,392 @@
+/***************************************************************************//**
+* \file cy_ipc_sema.c
+* \version 1.10.1
+*
+* Description:
+* IPC Semaphore Driver - This source file contains the source code for the
+* semaphore level APIs for the IPC interface.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "ipc/cy_ipc_drv.h"
+#include "ipc/cy_ipc_sema.h"
+#include "syslib/cy_syslib.h"
+#include <string.h> /* The memset() definition */
+
+/* Defines a mask to Check if semaphore count is a multiple of 32 */
+#define CY_IPC_SEMA_PER_WORD_MASK (CY_IPC_SEMA_PER_WORD - 1ul)
+
+/* Pointer to IPC structure used for semaphores */
+static IPC_STRUCT_Type* cy_semaIpcStruct;
+
+/*
+* Internal IPC semaphore control data structure.
+*/
+typedef struct
+{
+ uint32_t maxSema; /* Maximum semaphores in system */
+ uint32_t *arrayPtr; /* Pointer to semaphores array */
+} cy_stc_ipc_sema_t;
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Init
+****************************************************************************//**
+*
+* This function initializes the semaphores subsystem. The user must create an
+* array of unsigned 32-bit words to hold the semaphore bits. The number
+* of semaphores will be the size of the array * 32. The total semaphores count
+* will always be a multiple of 32.
+*
+* \note In a multi-CPU system this init function should be called with all
+* initialized parameters on one CPU only to provide a pointer to SRAM that can
+* be shared between all the CPUs in the system that will use semaphores.
+* On other CPUs user must specify the IPC semaphores channel and pass 0 / NULL
+* to count and memPtr parameters correspondingly.
+*
+* \param ipcChannel
+* The IPC channel number used for semaphores
+*
+* \param count
+* The maximum number of semaphores to be supported (multiple of 32).
+*
+* \param memPtr
+* This points to the array of (count/32) words that contain the semaphore data.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized
+* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero,
+* or count not multiple of 32
+* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Init
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel,
+ uint32_t count, uint32_t memPtr[])
+{
+ /* Structure containing semaphores control data */
+ static cy_stc_ipc_sema_t cy_semaData;
+
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM;
+
+ if (ipcChannel >= CY_IPC_CHANNELS)
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ else
+ {
+ if( (NULL == memPtr) && (0u == count))
+ {
+ cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel);
+
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+
+ /* Check for non Null pointers and count value */
+ else if ((NULL != memPtr) && (0u != count))
+ {
+ /* Check if semaphore count is a multiple of 32 */
+ if( 0ul == (count & CY_IPC_SEMA_PER_WORD_MASK))
+ {
+ cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel);
+
+ cy_semaData.maxSema = count;
+ cy_semaData.arrayPtr = memPtr;
+
+ /* Initialize all semaphores to released */
+ (void)memset(cy_semaData.arrayPtr, 0, (count /8u));
+
+ /* Make sure semaphores start out released. */
+ /* Ignore the return value since it is OK if it was already released. */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+
+ /* Set the IPC Data with the pointer to the array. */
+ if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_SendMsgPtr (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION, &cy_semaData))
+ {
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION))
+ {
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ /* IPC channel not released, still semaphored */
+ retStatus = CY_IPC_SEMA_ERROR_LOCKED;
+ }
+ }
+ else
+ {
+ /* Could not acquire semaphore channel */
+ retStatus = CY_IPC_SEMA_ERROR_LOCKED;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_BAD_PARAM;
+ }
+ }
+
+ return(retStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Set
+****************************************************************************//**
+*
+* This function tries to acquire a semaphore. If the
+* semaphore is not available, this function returns immediately with
+* CY_IPC_SEMA_LOCKED.
+*
+* It first acquires the IPC channel that is used for all the semaphores, sets
+* the semaphore if it is cleared, then releases the IPC channel used for the
+* semaphore.
+*
+* \param semaNumber
+* The semaphore number to acquire.
+*
+* \param preemptable
+* When this parameter is enabled the function can be preempted by another
+* task or other forms of context switching in an RTOS environment.
+*
+* \note
+* If <b>preemptable</b> is enabled (true), the user must ensure that there are
+* no deadlocks in the system, which can be caused by an interrupt that occurs
+* after the IPC channel is locked. Unless the user is ready to handle IPC
+* channel locks correctly at the application level, set <b>premptable</b> to
+* false.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully
+* \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked
+* by another process
+* \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Set
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable)
+{
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ uint32_t interruptState = 0ul;
+
+ cy_stc_ipc_sema_t *semaStruct;
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if (!preemptable)
+ {
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ }
+
+ /* Check to make sure the IPC channel is released
+ If so, check if specific channel can be locked. */
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct))
+ {
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) == 0ul)
+ {
+ semaStruct->arrayPtr[semaIndex] |= semaMask;
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_NOT_ACQUIRED;
+ }
+
+ /* Release, but do not trigger a release event */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+ }
+
+ if (!preemptable)
+ {
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Clear
+****************************************************************************//**
+*
+* This functions tries to releases a semaphore.
+*
+* It first acquires the IPC channel that is used for all the semaphores, clears
+* the semaphore if it is set, then releases the IPC channel used for the
+* semaphores.
+*
+* \param semaNumber
+* The index of the semaphore to release.
+*
+* \param preemptable
+* When this parameter is enabled the function can be preempted by another
+* task or other forms of context switching in an RTOS environment.
+*
+* \note
+* If <b>preemptable</b> is enabled (true), the user must ensure that there are
+* no deadlocks in the system, which can be caused by an interrupt that occurs
+* after the IPC channel is locked. Unless the user is ready to handle IPC
+* channel locks correctly at the application level, set <b>premptable</b> to
+* false.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully
+* \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared
+* \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Clear
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable)
+{
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ uint32_t interruptState = 0ul;
+
+ cy_stc_ipc_sema_t *semaStruct;
+ cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if (!preemptable)
+ {
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ }
+
+ /* Check to make sure the IPC channel is released
+ If so, check if specific channel can be locked. */
+ if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct))
+ {
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul)
+ {
+ semaStruct->arrayPtr[semaIndex] &= ~semaMask;
+ retStatus = CY_IPC_SEMA_SUCCESS;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_NOT_ACQUIRED;
+ }
+
+ /* Release, but do not trigger a release event */
+ (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION);
+ }
+
+ if (!preemptable)
+ {
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+ return(retStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_Status
+****************************************************************************//**
+*
+* This function returns the status of the semaphore.
+*
+* \param semaNumber
+* The index of the semaphore to return status.
+*
+* \return Status of the operation
+* \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state.
+* \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state.
+* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Status
+*
+*******************************************************************************/
+cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber)
+{
+ cy_en_ipcsema_status_t retStatus;
+ uint32_t semaIndex;
+ uint32_t semaMask;
+ cy_stc_ipc_sema_t *semaStruct;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ if (semaNumber < semaStruct->maxSema)
+ {
+ /* Get the index into the semaphore array and calculate the mask */
+ semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD;
+ semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) ));
+
+ if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul)
+ {
+ retStatus = CY_IPC_SEMA_STATUS_LOCKED;
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_STATUS_UNLOCKED;
+ }
+ }
+ else
+ {
+ retStatus = CY_IPC_SEMA_OUT_OF_RANGE;
+ }
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_IPC_Sema_GetMaxSems
+****************************************************************************//**
+*
+* This function returns the number of semaphores in the semaphores subsystem.
+*
+* \return
+* Returns the semaphores quantity.
+*
+* \funcusage
+* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_GetMaxSems
+*
+*******************************************************************************/
+uint32_t Cy_IPC_Sema_GetMaxSems(void)
+{
+ cy_stc_ipc_sema_t *semaStruct;
+
+ /* Get pointer to structure */
+ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct);
+
+ return (semaStruct->maxSema);
+}
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,114 @@
+/***************************************************************************//**
+* \file cy_ipc_sema.h
+* \version 1.10.1
+*
+* \brief
+* Header file for IPC SEM functions
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef CY_IPC_SEMA_H
+#define CY_IPC_SEMA_H
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+#include "cy_ipc_drv.h"
+#include <stdbool.h>
+
+/**
+* \addtogroup group_ipc_sema IPC semaphores layer (IPC_SEMA)
+* \{
+* The semaphores layer functions made use of a single IPC channel to allow
+* multiple semaphores that can be used by system or user function calls.
+* By default there are 128 semaphores provided, although the user may modify
+* the default value to any number, limited only by SRAM.
+*
+* \defgroup group_ipc_sema_macros Macros
+* Macro definitions are used in the driver
+*
+* \defgroup group_ipc_sema_functions Functions
+* Functions are used in the driver
+*
+* \defgroup group_ipc_sema_enums Enumerated Types
+* Enumerations are used in the driver
+* \}
+*
+* \addtogroup group_ipc_sema_macros
+* \{
+*/
+
+/** Software PDL driver ID for IPC semaphore functions */
+#define CY_IPC_SEMA_RTN (0x0100ul)
+/** Return prefix for IPC semaphore function status codes */
+#define CY_IPC_SEMA_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_SEMA_RTN)
+/** Return prefix for IPC semaphore function warning return values */
+#define CY_IPC_SEMA_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_SEMA_RTN)
+/** Return prefix for IPC semaphore function error return values */
+#define CY_IPC_SEMA_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_SEMA_RTN)
+
+#define CY_IPC_SEMA_PER_WORD (uint32_t)32u /**< 32 semaphores per word */
+
+/** \} group_ipc_sema_macros */
+
+/**
+* \addtogroup group_ipc_sema_enums
+* \{
+*/
+
+/** Return constants for IPC semaphores functions. */
+typedef enum
+{
+ /** No error has occurred */
+ CY_IPC_SEMA_SUCCESS = (uint32_t)(0ul),
+ /** Semaphores IPC channel has already been locked */
+ CY_IPC_SEMA_ERROR_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 1ul),
+ /** Semaphores IPC channel is unlocked */
+ CY_IPC_SEMA_ERROR_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 2ul),
+ /** Semaphore API bad parameter */
+ CY_IPC_SEMA_BAD_PARAM = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 3ul),
+ /** Semaphore API return when semaphore number is out of the range */
+ CY_IPC_SEMA_OUT_OF_RANGE = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 4ul),
+
+ /** Semaphore API return when IPC channel was not acquired */
+ CY_IPC_SEMA_NOT_ACQUIRED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 2ul),
+ /** Semaphore API return status when semaphore channel is busy or locked
+* by another process */
+ CY_IPC_SEMA_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 3ul),
+ /** Semaphore status return that the semaphore is set */
+ CY_IPC_SEMA_STATUS_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 1ul),
+ /** Semaphore status return that the semaphore is cleared */
+ CY_IPC_SEMA_STATUS_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 0ul)
+} cy_en_ipcsema_status_t;
+
+/** \} group_ipc_sema_enums */
+
+/**
+* \addtogroup group_ipc_sema_functions
+* \{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+cy_en_ipcsema_status_t Cy_IPC_Sema_Init (uint32_t ipcChannel, uint32_t count, uint32_t memPtr[]);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Set (uint32_t semaNumber, bool preemptable);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Clear (uint32_t semaNumber, bool preemptable);
+cy_en_ipcsema_status_t Cy_IPC_Sema_Status (uint32_t semaNumber);
+uint32_t Cy_IPC_Sema_GetMaxSems(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** \} group_ipc_sema_functions */
+
+#endif /* CY_IPC_SEMA_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,627 @@
+/*******************************************************************************
+* \file cy_lpcomp.c
+* \version 1.10.1
+*
+* \brief
+* This file provides the driver code to the API for the Low Power Comparator
+* component.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "cy_lpcomp.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+static cy_stc_lpcomp_context_t cy_lpcomp_context;
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_Init
+****************************************************************************//**
+*
+* Initializes LPCOMP and returns the LPCOMP register address.
+*
+* \param *base
+* LPCOMP registers structure pointer.
+*
+* \param *config
+* The pointer to the configuration structure for PDL.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \return cy_en_lpcomp_status_t
+* *base checking result. If the pointer is NULL, returns error.
+*
+*******************************************************************************/
+cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t* config)
+{
+ cy_en_lpcomp_status_t ret = CY_LPCOMP_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode));
+ CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis));
+ CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(config->power));
+ CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(config->intType));
+
+ if ((base != NULL) && (config != NULL))
+ {
+ Cy_LPComp_GlobalEnable(base);
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_CTRL = _VAL2FLD(LPCOMP_CMP0_CTRL_HYST0, (uint32_t)config->hysteresis) |
+ _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_BYPASS0, (uint32_t)config->outputMode) |
+ _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_LEVEL0, (uint32_t)config->outputMode >> 1u);
+ }
+ else
+ {
+ base->CMP1_CTRL = _VAL2FLD(LPCOMP_CMP1_CTRL_HYST1, (uint32_t)config->hysteresis) |
+ _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_BYPASS1, (uint32_t)config->outputMode) |
+ _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u);
+ }
+
+ /* Save intType to use it in the Cy_LPComp_Enable() function */
+ cy_lpcomp_context.intType[(uint8_t)channel - 1u] = config->intType;
+
+ /* Save power to use it in the Cy_LPComp_Enable() function */
+ cy_lpcomp_context.power[(uint8_t)channel - 1u] = config->power;
+
+ ret = CY_LPCOMP_SUCCESS;
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_Enable
+****************************************************************************//**
+*
+* Enables the LPCOMP and sets the LPCOMP interrupt mode.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
+{
+ cy_en_lpcomp_pwr_t powerSpeed;
+
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+
+ powerSpeed = cy_lpcomp_context.power[(uint8_t)channel - 1u];
+
+ /* Set power */
+ Cy_LPComp_SetPower(base, channel, powerSpeed);
+
+ /* Make delay before enabling the comparator interrupt to prevent false triggering */
+ if (CY_LPCOMP_MODE_ULP == powerSpeed)
+ {
+ Cy_SysLib_DelayUs(CY_LPCOMP_ULP_POWER_DELAY);
+ }
+ else if (CY_LPCOMP_MODE_LP == powerSpeed)
+ {
+ Cy_SysLib_DelayUs(CY_LPCOMP_LP_POWER_DELAY);
+ }
+ else
+ {
+ Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY);
+ }
+
+ /* Enable the comparator interrupt */
+ Cy_LPComp_SetInterruptTriggerMode(base, channel, cy_lpcomp_context.intType[(uint8_t)channel - 1u]);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_Disable
+****************************************************************************//**
+*
+* Disables the LPCOMP power and sets the interrupt mode to disabled.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+
+ /* Disable the comparator interrupt */
+ Cy_LPComp_SetInterruptTriggerMode(base, channel, CY_LPCOMP_INTR_DISABLE);
+
+ /* Set power off */
+ Cy_LPComp_SetPower(base, channel, CY_LPCOMP_MODE_OFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetInterruptTriggerMode
+****************************************************************************//**
+*
+* Sets the interrupt edge-detect mode.
+* This also controls the value provided on the output.
+* \note Interrupts can be enabled after the block is enabled and the appropriate
+* start-up time has elapsed:
+* 3 us for the normal power mode;
+* 6 us for the LP mode;
+* 50 us for the ULP mode.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \param intType
+* Interrupt edge trigger selection
+* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected
+* CY_LPCOMP_INTR_RISING (=1) - Rising edge
+* CY_LPCOMP_INTR_FALLING (=2) - Falling edge
+* CY_LPCOMP_INTR_BOTH (=3) - Both rising and falling edges.
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(intType));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_INTTYPE0, (uint32_t)intType);
+ }
+ else
+ {
+ base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_INTTYPE1, (uint32_t)intType);
+ }
+
+ /* Save interrupt type to use it in the Cy_LPComp_Enable() function */
+ cy_lpcomp_context.intType[(uint8_t)channel - 1u] = intType;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetPower
+****************************************************************************//**
+*
+* Sets the drive power and speeds to one of the four settings.
+* \note Interrupts can be enabled after the block is enabled and the appropriate
+* start-up time has elapsed:
+* 3 us for the normal power mode;
+* 6 us for the LP mode;
+* 50 us for the ULP mode.
+* Otherwise, unexpected interrupts events can occur.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \param power
+* The power setting sets an operation mode of the component:
+* CY_LPCOMP_OFF_POWER (=0) - Off power
+* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power
+* CY_LPCOMP_MODE_LP (=2) - Medium/low power
+* CY_LPCOMP_MODE_NORMAL(=3) - Fast/normal power
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(power));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_MODE0, (uint32_t)power);
+ }
+ else
+ {
+ base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_MODE1, (uint32_t)power);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetHysteresis
+****************************************************************************//**
+*
+* Adds the 30mV hysteresis to the comparator.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \param hysteresis
+* Sets an operation mode of the component
+* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST
+* CY_LPCOMP_HYST_DISABLE(=0) - Disable HYST.
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(hysteresis));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_HYST0, (uint32_t)hysteresis);
+ }
+ else
+ {
+ base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL , LPCOMP_CMP1_CTRL_HYST1, (uint32_t)hysteresis);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetInputs
+****************************************************************************//**
+*
+* Sets the comparator input sources. The comparator inputs can be connected
+* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative
+* comparator input can be connected to the local VREF.
+* At least one unconnected input causes a comparator undefined output.
+*
+* \note Connection to AMUXBUSA/AMUXBUSB requires closing the additional
+* switches which are a part of the IO system. These switches can be configured
+* using the HSIOM->AMUX_SPLIT_CTL[3] register.
+* Refer to the appropriate Technical Reference Manual (TRM) of a device
+* for a detailed description.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \param inputP
+* Positive input selection
+* CY_LPCOMP_SW_GPIO (0x01u)
+* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
+* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in the hibernate mode.
+*
+* \param inputN
+* Negative input selection
+* CY_LPCOMP_SW_GPIO (0x01u)
+* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
+* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode
+* CY_LPCOMP_SW_LOCAL_VREF (0x08u) - the negative input only for a crude REF.
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN)
+{
+ uint32_t input;
+
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_P_VALID(inputP));
+ CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_N_VALID(inputN));
+
+ switch(inputP)
+ {
+ case CY_LPCOMP_SW_AMUXBUSA:
+ {
+ input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AP0_Msk : LPCOMP_CMP1_SW_CMP1_AP1_Msk;
+ HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u);
+ break;
+ }
+ case CY_LPCOMP_SW_AMUXBUSB:
+ {
+ input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BP0_Msk : LPCOMP_CMP1_SW_CMP1_BP1_Msk;
+ HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u);
+ break;
+ }
+ default:
+ {
+ input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IP0_Msk : LPCOMP_CMP1_SW_CMP1_IP1_Msk;
+ break;
+ }
+ }
+
+ switch(inputN)
+ {
+ case CY_LPCOMP_SW_AMUXBUSA:
+ {
+ input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AN0_Msk : LPCOMP_CMP1_SW_CMP1_AN1_Msk;
+ HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u);
+ break;
+ }
+ case CY_LPCOMP_SW_AMUXBUSB:
+ {
+ input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BN0_Msk : LPCOMP_CMP1_SW_CMP1_BN1_Msk;
+ HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u);
+ break;
+ }
+ case CY_LPCOMP_SW_LOCAL_VREF:
+ {
+ input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_VN0_Msk : LPCOMP_CMP1_SW_CMP1_VN1_Msk;
+ break;
+ }
+ default:
+ {
+ input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IN0_Msk : LPCOMP_CMP1_SW_CMP1_IN1_Msk;
+ break;
+ }
+ }
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_POS_Msk | CY_LPCOMP_CMP0_SW_NEG_Msk;
+ base->CMP0_SW = input;
+ }
+ else
+ {
+ base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_POS_Msk | CY_LPCOMP_CMP1_SW_NEG_Msk;
+ base->CMP1_SW = input;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetOutputMode
+****************************************************************************//**
+*
+* Sets the type of the comparator DSI output.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \param outType
+* Interrupt edge trigger selection
+* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass
+* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator
+* CY_LPCOMP_OUT_SYNC (=2) - DSI output with the level option, it is similar to the
+* bypass mode but it is 1 cycle slow than the bypass.
+* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10]
+* 0 : 0 = 0x00 -> Pulse (PULSE)
+* 1 : 0 = 0x02 -> Level (SYNC)
+* x : 1 = 0x01 -> Bypass (Direct).
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+ CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(outType));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, CY_LPCOMP_CMP0_OUTPUT_CONFIG, (uint32_t)outType);
+ }
+ else
+ {
+ base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, CY_LPCOMP_CMP1_OUTPUT_CONFIG, (uint32_t)outType);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_DeepSleepCallback
+****************************************************************************//**
+*
+* This function checks the current power mode of LPComp and then disables the
+* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode.
+* It stores the state of the LPComp enable and then disables the LPComp block
+* before going to the low power modes, and recovers the LPComp power state after
+* wake-up using the stored value.
+*
+* \param *callbackParams
+* The \ref cy_stc_syspm_callback_params_t structure with the callback
+* parameters which consists of mode, base and context fields:
+* *base - LPComp register structure pointer;
+* *context - Context for the call-back function;
+* mode
+* CY_SYSPM_CHECK_READY - No action for this state.
+* CY_SYSPM_CHECK_FAIL - No action for this state.
+* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power
+* mode, and then disables or enables the LPComp block
+* according to the condition.
+* Stores the LPComp state to recover the state after
+* wake up.
+* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled
+* before the sleep mode.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t ret = CY_SYSPM_FAIL;
+ LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base);
+ static uint32_t enabled_status;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* Save the LPComp the enabled/disabled status. */
+ enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG);
+
+ if (0u != enabled_status)
+ {
+ /* Disable the LPComp block when there is no wake-up source from any channel. */
+ if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
+ _FLD2BOOL(LPCOMP_INTR_MASK_COMP0_MASK, locBase->INTR_MASK)) ||
+ ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
+ _FLD2BOOL(LPCOMP_INTR_MASK_COMP1_MASK, locBase->INTR_MASK))) )
+
+ {
+ /* Disable the LPComp block to avoid leakage. */
+ Cy_LPComp_GlobalDisable(locBase);
+ }
+ else
+ {
+ /* Set LPComp the status to the not changed state. */
+ enabled_status = 0u;
+ }
+ }
+ else
+ {
+ /* The LPComp block was already disabled and
+ * the system is allowed to go to the low power mode.
+ */
+ }
+
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* Enable LPComp to operate if it was enabled
+ * before entering to the low power mode.
+ */
+ if (0u != enabled_status)
+ {
+ Cy_LPComp_GlobalEnable(locBase);
+ }
+ else
+ {
+ /* The LPComp block was disabled before calling this API
+ * with mode = CY_SYSPM_CHECK_READY.
+ */
+ }
+
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_HibernateCallback
+****************************************************************************//**
+*
+* This function checks the current power mode of LPComp and then disable the
+* LPComp block, if there is no wake-up source from LPComp in the hibernate mode.
+*
+* \param *callbackParams
+* The \ref cy_stc_syspm_callback_params_t structure with the callback
+* parameters which consists of mode, base and context fields:
+* *base - LPComp register structure pointer;
+* *context - Context for the call-back function;
+* mode
+* CY_SYSPM_CHECK_READY - No action for this state.
+* CY_SYSPM_CHECK_FAIL - No action for this state.
+* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode
+* of the LPComp block, and then disables or enables
+* the LPComp block according to the condition.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t ret = CY_SYSPM_FAIL;
+ LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base);
+ static uint32_t enabled_status;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* Save the LPComp the enabled/disabled status. */
+ enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG);
+
+ if (0u != enabled_status)
+ {
+ /* Disable the LPComp block when there is no wake-up source from any channel. */
+ if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
+ _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN0, SRSS->PWR_HIBERNATE)) ||
+ ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
+ _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN1, SRSS->PWR_HIBERNATE))) )
+
+ {
+ /* Disable the LPComp block to avoid leakage. */
+ Cy_LPComp_GlobalDisable(locBase);
+ }
+ else
+ {
+ /* Set LPComp the status to the not changed state. */
+ enabled_status = 0u;
+ }
+ }
+ else
+ {
+ /* The LPComp block was already disabled and
+ * the system is allowed to go to the low power mode.
+ */
+ }
+
+ ret = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (ret);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,717 @@
+/***************************************************************************//**
+* \file cy_lpcomp.h
+* \version 1.10.1
+*
+* This file provides constants and parameter values for the Low Power Comparator driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_lpcomp Low Power Comparator (LPComp)
+* \{
+* Provides access to the low-power comparators implemented using the fixed-function
+* LP comparator block that is present in PSoC 6.
+*
+* These comparators can perform fast analog signal comparison of internal
+* and external analog signals in all system power modes. Low-power comparator
+* output can be inspected by the CPU, used as an interrupt/wakeup source to the
+* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as
+* a wakeup source to system resources when in Hibernate mode, or fed to DSI as
+* an asynchronous or synchronous signal (level or pulse).
+*
+* \section group_lpcomp_section_Configuration_Considerations Configuration Considerations
+* To set up an LPComp, the inputs, the output, the mode, the interrupts and
+* other configuration parameters should be configured. Power the LPComp to operate.
+*
+* The sequence recommended for the LPComp operation:
+*
+* 1) To initialize the driver, call the Cy_LPComp_Init() function providing
+* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number,
+* and the LPCOMP registers structure pointer.
+*
+* 2) Optionally, configure the interrupt requests if the interrupt event
+* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with
+* the parameter for the mask available in the configuration file.
+* Additionally, enable the Global interrupts and initialize the referenced
+* interrupt by setting the priority and the interrupt vector using
+* the \ref Cy_SysInt_Init() function of the sysint driver.
+*
+* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init()
+* functions of the GPIO driver.
+* The High Impedance Analog drive mode is for the inputs and
+* the Strong drive mode is for the output.
+* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs
+* to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref:
+* \image html lpcomp_inputs.png
+*
+* 4) Power on the comparator using the Cy_LPComp_Enable() function.
+*
+* 5) The comparator output can be monitored using
+* the Cy_LPComp_GetCompare() function or using the LPComp interrupt
+* (if the interrupt is enabled).
+*
+* \note The interrupt is not cleared automatically.
+* It is the user's responsibility to do that.
+* The interrupt is cleared by writing a 1 in the corresponding interrupt
+* register bit position. The preferred way to clear interrupt sources
+* is using the Cy_LPComp_ClearInterrupt() function.
+*
+* \note Individual comparator interrupt outputs are ORed together
+* as a single asynchronous interrupt source before it is sent out and
+* used to wake up the system in the low-power mode.
+* For PSoC 6 devices, the individual comparator interrupt is masked
+* by the INTR_MASK register. The masked result is captured in
+* the INTR_MASKED register.
+* Writing a 1 to the INTR register bit will clear the interrupt.
+*
+* \section group_lpcomp_lp Low Power Support
+* The LPComp provides the callback functions to facilitate
+* the low-power mode transition. The callback
+* \ref Cy_LPComp_DeepSleepCallback must be called during execution
+* of \ref Cy_SysPm_DeepSleep; \ref Cy_LPComp_HibernateCallback must be
+* called during execution of \ref Cy_SysPm_Hibernate.
+* To trigger the callback execution, the callback must be registered
+* before calling the mode transition function.
+* Refer to \ref group_syspm driver for more
+* information about low-power mode transitions.
+*
+* \section group_lpcomp_more_information More Information
+*
+* Refer to the appropriate device technical reference manual (TRM) for
+* a detailed description of the registers.
+*
+* \section group_lpcomp_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>
+* The pointer to the buffer memory is void to allow handling different
+* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
+* The cast operation is safe because the configuration is verified
+* before operation is performed.
+* The function \ref Cy_LPComp_DeepSleepCallback is a callback of
+* the \ref cy_en_syspm_status_t type. The cast operation safety in this
+* function becomes the user's responsibility because the pointers are
+* initialized when a callback is registered in the SysPm driver.</td>
+* </tr>
+* </table>
+*
+* \section group_lpcomp_Changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Added Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback()
+* and Cy_LPComp_HibernateCallback() functions<br>
+* Added input parameter validation to the API functions.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_lpcomp_macros Macros
+* \defgroup group_lpcomp_functions Functions
+* \{
+* \defgroup group_lpcomp_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_lpcomp_data_structures Data Structures
+* \defgroup group_lpcomp_enums Enumerated Types
+*/
+
+#ifndef CY_LPCOMP_PDL_H
+#define CY_LPCOMP_PDL_H
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXLPCOMP
+ #error "The LPCOMP driver is not supported on this device"
+#endif
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+* \addtogroup group_lpcomp_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_LPCOMP_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_LPCOMP_DRV_VERSION_MINOR 10
+
+/******************************************************************************
+* API Constants
+******************************************************************************/
+
+/**< LPCOMP PDL ID */
+#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u)
+
+/** The LPCOMP's number of channels. */
+#define CY_LPCOMP_MAX_CHANNEL_NUM (2u)
+
+/** LPCOMP's comparator 1 interrupt mask. */
+#define CY_LPCOMP_COMP0 (0x01u)
+/** LPCOMP's comparator 2 interrupt mask. */
+#define CY_LPCOMP_COMP1 (0x02u)
+
+/** \cond INTERNAL_MACROS */
+
+
+/******************************************************************************
+* Registers Constants
+******************************************************************************/
+
+#define CY_LPCOMP_MODE_ULP_Pos (0x0uL)
+#define CY_LPCOMP_MODE_ULP_Msk (0x1uL)
+
+#define CY_LPCOMP_INTR_Pos (LPCOMP_INTR_COMP0_Pos)
+#define CY_LPCOMP_INTR_Msk (LPCOMP_INTR_COMP0_Msk | LPCOMP_INTR_COMP1_Msk)
+
+#define CY_LPCOMP_CMP0_SW_POS_Msk (LPCOMP_CMP0_SW_CMP0_IP0_Msk | \
+ LPCOMP_CMP0_SW_CMP0_AP0_Msk | \
+ LPCOMP_CMP0_SW_CMP0_BP0_Msk)
+#define CY_LPCOMP_CMP0_SW_NEG_Msk (LPCOMP_CMP0_SW_CMP0_IN0_Msk | \
+ LPCOMP_CMP0_SW_CMP0_AN0_Msk | \
+ LPCOMP_CMP0_SW_CMP0_BN0_Msk | \
+ LPCOMP_CMP0_SW_CMP0_VN0_Msk)
+#define CY_LPCOMP_CMP1_SW_POS_Msk (LPCOMP_CMP1_SW_CMP1_IP1_Msk | \
+ LPCOMP_CMP1_SW_CMP1_AP1_Msk | \
+ LPCOMP_CMP1_SW_CMP1_BP1_Msk)
+#define CY_LPCOMP_CMP1_SW_NEG_Msk (LPCOMP_CMP1_SW_CMP1_IN1_Msk | \
+ LPCOMP_CMP1_SW_CMP1_AN1_Msk | \
+ LPCOMP_CMP1_SW_CMP1_BN1_Msk | \
+ LPCOMP_CMP1_SW_CMP1_VN1_Msk)
+
+#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Pos LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos
+#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Pos LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos
+
+#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Msk (LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk | \
+ LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk)
+
+#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Msk (LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk | \
+ LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk)
+
+#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos
+
+#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | \
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk)
+
+#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos
+
+#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | \
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk)
+
+#define CY_LPCOMP_REF_CONNECTED (1u)
+
+#define CY_LPCOMP_WAKEUP_PIN0_Msk CY_SYSPM_WAKEUP_LPCOMP0
+#define CY_LPCOMP_WAKEUP_PIN1_Msk CY_SYSPM_WAKEUP_LPCOMP1
+
+/* Internal constants for Cy_LPComp_Enable() */
+#define CY_LPCOMP_NORMAL_POWER_DELAY (3u)
+#define CY_LPCOMP_LP_POWER_DELAY (6u)
+#define CY_LPCOMP_ULP_POWER_DELAY (50u)
+
+/** \endcond */
+/** \} group_lpcomp_macros */
+
+/**
+* \addtogroup group_lpcomp_enums
+* \{
+*/
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+/** The LPCOMP output modes. */
+typedef enum
+{
+ CY_LPCOMP_OUT_PULSE = 0u, /**< The LPCOMP DSI output with the pulse option, no bypass. */
+ CY_LPCOMP_OUT_DIRECT = 1u, /**< The LPCOMP bypass mode, the direct output of a comparator. */
+ CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar
+ to the bypass mode but it is 1 cycle slow than the bypass. */
+} cy_en_lpcomp_out_t;
+
+/** The LPCOMP hysteresis modes. */
+typedef enum
+{
+ CY_LPCOMP_HYST_ENABLE = 1u, /**< The LPCOMP enable hysteresis. */
+ CY_LPCOMP_HYST_DISABLE = 0u /**< The LPCOMP disable hysteresis. */
+} cy_en_lpcomp_hyst_t;
+
+/** The LPCOMP's channel number. */
+typedef enum
+{
+ CY_LPCOMP_CHANNEL_0 = 0x1u, /**< The LPCOMP Comparator 0. */
+ CY_LPCOMP_CHANNEL_1 = 0x2u /**< The LPCOMP Comparator 1. */
+} cy_en_lpcomp_channel_t;
+
+/** The LPCOMP interrupt modes. */
+typedef enum
+{
+ CY_LPCOMP_INTR_DISABLE = 0u, /**< The LPCOMP interrupt disabled, no interrupt will be detected. */
+ CY_LPCOMP_INTR_RISING = 1u, /**< The LPCOMP interrupt on the rising edge. */
+ CY_LPCOMP_INTR_FALLING = 2u, /**< The LPCOMP interrupt on the falling edge. */
+ CY_LPCOMP_INTR_BOTH = 3u /**< The LPCOMP interrupt on both rising and falling edges. */
+} cy_en_lpcomp_int_t;
+
+/** The LPCOMP power-mode selection. */
+typedef enum
+{
+ CY_LPCOMP_MODE_OFF = 0u, /**< The LPCOMP's channel power-off. */
+ CY_LPCOMP_MODE_ULP = 1u, /**< The LPCOMP's channel ULP mode. */
+ CY_LPCOMP_MODE_LP = 2u, /**< The LPCOMP's channel LP mode. */
+ CY_LPCOMP_MODE_NORMAL = 3u /**< The LPCOMP's channel normal mode. */
+} cy_en_lpcomp_pwr_t;
+
+/** The LPCOMP inputs. */
+typedef enum
+{
+ CY_LPCOMP_SW_GPIO = 0x01u, /**< The LPCOMP input connects to GPIO pin. */
+ CY_LPCOMP_SW_AMUXBUSA = 0x02u, /**< The LPCOMP input connects to AMUXBUSA. */
+ CY_LPCOMP_SW_AMUXBUSB = 0x04u, /**< The LPCOMP input connects to AMUXBUSB. */
+ CY_LPCOMP_SW_LOCAL_VREF = 0x08u /**< The LPCOMP input connects to local VREF. */
+} cy_en_lpcomp_inputs_t;
+
+/** The LPCOMP error codes. */
+typedef enum
+{
+ CY_LPCOMP_SUCCESS = 0x00u, /**< Successful */
+ CY_LPCOMP_BAD_PARAM = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
+ CY_LPCOMP_TIMEOUT = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Operation timed out */
+ CY_LPCOMP_INVALID_STATE = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< Operation not setup or is in an improper state */
+ CY_LPCOMP_UNKNOWN = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0xFFu, /**< Unknown failure */
+} cy_en_lpcomp_status_t;
+
+/** \} group_lpcomp_enums */
+
+/**
+* \addtogroup group_lpcomp_data_structures
+* \{
+*/
+
+/******************************************************************************
+ * Structures
+ *****************************************************************************/
+
+/** The LPCOMP configuration structure. */
+typedef struct {
+ cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output,
+ Synchronized output or Pulse output */
+ cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */
+ cy_en_lpcomp_pwr_t power; /**< Sets the LPCOMP power mode */
+ cy_en_lpcomp_int_t intType; /**< Sets the LPCOMP interrupt mode */
+} cy_stc_lpcomp_config_t;
+
+/** \cond CONTEXT_STRUCTURE */
+
+typedef struct {
+ cy_en_lpcomp_int_t intType[CY_LPCOMP_MAX_CHANNEL_NUM];
+ cy_en_lpcomp_pwr_t power[CY_LPCOMP_MAX_CHANNEL_NUM];
+} cy_stc_lpcomp_context_t;
+
+/** \endcond */
+
+/** \} group_lpcomp_data_structures */
+
+/** \cond INTERNAL_MACROS */
+
+/******************************************************************************
+ * Macros
+ *****************************************************************************/
+#define CY_LPCOMP_IS_CHANNEL_VALID(channel) (((channel) == CY_LPCOMP_CHANNEL_0) || \
+ ((channel) == CY_LPCOMP_CHANNEL_1))
+#define CY_LPCOMP_IS_OUT_MODE_VALID(mode) (((mode) == CY_LPCOMP_OUT_PULSE) || \
+ ((mode) == CY_LPCOMP_OUT_DIRECT) || \
+ ((mode) == CY_LPCOMP_OUT_SYNC))
+#define CY_LPCOMP_IS_HYSTERESIS_VALID(hyst) (((hyst) == CY_LPCOMP_HYST_ENABLE) || \
+ ((hyst) == CY_LPCOMP_HYST_DISABLE))
+#define CY_LPCOMP_IS_INTR_MODE_VALID(intr) (((intr) == CY_LPCOMP_INTR_DISABLE) || \
+ ((intr) == CY_LPCOMP_INTR_RISING) || \
+ ((intr) == CY_LPCOMP_INTR_FALLING) || \
+ ((intr) == CY_LPCOMP_INTR_BOTH))
+#define CY_LPCOMP_IS_POWER_VALID(power) (((power) == CY_LPCOMP_MODE_OFF) || \
+ ((power) == CY_LPCOMP_MODE_ULP) || \
+ ((power) == CY_LPCOMP_MODE_LP) || \
+ ((power) == CY_LPCOMP_MODE_NORMAL))
+#define CY_LPCOMP_IS_INTR_VALID(intr) (((intr) == CY_LPCOMP_COMP0) || \
+ ((intr) == CY_LPCOMP_COMP1) || \
+ ((intr) == (CY_LPCOMP_COMP0 | CY_LPCOMP_COMP1)))
+#define CY_LPCOMP_IS_INPUT_P_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \
+ ((input) == CY_LPCOMP_SW_AMUXBUSA) || \
+ ((input) == CY_LPCOMP_SW_AMUXBUSB))
+#define CY_LPCOMP_IS_INPUT_N_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \
+ ((input) == CY_LPCOMP_SW_AMUXBUSA) || \
+ ((input) == CY_LPCOMP_SW_AMUXBUSB) || \
+ ((input) == CY_LPCOMP_SW_LOCAL_VREF))
+
+/** \endcond */
+
+/**
+* \addtogroup group_lpcomp_functions
+* \{
+*/
+
+/******************************************************************************
+* Functions
+*******************************************************************************/
+
+cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t *config);
+void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel);
+void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel);
+__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type *base);
+__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base);
+__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base);
+__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base);
+__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel);
+void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power);
+void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis);
+void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN);
+void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType);
+void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType);
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base);
+__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt);
+__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base);
+__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base);
+__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel);
+/** \addtogroup group_lpcomp_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep and Hibernate transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} */
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GlobalEnable
+****************************************************************************//**
+*
+* Activates the IP of the LPCOMP hardware block. This API should be enabled
+* before operating any channel of comparators.
+* Note: Interrupts can be enabled after the block is enabled and the appropriate
+* start-up time has elapsed:
+* 3 us for the normal power mode;
+* 6 us for the LP mode;
+* 50 us for the ULP mode.
+*
+* \param *base
+* The structure of the channel pointer.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type* base)
+{
+ base->CONFIG |= LPCOMP_CONFIG_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GlobalDisable
+****************************************************************************//**
+*
+* Deactivates the IP of the LPCOMP hardware block.
+* (Analog in power down, open all switches, all clocks off).
+*
+* \param *base
+* The structure of the channel pointer.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base)
+{
+ base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_UlpReferenceEnable
+****************************************************************************//**
+*
+* Enables the local reference-generator circuit.
+*
+* \param *base
+* The structure of the channel pointer.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base)
+{
+ base->CONFIG |= LPCOMP_CONFIG_LPREF_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_UlpReferenceDisable
+****************************************************************************//**
+*
+* Disables the local reference-generator circuit.
+*
+* \param *base
+* The structure of the channel pointer.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base)
+{
+ base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_LPREF_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GetCompare
+****************************************************************************//**
+*
+* This function returns a nonzero value when the voltage connected to the
+* positive input is greater than the negative input voltage.
+*
+* \param *base
+* The LPComp register structure pointer.
+*
+* \param channel
+* The LPComp channel index.
+*
+* \return LPComp compare result.
+* The value is a nonzero value when the voltage connected to the positive
+* input is greater than the negative input voltage.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel)
+{
+ uint32_t result;
+
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ result = _FLD2VAL(LPCOMP_STATUS_OUT0, base->STATUS);
+ }
+ else
+ {
+ result = _FLD2VAL(LPCOMP_STATUS_OUT1, base->STATUS);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetInterruptMask
+****************************************************************************//**
+*
+* Configures which bits of the interrupt request register will trigger an
+* interrupt event.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param interrupt
+* uint32_t interruptMask: Bit Mask of interrupts to set.
+* Bit 0: COMP0 Interrupt Mask
+* Bit 1: COMP1 Interrupt Mask
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt));
+
+ base->INTR_MASK |= interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GetInterruptMask
+****************************************************************************//**
+*
+* Returns an interrupt mask.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \return bit mapping information
+* Bit 0: COMP0 Interrupt Mask
+* Bit 1: COMP1 Interrupt Mask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base)
+{
+ return (base->INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns an interrupt request register masked by an interrupt mask.
+* Returns the result of the bitwise AND operation between the corresponding
+* interrupt request and mask bits.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \return bit mapping information
+* Bit 0: COMP0 Interrupt Masked
+* Bit 1: COMP1 Interrupt Masked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base)
+{
+ return (base->INTR_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns the status of 2 different LPCOMP interrupt requests.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \return bit mapping information
+* Bit 0: COMP0 Interrupt status
+* Bit 1: COMP1 Interrupt status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base)
+{
+ return (_FLD2VAL(CY_LPCOMP_INTR, base->INTR));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_ClearInterrupt
+****************************************************************************//**
+*
+* Clears LPCOMP interrupts by setting each bit.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param interrupt
+* Bit 0: COMP0 Interrupt status
+* Bit 1: COMP1 Interrupt status
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt));
+ base->INTR |= interrupt;
+ (void) LPCOMP->INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_SetInterrupt
+****************************************************************************//**
+*
+* Sets a software interrupt request.
+* This function is used in the case of combined interrupt signal from the global
+* signal reference. This function from either component instance can be used
+* to trigger either or both software interrupts. It sets the INTR_SET interrupt mask.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param interrupt
+* Bit 0: COMP0 Interrupt status
+* Bit 1: COMP1 Interrupt status
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt));
+ base->INTR_SET = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LPComp_ConnectULPReference
+****************************************************************************//**
+*
+* Connects the local reference generator output to the comparator negative input.
+*
+* \param *base
+* The LPCOMP register structure pointer.
+*
+* \param channel
+* The LPCOMP channel index.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel)
+{
+ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
+
+ if (CY_LPCOMP_CHANNEL_0 == channel)
+ {
+ base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_NEG_Msk;
+ base->CMP0_SW = _CLR_SET_FLD32U(base->CMP0_SW, LPCOMP_CMP0_SW_CMP0_VN0, CY_LPCOMP_REF_CONNECTED);
+ }
+ else
+ {
+ base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_NEG_Msk;
+ base->CMP1_SW = _CLR_SET_FLD32U(base->CMP1_SW, LPCOMP_CMP1_SW_CMP1_VN1, CY_LPCOMP_REF_CONNECTED);
+ }
+}
+
+/** \} group_lpcomp_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_LPCOMP_PDL_H */
+
+/** \} group_lpcomp */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,62 @@
+/***************************************************************************//**
+* \file cy_lvd.c
+* \version 1.0.1
+*
+* The source code file for the LVD driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_lvd.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_DeepSleepCallback
+****************************************************************************//**
+*
+* When this function is registered by \ref Cy_SysPm_RegisterCallback - it
+* automatically enables the LVD after wake up from Deep-Sleep mode.
+*
+* \param callbackParams The pointer to the callback parameters structure,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \return the SysPm callback status \ref cy_en_syspm_status_t.
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams)
+{
+ cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ case CY_SYSPM_CHECK_FAIL:
+ case CY_SYSPM_BEFORE_TRANSITION:
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ Cy_LVD_Enable();
+ break;
+
+ default:
+ ret = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return(ret);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,433 @@
+/***************************************************************************//**
+* \file cy_lvd.h
+* \version 1.0.1
+*
+* The header file of the LVD driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \addtogroup group_lvd
+* \{
+* The LVD driver provides an API to manage the Low Voltage Detection block.
+* The LVD block provides a status of currently observed VDDD voltage
+* and triggers an interrupt when the observed voltage crosses an adjusted
+* threshold.
+*
+* \section group_lvd_configuration_considerations Configuration Considerations
+* To set up an LVD, configure the voltage threshold by the
+* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD
+* interrupt are disabled (by the \ref Cy_LVD_Disable and
+* \ref Cy_LVD_ClearInterruptMask functions correspondingly) before changing the
+* threshold to prevent propagating a false interrupt.
+* Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do
+* not forget to initialise an interrupt handler (the interrupt source number
+* is srss_interrupt_IRQn).
+* Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 20us
+* to get the circuit stabilized and clear the possible false interrupts by the
+* \ref Cy_LVD_ClearInterrupt, and finally the LVD interrupt can be enabled by
+* the \ref Cy_LVD_SetInterruptMask function.
+*
+* For example:
+* \snippet lvd_1_0_sut_00.cydsn/main_cm4.c Cy_LVD_Snippet
+*
+* Note that the LVD circuit is available only in Active, LPACTIVE, Sleep, and
+* LPSLEEP power modes. If an LVD is required in Deep-Sleep mode, then the device
+* should be configured to periodically wake up from deep sleep using a
+* Deep-Sleep wakeup source. This makes sure a LVD check is performed during
+* Active/LPACTIVE mode.
+*
+* \section group_lvd_more_information More Information
+* See the LVD chapter of the device technical reference manual (TRM).
+*
+* \section group_lvd_MISRA MISRA-C Compliance
+* The LVD driver has the following specific deviations:
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite expression of 'essentially unsigned' type (%1s) is being
+* cast to a different type category, '%2s'.</td>
+* <td>The value got from the bitfield physically can't exceed the enumeration
+* that describes this bitfield. So the code is safety by design.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>The object addressed by the pointer parameter '%s' is not modified and
+* so the pointer could be of type 'pointer to const'.</td>
+* <td>The pointer parameter is not used or modified, as there is no need
+* to do any actions with it. However, such parameter is
+* required to be presented in the function, because the
+* \ref Cy_LVD_DeepSleepCallback is a callback
+* of \ref cy_en_syspm_status_t type.
+* The SysPM driver callback function type requires implementing the
+* function with the next parameters and return value: <br>
+* cy_en_syspm_status_t (*Cy_SysPmCallback)
+* (cy_stc_syspm_callback_params_t *callbackParams);</td>
+* </tr>
+* </table>
+*
+* \section group_lvd_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason of Change</th></tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Added Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial Version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_lvd_macros Macros
+* \defgroup group_lvd_functions Functions
+* \{
+* \defgroup group_lvd_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_lvd_enums Enumerated Types
+*/
+
+
+#if !defined CY_LVD_H
+#define CY_LVD_H
+
+#include "syspm/cy_syspm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \addtogroup group_lvd_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_LVD_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_LVD_DRV_VERSION_MINOR 0
+
+/** The LVD driver identifier */
+#define CY_LVD_ID (CY_PDL_DRV_ID(0x39U))
+
+/** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(),
+ \ref Cy_LVD_GetInterruptMask() and
+ \ref Cy_LVD_GetInterruptStatusMasked() */
+#define CY_LVD_INTR (SRSS_SRSS_INTR_HVLVD1_Msk)
+
+/** \} group_lvd_macros */
+
+
+/** \addtogroup group_lvd_enums
+* \{
+*/
+
+
+/**
+ * LVD reference voltage select.
+ */
+typedef enum
+{
+ CY_LVD_THRESHOLD_1_2_V = 0x0U, /**<Select LVD reference voltage: 1.2V */
+ CY_LVD_THRESHOLD_1_4_V = 0x1U, /**<Select LVD reference voltage: 1.4V */
+ CY_LVD_THRESHOLD_1_6_V = 0x2U, /**<Select LVD reference voltage: 1.6V */
+ CY_LVD_THRESHOLD_1_8_V = 0x3U, /**<Select LVD reference voltage: 1.8V */
+ CY_LVD_THRESHOLD_2_0_V = 0x4U, /**<Select LVD reference voltage: 2.0V */
+ CY_LVD_THRESHOLD_2_1_V = 0x5U, /**<Select LVD reference voltage: 2.1V */
+ CY_LVD_THRESHOLD_2_2_V = 0x6U, /**<Select LVD reference voltage: 2.2V */
+ CY_LVD_THRESHOLD_2_3_V = 0x7U, /**<Select LVD reference voltage: 2.3V */
+ CY_LVD_THRESHOLD_2_4_V = 0x8U, /**<Select LVD reference voltage: 2.4V */
+ CY_LVD_THRESHOLD_2_5_V = 0x9U, /**<Select LVD reference voltage: 2.5V */
+ CY_LVD_THRESHOLD_2_6_V = 0xAU, /**<Select LVD reference voltage: 2.6V */
+ CY_LVD_THRESHOLD_2_7_V = 0xBU, /**<Select LVD reference voltage: 2.7V */
+ CY_LVD_THRESHOLD_2_8_V = 0xCU, /**<Select LVD reference voltage: 2.8V */
+ CY_LVD_THRESHOLD_2_9_V = 0xDU, /**<Select LVD reference voltage: 2.9V */
+ CY_LVD_THRESHOLD_3_0_V = 0xEU, /**<Select LVD reference voltage: 3.0V */
+ CY_LVD_THRESHOLD_3_1_V = 0xFU /**<Select LVD reference voltage: 3.1V */
+} cy_en_lvd_tripsel_t;
+
+/**
+ * LVD interrupt configuration select.
+ */
+typedef enum
+{
+ CY_LVD_INTR_DISABLE = 0x0U, /**<Select LVD interrupt: disabled */
+ CY_LVD_INTR_RISING = 0x1U, /**<Select LVD interrupt: rising edge */
+ CY_LVD_INTR_FALLING = 0x2U, /**<Select LVD interrupt: falling edge */
+ CY_LVD_INTR_BOTH = 0x3U, /**<Select LVD interrupt: both edges */
+} cy_en_lvd_intr_config_t;
+
+/**
+ * LVD output status.
+ */
+typedef enum
+{
+ CY_LVD_STATUS_BELOW = 0x0U, /**<The voltage is below the threshold */
+ CY_LVD_STATUS_ABOVE = 0x1U, /**<The voltage is above the threshold */
+} cy_en_lvd_status_t;
+
+/** \} group_lvd_enums */
+
+/** \cond internal */
+/* Macros for conditions used by CY_ASSERT calls */
+#define CY_LVD_CHECK_TRIPSEL(threshold) (((threshold) == CY_LVD_THRESHOLD_1_2_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_1_4_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_1_6_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_1_8_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_0_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_1_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_2_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_3_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_4_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_5_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_6_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_7_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_8_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_2_9_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_3_0_V) || \
+ ((threshold) == CY_LVD_THRESHOLD_3_1_V))
+
+#define CY_LVD_CHECK_INTR_CFG(intrCfg) (((intrCfg) == CY_LVD_INTR_DISABLE) || \
+ ((intrCfg) == CY_LVD_INTR_RISING) || \
+ ((intrCfg) == CY_LVD_INTR_FALLING) || \
+ ((intrCfg) == CY_LVD_INTR_BOTH))
+/** \endcond */
+
+/**
+* \addtogroup group_lvd_functions
+* \{
+*/
+__STATIC_INLINE void Cy_LVD_Enable(void);
+__STATIC_INLINE void Cy_LVD_Disable(void);
+__STATIC_INLINE void Cy_LVD_SetThreshold(cy_en_lvd_tripsel_t threshold);
+__STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void);
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void);
+__STATIC_INLINE void Cy_LVD_ClearInterrupt(void);
+__STATIC_INLINE void Cy_LVD_SetInterrupt(void);
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void);
+__STATIC_INLINE void Cy_LVD_SetInterruptMask(void);
+__STATIC_INLINE void Cy_LVD_ClearInterruptMask(void);
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void);
+__STATIC_INLINE void Cy_LVD_SetInterruptConfig(cy_en_lvd_intr_config_t lvdInterruptConfig);
+/** \addtogroup group_lvd_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
+/** \} */
+
+/*******************************************************************************
+* Function Name: Cy_LVD_Enable
+****************************************************************************//**
+*
+* Enables the output of the LVD block when the VDDD voltage is
+* at or below the threshold.
+* See the Configuration Considerations section for details.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_Enable(void)
+{
+ SRSS->PWR_LVD_CTL |= SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_Disable
+****************************************************************************//**
+*
+* Disables the LVD block. A low voltage detection interrupt is disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_Disable(void)
+{
+ SRSS->PWR_LVD_CTL &= (uint32_t) ~SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_SetThreshold
+****************************************************************************//**
+*
+* Sets a threshold for monitoring the VDDD voltage.
+* To prevent propagating a false interrupt, before changing the threshold
+* ensure that the LVD block itself and LVD interrupt are disabled by the
+* \ref Cy_LVD_Disable and \ref Cy_LVD_ClearInterruptMask functions
+* correspondingly.
+*
+* \param threshold
+* Threshold selection for Low Voltage Detect circuit, \ref cy_en_lvd_tripsel_t.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_SetThreshold(cy_en_lvd_tripsel_t threshold)
+{
+ CY_ASSERT_L3(CY_LVD_CHECK_TRIPSEL(threshold));
+ SRSS->PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS->PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_GetStatus
+****************************************************************************//**
+*
+* Returns the status of LVD.
+* SRSS LVD Status Register (PWR_LVD_STATUS).
+*
+* \return LVD status, \ref cy_en_lvd_status_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void)
+{
+ return ((cy_en_lvd_status_t) _FLD2VAL(SRSS_PWR_LVD_STATUS_HVLVD1_OK, SRSS->PWR_LVD_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns the status of LVD interrupt.
+* SRSS Interrupt Register (SRSS_INTR).
+*
+* \return SRSS Interrupt status, \ref CY_LVD_INTR.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void)
+{
+ return (SRSS->SRSS_INTR & SRSS_SRSS_INTR_HVLVD1_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_ClearInterrupt
+****************************************************************************//**
+*
+* Clears LVD interrupt.
+* SRSS Interrupt Register (SRSS_INTR).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_ClearInterrupt(void)
+{
+ SRSS->SRSS_INTR = SRSS_SRSS_INTR_HVLVD1_Msk;
+ (void) SRSS->SRSS_INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_SetInterrupt
+****************************************************************************//**
+*
+* Triggers the device to generate interrupt for LVD.
+* SRSS Interrupt Set Register (SRSS_INTR_SET).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_SetInterrupt(void)
+{
+ SRSS->SRSS_INTR_SET = SRSS_SRSS_INTR_SET_HVLVD1_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the mask value of LVD interrupts.
+* SRSS Interrupt Mask Register (SRSS_INTR_MASK).
+*
+* \return SRSS Interrupt Mask value, \ref CY_LVD_INTR.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void)
+{
+ return (SRSS->SRSS_INTR_MASK & SRSS_SRSS_INTR_MASK_HVLVD1_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_SetInterruptMask
+****************************************************************************//**
+*
+* Enables LVD interrupts.
+* Sets the LVD interrupt mask in the SRSS_INTR_MASK register.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_SetInterruptMask(void)
+{
+ SRSS->SRSS_INTR_MASK |= SRSS_SRSS_INTR_MASK_HVLVD1_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_ClearInterruptMask
+****************************************************************************//**
+*
+* Disables LVD interrupts.
+* Clears the LVD interrupt mask in the SRSS_INTR_MASK register.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_ClearInterruptMask(void)
+{
+ SRSS->SRSS_INTR_MASK &= (uint32_t) ~SRSS_SRSS_INTR_MASK_HVLVD1_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the masked interrupt status which is a bitwise AND between the
+* interrupt status and interrupt mask registers.
+* SRSS Interrupt Masked Register (SRSS_INTR_MASKED).
+*
+* \return SRSS Interrupt Masked value, \ref CY_LVD_INTR.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void)
+{
+ return (SRSS->SRSS_INTR_MASKED & SRSS_SRSS_INTR_MASKED_HVLVD1_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_LVD_SetInterruptConfig
+****************************************************************************//**
+*
+* Sets a configuration for LVD interrupt.
+* SRSS Interrupt Configuration Register (SRSS_INTR_CFG).
+*
+* \param lvdInterruptConfig \ref cy_en_lvd_intr_config_t.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_LVD_SetInterruptConfig(cy_en_lvd_intr_config_t lvdInterruptConfig)
+{
+ CY_ASSERT_L3(CY_LVD_CHECK_INTR_CFG(lvdInterruptConfig));
+ SRSS->SRSS_INTR_CFG = _CLR_SET_FLD32U(SRSS->SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdInterruptConfig);
+}
+
+
+/** \} group_lvd_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_LVD_H */
+
+
+/** \} group_lvd */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,191 @@
+/***************************************************************************//**
+* \file cy_mcwdt.c
+* \version 1.10.1
+*
+* Description:
+* Provides a system API for the MCWDT driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_mcwdt.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Init
+****************************************************************************//**
+*
+* Initializes the MCWDT block.
+*
+* \param base
+* The base pointer to a structure that describes the registers.
+*
+* \param config
+* The pointer to a structure that contains component configuration data.
+*
+* \return cy_en_mcwdt_status_t
+* *base checking result. If the pointer is NULL, returns error.
+*
+* \note
+* This API should not be called when the counters are running. Prior to calling
+* this API the counter should be disabled.
+*
+*******************************************************************************/
+cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config)
+{
+ cy_en_mcwdt_status_t ret = CY_MCWDT_BAD_PARAM;
+
+ if ((base != NULL) && (config != NULL))
+ {
+ CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c0ClearOnMatch, config->c0Match));
+ CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c1ClearOnMatch, config->c1Match));
+ CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(config->c2ToggleBit));
+ CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c0Mode));
+ CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c1Mode));
+ CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c2Mode));
+
+ base->MCWDT_MATCH = _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, config->c1Match) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, config->c0Match);
+
+ base->MCWDT_CONFIG = _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, config->c2ToggleBit) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2, config->c2Mode) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, config->c0ClearOnMatch) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, config->c1ClearOnMatch) |
+ (config->c1c2Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk : 0UL) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) |
+ (config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) |
+ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode);
+
+ ret = CY_MCWDT_SUCCESS;
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_DeInit
+****************************************************************************//**
+*
+* De-initializes the MCWDT block, returns register values to their default state.
+*
+* \param base
+* The base pointer to a structure that describes the registers.
+*
+* \note
+* This API should not be called when the counters are running. Prior to calling
+* this API the counter should be disabled.
+*
+*******************************************************************************/
+void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base)
+{
+ Cy_MCWDT_Unlock(base);
+
+ base->MCWDT_CNTLOW = 0UL;
+ base->MCWDT_CNTHIGH = 0UL;
+ base->MCWDT_MATCH = 0UL;
+ base->MCWDT_CONFIG = 0UL;
+ base->MCWDT_CTL = 0UL;
+ base->MCWDT_INTR = 0UL;
+ base->MCWDT_INTR_SET = 0UL;
+ base->MCWDT_INTR_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetCountCascaded
+****************************************************************************//**
+*
+* Reports the current value of combined C1-C0 cascaded counters.
+*
+* \param base
+* The base pointer to a structure that describes the registers.
+*
+* \note
+* The user must enable both counters, and cascade C0 to C1,
+* before calling this function. C2 is not reported.
+* Instead, to get a 64-bit C2-C1-C0 cascaded value, the
+* user must call this function followed by
+* Cy_MCWDT_GetCount(base, CY_MCWDT_COUNTER2), and then combine the results.
+* \note This function does not return the correct result when it is called
+* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with
+* a delay less than two lf_clk cycles. The recommended waitUs parameter
+* value is 100 us.
+*
+*******************************************************************************/
+uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base)
+{
+ uint32_t countVal = base->MCWDT_CNTLOW;
+ uint32_t counter1 = countVal >> MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos;
+ uint32_t counter0 = countVal & MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
+ uint32_t match0 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH);
+ uint32_t match1 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH);
+
+ /*
+ * The counter counter0 goes to zero when it reaches the match0
+ * value (c0ClearOnMatch = 1) or reaches the maximum
+ * value (c0ClearOnMatch = 0). The counter counter1 increments on
+ * the next rising edge of the MCWDT clock after
+ * the Clear On Match event takes place.
+ * The software increments counter1 to eliminate the case
+ * when the both counter0 and counter1 counters have zeros.
+ */
+ if (0u == counter0)
+ {
+ counter1++;
+ }
+
+ /* Check if the counter0 is Free running */
+ if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG))
+ {
+ /* Save match0 value with the correction when counter0
+ * goes to zero when it reaches the match0 value.
+ */
+ countVal = match0 + 1u;
+
+ if (0u < counter1)
+ {
+ /* Set match to the maximum value */
+ match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
+ }
+
+ if (countVal < counter0)
+ {
+ /* Decrement counter1 when the counter0 is great than match0 value */
+ counter1--;
+ }
+ }
+
+ /* Add the correction to counter0 */
+ counter0 += counter1;
+
+ /* Set counter1 match value to 65535 when the counter1 is free running */
+ if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, base->MCWDT_CONFIG))
+ {
+ match1 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk >> MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos;
+ }
+
+ /* Check for overflow */
+ if (match1 < counter1)
+ {
+ counter1 = 0u;
+ }
+
+ /* Calculate the combined value for C1-C0 cascaded counters */
+ countVal = counter0 + (counter1 * match0);
+
+ return (countVal);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1084 @@
+/***************************************************************************//**
+* \file cy_mcwdt.h
+* \version 1.10.1
+*
+* Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_mcwdt Multi-Counter Watchdog (MCWDT)
+* \{
+* A MCWDT has two 16-bit counters and one 32-bit counter.
+* You can use this driver to create a free-running
+* timer or generate periodic interrupts. The driver also
+* includes support for the watchdog function to recover from CPU or
+* firmware failures.
+*
+* There are two primary use cases for MCWDT: generating periodic CPU interrupts;
+* and implementing a free-running timer. Both have many applications in
+* embedded systems:
+* * Measuring time between events
+* * Generating periodic events
+* * Synchronizing actions
+* * Real-time clocking
+* * Polling
+*
+* An additional use case is to implement a watchdog used for recovering from a CPU or
+* firmware failure.
+*
+* \section group_mcwdt_configuration Configuration Considerations
+*
+* Each MCWDT may be configured for a particular product.
+* One MCWDT block can be associated with only one CPU during runtime.
+* A single MCWDT is not intended to be used by multiple CPUs simultaneously.
+* Each block contains three sub-counters, each of which can be configured for
+* various system utility functions - free running counter, periodic interrupts,
+* watchdog reset, or three interrupts followed by a watchdog reset.
+* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
+* counter.
+* A simplified diagram of the MCWDT hardware is shown below:
+* \image html mcwdt.png
+* The frequency of the periodic interrupts can be configured using the Match
+* value with combining Clear on match option, which can be set individually
+* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
+* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
+* after 65535 counts and the match value defines the shift between interrupts
+* (see the figure below). The enabled Clear on match option
+* resets the counter when the interrupt occurs.
+* \image html mcwdt_counters.png
+* 32-bit sub-counter C2 does not have Clear on match option.
+* The interrupt of counter C2 occurs when the counts equal
+* 2<sup>Toggle bit</sup> value.
+* \image html mcwdt_subcounters.png
+* To set up an MCWDT, provide the configuration parameters in the
+* cy_stc_mcwdt_config_t structure. Then call
+* Cy_MCWDT_Init() to initialize the driver.
+* Call Cy_MCWDT_Enable() to enable all specified counters.
+*
+* You can also set the mode of operation for any counter. If you choose
+* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
+* parameter for the masks described in Macro Section. All counter interrupts
+* are OR'd together to from a single combined MCWDT interrupt.
+* Additionally, enable the Global interrupts and initialize the referenced
+* interrupt by setting the priority and the interrupt vector using
+* \ref Cy_SysInt_Init() of the sysint driver.
+*
+* The values of the MCWDT counters can be monitored using
+* Cy_MCWDT_GetCount().
+*
+* \note In addition to the MCWDTs, each device has a separate watchdog timer
+* (WDT) that can also be used to generate a watchdog reset or periodic
+* interrupts. For more information on the WDT, see the appropriate section
+* of the PDL.
+*
+* \section group_mcwdt_more_information More Information
+*
+* For more information on the MCWDT peripheral, refer to
+* the technical reference manual (TRM).
+*
+* \section group_mcwdt_MISRA MISRA-C Compliance]
+* The mcwdt driver does not have any specific deviations.
+*
+* \section group_mcwdt_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Added input parameter validation to the API functions.<br>
+* Added API function GetCountCascaded()</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_mcwdt_macros Macros
+* \defgroup group_mcwdt_functions Functions
+* \defgroup group_mcwdt_data_structures Data Structures
+* \defgroup group_mcwdt_enums Enumerated Types
+*/
+
+#ifndef CY_MCWDT_H
+#define CY_MCWDT_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+
+#ifndef CY_IP_MXS40SRSS_MCWDT
+ #error "The MCWDT driver is not supported on this device"
+#endif
+
+/**
+* \addtogroup group_mcwdt_data_structures
+* \{
+*/
+
+/** The MCWDT component configuration structure. */
+typedef struct
+{
+ uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
+ Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
+ c0ClearOnMatch = 1. */
+ uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
+ Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
+ c1ClearOnMatch = 1. */
+ uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
+ \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
+ uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
+ \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
+ uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
+ Range: 0 - 31. */
+ uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
+ and \ref CY_MCWDT_MODE_INT. */
+ bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */
+ bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */
+ bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. */
+ bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. */
+} cy_stc_mcwdt_config_t;
+
+/** \} group_mcwdt_data_structures */
+
+/**
+* \addtogroup group_mcwdt_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_MCWDT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_MCWDT_DRV_VERSION_MINOR 10
+
+/** \cond INTERNAL_MACROS */
+
+/***************************************
+* Registers Constants
+***************************************/
+
+#define CY_MCWDT_LOCK_CLR0 (1u)
+#define CY_MCWDT_LOCK_CLR1 (2u)
+#define CY_MCWDT_LOCK_SET01 (3u)
+
+#define CY_MCWDT_BYTE_SHIFT (8u)
+#define CY_MCWDT_C0C1_MODE_MASK (3u)
+#define CY_MCWDT_C2_MODE_MASK (1u)
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
+ MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
+
+#define CY_MCWDT_CTR0_Pos (0u)
+#define CY_MCWDT_CTR1_Pos (1u)
+#define CY_MCWDT_CTR2_Pos (2u)
+#define CY_MCWDT_CTR_Pos (0UL)
+
+#define CY_MCWDT_C2_MODE_MASK (1u)
+
+/** \endcond */
+
+#define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
+
+#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
+ that handle multiple counters, including Cy_MCWDT_Enable(),
+ Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
+
+/** \} group_mcwdt_macros */
+
+
+/**
+* \addtogroup group_mcwdt_enums
+* \{
+*/
+
+/** The mcwdt sub-counter identifiers. */
+typedef enum
+{
+ CY_MCWDT_COUNTER0, /**< Sub-counter#0 identifier. */
+ CY_MCWDT_COUNTER1, /**< Sub-counter#1 identifier. */
+ CY_MCWDT_COUNTER2 /**< Sub-counter#2 identifier. */
+} cy_en_mcwdtctr_t;
+
+/** The mcwdt modes. */
+typedef enum
+{
+ CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
+ CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
+ Set/GetMode functions. */
+} cy_en_mcwdtmode_t;
+
+/** The mcwdt cascading. */
+typedef enum
+{
+ CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
+ It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
+ It is used for Set/GetCascade functions. */
+ CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
+ and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
+ It is used for Set/GetCascade functions. */
+} cy_en_mcwdtcascade_t;
+
+/** The MCWDT error codes. */
+typedef enum
+{
+ CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
+ CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
+} cy_en_mcwdt_status_t;
+
+/** \} group_mcwdt_enums */
+
+
+/** \cond PARAM_CHECK_MACROS */
+
+/** Parameter check macros */
+#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
+
+#define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
+ (CY_MCWDT_COUNTER1 == (counter)) || \
+ (CY_MCWDT_COUNTER2 == (counter)))
+
+#define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
+ (CY_MCWDT_MODE_INT == (mode)) || \
+ (CY_MCWDT_MODE_RESET == (mode)) || \
+ (CY_MCWDT_MODE_INT_RESET == (mode)))
+
+#define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
+
+
+#define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
+ (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
+ (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
+ (CY_MCWDT_CASCADE_BOTH == (cascade)))
+
+#define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
+
+#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
+
+
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_mcwdt_functions
+* \{
+*/
+cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config);
+ void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode);
+__STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade);
+__STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
+__STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
+__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
+uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Enable
+****************************************************************************//**
+*
+* Enables all specified counters.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all counters to enable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the counter begins counting after two lf_clk cycles pass.
+* The recommended value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is
+* the user's responsibility to check whether the selected counters were enabled
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetEnabledStatus() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t enableCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for enable */
+ enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
+
+ base->MCWDT_CTL |= enableCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Disable
+****************************************************************************//**
+*
+* Disables all specified counters.
+*
+* \param base
+* The base pointer to a structure describing registers.
+*
+* \param counters
+* OR of all counters to disable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the counter stops counting after two lf_clk cycles pass.
+* The recommended value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is
+* the user's responsibility to check whether the selected counters were disabled
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetEnabledStatus() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t disableCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for disable */
+ disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
+
+ base->MCWDT_CTL &= ~disableCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetEnabledStatus
+****************************************************************************//**
+*
+* Reports the enabled status of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the MCWDT counter. The valid range is [0-2].
+*
+* \return
+* The status of the MCWDT counter: 0 = disabled, 1 = enabled.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t status = 0u;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ switch (counter)
+ {
+ case CY_MCWDT_COUNTER0:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0, base->MCWDT_CTL);
+ break;
+ case CY_MCWDT_COUNTER1:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1, base->MCWDT_CTL);
+ break;
+ case CY_MCWDT_COUNTER2:
+ status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2, base->MCWDT_CTL);
+ break;
+
+ default:
+ CY_ASSERT(0u != 0u);
+ break;
+ }
+
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Lock
+****************************************************************************//**
+*
+* Locks out configuration changes to all MCWDT registers.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ base->MCWDT_LOCK = _CLR_SET_FLD32U(base->MCWDT_LOCK, MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_SET01);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_Unlock
+****************************************************************************//**
+*
+* Unlocks the MCWDT configuration registers.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ base->MCWDT_LOCK = _CLR_SET_FLD32U(base->MCWDT_LOCK, MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
+ base->MCWDT_LOCK = _CLR_SET_FLD32U(base->MCWDT_LOCK, MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetLockStatus
+****************************************************************************//**
+*
+* Reports the locked/unlocked state of the MCWDT.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The state of the MCWDT counter: 0 = unlocked, 1 = locked.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
+{
+ return ((0UL != (base->MCWDT_LOCK & MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk)) ? 1UL : 0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetMode
+****************************************************************************//**
+*
+* Sets the mode of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \param mode
+* The mode of operation for the counter. See enum typedef cy_en_mcwdtmode_t.
+*
+* \note
+* The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
+*
+* \note
+* This API must not be called while the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode)
+{
+ uint32_t mask, shift;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
+
+ shift = CY_MCWDT_BYTE_SHIFT * counter;
+ mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
+ mask = mask << shift;
+
+ base->MCWDT_CONFIG = (base->MCWDT_CONFIG & ~mask) | ((uint32_t) mode << shift);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetMode
+****************************************************************************//**
+*
+* Reports the mode of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \return
+* The current mode of the counter. See enum typedef cy_en_mcwdtmode_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t mode, mask;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
+ mode = (base->MCWDT_CONFIG >> (CY_MCWDT_BYTE_SHIFT * counter)) & mask;
+
+ return ((cy_en_mcwdtmode_t) mode);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetClearOnMatch
+****************************************************************************//**
+*
+* Sets the Clear on match option for the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \note
+* The match values are not supported by Counter 2.
+*
+* \param enable
+* Set 0 to disable; 1 to enable.
+*
+* \note
+* This API must not be called while the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
+
+ if (CY_MCWDT_COUNTER0 == counter)
+ {
+ base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
+ }
+ else
+ {
+ base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetClearOnMatch
+****************************************************************************//**
+*
+* Reports the Clear on match setting for the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \return
+* The Clear on match status: 1 = enabled, 0 = disabled.
+*
+* \note
+* The match value is not supported by Counter 2.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t getClear;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ if (CY_MCWDT_COUNTER0 == counter)
+ {
+ getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG);
+ }
+ else
+ {
+ getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, base->MCWDT_CONFIG);
+ }
+
+ return (getClear);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetCascade
+****************************************************************************//**
+*
+* Sets all the counter cascade options.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param cascade
+* Sets or clears each of the cascade options.
+*
+* \note
+* This API must not be called when the counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
+
+ base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
+ (uint32_t) cascade);
+ base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
+ ((uint32_t) cascade >> 1u));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetCascade
+****************************************************************************//**
+*
+* Reports all the counter cascade option settings.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The current cascade option values.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base)
+{
+ uint32_t cascade;
+
+ cascade = (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, base->MCWDT_CONFIG) << 1u) |
+ _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, base->MCWDT_CONFIG);
+
+ return ((cy_en_mcwdtcascade_t) cascade);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetMatch
+****************************************************************************//**
+*
+* Sets the match comparison value for the specified counter (0 or 1).
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \param match
+* The value to match against the counter.
+* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
+* and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
+*
+* \note
+* The match value is not supported by Counter 2.
+*
+* \note
+* Action on match is taken on the next increment after the counter value
+* equal to match value.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning,
+* because the match affects after two lf_clk cycles pass. The recommended
+* value is 93 us.
+* \note
+* Setting this parameter to a zero means No wait. This must be taken
+* into account when changing the match values on the running counters.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
+{
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+ CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ?
+ ((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) :
+ ((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U),
+ match));
+
+ base->MCWDT_MATCH = (counter == CY_MCWDT_COUNTER0) ?
+ _CLR_SET_FLD32U(base->MCWDT_MATCH, MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
+ (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
+ _CLR_SET_FLD32U(base->MCWDT_MATCH, MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1,
+ (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk));
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetMatch
+****************************************************************************//**
+*
+* Reports the match comparison value for the specified counter (0 or 1).
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-1].
+*
+* \note
+* The match values are not supported by Counter 2.
+*
+* \return
+* A 16-bit match value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t match;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH) :
+ _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH);
+
+ return (match);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetToggleBit
+****************************************************************************//**
+*
+* Sets a bit in Counter 2 to monitor for a toggle.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param bit
+* The Counter 2 bit is set to monitor for a toggle. The valid range [0-31].
+*
+* \note
+* This API must not be called when counters are running.
+* Prior to calling this API, the counter must be disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
+
+ base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetToggleBit
+****************************************************************************//**
+*
+* Reports which bit in Counter 2 is monitored for a toggle.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The bit that is monitored (range 0 to 31).
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base)
+{
+ return (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, base->MCWDT_CONFIG));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetCount
+****************************************************************************//**
+*
+* Reports the current counter value of the specified counter.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counter
+* The number of the WDT counter. The valid range is [0-2].
+*
+* \return
+* A live counter value. Counters 0 and 1 are 16-bit counters and Counter 2 is
+* a 32-bit counter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
+{
+ uint32_t countVal = 0u;
+
+ CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
+
+ switch (counter)
+ {
+ case CY_MCWDT_COUNTER0:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0, base->MCWDT_CNTLOW);
+ break;
+ case CY_MCWDT_COUNTER1:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1, base->MCWDT_CNTLOW);
+ break;
+ case CY_MCWDT_COUNTER2:
+ countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2, base->MCWDT_CNTHIGH);
+ break;
+
+ default:
+ CY_ASSERT(0u != 0u);
+ break;
+ }
+
+ return (countVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_ResetCounters
+****************************************************************************//**
+*
+* Resets all specified counters.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all counters to reset. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+* \param waitUs
+* The function waits for some delay in microseconds before returning, because
+* a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
+* \note This function resets the counters two times to prevent the case when
+* the Counter 1 is not reset when the counters are cascaded. The delay waitUs
+* must be greater than 100 us when the counters are cascaded.
+* The total delay is greater than 2*waitUs because the function has
+* the delay after the first reset.
+* \note
+* Setting this parameter to a zero means No wait. In this case, it is the
+* user's responsibility to check whether the selected counters were reset
+* immediately after the function call. This can be done by the
+* Cy_MCWDT_GetCount() API.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
+{
+ uint32_t resetCounters;
+
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ /* Extract particular counters for reset */
+ resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
+ ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
+
+ base->MCWDT_CTL |= resetCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+
+ base->MCWDT_CTL |= resetCounters;
+
+ Cy_SysLib_DelayUs(waitUs);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptStatus
+****************************************************************************//**
+*
+* Reports the state of all MCWDT interrupts.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The OR'd state of the interrupts. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base)
+{
+ return (base->MCWDT_INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_ClearInterrupt
+****************************************************************************//**
+*
+* Clears all specified MCWDT interrupts.
+*
+* All the WDT interrupts must be cleared by the firmware; otherwise
+* interrupts are generated continuously.
+*
+* \param base
+* The base pointer to a structure describes registers.
+*
+* \param counters
+* OR of all interrupt sources to clear. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ base->MCWDT_INTR = counters;
+ (void) base->MCWDT_INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetInterrupt
+****************************************************************************//**
+*
+* Sets MCWDT interrupt sources in the interrupt request register.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all interrupt sources to set. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ base->MCWDT_INTR_SET = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the CWDT interrupt mask register. This register specifies which bits
+* from the MCWDT interrupt request register will trigger an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The OR'd state of the interrupt masks. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base)
+{
+ return (base->MCWDT_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_SetInterruptMask
+****************************************************************************//**
+*
+* Writes MCWDT interrupt mask register. This register configures which bits
+* from MCWDT interrupt request register will trigger an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \param counters
+* OR of all interrupt masks to set. See \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
+* CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
+{
+ CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
+
+ base->MCWDT_INTR_MASK = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_MCWDT_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the MCWDT interrupt masked request register. This register contains
+* the logical AND of corresponding bits from the MCWDT interrupt request and
+* mask registers.
+* In the interrupt service routine, this function identifies which of the
+* enabled MCWDT interrupt sources caused an interrupt event.
+*
+* \param base
+* The base pointer to a structure that describes registers.
+*
+* \return
+* The current status of enabled MCWDT interrupt sources. See
+* the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and CY_MCWDT_CTR2 macros.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base)
+{
+ return (base->MCWDT_INTR_MASKED);
+}
+
+
+/** \} group_mcwdt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_MCWDT_H */
+
+/** \} group_mcwdt */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,238 @@
+/***************************************************************************//**
+* \file cy_pdm_pcm.c
+* \version 2.10
+*
+* The source code file for the PDM_PCM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_pdm_pcm.h"
+
+/* The C binding of definitions if building with the C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+* \addtogroup group_pdm_pcm_functions
+* \{
+*/
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_Init
+***************************************************************************//**
+*
+* Initialize the PDM-PCM module
+*
+* \pre If the PDM-PCM module is initialized previously, the
+* \ref Cy_PDM_PCM_DeInit() must be called before calling this function.
+*
+* \param base The pointer to the PDM-PCM instance address
+* \param config The pointer to a configuration structure.
+* \return error / status code. See \ref cy_en_pdm_pcm_status_t.
+*
+* An example of a configuration structure:
+* \snippet PDM_PCM_PDL_sut_00.cydsn/main_cm4.c PDM_PCM Configuration
+*
+*******************************************************************************/
+cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t const * config)
+{
+ cy_en_pdm_pcm_status_t ret = CY_PDM_PCM_BAD_PARAM;
+
+ if((NULL != base) && (NULL != config))
+ {
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->clkDiv));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->mclkDiv));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CKO_CLOCK_DIV_VALID(config->ckoDiv));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_SINC_RATE_VALID(config->sincDecRate));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainRight));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainLeft));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_STEP_SEL_VALID(config->softMuteFineGain));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CH_SET_VALID(config->chanSelect));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_S_CYCLES_VALID(config->softMuteCycles));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CKO_DELAY_VALID(config->ckoDelay));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_HPF_GAIN_VALID(config->highPassFilterGain));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_WORD_LEN_VALID(config->wordLen));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_TRIG_LEVEL(config->rxFifoTriggerLevel, config->chanSelect));
+
+ ret = CY_PDM_PCM_SUCCESS;
+
+ base->CTL &= (uint32_t) ~PDM_CTL_ENABLED_Msk; /* Disable the PDM_PCM block */
+
+ /* The clock setting */
+ base->CLOCK_CTL = _VAL2FLD(PDM_CLOCK_CTL_CLK_CLOCK_DIV, config->clkDiv) |
+ _VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, config->mclkDiv) |
+ _VAL2FLD(PDM_CLOCK_CTL_CKO_CLOCK_DIV, config->ckoDiv) |
+ _VAL2FLD(PDM_CLOCK_CTL_SINC_RATE, config->sincDecRate);
+
+ /* Enable the PDM-PCM block */
+ base->CTL = _VAL2FLD(PDM_CTL_PGA_R, config->gainRight) |
+ _VAL2FLD(PDM_CTL_PGA_L, config->gainLeft) |
+ _VAL2FLD(PDM_CTL_STEP_SEL, config->softMuteFineGain) |
+ _BOOL2FLD(PDM_CTL_SOFT_MUTE, config->softMuteEnable) |
+ _BOOL2FLD(PDM_CTL_ENABLED, true);
+
+ base->MODE_CTL = _VAL2FLD(PDM_MODE_CTL_PCM_CH_SET, config->chanSelect) |
+ _BOOL2FLD(PDM_MODE_CTL_SWAP_LR, config->chanSwapEnable) |
+ _VAL2FLD(PDM_MODE_CTL_S_CYCLES, config->softMuteCycles) |
+ _VAL2FLD(PDM_MODE_CTL_CKO_DELAY, config->ckoDelay) |
+ _VAL2FLD(PDM_MODE_CTL_HPF_GAIN, config->highPassFilterGain) |
+ _BOOL2FLD(PDM_MODE_CTL_HPF_EN_N, config->highPassDisable);
+
+ base->DATA_CTL = _VAL2FLD(PDM_DATA_CTL_WORD_LEN, config->wordLen) |
+ _BOOL2FLD(PDM_DATA_CTL_BIT_EXTENSION, config->signExtension);
+
+ base->RX_FIFO_CTL = _VAL2FLD(PDM_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel);
+
+ base->TR_CTL = _BOOL2FLD(PDM_TR_CTL_RX_REQ_EN, config->dmaTriggerEnable);
+
+ Cy_PDM_PCM_SetInterruptMask(base, config->interruptMask);
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_PDM_PCM_DeInit
+****************************************************************************//**
+*
+* Uninitializes the PDM-PCM module.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+*******************************************************************************/
+void Cy_PDM_PCM_DeInit(PDM_Type * base)
+{
+ base->CMD = 0UL; /* Stop PDM-PCM operation */
+ base->INTR_MASK = 0UL; /* Disable interrupts */
+ base->RX_FIFO_CTL = 0UL;
+ base->TR_CTL = 0UL;
+ base->DATA_CTL = 0UL;
+ base->MODE_CTL = CY_PDM_PCM_MODE_CTL_DEFAULT;
+ base->CTL = CY_PDM_PCM_CTL_DEFAULT; /* Disable the PDM_PCM IP block */
+ base->CLOCK_CTL = CY_PDM_PCM_CLOCK_CTL_DEFAULT; /* The default clock settings */
+}
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_SetGain
+***************************************************************************//**
+*
+* Sets the gain factor to the left or right channel.
+*
+* \param base
+* The pointer to the PDM-PCM instance address.
+*
+* \param chan
+* The channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t.
+*
+* \param gain
+* Gain for the selected channel \ref cy_en_pdm_pcm_gain_t.
+*
+******************************************************************************/
+void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en_pdm_pcm_gain_t gain)
+{
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan));
+ CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(gain));
+
+ if (chan == CY_PDM_PCM_CHAN_LEFT)
+ {
+ base->CTL = _CLR_SET_FLD32U(base->CTL, PDM_CTL_PGA_L, ((uint32_t) gain));
+ }
+ else
+ {
+ base->CTL = _CLR_SET_FLD32U(base->CTL, PDM_CTL_PGA_R, ((uint32_t) gain));
+ }
+}
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetGain
+***************************************************************************//**
+*
+* Retrieves the current gain factor of the left or right channel.
+*
+* \param base
+* the pointer to the PDM-PCM instance address.
+*
+* \param chan
+* The channel selector for gain setting \ref cy_en_pdm_pcm_chan_select_t.
+*
+* \return
+* Gain of the selected channel \ref cy_en_pdm_pcm_gain_t.
+*
+******************************************************************************/
+cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan)
+{
+ cy_en_pdm_pcm_gain_t ret;
+
+ CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan));
+
+ if (chan == CY_PDM_PCM_CHAN_LEFT)
+ {
+ ret = (cy_en_pdm_pcm_gain_t) (_FLD2VAL(PDM_CTL_PGA_L, base->CTL));
+ }
+ else
+ {
+ ret = (cy_en_pdm_pcm_gain_t) (_FLD2VAL(PDM_CTL_PGA_R, base->CTL));
+ }
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_PDM_PCM_DeepSleepCallback
+****************************************************************************//**
+*
+* This is an example callback function that can be used at the application layer to
+* manage the PDM-PCM operation before entering and after exiting Deep-Sleep mode.
+*
+* \param callbackParams
+* The structure with the syspm callback parameters,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* syspm return status, see \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_PDM_PCM_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams)
+{
+ cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ case CY_SYSPM_CHECK_FAIL:
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ Cy_PDM_PCM_Disable((PDM_Type*) callbackParams->base); /* Stop PDM-PCM operation */
+ /* Unload FIFO to do not lost any data (if needed) */
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ Cy_PDM_PCM_ClearFifo((PDM_Type*) callbackParams->base); /* Clear FIFO */
+ Cy_PDM_PCM_Enable((PDM_Type*) callbackParams->base); /* Start PDM-PCM operation */
+ break;
+
+ default:
+ ret = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return(ret);
+}
+
+/** \} group_pdm_pcm_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,769 @@
+/***************************************************************************//**
+* \file cy_pdm_pcm.h
+* \version 2.10
+*
+* The header file of the PDM_PCM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_pdm_pcm PDM-PCM Converter (PDM_PCM)
+* \{
+*
+* The pulse-density modulation to pulse-code modulation (PDM-PCM) driver provides an
+* API to manage PDM-PCM conversion. A PDM-PCM converter is used
+* to convert 1-bit digital audio streaming data to PCM data.
+*
+* Features:
+* * Supports FIFO buffer for Incoming Data
+* * Supports Software Mute Mode
+* * Programmable Gain Settings
+* * Programmable Word Length
+*
+* Pulse-density modulation, or PDM, represents
+* an analog signal with a binary signal. In a PDM signal, specific amplitude values
+* are not encoded into codewords of pulses of different weight as they would be
+* in pulse-code modulation (PCM); rather, the relative density of the pulses corresponds
+* to the analog signal's amplitude. The output of a 1-bit DAC is the same
+* as the PDM encoding of the signal.
+*
+* Pulse-code modulation (PCM) is the method used to digitally represent sampled analog signals.
+* It is the standard form of digital audio in computers, compact discs, digital telephony,
+* and other digital audio applications. In a PCM stream, the amplitude of the analog signal
+* is sampled regularly at uniform intervals, and each sample is quantized
+* to the nearest value within a range of digital steps.
+*
+* \section group_pdm_pcm_configuration_considerations Configuration Considerations
+*
+* To set up a PDM-PCM, provide the configuration parameters in the
+* \ref cy_stc_pdm_pcm_config_t structure.
+*
+* For example, set dataStreamingEnable to true, configure rxFifoTriggerLevel,
+* dmaTriggerEnable (depending on whether DMA is going to be used),
+* provide clock settings (clkDiv, mclkDiv and ckoDiv), set sincDecRate
+* to the appropriate decimation rate, wordLen, and wordBitExtension.
+* No other parameters are necessary for this example.
+*
+* To initialize the PDM-PCM block, call the \ref Cy_PDM_PCM_Init function, providing the
+* filled \ref cy_stc_pdm_pcm_config_t structure.
+*
+* If you use a DMA, the DMA channel should be previously configured. PDM-PCM interrupts
+* (if applicable) can be enabled by calling \ref Cy_PDM_PCM_SetInterruptMask.
+*
+* For example, if the trigger interrupt is used during operation, the ISR
+* should call the \ref Cy_PDM_PCM_ReadFifo as many times as required for your
+* FIFO payload. Then call \ref Cy_PDM_PCM_ClearInterrupt with appropriate parameters.
+*
+* If a DMA is used and the DMA channel is properly configured, no CPU activity
+* (or application code) is needed for PDM-PCM operation.
+*
+* \section group_pdm_pcm_more_information More Information
+* See: the PDM-PCM chapter of the device technical reference manual (TRM);
+* the PDM_PCM_PDL Component datasheet;
+* CE219431 - PSOC 6 MCU PDM-TO-PCM EXAMPLE.
+*
+* \section group_pdm_pcm_MISRA MISRA-C Compliance
+* The PDM-PCM driver has the following specific deviations:
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite expression of the "essentially unsigned" type is
+* cast to a different type category.</td>
+* <td>The value got from the bitfield physically can't exceed the enumeration
+* that describes this bitfield. So the code is safe by design.</td>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to the object type and
+* a different pointer to the object type.</td>
+* <td>The function \ref Cy_I2S_DeepSleepCallback is a callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in this
+* function becomes the user responsibility because the pointer is
+* initialized when a callback is registered in SysPm driver.</td>
+* </tr>
+* </table>
+*
+* \section group_pdm_pcm_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td>The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected.
+* Added Low Power Callback section.</td>
+* <td>Incorrect setting of gain values in limited range.
+* Documentation update and clarification.</td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>Enumeration types for gain and soft mute cycles are added.<br>
+* Function parameter checks are added.<br>
+* The next functions are removed:
+* * Cy_PDM_PCM_EnterLowPowerCallback
+* * Cy_PDM_PCM_ExitLowPowerCallback
+* * Cy_PDM_PCM_EnableDataStream
+* * Cy_PDM_PCM_DisableDataStream
+* * Cy_PDM_PCM_SetFifoLevel
+* * Cy_PDM_PCM_GetFifoLevel
+* * Cy_PDM_PCM_EnableDmaRequest
+* * Cy_PDM_PCM_DisableDmaRequest
+*
+* The next functions behaviour are modified:
+* * Cy_PDM_PCM_Enable
+* * Cy_PDM_PCM_Disable
+* * Cy_PDM_PCM_SetInterruptMask
+* * Cy_PDM_PCM_GetInterruptMask
+* * Cy_PDM_PCM_GetInterruptStatusMasked
+* * Cy_PDM_PCM_GetInterruptStatus
+* * Cy_PDM_PCM_ClearInterrupt
+* * Cy_PDM_PCM_SetInterrupt
+*
+* The Cy_PDM_PCM_GetFifoNumWords function is renamed to Cy_PDM_PCM_GetNumInFifo.<br>
+* The Cy_PDM_PCM_GetCurrentState function is added.
+* </td>
+* <td>Improvements based on usability feedbacks.<br>
+* API is reworked for consistency within the PDL.
+* </td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_pdm_pcm_macros Macros
+* \defgroup group_pdm_pcm_functions Functions
+* \{
+* \defgroup group_pdm_pcm_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_pdm_pcm_data_structures Data Structures
+* \defgroup group_pdm_pcm_enums Enumerated Types
+*
+*/
+
+#if !defined(CY_PDM_PCM_H__)
+#define CY_PDM_PCM_H__
+
+/******************************************************************************/
+/* Include files */
+/******************************************************************************/
+
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifndef CY_IP_MXAUDIOSS
+ #error "The PDM-PCM driver is not supported on this device"
+#endif
+
+/* The C binding of definitions if building with the C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ * Global definitions
+ ******************************************************************************/
+
+/* Macros */
+/**
+* \addtogroup group_pdm_pcm_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_PDM_PCM_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_PDM_PCM_DRV_VERSION_MINOR 10
+
+/** The PDM-PCM driver identifier */
+#define CY_PDM_PCM_ID CY_PDL_DRV_ID(0x26u)
+
+/**
+* \defgroup group_pdm_pcm_macros_intrerrupt_masks Interrupt Masks
+* \{
+*/
+
+/** Bit 16: More entries in the RX FIFO than specified by Trigger Level. */
+#define CY_PDM_PCM_INTR_RX_TRIGGER (PDM_INTR_RX_TRIGGER_Msk)
+/** Bit 18: RX FIFO is not empty. */
+#define CY_PDM_PCM_INTR_RX_NOT_EMPTY (PDM_INTR_RX_NOT_EMPTY_Msk)
+/** Bit 21: Attempt to write to a full RX FIFO. */
+#define CY_PDM_PCM_INTR_RX_OVERFLOW (PDM_INTR_RX_OVERFLOW_Msk)
+/** Bit 22: Attempt to read from an empty RX FIFO. */
+#define CY_PDM_PCM_INTR_RX_UNDERFLOW (PDM_INTR_RX_UNDERFLOW_Msk)
+
+/** \} group_pdm_pcm_macros_intrerrupt_masks */
+
+/** \} group_pdm_pcm_macros */
+
+/**
+* \addtogroup group_pdm_pcm_enums
+* \{
+*/
+
+/** PDM Word Length. */
+typedef enum
+{
+ CY_PDM_PCM_WLEN_16_BIT = 0U, /**< Word length: 16 bit. */
+ CY_PDM_PCM_WLEN_18_BIT = 1U, /**< Word length: 18 bit. */
+ CY_PDM_PCM_WLEN_20_BIT = 2U, /**< Word length: 20 bit. */
+ CY_PDM_PCM_WLEN_24_BIT = 3U /**< Word length: 24 bit. */
+} cy_en_pdm_pcm_word_len_t;
+
+/** PDM Clock Divider. */
+typedef enum
+{
+ CY_PDM_PCM_CLK_DIV_BYPASS = 0U, /**< Clock 1/1. */
+ CY_PDM_PCM_CLK_DIV_1_2 = 1U, /**< Clock 1/2 (no 50% duty cycle). */
+ CY_PDM_PCM_CLK_DIV_1_3 = 2U, /**< Clock 1/3 (no 50% duty cycle). */
+ CY_PDM_PCM_CLK_DIV_1_4 = 3U /**< Clock 1/4 (no 50% duty cycle). */
+} cy_en_pdm_pcm_clk_div_t;
+
+/** PDM Output Mode. */
+typedef enum
+{
+ CY_PDM_PCM_OUT_CHAN_LEFT = 1U, /**< Channel mono left. */
+ CY_PDM_PCM_OUT_CHAN_RIGHT = 2U, /**< Channel mono right. */
+ CY_PDM_PCM_OUT_STEREO = 3U /**< Channel stereo. */
+} cy_en_pdm_pcm_out_t;
+
+/** PDM Channel selector. */
+typedef enum
+{
+ CY_PDM_PCM_CHAN_LEFT = 0U, /**< Channel left. */
+ CY_PDM_PCM_CHAN_RIGHT = 1U /**< Channel right. */
+} cy_en_pdm_pcm_chan_select_t;
+
+/** PDM Gain. */
+typedef enum
+{
+ CY_PDM_PCM_ATTN_12_DB = 0U, /**< -12 dB (attenuation). */
+ CY_PDM_PCM_ATTN_10_5_DB = 1U, /**< -10.5 dB (attenuation). */
+ CY_PDM_PCM_ATTN_9_DB = 2U, /**< -9 dB (attenuation). */
+ CY_PDM_PCM_ATTN_7_5_DB = 3U, /**< -7.5 dB (attenuation). */
+ CY_PDM_PCM_ATTN_6_DB = 4U, /**< -6 dB (attenuation). */
+ CY_PDM_PCM_ATTN_4_5_DB = 5U, /**< -4.5 dB (attenuation). */
+ CY_PDM_PCM_ATTN_3_DB = 6U, /**< -3 dB (attenuation). */
+ CY_PDM_PCM_ATTN_1_5_DB = 7U, /**< -1.5 dB (attenuation). */
+ CY_PDM_PCM_BYPASS = 8U, /**< 0 dB (bypass). */
+ CY_PDM_PCM_GAIN_1_5_DB = 9U, /**< +1.5 dB (amplification). */
+ CY_PDM_PCM_GAIN_3_DB = 10U, /**< +3 dB (amplification). */
+ CY_PDM_PCM_GAIN_4_5_DB = 11U, /**< +4.5 dB (amplification). */
+ CY_PDM_PCM_GAIN_6_DB = 12U, /**< +6 dB (amplification). */
+ CY_PDM_PCM_GAIN_7_5_DB = 13U, /**< +7.5 dB (amplification). */
+ CY_PDM_PCM_GAIN_9_DB = 14U, /**< +9 dB (amplification). */
+ CY_PDM_PCM_GAIN_10_5_DB = 15U /**< +10.5 dB (amplification). */
+} cy_en_pdm_pcm_gain_t;
+
+
+/** The time step for gain change during PGA or soft mute operation in
+ * number of 1/a sampling rate. */
+typedef enum
+{
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_64 = 0U, /**< 64 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_96 = 1U, /**< 96 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_128 = 2U, /**< 128 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_160 = 3U, /**< 160 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_192 = 4U, /**< 192 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_256 = 5U, /**< 256 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_384 = 6U, /**< 384 steps. */
+ CY_PDM_PCM_SOFT_MUTE_CYCLES_512 = 7U /**< 512 steps. */
+} cy_en_pdm_pcm_s_cycles_t;
+
+/** The PDM-PCM status codes. */
+typedef enum
+{
+ CY_PDM_PCM_SUCCESS = 0x00UL, /**< Success status code */
+ CY_PDM_PCM_BAD_PARAM = CY_PDM_PCM_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< Bad parameter status code */
+} cy_en_pdm_pcm_status_t;
+
+/** \} group_pdm_pcm_enums */
+
+
+/**
+* \addtogroup group_pdm_pcm_data_structures
+* \{
+*/
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+/** PDM-PCM initialization configuration */
+typedef struct
+{
+ cy_en_pdm_pcm_clk_div_t clkDiv; /**< PDM Clock Divider (1st divider), see #cy_en_pdm_pcm_clk_div_t
+ This configures a frequency of PDM CLK. The configured frequency
+ is used to operate PDM core. I.e. the frequency is input to
+ MCLKQ_CLOCK_DIV register. */
+ cy_en_pdm_pcm_clk_div_t mclkDiv; /**< MCLKQ divider (2nd divider), see #cy_en_pdm_pcm_clk_div_t */
+ uint8_t ckoDiv; /**< PDM CKO (FPDM_CKO) clock divider (3rd divider):
+ - if CKO_CLOCK_DIV >= 1 - *F(PDM_CKO) = F(PDM_CLK / (mclkDiv + 1))
+ - if CKO_CLOCK_DIV = 0 - *F(PDM_CKO) = MCLKQ / 2 */
+ uint8_t ckoDelay; /**< Extra PDM_CKO delay to internal sampler:
+ - 0: Three extra PDM_CLK period advance
+ - 1: Two extra PDM_CLK period advance
+ - 2: One extra PDM_CLK period advance
+ - 3: No delay
+ - 4: One extra PDM_CLK period delay
+ - 5: Two extra PDM_CLK period delay
+ - 6: Three extra PDM_CLK period delay
+ - 7: Four extra PDM_CLK clock delay */
+ uint8_t sincDecRate; /**< F(MCLK_L_R) = Fs * 2 * sincDecRate * mclkDiv,
+ Fs is a sampling frequency, 8kHz - 48kHz */
+ cy_en_pdm_pcm_out_t chanSelect; /**< see #cy_en_pdm_pcm_out_t */
+ bool chanSwapEnable; /**< Audio channels swapping */
+ uint8_t highPassFilterGain; /**< High pass filter gain:
+ H(Z) = (1 - Z^-1) / (1 - (1 - 2^highPassFilterGain) * Z^-1) */
+ bool highPassDisable; /**< High pass filter disable */
+ cy_en_pdm_pcm_s_cycles_t softMuteCycles; /**< The time step for gain change during PGA or soft mute operation in
+ number of 1/a sampling rate, see #cy_en_pdm_pcm_s_cycles_t. */
+ uint32_t softMuteFineGain; /**< Soft mute fine gain: 0 = 0.13dB, 1 = 0.26dB */
+ bool softMuteEnable; /**< Soft mute enable */
+ cy_en_pdm_pcm_word_len_t wordLen; /**< see #cy_en_pdm_pcm_word_len_t */
+ bool signExtension; /**< Word extension type:
+ - 0: extension by zero
+ - 1: extension by sign bits */
+ cy_en_pdm_pcm_gain_t gainLeft; /**< Gain for left channel, see #cy_en_pdm_pcm_gain_t */
+ cy_en_pdm_pcm_gain_t gainRight; /**< Gain for right channel, see #cy_en_pdm_pcm_gain_t */
+ uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words),
+ range: 0 - 253 for stereo and 0 - 254 for mono mode */
+ bool dmaTriggerEnable; /**< DMA trigger enable */
+ uint32_t interruptMask; /**< Interrupts enable mask */
+} cy_stc_pdm_pcm_config_t;
+
+/** \} group_pdm_pcm_data_structures */
+
+
+/** \cond INTERNAL */
+/******************************************************************************
+ * Local definitions
+*******************************************************************************/
+/** Define bit mask for all available interrupt sources */
+#define CY_PDM_PCM_INTR_MASK (CY_PDM_PCM_INTR_RX_TRIGGER | \
+ CY_PDM_PCM_INTR_RX_NOT_EMPTY | \
+ CY_PDM_PCM_INTR_RX_OVERFLOW | \
+ CY_PDM_PCM_INTR_RX_UNDERFLOW)
+
+/* Non-zero default values */
+#define CY_PDM_PCM_CTL_PGA_R_DEFAULT (0x8U)
+#define CY_PDM_PCM_CTL_PGA_L_DEFAULT (0x8U)
+#define CY_PDM_PCM_CTL_STEP_SEL_DEFAULT (0x1U)
+
+#define CY_PDM_PCM_CTL_DEFAULT (_VAL2FLD(PDM_CTL_PGA_R, CY_PDM_PCM_CTL_PGA_R_DEFAULT) | \
+ _VAL2FLD(PDM_CTL_PGA_L, CY_PDM_PCM_CTL_PGA_L_DEFAULT) | \
+ _VAL2FLD(PDM_CTL_STEP_SEL, CY_PDM_PCM_CTL_STEP_SEL_DEFAULT))
+
+#define CY_PDM_PCM_CLOCK_CTL_MCLKQ_CLOCK_DIV_DEFAULT (0x1U)
+#define CY_PDM_PCM_CLOCK_CTL_CKO_CLOCK_DIV_DEFAULT (0x3U)
+#define CY_PDM_PCM_CLOCK_CTL_SINC_RATE_DEFAULT (0x20U)
+
+#define CY_PDM_PCM_CLOCK_CTL_DEFAULT (_VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, CY_PDM_PCM_CLOCK_CTL_MCLKQ_CLOCK_DIV_DEFAULT) | \
+ _VAL2FLD(PDM_CLOCK_CTL_CKO_CLOCK_DIV, CY_PDM_PCM_CLOCK_CTL_CKO_CLOCK_DIV_DEFAULT) | \
+ _VAL2FLD(PDM_CLOCK_CTL_SINC_RATE, CY_PDM_PCM_CLOCK_CTL_SINC_RATE_DEFAULT))
+
+#define CY_PDM_PCM_MODE_CTL_PCM_CH_SET_DEFAULT (0x3U)
+#define CY_PDM_PCM_MODE_CTL_S_CYCLES_DEFAULT (0x1U)
+#define CY_PDM_PCM_MODE_CTL_HPF_GAIN_DEFAULT (0xBU)
+#define CY_PDM_PCM_MODE_CTL_HPF_EN_N_DEFAULT (0x1U)
+
+#define CY_PDM_PCM_MODE_CTL_DEFAULT (_VAL2FLD(PDM_MODE_CTL_PCM_CH_SET, CY_PDM_PCM_MODE_CTL_PCM_CH_SET_DEFAULT) | \
+ _VAL2FLD(PDM_MODE_CTL_S_CYCLES, CY_PDM_PCM_MODE_CTL_S_CYCLES_DEFAULT) | \
+ _VAL2FLD(PDM_MODE_CTL_HPF_GAIN, CY_PDM_PCM_MODE_CTL_HPF_GAIN_DEFAULT) | \
+ _VAL2FLD(PDM_MODE_CTL_HPF_EN_N, CY_PDM_PCM_MODE_CTL_HPF_EN_N_DEFAULT))
+
+/* Macros for conditions used by CY_ASSERT calls */
+#define CY_PDM_PCM_IS_CLK_DIV_VALID(clkDiv) (((clkDiv) == CY_PDM_PCM_CLK_DIV_BYPASS) || \
+ ((clkDiv) == CY_PDM_PCM_CLK_DIV_1_2) || \
+ ((clkDiv) == CY_PDM_PCM_CLK_DIV_1_3) || \
+ ((clkDiv) == CY_PDM_PCM_CLK_DIV_1_4))
+
+#define CY_PDM_PCM_IS_CH_SET_VALID(chanSelect) (((chanSelect) == CY_PDM_PCM_OUT_CHAN_LEFT) || \
+ ((chanSelect) == CY_PDM_PCM_OUT_CHAN_RIGHT) || \
+ ((chanSelect) == CY_PDM_PCM_OUT_STEREO))
+
+#define CY_PDM_PCM_IS_GAIN_VALID(gain) (((gain) == CY_PDM_PCM_ATTN_12_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_10_5_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_9_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_7_5_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_6_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_4_5_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_3_DB) || \
+ ((gain) == CY_PDM_PCM_ATTN_1_5_DB) || \
+ ((gain) == CY_PDM_PCM_BYPASS) || \
+ ((gain) == CY_PDM_PCM_GAIN_1_5_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_3_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_4_5_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_6_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_7_5_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_9_DB) || \
+ ((gain) == CY_PDM_PCM_GAIN_10_5_DB))
+
+#define CY_PDM_PCM_IS_WORD_LEN_VALID(wordLen) (((wordLen) == CY_PDM_PCM_WLEN_16_BIT) || \
+ ((wordLen) == CY_PDM_PCM_WLEN_18_BIT) || \
+ ((wordLen) == CY_PDM_PCM_WLEN_20_BIT) || \
+ ((wordLen) == CY_PDM_PCM_WLEN_24_BIT))
+
+#define CY_PDM_PCM_IS_CHAN_VALID(chan) (((chan) == CY_PDM_PCM_CHAN_LEFT) || \
+ ((chan) == CY_PDM_PCM_CHAN_RIGHT))
+
+#define CY_PDM_PCM_IS_S_CYCLES_VALID(sCycles) (((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_64) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_96) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_128) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_160) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_192) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_256) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_384) || \
+ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_512))
+
+#define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_INTR_MASK)))
+#define CY_PDM_PCM_IS_SINC_RATE_VALID(sincRate) ((sincRate) <= 127U)
+#define CY_PDM_PCM_IS_STEP_SEL_VALID(stepSel) ((stepSel) <= 1UL)
+#define CY_PDM_PCM_IS_CKO_DELAY_VALID(ckoDelay) ((ckoDelay) <= 7U)
+#define CY_PDM_PCM_IS_HPF_GAIN_VALID(hpfGain) ((hpfGain) <= 15U)
+#define CY_PDM_PCM_IS_CKO_CLOCK_DIV_VALID(ckoDiv) (((ckoDiv) >= 1U) && ((ckoDiv) <= 15U))
+#define CY_PDM_PCM_IS_TRIG_LEVEL(trigLevel, chanSelect) ((trigLevel) <= (((chanSelect) == CY_PDM_PCM_OUT_STEREO)? 253U : 254U))
+/** \endcond */
+
+/**
+* \addtogroup group_pdm_pcm_functions
+* \{
+*/
+
+cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t const * config);
+ void Cy_PDM_PCM_DeInit(PDM_Type * base);
+ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en_pdm_pcm_gain_t gain);
+cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan);
+
+/** \addtogroup group_pdm_pcm_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_PDM_PCM_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams);
+/** \} */
+
+__STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base);
+__STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base);
+__STATIC_INLINE void Cy_PDM_PCM_SetInterruptMask(PDM_Type * base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptMask(PDM_Type const * base);
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatusMasked(PDM_Type const * base);
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatus(PDM_Type const * base);
+__STATIC_INLINE void Cy_PDM_PCM_ClearInterrupt(PDM_Type * base, uint32_t interrupt);
+__STATIC_INLINE void Cy_PDM_PCM_SetInterrupt(PDM_Type * base, uint32_t interrupt);
+__STATIC_INLINE uint8_t Cy_PDM_PCM_GetNumInFifo(PDM_Type const * base);
+__STATIC_INLINE void Cy_PDM_PCM_ClearFifo(PDM_Type * base);
+__STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifo(PDM_Type const * base);
+__STATIC_INLINE void Cy_PDM_PCM_EnableSoftMute(PDM_Type * base);
+__STATIC_INLINE void Cy_PDM_PCM_DisableSoftMute(PDM_Type * base);
+__STATIC_INLINE void Cy_PDM_PCM_FreezeFifo(PDM_Type * base);
+__STATIC_INLINE void Cy_PDM_PCM_UnfreezeFifo(PDM_Type * base);
+__STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifoSilent(PDM_Type const * base);
+
+
+/** \} group_pdm_pcm_functions */
+
+/**
+* \addtogroup group_pdm_pcm_functions
+* \{
+*/
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_Enable
+***************************************************************************//**
+*
+* Enables the PDM-PCM data conversion.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_Enable(PDM_Type * base)
+{
+ base->CMD |= PDM_CMD_STREAM_EN_Msk;
+}
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_Disable
+***************************************************************************//**
+*
+* Disables the PDM-PCM data conversion.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_Disable(PDM_Type * base)
+{
+ base->CMD &= (uint32_t) ~PDM_CMD_STREAM_EN_Msk;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetCurrentState
+***************************************************************************//**
+*
+* Returns the current PDM-PCM state (running/stopped).
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The current state (CMD register).
+*
+******************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetCurrentState(PDM_Type const * base)
+{
+ return (base->CMD);
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_SetInterruptMask
+***************************************************************************//**
+*
+* Sets one or more PDM-PCM interrupt factor bits (sets the INTR_MASK register).
+*
+* \param base The pointer to the PDM-PCM instance address
+* \param interrupt Interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_SetInterruptMask(PDM_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
+ base->INTR_MASK = interrupt;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetInterruptMask
+***************************************************************************//**
+*
+* Returns the PDM-PCM interrupt mask (a content of the INTR_MASK register).
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+******************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptMask(PDM_Type const * base)
+{
+ return (base->INTR_MASK);
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetInterruptStatusMasked
+***************************************************************************//**
+*
+* Reports the status of enabled (masked) PDM-PCM interrupt sources.
+* (an INTR_MASKED register).
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+*****************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatusMasked(PDM_Type const * base)
+{
+ return (base->INTR_MASKED);
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetInterruptStatus
+***************************************************************************//**
+*
+* Reports the status of PDM-PCM interrupt sources (an INTR register).
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+******************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatus(PDM_Type const * base)
+{
+ return (base->INTR);
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_ClearInterrupt
+***************************************************************************//**
+*
+* Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits).
+*
+* \param base The pointer to the PDM-PCM instance address
+* \param interrupt
+* The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_ClearInterrupt(PDM_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
+ base->INTR = interrupt;
+ (void) base->INTR;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_SetInterrupt
+***************************************************************************//**
+*
+* Sets one or more interrupt source statuses (sets an INTR_SET register).
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \param interrupt
+* The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_SetInterrupt(PDM_Type * base, uint32_t interrupt)
+{
+ CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
+ base->INTR_SET = interrupt;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_GetNumInFifo
+***************************************************************************//**
+*
+* Reports the current number of used words in the output data FIFO.
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The current number of used FIFO words (range is 0 - 254).
+*
+******************************************************************************/
+__STATIC_INLINE uint8_t Cy_PDM_PCM_GetNumInFifo(PDM_Type const * base)
+{
+ return (uint8_t) (_FLD2VAL(PDM_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS));
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_ClearFifo
+***************************************************************************//**
+*
+* Resets the output data FIFO, removing all data words from the FIFO.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_ClearFifo(PDM_Type * base)
+{
+ base->RX_FIFO_CTL |= PDM_RX_FIFO_CTL_CLEAR_Msk; /* clear FIFO and disable it */
+ base->RX_FIFO_CTL &= (uint32_t) ~PDM_RX_FIFO_CTL_CLEAR_Msk; /* enable FIFO */
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_ReadFifo
+***************************************************************************//**
+*
+* Reads ("pops") one word from the output data FIFO.
+*
+* \param base The pointer to the PDM-PCM instance address.
+* \return The data word.
+*
+******************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifo(PDM_Type const * base)
+{
+ return (base->RX_FIFO_RD);
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_EnableSoftMute
+***************************************************************************//**
+*
+* Enables soft mute.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_EnableSoftMute(PDM_Type * base)
+{
+ base->CTL |= PDM_CTL_SOFT_MUTE_Msk;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_DisableSoftMute
+***************************************************************************//**
+*
+* Disables soft mute.
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_DisableSoftMute(PDM_Type * base)
+{
+ base->CTL &= (uint32_t) ~PDM_CTL_SOFT_MUTE_Msk;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_FreezeFifo
+***************************************************************************//**
+*
+* Freezes the RX FIFO (Debug purpose).
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_FreezeFifo(PDM_Type * base)
+{
+ base->RX_FIFO_CTL |= PDM_RX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_UnfreezeFifo
+***************************************************************************//**
+*
+* Unfreezes the RX FIFO (Debug purpose).
+*
+* \param base The pointer to the PDM-PCM instance address.
+*
+******************************************************************************/
+__STATIC_INLINE void Cy_PDM_PCM_UnfreezeFifo(PDM_Type * base)
+{
+ base->RX_FIFO_CTL &= (uint32_t) ~PDM_RX_FIFO_CTL_FREEZE_Msk;
+}
+
+
+/******************************************************************************
+* Function Name: Cy_PDM_PCM_ReadFifoSilent
+***************************************************************************//**
+*
+* Reads the RX FIFO silent (without touching the FIFO function).
+*
+* \param base Pointer to PDM-PCM instance address.
+* \return FIFO value.
+*
+******************************************************************************/
+__STATIC_INLINE uint32_t Cy_PDM_PCM_ReadFifoSilent(PDM_Type const * base)
+{
+ return (base->RX_FIFO_RD_SILENT);
+}
+
+/** \} group_pdm_pcm_functions */
+
+#ifdef __cplusplus
+}
+#endif /* of __cplusplus */
+
+#endif /* CY_PDM_PCM_H__ */
+
+/** \} group_pdm_pcm */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,426 @@
+/***************************************************************************//**
+* \file cy_profile.c
+* \version 1.0
+*
+* Provides an API declaration of the energy profiler (EP) driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_profile.h"
+#include <string.h>
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/* Number of elements in an array */
+#define CY_N_ELMTS(a) (sizeof(a)/sizeof((a)[0]))
+
+static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr);
+
+/* Internal structure - Control and status information for each counter */
+static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR];
+
+
+/* ========================================================================== */
+/* ===================== LOCAL FUNCTION SECTION ====================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_IsPtrValid
+****************************************************************************//**
+*
+* Local utility function: reports (1) whether or not a given pointer points into
+* the cy_ep_ctrs[] array, and (2) whether the counter has been assigned.
+*
+* \param ctrAddr The handle to (address of) the assigned counter
+*
+* \return CY_PROFILE_SUCCESS, or CY_PROFILE_BAD_PARAM for invalid ctrAddr or counter not
+* in use.
+*
+*******************************************************************************/
+static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr)
+{
+ cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM;
+
+ /* check for valid ctrAddr */
+ uint32_t p_epCtrs = (uint32_t)cy_ep_ctrs;
+ if ((p_epCtrs <= (uint32_t)ctrAddr) && ((uint32_t)ctrAddr < (p_epCtrs + (uint32_t)sizeof(cy_ep_ctrs))))
+ {
+ if (ctrAddr->used != 0u) /* check for counter being used */
+ {
+ retStatus = CY_PROFILE_SUCCESS;
+ }
+ }
+ return (retStatus);
+}
+
+
+/* ========================================================================== */
+/* ==================== INTERRUPT FUNCTION SECTION ==================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_ISR
+****************************************************************************//**
+*
+* EP interrupt handler: Increments the overflow member of the counter structure,
+* for each counter that is in use and has an overflow.
+*
+* This handler is not configured or used automatically. You must configure the
+* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure
+* the system to use \ref Cy_Profile_ISR() as the overflow interrupt handler. You
+* can provide a custom interrupt handler to perform additional operations if
+* required. Your handler can call \ref Cy_Profile_ISR() to handle counter
+* overflow.
+*
+*******************************************************************************/
+void Cy_Profile_ISR(void)
+{
+ uint32_t ctr;
+
+ /* Grab a copy of the overflow register. Each bit in the register indicates
+ whether or not the respective counter has overflowed. */
+ uint32_t ovflowBits = _FLD2VAL(PROFILE_INTR_MASKED_CNT_OVFLW, PROFILE->INTR_MASKED);
+
+ PROFILE->INTR = ovflowBits; /* clear the sources of the interrupts */
+
+ /* scan through the overflow bits, i.e., for each counter */
+ for (ctr = 0UL; (ctr < (uint32_t)(PROFILE_PRFL_CNT_NR)) && (ovflowBits != 0UL); ctr++)
+ {
+ /* Increment the overflow bit only if the counter is being used.
+ (Which should always be the case.) */
+ if (((ovflowBits & 1UL) != 0UL) && (cy_ep_ctrs[ctr].used != 0u))
+ {
+ cy_ep_ctrs[ctr].overflow++;
+ }
+ ovflowBits >>= 1; /* check the next bit, by shifting it into the LS position */
+ }
+}
+
+
+/* ========================================================================== */
+/* ================== GENERAL PROFILE FUNCTIONS ==================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_StartProfiling
+****************************************************************************//**
+*
+* Starts the profiling/measurement window.
+*
+* This operation allows the enabled profile counters to start counting.
+*
+* \note The profile interrupt should be enabled before calling this function
+* in order for the firmware to be notified when a counter overflow occurs.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_StartProfiling
+*
+*******************************************************************************/
+void Cy_Profile_StartProfiling(void)
+{
+ uint32_t i;
+
+ /* clear all of the counter array overflow variables */
+ for (i = 0UL; i < CY_N_ELMTS(cy_ep_ctrs); cy_ep_ctrs[i++].overflow = 0UL){}
+ /* send the hardware command */
+ PROFILE->CMD = CY_PROFILE_START_TR;
+}
+
+
+/* ========================================================================== */
+/* =================== COUNTER FUNCTIONS SECTION ====================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_ClearConfiguration
+****************************************************************************//**
+*
+* Clears all counter configurations and sets all counters and overflow counters
+* to 0. Calls Cy_Profile_ClearCounters() to clear counter registers.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ClearConfiguration
+*
+*******************************************************************************/
+void Cy_Profile_ClearConfiguration(void)
+{
+ (void)memset((void *)cy_ep_ctrs, 0, sizeof(cy_ep_ctrs));
+ Cy_Profile_ClearCounters();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_ConfigureCounter
+****************************************************************************//**
+*
+* Configures and assigns a hardware profile counter to the list of used counters.
+*
+* This function assigns an available profile counter to a slot in the internal
+* software data structure and returns the handle for that slot location. The data
+* structure is used to keep track of the counter status and to implement a 64-bit
+* profile counter. If no counter slots are available, the function returns a
+* NULL pointer.
+*
+* \param monitor The monitor source number
+*
+* \param duration Events are monitored (0), or duration is monitored (1)
+*
+* \param refClk Counter reference clock
+*
+* \param weight Weighting factor for the counter value
+*
+* \return A pointer to the counter data structure. NULL if no counter is
+* available.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ConfigureCounter
+*
+*******************************************************************************/
+cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy_en_profile_duration_t duration,
+ cy_en_profile_ref_clk_t refClk, uint32_t weight)
+{
+ cy_stc_profile_ctr_ptr_t retVal = NULL; /* error value if no counter is available */
+ volatile uint8_t i;
+ /* scan through the counters for an unused one */
+ for (i = 0u; (cy_ep_ctrs[i].used != 0u) && (i < CY_N_ELMTS(cy_ep_ctrs)); i++){}
+ if (i < CY_N_ELMTS(cy_ep_ctrs))
+ { /* found one, fill in its data structure */
+ cy_ep_ctrs[i].ctrNum = i;
+ cy_ep_ctrs[i].used = 1u;
+ cy_ep_ctrs[i].cntAddr = (PROFILE_CNT_STRUCT_Type *)&(PROFILE->CNT_STRUCT[i]);
+ cy_ep_ctrs[i].ctlRegVals.cntDuration = duration;
+ cy_ep_ctrs[i].ctlRegVals.refClkSel = refClk;
+ cy_ep_ctrs[i].ctlRegVals.monSel = monitor;
+ cy_ep_ctrs[i].overflow = 0UL;
+ cy_ep_ctrs[i].weight = weight;
+ /* pass back the handle to (address of) the counter data structure */
+ retVal = &cy_ep_ctrs[i];
+
+ /* Load the CTL register bitfields of the assigned counter. */
+ retVal->cntAddr->CTL =
+ _VAL2FLD(PROFILE_CNT_STRUCT_CTL_CNT_DURATION, retVal->ctlRegVals.cntDuration) |
+ _VAL2FLD(PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL, retVal->ctlRegVals.refClkSel) |
+ _VAL2FLD(PROFILE_CNT_STRUCT_CTL_MON_SEL, retVal->ctlRegVals.monSel);
+
+ }
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_FreeCounter
+****************************************************************************//**
+*
+* Frees up a counter from a previously-assigned monitor source.
+*
+* \ref Cy_Profile_ConfigureCounter() must have been called for this counter
+* before calling this function.
+*
+* \param ctrAddr The handle to the assigned counter (returned by calling
+* \ref Cy_Profile_ConfigureCounter()).
+*
+* \return
+* Status of the operation.
+*
+* \note The counter is not disabled by this function.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_FreeCounter
+*
+*******************************************************************************/
+cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
+{
+ cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM;
+
+ retStatus = Cy_Profile_IsPtrValid(ctrAddr);
+ if (retStatus == CY_PROFILE_SUCCESS)
+ {
+ ctrAddr->used = 0u;
+ }
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_EnableCounter
+****************************************************************************//**
+*
+* Enables an assigned counter.
+*
+* \ref Cy_Profile_ConfigureCounter() must have been called for this counter
+* before calling this function.
+*
+* \param ctrAddr The handle to the assigned counter, (returned by calling
+* \ref Cy_Profile_ConfigureCounter()).
+*
+* \return
+* Status of the operation.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_EnableCounter
+*
+*******************************************************************************/
+cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
+{
+ cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM;
+
+ retStatus = Cy_Profile_IsPtrValid(ctrAddr);
+ if (retStatus == CY_PROFILE_SUCCESS)
+ {
+ /* set the ENABLED bit */
+ ctrAddr->cntAddr->CTL |= _VAL2FLD(PROFILE_CNT_STRUCT_CTL_ENABLED, 1UL);
+ /* set the INTR_MASK bit for the counter being used */
+ PROFILE->INTR_MASK |= (1UL << (ctrAddr->ctrNum));
+ }
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_DisableCounter
+****************************************************************************//**
+*
+* Disables an assigned counter.
+*
+* \ref Cy_Profile_ConfigureCounter() must have been called for this counter
+* before calling this function.
+*
+* \param ctrAddr The handle to the assigned counter, (returned by calling
+* \ref Cy_Profile_ConfigureCounter()).
+*
+* \return
+* Status of the operation.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_DisableCounter
+*
+*******************************************************************************/
+cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
+{
+ cy_en_profile_status_t retStatus = Cy_Profile_IsPtrValid(ctrAddr);
+ if (retStatus == CY_PROFILE_SUCCESS)
+ {
+ /* clear the ENABLED bit */
+ ctrAddr->cntAddr->CTL &= ~(_VAL2FLD(PROFILE_CNT_STRUCT_CTL_ENABLED, 1UL));
+ /* clear the INTR_MASK bit for the counter being used */
+ PROFILE->INTR_MASK &= ~(1UL << (ctrAddr->ctrNum));
+ }
+ return (retStatus);
+}
+
+
+/* ========================================================================== */
+/* ================== CALCULATION FUNCTIONS SECTION =================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_GetRawCount
+****************************************************************************//**
+*
+* Reports the raw count value for a specified counter.
+*
+* \param ctrAddr The handle to the assigned counter, (returned by calling
+* \ref Cy_Profile_ConfigureCounter()).
+*
+* \param result Output parameter used to write in the result.
+*
+* \return
+* Status of the operation.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetRawCount
+*
+*******************************************************************************/
+cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result)
+{
+ cy_en_profile_status_t retStatus = Cy_Profile_IsPtrValid(ctrAddr);
+ if (retStatus == CY_PROFILE_SUCCESS)
+ {
+ /* read the counter control register, and the counter current value */
+ ctrAddr->ctlReg = ctrAddr->cntAddr->CTL;
+ ctrAddr->cntReg = ctrAddr->cntAddr->CNT;
+
+ /* report the count with overflow */
+ *result = ((uint64_t)(ctrAddr->overflow) << 32) | (uint64_t)(ctrAddr->cntReg);
+ }
+ return (retStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_Profile_GetWeightedCount
+****************************************************************************//**
+*
+* Reports the count value for a specified counter, multiplied by the weight
+* factor for that counter.
+*
+* \param ctrAddr The handle to the assigned counter, (returned by calling
+* \ref Cy_Profile_ConfigureCounter()).
+*
+* \param result Output parameter used to write in the result.
+*
+* \return
+* Status of the operation.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetWeightedCount
+*
+*******************************************************************************/
+cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result)
+{
+ uint64_t temp;
+ cy_en_profile_status_t retStatus = Cy_Profile_GetRawCount(ctrAddr, &temp);
+ if (retStatus == CY_PROFILE_SUCCESS)
+ {
+ /* calculate weighted count */
+ *result = temp * (uint64_t)(ctrAddr->weight);
+ }
+ return (retStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_Profile_GetSumWeightedCounts
+****************************************************************************//**
+*
+* Reports the weighted sum result of the first n number of counter count values
+* starting from the specified profile counter data structure base address.
+*
+* Each count value is multiplied by its weighing factor before the summing
+* operation is performed.
+*
+* \param ptrsArray Base address of the profile counter data structure
+*
+* \param numCounters Number of measured counters in ptrsArray[]
+*
+* \return
+* The weighted sum of the specified counters
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_GetSumWeightedCounts
+*
+*******************************************************************************/
+uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[],
+ uint32_t numCounters)
+{
+ uint64_t daSum = (uint64_t)0ul;
+ uint64_t num;
+ uint32_t i;
+
+ for (i = 0ul; i < numCounters; i++)
+ {
+ /* ignore error reported by Ep_GetWeightedCount() */
+ if (Cy_Profile_GetWeightedCount(ptrsArray[i], &num) == CY_PROFILE_SUCCESS)
+ {
+ daSum += num;
+ }
+ }
+
+ return (daSum);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,456 @@
+/***************************************************************************//**
+* \file cy_profile.h
+* \version 1.0
+*
+* Provides an API declaration of the energy profiler driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_energy_profiler Energy Profiler (Profile)
+* \{
+*
+* The energy profiler driver is an API for configuring and using the profile
+* hardware block. The profile block enables measurement of the signal activity
+* of select peripherals and monitor sources during a measurement window. Using
+* these measurements, it is possible to construct a profile of the energy consumed
+* in the device by scaling the individual peripheral actvities with appropriate
+* scaling (weight) factors. This gives the application the ability to monitor
+* the energy consumed by the internal resources with minimal CPU overhead and
+* without external monitoring hardware.
+*
+* \section group_profile_details Details
+*
+* \subsection group_profile_hardware Profile Hardware
+*
+* The profile hardware consists of a number of profile counters that accept specific
+* triggers for incrementing the count value. This allows the events of the source
+* (such as the number of SCB0 bus accesses or the duration of time the BLE RX radio
+* is active) to be counted during the measurement window. The available monitor
+* sources in the device can be found in the en_ep_mon_sel_t enum in the device
+* configuration file (e.g. psoc62_config.h). These can be sourced to any of the
+* profile counters as triggers. There are two methods of using the monitor sources
+* in a profile counter.
+*
+* - Event: The count value is incremented when a pulse event signal is seen by the
+* counter. This type of monitoring is suitable when the monitoring source of
+* interest needs to count the discrete events (such as the number of Flash read
+* accesses) happening in the measurement window.
+*
+* - Duration: The count value is incremented at every clock edge while the monitor
+* signal is high. This type of monitoring is suitable when a signal is active for
+* a finite amount of time (such as the time the BLE TX radio is active) and the
+* duration needs to be expressed as number of clock cycles in the measurement window.
+*
+* Many of the available monitor sources are suitable for event type monitoring.
+* Using a duration type on these signals may not give valuable information. Review
+* the device TRM for more information on the monitor sources and details on how they
+* should be used.
+*
+* \subsection group_profile_measurement_types Measurement Types
+*
+* Depending on the item of interest, energy measurement can be performed by using
+* the following methods.
+*
+* - Continuous measurement: A profile counter can be assigned a monitor signal of
+* constant 1 (PROFILE_ONE), which sets the counter to increment at every (assigned)
+* clock cycle. This can be used to give a reference time for the measurement window
+* and also allows the construction of time stamps. For example, a software controlled
+* GPIO can be "timestamped" by reading the counter value (on the fly) before it is
+* toggled. When the measurement window ends, the energy contribution caused by the
+* GPIO toggle can be incorporated into the final calculation.
+*
+* - Event measurement: Monitored events happening in a measurement window can be
+* used to increment a profile counter. This gives the activity numbers, which can
+* then be multiplied by the instantaneous power numbers associated with the source
+* to give the average energy consumption (Energy = Power x time). For example, the
+* energy consumped by an Operating System (OS) task can be estimated by monitoring
+* the processor's active cycle count (E.g. CPUSS_MONITOR_CM4) and the Flash read
+* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be
+* timestamped using the continuous measurement method to differentiate between the
+* different task switches. The activity numbers are then multiplied by the associated
+* processor and flash access power numbers to give the average energy consumed by
+* that task.
+*
+* - Duration measurement: A peripheral event such as the SMIF select signal can be
+* used by a profile counter to measure the time spent on XIP communication through the
+* SPI interface. This activity number can then be multiplied by the power associated
+* with that activity to give the average energy consumed by that block during the
+* measurement window. This type of monitoring should only be performed for signals
+* that are difficult to track in software. For example, a combination of interrupts
+* and time stamps can be used to track the activity of many peripherals in a continuous
+* monitoring model. However tracking the activity of signals such the BLE radio
+* should be done using the duration measurement method.
+*
+* - Low power measurement: The profile counters do not support measurement during chip
+* deep-sleep, hibernate and off states. i.e. the profile counters are meant for active
+* run-time measurements only. In order to measure the time spent in low power modes (LPM),
+* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a
+* timestamp upon LPM exit in a continuous measurement model. Then multiply the difference
+* by the appropriate LPM power numbers.
+*
+* \subsection group_profile_usage Driver Usage
+*
+* At the highest level, the energy profiler must perform the following steps to
+* obtain a measurement:
+*
+* 1. Initialize the profile hardware block.
+* 2. Initialize the profile interrupt (profile_interrupt_IRQn).
+* 3. Configure, initialize, and enable the profile counters.
+* 4. Enable the profile interrupt and start the profiling/measurement window.
+* 5. Perform run-time reads of the counters (if needed).
+* 6. Disable the profile interrupt and stop the profiling/measurement window.
+* 7. Read the counters and gather the results.
+* 8. Calculate the energy consumption.
+*
+* Refer to the SysInt driver on the details of configuring the profile hardware interrupt.
+*
+* The profile interrupt triggers when a counter overflow event is detected on any of the
+* enabled profile counters. A sample interrupt service routine Cy_Profile_ISR() is provided,
+* which can be used to update the internal counter states stored in RAM. Refer to the
+* Configuration Considerations for more information.
+*
+* \section group_profile_configuration Configuration Considerations
+*
+* Each counter is a 32-bit register that counts either a number of clock cycles,
+* or a number of events. It is possible to overflow the 32-bit register. To address
+* this issue, the driver implements a 32-bit overflow counter. Combined with the 32-bit
+* register, this gives a 64-bit counter for each monitored source.
+*
+* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is
+* configured using the SysInt driver, where the sample interrupt handler Cy_Profile_ISR()
+* can be used as the ISR. The ISR increments the overflow counter for each profiling counter
+* and clears the interrupt.
+*
+* \section group_profile_more_information More Information
+*
+* See the profiler chapter of the device technical reference manual (TRM).
+*
+* \section group_profile_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>12.4</td>
+* <td>R</td>
+* <td>Right hand operand of '&&' or '||' is an expression with possible side effects.</td>
+* <td>Function-like macros are used to achieve more efficient code.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>A pointer parameter can be of type 'pointer to const'.</td>
+* <td>The pointer is cast for comparison purposes and thus can't be a const.</td>
+* </tr>
+* </table>
+*
+* \section group_profile_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_profile_macros Macros
+* \defgroup group_profile_functions Functions
+* \{
+* \defgroup group_profile_functions_interrupt Interrupt Functions
+* \defgroup group_profile_functions_general General Functions
+* \defgroup group_profile_functions_counter Counter Functions
+* \defgroup group_profile_functions_calculation Calculation Functions
+* \}
+* \defgroup group_profile_data_structures Data Structures
+* \defgroup group_profile_enums Enumerated Types
+*/
+
+#if !defined(CY_PROFILE_H)
+#define CY_PROFILE_H
+
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include <stddef.h>
+
+#ifndef CY_IP_MXPROFILE
+ #error "The PROFILE driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/** \addtogroup group_profile_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_PROFILE_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_PROFILE_DRV_VERSION_MINOR 0
+
+/** Profile driver identifier */
+#define CY_PROFILE_ID CY_PDL_DRV_ID(0x1EU)
+
+/** Start profiling command for the CMD register */
+#define CY_PROFILE_START_TR 1UL
+
+/** Stop profiling command for the CMD register */
+#define CY_PROFILE_STOP_TR 2UL
+
+/** Command to clear all counter registers to 0 */
+#define CY_PROFILE_CLR_ALL_CNT 0x100UL
+
+/** \} group_profile_macros */
+
+/**
+* \addtogroup group_profile_enums
+* \{
+*/
+
+/**
+* Profile counter reference clock source. Used when duration monitoring.
+*/
+typedef enum
+{
+ CY_PROFILE_CLK_TIMER = 0, /**< Timer clock (TimerClk) */
+ CY_PROFILE_CLK_IMO = 1, /**< Internal main oscillator (IMO) */
+ CY_PROFILE_CLK_ECO = 2, /**< External crystal oscillator (ECO) */
+ CY_PROFILE_CLK_LF = 3, /**< Low-frequency clock (LFCLK) */
+ CY_PROFILE_CLK_HF = 4, /**< High-Frequency clock (HFCLK0) */
+ CY_PROFILE_CLK_PERI = 5, /**< Peripheral clock (PeriClk) */
+} cy_en_profile_ref_clk_t;
+
+/**
+* Monitor method type.
+*/
+typedef enum
+{
+ CY_PROFILE_EVENT = 0, /**< Count (edge-detected) module events */
+ CY_PROFILE_DURATION = 1, /**< Count (level) duration in clock cycles */
+} cy_en_profile_duration_t;
+
+/** Profiler status codes */
+typedef enum
+{
+ CY_PROFILE_SUCCESS = 0x00U, /**< Operation completed successfully */
+ CY_PROFILE_BAD_PARAM = CY_PROFILE_ID | CY_PDL_STATUS_ERROR | 1UL /**< Invalid input parameters */
+
+ } cy_en_profile_status_t;
+
+ /** \} group_profile_enums */
+
+/**
+* \addtogroup group_profile_data_structures
+* \{
+*/
+
+/**
+* Profile counter control register structure. For each counter, holds the CTL register fields.
+*/
+typedef struct
+{
+ cy_en_profile_duration_t cntDuration; /**< 0 = event; 1 = duration */
+ cy_en_profile_ref_clk_t refClkSel; /**< The reference clock used by the counter */
+ en_ep_mon_sel_t monSel; /**< The monitor signal to be observed by the counter */
+} cy_stc_profile_ctr_ctl_t;
+
+/**
+* Software structure for holding a profile counter status and configuration information.
+*/
+typedef struct
+{
+ uint8_t ctrNum; /**< Profile counter number */
+ uint8_t used; /**< 0 = available; 1 = used */
+ cy_stc_profile_ctr_ctl_t ctlRegVals; /**< Initial counter CTL register settings */
+ PROFILE_CNT_STRUCT_Type * cntAddr; /**< Base address of the counter instance registers */
+ uint32_t ctlReg; /**< Current CTL register value */
+ uint32_t cntReg; /**< Current CNT register value */
+ uint32_t overflow; /**< Extension of cntReg to form a 64-bit counter value */
+ uint32_t weight; /**< Weighting factor for the counter */
+} cy_stc_profile_ctr_t;
+
+/**
+* Pointer to a structure holding the status information for a profile counter.
+*/
+typedef cy_stc_profile_ctr_t * cy_stc_profile_ctr_ptr_t;
+/** \} group_profile_data_structures */
+
+/**
+* \addtogroup group_profile_functions
+* \{
+*/
+
+/**
+* \addtogroup group_profile_functions_interrupt
+* \{
+*/
+/* ========================================================================== */
+/* ==================== INTERRUPT FUNCTION SECTION ==================== */
+/* ========================================================================== */
+void Cy_Profile_ISR(void);
+/** \} group_profile_functions_interrupt */
+
+/**
+* \addtogroup group_profile_functions_general
+* \{
+*/
+__STATIC_INLINE void Cy_Profile_Init(void);
+__STATIC_INLINE void Cy_Profile_DeInit(void);
+void Cy_Profile_StartProfiling(void);
+__STATIC_INLINE void Cy_Profile_DeInit(void);
+__STATIC_INLINE void Cy_Profile_StopProfiling(void);
+__STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void);
+
+
+/* ========================================================================== */
+/* =============== GENERAL PROFILE FUNCTIONS SECTION ================= */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_Init
+****************************************************************************//**
+*
+* Initializes and enables the profile hardware.
+*
+* This function must be called once when energy profiling is desired. The
+* operation does not start a profiling session.
+*
+* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR()
+* can be used as its handler.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_Init
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_Profile_Init(void)
+{
+ PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) |
+ _VAL2FLD(PROFILE_CTL_WIN_MODE, 0UL/*start/stop mode*/);
+ PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_DeInit
+****************************************************************************//**
+*
+* Clears the interrupt mask and disables the profile hardware.
+*
+* This function should be called when energy profiling is no longer desired.
+*
+* \note The profile interrupt is not disabled by this operation and must be
+* disabled separately.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_DeInit
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_Profile_DeInit(void)
+{
+ PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 0UL/*disabled */);
+ PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_StopProfiling
+****************************************************************************//**
+*
+* Stops the profiling/measurement window.
+*
+* This operation prevents the enabled profile counters from counting.
+*
+* \note The profile interrupt should be disabled before calling this function.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_StopProfiling
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_Profile_StopProfiling(void)
+{
+ PROFILE->CMD = CY_PROFILE_STOP_TR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Profile_IsProfiling
+****************************************************************************//**
+*
+* Reports the active status of the profiling window.
+*
+* \return 0 = profiling is not active; 1 = profiling is active
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_IsProfiling
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void)
+{
+ return _FLD2VAL(PROFILE_STATUS_WIN_ACTIVE, PROFILE->STATUS);
+}
+/** \} group_profile_functions_general */
+
+/**
+* \addtogroup group_profile_functions_counter
+* \{
+*/
+void Cy_Profile_ClearConfiguration(void);
+__STATIC_INLINE void Cy_Profile_ClearCounters(void);
+cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy_en_profile_duration_t duration, cy_en_profile_ref_clk_t refClk, uint32_t weight);
+cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
+cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
+cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr);
+
+/* ========================================================================== */
+/* =================== COUNTER FUNCTIONS SECTION ====================== */
+/* ========================================================================== */
+/*******************************************************************************
+* Function Name: Cy_Profile_ClearCounters
+****************************************************************************//**
+*
+* Clears all hardware counters to 0.
+*
+* \funcusage
+* \snippet profile/profile_v1_0_sut_01.cydsn/main_cm4.c snippet_Cy_Profile_ClearCounters
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_Profile_ClearCounters(void)
+{
+ PROFILE->CMD = CY_PROFILE_CLR_ALL_CNT;
+}
+/** \} group_profile_functions_counter */
+
+/**
+* \addtogroup group_profile_functions_calculation
+* \{
+*/
+/* ========================================================================== */
+/* ================== CALCULATION FUNCTIONS SECTION =================== */
+/* ========================================================================== */
+cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result);
+cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result);
+uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[], uint32_t numCounters);
+/** \} group_profile_functions_calculation */
+
+/** \} group_profile_functions */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* CY_PROFILE_H */
+
+/** \} group_profile */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1818 @@
+/***************************************************************************//**
+* \file cy_prot.c
+* \version 1.10
+*
+* \brief
+* Provides an API implementation of the Protection Unit driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_prot.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigBusMaster
+****************************************************************************//**
+*
+* \brief Configures the allowed protection contexts, security (secure/non-secure)
+* and privilege level of the bus transaction created by the specified master.
+*
+* \param busMaster
+* Indicates which master needs to be configured. Refer to the CPUSS_MS_ID_X
+* defines.
+*
+* \param privileged
+* Boolean to define the privilege level of all subsequent bus transfers.
+* True - privileged, False - not privileged.
+* Note that this is an inherited value. If not inherited, then this bit will
+* be used.
+*
+* \param secure
+* Security setting for the master. True - Secure, False - Not secure.
+*
+* \param pcMask
+* This is a 16 bit value of the allowed contexts, it is an OR'ed (|) field of the
+* provided defines in cy_prot.h. For example: (PROT_PC1 | PROT_PC3 | PROT_PC4)
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The function completed successfully
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigBusMaster
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask)
+{
+ cy_en_prot_status_t status;
+ uint32_t regVal;
+ uint32_t * addrMsCtl;
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+
+ addrMsCtl = (uint32_t *)(PROT_BASE + (uint32_t)((uint32_t)busMaster << CY_PROT_MSX_CTL_SHIFT));
+
+ /* Check if PC mask is in supported range */
+ switch (busMaster)
+ {
+ case (CPUSS_MS_ID_CM0):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS0_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_CRYPTO):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS1_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_DW0):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS2_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_DW1):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS3_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_CM4):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS14_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_TC):
+ {
+ status = ((uint32_t)(pcMask & CY_PROT_MS15_PC_LIMIT_MASK) != 0UL) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ default:
+ status = CY_PROT_BAD_PARAM;
+ break;
+ }
+
+ if(status != CY_PROT_BAD_PARAM)
+ {
+ regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure)
+ | _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged)
+ | _VAL2FLD(PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1, pcMask);
+ *addrMsCtl = regVal;
+ status = (*addrMsCtl != regVal) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_SetActivePC
+****************************************************************************//**
+*
+* \brief Sets the current/active protection context of the specified bus master.
+*
+* Allowed PC values are 1-15. If this value is not inherited from another bus
+* master, the value set through this function is used.
+*
+* \param busMaster
+* The bus master to configure. Refer to the CPUSS_MS_ID_X defines.
+*
+* \param pc
+* Active protection context of the specified master. Note that only those
+* protection contexts allowed by the pcMask will take effect.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The function completed successfully
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_SetActivePC
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc)
+{
+ cy_en_prot_status_t status;
+ PROT_MPU_Type* addrMpu;
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+
+ addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]);
+
+ /* Check if PC value is in supported range */
+ switch (busMaster)
+ {
+ case (CPUSS_MS_ID_CM0):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_CRYPTO):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_DW0):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_DW1):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_CM4):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ case (CPUSS_MS_ID_TC):
+ {
+ status = (pc > CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1) ? CY_PROT_BAD_PARAM : CY_PROT_SUCCESS;
+ break;
+ }
+ default:
+ status = CY_PROT_BAD_PARAM;
+ break;
+ }
+
+ if(status != CY_PROT_BAD_PARAM)
+ {
+ addrMpu->MS_CTL = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc) | _VAL2FLD(PROT_MPU_MS_CTL_PC_SAVED, pc);
+ status = (_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL) != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_GetActivePC
+****************************************************************************//**
+*
+* \brief Returns the active protection context of a master.
+*
+* \param busMaster
+* The bus master, whose protection context is being read. Refer to the
+* CPUSS_MS_ID_X defines.
+*
+* \return
+* Active protection context of the master
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_SetActivePC
+*
+*******************************************************************************/
+uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster)
+{
+ PROT_MPU_Type* addrMpu;
+
+ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster));
+
+ addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]);
+
+ return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigMpuStruct
+****************************************************************************//**
+*
+* \brief This function configures a memory protection unit (MPU) struct with its
+* protection attributes.
+*
+* The protection structs act like the gatekeepers for a master's accesses to
+* memory, allowing only the permitted transactions to go through.
+*
+* \param base
+* The base address for the MPU struct being configured.
+*
+* \param config
+* Initialization structure containing all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was configured
+* CY_PROT_FAILURE | Configuration failed due to a protection violation
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_NS, !(config->secure))
+ | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE, config->regionSize);
+ base->ATT = attReg;
+ base->ADDR = addrReg;
+ status = ((base->ADDR != addrReg) || (base->ATT != attReg)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableMpuStruct
+****************************************************************************//**
+*
+* \brief Enables the MPU struct, which allows the MPU protection attributes to
+* take effect.
+*
+* \param base
+* The base address of the MPU struct being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was enabled
+* CY_PROT_FAILURE | The MPU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableMpuStruct
+****************************************************************************//**
+*
+* \brief Disbles the MPU struct, which prevents the MPU protection attributes
+* from taking effect.
+*
+* \param base
+* The base address of the MPU struct being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The MPU struct was disabled
+* CY_PROT_FAILURE | The MPU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableMpuStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigSmpuMasterStruct
+****************************************************************************//**
+*
+* \brief Configures a Shared Memory Protection Unit (SMPU) master protection
+* struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave SMPU struct. Since the
+* memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | SMPU master struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_SMPU_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT1 = attReg;
+ status = ((base->ATT1 & CY_PROT_SMPU_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigSmpuSlaveStruct
+****************************************************************************//**
+*
+* \brief Configures a Shared Memory Protection Unit (SMPU) slave protection
+* struct with its protection attributes.
+*
+* This function configures the slave struct of an SMPU pair, which can protect
+* any memory region in a device from invalid bus master accesses.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | SMPU slave struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ addrReg= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE, config->regionSize)
+ | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH, config->pcMatch);
+ base->ATT0 = attReg;
+ base->ADDR0 = addrReg;
+ status = ((base->ADDR0 != addrReg) || ((base->ATT0 & CY_PROT_SMPU_ATT0_MASK) != attReg))
+ ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableSmpuMasterStruct
+****************************************************************************//**
+*
+* \brief Enables the Master SMPU structure.
+*
+* This is an SMPU master struct enable function. The SMPU protection settings
+* will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableSmpuMasterStruct
+****************************************************************************//**
+*
+* \brief Disables the Master SMPU structure.
+*
+* This is an SMPU master struct disable function. The SMPU protection settings
+* will seize to take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableSmpuMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnableSmpuSlaveStruct
+****************************************************************************//**
+*
+* \brief Enables the Slave SMPU structure.
+*
+* This is an SMPU slave struct enable function. The SMPU protection settings
+* will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnableSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisableSmpuSlaveStruct
+****************************************************************************//**
+*
+* \brief Disables the Slave SMPU structure.
+*
+* This is an SMPU slave struct disable function. The SMPU protection settings
+* will seize to take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisableSmpuSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgMasterStruct
+****************************************************************************//**
+*
+* \brief Configures a Programmable Peripheral Protection Unit (PPU PROG) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU PROG struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU PROG master struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_PR_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_PROG_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT1 = attReg;
+ status = ((base->ATT1 & CY_PROT_PPU_PROG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuProgSlaveStruct
+****************************************************************************//**
+*
+* \brief Configures a Programmable Peripheral Protection Unit (PPU PROG) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU PROG pair, which can
+* protect any peripheral memory region in a device from invalid bus master
+* accesses.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU PROG slave struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t addrReg;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->privPermission));
+ CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ addrReg= _VAL2FLD(PERI_PPU_PR_ADDR0_SUBREGION_DISABLE, config->subregions)
+ | _VAL2FLD(PERI_PPU_PR_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT));
+ attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_REGION_SIZE, config->regionSize)
+ | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_PROG_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT0 = attReg;
+ base->ADDR0 = addrReg;
+ status = ((base->ADDR0 != addrReg) || ((base->ATT0 & CY_PROT_PPU_PROG_ATT0_MASK) != attReg))
+ ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuProgMasterStruct
+****************************************************************************//**
+*
+* \brief Enables the Master PPU PROG structure.
+*
+* This is a PPU PROG master struct enable function. The PPU PROG protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgMasterStruct
+****************************************************************************//**
+*
+* \brief Disables the Master PPU PROG structure.
+*
+* This is a PPU PROG master struct disable function. The PPU PROG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuProgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuProgSlaveStruct
+****************************************************************************//**
+*
+* \brief Enables the Slave PPU PROG structure.
+*
+* This is a PPU PROG slave struct enable function. The PPU PROG protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuProgSlaveStruct
+****************************************************************************//**
+*
+* \brief Disables the Slave PPU PROG structure.
+*
+* This is a PPU PROG slave struct disable function. The PPU PROG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuProgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Group Protection Unit (PPU GR) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU GR struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU GR master struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = (((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK))
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_GR_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_GR_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT1 = attReg;
+ status = ((base->ATT1 & CY_PROT_PPU_GR_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Group Protection Unit (PPU GR) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU GR pair, which can
+* protect an entire peripheral MMIO group from invalid bus master accesses.
+* Refer to the device Technical Reference manual for details on peripheral
+* MMIO grouping and which peripherals belong to which groups.
+*
+* Each fixed PPU GR is devoted to a defined MMIO group. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU GR slave struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = (uint32_t)(((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK))
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_PPU_GR_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_GR_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT0 = attReg;
+ status = ((base->ATT0 & CY_PROT_PPU_GR_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* \brief Enables the Master PPU GR structure.
+*
+* This is a PPU GR master struct enable function. The PPU GR protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedGrMasterStruct
+****************************************************************************//**
+*
+* \brief Disables the Master PPU GR structure.
+*
+* This is a PPU GR master struct disable function. The PPU GR protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedGrMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* \brief Enables the Slave PPU GR structure.
+*
+* This is a PPU GR slave struct enable function. The PPU GR protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedGrSlaveStruct
+****************************************************************************//**
+*
+* \brief Disables the Slave PPU GR structure.
+*
+* This is a PPU GR slave struct disable function. The PPU GR protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedGrSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Slave Protection Unit (PPU SL) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU SL struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU SL master struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_SL_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT1 = attReg;
+ status = ((base->ATT1 & CY_PROT_PPU_SL_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Slave Protection Unit (PPU SL) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU SL pair, which can
+* protect an entire peripheral slave instance from invalid bus master accesses.
+* For example, TCPWM0, TCPWM1, SCB0 and SCB1 etc.
+*
+* Each fixed PPU SL is devoted to a defined peripheral slave. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU SL slave struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_SL_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT0 = attReg;
+ status = ((base->ATT0 & CY_PROT_PPU_SL_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* \brief Enables the Master PPU SL structure.
+*
+* This is a PPU SL master struct enable function. The PPU SL protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedSlMasterStruct
+****************************************************************************//**
+*
+* \brief Disables the Master PPU SL structure.
+*
+* This is a PPU SL master struct disable function. The PPU SL protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedSlMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* \brief Enables the Slave PPU SL structure.
+*
+* This is a PPU SL slave struct enable function. The PPU SL protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedSlSlaveStruct
+****************************************************************************//**
+*
+* \brief Disables the Slave PPU SL structure.
+*
+* This is a PPU SL slave struct disable function. The PPU SL protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedSlSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Region Protection Unit (PPU RG) master
+* protection struct with its protection attributes.
+*
+* This function configures the master struct governing the corresponding slave
+* struct pair. It is a mechanism to protect the slave PPU RG struct. Since
+* the memory location of the slave struct is known, the address, regionSize and
+* subregions of the configuration struct are not applicable.
+*
+* Note that only the user/privileged write permissions are configurable. The
+* read and execute permissions are read-only and cannot be configured.
+*
+* \param base
+* The register base address of the protection struct being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU RG master struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR1 is read only. Only configure ATT1 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only for master structs */
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_RG_ATT1_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT1 = attReg;
+ status = ((base->ATT1 & CY_PROT_PPU_RG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_ConfigPpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* \brief Configures a Fixed Peripheral Region Protection Unit (PPU RG) slave
+* protection struct with its protection attributes.
+*
+* This function configures the slave struct of a PPU RG pair, which can
+* protect specified regions of peripheral instances. For example, individual
+* DW channel structs, SMPU structs, and IPC structs etc.
+*
+* Each fixed PPU RG is devoted to a defined peripheral region. Hence the address,
+* regionSize and subregions of the configuration struct are not applicable.
+*
+* Note that the user/privileged execute accesses are read-only and are always
+* enabled.
+*
+* \param base
+* The register base address of the protection structure being configured.
+*
+* \param config
+* Initialization structure with all the protection attributes.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | PPU RG slave struct was successfully configured
+* CY_PROT_FAILURE | The resource is locked
+* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_ConfigPpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config)
+{
+ cy_en_prot_status_t status;
+ uint32_t attReg;
+
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission));
+ CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission));
+
+ if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL)
+ {
+ /* PC mask out of range - not supported in device */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ /* ADDR0 is read only. Only configure ATT0 */
+ attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)
+ | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT)
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_NS, !(config->secure))
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1, config->pcMask)
+ /* No region size - read only */
+ | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MATCH, config->pcMatch);
+ if ((attReg & CY_PROT_PPU_RG_ATT0_MASK) != attReg)
+ {
+ /* Invalid parameter was passed */
+ status = CY_PROT_BAD_PARAM;
+ }
+ else
+ {
+ base->ATT0 = attReg;
+ status = ((base->ATT0 & CY_PROT_PPU_RG_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS;
+ }
+ }
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* \brief Enables the Master PPU RG structure.
+*
+* This is a PPU RG master struct enable function. The PPU RG protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was enabled
+* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 |= _VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedRgMasterStruct
+****************************************************************************//**
+*
+* \brief Disables the Master PPU RG structure.
+*
+* This is a PPU RG master struct disable function. The PPU RG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Master PU struct was disabled
+* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedRgMasterStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_EnablePpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* \brief Enables the Slave PPU RG structure.
+*
+* This is a PPU RG slave struct enable function. The PPU RG protection
+* settings will take effect after successful completion of this function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was enabled
+* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_EnablePpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Prot_DisablePpuFixedRgSlaveStruct
+****************************************************************************//**
+*
+* \brief Disables the Slave PPU RG structure.
+*
+* This is a PPU RG slave struct disable function. The PPU RG protection
+* settings will seize to take effect after successful completion of this
+* function call.
+*
+* \param base
+* The base address for the protection unit structure being configured.
+*
+* \return
+* Status of the function call.
+*
+* Status | Description
+* ------------ | -----------
+* CY_PROT_SUCCESS | The Slave PU struct was disabled
+* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked
+*
+* \funcusage
+* \snippet prot/prot_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_Prot_DisablePpuFixedRgSlaveStruct
+*
+*******************************************************************************/
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base)
+{
+ cy_en_prot_status_t status;
+
+ base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE);
+ status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ?
+ CY_PROT_FAILURE : CY_PROT_SUCCESS;
+
+ return status;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,893 @@
+/***************************************************************************//**
+* \file cy_prot.h
+* \version 1.10
+*
+* \brief
+* Provides an API declaration of the Protection Unit driver
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_prot Protection Unit (Prot)
+* \{
+*
+* The Protection Unit driver provides an API to configure the Memory Protection
+* Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection
+* Units (PPU). These are separate from the ARM Core MPUs and provide additional
+* mechanisms for securing resource accesses. The Protection units address the
+* following concerns in an embedded design:
+* - <b>Security requirements:</b> This includes the prevention of malicious attacks
+* to access secure memory or peripherals.
+* - <b>Safety requirements:</b> This includes detection of accidental (non-malicious)
+* SW errors and random HW errors. It is important to enable failure analysis
+* to investigate the root cause of a safety violation.
+*
+* \section group_prot_protection_type Protection Types
+*
+* Protection units are hardware configuration structures that control bus accesses
+* to the resources that they protect. By combining these individual configuration
+* structures, a system is built to allow strict restrictions on the capabilities
+* of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes.
+* This architecture can then be integrated into the overall security system
+* of the end application. To build this system, 3 main protection unit types
+* are available; MPU, SMPU and PPU. When a resource is accessed (memory/register),
+* it must pass the evaluation performed for each category. These access evaluations
+* are prioritized, where MPU has the highest priority, followed by SMPU, followed
+* by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is
+* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
+* denial-of-service scenario and the application should pay special attention in
+* taking ownership of the protection unit configurations.
+*
+* \subsection group_prot_memory_protection Memory Protection
+*
+* Memory access control for a bus master is controlled using an MPU. These are
+* most often used to distinguish user and privileged accesses from a single bus
+* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
+* core MPUs are used to perform this task. For other non-ARM bus masters such
+* as Crypto, MPU structs are available, which can be used in a similar manner
+* as the ARM core MPUs. These MPUs however must be configured by the ARM cores.
+* Other bus masters that do not have an MPU, such as DMA (DW), inherit the access
+* control attributes of the bus master that configured the channel. Also note
+* that unlike other protection units, MPUs do not support protection context
+* evaluation. MPU structs have a descending priority, where larger index struct
+* has higher priority access evaluation over lower index structs. E.g. MPU_STRUCT15
+* has higher priority than MPU_STRUCT14 and its access will be evaluated before
+* MPU_STRUCT14. If both target the same memory, then the higher index (MPU_STRUCT15)
+* will be used, and the lower index (MPU_STRUCT14) will be ignored.
+*
+* \subsection group_prot_shared_memory_protection Shared Memory Protection
+*
+* In order to protect a region of memory from all bus masters, an SMPU is used.
+* This protection effectively allows only those with correct bus master access
+* settings to read/write/execute the memory region. This type of protection
+* is used in general memory such as Flash and SRAM. Peripheral registers are
+* best configured using the peripheral protection units instead. SMPU structs
+* have a descending priority, where larger index struct has higher priority
+* access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority
+* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
+* If both target the same memory, then the higher index (MPU_STRUCT15) will be
+* used, and the lower index (SMPU_STRUCT14) will be ignored.
+*
+* \subsection group_prot_peripheral_protection Peripheral Protection
+*
+* Peripheral protection is provided by PPUs and allow control of peripheral
+* register accesses by bus masters. Four types of PPUs are available.
+* - <b>Fixed Group (GR) PPUs</b> are used to protect an entire peripheral MMIO group
+* from invalid bus master accesses. The MMIO grouping information and which
+* resource belongs to which group is device specific and can be obtained
+* from the device technical reference manual (TRM). Group PPUs have the highest
+* priority in the PPU category. Therefore their access evaluations take precedence
+* over the other types of PPUs.
+* - <b>Programmable (PROG) PPUs</b> are used to protect any peripheral memory region
+* in a device from invalid bus master accesses. It is the most versatile
+* type of peripheral protection unit. Programmable PPUs have the second highest
+* priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs,
+* higher index PROG PPUs have higher priority than lower indexes PROG PPUs.
+* - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
+* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
+* SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence
+* over Slave PPUs.
+* - <b>Fixed Slave (SL) PPUs</b> are used to protect specified regions of peripheral
+* instances. For example, individual DW channel structs, SMPU structs, and
+* IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and
+* therefore are evaluated last.
+*
+* \section group_prot_protection_context Protection Context
+*
+* Protection context (PC) attribute is present in all bus masters and is evaluated
+* when accessing memory protected by an SMPU or a PPU. There are no limitations
+* to how the PC values are allocated to the bus masters and this makes it
+* possible for multiple bus masters to essentially share protection context
+* values. The exception to this rule is the PC value 0.
+*
+* \subsection group_prot_pc0 PC=0
+*
+* Protection context 0 is a hardware controlled protection context update
+* mechanism that allows only a single entry point for transitioning into PC=0
+* value. This mechanism is only present for the secure CM0+ core and is a
+* fundamental feature in defining a security solution. While all bus masters
+* are configured to PC=0 at device boot, it is up to the security solution
+* to transition these bus masters to PC!=0 values. Once this is done, those
+* bus masters can no longer revert back to PC=0 and can no longer access
+* resources protected at PC=0.
+*
+* In order to enter PC=0, the CM0+ core must assign an interrupt vector or
+* an exception handler address to the CPUSS.CM0_PC0_HANDLER register. This
+* allows the hardware to check whether the executing code address matches the
+* value in this register. If they match, the current PC value is saved and
+* the CM0+ bus master automatically transitions to PC=0. It is then up to
+* the executing code to decide if and when it will revert to a PC!=0 value.
+* At that point, the only way to re-transition to PC=0 is through the defined
+* exception/interrupt handler.
+*
+* \section group_prot_access_evaluation Access Evaluation
+*
+* Each protection unit is capable of evaluating several access types. These can
+* be used to build a system of logical evaluations for different kinds of
+* bus master modes of operations. These access types can be divided into
+* three broad access categories.
+*
+* - <b>User/Privileged access:</b> The ARM convention of user mode versus privileged
+* mode is applied in the protection units. For ARM cores, switching between
+* user and privileged modes is handled by updating its Control register or
+* by exception entries. Other bus masters such as Crypto have their own
+* user/privileged settings bit in the bus master control register. This is
+* then controlled by the ARM cores. Bus masters that do not have
+* user/privileged access controls, such as DMA, inherit their attributes
+* from the bus master that configured it. The user/privileged distinction
+* is used mainly in the MPUs for single bus master accesses but they can
+* also be used in all other protection units.
+* - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
+* identifier to distinguish between two separate modes of operations. Much
+* like the user/privileged access, the secure/non-secure mode flag is present
+* in the bus master control register. The ARM core does not have this
+* attribute in its control register and must use the bus master control
+* register instead. Bus masters that inherit their attributes, such as DMA,
+* inherit the secure/non-secure attribute. The primary use-case for this
+* access evaluation is to define a region to be secure or non-secure using
+* an SMPU or a PPU. A bus master with a secure attribute can access
+* both secure and non-secure regions, whereas a bus master with non-secure
+* attribute can only access non-secure regions.
+* - <b>Protection Context access:</b> Protection Context is an attribute
+* that serves two purposes; To enter the hardware controlled secure PC=0
+* mode of operation from non-secure modes and to provide finer granularity
+* to the bus master access definitions. It is used in SMPU and PPU configuration
+* to control which bus master protection context can access the resources
+* that they protect.
+*
+* \section group_prot_protection_structure Protection Structure
+*
+* Each protection unit is comprised of a master struct and a slave struct pair.
+* The exception to this rule is MPU structs, which only have the slave struct
+* equivalent. The protection units apply their access evaluations in a decreasing
+* index order. For example, if SMPU1 and SMPU2 both protect a specific memory region,
+* the the higher index (SMPU2) will be evaluated first. In a secure system, the
+* higher index protection structs would then provide the high level of security
+* and the lower indexes would provide the lower level of security. Refer to the
+* \ref group_prot_protection_type section for more information.
+*
+* \subsection group_prot_slave_struct Slave Struct
+*
+* The slave struct is used to configure the protection settings for the resource
+* of interest (memory/registers). Depending on the type of protection unit,
+* the available attributes differ. However all Slave protection units have the
+* following general format.
+*
+* \subsubsection group_prot_slave_addr Slave Struct Address Definition
+*
+* - Address: For MPU, SMPU and PROG PPU, the address field is used to define
+* the base memory region to apply the protection. This field has a dependency
+* on the region size, which dictates the alignment of the protection unit. E.g.
+* if the region size is 64KB, the address field is aligned to 64KB. Hence
+* the lowest bits [15:0] are ignored. For instance, if the address is defined
+* at 0x0800FFFF, the protection unit would apply its protection settings from
+* 0x08000000. Thus alignment must be checked before defining the protection
+* address. The address field for other PPUs are not used, as they are bound
+* to their respective peripheral memory locations.
+* - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define
+* the memory block size to apply the protection settings, starting from the
+* defined base address. It is also used to define the 8 sub-regions for the
+* chosen memory block. E.g. If the region size is 64KB, each subregion would
+* be 8KB. This information can then be used to disable the protection
+* settings for select subregions, which gives finer granularity to the
+* memory regions. PPUs do not have region size definitions as they are bound
+* to their respective peripheral memory locations.
+* - Subregions: The memory block defined by the address and region size fields
+* is divided into 8 (0 to 7) equally spaced subregions. The protection settings
+* of the protection unit can be disabled for these subregions. E.g. for a
+* given 64KB of memory block starting from address 0x08000000, disabling
+* subregion 0 would result in the protection settings not affecting the memory
+* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
+* definitions as they are bound to their respective peripheral memory locations.
+*
+* \subsubsection group_prot_slave_attr Slave Struct Attribute Definition
+*
+* - User Permission: Protection units can control the access restrictions
+* of the read (R), write (W) and execute (X) (subject to their availability
+* depending on the type of protection unit) operations on the memory block
+* when the bus master is operating in user mode. PPU structs do not provide
+* execute attributes.
+* - Privileged Permission: Similar to the user permission, protection units can
+* control the access restrictions of the read (R), write (W) and execute (X)
+* (subject to their availability depending on the type of protection unit)
+* operations on the memory block when the bus master is operating in
+* privileged mode. PPU structs do not provide execute attributes.
+* - Secure/Non-secure: Applies the secure/non-secure protection settings to
+* the defined memory region. Secure protection allows only bus masters that
+* access the memory with secure attribute. Non-secure protection allows
+* bus masters that have either secure or non-secure attributes.
+* - PC match: This attribute allows the protection unit to either apply the
+* 3 access evaluations (user/privileged, secure/non-secure, protection context)
+* or to only provide an address range match. This is useful when multiple
+* protection units protect an overlapping memory region and it's desirable
+* to only have access evaluations applied from only one of these protection
+* units. For example, SMPU1 protects memory A and SMPU2 protects memory B.
+* There exists a region where A and B intersect and this is accessed by a
+* bus master. Both SMPU1 and SMPU2 are configured to operate in "match" mode.
+* In this scenario, the access evaluation will only be applied by the higher
+* index protection unit (i.e. SMPU2) and the access attributes of SMPU1 will
+* be ignored. If the bus master then tries to access a memory region A (that
+* does not intersect with B), the access evaluation from SMPU1 will be used.
+* Note that the PC match functionality is only available in SMPUs.
+* - PC mask: Defines the allowed protection context values that can access the
+* protected memory. The bus master attribute must be operating in one of the
+* protection context values allowed by the protection unit. E.g. If SMPU1 is
+* configured to allow only PC=1 and PC=5, a bus master (such as CM4) must
+* be operating at PC=1 or PC=5 when accessing the protected memory region.
+*
+* \subsection group_prot_master_struct Master Struct
+*
+* The master struct protects its slave struct in the protection unit. This
+* architecture makes possible for the slave configuration to be protected from
+* reconfiguration by an unauthorized bus master. The configuration attributes
+* and the format are similar to that of the slave structs.
+*
+* \subsubsection group_prot_master_addr Master Struct Address Definition
+*
+* - Address: The address definition for master struct is fixed to the slave
+* struct that it protects.
+* - Region Size: The region size is fixed to 256B region.
+* - Subregion: This value is fixed to only enable the first 64B subregions,
+* which applies the protection settings to the entire protection unit.
+*
+* \subsubsection group_prot_master_attr Master Struct Attribute Definition
+*
+* - User Permission: Only the write (W) access attribute is allowed for
+* master structs, which controls whether a bus master operating in user
+* mode has the write access.
+* - Privileged Permission: Only the write (W) access attribute is allowed for
+* master structs, which controls whether a bus master operating in privileged
+* mode has the write access.
+* - Secure/Non-Secure: Same behavior as slave struct.
+* - PC match: Same behavior as slave struct.
+* - PC mask: Same behavior as slave struct.
+*
+* \section group_prot_driver_usage Driver Usage
+*
+* Setting up and using protection units can be summed up in four stages:
+*
+* - Configure the bus master attributes. This defines the capabilities of
+* the bus master when trying to access the protected resources.
+* - Configure the slave struct of a given protection unit. This defines
+* the protection attributes to be applied to the bus master accessing
+* the protected resource and also defines the size and location of the
+* memory block to protect.
+* - Configure the master struct of the protection unit. This defines the
+* attributes to be checked against the bus master that is trying to
+* reconfigure the slave struct.
+* - Set the active PC value of the bus master and place it in the correct
+* mode of operation (user/privileged, secure/non-secure). Then access
+* the protected memory.
+*
+* For example, by configuring the CM0+ bus master configuration to allow
+* only protection contexts 2 and 3, the bus master will be able to
+* set its protection context only to 2 or 3. During runtime, the CM0+ core
+* can set its protection context to 2 by calling Cy_Prot_SetActivePC()
+* and access all regions of protected memory that allow PC=2. A fault will
+* be triggered if a resource is protected with different protection settings.
+*
+* Note that each protection unit is distinguished by its type (e.g.
+* PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be
+* obtained from the device definition header file. Choose a protection unit
+* of interest, and call its corresponding Cy_Prot_Config<X>Struct() function
+* with its software protection unit configuration structure populated. Then
+* enable the protection unit by calling the Cy_Prot_Enable<X>Struct() function.
+*
+* Note that the bus master ID (en_prot_master_t) is defined in the device
+* config header file.
+*
+* \section group_prot_configuration Configuration Considerations
+*
+* When a resource (memory/register) is accessed, it must pass evaluation of
+* all three protection unit categories in the following order: MPU->SMPU->PPU.
+* The application should ensure that a denial-of-service attack cannot be
+* made on the PPU by the SMPU. For this reason, it is recommended that the
+* application's security policy limit the ability for the non-secure client
+* from configuring the SMPUs.
+*
+* Within each category, the priority hierarchy must be carefully considered
+* to ensure that a higher priority protection unit cannot be configured to
+* override the security configuration of a lower index protection unit.
+* Therefore if a lower index protection unit is configured, relevant higher
+* priority indexes should be configured (or protected from unwanted
+* reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that
+* overlaps with the protected registers should also be configured. SImilar
+* to SMPUs, it is recommended that the configuration of PPU_PROG be limited.
+* Otherwise they can be used to override the protection settings of PPU_RG
+* and PPU_SL structs.
+*
+* All bus masters are set to PC=0 value at device reset and therefore have full
+* access to all resources. It is up to the security solution to implement
+* what privileges each bus master has. Once transitioned to a PC!=0 value,
+* only the CM0+ core is capable of re-entering the PC=0 via the user-defined
+* exception entry in the CPUSS.CM0_PC0_HANDLER register.
+*
+* - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at
+* device boot.
+* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
+* device boot.
+* - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot.
+*
+* \section group_prot_more_information More Information
+*
+* Refer to Technical Reference Manual (TRM) and the device datasheet.
+*
+* \section group_prot_MISRA MISRA-C Compliance]
+* The Prot driver does not have any driver-specific deviations.
+*
+* \section group_prot_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="2">1.10</td>
+* <td>Added input parameter validation to the API functions.<br>
+* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
+* types are set to typedef enum</td>
+* <td>Improved debugging capability</td>
+* </tr>
+* <tr>
+* <td>Expanded documentation</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_prot_macros Macros
+* \defgroup group_prot_functions Functions
+* \{
+* \defgroup group_prot_functions_busmaster Bus Master and PC Functions
+* \defgroup group_prot_functions_mpu MPU Functions
+* \defgroup group_prot_functions_smpu SMPU Functions
+* \defgroup group_prot_functions_ppu_prog PPU Programmable (PROG) Functions
+* \defgroup group_prot_functions_ppu_gr PPU Group (GR) Functions
+* \defgroup group_prot_functions_ppu_sl PPU Slave (SL) Functions
+* \defgroup group_prot_functions_ppu_rg PPU Region (RG) Functions
+* \}
+* \defgroup group_prot_data_structures Data Structures
+* \defgroup group_prot_enums Enumerated Types
+*/
+
+#if !defined(__CY_PROT_H__)
+#define __CY_PROT_H__
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_prot_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_PROT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_PROT_DRV_VERSION_MINOR 10
+
+/** Prot driver ID */
+#define CY_PROT_ID CY_PDL_DRV_ID(0x30u)
+
+/** \} group_prot_macros */
+
+/**
+* \addtogroup group_prot_enums
+* \{
+*/
+
+/**
+* Prot Driver error codes
+*/
+typedef enum
+{
+ CY_PROT_SUCCESS = 0x00u, /**< Returned successful */
+ CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
+ CY_PROT_FAILURE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x03u /**< The resource is locked */
+} cy_en_prot_status_t;
+
+/**
+* User/Privileged permission
+*/
+typedef enum
+{
+ CY_PROT_PERM_DISABLED = 0x00u, /**< Read, Write and Execute disabled */
+ CY_PROT_PERM_R = 0x01u, /**< Read enabled */
+ CY_PROT_PERM_W = 0x02u, /**< Write enabled */
+ CY_PROT_PERM_RW = 0x03u, /**< Read and Write enabled */
+ CY_PROT_PERM_X = 0x04u, /**< Execute enabled */
+ CY_PROT_PERM_RX = 0x05u, /**< Read and Execute enabled */
+ CY_PROT_PERM_WX = 0x06u, /**< Write and Execute enabled */
+ CY_PROT_PERM_RWX = 0x07u /**< Read, Write and Execute enabled */
+}cy_en_prot_perm_t;
+
+/**
+* Memory region size
+*/
+typedef enum
+{
+ CY_PROT_SIZE_256B = 7u, /**< 256 bytes */
+ CY_PROT_SIZE_512B = 8u, /**< 512 bytes */
+ CY_PROT_SIZE_1KB = 9u, /**< 1 Kilobyte */
+ CY_PROT_SIZE_2KB = 10u, /**< 2 Kilobytes */
+ CY_PROT_SIZE_4KB = 11u, /**< 4 Kilobytes */
+ CY_PROT_SIZE_8KB = 12u, /**< 8 Kilobytes */
+ CY_PROT_SIZE_16KB = 13u, /**< 16 Kilobytes */
+ CY_PROT_SIZE_32KB = 14u, /**< 32 Kilobytes */
+ CY_PROT_SIZE_64KB = 15u, /**< 64 Kilobytes */
+ CY_PROT_SIZE_128KB = 16u, /**< 128 Kilobytes */
+ CY_PROT_SIZE_256KB = 17u, /**< 256 Kilobytes */
+ CY_PROT_SIZE_512KB = 18u, /**< 512 Kilobytes */
+ CY_PROT_SIZE_1MB = 19u, /**< 1 Megabyte */
+ CY_PROT_SIZE_2MB = 20u, /**< 2 Megabytes */
+ CY_PROT_SIZE_4MB = 21u, /**< 4 Megabytes */
+ CY_PROT_SIZE_8MB = 22u, /**< 8 Megabytes */
+ CY_PROT_SIZE_16MB = 23u, /**< 16 Megabytes */
+ CY_PROT_SIZE_32MB = 24u, /**< 32 Megabytes */
+ CY_PROT_SIZE_64MB = 25u, /**< 64 Megabytes */
+ CY_PROT_SIZE_128MB = 26u, /**< 128 Megabytes */
+ CY_PROT_SIZE_256MB = 27u, /**< 256 Megabytes */
+ CY_PROT_SIZE_512MB = 28u, /**< 512 Megabytes */
+ CY_PROT_SIZE_1GB = 29u, /**< 1 Gigabyte */
+ CY_PROT_SIZE_2GB = 30u, /**< 2 Gigabytes */
+ CY_PROT_SIZE_4GB = 31u /**< 4 Gigabytes */
+}cy_en_prot_size_t;
+
+/**
+* Protection Context (PC)
+*/
+enum cy_en_prot_pc_t
+{
+ CY_PROT_PC1 = 1u, /**< PC = 1 */
+ CY_PROT_PC2 = 2u, /**< PC = 2 */
+ CY_PROT_PC3 = 3u, /**< PC = 3 */
+ CY_PROT_PC4 = 4u, /**< PC = 4 */
+ CY_PROT_PC5 = 5u, /**< PC = 5 */
+ CY_PROT_PC6 = 6u, /**< PC = 6 */
+ CY_PROT_PC7 = 7u, /**< PC = 7 */
+ CY_PROT_PC8 = 8u, /**< PC = 8 */
+ CY_PROT_PC9 = 9u, /**< PC = 9 */
+ CY_PROT_PC10 = 10u, /**< PC = 10 */
+ CY_PROT_PC11 = 11u, /**< PC = 11 */
+ CY_PROT_PC12 = 12u, /**< PC = 12 */
+ CY_PROT_PC13 = 13u, /**< PC = 13 */
+ CY_PROT_PC14 = 14u, /**< PC = 14 */
+ CY_PROT_PC15 = 15u /**< PC = 15 */
+};
+
+/**
+* Subregion disable (0-7)
+*/
+enum cy_en_prot_subreg_t
+{
+ CY_PROT_SUBREGION_DIS0 = 0x01u, /**< Disable subregion 0 */
+ CY_PROT_SUBREGION_DIS1 = 0x02u, /**< Disable subregion 1 */
+ CY_PROT_SUBREGION_DIS2 = 0x04u, /**< Disable subregion 2 */
+ CY_PROT_SUBREGION_DIS3 = 0x08u, /**< Disable subregion 3 */
+ CY_PROT_SUBREGION_DIS4 = 0x10u, /**< Disable subregion 4 */
+ CY_PROT_SUBREGION_DIS5 = 0x20u, /**< Disable subregion 5 */
+ CY_PROT_SUBREGION_DIS6 = 0x40u, /**< Disable subregion 6 */
+ CY_PROT_SUBREGION_DIS7 = 0x80u /**< Disable subregion 7 */
+};
+
+/**
+* Protection context mask (PC_MASK)
+*/
+enum cy_en_prot_pcmask_t
+{
+ CY_PROT_PCMASK1 = 0x0001u, /**< Mask to allow PC = 1 */
+ CY_PROT_PCMASK2 = 0x0002u, /**< Mask to allow PC = 2 */
+ CY_PROT_PCMASK3 = 0x0004u, /**< Mask to allow PC = 3 */
+ CY_PROT_PCMASK4 = 0x0008u, /**< Mask to allow PC = 4 */
+ CY_PROT_PCMASK5 = 0x0010u, /**< Mask to allow PC = 5 */
+ CY_PROT_PCMASK6 = 0x0020u, /**< Mask to allow PC = 6 */
+ CY_PROT_PCMASK7 = 0x0040u, /**< Mask to allow PC = 7 */
+ CY_PROT_PCMASK8 = 0x0080u, /**< Mask to allow PC = 8 */
+ CY_PROT_PCMASK9 = 0x0100u, /**< Mask to allow PC = 9 */
+ CY_PROT_PCMASK10 = 0x0200u, /**< Mask to allow PC = 10 */
+ CY_PROT_PCMASK11 = 0x0400u, /**< Mask to allow PC = 11 */
+ CY_PROT_PCMASK12 = 0x0800u, /**< Mask to allow PC = 12 */
+ CY_PROT_PCMASK13 = 0x1000u, /**< Mask to allow PC = 13 */
+ CY_PROT_PCMASK14 = 0x2000u, /**< Mask to allow PC = 14 */
+ CY_PROT_PCMASK15 = 0x4000u /**< Mask to allow PC = 15 */
+};
+
+/** \} group_prot_enums */
+
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* Helper function for finding max */
+#define CY_PROT_MAX(x,y) (((x)>(y))?(x):(y))
+
+/* General Masks and shifts */
+#define CY_PROT_MSX_CTL_SHIFT (0x02UL) /**< Shift for MSx_CTL register */
+#define CY_PROT_STRUCT_ENABLE (0x01UL) /**< Enable protection unit struct */
+#define CY_PROT_ADDR_SHIFT (8UL) /**< Address shift for MPU, SMPU and PROG PPU structs */
+
+/* Permission masks and shifts */
+#define CY_PROT_ATT_PERMISSION_MASK (0x07UL) /**< Protection Unit attribute permission mask */
+#define CY_PROT_ATT_USER_PERMISSION_SHIFT (0x00UL) /**< Protection Unit user attribute permission shift */
+#define CY_PROT_ATT_PRIV_PERMISSION_SHIFT (0x03UL) /**< Protection Unit priliged attribute permission shift */
+
+/* Maximum Master Protection Context */
+#define CY_PROT_MS_PC_NR_MAX CY_PROT_MAX(CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1, \
+ CY_PROT_MAX(CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1, \
+ CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1)))))))))))))))
+
+/* Protection Context limit masks */
+#define CY_PROT_MS0_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1)
+#define CY_PROT_MS1_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1)
+#define CY_PROT_MS2_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1)
+#define CY_PROT_MS3_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1)
+#define CY_PROT_MS4_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1)
+#define CY_PROT_MS5_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1)
+#define CY_PROT_MS6_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1)
+#define CY_PROT_MS7_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1)
+#define CY_PROT_MS8_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1)
+#define CY_PROT_MS9_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1)
+#define CY_PROT_MS10_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1)
+#define CY_PROT_MS11_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1)
+#define CY_PROT_MS12_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1)
+#define CY_PROT_MS13_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1)
+#define CY_PROT_MS14_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1)
+#define CY_PROT_MS15_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1)
+
+#define CY_PROT_MPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CY_PROT_MS_PC_NR_MAX)
+#define CY_PROT_SMPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_SMPU_STRUCT_PC_NR_MINUS1)
+#define CY_PROT_PPU_PROG_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_PROG_STRUCT_PC_NR_MINUS1)
+#define CY_PROT_PPU_FIXED_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1)
+
+/* Parameter validation masks to check for read-only values */
+#define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk))
+#define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk \
+ | PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_PROG_ATT0_MASK ((uint32_t)~(PERI_PPU_PR_ATT0_UX_Msk \
+ | PERI_PPU_PR_ATT0_PX_Msk \
+ | PERI_PPU_PR_ATT0_PC_MASK_0_Msk \
+ ))
+#define CY_PROT_PPU_PROG_ATT1_MASK ((uint32_t)~(PERI_PPU_PR_ATT1_UX_Msk \
+ | PERI_PPU_PR_ATT1_PX_Msk \
+ | PERI_PPU_PR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_PR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_GR_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_GR_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_SL_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_SL_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_RG_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
+ | PERI_PPU_GR_ATT0_PX_Msk \
+ | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
+ ))
+#define CY_PROT_PPU_RG_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
+ | PERI_PPU_GR_ATT1_PX_Msk \
+ | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
+ | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
+ ))
+
+/* Parameter check macros */
+#define CY_PROT_BUS_MASTER_MAX (16UL)
+#define CY_PROT_IS_BUS_MASTER_VALID(busMaster) (CY_PROT_BUS_MASTER_MAX > ((uint32_t)(busMaster)))
+
+#define CY_PROT_IS_MPU_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW) || \
+ ((permission) == CY_PROT_PERM_X) || \
+ ((permission) == CY_PROT_PERM_RX) || \
+ ((permission) == CY_PROT_PERM_WX) || \
+ ((permission) == CY_PROT_PERM_RWX))
+
+#define CY_PROT_IS_SMPU_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_SMPU_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW) || \
+ ((permission) == CY_PROT_PERM_X) || \
+ ((permission) == CY_PROT_PERM_RX) || \
+ ((permission) == CY_PROT_PERM_WX) || \
+ ((permission) == CY_PROT_PERM_RWX))
+
+#define CY_PROT_IS_PROG_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_PROG_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_FIXED_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_FIXED_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
+ ((permission) == CY_PROT_PERM_R) || \
+ ((permission) == CY_PROT_PERM_W) || \
+ ((permission) == CY_PROT_PERM_RW))
+
+#define CY_PROT_IS_REGION_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_256B) || \
+ ((regionSize) == CY_PROT_SIZE_512B) || \
+ ((regionSize) == CY_PROT_SIZE_1KB) || \
+ ((regionSize) == CY_PROT_SIZE_2KB) || \
+ ((regionSize) == CY_PROT_SIZE_4KB) || \
+ ((regionSize) == CY_PROT_SIZE_8KB) || \
+ ((regionSize) == CY_PROT_SIZE_16KB) || \
+ ((regionSize) == CY_PROT_SIZE_32KB) || \
+ ((regionSize) == CY_PROT_SIZE_64KB) || \
+ ((regionSize) == CY_PROT_SIZE_128KB) || \
+ ((regionSize) == CY_PROT_SIZE_256KB) || \
+ ((regionSize) == CY_PROT_SIZE_512KB) || \
+ ((regionSize) == CY_PROT_SIZE_1MB) || \
+ ((regionSize) == CY_PROT_SIZE_2MB) || \
+ ((regionSize) == CY_PROT_SIZE_4MB) || \
+ ((regionSize) == CY_PROT_SIZE_8MB) || \
+ ((regionSize) == CY_PROT_SIZE_16MB) || \
+ ((regionSize) == CY_PROT_SIZE_32MB) || \
+ ((regionSize) == CY_PROT_SIZE_64MB) || \
+ ((regionSize) == CY_PROT_SIZE_128MB) || \
+ ((regionSize) == CY_PROT_SIZE_256MB) || \
+ ((regionSize) == CY_PROT_SIZE_512MB) || \
+ ((regionSize) == CY_PROT_SIZE_1GB) || \
+ ((regionSize) == CY_PROT_SIZE_2GB) || \
+ ((regionSize) == CY_PROT_SIZE_4GB))
+
+/** \endcond */
+
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/**
+* \addtogroup group_prot_data_structures
+* \{
+*/
+
+/** Configuration structure for MPU Struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+} cy_stc_mpu_cfg_t;
+
+/** Configuration structure for SMPU struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_smpu_cfg_t;
+
+/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
+typedef struct
+{
+ uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
+ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
+ uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_prog_cfg_t;
+
+/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_gr_cfg_t;
+
+/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_sl_cfg_t;
+
+/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
+typedef struct
+{
+ cy_en_prot_perm_t userPermission; /**< User permissions for the region */
+ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
+ bool secure; /**< Non Secure = 0, Secure = 1 */
+ bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
+ uint16_t pcMask; /**< Mask of allowed protection context(s) */
+} cy_stc_ppu_rg_cfg_t;
+
+/** \} group_prot_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_prot_functions
+* \{
+*/
+
+/**
+* \addtogroup group_prot_functions_busmaster
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask);
+cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc);
+uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster);
+
+/** \} group_prot_functions_busmaster */
+
+/**
+* \addtogroup group_prot_functions_mpu
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
+
+/** \} group_prot_functions_mpu */
+
+/**
+* \addtogroup group_prot_functions_smpu
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
+
+/** \} group_prot_functions_smpu */
+
+/**
+* \addtogroup group_prot_functions_ppu_prog
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
+
+/** \} group_prot_functions_ppu_prog */
+
+/**
+* \addtogroup group_prot_functions_ppu_gr
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
+
+/** \} group_prot_functions_ppu_gr */
+
+/**
+* \addtogroup group_prot_functions_ppu_sl
+* \{
+*/
+
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
+
+/** \} group_prot_functions_ppu_sl */
+
+/**
+* \addtogroup group_prot_functions_ppu_rg
+* \{
+*/
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
+cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
+
+/** \} group_prot_functions_ppu_rg */
+
+/** \} group_prot_functions */
+
+/** \} group_prot */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_PROT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1700 @@
+/***************************************************************************//**
+* \file cy_rtc.c
+* \version 2.10
+*
+* This file provides constants and parameter values for the APIs for the
+* Real-Time Clock (RTC).
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_rtc.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** RTC days in months table */
+uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR] = {CY_RTC_DAYS_IN_JANUARY,
+ CY_RTC_DAYS_IN_FEBRUARY,
+ CY_RTC_DAYS_IN_MARCH,
+ CY_RTC_DAYS_IN_APRIL,
+ CY_RTC_DAYS_IN_MAY,
+ CY_RTC_DAYS_IN_JUNE,
+ CY_RTC_DAYS_IN_JULY,
+ CY_RTC_DAYS_IN_AUGUST,
+ CY_RTC_DAYS_IN_SEPTEMBER,
+ CY_RTC_DAYS_IN_OCTOBER,
+ CY_RTC_DAYS_IN_NOVEMBER,
+ CY_RTC_DAYS_IN_DECEMBER};
+
+/* Static functions */
+static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *timeBcd, uint32_t *dateBcd);
+static void ConstructAlarmTimeDate(cy_stc_rtc_alarm_t const *alarmDateTime, uint32_t *alarmTimeBcd,
+ uint32_t *alarmDateBcd);
+static uint32_t RelativeToFixed(cy_stc_rtc_dst_format_t const *convertDst);
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_Init
+****************************************************************************//**
+*
+* Initializes the RTC driver.
+*
+* \param *config
+* The pointer to the RTC configuration structure, see \ref cy_stc_rtc_config_t.
+*
+* \return
+* cy_en_rtc_status_t *config checking result. If the pointer is NULL,
+* returns an error.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config)
+{
+ return(Cy_RTC_SetDateAndTime(config));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetDateAndTime
+****************************************************************************//**
+*
+* Sets the time and date values into the RTC_TIME and RTC_DATE registers.
+*
+* \param dateTime
+* The pointer to the RTC configuration structure, see \ref cy_stc_rtc_config_t.
+*
+* \return
+* cy_en_rtc_status_t A validation check result of date and month. Returns an
+* error, if the date range is invalid.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ if (NULL != dateTime)
+ {
+ uint32_t tmpDaysInMonth;
+
+ CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(dateTime->sec));
+ CY_ASSERT_L3(CY_RTC_IS_MIN_VALID(dateTime->min));
+ CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(dateTime->hour));
+ CY_ASSERT_L3(CY_RTC_IS_DOW_VALID(dateTime->dayOfWeek));
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(dateTime->month));
+ CY_ASSERT_L3(CY_RTC_IS_YEAR_SHORT_VALID(dateTime->year));
+
+ /* Check dateTime->date input */
+ tmpDaysInMonth = Cy_RTC_DaysInMonth(dateTime->month, (dateTime->year + CY_RTC_TWO_THOUSAND_YEARS));
+
+ if ((dateTime->date > 0U) && (dateTime->date <= tmpDaysInMonth))
+ {
+ uint32_t interruptState;
+ uint32_t tmpTime;
+ uint32_t tmpDate;
+
+ ConstructTimeDate(dateTime, &tmpTime, &tmpDate);
+
+ /* The RTC AHB registers can be updated only under condition that the
+ * Write bit is set and the RTC busy bit is cleared (CY_RTC_BUSY = 0).
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED);
+ if(retVal == CY_RTC_SUCCESS)
+ {
+ BACKUP->RTC_TIME = tmpTime;
+ BACKUP->RTC_DATE = tmpDate;
+
+ /* Clear the RTC Write bit to finish RTC register update */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED);
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetDateAndTime
+****************************************************************************//**
+*
+* Gets the current RTC time and date. The AHB RTC Time and Date register values
+* are stored into the *dateTime structure.
+*
+* \param dateTime
+* The RTC time and date structure. See \ref group_rtc_data_structures.
+*
+*******************************************************************************/
+void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t* dateTime)
+{
+ uint32_t tmpTime;
+ uint32_t tmpDate;
+
+ CY_ASSERT_L1(NULL != dateTime);
+
+ /* Read the current RTC time and date to validate the input parameters */
+ Cy_RTC_SyncFromRtc();
+
+ /* Write the AHB RTC registers date and time into the local variables and
+ * updating the dateTime structure elements
+ */
+ tmpTime = BACKUP->RTC_TIME;
+ tmpDate = BACKUP->RTC_DATE;
+
+ dateTime->sec = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_SEC, tmpTime));
+ dateTime->min = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_MIN, tmpTime));
+ dateTime->hrFormat = ((_FLD2BOOL(BACKUP_RTC_TIME_CTRL_12HR, tmpTime)) ? CY_RTC_12_HOURS : CY_RTC_24_HOURS);
+
+ /* Read the current hour mode to know how many hour bits should be converted
+ * In the 24-hour mode, the hour value is presented in [21:16] bits in the
+ * BCD format.
+ * In the 12-hour mode the hour value is presented in [20:16] bits in the BCD
+ * format and bit [21] is present: 0 - AM; 1 - PM.
+ */
+ if (dateTime->hrFormat != CY_RTC_24_HOURS)
+ {
+ dateTime->hour =
+ Cy_RTC_ConvertBcdToDec((tmpTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) >> BACKUP_RTC_TIME_RTC_HOUR_Pos);
+
+ dateTime->amPm = ((0U != (tmpTime & CY_RTC_BACKUP_RTC_TIME_RTC_PM)) ? CY_RTC_PM : CY_RTC_AM);
+ }
+ else
+ {
+ dateTime->hour = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR, tmpTime));
+ }
+ dateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_DAY, tmpTime));
+
+ dateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_DATE, tmpDate));
+ dateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_MON, tmpDate));
+ dateTime->year = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, tmpDate));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetAlarmDateAndTime
+****************************************************************************//**
+*
+* Sets alarm time and date values into the ALMx_TIME and ALMx_DATE registers.
+*
+* \param alarmDateTime
+* The alarm configuration structure, see \ref cy_stc_rtc_alarm_t.
+*
+* \param alarmIndex
+* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
+*
+* \return
+* cy_en_rtc_status_t A validation check result of date and month. Returns an
+* error, if the date range is invalid.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDateTime, cy_en_rtc_alarm_t alarmIndex)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ if (NULL != alarmDateTime)
+ {
+ uint32_t tmpYear;
+ uint32_t tmpDaysInMonth;
+
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
+
+ CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(alarmDateTime->sec));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->secEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_MIN_VALID(alarmDateTime->min));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->minEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(alarmDateTime->hour));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->hourEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_DOW_VALID(alarmDateTime->dayOfWeek));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->dayOfWeekEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(alarmDateTime->month));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->monthEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->dateEn));
+
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_EN_VALID(alarmDateTime->almEn));
+
+ /* Read the current RTC year to validate alarmDateTime->date */
+ Cy_RTC_SyncFromRtc();
+
+ tmpYear =
+ CY_RTC_TWO_THOUSAND_YEARS + Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, BACKUP->RTC_DATE));
+
+ tmpDaysInMonth = Cy_RTC_DaysInMonth(alarmDateTime->month, tmpYear);
+
+ if ((alarmDateTime->date > 0U) && (alarmDateTime->date <= tmpDaysInMonth))
+ {
+ uint32_t interruptState;
+ uint32_t tmpAlarmTime;
+ uint32_t tmpAlarmDate;
+
+ ConstructAlarmTimeDate(alarmDateTime, &tmpAlarmTime, &tmpAlarmDate);
+
+ /* The RTC AHB registers can be updated only under condition that the
+ * Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0).
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED);
+ if (CY_RTC_SUCCESS == retVal)
+ {
+ /* Update the AHB RTC registers with formed values */
+ if (alarmIndex != CY_RTC_ALARM_2)
+ {
+ BACKUP->ALM1_TIME = tmpAlarmTime;
+ BACKUP->ALM1_DATE = tmpAlarmDate;
+ }
+ else
+ {
+ BACKUP->ALM2_TIME = tmpAlarmTime;
+ BACKUP->ALM2_DATE = tmpAlarmDate;
+ }
+
+ /* Clear the RTC Write bit to finish RTC update */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED);
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ }
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetAlarmDateAndTime
+****************************************************************************//**
+*
+* Returns the current alarm time and date values from the ALMx_TIME and
+* ALMx_DATE registers.
+*
+* \param alarmDateTime
+* The alarm configuration structure, see \ref cy_stc_rtc_alarm_t.
+*
+* \param alarmIndex
+* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
+*
+*******************************************************************************/
+void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_alarm_t alarmIndex)
+{
+ uint32_t tmpAlarmTime;
+ uint32_t tmpAlarmDate;
+ cy_en_rtc_hours_format_t curHoursFormat;
+
+ CY_ASSERT_L1(NULL != alarmDateTime);
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
+
+ /* Read the current RTC time and date to validate the input parameters */
+ Cy_RTC_SyncFromRtc();
+
+ curHoursFormat = Cy_RTC_GetHoursFormat();
+
+ /* Write the AHB RTC registers into the local variables and update the
+ * alarmDateTime structure elements
+ */
+ if (alarmIndex != CY_RTC_ALARM_2)
+ {
+ tmpAlarmTime = BACKUP->ALM1_TIME;
+ tmpAlarmDate = BACKUP->ALM1_DATE;
+
+ alarmDateTime->sec = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_SEC, tmpAlarmTime));
+ alarmDateTime->secEn =
+ ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_SEC_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->min = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_MIN, tmpAlarmTime));
+ alarmDateTime->minEn =
+ ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_MIN_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ /* Read the current hour mode to know how many hour bits to convert.
+ * In the 24-hour mode, the hour value is presented in [21:16] bits in
+ * the BCD format.
+ * In the 12-hour mode, the hour value is presented in [20:16] bits in
+ * the BCD format and bit [21] is present: 0 - AM; 1 - PM.
+ */
+ if (curHoursFormat != CY_RTC_24_HOURS)
+ {
+ alarmDateTime->hour =
+ Cy_RTC_ConvertBcdToDec((tmpAlarmTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR)
+ >> BACKUP_ALM1_TIME_ALM_HOUR_Pos);
+
+ /* In the structure, the hour value should be presented in the 24-hour mode. In
+ * that condition the firmware checks the AM/PM status and adds 12 hours to
+ * the converted hour value if the PM bit is set.
+ */
+ if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) &&
+ (0U != (BACKUP->ALM1_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ alarmDateTime->hour += CY_RTC_HOURS_PER_HALF_DAY;
+ }
+
+ /* Set zero hour, as the 12 A hour is zero hour in 24-hour format */
+ if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) &&
+ (0U == (BACKUP->ALM1_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ alarmDateTime->hour = 0U;
+ }
+
+ }
+ else
+ {
+ alarmDateTime->hour = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_HOUR, tmpAlarmTime));
+ }
+ alarmDateTime->hourEn =
+ ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_HOUR_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_DAY, tmpAlarmTime));
+ alarmDateTime->dayOfWeekEn =
+ ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_DAY_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_DATE_ALM_DATE, tmpAlarmDate));
+ alarmDateTime->dateEn =
+ ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_DATE_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_DATE_ALM_MON, tmpAlarmDate));
+ alarmDateTime->monthEn =
+ ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_MON_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->almEn =
+ ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+ }
+ else
+ {
+ tmpAlarmTime = BACKUP->ALM2_TIME;
+ tmpAlarmDate = BACKUP->ALM2_DATE;
+
+ alarmDateTime->sec = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_SEC, tmpAlarmTime));
+ alarmDateTime->secEn =
+ ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_SEC_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->min = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_MIN, tmpAlarmTime));
+ alarmDateTime->minEn =
+ ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_MIN_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ /* Read the current hour mode to know how many hour bits to convert.
+ * In the 24-hour mode, the hour value is presented in [21:16] bits in
+ * the BCD format.
+ * In the 12-hour mode the hour value is presented in [20:16] bits in
+ * the BCD format and bit [21] is present: 0 - AM; 1 - PM.
+ */
+ if (curHoursFormat != CY_RTC_24_HOURS)
+ {
+ alarmDateTime->hour = Cy_RTC_ConvertBcdToDec((tmpAlarmTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) >>
+ BACKUP_ALM2_TIME_ALM_HOUR_Pos);
+
+ /* In the structure, the hour value should be presented in the 24-hour mode. In
+ * that condition the firmware checks the AM/PM status and adds 12 hours to
+ * the converted hour value if the PM bit is set.
+ */
+ if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) &&
+ (0U != (BACKUP->ALM2_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ alarmDateTime->hour += CY_RTC_HOURS_PER_HALF_DAY;
+ }
+ /* Set zero hour, as the 12 am hour is zero hour in 24-hour format */
+ else if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) &&
+ (0U == (BACKUP->ALM2_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ alarmDateTime->hour = 0U;
+ }
+ else
+ {
+ /* No corrections are required */
+ }
+ }
+ else
+ {
+ alarmDateTime->hour = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_HOUR, tmpAlarmTime));
+ }
+ alarmDateTime->hourEn =
+ ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_HOUR_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_DAY, tmpAlarmTime));
+ alarmDateTime->dayOfWeekEn =
+ ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_DAY_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_DATE_ALM_DATE, tmpAlarmDate));
+ alarmDateTime->dateEn =
+ ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_DATE_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_DATE_ALM_MON, tmpAlarmDate));
+ alarmDateTime->monthEn =
+ ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_MON_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+
+ alarmDateTime->almEn =
+ ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetDateAndTimeDirect
+****************************************************************************//**
+*
+* Sets the time and date values into the RTC_TIME and RTC_DATE registers using
+* direct time parameters.
+*
+* \param sec The second valid range is [0-59].
+*
+* \param min The minute valid range is [0-59].
+*
+* \param hour
+* The hour valid range is [0-23]. This parameter should be presented in the
+* 24-hour format.
+*
+* The function reads the current 12/24-hour mode, then converts the hour value
+* properly as the mode.
+*
+* \param date
+* The date valid range is [1-31], if the month of February is
+* selected as the Month parameter, then the valid range is [0-29].
+*
+* \param month The month valid range is [1-12].
+*
+* \param year The year valid range is [0-99].
+*
+* \return
+* cy_en_rtc_status_t A validation check result of date and month. Returns an
+* error, if the date range is invalid or the RTC time and date set was
+* cancelled: the RTC Write bit was not set, the RTC was synchronizing.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, uint32_t year)
+{
+ uint32_t tmpDaysInMonth;
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(sec));
+ CY_ASSERT_L3(CY_RTC_IS_MIN_VALID(min));
+ CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(hour));
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L3(CY_RTC_IS_YEAR_SHORT_VALID(year));
+
+ /* Check date input */
+ tmpDaysInMonth = Cy_RTC_DaysInMonth(month, (year + CY_RTC_TWO_THOUSAND_YEARS));
+
+ if ((date > 0U) && (date <= tmpDaysInMonth))
+ {
+ cy_stc_rtc_config_t curTimeAndDate;
+ uint32_t tmpTime;
+ uint32_t tmpDate;
+ uint32_t interruptState;
+
+ /* Fill the date and time structure */
+ curTimeAndDate.sec = sec;
+ curTimeAndDate.min = min;
+
+ /* Read the current hour mode */
+ Cy_RTC_SyncFromRtc();
+
+ if (CY_RTC_12_HOURS != Cy_RTC_GetHoursFormat())
+ {
+ curTimeAndDate.hrFormat = CY_RTC_24_HOURS;
+ curTimeAndDate.hour = hour;
+ }
+ else
+ {
+ curTimeAndDate.hrFormat = CY_RTC_12_HOURS;
+
+ /* Convert the 24-hour format input value into the 12-hour format */
+ if (hour >= CY_RTC_HOURS_PER_HALF_DAY)
+ {
+ /* The current hour is more than 12 or equal 12, in the 24-hour
+ * format. Set the PM bit and convert the hour: hour = hour - 12,
+ * except that the hour is 12.
+ */
+ curTimeAndDate.hour =
+ (hour > CY_RTC_HOURS_PER_HALF_DAY) ? ((uint32_t) hour - CY_RTC_HOURS_PER_HALF_DAY) : hour;
+
+ curTimeAndDate.amPm = CY_RTC_PM;
+ }
+ else
+ {
+ /* The current hour is less than 12 AM. The zero hour is equal
+ * to 12:00 AM
+ */
+ curTimeAndDate.hour = ((hour == 0U) ? CY_RTC_HOURS_PER_HALF_DAY : hour);
+ curTimeAndDate.amPm = CY_RTC_AM;
+ }
+ }
+ curTimeAndDate.dayOfWeek = Cy_RTC_ConvertDayOfWeek(date, month, (year + CY_RTC_TWO_THOUSAND_YEARS));
+ curTimeAndDate.date = date;
+ curTimeAndDate.month = month;
+ curTimeAndDate.year = year;
+
+ ConstructTimeDate(&curTimeAndDate, &tmpTime, &tmpDate);
+
+ /* The RTC AHB register can be updated only under condition that the
+ * Write bit is set and the RTC busy bit is cleared (CY_RTC_BUSY = 0).
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED);
+ if(retVal == CY_RTC_SUCCESS)
+ {
+ BACKUP->RTC_TIME = tmpTime;
+ BACKUP->RTC_DATE = tmpDate;
+
+ /* Clear the RTC Write bit to finish RTC register update */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED);
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetAlarmDateAndTimeDirect
+****************************************************************************//**
+*
+* Sets alarm time and date values into the ALMx_TIME and ALMx_DATE
+* registers using direct time parameters. ALM_DAY_EN is default 0 (=ignore) for
+* this function.
+*
+* \param sec The alarm second valid range is [0-59].
+*
+* \param min The alarm minute valid range is [0-59].
+*
+* \param hour
+* The valid range is [0-23].
+* This parameter type is always in the 24-hour type. This function reads the
+* current 12/24-hour mode, then converts the hour value properly as the mode.
+*
+* \param date
+* The valid range is [1-31], if the month of February is selected as
+* the Month parameter, then the valid range is [0-29].
+*
+* \param month The alarm month valid range is [1-12].
+*
+* \param alarmIndex
+* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
+*
+* \return
+* cy_en_rtc_status_t A validation check result of date and month. Returns an
+* error, if the date range is invalid.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex)
+{
+ uint32_t tmpDaysInMonth;
+ uint32_t tmpCurrentYear;
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(sec));
+ CY_ASSERT_L3(CY_RTC_IS_MIN_VALID(min));
+ CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(hour));
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
+
+ /* Read the current time to validate the input parameters */
+ Cy_RTC_SyncFromRtc();
+
+ /* Get the current year value to calculate */
+ tmpCurrentYear =
+ Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, BACKUP->RTC_DATE));
+
+ tmpDaysInMonth = Cy_RTC_DaysInMonth(month, (tmpCurrentYear + CY_RTC_TWO_THOUSAND_YEARS));
+
+ if ((date > 0U) && (date <= tmpDaysInMonth))
+ {
+ uint32_t tmpAlarmTime;
+ uint32_t tmpAlarmDate;
+ uint32_t interruptState;
+ cy_stc_rtc_alarm_t alarmDateTime;
+
+ /* Fill the alarm structure */
+ alarmDateTime.sec = sec;
+ alarmDateTime.secEn = CY_RTC_ALARM_ENABLE;
+ alarmDateTime.min = min;
+ alarmDateTime.minEn = CY_RTC_ALARM_ENABLE;
+ alarmDateTime.hour = hour;
+ alarmDateTime.hourEn = CY_RTC_ALARM_ENABLE;
+ alarmDateTime.dayOfWeek = CY_RTC_SUNDAY;
+ alarmDateTime.dayOfWeekEn = CY_RTC_ALARM_DISABLE;
+
+ alarmDateTime.date = date;
+ alarmDateTime.dateEn = CY_RTC_ALARM_ENABLE;
+ alarmDateTime.month = month;
+ alarmDateTime.monthEn = CY_RTC_ALARM_ENABLE;
+ alarmDateTime.almEn = CY_RTC_ALARM_ENABLE;
+
+ ConstructAlarmTimeDate(&alarmDateTime, &tmpAlarmTime, &tmpAlarmDate);
+
+ /* The RTC AHB register can be updated only under condition that the
+ * Write bit is set and the RTC busy bit is cleared (CY_RTC_BUSY = 0).
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED);
+ if (retVal == CY_RTC_SUCCESS)
+ {
+ if (alarmIndex != CY_RTC_ALARM_2)
+ {
+ BACKUP->ALM1_TIME = tmpAlarmTime;
+ BACKUP->ALM1_DATE = tmpAlarmDate;
+ }
+ else
+ {
+ BACKUP->ALM2_TIME = tmpAlarmTime;
+ BACKUP->ALM2_DATE = tmpAlarmDate;
+ }
+
+ /* Clear the RTC Write bit to finish RTC register update */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED);
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetHoursFormat
+****************************************************************************//**
+*
+* Sets the 12/24-hour mode.
+*
+* \param hoursFormat
+* The current hour format, see \ref cy_en_rtc_hours_format_t.
+*
+* \return cy_en_rtc_status_t A validation check result of RTC register update.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat)
+{
+ uint32_t curTime;
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_RTC_IS_HRS_FORMAT_VALID(hoursFormat));
+
+ /* Read the current time to validate the input parameters */
+ Cy_RTC_SyncFromRtc();
+ curTime = BACKUP->RTC_TIME;
+
+ /* Hour format can be changed in condition that current hour format is not
+ * the same as requested in function argument
+ */
+ if (hoursFormat != Cy_RTC_GetHoursFormat())
+ {
+ uint32_t hourValue;
+
+ /* Convert the current hour value from 24H into the 12H format */
+ if (hoursFormat == CY_RTC_12_HOURS)
+ {
+ hourValue = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR, curTime));
+ if (hourValue >= CY_RTC_HOURS_PER_HALF_DAY)
+ {
+ /* The current hour is more than 12 or equal 12 in the 24-hour
+ * mode. Set the PM bit and convert the hour: hour = hour - 12.
+ */
+ hourValue = (uint32_t) (hourValue - CY_RTC_HOURS_PER_HALF_DAY);
+ hourValue = ((0U != hourValue) ? hourValue : CY_RTC_HOURS_PER_HALF_DAY);
+
+ curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, Cy_RTC_ConvertDecToBcd(hourValue)));
+ curTime |= CY_RTC_BACKUP_RTC_TIME_RTC_PM;
+ }
+ else if (hourValue < 1U)
+ {
+ /* The current hour in the 24-hour mode is 0 which is equal
+ * to 12:00 AM
+ */
+ curTime =
+ (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR,
+ Cy_RTC_ConvertDecToBcd(CY_RTC_HOURS_PER_HALF_DAY)));
+
+ /* Set the AM bit */
+ curTime &= ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM);
+ }
+ else
+ {
+ /* The current hour is less than 12 */
+ curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, Cy_RTC_ConvertDecToBcd(hourValue)));
+ curTime &= ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM);
+ }
+
+ curTime |= BACKUP_RTC_TIME_CTRL_12HR_Msk;
+ }
+ /* Convert the hour value into 24H format value */
+ else
+ {
+ /* Mask the AM/PM bit as the hour value is in [20:16] bits */
+ hourValue =
+ Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR,
+ (curTime & (uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM)));
+
+ /* Add 12 hours in condition that current time is in PM period */
+ if ((hourValue < CY_RTC_HOURS_PER_HALF_DAY) && (0U != (curTime & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ hourValue += CY_RTC_HOURS_PER_HALF_DAY;
+ }
+
+ /* Current hour is 12 AM which is equal to zero hour in 24-hour format */
+ if ((hourValue == CY_RTC_HOURS_PER_HALF_DAY) && (0U == (curTime & CY_RTC_BACKUP_RTC_TIME_RTC_PM)))
+ {
+ hourValue = 0U;
+ }
+
+ curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, Cy_RTC_ConvertDecToBcd(hourValue)));
+ curTime &= (uint32_t) ~BACKUP_RTC_TIME_CTRL_12HR_Msk;
+ }
+
+ /* Writing corrected hour value and hour format bit into the RTC AHB
+ * register. The RTC AHB register can be updated only under condition
+ * that the Write bit is set and the RTC busy bit is cleared
+ * (CY_RTC_BUSY = 0).
+ */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED);
+ if (retVal == CY_RTC_SUCCESS)
+ {
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ BACKUP->RTC_TIME = curTime;
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Clear the RTC Write bit to finish RTC register update */
+ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED);
+ }
+ }
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SelectFrequencyPrescaler()
+****************************************************************************//**
+*
+* Selects the RTC pre-scaler value and changes its clock frequency.
+* If the external 32.768 kHz WCO is absent on the board, the RTC can
+* be driven by a 32.768kHz square clock source or an external 50-Hz or 60-Hz
+* sine-wave clock source, for example the wall AC frequency.
+*
+* \param clkSel clock frequency, see \ref cy_en_rtc_clock_freq_t.
+*
+* In addition to generating the 32.768 kHz clock from external crystals, the WCO
+* can be sourced by an external clock source (50 Hz or 60Hz), even the wall AC
+* frequency as a timebase. The API helps select between the RTC sources:
+* * A 32.768 kHz digital clock source <br>
+* * An external 50-Hz or 60-Hz sine-wave clock source
+*
+* If you want to use an external 50-Hz or 60-Hz sine-wave clock source to
+* drive the RTC, the next procedure is required: <br>
+* 1) Disable the WCO <br>
+* 2) Bypass the WCO using the Cy_SysClk_WcoBypass() function <br>
+* 3) Configure both wco_out and wco_in pins. Note that only one of the wco pins
+* should be driven and the other wco pin should be floating, which depends on
+* the source that drives the RTC (*1) <br>
+* 4) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_60_HZ), if you want to
+* drive the WCO, for example, with a 60 Hz source <br>
+* 5) Enable the WCO <br>
+*
+* If you want to use the WCO after using an external 50-Hz or 60-Hz sine-wave
+* clock source: <br>
+* 1) Disable the WCO <br>
+* 2) Switch-off the WCO bypass using the Cy_SysClk_WcoBypass() function <br>
+* 3) Drive off the wco pin with an external signal source <br>
+* 4) Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_WCO_32768_HZ) <br>
+* 5) Enable the WCO <br>
+*
+* (1) - Refer to the device TRM to know how to configure the wco pins properly
+* and which wco pin should be driven/floating.
+*
+* \warning
+* There is a limitation to the external clock source frequencies. Only two
+* frequencies are allowed - 50 Hz or 60 Hz. Note that this limitation is related
+* to the RTC pre-scaling feature presented in this function. This
+* limitation is not related to WCO external clock sources which can drive the
+* WCO in Bypass mode.
+*
+*******************************************************************************/
+void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel)
+{
+ CY_ASSERT_L3(CY_RTC_IS_CLK_VALID(clkSel));
+
+ BACKUP->CTL = (_CLR_SET_FLD32U(BACKUP->CTL, BACKUP_CTL_PRESCALER, (uint32_t) clkSel));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_EnableDstTime
+****************************************************************************//**
+*
+* The function sets the DST time and configures the ALARM2 interrupt register
+* with the appropriate DST time. This function sets the DST stop time if the
+* current time is already in the DST period. The DST period is a period of time
+* between the DST start time and DST stop time. The DST start time and DST stop
+* time is presented in the DST configuration structure,
+* see \ref cy_stc_rtc_dst_t.
+*
+* \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t.
+*
+* \param timeDate
+* The time and date structure. The the appropriate DST time is
+* set based on this time and date, see \ref cy_stc_rtc_config_t.
+*
+* \return
+* cy_en_rtc_status_t A validation check result of RTC register update.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ if ((NULL != dstTime) && (NULL != timeDate))
+ {
+ if (Cy_RTC_GetDstStatus(dstTime, timeDate))
+ {
+ retVal = Cy_RTC_SetNextDstTime(&dstTime->stopDst);
+ }
+ else
+ {
+ retVal = Cy_RTC_SetNextDstTime(&dstTime->startDst);
+ }
+
+ Cy_RTC_SetInterruptMask(CY_RTC_INTR_ALARM2);
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetNextDstTime
+****************************************************************************//**
+*
+* Set the next time of the DST. This function sets the time to ALARM2 for a next
+* DST event. If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be
+* the DST stop, then this function should be called with the DST stop time.
+*
+* If the time format(.format) is relative option(=0), the
+* RelativeToFixed() is called to convert to a fixed date.
+*
+* \param nextDst
+* The structure with time at which a next DST event should occur
+* (ALARM2 interrupt should occur). See \ref cy_stc_rtc_config_t.
+*
+* \return
+* cy_en_rtc_status_t A validation check result of RTC register update.
+*
+*******************************************************************************/
+cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_RTC_IS_DST_FORMAT_VALID(nextDst->format));
+
+ if (NULL != nextDst)
+ {
+ uint32_t tryesToSetup = CY_RTC_TRYES_TO_SETUP_DST;
+ cy_stc_rtc_alarm_t dstAlarmTimeAndDate;
+
+ /* Configure an alarm structure based on the DST structure */
+ dstAlarmTimeAndDate.sec = 0U;
+ dstAlarmTimeAndDate.secEn = CY_RTC_ALARM_ENABLE;
+ dstAlarmTimeAndDate.min = 0U;
+ dstAlarmTimeAndDate.minEn = CY_RTC_ALARM_ENABLE;
+ dstAlarmTimeAndDate.hour = nextDst->hour;
+ dstAlarmTimeAndDate.hourEn = CY_RTC_ALARM_ENABLE;
+ dstAlarmTimeAndDate.dayOfWeek = nextDst->dayOfWeek;
+ dstAlarmTimeAndDate.dayOfWeekEn = CY_RTC_ALARM_DISABLE;
+
+ /* Calculate a day-of-month value for the relative DST start structure */
+ if (CY_RTC_DST_FIXED != nextDst->format)
+ {
+ dstAlarmTimeAndDate.date = RelativeToFixed(nextDst);
+ }
+ else
+ {
+ dstAlarmTimeAndDate.date = nextDst->dayOfMonth;
+ }
+ dstAlarmTimeAndDate.dateEn = CY_RTC_ALARM_ENABLE;
+ dstAlarmTimeAndDate.month = nextDst->month;
+ dstAlarmTimeAndDate.monthEn = CY_RTC_ALARM_ENABLE;
+ dstAlarmTimeAndDate.almEn = CY_RTC_ALARM_ENABLE;
+
+ while((retVal != CY_RTC_SUCCESS) && (0U != tryesToSetup))
+ {
+ retVal = Cy_RTC_SetAlarmDateAndTime(&dstAlarmTimeAndDate, CY_RTC_ALARM_2);
+ --tryesToSetup;
+
+ /* Delay after try to set the DST */
+ Cy_SysLib_DelayUs(CY_RTC_DELAY_AFTER_DST_US);
+ }
+
+ if (tryesToSetup == 0U)
+ {
+ retVal = CY_RTC_TIMEOUT;
+ }
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetDstStatus
+****************************************************************************//**
+*
+* Returns the current DST status using given time information. This function
+* is used in the initial state of a system. If the DST is enabled, the system
+* sets the DST start or stop as a result of this function.
+*
+* \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t.
+*
+* \param timeDate
+* The time and date structure. The the appropriate DST time is
+* set based on this time and date, see \ref cy_stc_rtc_config_t.
+*
+* \return
+* false - The current date and time is out of the DST period.
+* true - The current date and time is in the DST period.
+*
+*******************************************************************************/
+bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate)
+{
+ uint32_t dstStartTime;
+ uint32_t currentTime;
+ uint32_t dstStopTime;
+ uint32_t dstStartDayOfMonth;
+ uint32_t dstStopDayOfMonth;
+
+ CY_ASSERT_L1(NULL != dstTime);
+ CY_ASSERT_L1(NULL != timeDate);
+
+ /* Calculate a day-of-month value for the relative DST start structure */
+ if(CY_RTC_DST_RELATIVE != dstTime->startDst.format)
+ {
+ dstStartDayOfMonth = dstTime->startDst.dayOfMonth;
+ }
+ else
+ {
+ dstStartDayOfMonth = RelativeToFixed(&dstTime->startDst);
+ }
+
+ /* Calculate the day of a month value for the relative DST stop structure */
+ if(CY_RTC_DST_RELATIVE != dstTime->stopDst.format)
+ {
+ dstStopDayOfMonth = dstTime->stopDst.dayOfMonth;
+ }
+ else
+ {
+ dstStopDayOfMonth = RelativeToFixed(&dstTime->stopDst);
+ }
+
+ /* The function forms the date and time values for the DST start time,
+ * the DST Stop Time and for the Current Time. The function that compares
+ * the three formed values returns "true" under condition that:
+ * dstStartTime < currentTime < dstStopTime.
+ * The date and time value are formed this way:
+ * [13-10] - Month
+ * [9-5] - Day of Month
+ * [0-4] - Hour
+ */
+ dstStartTime = ((uint32_t) (dstTime->startDst.month << CY_RTC_DST_MONTH_POSITION) |
+ (dstStartDayOfMonth << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (dstTime->startDst.hour));
+
+ currentTime = ((uint32_t) (timeDate->month << CY_RTC_DST_MONTH_POSITION) |
+ (timeDate->date << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (timeDate->hour));
+
+ dstStopTime = ((uint32_t) (dstTime->stopDst.month << CY_RTC_DST_MONTH_POSITION) |
+ (dstStopDayOfMonth << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (dstTime->stopDst.hour));
+
+ return((dstStartTime <= currentTime) && (dstStopTime > currentTime));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_Alarm1Interrupt
+****************************************************************************//**
+*
+* A blank weak interrupt handler function which indicates assert of the RTC
+* alarm 1 interrupt.
+*
+* Function implementation should be defined in user source code in condition
+* that such event handler is required. If such event is not required user
+* should not do any actions.
+*
+* This function is called in the general RTC interrupt handler
+* `$INSTANCE_NAME`_Interrupt() function.
+*
+*******************************************************************************/
+__WEAK void Cy_RTC_Alarm1Interrupt(void)
+{
+ /* weak blank function */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_Alarm2Interrupt
+****************************************************************************//**
+*
+* A blank weak interrupt handler function which indicates assert of the RTC
+* alarm 2 interrupt.
+*
+* Function implementation should be defined in user source code in condition
+* that such event handler is required. If such event is not required user
+* should not do any actions.
+*
+* This function is called in the general RTC interrupt handler
+* `$INSTANCE_NAME`_Interrupt() function. Cy_RTC_Alarm2Interrupt() function is
+* ignored in `$INSTANCE_NAME`_Interrupt() function if DST is enabled. Refer to
+* `$INSTANCE_NAME`_Interrupt() description.
+*
+*******************************************************************************/
+__WEAK void Cy_RTC_Alarm2Interrupt(void)
+{
+ /* weak blank function */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_DstInterrupt
+****************************************************************************//**
+*
+* This is a processing handler against the DST event. It adjusts the current
+* time using the DST start/stop parameters and registers the next DST event time
+* into the ALARM2 interrupt.
+*
+* \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t.
+*
+*******************************************************************************/
+void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime)
+{
+ cy_stc_rtc_config_t curDateTime;
+
+ Cy_RTC_GetDateAndTime(&curDateTime);
+
+ if (Cy_RTC_GetDstStatus(dstTime, &curDateTime))
+ {
+ /* Under condition that the DST start time was selected as 23:00, and
+ * the time adjusting occurs, the other time and date values should be
+ * corrected (day of the week, date, month and year).
+ */
+ if(curDateTime.hour > CY_RTC_MAX_HOURS_24H)
+ {
+ /* Incrementing day of the week value as hour adjusted next day of
+ * the week and date. Correcting hour value as its incrementation
+ * adjusted it out of valid range [0-23].
+ */
+ curDateTime.dayOfWeek++;
+ curDateTime.hour = 0U;
+
+ /* Correct a day of the week if its incrementation adjusted it out
+ * of valid range [1-7].
+ */
+ if(curDateTime.dayOfWeek > CY_RTC_SATURDAY)
+ {
+ curDateTime.dayOfWeek = CY_RTC_SUNDAY;
+ }
+
+ curDateTime.date++;
+
+ /* Correct a day of a month if its incrementation adjusted it out of
+ * the valid range [1-31]. Increment month value.
+ */
+ if(curDateTime.date > Cy_RTC_DaysInMonth(curDateTime.month,
+ (curDateTime.year + CY_RTC_TWO_THOUSAND_YEARS)))
+ {
+ curDateTime.date = CY_RTC_FIRST_DAY_OF_MONTH;
+ curDateTime.month++;
+ }
+
+ /* Correct a month if its incrementation adjusted it out of the
+ * valid range [1-12]. Increment year value.
+ */
+ if(curDateTime.month > CY_RTC_MONTHS_PER_YEAR)
+ {
+ curDateTime.month = CY_RTC_JANUARY;
+ curDateTime.year++;
+ }
+ }
+ else
+ {
+ curDateTime.hour++;
+ }
+
+ (void) Cy_RTC_SetDateAndTime(&curDateTime);
+ (void) Cy_RTC_SetNextDstTime(&dstTime->stopDst);
+ }
+ else
+ {
+ if(curDateTime.hour < 1U)
+ {
+ /* Decrementing day of the week time and date values as hour
+ * adjusted next day of the week and date. Correct hour value as
+ * its incrementation adjusted it out of valid range [0-23].
+ */
+ curDateTime.hour = CY_RTC_MAX_HOURS_24H;
+ curDateTime.dayOfWeek--;
+
+ /* Correct a day of the week if its incrementation adjusted it out
+ * of the valid range [1-7].
+ */
+ if(curDateTime.dayOfWeek < CY_RTC_SUNDAY)
+ {
+ curDateTime.dayOfWeek = CY_RTC_SUNDAY;
+ }
+
+ curDateTime.date--;
+
+ /* Correct a day of a month value if its incrementation adjusted it
+ * out of the valid range [1-31]. Decrement month value.
+ */
+ if(curDateTime.date < CY_RTC_FIRST_DAY_OF_MONTH)
+ {
+ curDateTime.date =
+ Cy_RTC_DaysInMonth(curDateTime.month, (curDateTime.year + CY_RTC_TWO_THOUSAND_YEARS));
+ curDateTime.month--;
+ }
+
+ /* Correct a month if its increment pushed it out of the valid
+ * range [1-12]. Decrement year value.
+ */
+ if(curDateTime.month < CY_RTC_JANUARY)
+ {
+ curDateTime.month = CY_RTC_DECEMBER;
+ curDateTime.year--;
+ }
+ }
+ else
+ {
+ curDateTime.hour--;
+ }
+
+ (void) Cy_RTC_SetDateAndTime(&curDateTime);
+ (void) Cy_RTC_SetNextDstTime(&dstTime->startDst);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_CenturyInterrupt
+****************************************************************************//**
+*
+* This is a weak function and it should be redefined in user source code
+* in condition that such event handler is required.
+* By calling this function, it indicates the year reached 2100. It
+* should add an adjustment to avoid the Y2K problem.
+*
+* Function implementation should be defined in user source code in condition
+* that such event handler is required. If such event is not required user
+* should not do any actions.
+*
+*******************************************************************************/
+__WEAK void Cy_RTC_CenturyInterrupt(void)
+{
+ /* weak blank function */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns a status of RTC interrupt requests.
+*
+* \return
+* Bit mapping information, see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+uint32_t Cy_RTC_GetInterruptStatus(void)
+{
+ return(BACKUP->INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns an interrupt request register masked by the interrupt mask. Returns a
+* result of the bitwise AND operation between the corresponding interrupt
+* request and mask bits.
+*
+* \return
+* Bit mapping information, see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+uint32_t Cy_RTC_GetInterruptStatusMasked(void)
+{
+ return(BACKUP->INTR_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetInterruptMask
+****************************************************************************//**
+*
+* Returns an interrupt mask.
+*
+* \return
+* Bit mapping information, see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+uint32_t Cy_RTC_GetInterruptMask(void)
+{
+ return (BACKUP->INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetInterrupt
+****************************************************************************//**
+*
+* Sets a software interrupt request
+*
+* \param interruptMask Bit mask, see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+void Cy_RTC_SetInterrupt(uint32_t interruptMask)
+{
+ CY_ASSERT_L3(CY_RTC_INTR_VALID(interruptMask));
+
+ BACKUP->INTR_SET = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ClearInterrupt
+****************************************************************************//**
+*
+* Clears RTC interrupts by setting each bit.
+*
+* \param
+* interruptMask The bit mask of interrupts to set,
+* see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+void Cy_RTC_ClearInterrupt(uint32_t interruptMask)
+{
+ CY_ASSERT_L3(CY_RTC_INTR_VALID(interruptMask));
+
+ BACKUP->INTR = interruptMask;
+
+ (void) BACKUP->INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SetInterruptMask
+****************************************************************************//**
+*
+* Configures which bits of the interrupt request register that triggers an
+* interrupt event.
+*
+* \param interruptMask
+* The bit mask of interrupts to set, see \ref group_rtc_macros_interrupts.
+*
+*******************************************************************************/
+void Cy_RTC_SetInterruptMask(uint32_t interruptMask)
+{
+ CY_ASSERT_L3(CY_RTC_INTR_VALID(interruptMask));
+
+ BACKUP->INTR_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_Interrupt
+****************************************************************************//**
+*
+* The interrupt handler function which should be called in user provided
+* RTC interrupt function.
+*
+* This is the handler of the RTC interrupt in CPU NVIC. The handler checks
+* which RTC interrupt was asserted and calls the respective RTC interrupt
+* handler functions: Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt() or
+* Cy_RTC_DstInterrupt(), and Cy_RTC_CenturyInterrupt().
+*
+* The order of the RTC handler functions execution is incremental.
+* Cy_RTC_Alarm1Interrupt() is run as the first one and Cy_RTC_CenturyInterrupt()
+* is called as the last one.
+*
+* This function clears the RTC interrupt every time when it is called.
+*
+* Cy_RTC_DstInterrupt() function is called instead of Cy_RTC_Alarm2Interrupt()
+* in condition that the mode parameter is true.
+*
+* \param dstTime
+* The daylight saving time configuration structure, see \ref cy_stc_rtc_dst_t.
+*
+* \param mode false - if the DST is disabled, true - if DST is enabled.
+*
+* \note This function is required to be called in user interrupt handler.
+*
+*******************************************************************************/
+void Cy_RTC_Interrupt(cy_stc_rtc_dst_t const *dstTime, bool mode)
+{
+ uint32_t interruptStatus;
+ interruptStatus = Cy_RTC_GetInterruptStatusMasked();
+
+ Cy_RTC_ClearInterrupt(interruptStatus);
+
+ if(0U != (CY_RTC_INTR_ALARM1 & interruptStatus))
+ {
+ Cy_RTC_Alarm1Interrupt();
+ }
+
+ if(0U != (CY_RTC_INTR_ALARM2 & interruptStatus))
+ {
+ if(mode)
+ {
+ Cy_RTC_DstInterrupt(dstTime);
+ }
+ else
+ {
+ Cy_RTC_Alarm2Interrupt();
+ }
+ }
+
+ if(0U != (CY_RTC_INTR_CENTURY & interruptStatus))
+ {
+ Cy_RTC_CenturyInterrupt();
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_DeepSleepCallback
+****************************************************************************//**
+*
+* This function checks the RTC_BUSY bit to avoid data corruption before
+* enters the deep sleep mode.
+*
+* \param callbackParams
+* structure with the syspm callback parameters,
+* see \ref cy_stc_syspm_callback_params_t
+*
+* \return
+* syspm return status, see \ref cy_en_syspm_status_t
+*
+* \note The *base and *context elements are required to be present in
+* the parameter structure because this function uses the SysPm driver
+* callback type.
+* The SysPm driver callback function type requires implementing the function
+* with next parameters and return value: <br>
+* cy_en_syspm_status_t (*Cy_SysPmCallback)
+* (cy_stc_syspm_callback_params_t *callbackParams);
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ if(CY_RTC_AVAILABLE == Cy_RTC_GetSyncStatus())
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_HibernateCallback
+****************************************************************************//**
+*
+* This function checks the RTC_BUSY bit to avoid data corruption before
+* enters the hibernate mode.
+*
+* \param callbackParams
+* structure with the syspm callback parameters,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* syspm return status, see \ref cy_en_syspm_status_t
+*
+* \note The *base and *context elements are required to be present in
+* the parameter structure because this function uses the SysPm driver
+* callback type.
+* The SysPm driver callback function type requires implementing the function
+* with next parameters and return value: <br>
+* cy_en_syspm_status_t (*Cy_SysPmCallback)
+* (cy_stc_syspm_callback_params_t *callbackParams);
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_RTC_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ return (Cy_RTC_DeepSleepCallback(callbackParams));
+}
+
+
+/*******************************************************************************
+* Function Name: ConstructTimeDate
+****************************************************************************//**
+*
+* Returns BCD time and BCD date in the format used in APIs from individual
+* elements passed.
+* Converted BCD time(*timeBcd) and BCD date(*dateBcd) are matched with RTC_TIME
+* and RTC_DATE bit fields format.
+*
+* \param timeDate
+* The structure of time and date, see \ref cy_stc_rtc_config_t.
+*
+* \param timeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_TIME register: <br>
+* [0:6] - Calendar seconds in BCD, the range 0-59. <br>
+* [14:8] - Calendar minutes in BCD, the range 0-59. <br>
+* [21:16] - Calendar hours in BCD, value depends on the 12/24-hour mode. <br>
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; <br>
+* 24HR: [21:16] = 0-23. <br>
+* [22] - Selects the 12/24-hour mode: 1 - 12-hour, 0 - 24-hour. <br>
+* [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. <br>
+*
+* \param dateBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_DATE register: <br>
+* [5:0] - A calendar day of a month in BCD, the range 1-31. <br>
+* [12:8] - A calendar month in BCD, the range 1-12. <br>
+* [23:16] - A calendar year in BCD, the range 0-99. <br>
+*
+*******************************************************************************/
+static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *timeBcd, uint32_t *dateBcd)
+{
+ uint32_t tmpTime;
+ uint32_t tmpDate;
+
+ /* Prepare the RTC TIME value based on the structure obtained */
+ tmpTime = (_VAL2FLD(BACKUP_RTC_TIME_RTC_SEC, Cy_RTC_ConvertDecToBcd(timeDate->sec)));
+ tmpTime |= (_VAL2FLD(BACKUP_RTC_TIME_RTC_MIN, Cy_RTC_ConvertDecToBcd(timeDate->min)));
+
+ /* Read the current hour mode to know how many hour bits to convert.
+ * In the 24-hour mode, the hour value is presented in [21:16] bits in the
+ * BCD format.
+ * In the 12-hour mode, the hour value is presented in [20:16] bits in the
+ * BCD format and
+ * bit [21] is present: 0 - AM; 1 - PM.
+ */
+ if (timeDate->hrFormat != CY_RTC_24_HOURS)
+ {
+ if(CY_RTC_AM != timeDate->amPm)
+ {
+ /* Set the PM bit */
+ tmpTime |= CY_RTC_BACKUP_RTC_TIME_RTC_PM;
+ }
+ else
+ {
+ /* Set the AM bit */
+ tmpTime &= ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM);
+ }
+ tmpTime |= BACKUP_RTC_TIME_CTRL_12HR_Msk;
+ tmpTime |=
+ (_VAL2FLD(BACKUP_RTC_TIME_RTC_HOUR,
+ (Cy_RTC_ConvertDecToBcd(timeDate->hour) & ((uint32_t) ~CY_RTC_12HRS_PM_BIT))));
+ }
+ else
+ {
+ tmpTime &= ((uint32_t) ~BACKUP_RTC_TIME_CTRL_12HR_Msk);
+ tmpTime |= (_VAL2FLD(BACKUP_RTC_TIME_RTC_HOUR, Cy_RTC_ConvertDecToBcd(timeDate->hour)));
+ }
+ tmpTime |= (_VAL2FLD(BACKUP_RTC_TIME_RTC_DAY, Cy_RTC_ConvertDecToBcd(timeDate->dayOfWeek)));
+
+ /* Prepare the RTC Date value based on the structure obtained */
+ tmpDate = (_VAL2FLD(BACKUP_RTC_DATE_RTC_DATE, Cy_RTC_ConvertDecToBcd(timeDate->date)));
+ tmpDate |= (_VAL2FLD(BACKUP_RTC_DATE_RTC_MON, Cy_RTC_ConvertDecToBcd(timeDate->month)));
+ tmpDate |= (_VAL2FLD(BACKUP_RTC_DATE_RTC_YEAR, Cy_RTC_ConvertDecToBcd(timeDate->year)));
+
+ /* Update the parameter values with prepared values */
+ *timeBcd = tmpTime;
+ *dateBcd = tmpDate;
+}
+
+
+/*******************************************************************************
+* Function Name: ConstructAlarmTimeDate
+****************************************************************************//**
+*
+* Returns the BCD time and BCD date in the format used in APIs from individual
+* elements passed for alarm.
+* Converted BCD time(*alarmTimeBcd) and BCD date(*alarmDateBcd) should be
+* matched with the ALMx_TIME and ALMx_DATE bit fields format.
+*
+* \param timeDate
+* The structure of time and date, see \ref cy_stc_rtc_alarm_t.
+*
+* \param alarmTimeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* ALMx_TIME register time fields: <br>
+* [0:6] - Alarm seconds in BCD, the range 0-59. <br>
+* [7] - Alarm seconds Enable: 0 - ignore, 1 - match. <br>
+* [14:8] - Alarm minutes in BCD, the range 0-59. <br>
+* [15] - Alarm minutes Enable: 0 - ignore, 1 - match. <br>
+* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode
+* (RTC_CTRL_12HR) <br>
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; <br>
+* 24HR: [21:16] = the range 0-23. <br>
+* [23] - Alarm hours Enable: 0 - ignore, 1 - match. <br>
+* [26:24] - An alarm day of the week, the range 1 - 7, where 1 - Monday. <br>
+* [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. <br>
+*
+* \param alarmDateBcd
+* The BCD-formatted date variable which has the same bit masks as the
+* ALMx_DATE register date fields: <br>
+* [5:0] - An alarm day of a month in BCD, the range 1-31. <br>
+* [7] - An alarm day of a month Enable: 0 - ignore, 1 - match. <br>
+* [12:8] - An alarm month in BCD, the range 1-12. <br>
+* [15] - An alarm month Enable: 0 - ignore, 1 - match. <br>
+* [31] - The Enable alarm: 0 - Alarm is disabled, 1 - Alarm is enabled. <br>
+*
+* This function reads current AHB register RTC_TIME value to know hour mode.
+* It is recommended to call Cy_RTC_SyncFromRtc() function before calling the
+* ConstructAlarmTimeDate() functions.
+*
+* Construction is based on RTC_ALARM1 register bit fields.
+*
+*******************************************************************************/
+static void ConstructAlarmTimeDate(cy_stc_rtc_alarm_t const *alarmDateTime, uint32_t *alarmTimeBcd,
+ uint32_t *alarmDateBcd)
+{
+ uint32_t tmpAlarmTime;
+ uint32_t tmpAlarmDate;
+ uint32_t hourValue;
+
+ /* Prepare the RTC ALARM value based on the structure obtained */
+ tmpAlarmTime = (_VAL2FLD(BACKUP_ALM1_TIME_ALM_SEC, Cy_RTC_ConvertDecToBcd(alarmDateTime->sec)));
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_SEC_EN, alarmDateTime->secEn));
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_MIN, Cy_RTC_ConvertDecToBcd(alarmDateTime->min)));
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_MIN_EN, alarmDateTime->minEn));
+
+ /* Read the current hour mode to know how many hour bits to convert.
+ * In the 24-hour mode, the hour value is presented in [21:16] bits in the
+ * BCD format.
+ * In the 12-hour mode, the hour value is presented in [20:16] bits in the
+ * BCD format and bit [21] is present: 0 - AM; 1 - PM
+ */
+ Cy_RTC_SyncFromRtc();
+ if(CY_RTC_24_HOURS != Cy_RTC_GetHoursFormat())
+ {
+ /* Convert the hour from the 24-hour mode into the 12-hour mode */
+ if(alarmDateTime->hour >= CY_RTC_HOURS_PER_HALF_DAY)
+ {
+ /* The current hour is more than 12 in the 24-hour mode. Set the PM
+ * bit and converting hour: hour = hour - 12
+ */
+ hourValue = (uint32_t) alarmDateTime->hour - CY_RTC_HOURS_PER_HALF_DAY;
+ hourValue = ((0U != hourValue) ? hourValue : CY_RTC_HOURS_PER_HALF_DAY);
+ tmpAlarmTime |=
+ CY_RTC_BACKUP_RTC_TIME_RTC_PM | (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, Cy_RTC_ConvertDecToBcd(hourValue)));
+ }
+ else if(alarmDateTime->hour < 1U)
+ {
+ /* The current hour in the 24-hour mode is 0 which is equal to 12:00 AM */
+ tmpAlarmTime = (tmpAlarmTime & ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM)) |
+ (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, CY_RTC_HOURS_PER_HALF_DAY));
+ }
+ else
+ {
+ /* The current hour is less than 12. Set the AM bit */
+ tmpAlarmTime = (tmpAlarmTime & ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM)) |
+ (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, Cy_RTC_ConvertDecToBcd(alarmDateTime->hour)));
+ }
+ tmpAlarmTime |= BACKUP_RTC_TIME_CTRL_12HR_Msk;
+ }
+ else
+ {
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, Cy_RTC_ConvertDecToBcd(alarmDateTime->hour)));
+ tmpAlarmTime &= ((uint32_t) ~BACKUP_RTC_TIME_CTRL_12HR_Msk);
+ }
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR_EN, alarmDateTime->hourEn));
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_DAY, Cy_RTC_ConvertDecToBcd(alarmDateTime->dayOfWeek)));
+ tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_DAY_EN, alarmDateTime->dayOfWeekEn));
+
+ /* Prepare the RTC ALARM DATE value based on the obtained structure */
+ tmpAlarmDate = (_VAL2FLD(BACKUP_ALM1_DATE_ALM_DATE, Cy_RTC_ConvertDecToBcd(alarmDateTime->date)));
+ tmpAlarmDate |= (_VAL2FLD(BACKUP_ALM1_DATE_ALM_DATE_EN, alarmDateTime->dateEn));
+ tmpAlarmDate |= (_VAL2FLD(BACKUP_ALM1_DATE_ALM_MON, Cy_RTC_ConvertDecToBcd(alarmDateTime->month)));
+ tmpAlarmDate |= (_VAL2FLD(BACKUP_ALM1_DATE_ALM_MON_EN, alarmDateTime->monthEn));
+ tmpAlarmDate |= (_VAL2FLD(BACKUP_ALM1_DATE_ALM_EN, alarmDateTime->almEn));
+
+ /* Update the parameter values with prepared values */
+ *alarmTimeBcd = tmpAlarmTime;
+ *alarmDateBcd = tmpAlarmDate;
+}
+
+
+/*******************************************************************************
+* Function Name: RelativeToFixed
+****************************************************************************//**
+*
+* Converts time from a relative format to a fixed format to set the ALARM2.
+*
+* \param convertDst
+* The DST structure, its appropriate elements should be converted.
+*
+* \return
+* The current date of a month.
+*
+*******************************************************************************/
+static uint32_t RelativeToFixed(cy_stc_rtc_dst_format_t const *convertDst)
+{
+ uint32_t currentYear;
+ uint32_t currentDay;
+ uint32_t currentWeek;
+ uint32_t daysInMonth;
+ uint32_t tmpDayOfMonth;
+
+ /* Read the current year */
+ Cy_RTC_SyncFromRtc();
+
+ currentYear =
+ CY_RTC_TWO_THOUSAND_YEARS + Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, BACKUP->RTC_DATE));
+
+ currentDay = CY_RTC_FIRST_DAY_OF_MONTH;
+ currentWeek = CY_RTC_FIRST_WEEK_OF_MONTH;
+ daysInMonth = Cy_RTC_DaysInMonth(convertDst->month, currentYear);
+ tmpDayOfMonth = currentDay;
+
+ while((currentWeek <= convertDst->weekOfMonth) && (currentDay <= daysInMonth))
+ {
+ if(convertDst->dayOfWeek == Cy_RTC_ConvertDayOfWeek(currentDay, convertDst->month, currentYear))
+ {
+ tmpDayOfMonth = currentDay;
+ currentWeek++;
+ }
+ currentDay++;
+ }
+ return(tmpDayOfMonth);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1293 @@
+/***************************************************************************//**
+* \file cy_rtc.h
+* \version 2.10
+*
+* This file provides constants and parameter values for the APIs for the
+* Real-Time Clock (RTC).
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*
+*******************************************************************************/
+
+/**
+* \defgroup group_rtc Real-Time Clock (RTC)
+* \{
+*
+* The Real-time Clock (RTC) driver provides an application interface
+* for keeping track of time and date.
+*
+* Use the RTC driver when the system requires the current time or date. You
+* can also use the RTC when you do not need the current time and date but you
+* do need accurate timing of events with one-second resolution.
+*
+* The RTC driver provides these features: <br>
+* * Different hour format support <br>
+* * Multiple alarm function (two-alarms) <br>
+* * Daylight Savings Time (DST) support <br>
+* * Automatic leap year compensation <br>
+* * Option to drive the RTC by an external 50 Hz or 60 Hz clock source
+*
+* The RTC driver provides access to the HW real-time clock. The HW RTC is
+* located in the Backup domain. You need to choose the clock source for the
+* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock
+* for the Backup domain is set and enabled, the RTC automatically
+* starts counting.
+*
+* The RTC driver keeps track of second, minute, hour, day of the week, day of
+* the month, month, and year.
+*
+* DST may be enabled and supports any start and end date. The start and end
+* dates can be a fixed date (like 24 March) or a relative date (like the
+* second Sunday in March).
+*
+* The RTC has two alarms that you can configure to generate an interrupt.
+* You specify the match value for the time when you want the alarm to occur.
+* Your interrupt handler then handles the response. The alarm flexibility
+* supports periodic alarms (such as every minute), or a single alarm
+* (13:45 on 28 September, 2043).
+*
+* <b> Clock Source </b> <br>
+* The Backup domain can be driven by: <br>
+* * Watch-crystal oscillator (WCO). This is a high-accuracy oscillator that is
+* suitable for RTC applications and requires a 32.768 kHz external crystal
+* populated on the application board. The WCO can be supplied by vddbak and
+* therefore can run without vddd/vccd present. This can be used to wake the chip
+* from Hibernate mode.
+*
+* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly
+* (as alternate backup domain clock source). Depending on the device power
+* mode the alternate backup domain clock source is set. For example, for
+* DeepSleep mode the ILO is routed through Clk_LF. But for Hibernate
+* power mode the ILO is set directly. Note that, the ILO should be configured to
+* work in the Hibernate mode. For more info refer to the \ref group_sysclk
+* driver. The ILO is a low-accuracy RC-oscillator that does not require
+* any external elements on the board. Its poor accuracy (+/- 30%) means it is
+* less useful for the RTC. However, current can be supplied by an internal
+* power supply (Vback) and therefore it can run without Vddd/Vccd present.
+* This also can be used to wake the chip from Hibernate mode using RTC alarm
+* interrupt. For more details refer to Power Modes (syspm) driver description.
+*
+* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF
+* (alternate backup domain clock source). This is an RC-oscillator (ILO) that
+* can achieve accuracy of +/- 2% with periodic calibration. It is not expected
+* to be accurate enough for good RTC capability. The PILO requires
+* Vddd/Vccd present. It can be used in modes down to DeepSleep, but ceases to
+* function in Hibernate mode.
+*
+* * External 50 Hz or 60 Hz sine-wave clock source or 32.768kHz square clock
+* source.
+* For example, the wall AC frequency can be the clock source. Such a clock
+* source can be used if the external 32.768 kHz WCO is absent from the board.
+* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function
+* description.
+*
+* The WCO is the recommended clock source for the RTC, if it is present
+* in design. For setting the Backup domain clock source, refer to the
+* \ref group_sysclk driver.
+*
+* \note If the WCO is enabled, it should source the Backup domain directly.
+* Do not route the WCO through the Clk_LF. This is because Clk_LF is not
+* available in all low-power modes.
+*
+* \section group_rtc_section_configuration Configuration Considerations
+*
+* Before RTC set up, ensure that the Backup domain is clocked with the desired
+* clock source.
+*
+* To set up an RTC, provide the configuration parameters in the
+* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the
+* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled
+* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with
+* valid time and date values.
+*
+* <b> RTC Interrupt Handling </b> <br>
+* The RTC driver provides three interrupt handler functions:
+* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and
+* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with
+* the WEAK attribute. For any interrupt you use, redefine the interrupt handler
+* in your source code.
+*
+* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC
+* hardware provides a single interrupt line to the NVIC for the three RTC
+* interrupts. This function checks the interrupt register to determine which
+* interrupt (out of the three) was generated. It then calls the
+* appropriate handler.
+*
+* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is
+* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that
+* interrupt to manage daylight savings time using Cy_RTC_DstInterrupt().
+* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt()
+* function is called instead of Cy_RTC_Alarm2Interrupt().
+*
+* For RTC interrupt handling, the user should: <br>
+* 1) Implement strong interrupt handling function(s) for the required events
+* (see above). If DST is enabled, then Alarm2 is not available. The DST handler
+* is built into the PDL.<br>
+* 2) Implement an RTC interrupt handler and call Cy_RTC_Interrupt()
+* from there<br>
+* 3) Configure the RTC interrupt: <br>
+* a) Set the mask for RTC required interrupt using
+* Cy_RTC_SetInterruptMask()<br>
+* b) Initialize the RTC interrupt by setting priority and the RTC interrupt
+* vector using the Cy_SysInt_Init() function <br>
+* c) Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
+*
+* <b> Alarm functionality </b> <br>
+* To set up an alarm, enable the required RTC interrupt. Then provide the
+* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable
+* any item you want matched, and provide a match value. You disable any other.
+* You do not need to set match values for disabled elements, as they are
+* ignored.
+* \note The alarm itself must be enabled in this structure. When a match
+* occurs, the alarm is triggered and your interrupt handler is called.
+*
+* An example is the best way to explain how this works. If you want an alarm
+* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide
+* these values:
+*
+* Alarm_1.sec = 0u <br>
+* Alarm_1.secEn = CY_RTC_ALARM_ENABLE <br>
+* Alarm_1.min = 0u <br>
+* Alarm_1.minEn = CY_RTC_ALARM_ENABLE <br>
+* Alarm_1.hourEn = CY_RTC_ALARM_DISABLE <br>
+* Alarm_1.dayOfWeekEn = CY_RTC_ALARM_DISABLE <br>
+* Alarm_1.dateEn = CY_RTC_ALARM_DISABLE <br>
+* Alarm_1.monthEn = CY_RTC_ALARM_DISABLE <br>
+* Alarm_1.almEn = CY_RTC_ALARM_ENABLE <br>
+*
+* With this setup, every time both the second and minute are zero, Alarm1 is
+* asserted. That happens once per hour. Note that, counterintuitively, to have
+* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because
+* for an hourly alarm you do not match the value of the hour.
+*
+* After cy_stc_rtc_alarm_t structure is filled, call the
+* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the
+* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with
+* valid values.
+*
+* <b> The DST Feature </b> <br>
+* The DST feature is managed by the PDL using the RTC Alarm2 interrupt.
+* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt.
+*
+* To set up the DST, route the RTC interrupt to NVIC:<br>
+* 1) Initialize the RTC interrupt by setting priority and the RTC interrupt
+* vector using Cy_SysInt_Init() <br>
+* 2) Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
+*
+* After this, provide the configuration parameters in the
+* cy_stc_rtc_dst_t structure. This structure consists of two
+* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for
+* DST Stop time. You also specify whether these times are absolute or relative.
+*
+* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime()
+*
+* \section group_rtc_lp Low Power Support
+* The RTC provides the callback functions to facilitate
+* the low-power mode transition. The callback
+* \ref Cy_RTC_DeepSleepCallback must be called during execution
+* of \ref Cy_SysPm_DeepSleep; \ref Cy_RTC_HibernateCallback must be
+* called during execution of \ref Cy_SysPm_Hibernate.
+* To trigger the callback execution, the callback must be registered
+* before calling the mode transition function.
+* Refer to \ref group_syspm driver for more
+* information about low-power mode transitions.
+*
+* \section group_rtc_section_more_information More Information
+*
+* For more information on the RTC peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_rtc_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>A</td>
+* <td>The object addressed by the pointer parameter '%s' is not modified and
+* so the pointer could be of type 'pointer to const'.</td>
+* <td>
+* The pointer parameter is not used or modified, as there is no need
+* to do any actions with it. However, such parameter is
+* required to be presented in the function, because the
+* \ref Cy_RTC_DeepSleepCallback and \ref Cy_RTC_HibernateCallback are
+* callbacks of \ref cy_en_syspm_status_t type.
+* The SysPm driver callback function type requires implementing the
+* function with the next parameter and return value: <br>
+* cy_en_syspm_status_t (*Cy_SysPmCallback)
+* (cy_stc_syspm_callback_params_t *callbackParams);
+* </td>
+* </tr>
+* </table>
+*
+* \section group_rtc_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td> Corrected Cy_RTC_SetDateAndTimeDirect(), Cy_RTC_SetNextDstTime()
+* function <br>
+* Corrected internal macro <br>
+* Documentation updates</td>
+* <td> Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and
+* \ref Cy_RTC_SetNextDstTime() work in debug mode <br>
+* Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek,
+* \ref Cy_RTC_IsLeapYear, \ref Cy_RTC_DaysInMonth </td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>Enhancement and defect fixes: <br>
+* * Added input parameter(s) validation to all public functions. <br>
+* * Removed "Cy_RTC_" prefixes from the internal functions names. <br>
+* * Renamed the elements in the cy_stc_rtc_alarm structure. <br>
+* * Changed the type of elements with limited set of values, from
+* uint32_t to enumeration.
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_rtc_macros Macros
+* \defgroup group_rtc_functions Functions
+* \{
+* \defgroup group_rtc_general_functions General
+* \defgroup group_rtc_alarm_functions Alarm
+* \defgroup group_rtc_dst_functions DST functions
+* \defgroup group_rtc_low_level_functions Low-Level
+* \defgroup group_rtc_interrupt_functions Interrupt
+* \defgroup group_rtc_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_rtc_data_structures Data Structures
+* \defgroup group_rtc_enums Enumerated Types
+*/
+
+#if !defined (_CY_RTC_H_)
+#define _CY_RTC_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXS40SRSS_RTC
+ #error "The RTC driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/**
+* \addtogroup group_rtc_macros
+* \{
+*/
+
+/** RTC driver identifier */
+#define CY_RTC_ID (CY_PDL_DRV_ID(0x28U))
+
+/** Driver major version */
+#define CY_RTC_DRV_VERSION_MAJOR 2
+
+/** Driver minor version */
+#define CY_RTC_DRV_VERSION_MINOR 10
+/** \} group_rtc_macros */
+
+/*******************************************************************************
+* Enumerated Types
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_enums
+* \{
+*/
+
+/** RTC status enumeration */
+typedef enum
+ {
+ CY_RTC_SUCCESS = 0x00U, /**< Successful */
+ CY_RTC_BAD_PARAM = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */
+ CY_RTC_TIMEOUT = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< Time-out occurs */
+ CY_RTC_INVALID_STATE = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< Operation not setup or is in an improper state */
+ CY_RTC_UNKNOWN = CY_RTC_ID | CY_PDL_STATUS_ERROR | 0xFFU /**< Unknown failure */
+} cy_en_rtc_status_t;
+
+/** This enumeration is used to set frequency by changing the it pre-scaler */
+typedef enum
+{
+ CY_RTC_FREQ_WCO_32768_HZ, /**< prescaler value for 32.768 kHz oscillator */
+ CY_RTC_FREQ_60_HZ, /**< prescaler value for 60 Hz source */
+ CY_RTC_FREQ_50_HZ, /**< prescaler value for 50 Hz source */
+} cy_en_rtc_clock_freq_t;
+
+/** This enumeration is used to set/get information for alarm 1 or alarm 2 */
+typedef enum cy_en_rtc_alarm
+{
+ CY_RTC_ALARM_1, /**< Alarm 1 enum */
+ CY_RTC_ALARM_2 /**< Alarm 2 enum */
+} cy_en_rtc_alarm_t;
+
+/** This enumeration is used to set/get hours format */
+typedef enum
+{
+ CY_RTC_24_HOURS, /**< The 24 hour format */
+ CY_RTC_12_HOURS /**< The 12 hour (AM/PM) format */
+} cy_en_rtc_hours_format_t;
+
+/** Enumeration to configure the RTC Write register */
+typedef enum
+{
+ CY_RTC_WRITE_DISABLED, /**< Writing the RTC is disabled */
+ CY_RTC_WRITE_ENABLED /**< Writing the RTC is enabled */
+} cy_en_rtc_write_status_t;
+
+/** Enumeration used to set/get DST format */
+typedef enum
+{
+ CY_RTC_DST_RELATIVE, /**< Relative DST format */
+ CY_RTC_DST_FIXED /**< Fixed DST format */
+} cy_en_rtc_dst_format_t;
+
+/** Enumeration to indicate the AM/PM period of day */
+typedef enum
+{
+ CY_RTC_AM, /**< AM period of day */
+ CY_RTC_PM /**< PM period of day */
+} cy_en_rtc_am_pm_t;
+
+/** Enumeration to enable/disable the RTC alarm on match with required value */
+typedef enum
+{
+ CY_RTC_ALARM_DISABLE, /**< Disable alarm on match with required value */
+ CY_RTC_ALARM_ENABLE /**< Enable alarm on match with required value */
+} cy_en_rtc_alarm_enable_t;
+/** \} group_rtc_enums */
+
+
+/*******************************************************************************
+* Types definition
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_data_structures
+* \{
+*/
+
+/**
+* This is the data structure that is used to configure the rtc time
+* and date values.
+*/
+typedef struct cy_stc_rtc_config
+{
+ /* Time information */
+ uint32_t sec; /**< Seconds value, range [0-59] */
+ uint32_t min; /**< Minutes value, range [0-59] */
+ uint32_t hour; /**< Hour, range depends on hrFormat, if hrFormat = CY_RTC_24_HOURS, range [0-23];
+ If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day
+ period should be set (amPm) */
+ cy_en_rtc_am_pm_t amPm; /**< AM/PM hour period, see \ref cy_en_rtc_am_pm_t.
+ This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware
+ ignores this element if hrFormat = CY_RTC_24_HOURS */
+ cy_en_rtc_hours_format_t hrFormat; /**< Hours format, see \ref cy_en_rtc_hours_format_t */
+ uint32_t dayOfWeek; /**< Day of the week, range [1-7], see \ref group_rtc_day_of_the_week */
+
+ /* Date information */
+ uint32_t date; /**< Date of month, range [1-31] */
+ uint32_t month; /**< Month, range [1-12]. See \ref group_rtc_month */
+ uint32_t year; /**< Year, range [0-99] */
+} cy_stc_rtc_config_t;
+
+/** Decimal data structure that is used to save the Alarms */
+typedef struct cy_stc_rtc_alarm
+{
+ /* Alarm time information */
+ uint32_t sec; /**< Alarm seconds, range [0-59].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if secEn is previous enabled (secEn = 1) */
+ cy_en_rtc_alarm_enable_t secEn; /**< Enable alarm on seconds matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t min; /**< Alarm minutes, range [0-59].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if minEn is previous enabled (minEn = 1) */
+ cy_en_rtc_alarm_enable_t minEn; /**< Enable alarm on minutes matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t hour; /**< Alarm hours, range [0-23]
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if hourEn is previous enabled (hourEn = 1) */
+ cy_en_rtc_alarm_enable_t hourEn; /**< Enable alarm on hours matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t dayOfWeek; /**< Alarm day of the week, range [1-7]
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dayOfWeek is previous enabled (dayOfWeekEn = 1) */
+ cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching,
+ see \ref cy_en_rtc_alarm_enable_t */
+
+ /* Alarm date information */
+ uint32_t date; /**< Alarm date, range [1-31].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dateEn is previous enabled (dateEn = 1) */
+ cy_en_rtc_alarm_enable_t dateEn; /**< Enable alarm on date matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ uint32_t month; /**< Alarm Month, range [1-12].
+ The appropriate ALARMX interrupt is be asserted on matching with this
+ value if dateEn is previous enabled (dateEn = 1) */
+ cy_en_rtc_alarm_enable_t monthEn; /**< Enable alarm on month matching, see \ref cy_en_rtc_alarm_enable_t. */
+
+ cy_en_rtc_alarm_enable_t almEn; /**< Enable Alarm for appropriate ALARMX, see \ref cy_en_rtc_alarm_enable_t.
+ If all alarm structure elements are enabled (almEn = CY_RTC_ALARM_ENABLE)
+ the alarm interrupt is be asserted every second. */
+} cy_stc_rtc_alarm_t;
+
+/**
+* This is DST structure for DST feature setting. Structure is combined with the
+* fixed format and the relative format. It is used to save the DST time and date
+* fixed or relative time format.
+*/
+typedef struct
+{
+ cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t.
+ Based on this value other structure elements
+ should be filled or could be ignored */
+ uint32_t hour; /**< Should be filled for both format types.
+ Hour is always presented in 24hour format, range[0-23] */
+ uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if
+ format = CY_RTC_DST_FIXED. Firmware calculates this value in condition that
+ format = CY_RTC_DST_RELATIVE is selected */
+ uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if
+ format = CY_RTC_DST_RELATIVE.
+ Firmware calculates dayOfMonth value based on weekOfMonth
+ and dayOfWeek values */
+ uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that
+ format = CY_RTC_DST_RELATIVE. Range[1- 7],
+ see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value
+ based on dayOfWeek and weekOfMonth values */
+ uint32_t month; /**< Month value, range[1-12], see \ref group_rtc_month.
+ This value should be filled for both format types */
+} cy_stc_rtc_dst_format_t;
+
+/** This is the DST structure to handle start DST and stop DST */
+typedef struct
+{
+ cy_stc_rtc_dst_format_t startDst; /**< DST start time structure */
+ cy_stc_rtc_dst_format_t stopDst; /**< DST stop time structure */
+} cy_stc_rtc_dst_t;
+
+/** \} group_rtc_data_structures */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_rtc_functions
+* \{
+*/
+
+/**
+* \addtogroup group_rtc_general_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config);
+cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime);
+void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t *dateTime);
+cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, uint32_t year);
+cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat);
+void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);
+/** \} group_rtc_general_functions */
+
+/**
+* \addtogroup group_rtc_alarm_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
+void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
+cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
+ uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex);
+/** \} group_rtc_alarm_functions */
+
+/**
+* \addtogroup group_rtc_dst_functions
+* \{
+*/
+cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate);
+cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst);
+bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate);
+/** \} group_rtc_dst_functions */
+
+/**
+* \addtogroup group_rtc_interrupt_functions
+* \{
+*/
+void Cy_RTC_Interrupt(cy_stc_rtc_dst_t const *dstTime, bool mode);
+void Cy_RTC_Alarm1Interrupt(void);
+void Cy_RTC_Alarm2Interrupt(void);
+void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime);
+void Cy_RTC_CenturyInterrupt(void);
+uint32_t Cy_RTC_GetInterruptStatus(void);
+uint32_t Cy_RTC_GetInterruptStatusMasked(void);
+uint32_t Cy_RTC_GetInterruptMask(void);
+void Cy_RTC_ClearInterrupt(uint32_t interruptMask);
+void Cy_RTC_SetInterrupt(uint32_t interruptMask);
+void Cy_RTC_SetInterruptMask(uint32_t interruptMask);
+/** \} group_rtc_interrupt_functions */
+
+/**
+* \addtogroup group_rtc_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_RTC_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_rtc_low_power_functions */
+
+/**
+* \addtogroup group_rtc_low_level_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, uint32_t year);
+__STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year);
+__STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year);
+__STATIC_INLINE void Cy_RTC_SyncFromRtc(void);
+__STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t writeEnable);
+__STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void);
+__STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum);
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDecToBcd(uint32_t decNum);
+__STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void);
+__STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void);
+
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd);
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex);
+/** \} group_rtc_low_level_functions */
+
+/** \} group_rtc_functions */
+
+/**
+* \addtogroup group_rtc_macros
+* \{
+*/
+
+/*******************************************************************************
+* API Constants
+*******************************************************************************/
+
+/**
+* \defgroup group_rtc_day_of_the_week Day of the week definitions
+* \{
+* Definitions of days in the week
+*/
+#define CY_RTC_SUNDAY (1UL) /**< Sequential number of Sunday in the week */
+#define CY_RTC_MONDAY (2UL) /**< Sequential number of Monday in the week */
+#define CY_RTC_TUESDAY (3UL) /**< Sequential number of Tuesday in the week */
+#define CY_RTC_WEDNESDAY (4UL) /**< Sequential number of Wednesday in the week */
+#define CY_RTC_THURSDAY (5UL) /**< Sequential number of Thursday in the week */
+#define CY_RTC_FRIDAY (6UL) /**< Sequential number of Friday in the week */
+#define CY_RTC_SATURDAY (7UL) /**< Sequential number of Saturday in the week */
+/** \} group_rtc_day_of_the_week */
+
+/**
+* \defgroup group_rtc_dst_week_of_month Week of month definitions
+* \{
+* Week of Month setting constants definitions for Daylight Saving Time feature
+*/
+#define CY_RTC_FIRST_WEEK_OF_MONTH (1UL) /**< First week in the month */
+#define CY_RTC_SECOND_WEEK_OF_MONTH (2UL) /**< Second week in the month */
+#define CY_RTC_THIRD_WEEK_OF_MONTH (3UL) /**< Third week in the month */
+#define CY_RTC_FOURTH_WEEK_OF_MONTH (4UL) /**< Fourth week in the month */
+#define CY_RTC_FIFTH_WEEK_OF_MONTH (5UL) /**< Fifth week in the month */
+#define CY_RTC_LAST_WEEK_OF_MONTH (6UL) /**< Last week in the month */
+/** \} group_rtc_dst_week_of_month */
+
+/**
+* \defgroup group_rtc_month Month definitions
+* \{
+* Constants definition for Months
+*/
+#define CY_RTC_JANUARY (1UL) /**< Sequential number of January in the year */
+#define CY_RTC_FEBRUARY (2UL) /**< Sequential number of February in the year */
+#define CY_RTC_MARCH (3UL) /**< Sequential number of March in the year */
+#define CY_RTC_APRIL (4UL) /**< Sequential number of April in the year */
+#define CY_RTC_MAY (5UL) /**< Sequential number of May in the year */
+#define CY_RTC_JUNE (6UL) /**< Sequential number of June in the year */
+#define CY_RTC_JULY (7UL) /**< Sequential number of July in the year */
+#define CY_RTC_AUGUST (8UL) /**< Sequential number of August in the year */
+#define CY_RTC_SEPTEMBER (9UL) /**< Sequential number of September in the year */
+#define CY_RTC_OCTOBER (10UL) /**< Sequential number of October in the year */
+#define CY_RTC_NOVEMBER (11UL) /**< Sequential number of November in the year */
+#define CY_RTC_DECEMBER (12UL) /**< Sequential number of December in the year */
+/** \} group_rtc_month */
+
+/**
+* \defgroup group_rtc_days_in_month Number of days in month definitions
+* \{
+* Definition of days in current month
+*/
+#define CY_RTC_DAYS_IN_JANUARY (31U) /**< Number of days in January */
+#define CY_RTC_DAYS_IN_FEBRUARY (28U) /**< Number of days in February */
+#define CY_RTC_DAYS_IN_MARCH (31U) /**< Number of days in March */
+#define CY_RTC_DAYS_IN_APRIL (30U) /**< Number of days in April */
+#define CY_RTC_DAYS_IN_MAY (31U) /**< Number of days in May */
+#define CY_RTC_DAYS_IN_JUNE (30U) /**< Number of days in June */
+#define CY_RTC_DAYS_IN_JULY (31U) /**< Number of days in July */
+#define CY_RTC_DAYS_IN_AUGUST (31U) /**< Number of days in August */
+#define CY_RTC_DAYS_IN_SEPTEMBER (30U) /**< Number of days in September */
+#define CY_RTC_DAYS_IN_OCTOBER (31U) /**< Number of days in October */
+#define CY_RTC_DAYS_IN_NOVEMBER (30U) /**< Number of days in November */
+#define CY_RTC_DAYS_IN_DECEMBER (31U) /**< Number of days in December */
+/** \} group_rtc_days_in_month */
+
+/**
+* \defgroup group_rtc_macros_interrupts RTC Interrupt sources
+* \{
+* Definitions for RTC interrupt sources
+*/
+/** Alarm 1 status */
+#define CY_RTC_INTR_ALARM1 BACKUP_INTR_ALARM1_Msk
+
+/** Alarm 2 status */
+#define CY_RTC_INTR_ALARM2 BACKUP_INTR_ALARM2_Msk
+
+/**
+* This interrupt occurs when the year is reached to 2100 which is rolling
+* over the year field value from 99 to 0
+*/
+#define CY_RTC_INTR_CENTURY BACKUP_INTR_CENTURY_Msk
+/** \} group_rtc_macros_interrupts */
+
+/**
+* \defgroup group_rtc_busy_status RTC Status definitions
+* \{
+* Definitions for indicating the RTC BUSY bit
+*/
+#define CY_RTC_BUSY (1UL) /**< RTC Busy bit is set, RTC is pending */
+#define CY_RTC_AVAILABLE (0UL) /**< RTC Busy bit is cleared, RTC is available */
+/** \} group_rtc_busy_status */
+
+/*******************************************************************************
+* Internal Constants
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/** Days per week definition */
+#define CY_RTC_DAYS_PER_WEEK (7UL)
+
+/** Month per year definition */
+#define CY_RTC_MONTHS_PER_YEAR (12U)
+
+/** Maximum value of seconds and minutes */
+#define CY_RTC_MAX_SEC_OR_MIN (59UL)
+
+/** Biggest value of hours definition */
+#define CY_RTC_MAX_HOURS_24H (23UL)
+
+/** Maximum value of year definition */
+#define CY_RTC_MAX_DAYS_IN_MONTH (31UL)
+
+/** Maximum value of year definition */
+#define CY_RTC_MAX_YEAR (99UL)
+
+/** Number of RTC interrupts */
+#define CY_RTC_NUM_OF_INTR (3U)
+
+/** Number of RTC interrupts */
+#define CY_RTC_TRYES_TO_SETUP_DST (24U)
+
+/** RTC AM/PM bit for 12H hour mode */
+#define CY_RTC_12HRS_PM_BIT (0x20UL)
+
+/** Mask for reading RTC AM/PM bit for 12H mode */
+#define CY_RTC_BACKUP_RTC_TIME_RTC_PM ((uint32_t) (CY_RTC_12HRS_PM_BIT << BACKUP_RTC_TIME_RTC_HOUR_Pos))
+
+/** Internal define for BCD values converting */
+#define CY_RTC_BCD_NUMBER_SIZE (4UL)
+
+/** Internal mask for BCD values converting */
+#define CY_RTC_BCD_ONE_DIGIT_MASK (0x0000000FUL)
+
+/** Internal define of dozen degree for BCD values converting */
+#define CY_RTC_BCD_DOZED_DEGREE (10UL)
+
+/** Internal define of hundred degree for BCD values converting */
+#define CY_RTC_BCD_HUNDRED_DEGRE (100UL)
+
+/** Definition of six WCO clocks in microseconds */
+#define CY_RTC_DELAY_WHILE_READING_US (183U)
+
+/** Definition of two WCO clocks in microseconds */
+#define CY_RTC_DELAY_WRITE_US (62U)
+
+/** Definition of two WCO clocks in microseconds */
+#define CY_RTC_DELAY_FOR_NEXT_DST (2000U)
+
+/** Two thousand years definition */
+#define CY_RTC_TWO_THOUSAND_YEARS (2000UL)
+
+/** Two thousand years definition */
+#define CY_RTC_TWENTY_ONE_HUNDRED_YEARS (2100UL)
+
+/** Mask for reading RTC hour for 12H mode */
+#define CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR (0x1f0000UL)
+
+/** Half day hours definition */
+#define CY_RTC_HOURS_PER_HALF_DAY (12UL)
+
+/** First day of the month definition */
+#define CY_RTC_FIRST_DAY_OF_MONTH (1UL)
+
+/** Internal definition for DST GetDstStatus() function */
+#define CY_RTC_DST_MONTH_POSITION (10UL)
+
+/** Internal definition for DST GetDstStatus() function */
+#define CY_RTC_DST_DAY_OF_MONTH_POSITION (5UL)
+
+/** Definition of delay in microseconds after try to set DST */
+#define CY_RTC_DELAY_AFTER_DST_US (62U)
+
+/** RTC days in months table */
+extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR];
+
+/* Internal macro to validate parameters in Cy_RTC_SelectFrequencyPrescaler() function */
+#define CY_RTC_IS_CLK_VALID(clkSel) (((clkSel) == CY_RTC_FREQ_WCO_32768_HZ) || \
+ ((clkSel) == CY_RTC_FREQ_60_HZ) || \
+ ((clkSel) == CY_RTC_FREQ_50_HZ))
+
+/* Internal macro to validate parameters in Cy_RTC_SetHoursFormat() function */
+#define CY_RTC_IS_HRS_FORMAT_VALID(hoursFormat) (((hoursFormat) == CY_RTC_24_HOURS) || \
+ ((hoursFormat) == CY_RTC_12_HOURS))
+
+/* Internal macro to validate parameters in Cy_RTC_WriteEnable() function */
+#define CY_RTC_IS_WRITE_VALID(writeEnable) (((writeEnable) == CY_RTC_WRITE_DISABLED) || \
+ ((writeEnable) == CY_RTC_WRITE_ENABLED))
+
+/* Internal macro of all possible RTC interrupts */
+#define CY_RTC_INTR_MASK (CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2 | CY_RTC_INTR_CENTURY)
+
+/* Macro to validate parameters in interrupt related functions */
+#define CY_RTC_INTR_VALID(interruptMask) (0UL == ((interruptMask) & ((uint32_t) ~(CY_RTC_INTR_MASK))))
+
+/* Internal macro to validate RTC seconds and minutes parameters */
+#define CY_RTC_IS_SEC_VALID(sec) ((sec) <= CY_RTC_MAX_SEC_OR_MIN)
+
+/* Internal macro to validate RTC seconds and minutes parameters */
+#define CY_RTC_IS_MIN_VALID(min) ((min) <= CY_RTC_MAX_SEC_OR_MIN)
+
+/* Internal macro to validate RTC hour parameter */
+#define CY_RTC_IS_HOUR_VALID(hour) ((hour) <= CY_RTC_MAX_HOURS_24H)
+
+/* Internal macro to validate RTC day of the week parameter */
+#define CY_RTC_IS_DOW_VALID(dayOfWeek) (((dayOfWeek) > 0U) && ((dayOfWeek) <= CY_RTC_DAYS_PER_WEEK))
+
+/* Internal macro to validate RTC day parameter */
+#define CY_RTC_IS_DAY_VALID(day) (((day) > 0U) && ((day) <= CY_RTC_MAX_DAYS_IN_MONTH))
+
+/* Internal macro to validate RTC month parameter */
+#define CY_RTC_IS_MONTH_VALID(month) (((month) > 0U) && ((month) <= CY_RTC_MONTHS_PER_YEAR))
+
+/* Internal macro to validate RTC year parameter */
+#define CY_RTC_IS_YEAR_SHORT_VALID(year) ((year) <= CY_RTC_MAX_YEAR)
+
+/* Internal macro to validate the year value in the Cy_RTC_ConvertDayOfWeek() */
+#define CY_RTC_IS_YEAR_LONG_VALID(year) (((year) >= CY_RTC_TWO_THOUSAND_YEARS) && \
+ ((year) <= CY_RTC_TWENTY_ONE_HUNDRED_YEARS))
+
+/* Internal macro to validate RTC alarm parameter */
+#define CY_RTC_IS_ALARM_EN_VALID(alarmEn) (((alarmEn) == CY_RTC_ALARM_DISABLE) || \
+ ((alarmEn) == CY_RTC_ALARM_ENABLE))
+
+/* Internal macro to validate RTC alarm index parameter */
+#define CY_RTC_IS_ALARM_IDX_VALID(alarmIndex) (((alarmIndex) == CY_RTC_ALARM_1) || ((alarmIndex) == CY_RTC_ALARM_2))
+
+/* Internal macro to validate RTC alarm index parameter */
+#define CY_RTC_IS_DST_FORMAT_VALID(format) (((format) == CY_RTC_DST_RELATIVE) || ((format) == CY_RTC_DST_FIXED))
+
+/** \endcond */
+/** \} group_rtc_macros */
+
+/**
+* \addtogroup group_rtc_low_level_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertDayOfWeek
+****************************************************************************//**
+*
+* Returns a day of the week for a year, month, and day of month that are passed
+* through parameters. Zeller's congruence is used to calculate the day of
+* the week.
+* RTC HW block does not provide the converting function for day of week. This
+* function should be called before Cy_RTC_SetDateAndTime() to get the day of
+* week.
+*
+* For the Georgian calendar, Zeller's congruence is:
+* h = (q + [13 * (m + 1)] + K + [K/4] + [J/4] - 2J) mod 7
+*
+* h - The day of the week (0 = Saturday, 1 = Sunday, 2 = Monday, ., 6 = Friday).
+* q - The day of the month.
+* m - The month (3 = March, 4 = April, 5 = May, ..., 14 = February)
+* K - The year of the century (year mod 100).
+* J - The zero-based century (actually [year/100]) For example, the zero-based
+* centuries for 1995 and 2000 are 19 and 20 respectively (not to be
+* confused with the common ordinal century enumeration which indicates
+* 20th for both cases).
+*
+* \note In this algorithm January and February are counted as months 13 and 14
+* of the previous year.
+*
+* \param day The day of the month, Valid range 1..31.
+*
+* \param month The month of the year, see \ref group_rtc_month.
+*
+* \param year The year value. Valid range - 2000...2100.
+*
+* \return
+* Returns a day of the week, see \ref group_rtc_day_of_the_week.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, uint32_t year)
+{
+ uint32_t retVal;
+
+ CY_ASSERT_L3(CY_RTC_IS_DAY_VALID(day));
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L3(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ /* Converts month number from regular convention
+ * (1=January,..., 12=December) to convention required for this
+ * algorithm (January and February are counted as months 13 and 14 of
+ * previous year).
+ */
+ if(month < CY_RTC_MARCH)
+ {
+ month = CY_RTC_MONTHS_PER_YEAR + month;
+ year--;
+ }
+
+ /* Calculates Day of Week using Zeller's congruence algorithms */
+ retVal =
+ (day + (((month + 1UL) * 26UL) / 10UL) + year + (year / 4UL) + (6UL * (year / 100UL)) + (year / 400UL)) % 7UL;
+
+ /* Makes correction for Saturday. Saturday number should be 7 instead of 0*/
+ if(0u == retVal)
+ {
+ retVal = CY_RTC_SATURDAY;
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_IsLeapYear
+****************************************************************************//**
+*
+* Checks whether the year passed through the parameter is leap or not.
+*
+* This API is for checking an invalid value input for leap year.
+* RTC HW block does not provide a validation checker against time/date values,
+* the valid range of days in Month should be checked before SetDateAndTime()
+* function call. Leap year is identified as a year that is a multiple of 4
+* or 400 but not 100.
+*
+* \param year The year to be checked. Valid range - 2000...2100.
+*
+* \return
+* false - The year is not leap; true - The year is leap.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year)
+{
+ CY_ASSERT_L3(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ return(((0U == (year % 4UL)) && (0U != (year % 100UL))) || (0U == (year % 400UL)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_DaysInMonth
+****************************************************************************//**
+*
+* Returns a number of days in a month passed through the parameters. This API
+* is for checking an invalid value input for days.
+* RTC HW block does not provide a validation checker against time/date values,
+* the valid range of days in Month should be checked before SetDateAndTime()
+* function call.
+*
+* \param month The month of the year, see \ref group_rtc_month.
+*
+* \param year A year value. Valid range - 2000...2100.
+*
+* \return A number of days in a month in the year passed through the parameters.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year)
+{
+ uint32_t retVal;
+
+ CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month));
+ CY_ASSERT_L3(CY_RTC_IS_YEAR_LONG_VALID(year));
+
+ retVal = cy_RTC_daysInMonthTbl[month - 1UL];
+
+ if(CY_RTC_FEBRUARY == month)
+ {
+ if(Cy_RTC_IsLeapYear(year))
+ {
+ retVal++;
+ }
+ }
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncFromRtc
+****************************************************************************//**
+*
+* The Synchronizer updates RTC values into AHB RTC user registers from the
+* actual RTC. By calling this function, the actual RTC register values is
+* copied to AHB user registers.
+*
+* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be
+* read.
+* After Cy_RTC_SyncFromRtc() calling the snapshot of the actual RTC registers
+* are copied to the user registers. Meanwhile the RTC continues to clock.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncFromRtc(void)
+{
+ uint32_t interruptState;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0
+ * or RTC Write bit is not set.
+ */
+ if((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_WRITE, BACKUP->RTC_RW)))
+ {
+ /* Setting RTC Read bit */
+ BACKUP->RTC_RW = BACKUP_RTC_RW_READ_Msk;
+
+ /* Delay to guarantee RTC data reading */
+ Cy_SysLib_DelayUs(CY_RTC_DELAY_WHILE_READING_US);
+
+ /* Clearing RTC Read bit */
+ BACKUP->RTC_RW = 0U;
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_WriteEnable
+****************************************************************************//**
+*
+* Set/Clear writeable option for RTC user registers. When the Write bit is set,
+* data can be written into the RTC user registers. After all the RTC writes are
+* done, the firmware must clear (call Cy_RTC_WriteEnable(RTC_WRITE_DISABLED))
+* the Write bit for the RTC update to take effect.
+*
+* Set/Clear cannot be done if the RTC is still busy with a previous update
+* (CY_RTC_BUSY = 1) or RTC Reading is executing.
+*
+* \param writeEnable write status, see \ref cy_en_rtc_write_status_t.
+*
+* \return
+* cy_en_rtc_status_t CY_RTC_SUCCESS - Set/Clear Write bit was successful <br>
+* CY_RTC_INVALID_STATE - RTC is busy with a previous update.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t writeEnable)
+{
+ cy_en_rtc_status_t retVal = CY_RTC_INVALID_STATE;
+
+ CY_ASSERT_L3(CY_RTC_IS_WRITE_VALID(writeEnable));
+
+ if(writeEnable == CY_RTC_WRITE_ENABLED)
+ {
+ /* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0
+ * or RTC Read bit is not set
+ */
+ if((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_READ, BACKUP->RTC_RW)))
+ {
+ BACKUP->RTC_RW |= BACKUP_RTC_RW_WRITE_Msk;
+ retVal = CY_RTC_SUCCESS;
+ }
+ }
+ else
+ {
+ /* Clearing Write Bit to complete write procedure */
+ BACKUP->RTC_RW &= ((uint32_t) ~BACKUP_RTC_RW_WRITE_Msk);
+
+ /* Delay to guarantee data write after clearing write bit */
+ Cy_SysLib_DelayUs(CY_RTC_DELAY_WRITE_US);
+ retVal = CY_RTC_SUCCESS;
+ }
+
+ return(retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetSyncStatus
+****************************************************************************//**
+*
+* Return current status of CY_RTC_BUSY. The status indicates
+* synchronization between the RTC user register and the actual RTC register.
+* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set
+* the Read or Write bit until CY_RTC_BUSY clears.
+*
+* \return
+* The status of RTC user register synchronization. See
+* \ref group_rtc_busy_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void)
+{
+ return((_FLD2BOOL(BACKUP_STATUS_RTC_BUSY, BACKUP->STATUS)) ? CY_RTC_BUSY : CY_RTC_AVAILABLE);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertBcdToDec
+****************************************************************************//**
+*
+* Converts an 8-bit BCD number into an 8-bit hexadecimal number. Each byte is
+* converted individually and returned as an individual byte in the 32-bit
+* variable.
+*
+* \param
+* bcdNum An 8-bit BCD number. Each byte represents BCD.
+*
+* \return
+* decNum An 8-bit hexadecimal equivalent number of the BCD number.
+*
+* For example, for 0x11223344 BCD number, the function returns
+* 0x2C in hexadecimal format.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum)
+{
+ uint32_t retVal;
+
+ retVal =
+ ((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE))
+ >> CY_RTC_BCD_NUMBER_SIZE ) * CY_RTC_BCD_DOZED_DEGREE;
+
+ retVal += bcdNum & CY_RTC_BCD_ONE_DIGIT_MASK;
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_ConvertDecToBcd
+****************************************************************************//**
+*
+* Converts an 8-bit hexadecimal number into an 8-bit BCD number. Each byte
+* is converted individually and returned as an individual byte in the 32-bit
+* variable.
+*
+* \param
+* decNum An 8-bit hexadecimal number. Each byte is represented in hex.
+* 0x11223344 -> 0x20 hex format.
+*
+* \return
+* bcdNum - An 8-bit BCD equivalent of the passed hexadecimal number.
+*
+* For example, for 0x11223344 hexadecimal number, the function returns
+* 0x20 BCD number.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_RTC_ConvertDecToBcd(uint32_t decNum)
+{
+ uint32_t retVal;
+ uint32_t tmpVal;
+
+ tmpVal = decNum % CY_RTC_BCD_HUNDRED_DEGRE;
+ retVal = ((uint32_t)(tmpVal / CY_RTC_BCD_DOZED_DEGREE)) << CY_RTC_BCD_NUMBER_SIZE;
+ retVal += tmpVal % CY_RTC_BCD_DOZED_DEGREE;
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_GetHoursFormat
+****************************************************************************//**
+*
+* Returns current 12/24 hours format.
+*
+* \note
+* Before getting the RTC current hours format, the Cy_RTC_SyncFromRtc() function
+* should be called.
+*
+* \return
+* The current RTC hours format. See \ref cy_en_rtc_hours_format_t.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void)
+{
+ return((_FLD2BOOL(BACKUP_RTC_TIME_CTRL_12HR, BACKUP->RTC_TIME)) ? CY_RTC_12_HOURS : CY_RTC_24_HOURS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_IsExternalResetOccurred
+****************************************************************************//**
+*
+* The function checks the reset cause and returns the Boolean result.
+*
+* \return
+* True if the reset reason is the power cycle and the XRES (external reset) <br>
+* False if the reset reason is other than power cycle and the XRES.
+*
+* \note Based on a return value the RTC time and date can be updated or skipped
+* after the device reset. For example, you should skip the
+* Cy_RTC_SetAlarmDateAndTime() call function if internal WDT reset occurs.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void)
+{
+ return(0u == Cy_SysLib_GetResetReason());
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncToRtcAhbDateAndTime
+****************************************************************************//**
+*
+* This function updates new time and date into the time and date RTC AHB
+* registers.
+*
+* \param timeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_TIME register: <br>
+* [0:6] - Calendar seconds in BCD, the range 0-59. <br>
+* [14:8] - Calendar minutes in BCD, the range 0-59. <br>
+* [21:16] - Calendar hours in BCD, value depends on the 12/24-hour mode. <br>
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; <br>
+* 24HR: [21:16] = 0-23. <br>
+* [22] - Selects the 12/24-hour mode: 1 - 12-hour, 0 - 24-hour. <br>
+* [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. <br>
+*
+* \param dateBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* RTC_DATE register: <br>
+* [5:0] - A calendar day of a month in BCD, the range 1-31. <br>
+* [12:8] - A calendar month in BCD, the range 1-12. <br>
+* [23:16] - A calendar year in BCD, the range 0-99. <br>
+*
+* \note Ensure that the parameters are presented in the BCD format. Use the
+* ConstructTimeDate() function to construct BCD time and date values.
+* Refer to ConstructTimeDate() function description for more details
+* about the RTC_TIME and RTC_DATE bit fields format.
+*
+* The RTC AHB registers can be updated only under condition that the
+* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
+* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
+* Do not forget to clear the RTC Write bit to finish an RTC register update by
+* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
+* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
+* retuned CY_RTC_SUCCESS.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd)
+{
+ BACKUP->RTC_TIME = timeBcd;
+ BACKUP->RTC_DATE = dateBcd;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_RTC_SyncToRtcAhbAlarm
+****************************************************************************//**
+*
+* This function updates new alarm time and date into the alarm tire and date
+* RTC AHB registers.
+*
+* \param alarmTimeBcd
+* The BCD-formatted time variable which has the same bit masks as the
+* ALMx_TIME register time fields: <br>
+* [0:6] - Alarm seconds in BCD, the range 0-59. <br>
+* [7] - Alarm seconds Enable: 0 - ignore, 1 - match. <br>
+* [14:8] - Alarm minutes in BCD, the range 0-59. <br>
+* [15] - Alarm minutes Enable: 0 - ignore, 1 - match. <br>
+* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode
+* (RTC_CTRL_12HR) <br>
+* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; <br>
+* 24HR: [21:16] = the range 0-23. <br>
+* [23] - Alarm hours Enable: 0 - ignore, 1 - match. <br>
+* [26:24] - An alarm day of the week, the range 1 - 7, where 1 - Monday. <br>
+* [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. <br>
+*
+* \param alarmDateBcd
+* The BCD-formatted date variable which has the same bit masks as the
+* ALMx_DATE register date fields: <br>
+* [5:0] - An alarm day of a month in BCD, the range 1-31. <br>
+* [7] - An alarm day of a month Enable: 0 - ignore, 1 - match. <br>
+* [12:8] - An alarm month in BCD, the range 1-12. <br>
+* [15] - An alarm month Enable: 0 - ignore, 1 - match. <br>
+* [31] - The Enable alarm: 0 - Alarm is disabled, 1 - Alarm is enabled. <br>
+*
+* \param alarmIndex
+* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
+*
+* \note Ensure that the parameters are presented in the BCD format. Use the
+* ConstructTimeDate() function to construct BCD time and date values.
+* Refer to ConstructTimeDate() function description for more details
+* about the RTC ALMx_TIME and ALMx_DATE bit-fields format.
+*
+* The RTC AHB registers can be updated only under condition that the
+* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
+* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
+* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
+* Do not forget to clear the RTC Write bit to finish an RTC register update by
+* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
+* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
+* retuned CY_RTC_SUCCESS.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex)
+{
+ CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
+
+ if(alarmIndex != CY_RTC_ALARM_2)
+ {
+ BACKUP->ALM1_TIME = alarmTimeBcd;
+ BACKUP->ALM1_DATE = alarmDateBcd;
+ }
+ else
+ {
+ BACKUP->ALM2_TIME = alarmTimeBcd;
+ BACKUP->ALM2_DATE = alarmDateBcd;
+ }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _CY_RTC_H_ */
+
+/** \} group_rtc_low_level_functions */
+/** \} group_rtc */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1302 @@
+/***************************************************************************//**
+* \file cy_sar.c
+* \version 1.10
+*
+* Provides the public functions for the API for the SAR driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "cy_sar.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+static cy_stc_sar_state_backup_t enabledBeforeSleep =
+{
+ 0uL,
+ 0uL
+};
+
+volatile int16_t Cy_SAR_offset[CY_SAR_MAX_NUM_CHANNELS];
+volatile int32_t Cy_SAR_countsPer10Volt[CY_SAR_MAX_NUM_CHANNELS];
+
+/*******************************************************************************
+* Function Name: Cy_SAR_Init
+****************************************************************************//**
+*
+* Initialize all SAR configuration registers.
+* If routing is to be configured, all switches will be cleared before
+* being initialized.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param config
+* Pointer to structure containing configuration data. See \ref cy_stc_sar_config_t
+* and guidance in the \ref group_sar_initialization section.
+*
+* \return
+* - \ref CY_SAR_SUCCESS : initialization complete
+* - \ref CY_SAR_BAD_PARAM : input pointers are null, initialization incomplete
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_INIT_CUSTOM
+*
+*******************************************************************************/
+cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config)
+{
+ CY_ASSERT_L1(NULL != base);
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_sar_status_t result;
+ uint8_t chan;
+ int32_t counts;
+ bool vrefNegSelect;
+ bool singleEndedSigned;
+ bool chanSingleEnded;
+
+ if ((NULL == base) || (NULL == config))
+ {
+ result = CY_SAR_BAD_PARAM;
+ }
+ else
+ {
+ CY_ASSERT_L2(CY_SAR_CTRL(config->ctrl));
+ CY_ASSERT_L2(CY_SAR_SAMPLE_CTRL(config->sampleCtrl));
+ CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime01));
+ CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime23));
+ CY_ASSERT_L3(CY_SAR_RANGECOND(config->rangeCond));
+ CY_ASSERT_L2(CY_SAR_CHANMASK(config->chanEn));
+ CY_ASSERT_L2(CY_SAR_INTRMASK(config->intrMask));
+ CY_ASSERT_L2(CY_SAR_CHANMASK(config->satIntrMask));
+ CY_ASSERT_L2(CY_SAR_CHANMASK(config->rangeIntrMask));
+
+ base->SAMPLE_CTRL = config->sampleCtrl;
+ base->SAMPLE_TIME01 = config->sampleTime01;
+ base->SAMPLE_TIME23 = config->sampleTime23;
+ base->RANGE_THRES = config->rangeThres;
+ base->RANGE_COND = (uint32_t)config->rangeCond << SAR_RANGE_COND_RANGE_COND_Pos;
+ base->CHAN_EN = config->chanEn;
+
+ /* Check whether NEG_SEL is set for VREF */
+ vrefNegSelect = ((uint32_t)CY_SAR_NEG_SEL_VREF == (config->ctrl & SAR_CTRL_NEG_SEL_Msk))? true : false;
+ /* Check whether single ended channels are set to signed */
+ singleEndedSigned = (SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk == (config->sampleCtrl & SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk)) ? true : false;
+
+ for (chan = 0u; chan < CY_SAR_MAX_NUM_CHANNELS; chan++)
+ {
+ CY_ASSERT_L2(CY_SAR_CHAN_CONFIG(config->chanConfig[chan]));
+
+ base->CHAN_CONFIG[chan] = config->chanConfig[chan];
+
+ counts = (int32_t) CY_SAR_WRK_MAX_12BIT;
+
+ /* For signed single ended channels with NEG_SEL set to VREF,
+ * set the offset to minus half scale to convert results to unsigned format */
+ chanSingleEnded = (0uL == (config->chanConfig[chan] & (SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk | SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk))) ? true : false;
+ if (chanSingleEnded && vrefNegSelect && singleEndedSigned)
+ {
+ Cy_SAR_offset[chan] = (int16_t) (counts / -2);
+ }
+ else
+ {
+ Cy_SAR_offset[chan] = 0;
+ }
+
+ /* Calculate gain in counts per 10 volts with rounding */
+ Cy_SAR_countsPer10Volt[chan] = (int16_t)(((counts * CY_SAR_10MV_COUNTS) + (int32_t)config->vrefMvValue) / ((int32_t)config->vrefMvValue * 2));
+ }
+ base->INTR_MASK = config->intrMask;
+ base->SATURATE_INTR_MASK = config->satIntrMask;
+ base->RANGE_INTR_MASK = config->rangeIntrMask;
+
+ /* Set routing related registers if enabled */
+ if (true == config->configRouting)
+ {
+ CY_ASSERT_L2(CY_SAR_SWITCHMASK(config->muxSwitch));
+ CY_ASSERT_L2(CY_SAR_SQMASK(config->muxSwitchSqCtrl));
+
+ /* Clear out all the switches so that only the desired switches in the config structure are set. */
+ base->MUX_SWITCH_CLEAR0 = CY_SAR_CLEAR_ALL_SWITCHES;
+
+ base->MUX_SWITCH0 = config->muxSwitch;
+ base->MUX_SWITCH_SQ_CTRL = config->muxSwitchSqCtrl;
+ }
+
+ /* Set the Cap trim if it was trimmed out of range from sflash */
+ if ((CY_SAR_CAP_TRIM_MAX == base->ANA_TRIM0) || (CY_SAR_CAP_TRIM_MIN == base->ANA_TRIM0))
+ {
+ base->ANA_TRIM0 = CY_SAR_CAP_TRIM;
+ }
+
+ /* Set the REFBUF_EN bit as this is required for proper operation. */
+ base->CTRL = config->ctrl | SAR_CTRL_REFBUF_EN_Msk;
+
+ result = CY_SAR_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_DeInit
+****************************************************************************//**
+*
+* Reset SAR registers back to power on reset defaults.
+* The \ref Cy_SAR_offset and \ref Cy_SAR_countsPer10Volt arrays are NOT reset.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param deInitRouting
+* If true, all SARMUX switches are opened and switch control registers are reset
+* to zero. If false, switch registers are untouched.
+*
+* \return
+* - \ref CY_SAR_SUCCESS : de-initialization complete
+* - \ref CY_SAR_BAD_PARAM : input pointers are null, de-initialization incomplete
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_DEINIT
+*
+*******************************************************************************/
+cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting)
+{
+ CY_ASSERT_L1(NULL != base);
+
+ cy_en_sar_status_t result;
+ uint8_t chan;
+
+ if (NULL == base)
+ {
+ result = CY_SAR_BAD_PARAM;
+ }
+ else
+ {
+ base->CTRL = CY_SAR_DEINIT;
+ base->SAMPLE_CTRL = CY_SAR_DEINIT;
+ base->SAMPLE_TIME01 = CY_SAR_SAMPLE_TIME_DEINIT;
+ base->SAMPLE_TIME23 = CY_SAR_SAMPLE_TIME_DEINIT;
+ base->RANGE_THRES = CY_SAR_DEINIT;
+ base->RANGE_COND = CY_SAR_DEINIT;
+ base->CHAN_EN = CY_SAR_DEINIT;
+ for (chan = 0u; chan < CY_SAR_MAX_NUM_CHANNELS; chan++)
+ {
+ base->CHAN_CONFIG[chan] = CY_SAR_DEINIT;
+ }
+ base->INTR_MASK = CY_SAR_DEINIT;
+ base->SATURATE_INTR_MASK = CY_SAR_DEINIT;
+ base->RANGE_INTR_MASK = CY_SAR_DEINIT;
+ if (true == deInitRouting)
+ {
+ base->MUX_SWITCH_CLEAR0 = CY_SAR_CLEAR_ALL_SWITCHES;
+ base->MUX_SWITCH_DS_CTRL = CY_SAR_DEINIT;
+ base->MUX_SWITCH_SQ_CTRL = CY_SAR_DEINIT;
+ }
+ result = CY_SAR_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_Enable
+****************************************************************************//**
+*
+* Power up the SAR ADC subsystem block. The hardware is ready to use
+* after 2 us, which is included in this function.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+void Cy_SAR_Enable(SAR_Type *base)
+{
+ if (0uL == (base->CTRL & SAR_CTRL_ENABLED_Msk))
+ {
+ while (0uL != (base->STATUS & SAR_STATUS_BUSY_Msk))
+ {
+ /* Wait for SAR to go idle to avoid deadlock */
+ }
+
+ base->CTRL |= SAR_CTRL_ENABLED_Msk;
+
+ /* The block is ready to use 2 us after the enable signal is set high. */
+ Cy_SysLib_DelayUs(CY_SAR_2US_DELAY);
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_Sleep
+****************************************************************************//**
+*
+* This is the preferred routine to prepare the hardware for Deep sleep.
+*
+* It will call \ref Cy_SAR_StopConvert to disable continuous conversions
+* and wait for SAR conversions to stop before entering Deep Sleep.
+* If the SARMUX is not configured for Deep Sleep operation, the entire SAR hardware
+* block will be turned off.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+* \funcusage
+*
+* This function is used in the \ref Cy_SAR_DeepSleepCallback. There is no
+* need to call this function directly.
+*
+*******************************************************************************/
+void Cy_SAR_Sleep(SAR_Type *base)
+{
+ uint32_t ctrlReg = base->CTRL;
+
+ enabledBeforeSleep.hwEnabled = ctrlReg & SAR_CTRL_ENABLED_Msk;
+
+ /* Turn off the reference buffer */
+ ctrlReg &= ~SAR_CTRL_REFBUF_EN_Msk;
+
+ if (SAR_CTRL_ENABLED_Msk == enabledBeforeSleep.hwEnabled)
+ {
+
+ /* Save state of CONTINUOUS bit so that conversions can be re-started upon wake-up */
+ enabledBeforeSleep.continuous = base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_CONTINUOUS_Msk;
+
+ Cy_SAR_StopConvert(base);
+
+ while (0uL != (base->STATUS & SAR_STATUS_BUSY_Msk))
+ {
+ /* Wait for SAR to stop conversions before entering low power */
+ }
+
+ /* Turn off the entire hardware block only if the SARMUX is not
+ * enabled for Deep Sleep operation. */
+ if (SAR_CTRL_DEEPSLEEP_ON_Msk != (ctrlReg & SAR_CTRL_DEEPSLEEP_ON_Msk))
+ {
+ base->CTRL &= ~SAR_CTRL_ENABLED_Msk;
+ }
+ }
+
+ base->CTRL = ctrlReg;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_Wakeup
+****************************************************************************//**
+*
+* This is the preferred routine to restore the hardware to the state after calling
+* \ref Cy_SAR_Sleep. Restoring the hardware involves re-enabling the hardware,
+* the reference buffer, and continuous scanning if it was previously
+* enabled before entering sleep.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \sideeffect
+* Calling this function without previously calling \ref Cy_SAR_Sleep can lead to
+* unpredictable results.
+*
+* \return None
+*
+* \funcusage
+*
+* This function is used in the \ref Cy_SAR_DeepSleepCallback. There is no
+* need to call this function directly.
+*
+*******************************************************************************/
+void Cy_SAR_Wakeup(SAR_Type *base)
+{
+ /* Turn on the reference buffer */
+ base->CTRL |= SAR_CTRL_REFBUF_EN_Msk;
+
+ if (SAR_CTRL_ENABLED_Msk == enabledBeforeSleep.hwEnabled)
+ {
+ Cy_SAR_Enable(base);
+
+ if (SAR_SAMPLE_CTRL_CONTINUOUS_Msk == enabledBeforeSleep.continuous)
+ {
+ Cy_SAR_StartConvert(base, CY_SAR_START_CONVERT_CONTINUOUS);
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_StartConvert
+****************************************************************************//**
+*
+* Start a single scan (one shot) of all enabled channels or start scanning
+* continuously. When in continuous mode, all firmware and hardware triggers
+* are ignored. To stop continuous scanning, call \ref Cy_SAR_StopConvert.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param startSelect
+* A value of the enum \ref cy_en_sar_start_convert_sel_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_START_CONVERT
+*
+*******************************************************************************/
+void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSelect)
+{
+ CY_ASSERT_L3(CY_SAR_STARTCONVERT(startSelect));
+
+ switch(startSelect)
+ {
+ case CY_SAR_START_CONVERT_CONTINUOUS:
+ base->SAMPLE_CTRL |= SAR_SAMPLE_CTRL_CONTINUOUS_Msk;
+ break;
+ case CY_SAR_START_CONVERT_SINGLE_SHOT:
+ default:
+ base->START_CTRL = SAR_START_CTRL_FW_TRIGGER_Msk;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_StopConvert
+****************************************************************************//**
+*
+* Stop continuous scanning of enabled channels.
+* If a conversion is currently executing, that conversion will complete,
+* but no further conversions will occur until the next call to
+* \ref Cy_SAR_StartConvert or the next hardware trigger, if enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_STOP_CONVERT
+*
+*******************************************************************************/
+void Cy_SAR_StopConvert(SAR_Type *base)
+{
+ if (SAR_SAMPLE_CTRL_CONTINUOUS_Msk == (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_CONTINUOUS_Msk))
+ {
+ base->SAMPLE_CTRL &= ~SAR_SAMPLE_CTRL_CONTINUOUS_Msk;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetConvertMode
+****************************************************************************//**
+*
+* Set the mode in which conversions are triggered. This function does
+* not start any conversions; it only configures the mode for subsequent conversions.
+*
+* There are three modes:
+* - firmware only; hardware triggering is disabled
+* - firmware and edge sensitive hardware triggering
+* - firmware and level sensitive hardware triggering
+*
+* Note that firmware triggering is always enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param mode
+* A value of the enum \ref cy_en_sar_sample_ctrl_trigger_mode_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_CONVERT_MODE
+*
+*******************************************************************************/
+void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t mode)
+{
+ CY_ASSERT_L3(CY_SAR_TRIGGER(mode));
+
+ /* Clear the TRIGGER_EN and TRIGGER_LEVEL bits */
+ uint32_t sampleCtrlReg = base->SAMPLE_CTRL & ~(SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk | SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk);
+
+ base->SAMPLE_CTRL = sampleCtrlReg | mode;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_IsEndConversion
+****************************************************************************//**
+*
+* Immediately return the status of the conversion or does not return (blocking)
+* until the conversion completes, depending on the retMode parameter.
+* In blocking mode, there is a time out of about 10 seconds for a CPU speed of
+* 100 MHz.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param retMode
+* A value of the enum \ref cy_en_sar_return_mode_t
+*
+* \return
+* - \ref CY_SAR_SUCCESS : the last conversion is complete
+* - \ref CY_SAR_CONVERSION_NOT_COMPLETE : the conversion has not completed
+* - \ref CY_SAR_TIMEOUT : the watchdog timer has expired in blocking mode
+*
+* \sideeffect
+* This function reads the end of conversion status and clears it after.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_END_CONVERSION
+*
+*******************************************************************************/
+cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_t retMode)
+{
+ CY_ASSERT_L3(CY_SAR_RETURN(retMode));
+
+ cy_en_sar_status_t result;
+
+ uint32_t endOfConversion = base->INTR & SAR_INTR_EOS_INTR_Msk;
+ uint32_t wdt = 0x1555555uL; /* Watchdog timer for blocking while loop */
+
+ switch(retMode)
+ {
+ case CY_SAR_WAIT_FOR_RESULT:
+ while((0uL == endOfConversion) && (0uL != wdt))
+ {
+ endOfConversion = base->INTR & SAR_INTR_EOS_INTR_Msk;
+ wdt--;
+ }
+ break;
+ case CY_SAR_RETURN_STATUS:
+ default:
+ break;
+ }
+
+ /* Clear the EOS bit */
+ if (SAR_INTR_EOS_INTR_Msk == endOfConversion)
+ {
+ result = CY_SAR_SUCCESS;
+ base->INTR = SAR_INTR_EOS_INTR_Msk;
+ /* Do a dummy read after write for buffered write */
+ (void) base->INTR;
+ }
+ else if (0uL == wdt)
+ {
+ result = CY_SAR_TIMEOUT;
+ }
+ else
+ {
+ result = CY_SAR_CONVERSION_NOT_COMPLETE;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_IsChannelSigned
+****************************************************************************//**
+*
+* Return true if channel result is configured for signed format, else false.
+* The formats for single-ended and differential channels are independent.
+* This function will first check whether the channel is single-ended or differential.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel to check, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \return
+* If channel number is invalid, false is returned
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_CHANNEL_SIGNED
+*
+*******************************************************************************/
+bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ bool isSigned = false;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+
+ /* Sign bits are stored separately for differential and single ended channels. */
+ if (true == Cy_SAR_IsChannelDifferential(base, chan))
+ { /* Differential channel */
+ if (SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk == (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk))
+ {
+ isSigned = true;
+ }
+ }
+ else
+ { /* Single ended channel */
+ if (SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk == (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk))
+ {
+ isSigned = true;
+ }
+ }
+ }
+
+ return isSigned;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_IsChannelSingleEnded
+****************************************************************************//**
+*
+* Return true if channel is single ended, else false
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel to check, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \return
+* If channel number is invalid, false is returned
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_CHANNEL_SE
+*
+*******************************************************************************/
+bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ bool isSingleEnded = false;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ if (0uL == (base->CHAN_CONFIG[chan] & (SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk | SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk))){
+ isSingleEnded = true;
+ }
+ }
+
+ return isSingleEnded;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetResult16
+****************************************************************************//**
+*
+* Return the data available in the channel result data register as a signed
+* 16-bit integer.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel to read the result from, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \return
+* Data is returned as a signed 16-bit integer.
+* If channel number is invalid, 0 is returned.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_RESULT16
+*
+*******************************************************************************/
+int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ uint32_t adcResult = 0uL;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ adcResult = base->CHAN_RESULT[chan] & SAR_CHAN_RESULT_RESULT_Msk;
+ }
+
+ return (int16_t) adcResult;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetResult32
+****************************************************************************//**
+*
+* Return the data available in the channel result data register as a signed
+* 32-bit integer.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel to read the result from, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \return
+* Data is returned as a signed 32-bit integer.
+* If channel number is invalid, 0 is returned.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_RESULT32
+*
+*******************************************************************************/
+int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ uint32_t adcResult = 0uL;
+ int16_t adcResult16;
+ int32_t finalResult;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ adcResult = base->CHAN_RESULT[chan] & SAR_CHAN_RESULT_RESULT_Msk;
+ }
+
+ if (true == Cy_SAR_IsChannelSigned(base, chan))
+ {
+ adcResult16 = (int16) adcResult;
+ finalResult = (int32) adcResult16;
+ }
+ else
+ {
+ finalResult = (int32) adcResult;
+ }
+
+ return finalResult;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetLowLimit
+****************************************************************************//**
+*
+* Set the low threshold for range detection. The values are interpreted
+* as signed or unsigned according to the channel configuration. Range
+* detection is done on the value stored in the result register. That is, after
+* averaging, shifting sign extension, and left/right alignment.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param lowLimit
+* The low threshold for range detection
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_LOWHIGH_LIMIT
+*
+*******************************************************************************/
+void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit)
+{
+ CY_ASSERT_L2(CY_SAR_RANGE_LIMIT(lowLimit));
+
+ uint32_t rangeThresReg;
+
+ /* Preserve the RANGE_HIGH field value when changing the RANGE_LOW field value */
+ rangeThresReg = base->RANGE_THRES & ~SAR_RANGE_THRES_RANGE_LOW_Msk;
+ rangeThresReg |= lowLimit & SAR_RANGE_THRES_RANGE_LOW_Msk;
+ base->RANGE_THRES = rangeThresReg;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetHighLimit
+****************************************************************************//**
+*
+* Set the high threshold for range detection. The values are interpreted
+* as signed or unsigned according to the channel configuration. Range
+* detection is done on the value stored in the result register. That is, after
+* averaging, shifting sign extension, and left/right alignment.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param highLimit
+* The high threshold for range detection
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_LOWHIGH_LIMIT
+*
+*******************************************************************************/
+void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit)
+{
+ CY_ASSERT_L2(CY_SAR_RANGE_LIMIT(highLimit));
+
+ uint32_t rangeThresReg;
+
+ rangeThresReg = base->RANGE_THRES & ~SAR_RANGE_THRES_RANGE_HIGH_Msk;
+ rangeThresReg |= (highLimit << SAR_RANGE_THRES_RANGE_HIGH_Pos) & SAR_RANGE_THRES_RANGE_HIGH_Msk;
+ base->RANGE_THRES = rangeThresReg;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetOffset
+****************************************************************************//**
+*
+* Override the channel offset stored in the \ref Cy_SAR_offset array
+* for the voltage conversion functions.
+*
+* Offset is applied to counts before unit scaling and gain.
+* See \ref Cy_SAR_CountsTo_Volts for more about this formula.
+*
+* To change channel 0's offset based on a known V_offset_mV, use:
+*
+* Cy_SAR_SetOffset(0uL, -1 * V_offset_mV * (1uL << Resolution) / (2 * V_ref_mV));
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1.
+*
+* \param offset
+* The count value measured when the inputs are shorted or
+* connected to the same input voltage.
+*
+* \return
+* - \ref CY_SAR_SUCCESS : offset was set successfully
+* - \ref CY_SAR_BAD_PARAM : channel number is equal to or greater than \ref CY_SAR_MAX_NUM_CHANNELS
+*
+*******************************************************************************/
+cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ cy_en_sar_status_t result = CY_SAR_BAD_PARAM;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ Cy_SAR_offset[chan] = offset;
+ result = CY_SAR_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetGain
+****************************************************************************//**
+*
+* Override the gain stored in the \ref Cy_SAR_countsPer10Volt array for the voltage conversion functions.
+* The gain is configured at initialization in \ref Cy_SAR_Init
+* based on the SARADC resolution and voltage reference.
+*
+* Gain is applied after offset and unit scaling.
+* See \ref Cy_SAR_CountsTo_Volts for more about this formula.
+*
+* To change channel 0's gain based on a known V_ref_mV, use:
+*
+* Cy_SAR_SetGain(0uL, 10000 * (1uL << Resolution) / (2 * V_ref_mV));
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1.
+*
+* \param adcGain
+* The gain in counts per 10 volt.
+*
+* \return
+* - \ref CY_SAR_SUCCESS : gain was set successfully
+* - \ref CY_SAR_BAD_PARAM : channel number is equal to or greater than \ref CY_SAR_MAX_NUM_CHANNELS
+*
+*******************************************************************************/
+cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ cy_en_sar_status_t result = CY_SAR_BAD_PARAM;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ Cy_SAR_countsPer10Volt[chan] = adcGain;
+ result = CY_SAR_SUCCESS;
+ }
+
+ return result;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_RawCounts2Counts
+****************************************************************************//**
+*
+* Convert the channel result to a consistent result after accounting for
+* averaging and subtracting the offset.
+* The equation used is:
+*
+* Counts = (RawCounts/AvgDivider - Offset)
+*
+* where,
+* - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
+* - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
+* (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
+* - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
+* - Offset: Value from \ref Cy_SAR_offset
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \param adcCounts
+* Conversion result from \ref Cy_SAR_GetResult16
+*
+* \return
+* adcCounts after averaging and offset adjustments.
+* If channel number is invalid, adcCounts is returned unmodified.
+*
+* \funcusage
+*
+* This function is used by \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts,
+* and \ref Cy_SAR_CountsTo_uVolts. Calling this function directly is usually
+* not needed.
+*
+*******************************************************************************/
+int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ uint32_t temp;
+ uint32_t averageAdcSamplesDiv;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+
+ /* Divide the adcCount when accumulate averaging mode selected */
+ if (SAR_SAMPLE_CTRL_AVG_SHIFT_Msk != (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_AVG_SHIFT_Msk))
+ { /* If Average mode != fixed */
+
+ if (SAR_CHAN_CONFIG_AVG_EN_Msk == (base->CHAN_CONFIG[chan] & SAR_CHAN_CONFIG_AVG_EN_Msk))
+ { /* If channel uses averaging */
+
+ /* Divide by 2^(AVG_CNT + 1) */
+ averageAdcSamplesDiv = (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_AVG_CNT_Msk) >> SAR_SAMPLE_CTRL_AVG_CNT_Pos;
+ averageAdcSamplesDiv = (1uL << (averageAdcSamplesDiv + 1uL));
+
+ /* If averaging mode is ACCUNDUMP (channel will be sampled back to back and averaged)
+ * divider limit is 16 */
+ if (SAR_SAMPLE_CTRL_AVG_MODE_Msk != (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_AVG_MODE_Msk))
+ {
+ if (averageAdcSamplesDiv > 16uL)
+ {
+ averageAdcSamplesDiv = 16uL;
+ }
+ }
+
+ /* If unsigned format, prevent sign extension */
+ if (false == Cy_SAR_IsChannelSigned(base, chan))
+ {
+ temp = ((uint16) adcCounts / averageAdcSamplesDiv);
+ adcCounts = (int16) temp;
+ }
+ else
+ {
+ adcCounts /= (int16) averageAdcSamplesDiv;
+ }
+ }
+ }
+
+ /* Subtract ADC offset */
+ adcCounts -= Cy_SAR_offset[chan];
+ }
+
+ return adcCounts;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_CountsTo_Volts
+****************************************************************************//**
+*
+* Convert the ADC output to Volts as a float32. For example, if the ADC
+* measured 0.534 volts, the return value would be 0.534.
+* The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
+* \ref Cy_SAR_countsPer10Volt, and other parameters.
+* The equation used is:
+*
+* V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
+*
+* where,
+* - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
+* - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
+* (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
+* - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
+* - Offset: Value from \ref Cy_SAR_offset
+* - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
+* - Gain: Value from \ref Cy_SAR_countsPer10Volt
+*
+* \note
+* This funtion is only valid when result alignment is right aligned.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \param adcCounts
+* Conversion result from \ref Cy_SAR_GetResult16
+*
+* \return
+* Result in Volts.
+* - If channel number is invalid, 0 is returned.
+* - If channel is left aligned, 0 is returned.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_VOLTS
+*
+*******************************************************************************/
+float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ float32_t result_Volts = 0.0f;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ if (SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk != (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk))
+ {
+ adcCounts = Cy_SAR_RawCounts2Counts(base, chan, adcCounts);
+
+ result_Volts = (float32_t)adcCounts * CY_SAR_10V_COUNTS;
+ result_Volts /= (float32_t)Cy_SAR_countsPer10Volt[chan];
+ }
+ }
+
+ return result_Volts;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_CountsTo_mVolts
+****************************************************************************//**
+*
+* Convert the ADC output to millivolts as an int16. For example, if the ADC
+* measured 0.534 volts, the return value would be 534.
+* The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
+* \ref Cy_SAR_countsPer10Volt, and other parameters.
+* The equation used is:
+*
+* V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
+* mV = V * 1000
+*
+* where,
+* - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
+* - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
+* (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
+* - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
+* - Offset: Value from \ref Cy_SAR_offset
+* - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
+* - Gain: Value from \ref Cy_SAR_countsPer10Volt
+*
+* \note
+* This funtion is only valid when result alignment is right aligned.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \param adcCounts
+* Conversion result from \ref Cy_SAR_GetResult16
+*
+* \return
+* Result in millivolts.
+* - If channel number is invalid, 0 is returned.
+* - If channel is left aligned, 0 is returned.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_MVOLTS
+*
+*******************************************************************************/
+int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ int32_t result_mVolts = 0;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ if (SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk != (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk))
+ {
+ adcCounts = Cy_SAR_RawCounts2Counts(base, chan, adcCounts);
+
+ result_mVolts = ((int32_t)adcCounts * CY_SAR_10MV_COUNTS);
+ if (adcCounts > 0)
+ {
+ result_mVolts += Cy_SAR_countsPer10Volt[chan] / 2;
+ }
+ else
+ {
+ result_mVolts -= Cy_SAR_countsPer10Volt[chan] / 2;
+ }
+ result_mVolts /= Cy_SAR_countsPer10Volt[chan];
+ }
+ }
+
+ return (int16_t) result_mVolts;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_CountsTo_uVolts
+****************************************************************************//**
+*
+* Convert the ADC output to microvolts as a int32. For example, if the ADC
+* measured 0.534 volts, the return value would be 534000.
+* The calculation of voltage depends on the contents of \ref Cy_SAR_offset,
+* \ref Cy_SAR_countsPer10Volt, and other parameters.
+* The equation used is:
+*
+* V = (RawCounts/AvgDivider - Offset)*TEN_VOLT/Gain
+* uV = V * 1000000
+*
+* where,
+* - RawCounts: Raw counts from SAR 16-bit CHAN_RESULT register
+* - AvgDivider: divider based on averaging mode (\ref cy_en_sar_sample_ctrl_avg_mode_t) and number of samples averaged
+* (\ref cy_en_sar_sample_ctrl_avg_cnt_t)
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM : AvgDivider is the number of samples averaged or 16, whichever is smaller
+* - \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED : AvgDivider is 1
+* - \ref CY_SAR_AVG_MODE_INTERLEAVED : AvgDivider is the number of samples averaged
+* - Offset: Value from \ref Cy_SAR_offset
+* - TEN_VOLT: 10 V constant since the gain is in counts per 10 volts.
+* - Gain: Value from \ref Cy_SAR_countsPer10Volt
+*
+* \note
+* This funtion is only valid when result alignment is right aligned.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel number, between 0 and \ref CY_SAR_MAX_NUM_CHANNELS - 1
+*
+* \param adcCounts
+* Conversion result from \ref Cy_SAR_GetResult16
+*
+* \return
+* Result in microvolts.
+* - If channel number is valid, 0 is returned.
+* - If channel is left aligned, 0 is returned.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_COUNTSTO_UVOLTS
+*
+*******************************************************************************/
+int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts)
+{
+ CY_ASSERT_L2(CY_SAR_CHANNUM(chan));
+
+ int64_t result_uVolts = 0;
+
+ if (chan < CY_SAR_MAX_NUM_CHANNELS)
+ {
+ if (SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk != (base->SAMPLE_CTRL & SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk))
+ {
+ adcCounts = Cy_SAR_RawCounts2Counts(base, chan, adcCounts);
+ result_uVolts = (int64_t)adcCounts * CY_SAR_10UV_COUNTS;
+ result_uVolts /= Cy_SAR_countsPer10Volt[chan];
+ }
+ }
+
+ return (int32_t)result_uVolts;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetAnalogSwitch
+****************************************************************************//**
+*
+* Provide firmware control of the SARMUX switches for firmware sequencing.
+* Each call to this function can open or close a set of switches.
+* Previously configured switches are untouched.
+*
+* If the SARSEQ is enabled, there is no need to use this function.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchSelect
+* The switch register that contains the desired switches. Select a value
+* from \ref cy_en_sar_switch_register_sel_t.
+*
+* \param switchMask
+* The mask of the switches to either open or close.
+* Select one or more values from the \ref cy_en_sar_mux_switch_fw_ctrl_t enum
+* and "OR" them together.
+*
+* \param state
+* Open or close the desired swithces. Select a value from \ref cy_en_sar_switch_state_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_ANALOG_SWITCH
+*
+*******************************************************************************/
+void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_sar_switch_state_t state)
+{
+ CY_ASSERT_L3(CY_SAR_SWITCHSELECT(switchSelect));
+ CY_ASSERT_L2(CY_SAR_SWITCHMASK(switchMask));
+ CY_ASSERT_L3(CY_SAR_SWITCHSTATE(state));
+
+ __IOM uint32_t *switchReg;
+ __IOM uint32_t *switchClearReg;
+
+ switch(switchSelect)
+ {
+ case CY_SAR_MUX_SWITCH0:
+ default:
+ switchReg = &base->MUX_SWITCH0;
+ switchClearReg = &base->MUX_SWITCH_CLEAR0;
+ break;
+ }
+
+ switch(state)
+ {
+ case CY_SAR_SWITCH_CLOSE:
+ *switchReg |= switchMask;
+ break;
+ case CY_SAR_SWITCH_OPEN:
+ default:
+
+ /* Unlike the close case, we are not OR'ing the register. Set 1 to clear.*/
+ *switchClearReg = switchMask;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetAnalogSwitch
+****************************************************************************//**
+*
+* Return the state (open or close) of SARMUX switches.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchSelect
+* The switch register that contains the desired switches. Select a value
+* from \ref cy_en_sar_switch_register_sel_t.
+*
+* \return
+* Each bit corresponds to a single switch, where a bit value of 0 is open
+* and 1 is closed.
+* Compare this value to the switch masks in \ref cy_en_sar_mux_switch_fw_ctrl_t.
+*
+*******************************************************************************/
+uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect)
+{
+ CY_ASSERT_L3(CY_SAR_SWITCHSELECT(switchSelect));
+
+ uint32_t switchRegValue;
+
+ switch(switchSelect)
+ {
+ case CY_SAR_MUX_SWITCH0:
+ default:
+ switchRegValue = base->MUX_SWITCH0;
+ break;
+ }
+
+ return switchRegValue;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetSwitchSarSeqCtrl
+****************************************************************************//**
+*
+* Enable or disable SARSEQ control of one or more switches.
+* Previously configured switches are untouched.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param switchMask
+* The mask of the switches.
+* Select one or more values from the \ref cy_en_sar_mux_switch_sq_ctrl_t enum
+* and "OR" them together.
+*
+* \param ctrl
+* Enable or disable SARSEQ control. Select a value from \ref cy_en_sar_switch_sar_seq_ctrl_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_SET_SWITCH_SAR_SEQ_CTRL
+*
+*******************************************************************************/
+void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl)
+{
+ CY_ASSERT_L2(CY_SAR_SQMASK(switchMask));
+ CY_ASSERT_L3(CY_SAR_SQCTRL(ctrl));
+
+ switch(ctrl)
+ {
+ case CY_SAR_SWITCH_SEQ_CTRL_ENABLE:
+ base->MUX_SWITCH_SQ_CTRL |= switchMask;
+ break;
+ case CY_SAR_SWITCH_SEQ_CTRL_DISABLE:
+ default:
+ base->MUX_SWITCH_SQ_CTRL &= ~switchMask;
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback to prepare the SAR before entering Deep Sleep
+* and to re-enable the SAR after exiting Deep Sleep.
+*
+* \param callbackParams
+* Pointer to structure of type \ref cy_stc_syspm_callback_params_t
+*
+* \return
+* See \ref cy_en_syspm_status_t
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_DEEPSLEEP_CALLBACK
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t returnValue = CY_SYSPM_SUCCESS;
+
+ if (CY_SYSPM_BEFORE_TRANSITION == callbackParams->mode)
+ { /* Actions that should be done before entering the Deep Sleep mode */
+ Cy_SAR_Sleep((SAR_Type *)callbackParams->base);
+ }
+ else if (CY_SYSPM_AFTER_TRANSITION == callbackParams->mode)
+ { /* Actions that should be done after exiting the Deep Sleep mode */
+ Cy_SAR_Wakeup((SAR_Type *)callbackParams->base);
+ }
+ else
+ { /* Does nothing in other modes */
+ }
+
+ return returnValue;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2074 @@
+/***************************************************************************//**
+* \file cy_sar.h
+* \version 1.10
+*
+* Header file for the SAR driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_sar SAR ADC Subsystem (SAR)
+* \{
+* This driver configures and controls the SAR ADC subsystem block.
+*
+* This SAR ADC subsystem is comprised of:
+* - a 12-bit SAR converter (SARADC)
+* - an embedded reference block (SARREF)
+* - a mux (\ref group_sar_sarmux "SARMUX") at the inputs of the converter
+* - a sequence controller (\ref group_sar_sarmux "SARSEQ") that enables multi-channel acquisition
+* in a round robin fashion, without CPU intervention, to maximize scan rates.
+*
+* \image html sar_block_diagram.png
+*
+* The high level features of the subsystem are:
+* - maximum sample rate of 1 Msps
+* - Sixteen individually configurable channels (depends on device routing capabilities)
+* - per channel selectable
+* - single-ended or differential input mode
+* - input from external pin (8 channels in single-ended mode or 4 channels in differential mode)
+* or from internal signals (AMUXBUS, CTB, Die Temperature Sensor)
+* - choose one of four programmable acquisition times
+* - averaging and accumulation
+* - scan can be triggered by firmware or hardware in single shot or continuous mode
+* - hardware averaging from 2 to 256 samples
+* - selectable voltage references
+* - internal VDDA and VDDA/2 references
+* - buffered 1.2 V bandgap reference from \ref group_sysanalog "AREF"
+* - external reference from dedicated pin
+* - Interrupt generation
+*
+* \section group_sar_usage Usage
+*
+* The high level steps to use this driver are:
+*
+* -# \ref group_sar_initialization
+* -# \ref group_sar_trigger_conversions
+* -# \ref group_sar_handle_interrupts
+* -# \ref group_sar_retrieve_result
+*
+* \section group_sar_initialization Initialization and Enable
+*
+* To configure the SAR subsystem, call \ref Cy_SAR_Init. Pass in a pointer to the \ref SAR_Type
+* structure for the base hardware register address and pass in the configuration structure,
+* \ref cy_stc_sar_config_t.
+*
+* After initialization, call \ref Cy_SAR_Enable to enable the hardware.
+*
+* Here is guidance on how to set the data fields of the configuration structure:
+*
+* \subsection group_sar_init_struct_ctrl uint32_t ctrl
+*
+* This field specifies configurations that apply to all channels such as the Vref
+* source or the negative terminal selection for all single-ended channels.
+* Select a value from each of the following enums that begin with "cy_en_sar_ctrl_" and "OR" them together.
+* - \ref cy_en_sar_ctrl_pwr_ctrl_vref_t
+* - \ref cy_en_sar_ctrl_vref_sel_t
+* - \ref cy_en_sar_ctrl_bypass_cap_t
+* - \ref cy_en_sar_ctrl_neg_sel_t
+* - \ref cy_en_sar_ctrl_hw_ctrl_negvref_t
+* - \ref cy_en_sar_ctrl_comp_delay_t
+* - \ref cy_en_sar_ctrl_comp_pwr_t
+* - \ref cy_en_sar_ctrl_sarmux_deep_sleep_t
+* - \ref cy_en_sar_ctrl_sarseq_routing_switches_t
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SAR_CTRL
+*
+* \subsection group_sar_init_struct_sampleCtrl uint32_t sampleCtrl
+*
+* This field configures sampling details that apply to all channels.
+* Select a value from each of the following enums that begin with "cy_en_sar_sample_" and "OR" them together.
+* - \ref cy_en_sar_sample_ctrl_result_align_t
+* - \ref cy_en_sar_sample_ctrl_single_ended_format_t
+* - \ref cy_en_sar_sample_ctrl_differential_format_t
+* - \ref cy_en_sar_sample_ctrl_avg_cnt_t
+* - \ref cy_en_sar_sample_ctrl_avg_mode_t
+* - \ref cy_en_sar_sample_ctrl_trigger_mode_t
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SAMPLE_CTRL
+*
+* \subsection group_sar_init_struct_sampleTime01 uint32_t sampleTime01
+*
+* This field configures the value for sample times 0 and 1 in ADC clock cycles.
+*
+* The SAR has four programmable 10-bit aperture times that are configured using two data fields,
+* \ref group_sar_init_struct_sampleTime01 and
+* \ref group_sar_init_struct_sampleTime23.
+* Ten bits allow for a range of 0 to 1023 cycles, however 0 and 1 are invalid.
+* The minimum aperture time is 167 ns. With an 18 MHz ADC clock, this is
+* equal to 3 cycles or a value of 4 in this field. The actual aperture time is one cycle less than
+* the value stored in this field.
+*
+* Use the shifts defined in \ref cy_en_sar_sample_time_shift_t.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SAMPLE_TIME01
+*
+* \subsection group_sar_init_struct_sampleTime23 uint32_t sampleTime23
+*
+* This field configures the value for sample times 2 and 3 in ADC clock cycles.
+* Use the shifts defined in \ref cy_en_sar_sample_time_shift_t.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SAMPLE_TIME23
+*
+* \subsection group_sar_init_struct_rangeThres uint32_t rangeThres
+*
+* This field configures the upper and lower thresholds for the range interrupt.
+* These thresholds apply on a global level for all channels with range detection enabled.
+*
+* The SARSEQ supports range detection to allow for automatic detection of sample values
+* compared to two programmable thresholds without CPU involvement.
+* Range detection is done after averaging, alignment, and sign extension (if applicable). In other words the
+* threshold values need to have the same data format as the result data.
+* The values are interpreted as signed or unsigned according to each channel's configuration.
+*
+* Use the shifts defined in \ref cy_en_sar_range_thres_shift_t.
+*
+* The \ref Cy_SAR_SetLowLimit and \ref Cy_SAR_SetHighLimit provide run-time configurability of these thresholds.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_RANGE_THRES
+*
+* \subsection group_sar_init_struct_rangeCond cy_en_sar_range_detect_condition_t rangeCond
+*
+* This field configures the condition (below, inside, outside, or above) that will trigger
+* the range interrupt. Select a value from the \ref cy_en_sar_range_detect_condition_t enum.
+*
+* \subsection group_sar_init_struct_chanEn uint32_t chanEn
+*
+* This field configures which channels will be scanned.
+* Each bit corresponds to a channel. Bit 0 enables channel 0, bit 1 enables channel 1,
+* bit 2 enables channel 2, and so on.
+*
+* \subsection group_sar_init_struct_chanConfig uint32_t chanConfig[16]
+*
+* Each channel has its own channel configuration register.
+* The channel configuration specifies which pin/signal is connected to that channel
+* and how the channel is sampled.
+*
+* Select a value from each of the following enums that begin with "cy_en_sar_chan_config_" and "OR" them together.
+*
+* - \ref cy_en_sar_chan_config_input_mode_t
+* - \ref cy_en_sar_chan_config_pos_pin_addr_t
+* - \ref cy_en_sar_chan_config_pos_port_addr_t
+* - \ref cy_en_sar_chan_config_avg_en_t
+* - \ref cy_en_sar_chan_config_sample_time_t
+* - \ref cy_en_sar_chan_config_neg_pin_addr_t
+* - \ref cy_en_sar_chan_config_neg_port_addr_t
+*
+* Some important considerations are:
+* - The POS_PORT_ADDR and POS_PIN_ADDR bit fields are used by the SARSEQ to select
+* the connection to the positive terminal (Vplus) of the ADC for each channel.
+* - When the channel is an unpaired differential input (\ref CY_SAR_CHAN_DIFFERENTIAL_UNPAIRED), the
+* NEG_PORT_ADDR and NEG_PIN_ADDR are used by the SARSEQ to select the connection
+* to the negative terminal (Vminus) of the ADC.
+* - When the channel is a differential input pair (\ref CY_SAR_CHAN_DIFFERENTIAL_PAIRED), the NEG_PORT_ADDR and NEG_PIN_ADDR are ignored.
+* For differential input pairs, only the pin for the positive terminal needs to be
+* specified and this pin must be even. For example, Pin 0 (positive terminal) and Pin 1 (negative terminal)
+* are a pair. Pin 2 (positive terminal) and Pin 3 (negative terminal) are a pair.
+*
+* If the SARSEQ is disabled (\ref cy_en_sar_ctrl_sarseq_routing_switches_t) or
+* it is not controlling any switches (\ref group_sar_init_struct_muxSwitchSqCtrl = 0), the port and pin addresses
+* are ignored. This is possible when there is only one channel to scan.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_CHAN_CONFIG
+*
+* \subsection group_sar_init_struct_intrMask uint32_t intrMask
+*
+* This field configures which interrupt events (end of scan, overflow, or firmware collision) will be serviced by the firmware.
+*
+* Select one or more values from the \ref cy_en_sar_intr_mask_t enum and "OR" them
+* together.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_INTR_MASK
+*
+* \subsection group_sar_init_struct_satIntrMask uint32_t satIntrMask
+*
+* This field configures which channels will cause a saturation interrupt.
+*
+* The SARSEQ has a saturation detect that is always applied to every conversion.
+* This feature detects whether a channel's sample value is equal to the minimum or maximum values.
+* This allows the firmware to take action, for example, discard the result, when the SARADC saturates.
+* The sample value is tested right after conversion, that is, before averaging. This means that it
+* can happen that the interrupt is set while the averaged result in the data register is not
+* equal to the minimum or maximum.
+*
+* Each bit corresponds to a channel. A value of 0 disables saturation detection for all channels.
+*
+* \subsection group_sar_init_struct_rangeIntrMask uint32_t rangeIntrMask
+*
+* This field configures which channels will cause a range detection interrupt.
+* Each bit corresponds to a channel. A value of 0 disables range detection for all channels.
+*
+* \subsection group_sar_init_struct_muxSwitch uint32_t muxSwitch
+*
+* This field is the firmware control of the SARMUX switches.
+*
+* Use one or more values from the \ref cy_en_sar_mux_switch_fw_ctrl_t enum and "OR" them together.
+* If the SARSEQ is enabled, the SARMUX switches that will be used must
+* also be closed using this firmware control.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_MUX_SWITCH
+*
+* Firmware control can be changed at run-time by calling \ref Cy_SAR_SetAnalogSwitch with \ref CY_SAR_MUX_SWITCH0
+* and the desired switch states.
+*
+* \subsection group_sar_init_struct_muxSwitchSqCtrl uint32_t muxSwitchSqCtrl
+*
+* This field enables or disables SARSEQ control of the SARMUX switches.
+* To disable control of all switches, set this field to 0. To disable the SARSEQ all together,
+* use \ref CY_SAR_SARSEQ_SWITCH_DISABLE when configuring the \ref group_sar_init_struct_ctrl register.
+*
+* Use one or more values from the \ref cy_en_sar_mux_switch_sq_ctrl_t enum and "OR" them together.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_MUX_SQ_CTRL
+*
+* SARSEQ control can be changed at run-time by calling \ref Cy_SAR_SetSwitchSarSeqCtrl.
+*
+* \subsection group_sar_init_struct_configRouting bool configRouting
+*
+* If true, the \ref group_sar_init_struct_muxSwitch and \ref group_sar_init_struct_muxSwitchSqCtrl fields
+* will be used. If false, the fields will be ignored.
+*
+* \subsection group_sar_init_struct_vrefMvValue uint32_t vrefMvValue
+*
+* This field sets the value of the reference voltage in millivolts used. This value
+* is used for converting counts to volts in the \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, and
+* \ref Cy_SAR_CountsTo_uVolts functions.
+*
+* \section group_sar_trigger_conversions Triggering Conversions
+*
+* The SAR subsystem has the following modes for triggering a conversion:
+* <table class="doxtable">
+* <tr>
+* <th>Mode</th>
+* <th>Description</th>
+* <th>Usage</th>
+* </tr>
+* <tr>
+* <td>Continuous</td>
+* <td>After completing a scan, the
+* SARSEQ will immediately start the next scan. That is, the SARSEQ will always be BUSY.
+* As a result all other triggers, firmware or hardware, are essentially ignored.
+* </td>
+* <td>To enter this mode, call \ref Cy_SAR_StartConvert with \ref CY_SAR_START_CONVERT_CONTINUOUS.
+* To stop continuous conversions, call \ref Cy_SAR_StopConvert.
+* </td>
+* </tr>
+* <tr>
+* <td>Firmware single shot</td>
+* <td>A single conversion of all enabled channels is triggered with a function call to \ref Cy_SAR_StartConvert with
+* \ref CY_SAR_START_CONVERT_SINGLE_SHOT.
+* </td>
+* <td>
+* Firmware triggering is always available by calling \ref Cy_SAR_StartConvert with \ref CY_SAR_START_CONVERT_SINGLE_SHOT.
+* To allow only firmware triggering, or disable
+* hardware triggering, set up the \ref cy_stc_sar_config_t config structure with \ref CY_SAR_TRIGGER_MODE_FW_ONLY.
+* </td>
+* </tr>
+* <tr>
+* <td>Hardware edge sensitive</td>
+* <td>A single conversion of all enabled channels is triggered on the rising edge of the hardware
+* trigger signal.</td>
+* <td>To enable this mode, set up the \ref cy_stc_sar_config_t config structure with
+* \ref CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE.</td>
+* </tr>
+* <tr>
+* <td>Hardware level sensitive</td>
+* <td>Conversions are triggered continuously when the hardware trigger signal is high.</td>
+* <td>To enable this mode, set up the \ref cy_stc_sar_config_t config structure with
+* \ref CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL.</td>
+* </tr>
+* </table>
+*
+* The trigger mode can be changed during run time with \ref Cy_SAR_SetConvertMode.
+*
+* For the hardware trigger modes, use the \ref group_trigmux driver to route an internal or external
+* signal to the SAR trigger input.
+* When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enum, TRIG6_OUT_PASS_TR_SAR_IN,
+* for the SAR trigger input.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_CONFIG_TRIGGER
+*
+* \section group_sar_handle_interrupts Handling Interrupts
+*
+* The SAR can generate interrupts on these events:
+*
+* - End of scan (EOS): when scanning of all enabled channels complete.
+* - Overflow: when the result register is updated before the previous result is read.
+* - FW collision: when a new trigger is received while the SAR is still processing the previous trigger.
+* - Saturation detection: when the channel result is equal to the minimum or maximum value.
+* - Range detection: when the channel result meets the programmed upper or lower threshold values.
+*
+* The SAR interrupt to the NVIC is raised any time the intersection (logic and) of the interrupt
+* flags and the corresponding interrupt masks are non-zero.
+*
+* Implement an interrupt routine and assign it to the SAR interrupt.
+* Use the pre-defined enum, pass_interrupt_sar_IRQn, as the interrupt source for the SAR.
+*
+* The following code snippet demonstrates how to implement a routine to handle the interrupt.
+* The routine gets called when any one of the SAR interrupts are triggered.
+* When servicing an interrupt, the user must clear the interrupt so that subsequent
+* interrupts can be handled.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_ISR
+*
+* The following code snippet demonstrates how to configure and enable the interrupt.
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_CONFIG_INTR
+*
+* Alternately, instead of handling the interrupts, the \ref Cy_SAR_IsEndConversion function
+* allows for firmware polling of the end of conversion status.
+*
+* \section group_sar_retrieve_result Retrieve Channel Results
+*
+* Retrieve the ADC result by calling \ref Cy_SAR_GetResult16 with the desired channel.
+* To convert the result to a voltage, pass the ADC result to \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, or
+* \ref Cy_SAR_CountsTo_uVolts.
+*
+* \section group_sar_clock SAR Clock Configuration
+*
+* The SAR requires a clock. Assign a clock to the SAR using the
+* pre-defined enum, PCLK_PASS_CLOCK_SAR, to identify the SAR subsystem.
+* Set the clock divider value to achieve the desired clock rate. The SAR can support
+* a maximum frequency of 18 MHz.
+*
+* \snippet sar_sut_01.cydsn/main_cm4.c SAR_SNIPPET_CONFIGURE_CLOCK
+*
+* \section group_sar_scan_time Scan Rate
+*
+* The scan rate is dependent on the following:
+*
+* - ADC clock rate
+* - Number of channels
+* - Averaging
+* - Resolution
+* - Acquisition times
+*
+* \subsection group_sar_acquisition_time Acquisition Time
+*
+* The acquisition time of a channel is based on which of the four global aperture times are selected for that
+* channel. The selection is done during initialization per channel with \ref group_sar_init_struct_chanConfig.
+* The four global aperture times are also set during initialization with \ref group_sar_init_struct_sampleTime01 and
+* \ref group_sar_init_struct_sampleTime23. Note that these global aperture times are in SAR clock cycles and the
+* acquisition time is 1 less than that value in the register.
+*
+* \image html sar_acquisition_time_eqn.png
+*
+* \subsection group_sar_channel_sample_time Channel Sample Time
+*
+* The sample time for a channel is the time required to acquire the analog signal
+* and convert it to a digital code.
+*
+* \image html sar_channel_sample_time_eqn.png
+*
+* The SAR ADC is a 12-bit converter so Resolution = 12.
+*
+* \subsection group_sar_total_scan_time Total Scan Time
+*
+* Channels using one of the sequential averaging modes (\ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM or \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED)
+* are sampled multiple times per scan. The number of samples averaged are set during initialization
+* with \ref group_sar_init_struct_sampleCtrl using one of the values from \ref cy_en_sar_sample_ctrl_avg_cnt_t.
+* Channels that are not averaged or use the \ref CY_SAR_AVG_MODE_INTERLEAVED mode are only sampled once per scan.
+*
+* The total scan time is the sum of each channel's sample time multiplied by the samples per scan.
+*
+* \image html sar_scan_rate_eqn.png
+*
+* where N is the total number of channels in the scan.
+*
+* \section group_sar_sarmux SARMUX and SARSEQ
+*
+* The SARMUX is an analog programmable multiplexer. Its switches can be controlled by the SARSEQ or firmware.
+* and the inputs can come from:
+* - a dedicated port (can support 8 single-ended channels or 4 differential channels)
+* - an internal die temperature (DieTemp) sensor
+* - CTB output via SARBUS0/1 (if CTBs are available on the device)
+* - AMUXBUSA/B
+*
+* The following figure shows the SARMUX switches. See the device datasheet for the exact location of SARMUX pins.
+*
+* \image html sar_sarmux_switches.png
+*
+* When using the SARSEQ, the following configurations must be performed:
+* - enable SARSEQ control of required switches (see \ref group_sar_init_struct_muxSwitchSqCtrl)
+* - close the required switches with firmware (see \ref group_sar_init_struct_muxSwitch)
+* - configure the POS_PORT_ADDR and POS_PIN_ADDR, and if used, the NEG_PORT_ADDR and NEG_PIN_ADDR (see \ref group_sar_init_struct_chanConfig)
+*
+* While firmware can control every switch in the SARMUX, not every switch can be controlled by the SARSEQ (green switches in the above figure).
+* Additionally, switches outside of the SARMUX such as the AMUXBUSA/B switches or
+* CTB switches will require separate function calls (see \ref group_gpio "GPIO" and \ref group_ctb "CTB" drivers).
+* The SARSEQ can control three switches in the \ref group_ctb "CTB" driver (see \ref Cy_CTB_EnableSarSeqCtrl).
+* These switches need to be enabled for SARSEQ control if the CTB outputs are used as the SARMUX inputs.
+*
+* The following table shows the required POS_PORT_ADDR and POS_PIN_ADDR settings
+* for different input connections.
+*
+* <table class="doxtable">
+* <tr>
+* <th>Input Connection Selection</th>
+* <th>POS_PORT_ADDR</th>
+* <th>POS_PIN_ADDR</th>
+* </tr>
+* <tr>
+* <td>SARMUX dedicated port</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_0 through \ref CY_SAR_CHAN_POS_PIN_ADDR_7</td>
+* </tr>
+* <tr>
+* <td>DieTemp sensor</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_0</td>
+* </tr>
+* <tr>
+* <td>AMUXBUSA</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_2</td>
+* </tr>
+* <tr>
+* <td>AMUXBUSB</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_3</td>
+* </tr>
+* <tr>
+* <td>CTB0 Opamp0 1x output</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_CTB0</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_2</td>
+* </tr>
+* <tr>
+* <td>CTB0 Opamp1 1x output</td>
+* <td>\ref CY_SAR_POS_PORT_ADDR_CTB0</td>
+* <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_3</td>
+* </tr>
+* </table>
+*
+* \subsection group_sar_sarmux_dietemp Input from DieTemp sensor
+*
+* When using the DieTemp sensor, always use single-ended mode.
+* The temperature sensor can be routed to Vplus using the \ref CY_SAR_MUX_FW_TEMP_VPLUS switch.
+* Connecting this switch will also enable the sensor. Set the \ref group_sar_acquisition_time "acquisition time" to
+* be at least 1 us to meet the settling time of the temperature sensor.
+*
+* \image html sar_sarmux_dietemp.png
+*
+* \snippet sar_sut_02.cydsn/main_cm4.c SNIPPET_SAR_SARMUX_DIETEMP
+*
+* \subsection group_sar_sarmux_se_diff Input from SARMUX port
+*
+* The following figure and code snippet show how two GPIOs on the SARMUX dedicated port
+* are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
+*
+* \image html sar_sarmux_dedicated_port.png
+*
+* \snippet sar_sut_02.cydsn/main_cm4.c SNIPPET_SAR_SARMUX_SE_DIFF
+*
+* \subsection group_sar_sarmux_ctb Input from CTB output visa SARBUS0/1
+*
+* The following figure and code snippet show how the two opamp outputs from the CTB
+* are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
+* Note that separate function calls are needed to configure and enable the opamps, perform required analog routing,
+* and enable SARSEQ control of the switches contained in the CTB.
+*
+* \image html sar_sarmux_ctb.png
+*
+* \snippet sar_sut_02.cydsn/main_cm4.c SNIPPET_SAR_SARMUX_CTB
+*
+* \subsection group_sar_sarmux_amuxbus Input from other pins through AMUXBUSA/B
+*
+* The following figure and code snippet show how two GPIOs on any port through the AMUXBUSA and AMUXBUSB
+* are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
+* Note that separate function calls are needed to route the device pins to the SARMUX. The AMUXBUSes
+* are separated into multiple segments and these segments are connected/disconnected using the AMUX_SPLIT_CTL
+* registers in the HSIOM. In the following code snippet, to connect Port 1 to the SARMUX, the left and right
+* switches of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6] need to be closed.
+*
+* \image html sar_sarmux_amuxbus.png
+*
+* \snippet sar_sut_02.cydsn/main_cm4.c SNIPPET_SAR_SARMUX_AMUXBUS
+*
+* \section group_sar_low_power Low Power Support
+* This SAR driver provides a callback function to handle power mode transitions.
+* The \ref Cy_SAR_DeepSleepCallback function ensures that SAR conversions are stopped
+* before Deep Sleep entry. Upon wakeup, the callback
+* enables the hardware and continuous conversions, if previously enabled.
+*
+* To trigger the callback execution, the callback must be registered before calling \ref Cy_SysPm_DeepSleep. Refer to
+* \ref group_syspm driver for more information about power mode transitions and
+* callback registration.
+*
+* Recall that during configuration of the \ref group_sar_init_struct_ctrl "ctrl" field,
+* the SARMUX can be configured to remain enabled in Deep Sleep mode.
+* All other blocks (SARADC, REFBUF, and SARSEQ) do not support Deep Sleep mode operation.
+*
+* \section group_sar_more_information More Information
+* For more information on the SAR ADC subsystem, refer to the technical reference manual (TRM).
+*
+* \section group_sar_MISRA MISRA-C Compliance]
+*
+* This driver has the following specific deviations:
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>Advisory</td>
+* <td>A cast should not be performed between a pointer to object type and a different pointer to object type.</td>
+* <td>The cy_syspm driver defines the pointer to void in the \ref cy_stc_syspm_callback_params_t.base field.
+* This SAR driver implements a Deep Sleep callback conforming to the cy_syspm driver requirements.
+* When the callback is called, the base should point to the SAR_Type register address.
+* </td>
+* </tr>
+* </table>
+*
+* \section group_sar_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="3">1.10</td>
+* <td> Added workaround for parts with out of range CAP_TRIM in Init API.</td>
+* <td> Correct CAP_TRIM is necessary achieving specified SAR ADC linearity</td>
+* </tr>
+* <tr>
+* <td> Turn off the entire hardware block only if the SARMUX is not enabled
+* for Deep Sleep operation.
+* </td>
+* <td> Improvement of the \ref Cy_SAR_Sleep flow</td>
+* </tr>
+* <tr>
+* <td>Updated "Low Power Support" section to describe registering the Deep Sleep callback.
+* Added parenthesis around logical AND operation in Sleep API.</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sar_macros Macros
+* \defgroup group_sar_functions Functions
+* \{
+* \defgroup group_sar_functions_basic Initialization and Basic Functions
+* \defgroup group_sar_functions_power Low Power Callback
+* \defgroup group_sar_functions_config Run-time Configuration Functions
+* \defgroup group_sar_functions_countsto Counts Conversion Functions
+* \defgroup group_sar_functions_interrupt Interrupt Functions
+* \defgroup group_sar_functions_switches SARMUX Switch Control Functions
+* \defgroup group_sar_functions_helper Useful Configuration Query Functions
+* \}
+* \defgroup group_sar_globals Global Variables
+* \defgroup group_sar_data_structures Data Structures
+* \defgroup group_sar_enums Enumerated Types
+* \{
+* \defgroup group_sar_ctrl_register_enums Control Register Enums
+* \defgroup group_sar_sample_ctrl_register_enums Sample Control Register Enums
+* \defgroup group_sar_sample_time_shift_enums Sample Time Register Enums
+* \defgroup group_sar_range_thres_register_enums Range Interrupt Register Enums
+* \defgroup group_sar_chan_config_register_enums Channel Configuration Register Enums
+* \defgroup group_sar_intr_mask_t_register_enums Interrupt Mask Register Enums
+* \defgroup group_sar_mux_switch_register_enums SARMUX Switch Control Register Enums
+* \}
+*/
+
+#if !defined(CY_SAR_H)
+#define CY_SAR_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXS40PASS_SAR
+ #error "The SAR driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** \addtogroup group_sar_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SAR_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_SAR_DRV_VERSION_MINOR 10
+
+/** SAR driver identifier */
+#define CY_SAR_ID CY_PDL_DRV_ID(0x01u)
+
+/** Maximum number of channels */
+#define CY_SAR_MAX_NUM_CHANNELS (PASS_SAR_SAR_CHANNELS)
+
+/** \cond INTERNAL */
+#define CY_SAR_DEINIT (0uL) /**< De-init value for most SAR registers */
+#define CY_SAR_SAMPLE_TIME_DEINIT ((3uL << SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos) | (3uL << SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos)) /**< De-init value for the SAMPLE_TIME* registers */
+#define CY_SAR_CLEAR_ALL_SWITCHES (0x3FFFFFFFuL) /**< Value to clear all SARMUX switches */
+#define CY_SAR_DEINIT_SQ_CTRL (SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk \
+ | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk)
+#define CY_SAR_REG_CTRL_MASK (SAR_CTRL_PWR_CTRL_VREF_Msk \
+ | SAR_CTRL_VREF_SEL_Msk \
+ | SAR_CTRL_VREF_BYP_CAP_EN_Msk \
+ | SAR_CTRL_NEG_SEL_Msk \
+ | SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk \
+ | SAR_CTRL_COMP_DLY_Msk \
+ | SAR_CTRL_REFBUF_EN_Msk \
+ | SAR_CTRL_COMP_PWR_Msk \
+ | SAR_CTRL_DEEPSLEEP_ON_Msk \
+ | SAR_CTRL_DSI_SYNC_CONFIG_Msk \
+ | SAR_CTRL_DSI_MODE_Msk \
+ | SAR_CTRL_SWITCH_DISABLE_Msk \
+ | SAR_CTRL_ENABLED_Msk)
+#define CY_SAR_REG_SAMPLE_CTRL_MASK (SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk \
+ | SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk \
+ | SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk \
+ | SAR_SAMPLE_CTRL_AVG_CNT_Msk \
+ | SAR_SAMPLE_CTRL_AVG_SHIFT_Msk \
+ | SAR_SAMPLE_CTRL_AVG_MODE_Msk \
+ | SAR_SAMPLE_CTRL_CONTINUOUS_Msk \
+ | SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk \
+ | SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk \
+ | SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk \
+ | SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk \
+ | SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk \
+ | SAR_SAMPLE_CTRL_VALID_SEL_Msk \
+ | SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk \
+ | SAR_SAMPLE_CTRL_VALID_IGNORE_Msk \
+ | SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk \
+ | SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk)
+#define CY_SAR_REG_CHAN_CONFIG_MASK (SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk \
+ | SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk \
+ | SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk \
+ | SAR_CHAN_CONFIG_AVG_EN_Msk \
+ | SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk \
+ | SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk \
+ | SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk \
+ | SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk \
+ | SAR_CHAN_CONFIG_DSI_OUT_EN_Msk)
+#define CY_SAR_REG_SAMPLE_TIME_MASK (SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk | SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk)
+
+#define CY_SAR_2US_DELAY (2u) /**< Delay used in Enable API function to avoid SAR deadlock */
+#define CY_SAR_10V_COUNTS (10.0F) /**< Value of 10 in volts */
+#define CY_SAR_10MV_COUNTS (10000) /**< Value of 10 in millivolts */
+#define CY_SAR_10UV_COUNTS (10000000L) /**< Value of 10 in microvolts */
+#define CY_SAR_WRK_MAX_12BIT (0x00001000uL) /**< Maximum SAR work register value for a 12-bit resolution */
+#define CY_SAR_RANGE_LIMIT_MAX (0xFFFFuL) /**< Maximum value for the low and high range interrupt threshold values */
+#define CY_SAR_CAP_TRIM_MAX (0x3FuL) /**< Maximum value for CAP_TRIM */
+#define CY_SAR_CAP_TRIM_MIN (0x00uL) /**< Maximum value for CAP_TRIM */
+#define CY_SAR_CAP_TRIM (0x0BuL) /**< Correct cap trim value */
+
+/**< Macros for conditions used in CY_ASSERT calls */
+#define CY_SAR_CHANNUM(chan) ((chan) < CY_SAR_MAX_NUM_CHANNELS)
+#define CY_SAR_CHANMASK(mask) ((mask) < (1uL << CY_SAR_MAX_NUM_CHANNELS))
+#define CY_SAR_RANGECOND(cond) ((cond) <= CY_SAR_RANGE_COND_OUTSIDE)
+#define CY_SAR_INTRMASK(mask) ((mask) <= (uint32_t)(CY_SAR_INTR_EOS_MASK | CY_SAR_INTR_OVERFLOW_MASK | CY_SAR_INTR_FW_COLLISION_MASK))
+#define CY_SAR_TRIGGER(mode) (((mode) == CY_SAR_TRIGGER_MODE_FW_ONLY) \
+ || ((mode) == CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE) \
+ || ((mode) == CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL))
+#define CY_SAR_RETURN(mode) (((mode) == CY_SAR_RETURN_STATUS) || ((mode) == CY_SAR_WAIT_FOR_RESULT))
+#define CY_SAR_STARTCONVERT(mode) (((mode) == CY_SAR_START_CONVERT_SINGLE_SHOT) || ((mode) == CY_SAR_START_CONVERT_CONTINUOUS))
+#define CY_SAR_RANGE_LIMIT(limit) ((limit) <= CY_SAR_RANGE_LIMIT_MAX)
+#define CY_SAR_SWITCHSELECT(select) ((select) == CY_SAR_MUX_SWITCH0)
+#define CY_SAR_SWITCHMASK(mask) ((mask) <= CY_SAR_CLEAR_ALL_SWITCHES)
+#define CY_SAR_SWITCHSTATE(state) (((state) == CY_SAR_SWITCH_OPEN) || ((state) == CY_SAR_SWITCH_CLOSE))
+#define CY_SAR_SQMASK(mask) (((mask) & (~CY_SAR_DEINIT_SQ_CTRL)) == 0uL)
+#define CY_SAR_SQCTRL(ctrl) (((ctrl) == CY_SAR_SWITCH_SEQ_CTRL_ENABLE) || ((ctrl) == CY_SAR_SWITCH_SEQ_CTRL_DISABLE))
+
+#define CY_SAR_CTRL(value) (((value) & (~CY_SAR_REG_CTRL_MASK)) == 0uL)
+#define CY_SAR_SAMPLE_CTRL(value) (((value) & (~CY_SAR_REG_SAMPLE_CTRL_MASK)) == 0uL)
+#define CY_SAR_SAMPLE_TIME(value) (((value) & (~CY_SAR_REG_SAMPLE_TIME_MASK)) == 0uL)
+#define CY_SAR_CHAN_CONFIG(value) (((value) & (~CY_SAR_REG_CHAN_CONFIG_MASK)) == 0uL)
+/** \endcond */
+
+/** \} group_sar_macro */
+
+/** \addtogroup group_sar_globals
+* \{
+*/
+/***************************************
+* Global Variables
+***************************************/
+
+/** This array is used to calibrate the offset for each channel.
+*
+* At initialization, channels that are single-ended, signed, and with Vneg = Vref
+* have an offset of -(2^12)/2 = -2048. All other channels have an offset of 0.
+* The offset can be overridden using \ref Cy_SAR_SetOffset.
+*
+* The channel offsets are used by the \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, and
+* \ref Cy_SAR_CountsTo_uVolts functions to convert counts to voltage.
+*
+*/
+extern volatile int16_t Cy_SAR_offset[CY_SAR_MAX_NUM_CHANNELS];
+
+/** This array is used to calibrate the gain for each channel.
+*
+* It is set at initialization and the value depends on the SARADC resolution
+* and voltage reference, 10*(2^12)/(2*Vref).
+* The gain can be overridden using \ref Cy_SAR_SetGain.
+*
+* The channel gains are used by the \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, and
+* \ref Cy_SAR_CountsTo_uVolts functions to convert counts to voltage.
+*/
+extern volatile int32_t Cy_SAR_countsPer10Volt[CY_SAR_MAX_NUM_CHANNELS];
+
+/** \} group_sar_globals */
+
+/** \addtogroup group_sar_enums
+* \{
+*/
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/** The SAR status/error code definitions */
+typedef enum
+{
+ CY_SAR_SUCCESS = 0x00uL, /**< Success */
+ CY_SAR_BAD_PARAM = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x01uL, /**< Invalid input parameters */
+ CY_SAR_TIMEOUT = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x02uL, /**< A timeout occurred */
+ CY_SAR_CONVERSION_NOT_COMPLETE = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x03uL, /**< SAR conversion is not complete */
+}cy_en_sar_status_t;
+
+/** Definitions for starting a conversion used in \ref Cy_SAR_StartConvert */
+typedef enum
+{
+ CY_SAR_START_CONVERT_SINGLE_SHOT = 0uL, /**< Start a single scan (one shot) from firmware */
+ CY_SAR_START_CONVERT_CONTINUOUS = 1uL, /**< Continuously scan enabled channels and ignores all triggers, firmware or hardware */
+}cy_en_sar_start_convert_sel_t;
+
+/** Definitions for the return mode used in \ref Cy_SAR_IsEndConversion */
+typedef enum
+{
+ CY_SAR_RETURN_STATUS = 0uL, /**< Immediately returns the conversion status. */
+ CY_SAR_WAIT_FOR_RESULT = 1uL, /**< Does not return a result until the conversion of all sequential channels is complete. This mode is blocking. */
+}cy_en_sar_return_mode_t;
+
+/** Switch state definitions */
+typedef enum
+{
+ CY_SAR_SWITCH_OPEN = 0uL, /**< Open the switch */
+ CY_SAR_SWITCH_CLOSE = 1uL /**< Close the switch */
+}cy_en_sar_switch_state_t;
+
+/** Definitions for sequencer control of switches */
+typedef enum
+{
+ CY_SAR_SWITCH_SEQ_CTRL_DISABLE = 0uL, /**< Disable sequencer control of switch */
+ CY_SAR_SWITCH_SEQ_CTRL_ENABLE = 1uL /**< Enable sequencer control of switch */
+}cy_en_sar_switch_sar_seq_ctrl_t;
+
+/** Switch register selection for \ref Cy_SAR_SetAnalogSwitch and \ref Cy_SAR_GetAnalogSwitch */
+typedef enum
+{
+ CY_SAR_MUX_SWITCH0 = 0uL, /**< SARMUX switch control register */
+}cy_en_sar_switch_register_sel_t;
+
+/** \addtogroup group_sar_ctrl_register_enums
+* This set of enumerations aids in configuring the SAR CTRL register
+* \{
+*/
+/** Reference voltage buffer power mode definitions */
+typedef enum
+{
+ CY_SAR_VREF_PWR_100 = 0uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< Full power (100%) */
+ CY_SAR_VREF_PWR_80 = 1uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 80% power */
+ CY_SAR_VREF_PWR_60 = 2uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 60% power */
+ CY_SAR_VREF_PWR_50 = 3uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 50% power */
+ CY_SAR_VREF_PWR_40 = 4uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 40% power */
+ CY_SAR_VREF_PWR_30 = 5uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 30% power */
+ CY_SAR_VREF_PWR_20 = 6uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 20% power */
+ CY_SAR_VREF_PWR_10 = 7uL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 10% power */
+}cy_en_sar_ctrl_pwr_ctrl_vref_t;
+
+/** Reference voltage selection definitions */
+typedef enum
+{
+ CY_SAR_VREF_SEL_BGR = 4uL << SAR_CTRL_VREF_SEL_Pos, /**< System wide bandgap from \ref group_sysanalog "AREF" (Vref buffer on) */
+ CY_SAR_VREF_SEL_EXT = 5uL << SAR_CTRL_VREF_SEL_Pos, /**< External Vref direct from a pin */
+ CY_SAR_VREF_SEL_VDDA_DIV_2 = 6uL << SAR_CTRL_VREF_SEL_Pos, /**< Vdda/2 (Vref buffer on) */
+ CY_SAR_VREF_SEL_VDDA = 7uL << SAR_CTRL_VREF_SEL_Pos /**< Vdda */
+}cy_en_sar_ctrl_vref_sel_t;
+
+/** Vref bypass cap enable.
+* When enabled, a bypass capacitor should
+* be connected to the dedicated Vref pin of the device.
+* Refer to the device datasheet for the minimum bypass capacitor value to use.
+*/
+typedef enum
+{
+ CY_SAR_BYPASS_CAP_DISABLE = 0uL << SAR_CTRL_VREF_BYP_CAP_EN_Pos, /**< Disable Vref bypass cap */
+ CY_SAR_BYPASS_CAP_ENABLE = 1uL << SAR_CTRL_VREF_BYP_CAP_EN_Pos /**< Enable Vref bypass cap */
+}cy_en_sar_ctrl_bypass_cap_t;
+
+/** Negative terminal (Vminus) selection definitions for single-ended channels.
+*
+* The Vminus input for single ended channels can be connected to
+* Vref, VSSA, or routed out to an external pin.
+* The options for routing to a pin are through Pin 1, Pin 3, Pin 5, or Pin 7
+* of the SARMUX dedicated port or an acore wire in AROUTE, if available on the device.
+*
+* \ref CY_SAR_NEG_SEL_VSSA_KELVIN comes straight from a Vssa pad without any shared branches
+* so as to keep quiet and avoid voltage drops.
+*/
+typedef enum
+{
+ CY_SAR_NEG_SEL_VSSA_KELVIN = 0uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to VSSA_KELVIN */
+ CY_SAR_NEG_SEL_P1 = 2uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 1 of SARMUX dedicated port */
+ CY_SAR_NEG_SEL_P3 = 3uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 3 of SARMUX dedicated port */
+ CY_SAR_NEG_SEL_P5 = 4uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 5 of SARMUX dedicated port */
+ CY_SAR_NEG_SEL_P7 = 5uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 6 of SARMUX dedicated port */
+ CY_SAR_NEG_SEL_ACORE = 6uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to an ACORE in AROUTE */
+ CY_SAR_NEG_SEL_VREF = 7uL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to VREF input of SARADC */
+}cy_en_sar_ctrl_neg_sel_t;
+
+/** Enable hardware control of the switch between Vref and the Vminus input */
+typedef enum
+{
+ CY_SAR_CTRL_NEGVREF_FW_ONLY = 0uL << SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos, /**< Only firmware control of the switch */
+ CY_SAR_CTRL_NEGVREF_HW = 1uL << SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos /**< Enable hardware control of the switch */
+}cy_en_sar_ctrl_hw_ctrl_negvref_t;
+
+/** Configure the comparator latch delay */
+typedef enum
+{
+ CY_SAR_CTRL_COMP_DLY_2P5 = 0uL << SAR_CTRL_COMP_DLY_Pos, /**< 2.5 ns delay, use for SAR conversion rate up to 2.5 Msps */
+ CY_SAR_CTRL_COMP_DLY_4 = 1uL << SAR_CTRL_COMP_DLY_Pos, /**< 4 ns delay, use for SAR conversion rate up to 2.0 Msps */
+ CY_SAR_CTRL_COMP_DLY_10 = 2uL << SAR_CTRL_COMP_DLY_Pos, /**< 10 ns delay, use for SAR conversion rate up to 1.5 Msps */
+ CY_SAR_CTRL_COMP_DLY_12 = 3uL << SAR_CTRL_COMP_DLY_Pos /**< 12 ns delay, use for SAR conversion rate up to 1 Msps */
+}cy_en_sar_ctrl_comp_delay_t;
+
+/** Configure the comparator power mode */
+typedef enum
+{
+ CY_SAR_COMP_PWR_100 = 0uL << SAR_CTRL_COMP_PWR_Pos, /**< 100% power, use this for > 2 Msps */
+ CY_SAR_COMP_PWR_80 = 1uL << SAR_CTRL_COMP_PWR_Pos, /**< 80% power, use this for 1.5 - 2 Msps */
+ CY_SAR_COMP_PWR_60 = 2uL << SAR_CTRL_COMP_PWR_Pos, /**< 60% power, use this for 1.0 - 1.5 Msps */
+ CY_SAR_COMP_PWR_50 = 3uL << SAR_CTRL_COMP_PWR_Pos, /**< 50% power, use this for 500 ksps - 1 Msps */
+ CY_SAR_COMP_PWR_40 = 4uL << SAR_CTRL_COMP_PWR_Pos, /**< 40% power, use this for 250 - 500 ksps */
+ CY_SAR_COMP_PWR_30 = 5uL << SAR_CTRL_COMP_PWR_Pos, /**< 30% power, use this for 100 - 250 ksps */
+ CY_SAR_COMP_PWR_20 = 6uL << SAR_CTRL_COMP_PWR_Pos, /**< 20% power, use this for TDB sps */
+ CY_SAR_COMP_PWR_10 = 7uL << SAR_CTRL_COMP_PWR_Pos, /**< 10% power, use this for < 100 ksps */
+}cy_en_sar_ctrl_comp_pwr_t;
+
+/** Enable or disable the SARMUX during Deep Sleep power mode. */
+typedef enum
+{
+ CY_SAR_DEEPSLEEP_SARMUX_OFF = 0uL << SAR_CTRL_DEEPSLEEP_ON_Pos, /**< Disable SARMUX operation during Deep Sleep */
+ CY_SAR_DEEPSLEEP_SARMUX_ON = 1uL << SAR_CTRL_DEEPSLEEP_ON_Pos /**< Enable SARMUX operation during Deep Sleep */
+}cy_en_sar_ctrl_sarmux_deep_sleep_t;
+
+/** Enable or disable the SARSEQ control of routing switches */
+typedef enum
+{
+ CY_SAR_SARSEQ_SWITCH_ENABLE = 0uL << SAR_CTRL_SWITCH_DISABLE_Pos, /**< Enable the SARSEQ to change the routing switches defined in the channel configurations */
+ CY_SAR_SARSEQ_SWITCH_DISABLE = 1uL << SAR_CTRL_SWITCH_DISABLE_Pos /**< Disable the SARSEQ. It is up to the firmware to set the routing switches */
+}cy_en_sar_ctrl_sarseq_routing_switches_t;
+
+/* \} */
+
+/** \addtogroup group_sar_sample_ctrl_register_enums
+* This set of enumerations are used in configuring the SAR SAMPLE_CTRL register
+* \{
+*/
+/** Configure result alignment, either left or right aligned.
+*
+* \note
+* Averaging always uses right alignment. If the \ref CY_SAR_LEFT_ALIGN
+* is selected with averaging enabled, it is ignored.
+*
+* \note
+* The voltage conversion functions (\ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts,
+* \ref Cy_SAR_CountsTo_uVolts) are only valid for right alignment.
+* */
+typedef enum
+{
+ CY_SAR_RIGHT_ALIGN = 0uL << SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos, /**< Right align result data to bits [11:0] with sign extension to 16 bits if channel is signed */
+ CY_SAR_LEFT_ALIGN = 1uL << SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos /**< Left align result data to bits [15:4] */
+}cy_en_sar_sample_ctrl_result_align_t;
+
+/** Configure format, signed or unsigned, of single-ended channels */
+typedef enum
+{
+ CY_SAR_SINGLE_ENDED_UNSIGNED = 0uL << SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos, /**< Result data for single-ended channels is unsigned */
+ CY_SAR_SINGLE_ENDED_SIGNED = 1uL << SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos /**< Result data for single-ended channels is signed */
+}cy_en_sar_sample_ctrl_single_ended_format_t;
+
+/** Configure format, signed or unsigned, of differential channels */
+typedef enum
+{
+ CY_SAR_DIFFERENTIAL_UNSIGNED = 0uL << SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos, /**< Result data for differential channels is unsigned */
+ CY_SAR_DIFFERENTIAL_SIGNED = 1uL << SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos /**< Result data for differential channels is signed */
+}cy_en_sar_sample_ctrl_differential_format_t;
+
+/** Configure number of samples for averaging.
+* This applies only to channels with averaging enabled.
+*/
+typedef enum
+{
+ CY_SAR_AVG_CNT_2 = 0uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 2 */
+ CY_SAR_AVG_CNT_4 = 1uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 4 */
+ CY_SAR_AVG_CNT_8 = 2uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 8 */
+ CY_SAR_AVG_CNT_16 = 3uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 16 */
+ CY_SAR_AVG_CNT_32 = 4uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 32 */
+ CY_SAR_AVG_CNT_64 = 5uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 64 */
+ CY_SAR_AVG_CNT_128 = 6uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 128 */
+ CY_SAR_AVG_CNT_256 = 7uL << SAR_SAMPLE_CTRL_AVG_CNT_Pos /**< Set samples averaged to 256 */
+}cy_en_sar_sample_ctrl_avg_cnt_t;
+
+/** Configure the averaging mode.
+*
+* - Sequential accumulate and dump: a channel will be sampled back to back.
+* The result is added to a running sum in a 20-bit register. At the end
+* of the scan, the accumulated value is shifted right to fit into 16 bits
+* and stored into the CHAN_RESULT register.
+* - Sequential fixed: a channel will be sampled back to back.
+* The result is added to a running sum in a 20-bit register. At the end
+* of the scan, the accumulated value is shifted right to fit into 12 bits
+* and stored into the CHAN_RESULT register.
+* - Interleaved: a channel will be sampled once per scan.
+* The result is added to a running sum in a 16-bit register.
+* In the scan where the final averaging count is reached,
+* the accumulated value is shifted right to fit into 12 bits
+* and stored into the CHAN_RESULT register.
+* In all other scans, the CHAN_RESULT will have an invalid result.
+* In interleaved mode, make sure that the averaging
+* count is low enough to ensure that the intermediate value does not exceed 16 bits,
+* that is averaging count is 16 or less. Otherwise, the MSBs will be lost.
+* In the special case that averaging is enabled for all enabled channels
+* and interleaved mode is used, the interrupt frequency
+* will be reduced by a factor of the number of samples averaged.
+*/
+typedef enum
+{
+ CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM = 0uL, /**< Set mode to sequential accumulate and dump */
+ CY_SAR_AVG_MODE_SEQUENTIAL_FIXED = SAR_SAMPLE_CTRL_AVG_SHIFT_Msk, /**< Set mode to sequential 12-bit fixed */
+ CY_SAR_AVG_MODE_INTERLEAVED = SAR_SAMPLE_CTRL_AVG_MODE_Msk, /**< Set mode to interleaved. Number of samples per scan must be 16 or less. */
+}cy_en_sar_sample_ctrl_avg_mode_t;
+
+/** Configure the trigger mode.
+*
+* Firmware triggering is always enabled and can be single shot or continuous.
+* Additionally, hardware triggering can be enabled with the option to be
+* edge or level sensitive.
+*/
+typedef enum
+{
+ CY_SAR_TRIGGER_MODE_FW_ONLY = 0uL, /**< Firmware trigger only, disable hardware trigger*/
+ CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE = SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk, /**< Enable edge sensitive hardware trigger. Each rising edge will trigger a single scan. */
+ CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL = SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk | SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk, /**< Enable level sensitive hardware trigger. The SAR will continuously scan while the trigger signal is high. */
+}cy_en_sar_sample_ctrl_trigger_mode_t;
+
+/* \} */
+
+/** \addtogroup group_sar_sample_time_shift_enums
+* This set of enumerations aids in configuring the SAR SAMPLE_TIME* registers
+* \{
+*/
+/** Configure the sample time by using these shifts */
+typedef enum
+{
+ CY_SAR_SAMPLE_TIME0_SHIFT = SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos, /**< Shift for sample time 0 */
+ CY_SAR_SAMPLE_TIME1_SHIFT = SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos, /**< Shift for sample time 1 */
+ CY_SAR_SAMPLE_TIME2_SHIFT = SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos, /**< Shift for sample time 2 */
+ CY_SAR_SAMPLE_TIME3_SHIFT = SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos, /**< Shift for sample time 3 */
+}cy_en_sar_sample_time_shift_t;
+/* \} */
+
+/** \addtogroup group_sar_range_thres_register_enums
+* This set of enumerations aids in configuring the SAR RANGE* registers
+* \{
+*/
+/** Configure the lower and upper thresholds for range detection
+*
+* The SARSEQ supports range detection to allow for automatic detection of sample
+* values compared to two programmable thresholds without CPU involvement.
+* Range detection is defined by two global thresholds and a condition.
+* The RANGE_LOW value defines the lower threshold and RANGE_HIGH defines
+* the upper threshold of the range.
+*
+* Range detect is done after averaging, alignment, and sign extension (if applicable).
+* In other words, the thresholds values must have the same data format as the result data.
+* Range detection is always done for all channels scanned. By making RANGE_INTR_MASK=0,
+* the firmware can choose to ignore the range detect interrupt for any channel.
+*/
+typedef enum
+{
+ CY_SAR_RANGE_LOW_SHIFT = SAR_RANGE_THRES_RANGE_LOW_Pos, /**< Shift for setting lower limit of range detection */
+ CY_SAR_RANGE_HIGH_SHIFT = SAR_RANGE_THRES_RANGE_HIGH_Pos, /**< Shift for setting upper limit of range detection */
+}cy_en_sar_range_thres_shift_t;
+
+/** Configure the condition (below, inside, above, or outside) of the range detection interrupt */
+typedef enum
+{
+ CY_SAR_RANGE_COND_BELOW = 0uL, /**< Range interrupt detected when result < RANGE_LOW */
+ CY_SAR_RANGE_COND_INSIDE = 1uL, /**< Range interrupt detected when RANGE_LOW <= result < RANGE_HIGH */
+ CY_SAR_RANGE_COND_ABOVE = 2uL, /**< Range interrupt detected when RANGE_HIGH <= result */
+ CY_SAR_RANGE_COND_OUTSIDE = 3uL, /**< Range interrupt detected when result < RANGE_LOW || RANGE_HIGH <= result */
+}cy_en_sar_range_detect_condition_t;
+/* \} */
+
+/** \addtogroup group_sar_chan_config_register_enums
+* This set of enumerations aids in configuring the SAR CHAN_CONFIG register
+* \{
+*/
+/** Configure the input mode of the channel
+*
+* - Single ended channel: the \ref cy_en_sar_ctrl_neg_sel_t selection in the \ref group_sar_init_struct_ctrl register
+* determines what drives the Vminus pin
+* - Differential paired: Vplus and Vminus are a pair. Bit 0 of \ref cy_en_sar_chan_config_pos_pin_addr_t "POS_PIN_ADDR"
+* is ignored and considered to be 0.
+* In other words, \ref cy_en_sar_chan_config_pos_pin_addr_t "POS_PIN_ADDR" points to the even pin of a pin pair.
+* The even pin is connected to Vplus and the odd pin is connected to Vminus.
+* \ref cy_en_sar_chan_config_pos_port_addr_t "POS_PORT_ADDR" is used to identify the port that contains the pins.
+* - Differential unpaired: The \ref cy_en_sar_chan_config_neg_pin_addr_t "NEG_PIN_ADDR" and
+* \ref cy_en_sar_chan_config_neg_port_addr_t "NEG_PORT_ADDR" determine what drives the Vminus pin.
+* This is a variation of differential mode with no even-odd pair limitation
+*/
+typedef enum
+{
+ CY_SAR_CHAN_SINGLE_ENDED = 0uL, /**< Single ended channel */
+ CY_SAR_CHAN_DIFFERENTIAL_PAIRED = SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk, /**< Differential with even-odd pair limitation */
+ CY_SAR_CHAN_DIFFERENTIAL_UNPAIRED = SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk /**< Differential with no even-odd pair limitation */
+}cy_en_sar_chan_config_input_mode_t;
+
+/** Configure address of the pin connected to the Vplus terminal of the SARADC. */
+typedef enum
+{
+ CY_SAR_CHAN_POS_PIN_ADDR_0 = 0uL, /**< Pin 0 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_1 = 1uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 1 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_2 = 2uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 2 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_3 = 3uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 3 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_4 = 4uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 4 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_5 = 5uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 5 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_6 = 6uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 6 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+ CY_SAR_CHAN_POS_PIN_ADDR_7 = 7uL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 7 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
+}cy_en_sar_chan_config_pos_pin_addr_t;
+
+/** Configure address of the port that contains the pin connected to the Vplus terminal of the SARADC
+*
+* - \ref CY_SAR_POS_PORT_ADDR_SARMUX is for the dedicated SARMUX port (8 pins)
+* - Port 1 through 4 are respectively the pins of CTB0, CTB1, CTB2, and CTB3 (if present)
+* - Port 7, 5, and 6 (VPORT0/1/2) are the groups of internal signals that can be selected
+* in the SARMUX or AROUTE (if present).
+*
+* See the \ref group_sar_sarmux section for more guidance.
+*/
+typedef enum
+{
+ CY_SAR_POS_PORT_ADDR_SARMUX = 0uL, /**< Dedicated SARMUX port with 8 possible pins */
+ CY_SAR_POS_PORT_ADDR_CTB0 = 1uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB0, if present */
+ CY_SAR_POS_PORT_ADDR_CTB1 = 2uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB1, if present */
+ CY_SAR_POS_PORT_ADDR_CTB2 = 3uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB2, if present */
+ CY_SAR_POS_PORT_ADDR_CTB3 = 4uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB3, if present */
+ CY_SAR_POS_PORT_ADDR_AROUTE_VIRT2 = 5uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT2), if present */
+ CY_SAR_POS_PORT_ADDR_AROUTE_VIRT1 = 6uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT1), if present */
+ CY_SAR_POS_PORT_ADDR_SARMUX_VIRT = 7uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< SARMUX virtual port for DieTemp and AMUXBUSA/B */
+}cy_en_sar_chan_config_pos_port_addr_t;
+
+/** Enable or disable averaging for the channel */
+typedef enum
+{
+ CY_SAR_CHAN_AVG_DISABLE = 0uL, /**< Disable averaging for the channel */
+ CY_SAR_CHAN_AVG_ENABLE = 1uL << SAR_CHAN_CONFIG_AVG_EN_Pos /**< Enable averaging for the channel */
+}cy_en_sar_chan_config_avg_en_t;
+
+/** Select which sample time to use for the channel.
+* There are four global samples times available set by \ref group_sar_init_struct_sampleTime01 and
+* \ref group_sar_init_struct_sampleTime23.
+*/
+typedef enum
+{
+ CY_SAR_CHAN_SAMPLE_TIME_0 = 0uL, /**< Use sample time 0 for the channel */
+ CY_SAR_CHAN_SAMPLE_TIME_1 = 1uL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 1 for the channel */
+ CY_SAR_CHAN_SAMPLE_TIME_2 = 2uL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 2 for the channel */
+ CY_SAR_CHAN_SAMPLE_TIME_3 = 3uL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 3 for the channel */
+}cy_en_sar_chan_config_sample_time_t;
+
+/** Configure address of the pin connected to the Vminus terminal of the SARADC. */
+typedef enum
+{
+ CY_SAR_CHAN_NEG_PIN_ADDR_0 = 0uL, /**< Pin 0 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_1 = 1uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 1 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_2 = 2uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 2 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_3 = 3uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 3 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_4 = 4uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 4 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_5 = 5uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 5 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_6 = 6uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 6 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+ CY_SAR_CHAN_NEG_PIN_ADDR_7 = 7uL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 7 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
+}cy_en_sar_chan_config_neg_pin_addr_t;
+
+/** Configure address of the port that contains the pin connected to the Vminus terminal of the SARADC.
+*
+* - Port 0 is 8 pins of the SARMUX
+* - Port 7, 5, and 6 (VPORT0/1/2) are the groups of internal signals that can be selected
+* in the SARMUX or AROUTE (if present).
+*/
+typedef enum
+{
+ CY_SAR_NEG_PORT_ADDR_SARMUX = 0uL, /**< Dedicated SARMUX port with 8 possible pins */
+ CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT2 = 5uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT2), if present */
+ CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT1 = 6uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT1), if present */
+ CY_SAR_NEG_PORT_ADDR_SARMUX_VIRT = 7uL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< SARMUX virtual port for AMUXBUSA/B */
+}cy_en_sar_chan_config_neg_port_addr_t;
+
+/* \} */
+
+/** \addtogroup group_sar_intr_mask_t_register_enums
+* This set of enumerations aids in configuring the SAR INTR_MASK register
+* \{
+*/
+/** Configure which signal will cause an interrupt event.
+*
+* - End of scan (EOS): occurs after completing a scan of all enabled channels
+* - Overflow: occurs when hardware sets a new EOS interrupt while the previous interrupt
+* has not be cleared by the firmware
+* - Firmware collision: occurs when firmware attempts to start one-shot
+* conversion while the SAR is busy.
+*
+* Enable all, one, or none of the interrupt events.
+*/
+typedef enum
+{
+ CY_SAR_INTR_MASK_NONE = 0uL, /**< Disable all interrupt sources */
+ CY_SAR_INTR_EOS_MASK = SAR_INTR_MASK_EOS_MASK_Msk, /**< Enable end of scan (EOS) interrupt */
+ CY_SAR_INTR_OVERFLOW_MASK = SAR_INTR_MASK_OVERFLOW_MASK_Msk, /**< Enable overflow interrupt */
+ CY_SAR_INTR_FW_COLLISION_MASK = SAR_INTR_MASK_FW_COLLISION_MASK_Msk, /**< Enable firmware collision interrupt */
+}cy_en_sar_intr_mask_t;
+
+/* \} */
+
+/** \addtogroup group_sar_mux_switch_register_enums
+* This set of enumerations aids in configuring the \ref group_sar_init_struct_muxSwitch and \ref group_sar_init_struct_muxSwitchSqCtrl registers
+* \{
+*/
+
+/** Firmware control for the SARMUX switches to connect analog signals to the SAR ADC
+*
+* To close multiple switches, "OR" the enum values together.
+*
+* See the \ref group_sar_sarmux section for more guidance.
+*/
+typedef enum
+{
+ /* SARMUX pins to Vplus */
+ CY_SAR_MUX_FW_P0_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk, /**< Switch between Pin 0 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P1_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk, /**< Switch between Pin 1 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P2_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk, /**< Switch between Pin 2 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P3_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk, /**< Switch between Pin 3 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P4_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk, /**< Switch between Pin 4 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P5_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk, /**< Switch between Pin 5 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P6_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk, /**< Switch between Pin 6 of SARMUX and Vplus of SARADC */
+ CY_SAR_MUX_FW_P7_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk, /**< Switch between Pin 7 of SARMUX and Vplus of SARADC */
+
+ /* SARMUX pins to Vminus */
+ CY_SAR_MUX_FW_P0_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk, /**< Switch between Pin 0 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P1_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk, /**< Switch between Pin 1 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P2_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk, /**< Switch between Pin 2 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P3_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk, /**< Switch between Pin 3 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P4_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk, /**< Switch between Pin 4 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P5_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk, /**< Switch between Pin 5 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P6_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk, /**< Switch between Pin 6 of SARMUX and Vminus of SARADC */
+ CY_SAR_MUX_FW_P7_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk, /**< Switch between Pin 7 of SARMUX and Vminus of SARADC */
+
+ /* Vssa to Vminus and temperature sensor to Vplus */
+ CY_SAR_MUX_FW_VSSA_VMINUS = SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk, /**< Switch between VSSA and Vminus of SARADC */
+ CY_SAR_MUX_FW_TEMP_VPLUS = SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk, /**< Switch between the DieTemp sensor and vplus of SARADC */
+
+ /* Amuxbus A and B to Vplus and Vminus */
+ CY_SAR_MUX_FW_AMUXBUSA_VPLUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, /**< Switch between AMUXBUSA and vplus of SARADC */
+ CY_SAR_MUX_FW_AMUXBUSB_VPLUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk, /**< Switch between AMUXBUSB and vplus of SARADC */
+ CY_SAR_MUX_FW_AMUXBUSA_VMINUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk, /**< Switch between AMUXBUSA and vminus of SARADC */
+ CY_SAR_MUX_FW_AMUXBUSB_VMINUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk, /**< Switch between AMUXBUSB and vminus of SARADC */
+
+ /* Sarbus 0 and 1 to Vplus and Vminus */
+ CY_SAR_MUX_FW_SARBUS0_VPLUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk, /**< Switch between SARBUS0 and vplus of SARADC */
+ CY_SAR_MUX_FW_SARBUS1_VPLUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk, /**< Switch between SARBUS1 and vplus of SARADC */
+ CY_SAR_MUX_FW_SARBUS0_VMINUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk, /**< Switch between SARBUS0 and vminus of SARADC */
+ CY_SAR_MUX_FW_SARBUS1_VMINUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk, /**< Switch between SARBUS1 and vminus of SARADC */
+
+ /* SARMUX pins to Core IO */
+ CY_SAR_MUX_FW_P4_COREIO0 = SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk, /**< Switch between Pin 4 of SARMUX and coreio0, if present */
+ CY_SAR_MUX_FW_P5_COREIO1 = SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk, /**< Switch between Pin 5 of SARMUX and coreio1, if present */
+ CY_SAR_MUX_FW_P6_COREIO2 = SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk, /**< Switch between Pin 6 of SARMUX and coreio2, if present */
+ CY_SAR_MUX_FW_P7_COREIO3 = SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk, /**< Switch between Pin 7 of SARMUX and coreio3, if present */
+}cy_en_sar_mux_switch_fw_ctrl_t;
+
+/** Mask definitions of SARMUX switches that can be controlled by the SARSEQ.
+*
+* To enable sequencer control of multiple switches, "OR" the enum values together.
+*
+* See the \ref group_sar_sarmux section for more guidance.
+*/
+typedef enum
+{
+ CY_SAR_MUX_SQ_CTRL_P0 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk, /**< Enable SARSEQ control of Pin 0 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P1 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk, /**< Enable SARSEQ control of Pin 1 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P2 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk, /**< Enable SARSEQ control of Pin 2 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P3 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk, /**< Enable SARSEQ control of Pin 3 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P4 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk, /**< Enable SARSEQ control of Pin 4 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P5 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk, /**< Enable SARSEQ control of Pin 5 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P6 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk, /**< Enable SARSEQ control of Pin 6 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_P7 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk, /**< Enable SARSEQ control of Pin 7 switches (for Vplus and Vminus) of SARMUX dedicated port */
+ CY_SAR_MUX_SQ_CTRL_VSSA = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk, /**< Enable SARSEQ control of the switch between VSSA and Vminus */
+ CY_SAR_MUX_SQ_CTRL_TEMP = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk, /**< Enable SARSEQ control of the switch between DieTemp and Vplus */
+ CY_SAR_MUX_SQ_CTRL_AMUXBUSA = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk, /**< Enable SARSEQ control of AMUXBUSA switches (for Vplus and Vminus) */
+ CY_SAR_MUX_SQ_CTRL_AMUXBUSB = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk, /**< Enable SARSEQ control of AMUXBUSB switches (for Vplus and Vminus) */
+ CY_SAR_MUX_SQ_CTRL_SARBUS0 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk, /**< Enable SARSEQ control of SARBUS0 switches (for Vplus and Vminus) */
+ CY_SAR_MUX_SQ_CTRL_SARBUS1 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk, /**< Enable SARSEQ control of SARBUS1 switches (for Vplus and Vminus) */
+}cy_en_sar_mux_switch_sq_ctrl_t;
+
+/* \} */
+
+/** \} group_sar_enums */
+
+/** \addtogroup group_sar_data_structures
+* \{
+*/
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/** This structure is used to initialize the SAR ADC subsystem.
+*
+* The SAR ADC subsystem is highly configurable with many options.
+* When calling \ref Cy_SAR_Init, provide a pointer to the structure containing this configuration data.
+* A set of enumerations is provided in this
+* driver to help with configuring this structure.
+*
+* See the \ref group_sar_initialization section for guidance.
+**/
+typedef struct
+{
+ uint32_t ctrl; /**< Control register settings (applies to all channels) */
+ uint32_t sampleCtrl; /**< Sample control register settings (applies to all channels) */
+ uint32_t sampleTime01; /**< Sample time in ADC clocks for Sample Time 0 and 1 */
+ uint32_t sampleTime23; /**< Sample time in ADC clocks for Sample Time 2 and 3 */
+ uint32_t rangeThres; /**< Range detect threshold register for all channels */
+ cy_en_sar_range_detect_condition_t rangeCond; /**< Range detect condition (below, inside, output, or above) for all channels */
+ uint32_t chanEn; /**< Enable bits for the channels */
+ uint32_t chanConfig[CY_SAR_MAX_NUM_CHANNELS]; /**< Channel configuration */
+ uint32_t intrMask; /**< Interrupt enable mask */
+ uint32_t satIntrMask; /**< Saturation detection interrupt enable mask */
+ uint32_t rangeIntrMask; /**< Range detection interrupt enable mask */
+ uint32_t muxSwitch; /**< SARMUX firmware switches to connect analog signals to SAR */
+ uint32_t muxSwitchSqCtrl; /**< Enable SARSEQ control of specific SARMUX switches */
+ bool configRouting; /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */
+ uint32_t vrefMvValue; /**< Reference voltage in millivolts used in converting counts to volts */
+} cy_stc_sar_config_t;
+
+/** This structure is used by the driver to backup the state of the SAR
+* before entering sleep so that it can be re-enabled after waking up */
+typedef struct
+{
+ uint32_t hwEnabled; /**< SAR enabled state */
+ uint32_t continuous; /**< State of the continuous bit */
+} cy_stc_sar_state_backup_t;
+
+/** \} group_sar_data_structures */
+
+/** \addtogroup group_sar_functions
+* \{
+*/
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/** \addtogroup group_sar_functions_basic
+* This set of functions is for initialization and basic usage
+* \{
+*/
+cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config);
+cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting);
+void Cy_SAR_Enable(SAR_Type *base);
+__STATIC_INLINE void Cy_SAR_Disable(SAR_Type *base);
+void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSelect);
+void Cy_SAR_StopConvert(SAR_Type *base);
+cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_t retMode);
+int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan);
+int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan);
+__STATIC_INLINE uint32_t Cy_SAR_GetChanResultUpdated(const SAR_Type *base);
+/** \} */
+
+/** \addtogroup group_sar_functions_power
+* This set of functions is for Deep Sleep entry and exit
+* \{
+*/
+cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+void Cy_SAR_Sleep(SAR_Type *base);
+void Cy_SAR_Wakeup(SAR_Type *base);
+/** \} */
+
+/** \addtogroup group_sar_functions_config
+* This set of functions allows changes to the SAR configuration
+* after initialization.
+* \{
+*/
+void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t mode);
+__STATIC_INLINE void Cy_SAR_SetChanMask(SAR_Type *base, uint32_t enableMask);
+void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit);
+void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit);
+__STATIC_INLINE void Cy_SAR_SetRangeCond(SAR_Type *base, cy_en_sar_range_detect_condition_t cond);
+/** \} */
+
+/** \addtogroup group_sar_functions_countsto
+* This set of functions performs counts to *volts conversions.
+* \{
+*/
+int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
+float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
+int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
+int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
+cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset);
+cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain);
+/** \} */
+
+/** \addtogroup group_sar_functions_switches
+* This set of functions is for controlling/querying the SARMUX switches
+* \{
+*/
+void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_sar_switch_state_t state);
+uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect);
+__STATIC_INLINE void Cy_SAR_SetVssaVminusSwitch(SAR_Type *base, cy_en_sar_switch_state_t state);
+void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
+__STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
+/** \} */
+
+/** \addtogroup group_sar_functions_interrupt
+* This set of functions are related to SAR interrupts.
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatus(const SAR_Type *base);
+__STATIC_INLINE void Cy_SAR_ClearInterrupt(SAR_Type *base, uint32_t intrMask);
+__STATIC_INLINE void Cy_SAR_SetInterrupt(SAR_Type *base, uint32_t intrMask);
+__STATIC_INLINE void Cy_SAR_SetInterruptMask(SAR_Type *base, uint32_t intrMask);
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptMask(const SAR_Type *base);
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatusMasked(const SAR_Type *base);
+
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatus(const SAR_Type *base);
+__STATIC_INLINE void Cy_SAR_ClearRangeInterrupt(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE void Cy_SAR_SetRangeInterrupt(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE void Cy_SAR_SetRangeInterruptMask(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptMask(const SAR_Type *base);
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatusMasked(const SAR_Type *base);
+
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatus(const SAR_Type *base);
+__STATIC_INLINE void Cy_SAR_ClearSatInterrupt(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE void Cy_SAR_SetSatInterrupt(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE void Cy_SAR_SetSatInterruptMask(SAR_Type *base, uint32_t chanMask);
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptMask(const SAR_Type *base);
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatusMasked(const SAR_Type *base);
+
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptCause(const SAR_Type *base);
+/** \} */
+
+
+/** \addtogroup group_sar_functions_helper
+* This set of functions is for useful configuration query
+* \{
+*/
+bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan);
+bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan);
+__STATIC_INLINE bool Cy_SAR_IsChannelDifferential(const SAR_Type *base, uint32_t chan);
+/** \} */
+
+/** \addtogroup group_sar_functions_basic
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SAR_Disable
+****************************************************************************//**
+*
+* Turn off the hardware block.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_Disable(SAR_Type *base)
+{
+ base->CTRL &= ~SAR_CTRL_ENABLED_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetChanResultUpdated
+****************************************************************************//**
+*
+* Return whether the RESULT register has been updated or not.
+* If the bit is high, the corresponding channel RESULT register was updated,
+* i.e. was sampled during the previous scan and, in case of Interleaved averaging,
+* reached the averaging count.
+* If the bit is low, the corresponding channel is not enabled or the averaging count
+* is not yet reached for Interleaved averaging.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Each bit of the result corresponds to the channel.
+* Bit 0 is for channel 0, etc.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_CHAN_RESULT_UPDATED
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetChanResultUpdated(const SAR_Type *base)
+{
+ return base->CHAN_RESULT_UPDATED;
+}
+/** \} */
+
+/** \addtogroup group_sar_functions_config
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SAR_SetChanMask
+****************************************************************************//**
+*
+* Set the enable/disable mask for the channels.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param enableMask
+* Channel enable/disable mask. Each bit corresponds to a channel.
+* - 0: the corresponding channel is disabled.
+* - 1: the corresponding channel is enabled; it will be included in the next scan.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_CHAN_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetChanMask(SAR_Type *base, uint32_t enableMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(enableMask));
+
+ base->CHAN_EN = enableMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetRangeCond
+****************************************************************************//**
+*
+* Set the condition in which range detection interrupts are triggered.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param cond
+* A value of the enum \ref cy_en_sar_range_detect_condition_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_RANGE_COND
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetRangeCond(SAR_Type *base, cy_en_sar_range_detect_condition_t cond)
+{
+ CY_ASSERT_L3(CY_SAR_RANGECOND(cond));
+
+ base->RANGE_COND = (uint32_t)cond << SAR_RANGE_COND_RANGE_COND_Pos;
+}
+
+/** \} */
+
+/** \addtogroup group_sar_functions_interrupt
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SAR_GetInterruptStatus
+****************************************************************************//**
+*
+* Return the interrupt register status.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return Interrupt status
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_ISR
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatus(const SAR_Type *base)
+{
+ return base->INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_ClearInterrupt
+****************************************************************************//**
+*
+* Clear the interrupt.
+* The interrupt must be cleared with this function so that the hardware
+* can set subsequent interrupts and those interrupts can be forwarded
+* to the interrupt controller, if enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param intrMask
+* The mask of interrupts to clear. Typically this will be the value returned
+* from \ref Cy_SAR_GetInterruptStatus.
+* Alternately, select one or more values from \ref cy_en_sar_intr_mask_t and "OR" them together.
+* - \ref CY_SAR_INTR_EOS_MASK
+* - \ref CY_SAR_INTR_OVERFLOW_MASK
+* - \ref CY_SAR_INTR_FW_COLLISION_MASK
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_ClearInterrupt(SAR_Type *base, uint32_t intrMask)
+{
+ CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
+
+ base->INTR = intrMask;
+
+ /* Dummy read for buffered writes. */
+ (void) base->INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetInterrupt
+****************************************************************************//**
+*
+* Trigger an interrupt with software.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param intrMask
+* The mask of interrupts to set.
+* Select one or more values from \ref cy_en_sar_intr_mask_t and "OR" them together.
+* - \ref CY_SAR_INTR_EOS_MASK
+* - \ref CY_SAR_INTR_OVERFLOW_MASK
+* - \ref CY_SAR_INTR_FW_COLLISION_MASK
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetInterrupt(SAR_Type *base, uint32_t intrMask)
+{
+ CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
+
+ base->INTR_SET = intrMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetInterruptMask
+****************************************************************************//**
+*
+* Enable which interrupts can trigger the CPU interrupt controller.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param intrMask
+* The mask of interrupts. Select one or more values from \ref cy_en_sar_intr_mask_t
+* and "OR" them together.
+* - \ref CY_SAR_INTR_MASK_NONE : Disable EOS, overflow, and firmware collision interrupts.
+* - \ref CY_SAR_INTR_EOS_MASK
+* - \ref CY_SAR_INTR_OVERFLOW_MASK
+* - \ref CY_SAR_INTR_FW_COLLISION_MASK
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetInterruptMask(SAR_Type *base, uint32_t intrMask)
+{
+ CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
+
+ base->INTR_MASK = intrMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetInterruptMask
+****************************************************************************//**
+*
+* Return which interrupts can trigger the CPU interrupt controller
+* as configured by \ref Cy_SAR_SetInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Interrupt mask. Compare this value with masks in \ref cy_en_sar_intr_mask_t.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptMask(const SAR_Type *base)
+{
+ return base->INTR_MASK;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the bitwise AND between the interrupt request and mask registers.
+* See \ref Cy_SAR_GetInterruptStatus and \ref Cy_SAR_GetInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Bitwise AND of the interrupt request and mask registers
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatusMasked(const SAR_Type *base)
+{
+ return base->INTR_MASKED;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetRangeInterruptStatus
+****************************************************************************//**
+*
+* Return the range interrupt register status.
+* If the status bit is low for a channel, the channel may not be enabled
+* (\ref Cy_SAR_SetChanMask), range detection is not enabled for the
+* channel (\ref Cy_SAR_SetRangeInterruptMask), or range detection was not
+* triggered for the channel.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* The range interrupt status for all channels. Bit 0 is for channel 0, etc.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_RANGE_INTERRUPT_STATUS
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatus(const SAR_Type *base)
+{
+ return base->RANGE_INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_ClearRangeInterrupt
+****************************************************************************//**
+*
+* Clear the range interrupt for the specified channel mask.
+* The interrupt must be cleared with this function so that
+* the hardware can set subset interrupts and those interrupts can
+* be forwarded to the interrupt controller, if enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+* Typically, this is the value returned from \ref Cy_SAR_GetRangeInterruptStatus.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_ClearRangeInterrupt(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->RANGE_INTR = chanMask;
+
+ /* Dummy read for buffered writes. */
+ (void) base->RANGE_INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetRangeInterrupt
+****************************************************************************//**
+*
+* Trigger a range interrupt with software for the specific channel mask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetRangeInterrupt(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->RANGE_INTR_SET = chanMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetRangeInterruptMask
+****************************************************************************//**
+*
+* Enable which channels can trigger a range interrupt.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_SET_RANGE_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetRangeInterruptMask(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->RANGE_INTR_MASK = chanMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetRangeInterruptMask
+****************************************************************************//**
+*
+* Return which interrupts can trigger a range interrupt as configured by
+* \ref Cy_SAR_SetRangeInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* The range interrupt mask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptMask(const SAR_Type *base)
+{
+ return base->RANGE_INTR_MASK;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetRangeInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the bitwise AND between the range interrupt request and mask registers.
+* See \ref Cy_SAR_GetRangeInterruptStatus and \ref Cy_SAR_GetRangeInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Bitwise AND between of range interrupt request and mask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatusMasked(const SAR_Type *base)
+{
+ return base->RANGE_INTR_MASKED;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetSatInterruptStatus
+****************************************************************************//**
+*
+* Return the saturate interrupt register status.
+* If the status bit is low for a channel, the channel may not be enabled
+* (\ref Cy_SAR_SetChanMask), saturation detection is not enabled for the
+* channel (\ref Cy_SAR_SetSatInterruptMask), or saturation detection was not
+* triggered for the channel.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* The saturate interrupt status for all channels. Bit 0 is for channel 0, etc.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_SAT_INTERRUPT_STATUS
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatus(const SAR_Type *base)
+{
+ return base->SATURATE_INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_ClearSatInterrupt
+****************************************************************************//**
+*
+* Clear the saturate interrupt for the specified channel mask.
+* The interrupt must be cleared with this function so that the hardware
+* can set subsequent interrupts and those interrupts can be forwarded
+* to the interrupt controller, if enabled.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+* Typically, this is the value returned from \ref Cy_SAR_GetSatInterruptStatus.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_ClearSatInterrupt(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->SATURATE_INTR = chanMask;
+
+ /* Dummy read for buffered writes. */
+ (void) base->SATURATE_INTR;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetSatInterrupt
+****************************************************************************//**
+*
+* Trigger a saturate interrupt with software for the specific channel mask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+*
+* \return None
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetSatInterrupt(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->SATURATE_INTR_SET = chanMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetSatInterruptMask
+****************************************************************************//**
+*
+* Enable which channels can trigger a saturate interrupt.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chanMask
+* The channel mask. Bit 0 is for channel 0, etc.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_GET_SAT_INTERRUPT_MASK
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetSatInterruptMask(SAR_Type *base, uint32_t chanMask)
+{
+ CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
+
+ base->SATURATE_INTR_MASK = chanMask;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetSatInterruptMask
+****************************************************************************//**
+*
+* Return which interrupts can trigger a saturate interrupt as configured
+* by \ref Cy_SAR_SetSatInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* The saturate interrupt mask. Bit 0 is for channel 0, etc.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptMask(const SAR_Type *base)
+{
+ return base->SATURATE_INTR_MASK;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetSatInterruptStatusMasked
+****************************************************************************//**
+*
+* Return the bitwise AND between the saturate interrupt request and mask registers.
+* See \ref Cy_SAR_GetSatInterruptStatus and \ref Cy_SAR_GetSatInterruptMask.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Bitwise AND of the saturate interrupt request and mask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatusMasked(const SAR_Type *base)
+{
+ return base->SATURATE_INTR_MASKED;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_GetInterruptCause
+****************************************************************************//**
+*
+* Return the cause of the interrupt.
+* The interrupt routine can be called due to one of the following events:
+* - End of scan (EOS)
+* - Overflow
+* - Firmware collision
+* - Saturation detected on one or more channels
+* - Range detected on one or more channels
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \return
+* Mask of what caused the interrupt. Compare this value with one of these masks:
+* - SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk : EOS caused the interrupt
+* - SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk : Overflow caused the interrupt
+* - SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk : Firmware collision cause the interrupt
+* - SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk : Saturation detection on one or more channels caused the interrupt
+* - SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk : Range detection on one or more channels caused the interrupt
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SAR_GetInterruptCause(const SAR_Type *base)
+{
+ return base->INTR_CAUSE;
+}
+/** \} */
+
+/** \addtogroup group_sar_functions_helper
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SAR_IsChannelDifferential
+****************************************************************************//**
+*
+* Return true of channel is differential, else false.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param chan
+* The channel to check, starting at 0.
+*
+* \return
+* A false is return if chan is invalid.
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_IS_CHANNEL_DIFF
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SAR_IsChannelDifferential(const SAR_Type *base, uint32_t chan)
+{
+ return !Cy_SAR_IsChannelSingleEnded(base, chan);
+}
+/** \} */
+
+/** \addtogroup group_sar_functions_switches
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SAR_SetVssaVminusSwitch
+****************************************************************************//**
+*
+* Open or close the switch between VSSA and Vminus of the SARADC through firmware.
+* This function calls \ref Cy_SAR_SetAnalogSwitch with switchSelect set to
+* \ref CY_SAR_MUX_SWITCH0 and switchMask set to SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param state
+* Open or close the switch. Select a value from \ref cy_en_sar_switch_state_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_VSSA_VMINUS_SWITCH
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetVssaVminusSwitch(SAR_Type *base, cy_en_sar_switch_state_t state)
+{
+ Cy_SAR_SetAnalogSwitch(base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk, state);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SAR_SetVssaSarSeqCtrl
+****************************************************************************//**
+*
+* Enable or disable SARSEQ control of the switch between VSSA and Vminus of the SARADC.
+* This function calls \ref Cy_SAR_SetSwitchSarSeqCtrl
+* with switchMask set to SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk.
+*
+* \param base
+* Pointer to structure describing registers
+*
+* \param ctrl
+* Enable or disable control. Select a value from \ref cy_en_sar_switch_sar_seq_ctrl_t.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sar_sut_01.cydsn/main_cm0p.c SNIPPET_SAR_VSSA_SARSEQ_CTRL
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl)
+{
+ Cy_SAR_SetSwitchSarSeqCtrl(base, SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk, ctrl);
+}
+/** \} */
+
+/** \} group_sar_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /** !defined(CY_SAR_H) */
+
+/** \} group_sar */
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,412 @@
+/***************************************************************************//**
+* \file cy_scb_common.c
+* \version 2.10
+*
+* Provides common API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_scb_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArrayNoCheck
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO without checking if the
+* receive FIFO has enough data elements.
+* Before calling this function, make sure that the receive FIFO has enough data
+* elements to be read.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to location to place data read from the receive FIFO.
+* The size of the data element defined by the configured data width.
+*
+* \param size
+* The number of data elements read from the receive FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_ReadArrayNoCheck(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ uint32_t idx;
+
+ if (Cy_SCB_IsRxDataWidthByte(base))
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+
+ /* Get data available in RX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ buf[idx] = (uint8_t) Cy_SCB_ReadRxFifo(base);
+ }
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+
+ /* Get data available in RX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ buf[idx] = (uint16_t) Cy_SCB_ReadRxFifo(base);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArray
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO.
+* This function does not block; it returns how many data elements are
+* read from the receive FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to location to place data read from receive FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the receive FIFO.
+*
+* \return
+* The number of data elements read from the receive FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ /* Get available items in RX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
+
+ /* Adjust items that will be read */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ /* Get data available in RX FIFO */
+ Cy_SCB_ReadArrayNoCheck(base, buffer, numToCopy);
+
+ return (numToCopy);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadArrayBlocking
+****************************************************************************//**
+*
+* Reads an array of data out of the SCB receive FIFO.
+* This function blocks until the number of data elements specified by the
+* size has been read from the receive FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to the location to place data read from the receive FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from receive FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_ReadArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ uint32_t numCopied;
+ uint8_t *buf = (uint8_t *) buffer;
+ bool byteMode = Cy_SCB_IsRxDataWidthByte(base);
+
+ /* Get data from RX FIFO. Stop when the requested size is read. */
+ while (size > 0UL)
+ {
+ numCopied = Cy_SCB_ReadArray(base, (void *) buf, size);
+
+ buf = &buf[(byteMode ? (numCopied) : (2UL * numCopied))];
+ size -= numCopied;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_Write
+****************************************************************************//**
+*
+* Places a single data element in the SCB transmit FIFO.
+* This function does not block. It returns how many data elements are placed
+* in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param data
+* Data to put in the transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \return
+* The number of data elements placed in the transmit FIFO: 0 or 1.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_Write(CySCB_Type *base, uint32_t data)
+{
+ uint32_t numCopied = 0UL;
+
+ if (Cy_SCB_GetFifoSize(base) != Cy_SCB_GetNumInTxFifo(base))
+ {
+ Cy_SCB_WriteTxFifo(base, data);
+
+ numCopied = 1UL;
+ }
+
+ return (numCopied);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArrayNoCheck
+****************************************************************************//**
+*
+* Places an array of data in the SCB transmit FIFO without checking whether the
+* transmit FIFO has enough space.
+* Before calling this function, make sure that the transmit FIFO has enough
+* space to put all requested data elements.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_WriteArrayNoCheck(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ uint32_t idx;
+
+ if (Cy_SCB_IsTxDataWidthByte(base))
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+
+ /* Put data into TX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]);
+ }
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+
+ /* Put data into TX FIFO */
+ for (idx = 0UL; idx < size; ++idx)
+ {
+ Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArray
+****************************************************************************//**
+*
+* Places an array of data in the SCB transmit FIFO.
+* This function does not block. It returns how many data elements were
+* placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the transmit FIFO.
+* The item size is defined by the data type which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_WriteArray(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ /* Get free entries in TX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base);
+
+ /* Adjust the data elements to write */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ Cy_SCB_WriteArrayNoCheck(base, buffer, numToCopy);
+
+ return (numToCopy);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteArrayBlocking
+****************************************************************************//**
+*
+* Places an array of data in the transmit FIFO.
+* This function blocks until the number of data elements specified by the size
+* is placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param buffer
+* The pointer to data to place in transmit FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to write into the transmit FIFO.
+*
+*******************************************************************************/
+void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ uint32_t numCopied;
+ uint8_t *buf = (uint8_t *) buffer;
+ bool byteMode = Cy_SCB_IsTxDataWidthByte(base);
+
+ /* Get data from RX FIFO. Stop when the requested size is read. */
+ while (size > 0UL)
+ {
+ numCopied = Cy_SCB_WriteArray(base, (void *) buf, size);
+
+ buf = &buf[(byteMode ? (numCopied) : (2UL * numCopied))];
+ size -= numCopied;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteString
+****************************************************************************//**
+*
+* Places a NULL terminated string in the transmit FIFO.
+* This function blocks until the entire string is placed in the transmit FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param string
+* The pointer to the null terminated string array.
+*
+*******************************************************************************/
+void Cy_SCB_WriteString(CySCB_Type *base, char_t const string[])
+{
+ uint32_t idx = 0UL;
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+
+ /* Put data from TX FIFO. Stop when string is terminated */
+ while (((char_t) 0) != string[idx])
+ {
+ /* Wait for free space to be available */
+ while (fifoSize == Cy_SCB_GetNumInTxFifo(base))
+ {
+ }
+
+ Cy_SCB_WriteTxFifo(base, (uint32_t) string[idx]);
+ ++idx;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteDefaultArrayNoCheck
+****************************************************************************//**
+*
+* Places a number of the same data elements in the SCB transmit FIFO without
+* checking whether the transmit FIFO has enough space. The data elements is equal
+* to txData parameter.
+* Before calling this function, make sure that transmit FIFO has enough space
+* to put all requested data elements.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param txData
+* The data element to transmit repeatedly.
+*
+* \param size
+* The number of data elements to transmit.
+*
+*******************************************************************************/
+void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size)
+{
+ while (size > 0UL)
+ {
+ Cy_SCB_WriteTxFifo(base, txData);
+ --size;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteDefaultArray
+****************************************************************************//**
+*
+* Places a number of the same data elements in the SCB transmit FIFO.
+* The data elements is equal to the txData parameter.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param txData
+* The data element to transmit repeatedly.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the transmit FIFO.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_WriteDefaultArray(CySCB_Type *base, uint32_t txData, uint32_t size)
+{
+ /* Get free entries in TX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base);
+
+ /* Adjust data elements to write */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ Cy_SCB_WriteDefaultArrayNoCheck(base, txData, numToCopy);
+
+ return (numToCopy);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1754 @@
+/***************************************************************************//**
+* \file cy_scb_common.h
+* \version 2.10
+*
+* Provides common API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_scb Serial Communication Block (SCB)
+* \{
+* \defgroup group_scb_common Common
+* \defgroup group_scb_ezi2c EZI2C (SCB)
+* \defgroup group_scb_i2c I2C (SCB)
+* \defgroup group_scb_spi SPI (SCB)
+* \defgroup group_scb_uart UART (SCB)
+* \} */
+
+/**
+* \addtogroup group_scb_common
+* \{
+*
+* Common API for the Serial Communication Block.
+*
+* This is the common API that provides an interface to the SCB hardware.
+* The I2C, SPI, and UART drivers use this common API.
+* Most users will use individual drivers and do not need to use the common
+* API for the SCB. However, you can use the common SCB API to implement
+* a custom driver based on the SCB hardware.
+*
+* \section group_scb_common_configuration Configuration Considerations
+*
+* This is not a driver and it does not require configuration.
+*
+* \section group_scb_common_more_information More Information
+*
+* Refer to the SCB chapter of the technical reference manual (TRM).
+*
+* \section group_scb_common_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>The pointer to the buffer memory is void to allow handling of
+* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
+* The cast operation is safe because the configuration is verified
+* before operation is performed.
+* </td>
+* </tr>
+* </table>
+*
+* \section group_scb_common_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td>None.</td>
+* <td>SCB I2C driver updated.</td>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.0</td>
+* <td>Added parameters validation for public API.
+* <td></td>
+* </tr>
+* <tr>
+* <td>Fixed functions which return interrupt status to return only defined
+* set of interrupt statuses.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_scb_common_macros Macros
+* \defgroup group_scb_common_functions Functions
+* \defgroup group_scb_common_data_structures Data Structures
+*
+*/
+
+#if !defined(CY_SCB_COMMON_H)
+#define CY_SCB_COMMON_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXSCB
+ #error "The SCB driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_scb_common_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
+
+__STATIC_INLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
+__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base);
+
+__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask);
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask);
+
+
+/***************************************
+* Internal Function Prototypes
+***************************************/
+
+/** \cond INTERNAL */
+void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *buffer, uint32_t size);
+void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data);
+void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *buffer, uint32_t size);
+uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *buffer, uint32_t size);
+void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
+void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]);
+void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size);
+uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base);
+__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
+/** \endcond */
+
+/** \} group_scb_common_functions */
+
+/***************************************
+* API Constants
+***************************************/
+
+/**
+* \addtogroup group_scb_common_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SCB_DRV_VERSION_MAJOR (2)
+
+/** Driver minor version */
+#define CY_SCB_DRV_VERSION_MINOR (10)
+
+/** SCB driver identifier */
+#define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
+
+/** Position for SCB driver sub mode */
+#define CY_SCB_SUB_MODE_Pos (13UL)
+
+/** EZI2C mode identifier */
+#define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos)
+
+/** EZI2C mode identifier */
+#define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos)
+
+/**
+* \defgroup group_scb_common_macros_intr_cause SCB Interrupt Causes
+* \{
+*/
+/** Interrupt from Master interrupt sources */
+#define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk
+
+/** Interrupt from Slave interrupt sources */
+#define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk
+
+/** Interrupt from TX interrupt sources */
+#define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk
+
+/** Interrupt from RX interrupt sources */
+#define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk
+
+/** Interrupt from I2C externally clocked interrupt sources */
+#define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk
+
+/** Interrupt from SPI externally clocked interrupt sources */
+#define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk
+/** \} group_scb_common_macros_intr_cause */
+
+/**
+* \defgroup group_scb_common_macros_tx_intr TX Interrupt Statuses
+* \{
+*/
+/**
+* The number of data elements in the TX FIFO is less than the value
+* of the TX FIFO level
+*/
+#define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk
+
+/** The TX FIFO is not full */
+#define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk
+
+/** The TX FIFO is empty */
+#define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk
+
+/** An attempt to write to a full TX FIFO */
+#define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk
+
+/** An attempt to read from an empty TX FIFO */
+#define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk
+
+/** The UART transfer is complete: all data elements from the TX FIFO are sent
+*/
+#define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk
+
+/** SmartCard only: UART received a NACK */
+#define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk
+
+/**
+* SmartCard only: the value on the TX line of the UART does not match the
+* value on the RX line
+*/
+#define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk
+/** \} group_scb_common_macros_tx_intr */
+
+/**
+* \defgroup group_scb_common_macros_rx_intr RX Interrupt Statuses
+* \{
+*/
+/**
+* The number of data elements in the RX FIFO is greater than the value of the
+* RX FIFO level
+*/
+#define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk
+
+/** The RX FIFO is not empty */
+#define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk
+
+/** The RX FIFO is full */
+#define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk
+
+/** An attempt to write to a full RX FIFO */
+#define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk
+
+/** An attempt to read from an empty RX FIFO */
+#define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk
+
+/** A UART framing error detected */
+#define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk
+
+/** A UART parity error detected */
+#define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk
+
+/** A UART break detected */
+#define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk
+/** \} group_scb_common_macros_rx_intr */
+
+/**
+* \defgroup group_scb_common_macros_slave_intr Slave Interrupt Statuses
+* \{
+*/
+/**
+* I2C slave lost arbitration: the value driven on the SDA line is not the same
+* as the value observed on the SDA line
+*/
+#define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk
+
+/** The I2C slave received a NAK */
+#define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk
+
+/** The I2C slave received an ACK */
+#define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk
+
+/**
+* A Stop or Repeated Start event for a write transfer intended for this slave
+* was detected.
+*/
+#define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk
+
+/** A Stop or Repeated Start event intended for this slave was detected */
+#define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk
+
+/** The I2C slave received a Start condition */
+#define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk
+
+/** The I2C slave received the matching address */
+#define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk
+
+/** The I2C Slave received the general call address */
+#define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk
+
+/** The I2C slave bus error (detection of unexpected Start or Stop condition) */
+#define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk
+
+/**
+* The SPI slave select line is deselected at an expected time during an
+* SPI transfer.
+*/
+#define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk
+/** \} group_scb_common_macros_slave_intr */
+
+/**
+* \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
+* \{
+*/
+/** The I2C master lost arbitration */
+#define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
+
+/** The I2C master received a NACK */
+#define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk
+
+/** The I2C master received an ACK */
+#define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk
+
+/** The I2C master generated a Stop */
+#define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk
+
+/** The I2C master bus error (detection of unexpected START or STOP condition)
+*/
+#define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk
+
+/**
+* The SPI master transfer is complete: all data elements transferred from the
+* TX FIFO and TX shift register.
+*/
+#define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk
+/** \} group_scb_common_macros_master_intr */
+
+/**
+* \defgroup group_scb_common_macros_i2c_intr I2C Interrupt Statuses
+* \{
+*/
+/**
+* Wake up request: the I2C slave received the matching address.
+* Note that this interrupt source triggers in active mode.
+*/
+#define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk
+/** \} group_scb_common_macros_i2c_intr */
+
+/**
+* \defgroup group_scb_common_macros_SpiIntrStatuses SPI Interrupt Statuses
+* \{
+*/
+/**
+* Wake up request: the SPI slave detects an active edge of the slave select
+* signal. Note that this interrupt source triggers in active mode.
+*/
+#define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
+/** \} group_scb_common_macros_SpiIntrStatuses */
+
+
+/***************************************
+* Internal Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* Default registers values */
+#define CY_SCB_CTRL_DEF_VAL (_VAL2FLD(SCB_CTRL_OVS, 15UL) | \
+ _VAL2FLD(SCB_CTRL_MODE, 3UL))
+
+#define CY_SCB_I2C_CTRL_DEF_VAL (_VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_M_READY_DATA_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_M_NOT_READY_DATA_NACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_READY_ADDR_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_READY_DATA_ACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK, 1UL) | \
+ _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_DATA_NACK, 1UL))
+
+#define CY_SCB_I2C_CFG_DEF_VAL (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 3UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_SEL, 1UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SCL_IN_FILT_SEL, 1UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT0_TRIM, 2UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT1_TRIM, 2UL) | \
+ _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT2_TRIM, 2UL))
+
+#define CY_SCB_SPI_CTRL_DEF_VAL _VAL2FLD(SCB_SPI_CTRL_MODE, 3UL)
+#define CY_SCB_UART_CTRL_DEF_VAL _VAL2FLD(SCB_UART_CTRL_MODE, 3UL)
+
+#define CY_SCB_UART_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, 2UL) | \
+ _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, 10UL))
+
+#define CY_SCB_UART_TX_CTRL_DEF_VAL _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, 2UL)
+
+#define CY_SCB_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, 7UL) | \
+ _VAL2FLD(SCB_RX_CTRL_MSB_FIRST, 1UL))
+
+#define CY_SCB_TX_CTRL_DEF_VAL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, 7UL) | \
+ _VAL2FLD(SCB_TX_CTRL_MSB_FIRST, 1UL))
+
+/* SCB CTRL modes */
+#define CY_SCB_CTRL_MODE_I2C (0UL)
+#define CY_SCB_CTRL_MODE_SPI (1UL)
+#define CY_SCB_CTRL_MODE_UART (2UL)
+
+/* The position and mask to set the I2C mode */
+#define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
+#define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
+ SCB_I2C_CTRL_MASTER_MODE_Msk)
+
+/* Cypress ID #282226:
+* SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
+*/
+#define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
+
+/* I2C has fixed data width */
+#define CY_SCB_I2C_DATA_WIDTH (7UL)
+
+/* RX and TX control register values */
+#define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
+ SCB_RX_CTRL_MSB_FIRST_Msk)
+#define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
+ SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk)
+
+/* The position and mask to make an address byte */
+#define CY_SCB_I2C_ADDRESS_Pos (1UL)
+#define CY_SCB_I2C_ADDRESS_Msk (0xFEUL)
+
+/* SPI slave select polarity */
+#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos
+#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \
+ SCB_SPI_CTRL_SSEL_POLARITY3_Msk)
+
+/* SPI clock modes: CPHA and CPOL */
+#define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos
+#define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk)
+
+/* UART parity and parity enable combination */
+#define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \
+ SCB_UART_RX_CTRL_PARITY_Msk)
+#define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos SCB_UART_RX_CTRL_PARITY_Pos
+
+#define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \
+ SCB_UART_TX_CTRL_PARITY_Msk)
+#define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos SCB_UART_TX_CTRL_PARITY_Pos
+
+/* Max number of bits for byte mode */
+#define CY_SCB_BYTE_WIDTH (8UL)
+
+/* Single unit to wait */
+#define CY_SCB_WAIT_1_UNIT (1U)
+
+/* Clear interrupt sources */
+#define CY_SCB_CLEAR_ALL_INTR_SRC (0UL)
+
+/* Hardware FIFO size */
+#define CY_SCB_FIFO_SIZE(base) (SCB_GET_EZ_DATA_NR(base) / 2UL)
+
+/* Provides a list of allowed sources */
+#define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_INTR_EMPTY | \
+ CY_SCB_TX_INTR_OVERFLOW | CY_SCB_TX_INTR_UNDERFLOW | CY_SCB_TX_INTR_UART_DONE | \
+ CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_RX_INTR_MASK (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_FULL | \
+ CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UNDERFLOW | \
+ CY_SCB_RX_INTR_UART_FRAME_ERROR | CY_SCB_RX_INTR_UART_PARITY_ERROR | \
+ CY_SCB_RX_INTR_UART_BREAK_DETECT)
+
+
+#define CY_SCB_SLAVE_INTR_MASK (CY_SCB_SLAVE_INTR_I2C_ARB_LOST | CY_SCB_SLAVE_INTR_I2C_NACK | CY_SCB_SLAVE_INTR_I2C_ACK | \
+ CY_SCB_SLAVE_INTR_I2C_WRITE_STOP | CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_START | \
+ CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
+ CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)
+
+#define CY_SCB_MASTER_INTR_MASK (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_NACK | \
+ CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_STOP | \
+ CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_SPI_DONE)
+
+#define CY_SCB_I2C_INTR_MASK CY_SCB_I2C_INTR_WAKEUP
+
+#define CY_SCB_SPI_INTR_MASK CY_SCB_SPI_INTR_WAKEUP
+
+#define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) )
+#define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base))
+
+#define CY_SCB_IS_I2C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) )
+#define CY_SCB_IS_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) )
+#define CY_SCB_IS_I2C_BUFFER_VALID(buffer, size) ( (0UL == (size)) ? true : (NULL != (buffer)) )
+/** \endcond */
+
+/** \} group_scb_common_macros */
+
+
+/***************************************
+* Inline Function Implementation
+***************************************/
+
+/**
+* \addtogroup group_scb_common_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ReadRxFifo
+****************************************************************************//**
+*
+* Reads a data element directly out of the RX FIFO.
+* This function does not check whether the RX FIFO has data before reading it.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Data from RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base)
+{
+ return (base->RX_FIFO_RD);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxFifoLevel
+****************************************************************************//**
+*
+* Sets the RX FIFO level. When there are more data elements in the RX FIFO than
+* this level, the RX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param level
+* When there are more data elements in the FIFO than this level, the RX level
+* interrupt is triggered.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ base->RX_FIFO_CTRL = _CLR_SET_FLD32U(base->RX_FIFO_CTRL, SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetNumInRxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements currently in the RX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The number or data elements in RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxSrValid
+****************************************************************************//**
+*
+* Returns the status of the RX FIFO Shift Register valid bit.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* 1 - RX shift register valid; 0 - RX shift register not valid.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, base->RX_FIFO_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearRxFifo
+****************************************************************************//**
+*
+* Clears the RX FIFO and shifter.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \note
+* If there is partial data in the shifter, it is cleared and lost.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
+{
+ base->RX_FIFO_CTRL |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk;
+ base->RX_FIFO_CTRL &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk;
+
+ (void) base->RX_FIFO_CTRL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_WriteTxFifo
+****************************************************************************//**
+*
+* Writes data directly into the TX FIFO.
+* This function does not check whether the TX FIFO is not full before writing
+* into it.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param data
+* Data to write to the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
+{
+ base->TX_FIFO_WR = data;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxFifoLevel
+****************************************************************************//**
+*
+* Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
+* this level, the TX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param level
+* When there are fewer data elements in the FIFO than this level, the TX level
+* interrupt is triggered.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ base->TX_FIFO_CTRL = _CLR_SET_FLD32U(base->TX_FIFO_CTRL, SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetNumInTxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements currently in the TX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The number or data elements in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxSrValid
+****************************************************************************//**
+*
+* Returns the status of the TX FIFO Shift Register valid bit.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* 1 - TX shift register valid; 0 - TX shift register not valid.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, base->TX_FIFO_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsTxComplete
+****************************************************************************//**
+*
+* Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
+*
+* \param base
+* Pointer to SPI the SCB instance.
+*
+* \return
+* If true, transmission complete. If false, transmission is not complete.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
+{
+ return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearTxFifo
+****************************************************************************//**
+*
+* Clears the TX FIFO.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \note
+* The TX FIFO clear operation also clears the shift register. Thus the shifter
+* could be cleared in the middle of a data element transfer. Thia results in
+* "ones" being sent on the bus for the remainder of the transfer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
+{
+ base->TX_FIFO_CTRL |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk;
+ base->TX_FIFO_CTRL &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk;
+
+ (void) base->TX_FIFO_CTRL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetByteMode
+****************************************************************************//**
+*
+* Sets whether the RX and TX FIFOs are in byte mode.
+* The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
+* When the FIFO is in byte mode it is twice as deep. See the device datasheet
+* for FIFO depths.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param byteMode
+* If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode)
+{
+ if (byteMode)
+ {
+ base->CTRL |= SCB_CTRL_BYTE_MODE_Msk;
+ }
+ else
+ {
+ base->CTRL &= ~SCB_CTRL_BYTE_MODE_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetInterruptCause
+****************************************************************************//**
+*
+* Returns the mask of bits showing the source of the current triggered
+* interrupt. This is useful for modes of operation where an interrupt can
+* be generated by conditions in multiple interrupt source registers.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The mask with the OR of the following conditions that have been triggered.
+* See \ref group_scb_common_macros_intr_cause for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base)
+{
+ return (base->INTR_CAUSE);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptStatus
+****************************************************************************//**
+*
+* Returns the RX interrupt request register. This register contains the current
+* status of the RX interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the RX interrupt sources. Each constant is a bit field
+* value. The value returned may have multiple bits set to indicate the
+* current status.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_RX & CY_SCB_RX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxInterruptMask
+****************************************************************************//**
+*
+* Writes the RX interrupt mask register. This register configures which bits
+* from the RX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ base->INTR_RX_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptMask
+****************************************************************************//**
+*
+* Returns the RX interrupt mask register. This register specifies which bits
+* from the RX interrupt request register trigger can an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_RX_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the RX interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the RX interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of the enabled RX interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled RX interrupt sources.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_RX_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearRxInterrupt
+****************************************************************************//**
+*
+* Clears the RX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The RX interrupt sources to be cleared.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+* \note
+* - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when
+* the RX FIFO has more entries than the level.
+* - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the
+* RX FIFO is not empty.
+* - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the
+* RX FIFO is full.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ base->INTR_RX = interruptMask;
+ (void) base->INTR_RX;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetRxInterrupt
+****************************************************************************//**
+*
+* Sets the RX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The RX interrupt sources to set in the RX interrupt request register.
+* See \ref group_scb_common_macros_rx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
+
+ base->INTR_RX_SET = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptStatus
+****************************************************************************//**
+*
+* Returns the TX interrupt request register. This register contains the current
+* status of the TX interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of TX interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_TX & CY_SCB_TX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxInterruptMask
+****************************************************************************//**
+*
+* Writes the TX interrupt mask register. This register configures which bits
+* from the TX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ base->INTR_TX_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptMask
+****************************************************************************//**
+*
+* Returns the TX interrupt mask register. This register specifies which
+* bits from the TX interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_TX_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetTxInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the TX interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the TX interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled TX interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled TX interrupt sources.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_TX_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearTxInterrupt
+****************************************************************************//**
+*
+* Clears the TX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The TX interrupt sources to be cleared.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+* \note
+* - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
+* TX FIFO has fewer entries than the TX level.
+* - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
+* TX FIFO has empty entries in the TX FIFO.
+* - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
+* TX FIFO is empty.
+* - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the
+* TX FIFO is empty. Put data into the TX FIFO before clearing it.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ base->INTR_TX = interruptMask;
+ (void) base->INTR_TX;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetTxInterrupt
+****************************************************************************//**
+*
+* Sets TX interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The TX interrupt sources to set in the TX interrupt request register.
+* See \ref group_scb_common_macros_tx_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
+
+ base->INTR_TX_SET = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptStatus
+****************************************************************************//**
+*
+* Returns the master interrupt request register. This register contains the current
+* status of the master interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the master interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_M & CY_SCB_MASTER_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetMasterInterruptMask
+****************************************************************************//**
+*
+* Writes the master interrupt mask register. This register specifies which bits
+* from the master interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to be enable.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ base->INTR_M_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptMask
+****************************************************************************//**
+*
+* Returns the master interrupt mask register. This register specifies which bits
+* from the master interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled master interrupt sources.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_M_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetMasterInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the master interrupt masked request register. This register contains a
+* logical AND of corresponding bits from the master interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of the enabled master interrupt sources caused the interrupt
+* event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled master interrupt sources.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_M_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearMasterInterrupt
+****************************************************************************//**
+*
+* Clears master interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to be cleared.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ base->INTR_M = interruptMask;
+ (void) base->INTR_M;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetMasterInterrupt
+****************************************************************************//**
+*
+* Sets master interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The master interrupt sources to set in the master interrupt request register.
+* See \ref group_scb_common_macros_master_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
+
+ base->INTR_M_SET = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptStatus
+****************************************************************************//**
+*
+* Returns the slave interrupt request register. This register contains the current
+* status of the slave interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the slave interrupt sources.
+* Each constant is a bit field value. The value returned may have multiple
+* bits set to indicate the current status.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_S & CY_SCB_SLAVE_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSlaveInterruptMask
+****************************************************************************//**
+*
+* Writes slave interrupt mask register.
+* This register specifies which bits from the slave interrupt request register
+* can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ base->INTR_S_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptMask
+****************************************************************************//**
+*
+* Returns the slave interrupt mask register.
+* This register specifies which bits from the slave interrupt request register
+* can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_S_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSlaveInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the slave interrupt masked request register. This register contains a
+* logical AND of corresponding bits from the slave interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled slave interrupt sources caused the interrupt
+* event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled slave interrupt sources.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_S_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearSlaveInterrupt
+****************************************************************************//**
+*
+* Clears the slave interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Slave interrupt sources to be cleared.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ base->INTR_S = interruptMask;
+ (void) base->INTR_S;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSlaveInterrupt
+****************************************************************************//**
+*
+* Sets slave interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The slave interrupt sources to set in the slave interrupt request register
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
+
+ base->INTR_S_SET = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptStatus
+****************************************************************************//**
+*
+* Returns the I2C interrupt request register. This register contains the
+* current status of the I2C interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of the I2C interrupt sources. Each constant is a bit
+* field value.
+* The value returned may have multiple bits set to indicate the current status.
+* See \ref group_scb_common_macros_slave_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_I2C_EC & CY_SCB_I2C_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetI2CInterruptMask
+****************************************************************************//**
+*
+* Writes the I2C interrupt mask register. This register specifies which bits
+* from the I2C interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
+
+ base->INTR_I2C_EC_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptMask
+****************************************************************************//**
+*
+* Returns the I2C interrupt mask register. This register specifies which bits
+* from the I2C interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_I2C_EC_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetI2CInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the I2C interrupt masked request register. This register contains
+* a logical AND of corresponding bits from I2C interrupt request and mask
+* registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled I2C interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled I2C interrupt sources.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_I2C_EC_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearI2CInterrupt
+****************************************************************************//**
+*
+* Clears I2C interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The I2C interrupt sources to be cleared.
+* See \ref group_scb_common_macros_i2c_intr for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
+
+ base->INTR_I2C_EC = interruptMask;
+ (void) base->INTR_I2C_EC;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptStatus
+****************************************************************************//**
+*
+* Returns the SPI interrupt request register. This register contains the current
+* status of the SPI interrupt sources.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of SPI interrupt sources. Each constant is a bit field value.
+* The value returned may have multiple bits set to indicate the current status
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base)
+{
+ return (base->INTR_SPI_EC & CY_SCB_SPI_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SetSpiInterruptMask
+****************************************************************************//**
+*
+* Writes the SPI interrupt mask register. This register specifies which
+* bits from the SPI interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* Enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
+
+ base->INTR_SPI_EC_MASK = interruptMask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptMask
+****************************************************************************//**
+*
+* Returns the SPI interrupt mask register. This register specifies which bits
+* from the SPI interrupt request register can trigger an interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* Enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base)
+{
+ return (base->INTR_SPI_EC_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetSpiInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns the SPI interrupt masked request register. This register contains
+* a logical AND of corresponding bits from the SPI interrupt request and
+* mask registers.
+* This function is intended to be used in the interrupt service routine to
+* identify which of enabled SPI interrupt sources caused the interrupt event.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* The current status of enabled SPI interrupt sources.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base)
+{
+ return (base->INTR_SPI_EC_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_ClearSpiInterrupt
+****************************************************************************//**
+*
+* Clears SPI interrupt sources in the interrupt request register.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \param interruptMask
+* The SPI interrupt sources to be cleared.
+* See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
+
+ base->INTR_SPI_EC = interruptMask;
+ (void) base->INTR_SPI_EC;
+}
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Function Name: Cy_SCB_GetFifoSize
+****************************************************************************//**
+*
+* Returns the RX and TX FIFO depth.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* FIFO depth.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base)
+{
+ return (_FLD2BOOL(SCB_CTRL_BYTE_MODE, base->CTRL) ?
+ (CY_SCB_FIFO_SIZE(base)) : (CY_SCB_FIFO_SIZE(base) / 2UL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsRxDataWidthByte
+****************************************************************************//**
+*
+* Returns true if the RX data width is a byte (8 bits).
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* True if the RX data width is a byte (8 bits).
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
+{
+ return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, base->RX_CTRL) < CY_SCB_BYTE_WIDTH);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_IsTxDataWidthByte
+****************************************************************************//**
+*
+* Returns true if the TX data width is a byte (8 bits).
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* If true, the TX data width is a byte (8 bits). Otherwise, false.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
+{
+ return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, base->TX_CTRL) < CY_SCB_BYTE_WIDTH);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_FwBlockReset
+****************************************************************************//**
+*
+* Disables and enables the block to return it into the known state (default):
+* FIFOs and interrupt statuses are cleared.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base)
+{
+ base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ /* Clean-up command registers */
+ base->I2C_M_CMD = 0UL;
+ base->I2C_S_CMD = 0UL;
+
+ base->CTRL |= (uint32_t) SCB_CTRL_ENABLED_Msk;
+
+ (void) base->CTRL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_GetRxFifoLevel
+****************************************************************************//**
+*
+* Returns the RX FIFO level when there are more words in the RX FIFO than the
+* level, the RX FIFO level interrupt is triggered.
+*
+* \param base
+* The pointer to the SCB instance.
+*
+* \return
+* RX FIFO level.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, base->RX_FIFO_CTRL);
+}
+
+/** \endcond */
+/** \} group_scb_common_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_common */
+
+#endif /* (CY_SCB_COMMON_H) */
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1302 @@
+/***************************************************************************//**
+* \file cy_scb_ezi2c.c
+* \version 2.10
+*
+* Provides EZI2C API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_scb_ezi2c.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+static void HandleErrors (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+static void HandleAddress (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+static void UpdateRxFifoLevel (CySCB_Type *base, uint32_t bufSize);
+static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+static void HandleStop (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+static void UpdateAddressMask (CySCB_Type *base, cy_stc_scb_ezi2c_context_t const *context);
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_Init
+****************************************************************************//**
+*
+* Initializes the SCB for the EZI2C operation.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param config
+* The pointer to the configuration structure \ref cy_stc_scb_ezi2c_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_ezi2c_status_t
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config,
+ cy_stc_scb_ezi2c_context_t *context)
+{
+ /* Input parameters verification */
+ if ((NULL == base) || (NULL == config) || (NULL == context))
+ {
+ return CY_SCB_EZI2C_BAD_PARAM;
+ }
+
+ if (!SCB_IS_I2C_SLAVE_CAPABLE(base))
+ {
+ return CY_SCB_EZI2C_BAD_PARAM;
+ }
+
+ if ((config->enableWakeFromSleep) && (!SCB_IS_I2C_DS_CAPABLE(base)))
+ {
+ return CY_SCB_EZI2C_BAD_PARAM;
+ }
+
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress1));
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress2));
+ CY_ASSERT_L2(config->slaveAddress1 != config->slaveAddress2);
+ CY_ASSERT_L3(CY_SCB_EZI2C_IS_NUM_OF_ADDR_VALID (config->numberOfAddresses));
+ CY_ASSERT_L3(CY_SCB_EZI2C_IS_SUB_ADDR_SIZE_VALID(config->subAddressSize));
+
+ /* Configure the EZI2C interface */
+ base->CTRL = _BOOL2FLD(SCB_CTRL_ADDR_ACCEPT, (config->numberOfAddresses == CY_SCB_EZI2C_TWO_ADDRESSES)) |
+ _BOOL2FLD(SCB_CTRL_EC_AM_MODE, config->enableWakeFromSleep) |
+ SCB_CTRL_BYTE_MODE_Msk;
+
+ base->I2C_CTRL = CY_SCB_EZI2C_I2C_CTRL;
+
+ /* Configure the RX direction */
+ base->RX_CTRL = CY_SCB_EZI2C_RX_CTRL;
+ base->RX_FIFO_CTRL = 0UL;
+
+ /* Set the default address and mask */
+ if (config->numberOfAddresses == CY_SCB_EZI2C_ONE_ADDRESS)
+ {
+ context->address2 = 0U;
+ Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context);
+ }
+ else
+ {
+ Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context);
+ Cy_SCB_EZI2C_SetAddress2(base, config->slaveAddress2, context);
+ }
+
+ /* Configure the TX direction */
+ base->TX_CTRL = CY_SCB_EZI2C_TX_CTRL;
+ base->TX_FIFO_CTRL = CY_SCB_EZI2C_HALF_FIFO_SIZE(base);
+
+ /* Configure the interrupt sources */
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+ base->INTR_S_MASK = CY_SCB_EZI2C_SLAVE_INTR;
+
+ /* Initialize the context */
+ context->status = 0UL;
+ context->state = CY_SCB_EZI2C_STATE_IDLE;
+
+ context->subAddrSize = config->subAddressSize;
+
+ context->buf1Size = 0UL;
+ context->buf1rwBondary = 0UL;
+ context->baseAddr1 = 0UL;
+
+ context->buf1Size = 0UL;
+ context->buf1rwBondary = 0UL;
+ context->baseAddr2 = 0UL;
+
+ return CY_SCB_EZI2C_SUCCESS;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_DeInit
+****************************************************************************//**
+*
+* De-initializes the SCB block, returns the register values to default.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_DeInit(CySCB_Type *base)
+{
+ /* Return the block registers into the default state */
+ base->CTRL = CY_SCB_CTRL_DEF_VAL;
+ base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL;
+
+ base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL;
+ base->RX_FIFO_CTRL = 0UL;
+ base->RX_MATCH = 0UL;
+
+ base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL;
+ base->TX_FIFO_CTRL = 0UL;
+
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+ base->INTR_S_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_Disable
+****************************************************************************//**
+*
+* Disables the SCB block and clears the context statuses.
+* Note that after the block is disabled, the TX and RX FIFOs and hardware
+* statuses are cleared. Also, the hardware stops driving the output and
+* ignores the input.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* Calling this function while EZI2C is busy (the slave has been addressed and is
+* communicating with the master), may cause transaction corruption because
+* the hardware stops driving the output and ignores the input. Ensure that
+* the EZI2C slave is not busy before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ /* Set the state to default and clear the statuses */
+ context->status = 0UL;
+ context->state = CY_SCB_EZI2C_STATE_IDLE;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the EZI2C SCB into and out of
+* Deep Sleep mode. It prevents the device from entering Deep Sleep mode if
+* the EZI2C slave is actively communicating.
+* The following behavior of the EZI2C depends on whether the SCB block is
+* wakeup-capable:
+* * The SCB <b>wakeup-capable</b>: on the incoming EZI2C slave address, the slave
+* receives the address and stretches the clock until the device is woken from
+* Deep Sleep mode. If the slave address occurs before the device enters
+* Deep Sleep mode, the device will not enter Deep Sleep mode.
+* * The SCB is <b>not wakeup-capable</b>: the EZI2C is disabled. It is enabled
+* when the device fails to enter Deep Sleep mode or it is woken from Deep Sleep
+* mode. While the EZI2C is disabled, it stops driving the outputs and
+* ignores the input lines. The slave NACKs all incoming addresses.
+*
+* This function must be called during execution of \ref Cy_SysPm_DeepSleep.
+* To do this, register this function as a callback before calling
+* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure.
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the EZI2C slave is configured to be a wakeup source
+* from Deep Sleep mode, this function must be copied and modified by the user.
+* The EZI2C clock disable code must be inserted in the
+* \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the
+* \ref CY_SYSPM_AFTER_TRANSITION mode processing.
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_ezi2c_context_t *locContext = (cy_stc_scb_ezi2c_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch (callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Disable the slave interrupt sources to protect the state */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* If the EZI2C is in the IDLE state, it is ready for Deep Sleep
+ * mode. Otherwise, it returns fail and restores the slave interrupt
+ * sources.
+ */
+ if (CY_SCB_EZI2C_STATE_IDLE == locContext->state)
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: do not restore the address
+ * match interrupt source. The next transaction intended
+ * for the slave will be paused (the SCL is stretched) before
+ * the address is ACKed because the corresponding interrupt
+ * source is disabled.
+ */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR_NO_ADDR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: disable the EZI2C.
+ * The slave stops responding to the master until the
+ * EZI2C is enabled. This happens when the device fails
+ * to enter Deep Sleep mode or it is woken from Deep Sleep
+ * mode.
+ */
+ Cy_SCB_EZI2C_Disable(locBase, locContext);
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ else
+ {
+ /* Restore the slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Deep Sleep mode. Restore
+ * Active mode configuration.
+ */
+
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: restore the slave interrupt
+ * sources.
+ */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: enable the slave to operate. */
+ Cy_SCB_EZI2C_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* This code executes inside the critical section and enabling the
+ * active interrupt source makes the interrupt pending in the NVIC.
+ * However, the interrupt processing is delayed until the code exists
+ * the critical section. The pending interrupt force WFI instruction
+ * does nothing and the device remains in Active mode.
+ */
+
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: enable the I2C wakeup interrupt
+ * source. If any transaction was paused the the EZI2C interrupt
+ * becomes pending and prevents entering Deep Sleep mode.
+ * The transaction continues as soon as the global interrupts
+ * are enabled.
+ */
+ Cy_SCB_SetI2CInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
+
+ /* Disable SCB clock */
+ locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper entering Deep Sleep mode the I2C clock must be disabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* Enable SCB clock */
+ locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper exiting Deep Sleep mode, the I2C clock must be enabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+
+ /* The SCB is wakeup-capable: disable the I2C wakeup interrupt
+ * source and restore slave interrupt sources.
+ */
+ Cy_SCB_SetI2CInterruptMask (locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: enable the slave to operate */
+ Cy_SCB_EZI2C_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the EZI2C SCB block into Hibernate
+* mode. It prevents the device from entering Hibernate mode if the EZI2C slave
+* is actively communicating.
+* If the EZI2C is ready to enter Hibernate mode, it is disabled. If the device
+* fails to enter Hibernate mode, the EZI2C is enabled. While the EZI2C
+* is disabled, it stops driving the output and ignores the inputs.
+* The slave NACKs all incoming addresses.
+*
+* This function must be called during execution of \ref Cy_SysPm_Hibernate.
+* To do this, register this function as a callback before calling
+* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_ezi2c_context_t *locContext = (cy_stc_scb_ezi2c_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch (callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Disable the slave interrupt sources to protect the state */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* If the EZI2C is in the IDLE state, it is ready for Hibernate mode.
+ * Otherwise, returns fail and restores the slave interrupt sources.
+ */
+ if (CY_SCB_EZI2C_STATE_IDLE == locContext->state)
+ {
+ /* Disable the EZI2C. It stops responding to the master until
+ * the EZI2C is enabled. This happens if the device fails to
+ * enter Hibernate mode.
+ */
+ Cy_SCB_EZI2C_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+
+ /* Restore the slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Hibernate mode. Restore the
+ * Active mode configuration.
+ */
+
+ /* Enable the slave to operate */
+ Cy_SCB_EZI2C_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* The SCB is not capable of waking up from Hibernate mode: do nothing */
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_GetActivity
+****************************************************************************//**
+*
+* Returns a non-zero value if an I2C Read or Write cycle has occurred since the
+* last time this function was called. All flags are reset to zero at the end of
+* this function call, except the \ref CY_SCB_EZI2C_STATUS_BUSY.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_ezi2c_macros_get_activity.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ uint32_t intrState;
+ uint32_t retStatus;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ retStatus = context->status;
+ context->status &= CY_SCB_EZI2C_STATUS_BUSY;
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_SetAddress1
+****************************************************************************//**
+*
+* Sets the primary EZI2C slave address.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param addr
+* The 7-bit right justified slave address.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr));
+ CY_ASSERT_L2(addr != context->address2);
+
+ context->address1 = addr;
+
+ base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL)));
+
+ UpdateAddressMask(base, context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_GetAddress1
+****************************************************************************//**
+*
+* Returns the primary the EZI2C slave address.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* * \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The 7-bit right justified slave address.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return ((uint32_t) context->address1);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_SetBuffer1
+****************************************************************************//**
+*
+* Sets up the data buffer to be exposed to the I2C master on the primary slave
+* address request.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param buffer
+* The pointer to the data buffer.
+*
+* \param size
+* The size of the buffer in bytes.
+*
+* \param rwBoundary
+* The number of data bytes starting from the beginning of the buffer with Read and
+* Write access. The data bytes located at rwBoundary or greater are read only.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * This function is not interrupt-protected and to prevent a race condition,
+* it must be protected from the EZI2C interruption in the place where it
+* is called.
+* * Calling this function in the middle of a transaction intended for the
+* secondary slave address leads to unexpected behavior.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context)
+{
+ CY_ASSERT_L1(CY_SCB_IS_I2C_BUFFER_VALID(buffer, size));
+ CY_ASSERT_L2(rwBoundary <= size);
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->buf1 = buffer;
+ context->buf1Size = size;
+ context->buf1rwBondary = rwBoundary;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_SetAddress2
+****************************************************************************//**
+*
+* Sets the secondary EZI2C slave address.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param addr
+* The 7-bit right justified slave address.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* Calling this function when the EZI2C slave is configured for one-address
+* operation leads to unexpected behavior because it updates the address mask.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr));
+ CY_ASSERT_L2(addr != context->address1);
+
+ context->address2 = addr;
+
+ UpdateAddressMask(base, context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_GetAddress2
+****************************************************************************//**
+*
+* Returns the secondary EZI2C slave address.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The 7-bit right justified slave address.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return ((uint32_t) context->address2);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_SetBuffer2
+****************************************************************************//**
+*
+* Sets up the data buffer to be exposed to the I2C master on the secondary
+* slave address request.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param buffer
+* The pointer to the data buffer.
+*
+* \param size
+* The size of the buffer in bytes.
+*
+* \param rwBoundary
+* The number of data bytes starting from the beginning of the buffer with Read and
+* Write access. The data bytes located at rwBoundary or greater are read only.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
+* allocated by the user. The structure is used during the EZI2C operation for
+* internal configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * This function is not interrupt-protected. To prevent a race condition,
+* it must be protected from the EZI2C interruption in the place where it
+* is called.
+* * Calling this function in the middle of a transaction intended for the
+* secondary slave address leads to unexpected behavior.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context)
+{
+ CY_ASSERT_L1(CY_SCB_IS_I2C_BUFFER_VALID(buffer, size));
+ CY_ASSERT_L2(rwBoundary <= size);
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->buf2 = buffer;
+ context->buf2Size = size;
+ context->buf2rwBondary = rwBoundary;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_Interrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in the EZI2C mode.
+* This function must be called inside the user-defined interrupt service
+* routine to make the EZI2C slave work.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ uint32_t slaveIntrStatus;
+
+ /* Handle an I2C wake-up event */
+ if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base)))
+ {
+ /* Move from IDLE state, the slave was addressed. Following address match
+ * interrupt continue transfer.
+ */
+ context->state = CY_SCB_EZI2C_STATE_ADDR;
+
+ Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
+ }
+
+ /* Get the slave interrupt sources */
+ slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);
+
+ /* Handle the error conditions */
+ if (0UL != (CY_SCB_EZI2C_SLAVE_INTR_ERROR & slaveIntrStatus))
+ {
+ HandleErrors(base, context);
+
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_EZI2C_SLAVE_INTR_ERROR);
+
+ /* Trigger the stop handling to complete the transaction */
+ slaveIntrStatus |= CY_SCB_SLAVE_INTR_I2C_STOP;
+ }
+ else
+ {
+ if ((CY_SCB_EZI2C_STATE_RX_DATA1 == context->state) &&
+ (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus)))
+ {
+ /* Get data from the RX FIFO after Stop is generated */
+ Cy_SCB_SetRxInterrupt (base, CY_SCB_RX_INTR_LEVEL);
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ }
+
+ /* Handle the receive direction (master writes data) */
+ if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ HandleDataReceive(base, context);
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ /* Handle the transaction completion */
+ if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))
+ {
+ HandleStop(base, context);
+
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP);
+
+ /* Update the slave interrupt status */
+ slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);
+ }
+
+ /* Handle the address byte */
+ if (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH & slaveIntrStatus))
+ {
+ HandleAddress(base, context);
+
+ Cy_SCB_ClearI2CInterrupt (base, CY_SCB_I2C_INTR_WAKEUP);
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH);
+ }
+
+ /* Handle the transmit direction (master reads data) */
+ if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ HandleDataTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+}
+
+
+
+/*******************************************************************************
+* Function Name: HandleErrors
+****************************************************************************//**
+*
+* Handles an error conditions.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleErrors(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ context->status |= CY_SCB_EZI2C_STATUS_ERR;
+
+ /* Drop any data available in the RX FIFO */
+ Cy_SCB_ClearRxFifo(base);
+
+ /* Stop the TX and RX processing */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+}
+
+
+/*******************************************************************************
+* Function Name: HandleAddress
+****************************************************************************//**
+*
+* Prepares the EZI2C slave for the following read or write transfer after the
+* matched address was received.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleAddress(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ /* Default actions: ACK address 1 */
+ uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk;
+ context->addr1Active = true;
+
+ if (0U != context->address2)
+ {
+ /* Get an address from the RX FIFO and make it a 7-bit address */
+ uint32_t address = (Cy_SCB_ReadRxFifo(base) >> 1UL);
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+
+ /* Decide whether the address matches */
+ if ((address == context->address1) || (address == context->address2))
+ {
+ /* ACK the address */
+ if (address == context->address2)
+ {
+ context->addr1Active = false;
+ }
+
+ /* Clear and enable the stop interrupt source */
+ Cy_SCB_ClearSlaveInterrupt (base, CY_SCB_SLAVE_INTR_I2C_STOP);
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_EZI2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* NACK the address */
+ cmd = SCB_I2C_S_CMD_S_NACK_Msk;
+
+ /* Disable the stop interrupt source */
+ Cy_SCB_SetI2CInterruptMask(base, CY_SCB_EZI2C_SLAVE_INTR_NO_STOP);
+ }
+ }
+
+ /* Clear the TX FIFO before continuing the transaction */
+ Cy_SCB_ClearTxFifo(base);
+
+ /* Set the command to an ACK or NACK address */
+ base->I2C_S_CMD = cmd;
+
+ if (cmd == SCB_I2C_S_CMD_S_ACK_Msk)
+ {
+ context->status |= CY_SCB_EZI2C_STATUS_BUSY;
+
+ /* Prepare for a transaction */
+ if (_FLD2BOOL(SCB_I2C_STATUS_S_READ,base->I2C_STATUS))
+ {
+ /* The master reads data from the slave */
+ context->state = CY_SCB_EZI2C_STATE_TX_DATA;
+
+ /* Prepare the buffer for transmit */
+ if (context->addr1Active)
+ {
+ context->curBuf = &context->buf1[context->baseAddr1];
+ context->bufSize = context->buf1Size - context->baseAddr1;
+ }
+ else
+ {
+ context->curBuf = &context->buf2[context->baseAddr2];
+ context->bufSize = context->buf2Size - context->baseAddr2;
+ }
+
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+ else
+ {
+ /* The master writes data into the slave */
+ context->state = CY_SCB_EZI2C_STATE_RX_OFFSET_MSB;
+
+ context->bufSize = ((context->addr1Active) ? context->buf1Size : context->buf2Size);
+
+ Cy_SCB_SetRxFifoLevel (base, 0UL);
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleDataReceive
+****************************************************************************//**
+*
+* Updates the RX FIFO level to trigger the next read from it. It also manages
+* the auto-data NACK feature.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param bufSize
+* The size of the buffer in bytes.
+*
+*******************************************************************************/
+static void UpdateRxFifoLevel(CySCB_Type *base, uint32_t bufSize)
+{
+ uint32_t level;
+ uint32_t fifoSize = CY_SCB_EZI2C_FIFO_SIZE(base);
+
+ if (bufSize > fifoSize)
+ {
+ /* Continue the transaction: there is space in the buffer */
+ level = (bufSize - fifoSize);
+ level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL;
+ }
+ else
+ {
+ /* Prepare to end the transaction: after the FIFO becomes full, NACK the next byte.
+ * The NACKed byte is dropped by the hardware.
+ */
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk;
+
+ level = ((bufSize == 0UL) ? (0UL) : (bufSize - 1UL));
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ Cy_SCB_SetRxFifoLevel(base, level);
+}
+
+
+/*******************************************************************************
+* Function Name: HandleDataReceive
+****************************************************************************//**
+*
+* Handles the data read from the RX FIFO.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ switch(context->state)
+ {
+ case CY_SCB_EZI2C_STATE_RX_OFFSET_MSB:
+ case CY_SCB_EZI2C_STATE_RX_OFFSET_LSB:
+ {
+ /* Default actions: compare the base address and ACK it */
+ bool checkBaseAddr = true;
+
+ /* Get the base address from the RX FIFO */
+ uint32_t baseAddr = Cy_SCB_ReadRxFifo(base);
+
+ if (context->subAddrSize == CY_SCB_EZI2C_SUB_ADDR16_BITS)
+ {
+ if (context->state == CY_SCB_EZI2C_STATE_RX_OFFSET_MSB)
+ {
+ /* ACK base address MSB */
+ base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk;
+
+ /* Temporary store base address MSB */
+ context->idx = (uint32_t) (baseAddr << 8UL);
+
+ /* Do not compare until 16 bits are received */
+ checkBaseAddr = false;
+ context->state = CY_SCB_EZI2C_STATE_RX_OFFSET_LSB;
+ }
+ else
+ {
+ /* Get the base address (MSB | LSB) */
+ baseAddr |= context->idx;
+ }
+ }
+
+ /* Check whether the received base address is valid */
+ if (checkBaseAddr)
+ {
+ uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk;
+
+ /* Decide whether the base address within the buffer range */
+ if (baseAddr < context->bufSize)
+ {
+ /* Accept the new base address */
+ if (context->addr1Active)
+ {
+ context->baseAddr1 = baseAddr;
+ }
+ else
+ {
+ context->baseAddr2 = baseAddr;
+ }
+
+ /* Store the base address to use it later */
+ context->idx = baseAddr;
+ }
+ else
+ {
+ /* Restore the valid base address */
+ context->idx = ((context->addr1Active) ? context->baseAddr1 : context->baseAddr2);
+
+ /* The base address is out of range - NACK it */
+ cmd = SCB_I2C_S_CMD_S_NACK_Msk;
+ }
+
+ /* Set the command to an ACK or NACK address */
+ base->I2C_S_CMD = cmd;
+
+ if (cmd == SCB_I2C_S_CMD_S_ACK_Msk)
+ {
+ /* Prepare the buffer for a write */
+ if (context->addr1Active)
+ {
+ context->curBuf = &context->buf1[context->baseAddr1];
+ context->bufSize = ((context->baseAddr1 < context->buf1rwBondary) ?
+ (context->buf1rwBondary - context->baseAddr1) : (0UL));
+ }
+ else
+ {
+ context->curBuf = &context->buf2[context->baseAddr2];
+ context->bufSize = ((context->baseAddr2 < context->buf2rwBondary) ?
+ (context->buf2rwBondary - context->baseAddr2) : (0UL));
+ }
+
+ /* Choice receive scheme */
+ if ((0U != context->address2) || (context->bufSize < CY_SCB_EZI2C_FIFO_SIZE(base)))
+ {
+ /* Handle each byte separately */
+ context->state = CY_SCB_EZI2C_STATE_RX_DATA0;
+ }
+ else
+ {
+ /* Use the RX FIFO and the auto-ACK/NACK features */
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk;
+ UpdateRxFifoLevel(base, context->bufSize);
+
+ context->state = CY_SCB_EZI2C_STATE_RX_DATA1;
+ }
+ }
+ }
+ }
+ break;
+
+ case CY_SCB_EZI2C_STATE_RX_DATA0:
+ {
+ uint32_t byte = Cy_SCB_ReadRxFifo(base);
+
+ /* Check whether there is space to store the byte */
+ if (context->bufSize > 0UL)
+ {
+ /* Continue the transfer: send an ACK */
+ base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk;
+
+ /* Store the byte in the buffer */
+ context->curBuf[0UL] = (uint8_t) byte;
+ context->bufSize--;
+ context->curBuf++;
+
+ /* Update the base address to notice that the buffer is modified */
+ context->idx++;
+ }
+ else
+ {
+ /* Finish the transfer: send a NACK. Drop the received byte */
+ base->I2C_S_CMD = SCB_I2C_S_CMD_S_NACK_Msk;
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+ }
+ break;
+
+ case CY_SCB_EZI2C_STATE_RX_DATA1:
+ {
+ /* Get the number of bytes to read from the RX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetRxFifoLevel(base) + 1UL;
+
+ /* Get data from the RX FIFO */
+ numToCopy = Cy_SCB_ReadArray(base, context->curBuf, numToCopy);
+ context->bufSize -= numToCopy;
+ context->curBuf += numToCopy;
+
+ /* Configure the next RX FIFO read event */
+ UpdateRxFifoLevel(base, context->bufSize);
+
+ /* Update the base address to notice that the buffer is modified */
+ context->idx++;
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleDataTransmit
+****************************************************************************//**
+*
+* Loads the TX FIFO with data from the buffer.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ if (context->bufSize > 0UL)
+ {
+ /* Write data into the TX FIFO from the buffer */
+ uint32_t numToCopy = Cy_SCB_WriteArray(base, context->curBuf, context->bufSize);
+ context->bufSize -= numToCopy;
+ context->curBuf += numToCopy;
+ }
+
+ if (0UL == context->bufSize)
+ {
+ /* Write the default bytes into the TX FIFO */
+ (void) Cy_SCB_WriteDefaultArray(base, CY_SCB_EZI2C_DEFAULT_TX, CY_SCB_EZI2C_FIFO_SIZE(base));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleStop
+****************************************************************************//**
+*
+* Handles the transfer completion.
+* It is triggered by a Stop or Restart condition on the bus.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleStop(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
+{
+ /* Check for errors */
+ if (0UL != (CY_SCB_EZI2C_STATUS_ERR & context->status))
+ {
+ /* Re-enable the SCB to recover from errors */
+ Cy_SCB_FwBlockReset(base);
+ }
+
+ /* Clean up the hardware to be ready for the next transaction */
+ if (CY_SCB_EZI2C_STATE_TX_DATA == context->state)
+ {
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+ else
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ base->I2C_CTRL &= (uint32_t) ~(SCB_I2C_CTRL_S_READY_DATA_ACK_Msk |
+ SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk);
+ }
+
+ /* Update the statuses */
+ context->status &= (uint32_t) ~CY_SCB_EZI2C_STATUS_BUSY;
+
+ if (context->addr1Active)
+ {
+ context->status |= ((CY_SCB_EZI2C_STATE_TX_DATA == context->state) ? CY_SCB_EZI2C_STATUS_READ1 :
+ ((context->baseAddr1 != context->idx) ? CY_SCB_EZI2C_STATUS_WRITE1 : 0UL));
+ }
+ else
+ {
+ context->status |= ((CY_SCB_EZI2C_STATE_TX_DATA == context->state) ? CY_SCB_EZI2C_STATUS_READ2 :
+ ((context->baseAddr2 != context->idx) ? CY_SCB_EZI2C_STATUS_WRITE2 : 0UL));
+ }
+
+ /* Back to the idle state */
+ context->state = CY_SCB_EZI2C_STATE_IDLE;
+}
+
+
+/*******************************************************************************
+* Function Name: UpdateAddressMask
+****************************************************************************//**
+*
+* Updates the slave address mask to enable the SCB hardware to receive matching
+* slave addresses.
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated
+* by the user. The structure is used during the EZI2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void UpdateAddressMask(CySCB_Type *base, cy_stc_scb_ezi2c_context_t const *context)
+{
+ uint32_t addrMask;
+
+ /* Check how many addresses are used: */
+ if (0U != context->address2)
+ {
+ /* If (addr1 and addr2) bits match - mask bit equals 1; otherwise 0 */
+ addrMask = (uint32_t) ~((uint32_t) context->address1 ^ (uint32_t) context->address2);
+ }
+ else
+ {
+ addrMask = CY_SCB_EZI2C_ONE_ADDRESS_MASK;
+ }
+
+ /* Update the hardware address match */
+ base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_MASK, ((uint32_t) addrMask << 1UL));
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,570 @@
+/***************************************************************************//**
+* \file cy_scb_ezi2c.h
+* \version 2.10
+*
+* Provides EZI2C API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_ezi2c
+* \{
+* Driver API for EZI2C Slave Peripheral
+*
+* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
+* The two-wire hardware interface was developed by Philips Semiconductors
+* (now NXP Semiconductors).
+*
+* The EZI2C slave peripheral driver provides an API to implement the I2C slave
+* device based on the SCB hardware block. This slave device emulates a common
+* I2C EEPROM interface that acts like dual-port memory between the external
+* master and your code. I2C devices based on the SCB hardware are compatible
+* with the I2C Standard mode, Fast mode, and Fast mode Plus specifications, as
+* defined in the I2C bus specification.
+*
+* Features:
+* * An industry-standard I2C bus interface
+* * Supports standard data rates of 100/400/1000 kbps
+* * Emulates a common I2C EEPROM Interface
+* * Acts like dual-port memory between the external master and your code
+* * Supports Hardware Address Match
+* * Supports two hardware addresses with separate buffers
+* * Supports Wake from Deep Sleep on address match
+* * Simple to set up and use; does not require calling EZI2C API
+* at run time.
+*
+* \section group_scb_ezi2c_configuration Configuration Considerations
+* The EZI2C slave driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_ezi2c_config
+* * \ref group_scb_ezi2c_pins
+* * \ref group_scb_ezi2c_clock
+* * \ref group_scb_ezi2c_data_rate
+* * \ref group_scb_ezi2c_intr
+* * \ref group_scb_ezi2c_enable
+*
+* \note
+* EZI2C slave driver is built on top of the SCB hardware block. The SCB3
+* instance is used as an example for all code snippets. Modify the code to
+* match your design.
+*
+* \subsection group_scb_ezi2c_config Configure EZI2C slave
+* To set up the EZI2C slave driver, provide the configuration parameters in the
+* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
+* slaveAddress1 must be provided. The other parameters are optional for
+* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
+* function providing a pointer to the filled \ref cy_stc_scb_ezi2c_config_t
+* structure and allocated \ref cy_stc_scb_ezi2c_context_t.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG
+*
+* Set up the EZI2C slave buffer before enabling its
+* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
+* and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled).
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_BUFFER
+*
+* \subsection group_scb_ezi2c_pins Assign and Configure Pins
+* Only dedicated SCB pins can be used for I2C operation. The HSIOM
+* register must be configured to connect the block to the pins. Also the I2C pins
+* must be configured in Open-Drain, Drives Low mode (this pin configuration
+* implies usage of external pull-up resistors):
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_PINS
+*
+* \note
+* The alternative pins configuration is Resistive Pull-ups which implies usage
+* internal pull-up resistors. This configuration is not recommended because
+* resistor value is fixed and cannot be used for all supported data rates.
+* Refer to device datasheet parameter RPULLUP for resistor value specifications.
+*
+* \subsection group_scb_ezi2c_clock Assign Clock Divider
+* The clock source must be connected to the SCB block to oversample input and
+* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
+* source clock of this divider must be Clk_Peri)</b></em>. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_ASSIGN_CLOCK
+*
+* \subsection group_scb_ezi2c_data_rate Configure Data Rate
+* To get EZI2C slave to operate at the desired data rate, the source clock must be
+* fast enough to provide sufficient oversampling. Therefore, the clock divider
+* must be configured to provide desired clock frequency. Use the
+* \ref group_sysclk driver API to do that.
+* Refer to the technical reference manual (TRM) section I2C sub-section
+* Oversampling and Bit Rate to get information about how to configure the I2C to run
+* at the desired data rate.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_DATA_RATE
+*
+* \subsection group_scb_ezi2c_intr Configure Interrupt
+* The interrupt is mandatory for the EZI2C slave operation.
+* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
+* handler for the selected SCB instance. Also, this interrupt must be enabled
+* in the NVIC or it will not work.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_A
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_B
+*
+* \subsection group_scb_ezi2c_enable Enable EZI2C slave
+* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
+* Now the I2C device responds to the assigned address.
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_ENABLE
+*
+* \section group_scb_ezi2c_use_cases Common Use Cases
+* The EZI2C slave operation might not require calling any EZI2C slave function
+* because the I2C master is able to access the slave buffer. The application
+* can directly access it as well. Note that this is an application-level task
+* to ensure the buffer content integrity.
+*
+* \subsection group_scb_ezi2c_master_wr Master Write operation
+* This operation starts with sending a base address that is one
+* or two bytes, depending on the sub-address size configuration. This base
+* address is retained and will be used for later read operations. Following
+* the base address, there is a sequence of bytes written into the buffer
+* starting from the base address location. The buffer index is incremented
+* for each written byte, but this does not affect the base address that is
+* retained. The length of a write operation is limited by the maximum buffer
+* read/write region size.\n
+* When a master attempts to write outside the read/write region or past the
+* end of the buffer, the last byte is NACKed.
+*
+* \image html scb_ezi2c_write.png
+*
+* \subsection group_scb_ezi2c_master_rd Master Read operation
+* This operation always starts from the base address set by the most
+* recent write operation. The buffer index is incremented for each read byte.
+* Two sequential read operations start from the same base address no matter
+* how many bytes are read. The length of a read operation is not limited by
+* the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes
+* if the read operation passes the end of the buffer.\n
+* Typically, a read operation requires the base address to be updated before
+* starting the read. In this case, the write and read operations must be
+* combined together.
+*
+* \image html scb_ezi2c_read.png
+*
+* The I2C master may use the ReStart or Stop/Start conditions to combine the
+* operations. The write operation sets only the base address and the following
+* read operation will start from the new base address. In cases where the base
+* address remains the same, there is no need for a write operation.
+* \image html scb_ezi2c_set_ba_read.png
+*
+* \section group_scb_ezi2c_lp Low Power Support
+* The EZI2C slave provides the callback functions to handle power mode
+* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_DeepSleep;
+* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
+* \ref Cy_SysPm_Hibernate. To trigger the callback execution, the callback must
+* be registered before calling the power mode transition function. Refer to
+* \ref group_syspm driver for more information about power mode transitions and
+* callback registration.
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the EZI2C slave is configured to be a wakeup
+* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
+* be copied and modified. Refer to the function description to get the details.
+*
+* \section group_scb_ezi2c_more_information More Information
+*
+* For more information on the SCB peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_scb_ezi2c_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>The functions \ref Cy_SCB_EZI2C_DeepSleepCallback and
+* \ref Cy_SCB_EZI2C_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.</td>
+* </tr>
+* <tr>
+* <td>14.1</td>
+* <td>R</td>
+* <td>There shall be no unreachable code.</td>
+* <td>The SCB block parameters can be a constant false or true depending on
+* the selected device and cause code to be unreachable.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is done to improve
+* code clarity when returning error status code if input parameter
+* validation fails.</td>
+* </tr>
+* </table>
+*
+* \section group_scb_ezi2c_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td>None.</td>
+* <td>SCB I2C driver updated.</td>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.0</td>
+* <td>Added parameters validation for public API.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Replaced variables that have limited range of values with enumerated
+* types.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_scb_ezi2c_macros Macros
+* \defgroup group_scb_ezi2c_functions Functions
+* \{
+* \defgroup group_scb_ezi2c_general_functions General
+* \defgroup group_scb_ezi2c_slave_functions Slave
+* \defgroup group_scb_ezi2c_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_ezi2c_data_structures Data Structures
+* \defgroup group_scb_ezi2c_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_EZI2C_H)
+#define CY_SCB_EZI2C_H
+
+#include "cy_scb_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_enums
+* \{
+*/
+
+/** EZI2C slave status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_EZI2C_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_EZI2C_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_EZI2C_ID | 1U),
+} cy_en_scb_ezi2c_status_t;
+
+/** Number of Addresses */
+typedef enum
+{
+ CY_SCB_EZI2C_ONE_ADDRESS, /**< Only one address */
+ CY_SCB_EZI2C_TWO_ADDRESSES /**< Two addresses */
+} cy_en_scb_ezi2c_num_of_addr_t;
+
+/** Size of Sub-Address */
+typedef enum
+{
+ CY_SCB_EZI2C_SUB_ADDR8_BITS, /**< Sub-address is 8 bits */
+ CY_SCB_EZI2C_SUB_ADDR16_BITS /**< Sub-address is 16 bits */
+} cy_en_scb_ezi2c_sub_addr_size_t;
+
+/** \cond INTERNAL */
+/** EZI2C slave FSM states */
+typedef enum
+{
+ CY_SCB_EZI2C_STATE_IDLE,
+ CY_SCB_EZI2C_STATE_ADDR,
+ CY_SCB_EZI2C_STATE_RX_OFFSET_MSB,
+ CY_SCB_EZI2C_STATE_RX_OFFSET_LSB,
+ CY_SCB_EZI2C_STATE_RX_DATA0,
+ CY_SCB_EZI2C_STATE_RX_DATA1,
+ CY_SCB_EZI2C_STATE_TX_DATA
+} cy_en_scb_ezi2c_state_t;
+/** \endcond */
+/** \} group_scb_ezi2c_enums */
+
+
+/***************************************
+* Type Definitions
+***************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_data_structures
+* \{
+*/
+
+/** EZI2C slave configuration structure */
+typedef struct cy_stc_scb_ezi2c_config
+{
+ /** The number of supported addresses either */
+ cy_en_scb_ezi2c_num_of_addr_t numberOfAddresses;
+
+ /** The 7-bit right justified primary slave address */
+ uint8_t slaveAddress1;
+
+ /** The 7-bit right justified secondary slave address */
+ uint8_t slaveAddress2;
+
+ /** The size of the sub-address, can either be 8 or 16 bits */
+ cy_en_scb_ezi2c_sub_addr_size_t subAddressSize;
+
+ /**
+ * When set, the slave will wake the device from Deep Sleep on an address
+ * match (The device datasheet must be consulted to determine which SCBs
+ * support this mode)
+ */
+ bool enableWakeFromSleep;
+} cy_stc_scb_ezi2c_config_t;
+
+/** EZI2C slave context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_ezi2c_context
+{
+ /** \cond INTERNAL */
+ volatile cy_en_scb_ezi2c_state_t state; /**< The driver state */
+ volatile uint32_t status; /**< The slave status */
+
+ uint8_t address1; /**< The primary slave address (7-bits right justified) */
+ uint8_t address2; /**< The secondary slave address (7-bits right justified) */
+ cy_en_scb_ezi2c_sub_addr_size_t subAddrSize; /**< The sub-address size */
+
+ uint32_t idx; /**< The index within the buffer during operation */
+ uint32_t baseAddr1; /**< The valid base address for the primary slave address */
+ uint32_t baseAddr2; /**< The valid base address for the secondary slave address */
+
+ bool addr1Active; /**< Defines whether the request is intended for the primary slave address */
+ uint8_t *curBuf; /**< The pointer to the current location in the buffer (while it is accessed) */
+ uint32_t bufSize; /**< Specifies how many bytes are left in the current buffer */
+
+ uint8_t *buf1; /**< The pointer to the buffer exposed on the request intended for the primary slave address */
+ uint32_t buf1Size; /**< The buffer size assigned to the primary slave address */
+ uint32_t buf1rwBondary; /**< The Read/Write boundary within the buffer assigned to the primary slave address */
+
+ uint8_t *buf2; /**< The pointer to the buffer exposed on the request intended for the secondary slave address */
+ uint32_t buf2Size; /**< The buffer size assigned to the secondary slave address */
+ uint32_t buf2rwBondary; /**< The Read/Write boundary within the buffer assigned for the secondary slave address */
+ /** \endcond */
+} cy_stc_scb_ezi2c_context_t;
+/** \} group_scb_ezi2c_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_general_functions
+* \{
+*/
+cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config,
+ cy_stc_scb_ezi2c_context_t *context);
+void Cy_SCB_EZI2C_DeInit(CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base);
+void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+
+void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
+uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
+
+void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context);
+uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context);
+/** \} group_scb_ezi2c_general_functions */
+
+/**
+* \addtogroup group_scb_ezi2c_slave_functions
+* \{
+*/
+void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context);
+void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buffer, uint32_t size, uint32_t rwBoundary,
+ cy_stc_scb_ezi2c_context_t *context);
+
+uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context);
+
+void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context);
+/** \} group_scb_ezi2c_slave_functions */
+
+/**
+* \addtogroup group_scb_ezi2c_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_scb_ezi2c_low_power_functions */
+
+
+/***************************************
+* API Constants
+***************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_ezi2c_macros_get_activity EZI2C Activity Status
+* Each EZI2C slave status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+* \{
+*/
+
+/**
+* The Read transfer intended for the primary slave address is complete.
+* The error condition status bit must be checked to ensure that the Read
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_READ1 (0x01UL)
+
+/**
+* The Write transfer intended for the primary slave address is complete.
+* The buffer content was modified.
+* The error condition status bit must be checked to ensure that the Write
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL)
+
+/**
+* The Read transfer intended for the secondary slave address is complete.
+* The error condition status bit must be checked to ensure that the Read
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_READ2 (0x04UL)
+
+/**
+* The Write transfer intended for the secondary slave address is complete.
+* The buffer content was modified.
+* The error condition status bit must be checked to ensure that the Write
+* transfer was completed successfully.
+*/
+#define CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL)
+
+/**
+* A transfer intended for the primary address or secondary address is in
+* progress. The status bit is set after an address match and cleared
+* on a Stop or ReStart condition.
+*/
+#define CY_SCB_EZI2C_STATUS_BUSY (0x10UL)
+
+/**
+* An error occurred during a transfer intended for the primary or secondary
+* slave address. The sources of the error are: a misplaced Start or Stop
+* condition or lost arbitration while the slave drives SDA.
+* When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an
+* invalid byte. Discard the buffer content in this case.
+*/
+#define CY_SCB_EZI2C_STATUS_ERR (0x20UL)
+/** \} group_scb_ezi2c_macros_get_activity */
+
+/**
+* This value is returned by the slave when the buffer is not configured or
+* the master requests more bytes than are available in the buffer.
+*/
+#define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL)
+
+
+/***************************************
+* Internal Constants
+***************************************/
+
+/** \cond INTERNAL */
+/* Default registers values */
+#define CY_SCB_EZI2C_I2C_CTRL (SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk | SCB_I2C_CTRL_SLAVE_MODE_Msk)
+#define CY_SCB_EZI2C_RX_CTRL (CY_SCB_I2C_RX_CTRL)
+#define CY_SCB_EZI2C_TX_CTRL (CY_SCB_I2C_TX_CTRL)
+
+#define CY_SCB_EZI2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_STOP | \
+ CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+/* Error interrupt sources */
+#define CY_SCB_EZI2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+
+/* Disables Stop interrupt source */
+#define CY_SCB_EZI2C_SLAVE_INTR_NO_STOP (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP))
+
+/* Disable Address interrupt source */
+#define CY_SCB_EZI2C_SLAVE_INTR_NO_ADDR (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH))
+
+/* FIFO size */
+#define CY_SCB_EZI2C_FIFO_SIZE(base) CY_SCB_FIFO_SIZE(base)
+#define CY_SCB_EZI2C_HALF_FIFO_SIZE(base) (CY_SCB_FIFO_SIZE(base) / 2UL)
+
+#define CY_SCB_EZI2C_ONE_ADDRESS_MASK (0xFFUL)
+
+#define CY_SCB_EZI2C_IS_NUM_OF_ADDR_VALID(numAddr) ( (CY_SCB_EZI2C_ONE_ADDRESS == (numAddr)) || \
+ (CY_SCB_EZI2C_TWO_ADDRESSES == (numAddr)) )
+
+#define CY_SCB_EZI2C_IS_SUB_ADDR_SIZE_VALID(subAddrSize) ( (CY_SCB_EZI2C_SUB_ADDR8_BITS == (subAddrSize)) || \
+ (CY_SCB_EZI2C_SUB_ADDR16_BITS == (subAddrSize)) )
+/** \endcond */
+/** \} group_scb_ezi2c_macros */
+
+
+/***************************************
+* Inline Function Implementation
+***************************************/
+
+/**
+* \addtogroup group_scb_ezi2c_general_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_EZI2C_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the EZI2C operation
+*
+* \param base
+* The pointer to the EZI2C SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base)
+{
+ base->CTRL |= SCB_CTRL_ENABLED_Msk;
+}
+
+/** \} group_scb_ezi2c_general_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_ezi2c */
+
+#endif /* (CY_SCB_EZI2C_H) */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,3229 @@
+/***************************************************************************//**
+* \file cy_scb_i2c.c
+* \version 2.10
+*
+* Provides I2C API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_scb_i2c.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+static void SlaveHandleAddress (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void SlaveHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void SlaveHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+
+static void MasterHandleEvents (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void MasterHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void MasterHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+static void MasterHandleComplete (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+
+static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status,
+ cy_stc_scb_i2c_context_t *context);
+static uint32_t WaitOneUnit(uint32_t *timeout);
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_Init
+****************************************************************************//**
+*
+* Initializes the SCB for the I2C operation.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param config
+* The pointer to the configuration structure \ref cy_stc_scb_i2c_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config, cy_stc_scb_i2c_context_t *context)
+{
+ /* Input parameters verification */
+ if ((NULL == base) || (NULL == config) || (NULL == context))
+ {
+ return CY_SCB_I2C_BAD_PARAM;
+ }
+
+ CY_ASSERT_L3(CY_SCB_I2C_IS_MODE_VALID(config->i2cMode));
+
+ if ((config->i2cMode == CY_SCB_I2C_SLAVE) && (!SCB_IS_I2C_SLAVE_CAPABLE(base)))
+ {
+ return CY_SCB_I2C_BAD_PARAM;
+ }
+
+ if ((config->i2cMode == CY_SCB_I2C_MASTER) && (!SCB_IS_I2C_MASTER_CAPABLE(base)))
+ {
+ return CY_SCB_I2C_BAD_PARAM;
+ }
+
+ if ((config->i2cMode == CY_SCB_I2C_MASTER_SLAVE) &&
+ (!(SCB_IS_I2C_MASTER_CAPABLE(base) && SCB_IS_I2C_SLAVE_CAPABLE(base))))
+ {
+ return CY_SCB_I2C_BAD_PARAM;
+ }
+
+ if ((config->enableWakeFromSleep) && (!SCB_IS_I2C_DS_CAPABLE(base)))
+ {
+ return CY_SCB_I2C_BAD_PARAM;
+ }
+
+ CY_ASSERT_L2((config->useRxFifo) ? (!config->acceptAddrInFifo) : true);
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (config->slaveAddress));
+ CY_ASSERT_L2(CY_SCB_I2C_IS_ADDR_MASK_VALID(config->slaveAddressMask));
+
+ /* Configure the I2C interface */
+ base->CTRL = _BOOL2FLD(SCB_CTRL_ADDR_ACCEPT, config->acceptAddrInFifo) |
+ _BOOL2FLD(SCB_CTRL_EC_AM_MODE, config->enableWakeFromSleep) |
+ SCB_CTRL_BYTE_MODE_Msk;
+
+ base->I2C_CTRL = _BOOL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, !config->ackGeneralAddr) |
+ _VAL2FLD(CY_SCB_I2C_CTRL_MODE, (uint32_t) config->i2cMode);
+
+ /* Configure the RX direction */
+ base->RX_CTRL = CY_SCB_I2C_RX_CTRL;
+ base->RX_FIFO_CTRL = (config->useRxFifo ? (CY_SCB_I2C_FIFO_SIZE(base) - 1UL) : 0UL);
+
+ /* Set the default address and mask */
+ base->RX_MATCH = _VAL2FLD(SCB_RX_MATCH_ADDR, ((uint32_t) config->slaveAddress << 1UL)) |
+ _VAL2FLD(SCB_RX_MATCH_MASK, (uint32_t) config->slaveAddressMask);
+
+ /* Configure the TX direction */
+ base->TX_CTRL = CY_SCB_I2C_TX_CTRL;
+ base->TX_FIFO_CTRL = (config->useTxFifo ? CY_SCB_I2C_HALF_FIFO_SIZE(base) : 1UL);
+
+ /* Configure interrupt sources */
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+
+ base->INTR_S_MASK = (CY_SCB_I2C_MASTER != config->i2cMode) ? CY_SCB_I2C_SLAVE_INTR : 0UL;
+
+ /* Initialize the context */
+ context->useRxFifo = config->useRxFifo;
+ context->useTxFifo = config->useTxFifo;
+
+ context->state = CY_SCB_I2C_IDLE;
+
+ /* Master-specific */
+ context->masterStatus = 0UL;
+ context->masterBufferIdx = 0UL;
+
+ /* Slave-specific */
+ context->slaveStatus = 0UL;
+
+ context->slaveRxBufferIdx = 0UL;
+ context->slaveRxBufferSize = 0UL;
+
+ context->slaveTxBufferIdx = 0UL;
+ context->slaveTxBufferSize = 0UL;
+
+ /* Unregister callbacks */
+ context->cbEvents = NULL;
+ context->cbAddr = NULL;
+
+ return CY_SCB_I2C_SUCCESS;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_DeInit
+****************************************************************************//**
+*
+* De-initializes the SCB block and returns register values to default.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_DeInit(CySCB_Type *base)
+{
+ /* Returns block registers into the default state */
+ base->CTRL = CY_SCB_CTRL_DEF_VAL;
+ base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL;
+ base->I2C_CFG = CY_SCB_I2C_CFG_DEF_VAL;
+
+ base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL;
+ base->RX_FIFO_CTRL = 0UL;
+ base->RX_MATCH = 0UL;
+
+ base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL;
+ base->TX_FIFO_CTRL = 0UL;
+
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+ base->INTR_S_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_Disable
+****************************************************************************//**
+*
+* Disables the SCB block and clears context statuses.
+* Note that after the block is disabled, the TX and RX FIFOs and hardware
+* statuses are cleared. Also, the hardware stops driving the output and
+* ignores the input.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* Calling this function when I2C is busy (master preforms transaction or slave
+* was address and communicates with master) may cause transaction corruption
+* because the hardware stops driving the outputs and ignores the inputs.
+* Ensure that I2C is not busy before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ /* Set the state to default and clear statuses */
+ context->state = CY_SCB_I2C_IDLE;
+ context->masterStatus = 0UL;
+ context->slaveStatus = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the I2C SCB into and out of
+* Deep Sleep mode. It prevents the device from entering Deep Sleep
+* mode if the I2C slave or master is actively communicating.
+* The following behavior of the I2C SCB depends on whether the SCB block is
+* wakeup-capable or not:
+* * The SCB <b>wakeup-capable</b>: on the incoming I2C slave address, the slave
+* receives address and stretches the clock until the device is awoken from
+* Deep Sleep mode. If the slave address occurs before the device enters
+* Deep Sleep mode, the device will not enter Deep Sleep mode.
+* Only the I2C slave can be configured to be a wakeup source from Deep Sleep
+* mode.
+* * The SCB is <b>not wakeup-capable</b>: the I2C is disabled. It is enabled when
+* the device failed to enter Deep Sleep mode or when it is awoken from Deep
+* Sleep mode. While the I2C is disabled, it does stops driving the outputs and
+* ignores the inputs. The slave NACKs all incoming addresses.
+*
+* This function must be called during execution of \ref Cy_SysPm_DeepSleep.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the I2C slave is configured to be a wakeup source
+* from Deep Sleep mode, this function must be copied and modified by the user.
+* The I2C clock disable code must be inserted in the \ref CY_SYSPM_BEFORE_TRANSITION
+* and clock enable code in the \ref CY_SYSPM_AFTER_TRANSITION mode processing.
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_I2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_i2c_context_t *locContext = (cy_stc_scb_i2c_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Disable the slave interrupt sources to protect the state */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* If the I2C is in the IDLE state, it is ready for Deep Sleep mode
+ * (either the master or the slave is not busy),
+ * otherwise return fail and restore the slave interrupt sources.
+ */
+ if (CY_SCB_I2C_IDLE == locContext->state)
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: do not restore the address
+ * match and general call interrupt sources. The next
+ * transaction intended to the slave will be paused
+ * (SCL is stretched) before the address is ACKed because
+ * the corresponding interrupt source is disabled.
+ */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR_NO_ADDR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: disable the I2C. The slave
+ * stops responding to the master and the master stops
+ * driving the bus until the I2C is enabled. This happens
+ * when the device failed to enter into Deep Sleep mode or it
+ * is awaken from Deep Sleep mode.
+ */
+ Cy_SCB_I2C_Disable(locBase, locContext);
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ else
+ {
+ /* Restore the slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR);
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Deep Sleep mode. Restore
+ * Active mode configuration.
+ */
+
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: restore the slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: enable the I2C to operate */
+ Cy_SCB_I2C_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* This code executes inside the critical section. Enabling the
+ * active interrupt source makes the interrupt pending in the NVIC.
+ * However, the interrupt processing is delayed until the code exits
+ * the critical section. The pending interrupt force WFI instruction
+ * does nothing and the device remains in Active mode.
+ */
+
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: enable the I2C wakeup interrupt
+ * source. If any transaction was paused, the I2C interrupt
+ * becomes pending and prevents entering Deep Sleep mode.
+ * The transaction continues as soon as the global interrupts
+ * are enabled.
+ */
+ Cy_SCB_SetI2CInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
+
+ /* Disable SCB clock */
+ locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper entering Deep Sleep mode the I2C clock must be disabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* Enable SCB clock */
+ locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper exiting Deep Sleep, the I2C clock must be enabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+
+ /* The SCB is wakeup-capable: disable the I2C wakeup interrupt
+ * source and restore slave interrupt sources.
+ */
+ Cy_SCB_SetI2CInterruptMask (locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: enable the I2C to operate */
+ Cy_SCB_I2C_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the I2C SCB block into Hibernate
+* mode. It prevents the device from entering Hibernate mode if the I2C slave or
+* master is actively communicating.
+* If the I2C is ready to enter Hibernate mode, it is disabled. If the device failed
+* to enter Hibernate mode, the I2C is enabled. After the I2C is disabled, it stops
+* driving the outputs and ignores the inputs. The slave NACKs all incoming
+* addresses.
+*
+* This function must be called during execution of \ref Cy_SysPm_Hibernate.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_i2c_context_t *locContext = (cy_stc_scb_i2c_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Disable the slave interrupt sources to protect the state */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* If the I2C is in the IDLE state, it is ready for Hibernate mode
+ * (either the master or the slave is not busy).
+ * Otherwise, return fail and restore the slave interrupt sources.
+ */
+ if (CY_SCB_I2C_IDLE == locContext->state)
+ {
+ /* Disable the I2C. The slave stops responding to the master and
+ * the master stops driving the bus until the I2C is enabled.
+ * This happens if the device failed to enter Hibernate mode.
+ */
+ Cy_SCB_I2C_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+
+ /* Restore the slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(locBase, CY_SCB_I2C_SLAVE_INTR);
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Hibernate mode. Restore the
+ * Active mode configuration.
+ */
+
+ /* Enable the I2C to operate */
+ Cy_SCB_I2C_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* The SCB is not capable of waking up from Hibernate mode: do nothing */
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SetDataRate
+****************************************************************************//**
+*
+* Configures the SCB to work at the desired data rate.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param dataRateHz
+* The desired data Rate in Hz.
+*
+* \param scbClockHz
+* The frequency of the clock connected to the SCB in Hz.
+*
+* \return
+* The achieved data rate in Hz.
+*
+* \note
+* This function does not change the values of the clock divider connected
+* to the SCB, it changes only the SCB clock oversample registers. If this
+* function is not able to achieve the desired data rate, then the clock
+* divider must be adjusted. Call this function only while the SCB is
+* disabled. For the slave, this function only checks that the attached clock is
+* fast enough to meet the desired data rate. It does not change any registers.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t scbClockHz)
+{
+ CY_ASSERT_L2(scbClockHz > 0UL);
+ CY_ASSERT_L2(CY_SCB_I2C_IS_DATA_RATE_VALID(dataRateHz));
+
+ uint32_t actualDataRate = 0UL;
+
+ if (((uint32_t) CY_SCB_I2C_SLAVE) == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL))
+ {
+ actualDataRate = Cy_SCB_I2C_GetDataRate(base, scbClockHz);
+
+ /* Use an analog filter for the slave */
+ base->RX_CTRL &= (uint32_t) ~SCB_RX_CTRL_MEDIAN_Msk;
+ base->I2C_CFG = CY_SCB_I2C_ENABLE_ANALOG_FITLER;
+ }
+ else
+ {
+ if ((scbClockHz > 0U) && (dataRateHz > 0U))
+ {
+ uint32_t sclLow;
+ uint32_t sclHigh;
+ uint32_t lowPhase;
+ uint32_t highPhase;
+
+ /* Convert SCB clock and data rate in kHz */
+ uint32_t scbClockKHz = scbClockHz / 1000UL;
+ uint32_t dataRateKHz = dataRateHz / 1000UL;
+
+ /* Get period of the SCB clock in ns */
+ uint32_t period = 1000000000UL / scbClockHz;
+
+ /* Get duration of SCL low and high for the selected data rate */
+ if (dataRateHz <= CY_SCB_I2C_STD_DATA_RATE)
+ {
+ sclLow = CY_SCB_I2C_MASTER_STD_SCL_LOW;
+ sclHigh = CY_SCB_I2C_MASTER_STD_SCL_HIGH;
+ }
+ else if (dataRateHz <= CY_SCB_I2C_FST_DATA_RATE)
+ {
+ sclLow = CY_SCB_I2C_MASTER_FST_SCL_LOW;
+ sclHigh = CY_SCB_I2C_MASTER_FST_SCL_HIGH;
+ }
+ else
+ {
+ sclLow = CY_SCB_I2C_MASTER_FSTP_SCL_LOW;
+ sclHigh = CY_SCB_I2C_MASTER_FSTP_SCL_HIGH;
+ }
+
+ /* Get low phase minimum value in SCB clocks */
+ lowPhase = sclLow / period;
+ while (((period * lowPhase) < sclLow) && (lowPhase < CY_SCB_I2C_LOW_PHASE_MAX))
+ {
+ ++lowPhase;
+ }
+
+ /* Get high phase minimum value in SCB clocks */
+ highPhase = sclHigh / period;
+ while (((period * highPhase) < sclHigh) && (highPhase < CY_SCB_I2C_HIGH_PHASE_MAX))
+ {
+ ++highPhase;
+ }
+
+ /* Get actual data rate */
+ actualDataRate = scbClockKHz / (lowPhase + highPhase);
+
+ uint32_t idx = 0UL;
+ while ((actualDataRate > dataRateKHz) &&
+ ((lowPhase + highPhase) < CY_SCB_I2C_DUTY_CYCLE_MAX))
+ {
+ /* Increase low and high phase to reach desired data rate */
+ if (0UL != (idx & 0x1UL))
+ {
+ if (highPhase < CY_SCB_I2C_HIGH_PHASE_MAX)
+ {
+ highPhase++;
+ }
+ }
+ else
+ {
+ if (lowPhase < CY_SCB_I2C_LOW_PHASE_MAX)
+ {
+ lowPhase++;
+ }
+ }
+
+ idx++;
+
+ /* Update actual data rate */
+ actualDataRate = scbClockKHz / (lowPhase + highPhase);
+ }
+
+ /* Set filter configuration based on actual data rate */
+ if (actualDataRate > CY_SCB_I2C_FST_DATA_RATE)
+ {
+ /* Use a digital filter */
+ base->RX_CTRL |= (uint32_t) SCB_RX_CTRL_MEDIAN_Msk;
+ base->I2C_CFG = CY_SCB_I2C_DISABLE_ANALOG_FITLER;
+ }
+ else
+ {
+ /* Use an analog filter */
+ base->RX_CTRL &= (uint32_t) ~SCB_RX_CTRL_MEDIAN_Msk;
+ base->I2C_CFG = CY_SCB_I2C_ENABLE_ANALOG_FITLER;
+ }
+
+ /* Set phase low and high */
+ Cy_SCB_I2C_MasterSetLowPhaseDutyCycle (base, lowPhase);
+ Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(base, highPhase);
+
+ /* Convert actual data rate in Hz */
+ actualDataRate = scbClockHz / (lowPhase + highPhase);
+ }
+ }
+
+ return (actualDataRate);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_GetDataRate
+****************************************************************************//**
+*
+* Returns the data rate for the selected SCB block.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param scbClockHz
+* The frequency of the clock connected to the SCB in Hz.
+*
+* \return
+* The data rate in Hz.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_GetDataRate(CySCB_Type const *base, uint32_t scbClockHz)
+{
+ CY_ASSERT_L2(scbClockHz > 0UL);
+
+ uint32_t actualDataRate = 0UL;
+
+ if (((uint32_t) CY_SCB_I2C_SLAVE) == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL))
+ {
+ /* Check the clock frequency range to get maximum supported data rate */
+ if ((scbClockHz >= CY_SCB_I2C_SLAVE_FST_CLK_MIN) && (scbClockHz <= CY_SCB_I2C_SLAVE_FST_CLK_MAX))
+ {
+ actualDataRate = CY_SCB_I2C_FST_DATA_RATE;
+ }
+ else if ((scbClockHz >= CY_SCB_I2C_SLAVE_STD_CLK_MIN) && (scbClockHz <= CY_SCB_I2C_SLAVE_STD_CLK_MAX))
+ {
+ actualDataRate = CY_SCB_I2C_STD_DATA_RATE;
+ }
+ else if ((scbClockHz >= CY_SCB_I2C_SLAVE_FSTP_CLK_MIN) && (scbClockHz <= CY_SCB_I2C_SLAVE_FSTP_CLK_MAX))
+ {
+ actualDataRate = CY_SCB_I2C_FSTP_DATA_RATE;
+ }
+ else
+ {
+ /* The clock frequency is too low or it gets to the gap between
+ * Fast and Fast Plus data rates.
+ */
+ actualDataRate = 0UL;
+ }
+ }
+ else
+ {
+ if (scbClockHz > 0U)
+ {
+ uint32_t dutyCycle;
+
+ /* Get number of clocks in one SCL period */
+ dutyCycle = _FLD2VAL(SCB_I2C_CTRL_LOW_PHASE_OVS, base->I2C_CTRL) +
+ _FLD2VAL(SCB_I2C_CTRL_HIGH_PHASE_OVS, base->I2C_CTRL) +
+ 2UL;
+
+ /* Calculate the actual data rate */
+ actualDataRate = (scbClockHz / dutyCycle);
+ }
+ }
+
+ return (actualDataRate);
+}
+
+
+/*******************************************************************************
+* I2C Slave API
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveGetStatus
+****************************************************************************//**
+*
+* Returns the current I2C slave status.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_i2c_macros_slave_status.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SlaveGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->slaveStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveConfigReadBuf
+****************************************************************************//**
+*
+* Configures the buffer pointer and the read buffer size. This is the buffer
+* from which the master reads data. After this function is called, data
+* transfer from the read buffer to the master is handled by
+* \ref Cy_SCB_I2C_Interrupt.
+*
+* When the Read transaction is completed (master generated Stop, ReStart or
+* error occurred), the \ref CY_SCB_I2C_SLAVE_RD_BUSY status is cleared and
+* the \ref CY_SCB_I2C_SLAVE_RD_CMPLT is set. Also
+* the \ref CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT event is generated.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param buffer
+* The pointer to the buffer with data to be read by the master.
+*
+* \param size
+* Size of the buffer.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The Read buffer must not be modified and stay allocated until it has been
+* read by the master.
+* * If this function has not been called, and the master tries to read data
+* from the slave a \ref CY_SCB_I2C_DEFAULT_TX is returned to the master.
+* * If the master tries to read more bytes than available in the Read buffer,
+* a \ref CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT event occurs. The
+* \ref CY_SCB_I2C_DEFAULT_TX is returned to the master if the buffer remains
+* empty after an event notification.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_SlaveConfigReadBuf(CySCB_Type const *base, uint8_t *buffer, uint32_t size,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L1(CY_SCB_IS_I2C_BUFFER_VALID(buffer, size));
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->slaveTxBuffer = buffer;
+ context->slaveTxBufferSize = size;
+ context->slaveTxBufferIdx = 0UL;
+ context->slaveTxBufferCnt = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveAbortRead
+****************************************************************************//**
+*
+* Aborts the configured slave read buffer to be read by the master.
+* If the master reads and "abort operation" is requested, the
+* \ref CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT event occurs. The
+* \ref CY_SCB_I2C_DEFAULT_TX is returned to the master if the buffer remains
+* empty after the event notification.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \sideeffect
+* If the TX FIFO is used, this function clears it.
+* The TX FIFO clear operation also clears the shift register, thus
+* the shifter can be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as "ones" on the bus.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_SlaveAbortRead(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t intrState;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ /* Reset index to make write buffer empty */
+ context->slaveTxBufferSize = 0UL;
+
+ if ((context->useTxFifo) &&
+ (0UL != (CY_SCB_I2C_SLAVE_RD_BUSY & context->slaveStatus)))
+ {
+ /* Clear TX FIFO from available data */
+ Cy_SCB_ClearTxFifo(base);
+ }
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveGetReadTransferCount
+****************************************************************************//**
+*
+* Returns the number of bytes read by the master since the last time
+* \ref Cy_SCB_I2C_SlaveConfigReadBuf is called.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of bytes read by the master.
+*
+* \note
+* * This function returns an invalid value if a read transaction was
+* aborted or any listed event occurs during the transaction:
+* \ref CY_SCB_I2C_SLAVE_ARB_LOST, \ref CY_SCB_I2C_SLAVE_BUS_ERR.
+* * This number is updated only when a transaction completes, either through
+* an error or successfully.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SlaveGetReadTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->slaveTxBufferCnt);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveClearReadStatus
+****************************************************************************//**
+*
+* Clears the read status and error conditions flags and returns their values.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_i2c_macros_slave_status.
+*
+* \note
+* The \ref CY_SCB_I2C_SLAVE_RD_BUSY flag is not cleared.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SlaveClearReadStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t retStatus;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ retStatus = (context->slaveStatus & CY_SCB_I2C_SLAVE_RD_CLEAR);
+ context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_RD_CLEAR;
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveConfigWriteBuf
+****************************************************************************//**
+*
+* Configures the buffer pointer and size of the write buffer. This is the buffer
+* that the master writes data to. After this function is called data transfer
+* from the master into the write buffer is handled by \ref Cy_SCB_I2C_Interrupt.
+*
+* When write transaction is completed (master generated Stop, ReStart or
+* error occurred) the \ref CY_SCB_I2C_SLAVE_WR_BUSY status is cleared and
+* the \ref CY_SCB_I2C_SLAVE_WR_CMPLT is set, also
+* the \ref CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT event is generated.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param buffer
+* The pointer to buffer to store data written by the master.
+*
+* \param size
+* Size of the buffer.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The write buffer must not be modified and must stay allocated until it has been
+* written by the master.
+* * If this function has not been called and the master tries to write data,
+* the first byte is NAKed and discarded.
+* * If the master writes more bytes than the slave can store in the write buffer,
+* the \ref CY_SCB_I2C_SLAVE_WR_OVRFL status is set and the slave will NACK last
+* byte, unless the RX FIFO is used. Then the slave will NAK only after
+* RX FIFO becomes full.
+* * If the RX FIFO is used, the minimum write buffer size is automatically
+* the size of the RX FIFO. If a write buffer is less than the RX FIFO size, extra
+* bytes are ACKed and stored into RX FIFO but ignored by firmware.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_SlaveConfigWriteBuf(CySCB_Type const *base, uint8_t *buffer, uint32_t size,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L1(CY_SCB_IS_I2C_BUFFER_VALID(buffer, size));
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->slaveRxBuffer = buffer;
+ context->slaveRxBufferSize = size;
+ context->slaveRxBufferIdx = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveAbortWrite
+****************************************************************************//**
+*
+* Aborts the configured slave write buffer to be written by the master.
+* If master writes and "abort operation" are requested, the next incoming byte will
+* be NAKed.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* If the RX FIFO is used, the NAK will not be sent until RX FIFO
+* becomes full, however bytes accepted after an abort request are ignored.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_SlaveAbortWrite(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t intrState;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ /* Reset index to make read buffer empty */
+ context->slaveRxBufferSize = 0UL;
+
+ if ((context->useRxFifo) &&
+ (0UL != (CY_SCB_I2C_SLAVE_WR_BUSY & context->slaveStatus)))
+ {
+ /* Configure to NACK when RX FIFO is full and disable RX level
+ * interrupt sources to stop getting data from RX FIFO.
+ */
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk;
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveGetWriteTransferCount
+****************************************************************************//**
+*
+* Returns the number of bytes written by the master since the last time
+* \ref Cy_SCB_I2C_SlaveConfigWriteBuf is called.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* Number of bytes written by the master.
+*
+* \note
+* * This function returns an invalid value if write transaction is
+* aborted or any listed event occurs during the transaction:
+* \ref CY_SCB_I2C_SLAVE_ARB_LOST, \ref CY_SCB_I2C_SLAVE_BUS_ERR.
+* * This number is updated only when the transaction completes, either through
+* an error or successfully.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SlaveGetWriteTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->slaveRxBufferIdx);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveClearWriteStatus
+****************************************************************************//**
+*
+* Clears the write status flags and error condition flags and returns their
+* values.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_i2c_macros_slave_status.
+*
+* \note
+* The \ref CY_SCB_I2C_SLAVE_WR_BUSY flag is not cleared.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_SlaveClearWriteStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t retStatus;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ retStatus = (context->slaveStatus & CY_SCB_I2C_SLAVE_WR_CLEAR);
+ context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_WR_CLEAR;
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* I2C Master API: High level
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterGetStatus
+****************************************************************************//**
+*
+* Returns the current I2C master status.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_i2c_macros_master_status.
+* Note that not all I2C master statuses are returned by this function. Refer to
+* more details of each status.
+*
+* \note
+* Status is cleared by calling \ref Cy_SCB_I2C_MasterRead or
+* \ref Cy_SCB_I2C_MasterWrite.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_MasterGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->masterStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterRead
+****************************************************************************//**
+*
+* This function configures the master to automatically read an entire buffer
+* of data from the slave device. After the transaction is initiated by this
+* function it returns and \ref Cy_SCB_I2C_Interrupt manages further data
+* transfer.
+*
+* When a read transaction is completed (requested number of bytes are read or
+* error occurred) the \ref CY_SCB_I2C_MASTER_BUSY status is cleared and
+* the \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT event is generated.
+*
+* Note that the master must read at least one byte.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param xferConfig
+* Master transfer configuration structure
+* \ref cy_stc_scb_i2c_master_xfer_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* * The buffer must not be modified and must stay allocated until read operation
+* completion.
+*
+* * \ref Cy_SCB_I2C_MasterRead requests the SCB hardware to generate a Start
+* Condition. The hardware will not generate the Start while the I2C bus is busy.
+* The SCB hardware sets the busy status after the Start detection, and clears
+* it on the Stop detection. Noise caused by the ESD or other events may cause
+* an erroneous Start condition on the bus. Then, the master will never generate
+* a Start condition because the hardware assumes the bus is busy. If this occurs,
+* the \ref Cy_SCB_I2C_MasterGetStatus returns \ref CY_SCB_I2C_MASTER_BUSY
+* status and the transaction will never finish. The option is to implement a
+* timeout to detect the transfer completion. If the transfer never completes,
+* the SCB needs a reset by calling the \ref Cy_SCB_I2C_Disable and
+* \ref Cy_SCB_I2C_Enable functions. The \ref Cy_SCB_I2C_MasterAbortRead
+* function will not work, the block must be reset.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead(CySCB_Type *base,
+ cy_stc_scb_i2c_master_xfer_config_t *xferConfig,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L1(xferConfig != NULL);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID (xferConfig->buffer, xferConfig->bufferSize));
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(xferConfig->slaveAddress));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ /* Disable I2C slave interrupt sources to protect state */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (0UL != (CY_SCB_I2C_IDLE_MASK & context->state))
+ {
+ uint32_t intrState;
+
+ /* Set address byte (bit0 = 1, read direction) */
+ uint32_t address = _VAL2FLD(CY_SCB_I2C_ADDRESS, xferConfig->slaveAddress) |
+ (uint32_t) CY_SCB_I2C_READ_XFER;
+
+ /* Setup context */
+ context->masterStatus = CY_SCB_I2C_MASTER_BUSY;
+
+ context->masterBuffer = xferConfig->buffer;
+ context->masterBufferSize = xferConfig->bufferSize;
+ context->masterBufferIdx = 0UL;
+ context->masterNumBytes = 0UL;
+ context->masterPause = xferConfig->xferPending;
+ context->masterRdDir = true;
+
+ /* Clean-up hardware before transfer. Note RX FIFO is empty at here. */
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ Cy_SCB_ClearTxFifo(base);
+
+ if (CY_SCB_I2C_IDLE == context->state)
+ {
+ /* Put the address in the TX FIFO, then generate a Start condition.
+ * This sequence ensures that after the Start condition generation
+ * the address is available to be sent onto the bus.
+ */
+ Cy_SCB_WriteTxFifo(base, address);
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk;
+ }
+ else
+ {
+ /* Generate a ReStart condition.
+ * If the previous transfer was read, NACK is generated before
+ * ReStart to complete the previous transfer.
+ */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_START_Msk | (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ?
+ SCB_I2C_M_CMD_M_NACK_Msk : 0UL));
+
+ /* Put address in TX FIFO */
+ Cy_SCB_WriteTxFifo(base, address);
+ }
+
+ /* Configure interrupt for data reception */
+ if ((context->useRxFifo) && (!context->masterPause) && (context->masterBufferSize >= 2UL))
+ {
+ uint32_t fifoSize = CY_SCB_I2C_FIFO_SIZE(base);
+
+ /* Enable Auto data ACK */
+ base->I2C_CTRL |= SCB_I2C_CTRL_M_READY_DATA_ACK_Msk;
+
+ /* Adjust level in RX FIFO */
+ Cy_SCB_SetRxFifoLevel(base, (context->masterBufferSize <= fifoSize) ?
+ (context->masterBufferSize - 2UL) : ((fifoSize / 2UL) - 1UL));
+
+ context->state = CY_SCB_I2C_MASTER_RX1;
+ }
+ else
+ {
+ /* Adjust level in RX FIFO */
+ Cy_SCB_SetRxFifoLevel(base, 0UL);
+
+ context->state = CY_SCB_I2C_MASTER_RX0;
+ }
+
+ /* Enable interrupt sources to continue transfer.
+ * Requires critical section to not cause race condition between RX and Master
+ * interrupt sources.
+ */
+ intrState = Cy_SysLib_EnterCriticalSection();
+ Cy_SCB_SetRxInterruptMask (base, CY_SCB_RX_INTR_LEVEL);
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR);
+ Cy_SysLib_ExitCriticalSection(intrState);
+
+ retStatus = CY_SCB_I2C_SUCCESS;
+ }
+
+ /* Enable I2C slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR);
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterAbortRead
+****************************************************************************//**
+*
+* This function requests master to abort read operation by NAKing the next byte
+* and generating a Stop condition. The function does not wait until these
+* actions are completed. Therefore the next read operation can be initiated only
+* after the \ref CY_SCB_I2C_MASTER_BUSY is cleared.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+******************************************************************************/
+void Cy_SCB_I2C_MasterAbortRead(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t intrState;
+
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ if (0UL != (CY_SCB_I2C_MASTER_BUSY & context->masterStatus))
+ {
+ /* Catch state to abort read operation */
+ if ((CY_SCB_I2C_MASTER_RX0 == context->state) || (CY_SCB_I2C_MASTER_RX1 == context->state))
+ {
+ if (context->useRxFifo)
+ {
+ /* Disable RX processing */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* Change state to request Stop generation */
+ context->state = CY_SCB_I2C_MASTER_STOP;
+
+ /* Enable ACK interrupt source to generate Stop after Start was generated */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ }
+ else
+ {
+ /* Reduce buffer size to minimum */
+ context->masterBufferSize = 1UL;
+ }
+
+ /* Cancel pending read operation if it was requested */
+ context->masterPause = false;
+ }
+ }
+ else
+ {
+ /* There are two possible states when master is not busy:
+ * CY_SCB_I2C_MASTER_WAIT and CY_SCB_I2C_IDLE.
+ * Do nothing for CY_SCB_I2C_IDLE.
+ */
+ if (CY_SCB_I2C_MASTER_WAIT == context->state)
+ {
+ /* Clear master previous transaction results:
+ * - status to indicate that master is busy;
+ * - number of bytes (only Stop is generated);
+ * - cancel previous pending operation.
+ */
+ context->masterStatus = CY_SCB_I2C_MASTER_BUSY;
+ context->masterNumBytes = 0UL;
+ context->masterPause = false;
+
+ /* Enable master interrupt sources to catch Stop condition */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR);
+
+ /* Complete transaction generating Stop */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk);
+ context->state = CY_SCB_I2C_MASTER_WAIT_STOP;
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterWrite
+****************************************************************************//**
+*
+* This function configures the master to automatically write an entire buffer
+* of data to a slave device. After the transaction is initiated by this
+* function it returns and \ref Cy_SCB_I2C_Interrupt manages further data
+* transfer.
+*
+* When a write transaction is completed (requested number of bytes are written
+* or error occurred) the \ref CY_SCB_I2C_MASTER_BUSY status is cleared and
+* the \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT event is generated.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param xferConfig
+* Master transfer configuration structure
+* \ref cy_stc_scb_i2c_master_xfer_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* * The buffer must not be modified and must stay allocated until data has been
+* copied into TX FIFO.
+*
+* * \ref Cy_SCB_I2C_MasterWrite requests the SCB hardware to generate a Start
+* Condition. The hardware will not generate the Start while the I2C bus is busy.
+* The SCB hardware sets the busy status after the Start detection, and clears
+* it on the Stop detection. Noise caused by the ESD or other events may cause
+* an erroneous Start condition on the bus. Then, the master will never generate
+* a Start condition because the hardware assumes the bus is busy. If this occurs,
+* the \ref Cy_SCB_I2C_MasterGetStatus returns \ref CY_SCB_I2C_MASTER_BUSY
+* status and the transaction will never finish. The option is to implement a
+* timeout to detect the transfer completion. If the transfer never completes,
+* the SCB needs a reset by calling the \ref Cy_SCB_I2C_Disable and
+* \ref Cy_SCB_I2C_Enable functions. The \ref Cy_SCB_I2C_MasterAbortWrite
+* function will not work, the block must be reset.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base,
+ cy_stc_scb_i2c_master_xfer_config_t *xferConfig,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L1(xferConfig != NULL);
+ CY_ASSERT_L1(CY_SCB_IS_I2C_BUFFER_VALID(xferConfig->buffer, xferConfig->bufferSize));
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (xferConfig->slaveAddress));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ /* Disable I2C slave interrupt sources to protect state */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (0UL != (CY_SCB_I2C_IDLE_MASK & context->state))
+ {
+ uint32_t intrState;
+
+ /* Set address byte (bit0 = 0, write direction) */
+ uint32_t address = _VAL2FLD(CY_SCB_I2C_ADDRESS, xferConfig->slaveAddress);
+
+ /* Setup context */
+ context->masterStatus = CY_SCB_I2C_MASTER_BUSY;
+
+ context->masterBuffer = xferConfig->buffer;
+ context->masterBufferSize = xferConfig->bufferSize;
+ context->masterBufferIdx = 0UL;
+ context->masterNumBytes = 0UL;
+ context->masterPause = xferConfig->xferPending;
+ context->masterRdDir = false;
+
+ /* Clean-up hardware before transfer. Note RX FIFO is empty at here. */
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ Cy_SCB_ClearTxFifo(base);
+
+ if (CY_SCB_I2C_IDLE == context->state)
+ {
+ /* Put the address in the TX FIFO, then generate a Start condition.
+ * This sequence ensures that after the Start condition generation
+ * the address is available to be sent onto the bus.
+ */
+ Cy_SCB_WriteTxFifo (base, address);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk;
+ }
+ else
+ {
+ /* Generate a ReStart condition.
+ * If the previous transfer was read, NACK is generated before
+ * ReStart to complete the previous transfer.
+ */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_START_Msk | (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ?
+ SCB_I2C_M_CMD_M_NACK_Msk : 0UL));
+
+ if (0U == context->masterBufferSize)
+ {
+ /* The address is the last byte to transfer.
+ * Put the address byte in the TX FIFO and clear the TX
+ * Underflow interrupt source inside the critical section
+ * to ensure that the TX Underflow interrupt will trigger
+ * after the address byte is sent onto the bus.
+ */
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ /* Put address in TX FIFO */
+ Cy_SCB_WriteTxFifo (base, address);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+ }
+ else
+ {
+ /* Put address in TX FIFO */
+ Cy_SCB_WriteTxFifo(base, address);
+ }
+ }
+
+ context->state = CY_SCB_I2C_MASTER_TX;
+
+ /* TX FIFO is empty. Set level to start transfer */
+ Cy_SCB_SetTxFifoLevel(base, (context->useTxFifo) ? CY_SCB_I2C_HALF_FIFO_SIZE(base) : (1UL));
+
+ /* Enable interrupt sources to continue transfer.
+ * Requires critical section to not cause race condition between TX and Master
+ * interrupt sources.
+ */
+ intrState = Cy_SysLib_EnterCriticalSection();
+ Cy_SCB_SetTxInterruptMask (base, CY_SCB_TX_INTR_LEVEL);
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR);
+ Cy_SysLib_ExitCriticalSection(intrState);
+
+ retStatus = CY_SCB_I2C_SUCCESS;
+ }
+
+ /* Enable I2C slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR);
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterAbortWrite
+****************************************************************************//**
+*
+* This function requests the master to abort write operation by generating a Stop
+* condition. The function does not wait until this action is completed.
+* Therefore next write operation can be initiated only after the
+* \ref CY_SCB_I2C_MASTER_BUSY is cleared.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \sideeffect
+* If the TX FIFO is used, it is cleared before Stop generation.
+* The TX FIFO clear operation also clears shift register. Thus the shifter
+* could be cleared in the middle of a data element transfer, corrupting it.
+* The remaining bits to transfer within corrupted data element are
+* complemented with ones.\n
+* If the clear operation is requested while the master transmits the address,
+* the direction of transaction is changed to read and one byte is read
+* before Stop is issued. This byte is discarded.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_MasterAbortWrite(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t intrState;
+
+ intrState = Cy_SysLib_EnterCriticalSection();
+
+ if (0UL != (CY_SCB_I2C_MASTER_BUSY & context->masterStatus))
+ {
+ /* Disable TX processing */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (context->useTxFifo)
+ {
+ /* Clear TX FIFO to allow Stop generation */
+ Cy_SCB_ClearTxFifo(base);
+ }
+
+ if ((CY_SCB_I2C_MASTER_TX == context->state) || (CY_SCB_I2C_MASTER_TX_DONE == context->state))
+ {
+ /* Change state to request Stop generation */
+ context->state = CY_SCB_I2C_MASTER_STOP;
+
+ /* Enable ACK interrupt source to trigger Stop generation */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ }
+
+ /* Cancel pending write operation if it was requested */
+ context->masterPause = false;
+ }
+ else
+ {
+ /* There are two possible states when master is not busy:
+ * CY_SCB_I2C_MASTER_WAIT and CY_SCB_I2C_IDLE.
+ * Do nothing for CY_SCB_I2C_IDLE.
+ */
+ if (CY_SCB_I2C_MASTER_WAIT == context->state)
+ {
+ /* Clear master previous transaction results:
+ * - status to indicate that master is busy;
+ * - number of bytes (only Stop is generated);
+ * - cancel previous pending operation.
+ */
+ context->masterStatus = CY_SCB_I2C_MASTER_BUSY;
+ context->masterNumBytes = 0UL;
+ context->masterPause = false;
+
+ /* Enable master interrupt sources to catch Stop condition */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR);
+
+ /* Complete transaction generating Stop */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk);
+ context->state = CY_SCB_I2C_MASTER_WAIT_STOP;
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(intrState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterGetTransferCount
+****************************************************************************//**
+*
+* Returns the number of bytes transferred since the last call of
+* \ref Cy_SCB_I2C_MasterWrite or \ref Cy_SCB_I2C_MasterRead function.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* Number of bytes read or written by the master.
+*
+* \note
+* * This function returns an invalid value if read or write transaction was
+* aborted or any listed event occurs during the transaction:
+* \ref CY_SCB_I2C_MASTER_ARB_LOST, \ref CY_SCB_I2C_MASTER_BUS_ERR or
+* \ref CY_SCB_I2C_MASTER_ABORT_START.
+*
+* * This number is updated only when the transaction completes, either through
+* an error or successfully.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_I2C_MasterGetTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->masterNumBytes);
+}
+
+
+/*******************************************************************************
+* I2C Master API: Low level
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterSendStart
+****************************************************************************//**
+*
+* Generates a Start condition and sends a slave address with the Read/Write bit.
+* This function is blocking. It does not return until the Start condition
+* and address byte are sent and a ACK/NAK is received, or an error or timeout
+* occurs.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param address
+* 7 bit right justified slave address.
+*
+* \param bitRnW
+* This sets the value of the Read/Write bit in the address, thus defining
+* the direction of the following transfer.
+* See \ref cy_en_scb_i2c_direction_t for the set of constants.
+*
+* \param timeoutMs
+* Defines in milliseconds the time for which this function can block.
+* If that time expires, the function returns. If a zero is passed,
+* the function waits forever for the action to complete. If a timeout occurs,
+* the SCB block is reset. Note The maximum value is UINT32_MAX/1000.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* After a read transaction is initiated and the slave ACKs the address, at
+* least one byte must be read before completing the transaction or changing
+* its direction.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStart(CySCB_Type *base,
+ uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
+ uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (address));
+ CY_ASSERT_L2(CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs));
+ CY_ASSERT_L3(CY_SCB_I2C_IS_RW_BIT_VALID (bitRnW));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ /* Disable the I2C slave interrupt sources to protect the state */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (CY_SCB_I2C_IDLE == context->state)
+ {
+ uint32_t locStatus;
+ uint32_t timeout = CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs);
+
+ /* Set the read or write direction */
+ context->state = CY_SCB_I2C_MASTER_ADDR;
+ context->masterRdDir = (CY_SCB_I2C_READ_XFER == bitRnW);
+
+ /* Clean up the hardware before a transfer. Note RX FIFO is empty at here */
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ Cy_SCB_ClearRxInterrupt (base, CY_SCB_RX_INTR_NOT_EMPTY);
+ Cy_SCB_ClearTxFifo(base);
+
+ /* Generate a Start and send address byte */
+ Cy_SCB_WriteTxFifo(base, (_VAL2FLD(CY_SCB_I2C_ADDRESS, address) | (uint32_t) bitRnW));
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk;
+
+ /* Wait for a completion event from the master or slave */
+ do
+ {
+ locStatus = (CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base));
+ locStatus |= (CY_SCB_I2C_SLAVE_ADDR_DONE & Cy_SCB_GetSlaveInterruptStatus(base));
+ locStatus |= WaitOneUnit(&timeout);
+
+ } while (0UL == locStatus);
+
+ /* Convert the status from register plus timeout to the return status */
+ retStatus = HandleStatus(base, locStatus, context);
+ }
+
+ /* Enable I2C slave interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR);
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterSendReStart
+****************************************************************************//**
+*
+* Generates a ReStart condition and sends a slave address with the Read/Write
+* bit.
+* This function is blocking. It does not return until the ReStart condition
+* and address byte are sent and an ACK/NAK is received, or an error or timeout
+* occurs.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param address
+* A 7-bit right-justified slave address.
+*
+* \param bitRnW
+* This sets the value of the Read/Write bit in the address, thus defining
+* the direction of the following transfer.
+* See \ref cy_en_scb_i2c_direction_t for the set of constants.
+*
+* \param timeoutMs
+* Defines in milliseconds the time for which this function can block.
+* If that time expires, the function returns. If a zero is passed,
+* the function waits forever for the action to complete. If a timeout occurs,
+* the SCB block is reset. Note The maximum value is UINT32_MAX/1000.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* * A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart
+* before calling this function. If this condition is not met, this function
+* does nothing and returns \ref CY_SCB_I2C_MASTER_NOT_READY.
+* * After a read transaction is initiated and the slave ACKs the address,
+* at least one byte must be read before completing the transaction or
+* changing its direction.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base,
+ uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
+ uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (address));
+ CY_ASSERT_L2(CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs));
+ CY_ASSERT_L3(CY_SCB_I2C_IS_RW_BIT_VALID (bitRnW));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state))
+ {
+ uint32_t locStatus = 0U;
+ uint32_t timeout = CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs);
+
+ /* Set the read or write direction */
+ context->state = CY_SCB_I2C_MASTER_ADDR;
+ context->masterRdDir = (CY_SCB_I2C_READ_XFER == bitRnW);
+
+ /* Generate ReStart condition.
+ * If previous transfer was read, NACK is generated before ReStart to
+ * complete previous transfer.
+ */
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_Msk | (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ?
+ SCB_I2C_M_CMD_M_NACK_Msk : 0UL);
+
+ /* Previous transfer was a write */
+ if (false == _FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS))
+ {
+ /* Cypress ID #295908: Wait until ReStart is generated to complete
+ * the previous write transfer. This ensures that the address byte
+ * will not be interpreted as the data byte of the previous
+ * transfer.
+ */
+ while ((0U == locStatus) &&
+ (0U != (SCB_I2C_M_CMD_M_START_Msk & base->I2C_M_CMD)))
+ {
+ locStatus = WaitOneUnit(&timeout);
+ }
+ }
+
+ /* Check for timeout and continue */
+ if (0U == locStatus)
+ {
+ /* Send the address byte */
+ Cy_SCB_WriteTxFifo(base, (_VAL2FLD(CY_SCB_I2C_ADDRESS, address) | (uint32_t) bitRnW));
+
+ /* Wait for a completion event from the or slave */
+ do
+ {
+ locStatus = (CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base));
+ locStatus |= WaitOneUnit(&timeout);
+
+ } while (0UL == locStatus);
+ }
+
+ /* Convert the status from register plus timeout to the return status */
+ retStatus = HandleStatus(base, locStatus, context);
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterSendStop
+****************************************************************************//**
+*
+* Generates a Stop condition to complete the current transaction.
+* This function is blocking. It does not return until the Stop condition
+* is generated, or an error or timeout occurs.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param timeoutMs
+* Defines in milliseconds the time for which this function can block.
+* If that time expires, the function returns. If a zero is passed,
+* the function waits forever for the action to complete. If a timeout occurs,
+* the SCB block is reset. Note The maximum value is UINT32_MAX/1000.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* * A successful transaction must be initiated by
+* \ref Cy_SCB_I2C_MasterSendStart or \ref Cy_SCB_I2C_MasterSendReStart
+* before calling this function. If this condition is not met, this function
+* does nothing and returns.
+* \ref CY_SCB_I2C_MASTER_NOT_READY.
+* * Even after the slave NAKs the address, this function must be called
+* to complete the transaction.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStop(CySCB_Type *base,uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state))
+ {
+ uint32_t locStatus;
+ uint32_t timeout = CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs);
+
+ /* Generate a stop (for Write direction) and NACK plus stop for the Read direction */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk);
+
+ /* Wait for a completion event from the master or slave */
+ do
+ {
+ locStatus = (CY_SCB_I2C_MASTER_STOP_DONE & Cy_SCB_GetMasterInterruptStatus(base));
+ locStatus |= WaitOneUnit(&timeout);
+
+ } while (0UL == locStatus);
+
+ /* Convert the status from register plus timeout to the return status */
+ retStatus = HandleStatus(base, locStatus, context);
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterReadByte
+****************************************************************************//**
+*
+* Reads one byte from a slave and generates an ACK or prepares to generate
+* a NAK. The NAK will be generated before a Stop or ReStart condition by
+* \ref Cy_SCB_I2C_MasterSendStop or \ref Cy_SCB_I2C_MasterSendReStart function
+* appropriately.
+* This function is blocking. It does not return until a byte is
+* received, or an error or timeout occurs.
+* The corresponding non-blocking function is \ref Cy_SCB_I2C_MasterRead.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param ackNack
+* A response to a received byte.
+* See \ref cy_en_scb_i2c_command_t for the set of constants.
+*
+* \param byte
+* The pointer to the location to store the Read byte.
+*
+* \param timeoutMs
+* Defines in milliseconds the time for which this function can block.
+* If that time expires, the function returns. If a zero is passed,
+* the function waits forever for the action to complete. If a timeout occurs,
+* the SCB block is reset. Note The maximum value is UINT32_MAX/1000.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart
+* or \ref Cy_SCB_I2C_MasterSendReStart before calling this function. If this
+* condition is not met, this function does nothing and returns
+* \ref CY_SCB_I2C_MASTER_NOT_READY.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterReadByte(CySCB_Type *base,
+ cy_en_scb_i2c_command_t ackNack, uint8_t *byte,
+ uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID (byte, 1UL));
+ CY_ASSERT_L2(CY_SCB_I2C_IS_TIMEOUT_VALID (timeoutMs));
+ CY_ASSERT_L3(CY_SCB_I2C_IS_RESPONSE_VALID(ackNack));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ if (CY_SCB_I2C_MASTER_RX0 == context->state)
+ {
+ bool rxNotEmpty;
+ uint32_t locStatus;
+ uint32_t timeout = CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs);
+
+ /* Wait for ACK/NAK transmission and data byte reception */
+ do
+ {
+ rxNotEmpty = (0UL != (CY_SCB_RX_INTR_NOT_EMPTY & Cy_SCB_GetRxInterruptStatus(base)));
+ locStatus = (CY_SCB_I2C_MASTER_RX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base));
+ locStatus |= WaitOneUnit(&timeout);
+
+ } while ((!rxNotEmpty) && (0UL == locStatus));
+
+
+ if (rxNotEmpty)
+ {
+ /* Get the received data byte */
+ *byte = (uint8_t) Cy_SCB_ReadRxFifo(base);
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_LEVEL);
+ }
+
+ /* Convert the status from register plus timeout to the return status */
+ retStatus = HandleStatus(base, locStatus, context);
+
+ if (CY_SCB_I2C_SUCCESS == retStatus)
+ {
+ if (CY_SCB_I2C_ACK == ackNack)
+ {
+ /* Generate ACK */
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_ACK_Msk;
+ }
+ else
+ {
+ /* NAK is generated by SendStop() or SendReStart() */
+ }
+ }
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterWriteByte
+****************************************************************************//**
+*
+* Sends one byte to a slave.
+* This function is blocking. It does not return until a byte is
+* transmitted, or an error or timeout occurs.
+* The corresponding non-blocking function is \ref Cy_SCB_I2C_MasterWrite.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param byte
+* The byte to write to a slave.
+*
+* \param timeoutMs
+* Defines in milliseconds the time for which this function can block.
+* If that time expires, the function returns. If a zero is passed,
+* the function waits forever for the action to complete. If a timeout occurs,
+* the SCB block is reset. Note The maximum value is UINT32_MAX/1000.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+* \note
+* A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart
+* or \ref Cy_SCB_I2C_MasterSendReStart before calling this function. If this
+* condition is not met, this function does nothing and returns
+* \ref CY_SCB_I2C_MASTER_NOT_READY.
+*
+*******************************************************************************/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte(CySCB_Type *base, uint8_t byte, uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context)
+{
+ CY_ASSERT_L2(CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs));
+
+ cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY;
+
+ if (CY_SCB_I2C_MASTER_TX == context->state)
+ {
+ uint32_t locStatus;
+ uint32_t timeout = CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs);
+
+ /* Send the data byte */
+ Cy_SCB_WriteTxFifo(base, (uint32_t) byte);
+
+ /* Wait for a completion event from the master or slave */
+ do
+ {
+ locStatus = (CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base));
+ locStatus |= WaitOneUnit(&timeout);
+
+ } while (0UL == locStatus);
+
+ /* Convert the status from register plus timeout to the API status */
+ retStatus = HandleStatus(base, locStatus, context);
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_Interrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in the I2C mode.
+* The interrupt is mandatory for I2C operation and this function must be called
+* inside the user-defined interrupt service. The exception is the I2C master,
+* which uses only the \ref group_scb_i2c_master_low_level_functions functions.
+* To reduce the flash consumed by the I2C driver call
+* \ref Cy_SCB_I2C_SlaveInterrupt when I2C mode is the slave and
+* \ref Cy_SCB_I2C_MasterInterrupt when I2C mode is the master.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_Interrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state))
+ {
+ /* Execute a transfer as the master */
+ Cy_SCB_I2C_MasterInterrupt(base, context);
+ }
+ else
+ {
+ /* Execute a transfer as the slave */
+ Cy_SCB_I2C_SlaveInterrupt(base, context);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveInterrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in I2C mode as the
+* slave. This function should be called inside the user-defined interrupt
+* service routine to make any of the slave functions to work.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_SlaveInterrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t slaveIntrStatus;
+
+ /* Handle an I2C wake-up event */
+ if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base)))
+ {
+ /* Move from IDLE state, the slave was addressed. Following address match
+ * interrupt continue transfer.
+ */
+ context->state = CY_SCB_I2C_SLAVE_ACTIVE;
+
+ Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
+ }
+
+ /* Handle the slave interrupt sources */
+ slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);
+
+ /* Handle the error conditions */
+ if (0UL != (CY_SCB_I2C_SLAVE_INTR_ERROR & slaveIntrStatus))
+ {
+ /* Update the status */
+ context->slaveStatus |= (0UL != (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR & slaveIntrStatus)) ?
+ CY_SCB_I2C_SLAVE_BUS_ERR : CY_SCB_I2C_SLAVE_ARB_LOST;
+
+ /* Disable the RX interrupt source to drop data into RX FIFO if any */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* Add the stop status to back into the default state and set completion statuses */
+ slaveIntrStatus |= CY_SCB_SLAVE_INTR_I2C_STOP;
+ }
+ else
+ {
+ if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))
+ {
+ /* Get data from the RX FIFO after a stop is generated if there is
+ * space to store it.
+ */
+ if ((Cy_SCB_GetNumInRxFifo(base) > 0UL) && (context->slaveRxBufferSize > 0UL))
+ {
+ Cy_SCB_SetRxInterrupt (base, CY_SCB_RX_INTR_LEVEL);
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ }
+ }
+
+ /* Handle the receive direction (master writes data) */
+ if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ SlaveHandleDataReceive(base, context);
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ /* Handle the transfer completion */
+ if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))
+ {
+ SlaveHandleStop(base, context);
+
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP);
+
+ /* Update the slave interrupt status */
+ slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);
+ }
+
+ /* Handle the address reception */
+ if (0UL != (CY_SCB_I2C_SLAVE_INTR_ADDR & slaveIntrStatus))
+ {
+ SlaveHandleAddress(base, context);
+
+ Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_I2C_SLAVE_INTR_ADDR);
+ }
+
+ /* Handle the transmit direction (master reads data) */
+ if (0UL != (CY_SCB_I2C_SLAVE_INTR_TX & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ SlaveHandleDataTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SlaveHandleAddress
+****************************************************************************//**
+*
+* Prepares the slave for the following Read or Write transfer after the
+* matched address was received.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void SlaveHandleAddress(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ /* The default command is the ACK address. It can be overridden in an address callback */
+ cy_en_scb_i2c_command_t cmd = CY_SCB_I2C_ACK;
+
+ /* The callback for the address in RX FIFO or a general call */
+ if (NULL != context->cbAddr)
+ {
+ uint32_t events = 0UL;
+
+ /* Set an address in the FIFO event if the address accept is enabled */
+ if (_FLD2BOOL(SCB_CTRL_ADDR_ACCEPT, base->CTRL))
+ {
+ events = (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ?
+ CY_SCB_I2C_ADDR_IN_FIFO_EVENT : 0UL;
+ }
+
+ /* Set a general call event if "ignore general call" is disabled */
+ if (!_FLD2BOOL(SCB_I2C_CTRL_S_GENERAL_IGNORE, base->I2C_CTRL))
+ {
+ events |= (0UL != (CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ?
+ CY_SCB_I2C_GENERAL_CALL_EVENT : 0UL;
+ }
+
+ /* Check presence of events before involve callback */
+ if (0UL != events)
+ {
+ /* Involve a callback for the address phase and get the ACK/NACK command */
+ cmd = context->cbAddr(events);
+
+ /* Clear RX level interrupt after address reception */
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+
+ if (cmd == CY_SCB_I2C_ACK)
+ {
+ /* Clear the stall stop status and enable the stop interrupt source */
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP);
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR);
+ }
+ else
+ {
+ /* Disable the stop interrupt source */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR_NO_STOP);
+ }
+ }
+ }
+
+ /* Clear the TX FIFO before continue the transaction */
+ Cy_SCB_ClearTxFifo(base);
+
+ /* Set the command to an ACK or NACK address */
+ base->I2C_S_CMD = (cmd == CY_SCB_I2C_ACK) ? SCB_I2C_S_CMD_S_ACK_Msk : SCB_I2C_S_CMD_S_NACK_Msk;
+
+ if (cmd == CY_SCB_I2C_ACK)
+ {
+ bool readDirection = _FLD2BOOL(SCB_I2C_STATUS_S_READ,base->I2C_STATUS);
+
+ /* Notify the user about start of transfer */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(readDirection ? CY_SCB_I2C_SLAVE_READ_EVENT : CY_SCB_I2C_SLAVE_WRITE_EVENT);
+ }
+
+ /* Prepare for a transfer */
+ if (readDirection)
+ {
+ context->state = CY_SCB_I2C_SLAVE_TX;
+ context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_BUSY;
+
+ /* Prepare to transmit data */
+ context->slaveTxBufferIdx = context->slaveTxBufferCnt;
+ context->slaveRdBufEmpty = false;
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+ else
+ {
+ uint32_t level = 0UL;
+
+ context->state = CY_SCB_I2C_SLAVE_RX;
+ context->slaveStatus |= CY_SCB_I2C_SLAVE_WR_BUSY;
+
+ /* Prepare to receive data */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+
+ if (context->useRxFifo)
+ {
+ if (context->slaveRxBufferSize > 0UL)
+ {
+ uint32_t fifoSize = CY_SCB_I2C_FIFO_SIZE(base);
+
+ /* ACK data automatically until RX FIFO is full */
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk;
+
+ if (context->slaveRxBufferSize > fifoSize)
+ {
+ /* Set a level in RX FIFO to trigger the receive interrupt source */
+ level = (context->slaveRxBufferSize - fifoSize);
+ level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL;
+ }
+ else
+ {
+ /* Set a level in RX FIFO to read the number of bytes */
+ level = (context->slaveRxBufferSize - 1UL);
+
+ /* NACK when RX FIFO becomes full */
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk;
+
+ /* Disable the RX level interrupt and wait until RX FIFO is full or stops */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+ }
+ }
+
+ Cy_SCB_SetRxFifoLevel(base, level);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SlaveHandleDataReceive
+****************************************************************************//**
+*
+* Reads data from RX FIFO into the buffer provided by
+* \ref Cy_SCB_I2C_SlaveConfigWriteBuf.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void SlaveHandleDataReceive(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ /* Check whether there is space to put data */
+ if (context->slaveRxBufferSize > 0UL)
+ {
+ if (context->useRxFifo)
+ {
+ uint32_t level;
+ uint32_t fifoSize = CY_SCB_I2C_FIFO_SIZE(base);
+
+ /* Get the number of bytes to read from RX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetRxFifoLevel(base) + 1UL;
+
+ /* Get data from RX FIFO */
+ numToCopy = Cy_SCB_ReadArray(base, context->slaveRxBuffer, numToCopy);
+ context->slaveRxBufferIdx += numToCopy;
+ context->slaveRxBufferSize -= numToCopy;
+ context->slaveRxBuffer = &context->slaveRxBuffer[numToCopy];
+
+ /* Prepare to read a next chunk of data */
+ if (context->slaveRxBufferSize > fifoSize)
+ {
+ level = context->slaveRxBufferSize - fifoSize;
+ level = ((level > fifoSize) ? (fifoSize / 2UL) : level) - 1UL;
+ }
+ else
+ {
+ base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk;
+
+ level = (context->slaveRxBufferSize == 0UL) ? (0UL) : (context->slaveRxBufferSize - 1UL);
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ /* Set the RX level to trigger an interrupt */
+ Cy_SCB_SetRxFifoLevel(base, level);
+ }
+ else
+ {
+ /* Continue the transfer: send an ACK */
+ base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk;
+
+ /* Put data into the RX buffer */
+ context->slaveRxBuffer[context->slaveRxBufferIdx] = (uint8_t) Cy_SCB_ReadRxFifo(base);
+ ++context->slaveRxBufferIdx;
+ --context->slaveRxBufferSize;
+ }
+ }
+ else
+ {
+ /* Finish a transfer: send a NACK and discard the received byte */
+ base->I2C_S_CMD = SCB_I2C_S_CMD_S_NACK_Msk;
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SlaveHandleDataTransmit
+****************************************************************************//**
+*
+* Loads TX FIFO with data provided by \ref Cy_SCB_I2C_SlaveConfigReadBuf.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t numToCopy;
+
+ /* Notify the user that there is no data to send to the master.
+ * This event triggers once in scope of a transfer.
+ */
+ if ((!context->slaveRdBufEmpty) && (0UL == context->slaveTxBufferSize))
+ {
+ /* Involve a callback if registered: no data to send */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT);
+ }
+
+ /* Update the Read buffer empty status after a callback is involved */
+ context->slaveRdBufEmpty = (0UL == context->slaveTxBufferSize);
+
+ /* Enable the TX level interrupt source to continue sending data */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ /* Check whether the Read buffer was updated in the callback */
+ if (context->slaveRdBufEmpty)
+ {
+ /* The Read buffer is empty: copy CY_SCB_I2C_DEFAULT_TX into TX FIFO */
+ numToCopy = (context->useTxFifo) ? Cy_SCB_GetFifoSize(base) : 1UL;
+
+ numToCopy = Cy_SCB_WriteDefaultArray(base, CY_SCB_I2C_DEFAULT_TX, numToCopy);
+ context->slaveTxBufferIdx += numToCopy;
+
+ context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_UNDRFL;
+ }
+ else
+ {
+ if (context->slaveTxBufferSize > 1UL)
+ {
+ /* Get the number of bytes to copy into TX FIFO */
+ numToCopy = (context->useTxFifo) ? (context->slaveTxBufferSize - 1UL) : (1UL);
+
+ /* Write data into TX FIFO */
+ numToCopy = Cy_SCB_WriteArray(base, context->slaveTxBuffer, numToCopy);
+ context->slaveTxBufferIdx += numToCopy;
+ context->slaveTxBufferSize -= numToCopy;
+ context->slaveTxBuffer = &context->slaveTxBuffer[numToCopy];
+ }
+
+ /* Put the last byte */
+ if ((CY_SCB_I2C_FIFO_SIZE(base) != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->slaveTxBufferSize))
+ {
+ uint32_t intrStatus;
+
+ /* Put the last data byte in the TX FIFO and clear the TX Underflow
+ * interrupt source inside the critical section to ensure that the
+ * TX Underflow interrupt will trigger after all data bytes from the
+ * TX FIFO are transferred onto the bus.
+ */
+ intrStatus = Cy_SysLib_EnterCriticalSection();
+
+ Cy_SCB_WriteTxFifo (base, (uint32_t) context->slaveTxBuffer[0UL]);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
+
+ Cy_SysLib_ExitCriticalSection(intrStatus);
+
+ /* Move the pointers */
+ ++context->slaveTxBufferIdx;
+ context->slaveTxBufferSize = 0UL;
+ context->slaveTxBuffer = &context->slaveTxBuffer[1UL];
+
+ /* Enable the TX underflow interrupt to catch when there is no data to send */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW);
+
+ if (context->useTxFifo)
+ {
+ /* Data is copied into TX FIFO */
+ context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_IN_FIFO;
+
+ /* Involve a callback if registered: data copied into TX FIFO */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT);
+ }
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SlaveHandleStop
+****************************************************************************//**
+*
+* Handles transfer completion. It is triggered by a stop or restart
+* condition on the bus.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void SlaveHandleStop(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t locEvents;
+
+ if (CY_SCB_I2C_SLAVE_RX == context->state)
+ {
+ /* If any data is left in RX FIFO, this is an overflow */
+ if (Cy_SCB_GetNumInRxFifo(base) > 0UL)
+ {
+ context->slaveStatus |= CY_SCB_I2C_SLAVE_WR_OVRFL;
+
+ if (context->useRxFifo)
+ {
+ Cy_SCB_ClearRxFifo(base);
+ }
+ else
+ {
+ (void) Cy_SCB_ReadRxFifo(base);
+ }
+ }
+
+ locEvents = (uint32_t) CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT;
+ context->slaveStatus |= (uint32_t) CY_SCB_I2C_SLAVE_WR_CMPLT;
+ context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_WR_BUSY;
+
+ /* Clean up the RX direction */
+ base->I2C_CTRL &= (uint32_t) ~(SCB_I2C_CTRL_S_READY_DATA_ACK_Msk |
+ SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk);
+
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ else
+ {
+ /* The number of bytes left in TX FIFO */
+ uint32_t size = Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base);
+
+ /* Get the number of bytes transferred from the read buffer */
+ context->slaveTxBufferCnt = (context->slaveTxBufferIdx - size);
+
+ /* Update buffer pointer and its size if there is no overflow */
+ if (0UL == (CY_SCB_I2C_SLAVE_RD_UNDRFL & context->slaveStatus))
+ {
+ context->slaveTxBufferSize += size;
+ context->slaveTxBuffer -= size;
+ }
+
+ locEvents = (uint32_t) CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT;
+ context->slaveStatus |= (uint32_t) CY_SCB_I2C_SLAVE_RD_CMPLT;
+ context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_RD_BUSY;
+
+ /* Clean up the TX direction */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ /* Return scb into the known state after an error */
+ if (0UL != (CY_SCB_I2C_SLAVE_INTR_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base)))
+ {
+ /* After scb IP is reset, the interrupt statuses are cleared */
+ Cy_SCB_FwBlockReset(base);
+
+ locEvents |= CY_SCB_I2C_SLAVE_ERR_EVENT;
+ }
+
+ /* After a stop or error, set the state to idle */
+ context->state = CY_SCB_I2C_IDLE;
+
+ /* Call a completion callback if registered */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(locEvents);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterInterrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in I2C mode as the
+* master. This function should be called inside the user-defined interrupt
+* service routine to make \ref group_scb_i2c_master_high_level_functions
+* functions to work.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_I2C_MasterInterrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t intrCause = Cy_SCB_GetInterruptCause(base);
+
+ /* Check whether the slave is active. It can be addressed during the master set-up transfer */
+ if (0UL != (CY_SCB_SLAVE_INTR & intrCause))
+ {
+ /* Abort the transfer due to slave operation */
+ if (0UL != base->I2C_M_CMD)
+ {
+ base->I2C_M_CMD = 0UL;
+
+ context->masterStatus |= CY_SCB_I2C_MASTER_ABORT_START;
+ }
+
+ context->state = CY_SCB_I2C_MASTER_CMPLT;
+ }
+
+ /* Check for master error conditions */
+ if (0UL != (CY_SCB_MASTER_INTR & intrCause))
+ {
+ MasterHandleEvents(base, context);
+
+ /* Any master event does not require further TX processing */
+ intrCause &= (uint32_t) ~CY_SCB_TX_INTR;
+ }
+
+ if (0UL != (CY_SCB_RX_INTR & intrCause))
+ {
+ MasterHandleDataReceive(base, context);
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ if (0UL != (CY_SCB_TX_INTR & intrCause))
+ {
+ MasterHandleDataTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ /* Complete the transfer */
+ if (CY_SCB_I2C_MASTER_CMPLT == context->state)
+ {
+ MasterHandleComplete(base, context);
+ }
+
+ /* Generate stop to complete transfer */
+ if (CY_SCB_I2C_MASTER_STOP == context->state)
+ {
+ MasterHandleStop(base, context);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: MasterHandleMasterEvents
+****************************************************************************//**
+*
+* Reads data from RX FIFO into the buffer provided by \ref Cy_SCB_I2C_MasterRead.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* The master CY_SCB_MASTER_INTR_I2C_ACK interrupt source is used for Stop
+* generation or request to abort transfer.
+*
+*******************************************************************************/
+static void MasterHandleEvents(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t masterIntrStatus = Cy_SCB_GetMasterInterruptStatusMasked(base);
+
+ /* The master has not received the acknowledgment for slave */
+ if (0UL != (CY_SCB_MASTER_INTR_I2C_NACK & masterIntrStatus))
+ {
+ /* Clear NAK interrupt source */
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_MASTER_INTR_I2C_NACK);
+
+ /* Update status to indicate address or data was NACKed */
+ context->masterStatus |= (0UL != (CY_SCB_MASTER_INTR_I2C_ACK & Cy_SCB_GetMasterInterruptStatus(base))) ?
+ CY_SCB_I2C_MASTER_DATA_NAK : CY_SCB_I2C_MASTER_ADDR_NAK;
+
+ /* Check whether Stop generation was requested before */
+ if (CY_SCB_I2C_MASTER_WAIT_STOP != context->state)
+ {
+ context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_CMPLT : CY_SCB_I2C_MASTER_STOP;
+ }
+ }
+
+ /* The master detected a bus error condition */
+ if (0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & masterIntrStatus))
+ {
+ context->masterStatus |= CY_SCB_I2C_MASTER_BUS_ERR;
+ }
+
+ /* The master detected an arbitration lost condition */
+ if (0UL != (CY_SCB_MASTER_INTR_I2C_ARB_LOST & masterIntrStatus))
+ {
+ context->masterStatus |= CY_SCB_I2C_MASTER_ARB_LOST;
+ }
+
+ /* Complete the transfer: stop, bus error or arbitration lost */
+ if (0UL != (CY_SCB_I2C_MASTER_INTR_CMPLT & masterIntrStatus))
+ {
+ context->state = CY_SCB_I2C_MASTER_CMPLT;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: MasterHandleDataReceive
+****************************************************************************//**
+*
+* Reads data from RX FIFO into the buffer provided by \ref Cy_SCB_I2C_MasterRead.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void MasterHandleDataReceive(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ switch (context->state)
+ {
+ case CY_SCB_I2C_MASTER_RX0:
+ {
+ /* Put data into the component buffer */
+ context->masterBuffer[0UL] = (uint8_t) Cy_SCB_ReadRxFifo(base);
+
+ ++context->masterBufferIdx;
+ --context->masterBufferSize;
+
+ if (context->masterBufferSize > 0UL)
+ {
+ /* Continue the transaction: move pointer send an ACK */
+ context->masterBuffer = &context->masterBuffer[1UL];
+ base->I2C_M_CMD = SCB_I2C_M_CMD_M_ACK_Msk;
+ }
+ else
+ {
+ /* Complete the transaction */
+ context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_CMPLT : CY_SCB_I2C_MASTER_STOP;
+ }
+ }
+ break;
+
+ case CY_SCB_I2C_MASTER_RX1:
+ {
+ uint32_t numToCopied;
+
+ /* Get data from RX FIFO */
+ numToCopied = Cy_SCB_ReadArray(base, context->masterBuffer, context->masterBufferSize);
+ context->masterBufferIdx += numToCopied;
+ context->masterBufferSize -= numToCopied;
+ context->masterBuffer = &context->masterBuffer[numToCopied];
+
+ if (context->masterBufferSize < 2UL)
+ {
+ /* Stop ACKing data */
+ base->I2C_CTRL &= (uint32_t) ~SCB_I2C_CTRL_M_READY_DATA_ACK_Msk;
+
+ if (1UL == context->masterBufferSize)
+ {
+ /* Catch the last byte */
+ Cy_SCB_SetRxFifoLevel(base, 0UL);
+
+ context->state = CY_SCB_I2C_MASTER_RX0;
+ }
+ else
+ {
+ /* Stop RX processing */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ context->state = CY_SCB_I2C_MASTER_STOP;
+ }
+ }
+ else
+ {
+ uint32_t halfFifoSize = CY_SCB_I2C_HALF_FIFO_SIZE(base);
+
+ /* Continue the transfer: Adjust the level in RX FIFO */
+ Cy_SCB_SetRxFifoLevel(base, (context->masterBufferSize <= halfFifoSize) ?
+ (context->masterBufferSize - 2UL) : (halfFifoSize - 1UL));
+ }
+ }
+ break;
+
+ default:
+ /* Do nothing: drop data into RX FIFO */
+ break;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: MasterHandleDataTransmit
+****************************************************************************//**
+*
+* Loads TX FIFO with data provided by \ref Cy_SCB_I2C_MasterWrite.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ if (CY_SCB_I2C_MASTER_TX_DONE == context->state)
+ {
+ context->state = CY_SCB_I2C_MASTER_CMPLT;
+ }
+ else if (CY_SCB_I2C_MASTER_TX == context->state)
+ {
+ if (context->masterBufferSize > 1UL)
+ {
+ /* Get the number of bytes to copy into TX FIFO */
+ uint32_t NumToCopy = (context->useTxFifo) ? (context->masterBufferSize - 1UL) : (1UL);
+
+ /* Write data into TX FIFO */
+ NumToCopy = Cy_SCB_WriteArray(base, context->masterBuffer, NumToCopy);
+ context->masterBufferIdx += NumToCopy;
+ context->masterBufferSize -= NumToCopy;
+ context->masterBuffer = &context->masterBuffer[NumToCopy];
+ }
+
+ /* Put the last byte */
+ if ((CY_SCB_I2C_FIFO_SIZE(base) != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->masterBufferSize))
+ {
+ uint32_t intrStatus;
+
+ /* Put the last data byte in the TX FIFO and clear the TX Underflow
+ * interrupt source inside the critical section to ensure that the
+ * TX Underflow interrupt will trigger after all data bytes from the
+ * TX FIFO are transferred onto the bus.
+ */
+ intrStatus = Cy_SysLib_EnterCriticalSection();
+
+ Cy_SCB_WriteTxFifo (base, (uint32_t) context->masterBuffer[0UL]);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
+
+ Cy_SysLib_ExitCriticalSection(intrStatus);
+
+ ++context->masterBufferIdx;
+ context->masterBufferSize = 0UL;
+ }
+
+ /* Complete the transfer */
+ if (0UL == context->masterBufferSize)
+ {
+ if (context->masterPause)
+ {
+ /* Wait until data is transfered onto the bus */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW);
+
+ context->state = CY_SCB_I2C_MASTER_TX_DONE;
+ }
+ else
+ {
+ /* Disable TX processing */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* Request Stop generation */
+ context->state = CY_SCB_I2C_MASTER_STOP;
+ }
+
+ if (context->useTxFifo)
+ {
+ /* Notify the user that data is in TX FIFO */
+ context->masterStatus |= CY_SCB_I2C_MASTER_WR_IN_FIFO;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: MasterHandleStop
+****************************************************************************//**
+*
+* Handles the stop condition generation
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void MasterHandleStop(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ /* Stop RX and TX processing */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (0UL != base->I2C_M_CMD)
+ {
+ /* Enable ACK interrupt source: it triggers after ACK response to
+ * address was received.
+ */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ }
+ else
+ {
+ /* Disable ACK interrupt source */
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR);
+
+ /* Complete transaction generating Stop */
+ base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk);
+ context->state = CY_SCB_I2C_MASTER_WAIT_STOP;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: MasterHandleComplete
+****************************************************************************//**
+*
+* Handles the transfer completion on a stop or restart - the normal case or
+* completion due to an error on the bus or lost arbitration.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated
+* by the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void MasterHandleComplete(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
+{
+ uint32_t masterIntrStatus = Cy_SCB_GetMasterInterruptStatusMasked(base);
+
+ /* Clean-up hardware */
+
+ /* Disalbe auto data ACK option */
+ base->I2C_CTRL &= (uint32_t) ~SCB_I2C_CTRL_M_READY_DATA_ACK_Msk;
+
+ /* Disable the interrupt source for master operation */
+ Cy_SCB_SetRxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetTxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL);
+
+ /* Operation complete - master is not busy anymore */
+ context->masterStatus &= (uint32_t) ~CY_SCB_I2C_MASTER_BUSY;
+
+ /* Get number of byte transferred on the bus */
+ if (context->masterRdDir)
+ {
+ context->masterNumBytes = context->masterBufferIdx;
+ }
+ else
+ {
+ context->masterNumBytes = context->masterBufferIdx -
+ (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base));
+ }
+
+ /* Clean up after a not completed transfer */
+ if (0UL != (CY_SCB_I2C_MASTER_INTR_ERR & masterIntrStatus))
+ {
+ /* Reset the scb IP block when:
+ * 1. Master mode: Reset IP when arbitration is lost or a bus error occurs.
+ * 2. Master-Slave mode: Reset IP if it is not the address phase (ACK is 0).
+ * Otherwise, reset only on a bus error. If "lost arbitration" happens, the slave
+ * can be addressed, so let the slave accept the address.
+ */
+
+ bool resetIp = true;
+
+ /* Check the Master-Slave address an ACK/NACK */
+ if (((uint32_t) CY_SCB_I2C_MASTER_SLAVE) == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL))
+ {
+ resetIp = ((0UL != (CY_SCB_MASTER_INTR_I2C_ACK & masterIntrStatus)) ? true :
+ ((0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & masterIntrStatus)) ? true : false));
+ }
+
+ if (resetIp)
+ {
+ /* Reset to get it back in an known state */
+ Cy_SCB_FwBlockReset(base);
+ }
+
+ /* Back to the idle state. The master is not active anymore */
+ context->state = CY_SCB_I2C_IDLE;
+ }
+ else
+ {
+ if (context->useRxFifo)
+ {
+ /* Clear RX FIFO from remaining data and level interrupt source */
+ Cy_SCB_ClearRxFifo(base);
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_WAIT : CY_SCB_I2C_IDLE;
+ }
+
+ /* An operation completion callback */
+ if (NULL != context->cbEvents)
+ {
+ /* Get completion events based on the hardware status */
+ uint32_t locEvents = context->masterRdDir ? CY_SCB_I2C_MASTER_RD_CMPLT_EVENT : CY_SCB_I2C_MASTER_WR_CMPLT_EVENT;
+
+ /* Add errors if any */
+ locEvents |= (0UL != (CY_SCB_I2C_MASTER_ERR & context->masterStatus)) ? CY_SCB_I2C_MASTER_ERR_EVENT : 0UL;
+
+ context->cbEvents(locEvents);
+ }
+}
+
+
+
+/******************************************************************************
+* Function Name: WaitOneUnit
+****************************************************************************//**
+*
+* Waits for one unit before unblock code execution.
+* Note that if a timeout value is 0, this function does nothing and returns 0.
+*
+* \param timeout
+* The pointer to a timeout value.
+*
+* \return
+* Returns 0 if a timeout does not expire or the timeout mask.
+*
+*******************************************************************************/
+static uint32_t WaitOneUnit(uint32_t *timeout)
+{
+ uint32_t status = 0UL;
+
+ /* If the timeout equal to 0. Ignore the timeout */
+ if (*timeout > 0UL)
+ {
+ Cy_SysLib_DelayUs(CY_SCB_WAIT_1_UNIT);
+ --(*timeout);
+
+ if (0UL == *timeout)
+ {
+ status = CY_SCB_I2C_MASTER_TIMEOUT_DONE;
+ }
+ }
+
+ return (status);
+}
+
+
+/******************************************************************************
+* Function Name: HandleStatus
+****************************************************************************//**
+*
+* Converts passed status into the cy_en_scb_i2c_status_t.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param status
+* The status to covert.
+*
+* \return
+* \ref cy_en_scb_i2c_status_t
+*
+*******************************************************************************/
+static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status, cy_stc_scb_i2c_context_t *context)
+{
+ cy_en_scb_i2c_status_t retStatus;
+ bool resetBlock = false;
+
+ /* Convert the master status to the API status */
+ if (0UL != (CY_SCB_I2C_MASTER_TIMEOUT_DONE & status))
+ {
+ retStatus = CY_SCB_I2C_MASTER_MANUAL_TIMEOUT;
+ resetBlock = true;
+ }
+ else if (0UL != (CY_SCB_I2C_SLAVE_ADDR_DONE & status))
+ {
+ /* Abort the master operation, the slave was addressed first */
+ retStatus = CY_SCB_I2C_MASTER_MANUAL_ABORT_START;
+
+ base->I2C_M_CMD = 0UL;
+ context->state = CY_SCB_I2C_IDLE;
+ }
+ else if (0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & status))
+ {
+ retStatus = CY_SCB_I2C_MASTER_MANUAL_BUS_ERR;
+ resetBlock = true;
+ }
+ else if (0UL != (CY_SCB_MASTER_INTR_I2C_ARB_LOST & status))
+ {
+ retStatus = CY_SCB_I2C_MASTER_MANUAL_ARB_LOST;
+
+ if (CY_SCB_I2C_MASTER_ADDR == context->state)
+ {
+ /* This is the address phase:
+ * 1. Master mode: Reset IP when "arbitration lost" occurs.
+ * 2. Master-Slave mode: If "lost arbitration" occurs, the slave
+ * can be addressed to let the slave accept the address; do not
+ * reset IP.
+ */
+ resetBlock = !_FLD2BOOL(SCB_I2C_CTRL_SLAVE_MODE, base->I2C_CTRL);
+
+ context->state = CY_SCB_I2C_IDLE;
+ }
+ else
+ {
+ resetBlock = true;
+ }
+ }
+ else if (0UL != (CY_SCB_MASTER_INTR_I2C_NACK & status))
+ {
+ /* An address or data was NAKed */
+ retStatus = (CY_SCB_I2C_MASTER_ADDR == context->state) ?
+ CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK : CY_SCB_I2C_MASTER_MANUAL_NAK;
+ }
+ else
+ {
+ retStatus = CY_SCB_I2C_SUCCESS;
+
+ if (0UL != (CY_SCB_MASTER_INTR_I2C_STOP & status))
+ {
+ /* End of transaction, go to idle state */
+ context->state = CY_SCB_I2C_IDLE;
+ }
+ else
+ {
+ /* Continue trasaction */
+ if (CY_SCB_I2C_MASTER_ADDR == context->state)
+ {
+ /* Switch from address to data state */
+ context->state = (context->masterRdDir) ?
+ CY_SCB_I2C_MASTER_RX0 : CY_SCB_I2C_MASTER_TX;
+ }
+ }
+ }
+
+ if (resetBlock)
+ {
+ /* Back block into default state */
+ Cy_SCB_FwBlockReset(base);
+
+ context->state = CY_SCB_I2C_IDLE;
+ }
+ else
+ {
+ Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL);
+ }
+
+ return (retStatus);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1417 @@
+/***************************************************************************//**
+* \file cy_scb_i2c.h
+* \version 2.10
+*
+* Provides I2C API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_i2c
+* \{
+* Driver API for I2C Bus Peripheral
+*
+* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
+* The two-wire hardware interface was developed by Philips Semiconductors
+* (now NXP Semiconductors).
+*
+* The I2C peripheral driver provides an API to implement I2C slave, master,
+* or master-slave devices based on the SCB hardware block.
+* I2C devices based on SCB hardware are compatible with I2C
+* Standard-mode, Fast-mode, and Fast-mode Plus specifications as defined in
+* the I2C-bus specification.
+*
+* Features:
+* * An industry-standard I2C bus interface
+* * Supports slave, master, and master-slave operation
+* * Supports standard data rates of 100/400/1000 kbps
+* * Hardware Address Match, multiple addresses
+* * Wake From Deep Sleep on Address Match
+*
+* \section group_scb_i2c_configuration Configuration Considerations
+* The I2C driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_i2c_config
+* * \ref group_scb_i2c_pins
+* * \ref group_scb_i2c_clock
+* * \ref group_scb_i2c_data_rate
+* * \ref group_scb_i2c_intr
+* * \ref group_scb_i2c_enable
+*
+* \note
+* I2C driver is built on top of the SCB hardware block. The SCB3 instance is
+* used as an example for all code snippets. Modify the code to match your
+* design.
+*
+* \subsection group_scb_i2c_config Configure I2C
+* To set up the I2C slave driver, provide the configuration parameters in the
+* \ref cy_stc_scb_i2c_config_t structure. Provide i2cMode to the select
+* operation mode slave, master or master-slave. For master modes, provide
+* useRxFifo and useTxFifo parameters. For slave mode, also provide the
+* slaveAddress and slaveAddressMask. The other parameters are optional for
+* operation. To initialize the driver, call \ref Cy_SCB_I2C_Init
+* function providing a pointer to the filled \ref cy_stc_scb_i2c_config_t
+* structure and allocated \ref cy_stc_scb_i2c_context_t.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG
+*
+* \subsection group_scb_i2c_pins Assign and Configure Pins
+* Only dedicated SCB pins can be used for I2C operation. The HSIOM
+* register must be configured to connect block to the pins. Also the I2C pins
+* must be configured in Open-Drain, Drives Low mode (this pins configuration
+* implies usage of external pull-up resistors):
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_PINS
+*
+* \note
+* The alternative pins configuration is Resistive Pull-ups which implies usage
+* internal pull-up resistors. This configuration is not recommended because
+* resistor value is fixed and cannot be used for all supported data rates.
+* Refer to the device datasheet parameter RPULLUP for resistor value specifications.
+*
+* \subsection group_scb_i2c_clock Assign Clock Divider
+* The clock source must be connected to the SCB block to oversample input and
+* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
+* source clock of this divider must be Clk_Peri)</b></em>. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_ASSIGN_CLOCK
+*
+* Set up I2C slave read and write buffer before enabling its
+* operation using \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref
+* Cy_SCB_I2C_SlaveConfigWriteBuf appropriately. Note that the master reads
+* data from the slave read buffer and writes data into the slave write buffer.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_BUFFER
+*
+* \subsection group_scb_i2c_data_rate Configure Data Rate
+* To get I2C slave operation with the desired data rate, the source clock must be
+* fast enough to provide sufficient oversampling. Therefore, the clock divider
+* must be configured to provide desired clock frequency. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_DATA_RATE_SLAVE
+*
+* To get I2C master operation with the desired data rate, the source clock
+* frequency and SCL low and high phase duration must be configured. Use the
+* \ref group_sysclk driver API to configure source clock frequency. Then call
+* \ref Cy_SCB_I2C_SetDataRate to set the SCL low and high phase duration.
+* This function reach for SCL low and high phase settings based on source clock
+* frequency.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_CFG_DATA_RATE_MASTER
+*
+* Alternatively, the low and high phase can be set directly using
+* \ref Cy_SCB_I2C_MasterSetLowPhaseDutyCycle and
+* \ref Cy_SCB_I2C_MasterSetHighPhaseDutyCycle functions. \n
+* Refer to the technical reference manual (TRM) section I2C sub-section
+* Oversampling and Bit Rate to get information how to configure I2C to run with
+* the desired data rate.
+*
+* \note
+* For I2C slave, the analog filter is used for all supported data rates. \n
+* For I2C master, the analog filter is used for Standard and Fast modes and the
+* digital filter for Fast Plus mode.
+*
+* \subsection group_scb_i2c_intr Configure Interrupt
+* The interrupt is mandatory for I2C operation. The exception is the I2C master,
+* which uses only the \ref group_scb_i2c_master_low_level_functions functions.
+* The driver provides three interrupt functions: \ref Cy_SCB_I2C_Interrupt,
+* \ref Cy_SCB_I2C_SlaveInterrupt, and \ref Cy_SCB_I2C_MasterInterrupt. One of
+* these functions must be called in the interrupt handler for the selected SCB
+* instance. Call \ref Cy_SCB_I2C_SlaveInterrupt when I2C is configured to
+* operate as a slave, \ref Cy_SCB_I2C_MasterInterrupt when I2C is configured
+* to operate as a master and \ref Cy_SCB_I2C_Interrupt when I2C is configured
+* to operate as master and slave. Using the slave- or master-specific interrupt
+* function allows reducing the flash consumed by the I2C driver. Also this
+* interrupt must be enabled in the NVIC otherwise it will not work.
+* \note
+* The I2C driver documentation refers to the \ref Cy_SCB_I2C_Interrupt function
+* when interrupt processing is mandatory for the operation. This is done to
+* simplify the readability of the driver's documentation. The application should
+* call the slave- or master-specific interrupt functions \ref Cy_SCB_I2C_SlaveInterrupt
+* or \ref Cy_SCB_I2C_MasterInterrupt, when appropriate.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_INTR_A
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_INTR_B
+*
+* \subsection group_scb_i2c_enable Enable I2C
+* Finally, enable the I2C operation calling \ref Cy_SCB_I2C_Enable. Then I2C
+* slave starts respond to the assigned address and I2C master ready to execute
+* transfers.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_ENABLE
+*
+* \section group_scb_i2c_use_cases Common Use Cases
+*
+* \subsection group_scb_i2c_master_mode Master Operation
+* The master API is divided into two categories:
+* \ref group_scb_i2c_master_high_level_functions and
+* \ref group_scb_i2c_master_low_level_functions. Therefore, there are two
+* methods for initiating I2C master transactions using either <b>Low-Level or
+* High-Level</b> API. These two methods are described below. Only one method
+* should be used at a time. They should not be mixed.
+*
+* \subsubsection group_scb_i2c_master_hl Use High-Level Functions
+* Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to
+* communicate with the slave. These functions do not block and only start a
+* transaction. After a transaction starts, the \ref Cy_SCB_I2C_Interrupt
+* handles the further data transaction until its completion (successfully or with an error
+* occurring). Therefore, \ref Cy_SCB_I2C_Interrupt must be called inside the
+* interrupt handler to make the functions above work. To monitor the transaction,
+* use \ref Cy_SCB_I2C_MasterGetStatus or register callback function using
+* \ref Cy_SCB_I2C_RegisterEventCallback to be notified about
+* \ref group_scb_i2c_macros_callback_events.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_WRITE_READ_INT
+*
+* \subsubsection group_scb_i2c_master_ll Use Low-Level Functions
+* Call \ref Cy_SCB_I2C_MasterSendStart to generate a start, send an address
+* with the Read/Write direction bit, and receive acknowledgment. After the
+* address is ACKed by the slave, the transaction can be continued by calling
+* \ref Cy_SCB_I2C_MasterReadByte or \ref Cy_SCB_I2C_MasterWriteByte depending
+* on its direction. These functions handle one byte per call. Therefore,
+* they should be called for each byte in the transaction. Note that for the
+* Read transaction, the last byte must be NAKed. To complete the current
+* transaction, call \ref Cy_SCB_I2C_MasterSendStop or call
+* \ref Cy_SCB_I2C_MasterSendReStart to complete the current transaction and
+* start a new one. Typically, do a restart to change the transaction
+* direction without releasing the bus from the master control.
+* The Low-Level functions are blocking and do not require calling
+* \ref Cy_SCB_I2C_Interrupt inside the interrupt handler. Using these
+* functions requires extensive knowledge of the I2C protocol to execute
+* transactions correctly.
+*
+* <b>Master Write Operation</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_WRITE_MANUAL
+*
+* <b>Master Read Operation</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_MASTER_READ_MANUAL
+*
+* \subsection group_scb_i2c_slave Slave Operation
+* The slave operation is based on the \ref Cy_SCB_I2C_Interrupt that must be
+* called inside the interrupt handler. The Read and Write buffer must
+* be provided for the slave to enable communication with the master. Use
+* \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref Cy_SCB_I2C_SlaveConfigWriteBuf
+* for this purpose. Note that after transaction completion the buffer must be
+* configured again. Otherwise, the same buffer is used starting from the point
+* where the master stopped a previous transaction.
+* For example: The Read buffer is configured to be 10 bytes and the master Read
+* is 8 bytes. If the Read buffer is not configured again, the next master Read
+* will start from the 9th byte.
+* To monitor the transaction status, use \ref Cy_SCB_I2C_SlaveGetStatus or
+* use \ref Cy_SCB_I2C_RegisterEventCallback to register a callback function
+* to be notified about \ref group_scb_i2c_macros_callback_events.
+*
+* <b>Get Slave Events Notification</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_REG_CALLBACK
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_NOTIFICATION
+*
+* <b>Polling Slave Completion Events</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\i2c_snippets.c I2C_SLAVE_POLLING
+*
+* \note
+* All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and
+* \ref Cy_SCB_I2C_SlaveAbortWrite) <b>are not interrupt-protected</b> and to
+* prevent a race condition, they should be protected from the I2C interruption
+* in the place where they are called.
+*
+* \section group_scb_i2c_lp Low Power Support
+* The I2C driver provides the callback functions to handle power mode transition.
+* The callback \ref Cy_SCB_I2C_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_I2C_HibernateCallback
+* must be called during execution of \ref Cy_SysPm_Hibernate. To trigger the
+* callback execution, the callback must be registered before calling the
+* power mode transition function. Refer to \ref group_syspm driver for more
+* information about power mode transitions and callback registration.
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the I2C slave is configured to be a wakeup
+* source from Deep Sleep mode, the \ref Cy_SCB_I2C_DeepSleepCallback must be
+* copied and modified. Refer to the function description to get the details.
+*
+* \section group_scb_i2c_more_information More Information
+* For more information on the SCB peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_scb_i2c_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>The functions \ref Cy_SCB_I2C_DeepSleepCallback and
+* \ref Cy_SCB_I2C_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.</td>
+* </tr>
+* <tr>
+* <td>14.1</td>
+* <td>R</td>
+* <td>There shall be no unreachable code.</td>
+* <td>The SCB block parameters can be a constant false or true depends on
+* the selected device and cause code to be unreachable.</td>
+* </tr>
+* <tr>
+* <td>13.7</td>
+* <td>R</td>
+* <td>Boolean operations whose results are invariant shall not be
+* permitted.</td>
+* <td>
+* * The SCB block parameters can be a constant false or true depends on
+* the selected device and cause this violation.
+* * The same condition check is executed before and after callback is
+* called because after the callback returns, the condition might be not
+* true any more.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is done to improve
+* code clarity when returning error status code if input parameters
+* validation fails.</td>
+* </tr>
+* </table>
+*
+* \section group_scb_i2c_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td rowspan="4"> 2.10</td>
+* <td>Fixed the ReStart condition generation sequence for a write
+* transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
+* <td>The driver can notify about a zero length write transaction completion
+* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
+* function execution was interrupted between setting the restart
+* generation command and writing the address byte into the TX FIFO.</td>
+* </tr>
+* <tr>
+* <td>Added the slave- and master-specific interrupt functions:
+* \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
+* </td>
+* <td>Improved the interrupt configuration options for the I2C slave and
+* master mode configurations.</td>
+* </tr>
+* <tr>
+* <td>Updated the Start condition generation sequence in the \ref
+* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Updated the ReStart condition generation sequence for a write
+* transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td rowspan="5"> 2.0</td>
+* <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
+* generate the ReStart condition when the previous transaction was
+* a write.</td>
+* <td>The master interpreted the address byte written into the TX FIFO as a
+* data byte and continued a write transaction. The ReStart condition was
+* generated after the master completed transferring the data byte.
+* The SCL line was stretched by the master waiting for the address byte
+* to be written into the TX FIFO after the ReStart condition generation.
+* The following timeout detection released the bus from the master
+* control.</td>
+* </tr>
+* <tr>
+* <td>Fixed the slave operation after the address byte was NACKed by the
+* firmware.</td>
+* <td>The observed slave operation failure depends on whether Level 2 assert
+* is enabled or not. Enabled: the device stuck in the fault handler due
+* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
+* the slave sets the transaction completion status and notifies on the
+* transaction completion event after the address was NACKed. The failure
+* is observed only when the slave is configured to accept an address in
+* the RX FIFO.</td>
+* </tr>
+* <tr>
+* <td>Added parameters validation for public API.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Replaced variables which have limited range of values with enumerated
+* types.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added missing "cy_cb_" to the callback function type names.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_scb_i2c_macros Macros
+* \defgroup group_scb_i2c_functions Functions
+* \{
+* \defgroup group_scb_i2c_general_functions General
+* \defgroup group_scb_i2c_slave_functions Slave
+* \defgroup group_scb_i2c_master_high_level_functions Master High-Level
+* \defgroup group_scb_i2c_master_low_level_functions Master Low-Level
+* \defgroup group_scb_i2c_interrupt_functions Interrupt
+* \defgroup group_scb_i2c_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_i2c_data_structures Data Structures
+* \defgroup group_scb_i2c_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_I2C_H)
+#define CY_SCB_I2C_H
+
+#include "cy_scb_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_scb_i2c_enums
+* \{
+*/
+
+/** I2C status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_I2C_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_I2C_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 1U),
+
+ /**
+ * The master is not ready to start a new transaction.
+ * Either the master is still processing a previous transaction or in the
+ * master-slave mode, the slave operation is in progress. Call this function
+ * again after that operation is completed or aborted.
+ */
+ CY_SCB_I2C_MASTER_NOT_READY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 2U),
+
+ /**
+ * The master operation timed out before completing. Applicable only for
+ * the \ref group_scb_i2c_master_low_level_functions functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_TIMEOUT = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 3U),
+
+ /** The slave NACKed the address. Applicable only for the
+ * \ref group_scb_i2c_master_low_level_functions functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 4U),
+
+ /** The slave NACKed the data byte. Applicable only for the
+ * \ref group_scb_i2c_master_low_level_functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_NAK = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 5U),
+
+ /**
+ * The master lost arbitration, the transaction was aborted. Applicable only
+ * for the \ref group_scb_i2c_master_low_level_functions functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_ARB_LOST = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 6U),
+
+ /**
+ * The master detected an erroneous start or stop, the transaction was
+ * aborted. Applicable only for the
+ * \ref group_scb_i2c_master_low_level_functions functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_BUS_ERR = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 7U),
+
+ /**
+ * The master transaction was aborted and the slave transaction is on-going
+ * because the slave was addressed before the master generated a start.
+ * Applicable only for the \ref group_scb_i2c_master_low_level_functions
+ * functions.
+ */
+ CY_SCB_I2C_MASTER_MANUAL_ABORT_START = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 8U)
+} cy_en_scb_i2c_status_t;
+
+/** I2C Operation Modes */
+typedef enum
+{
+ CY_SCB_I2C_SLAVE = 1U, /**< Configures SCB for I2C Slave operation */
+ CY_SCB_I2C_MASTER = 2U, /**< Configures SCB for I2C Master operation */
+ CY_SCB_I2C_MASTER_SLAVE = 3U, /**< Configures SCB for I2C Master-Slave operation */
+} cy_en_scb_i2c_mode_t;
+
+/** I2C Transaction Direction */
+typedef enum
+{
+ CY_SCB_I2C_WRITE_XFER = 0U, /**< Current transaction is Write */
+ CY_SCB_I2C_READ_XFER = 1U, /**< Current transaction is Read */
+} cy_en_scb_i2c_direction_t;
+
+/** I2C Command ACK / NAK */
+typedef enum
+{
+ CY_SCB_I2C_ACK, /**< Send ACK to current byte */
+ CY_SCB_I2C_NAK, /**< Send NAK to current byte */
+} cy_en_scb_i2c_command_t;
+/** \} group_scb_i2c_enums */
+
+
+/***************************************
+* Type Definitions
+***************************************/
+
+/**
+* \addtogroup group_scb_i2c_data_structures
+* \{
+*/
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of
+* \ref group_scb_i2c_macros_callback_events.
+*/
+typedef void (* cy_cb_scb_i2c_handle_events_t)(uint32_t event);
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of
+* \ref group_scb_i2c_macros_addr_callback_events.
+* This callback must return a decision to ACK (continue transaction) or
+* NAK (end transaction) the received address.
+* Note if the slave is configured to accept an address in RX FIFO, it must read
+* from it using the \ref Cy_SCB_ReadRxFifo function.
+*/
+typedef cy_en_scb_i2c_command_t (* cy_cb_scb_i2c_handle_addr_t)(uint32_t event);
+
+/** I2C configuration structure */
+typedef struct cy_stc_scb_i2c_config
+{
+ /** Specifies the mode of operation */
+ cy_en_scb_i2c_mode_t i2cMode;
+
+ /**
+ * The SCB provides an RX FIFO in hardware (consult the selected device
+ * datasheet to get the actual FIFO size). The useRxFifo field defines
+ * how the driver firmware reads data from the RX FIFO:
+ * * If this option is enabled, the hardware is configured to automatically
+ * ACK incoming data, and interrupt is enabled to take data out of the RX
+ * FIFO when it has some number of bytes (typically, when it is half full).
+ * * If this option is disabled, the interrupt is enabled to take data out of
+ * the RX FIFO when a byte is available. Also, hardware does not
+ * automatically ACK the data. Firmware must tell the hardware to ACK
+ * the byte (so each byte requires interrupt processing).
+ * \n <b>Typically, this option should be enabled</b> to configure hardware to
+ * automatically ACK incoming data. Otherwise hardware might not get the command
+ * to ACK or NACK a byte fast enough, and clock stretching is applied
+ * (the transaction is delayed) until the command is set. When this option is
+ * enabled, the number of interrupts required to process the transaction
+ * is significantly reduced because several bytes are handled at once.
+ * \n <b>However, there is a side effect:</b>
+ * * For master mode, the drawback is that the master may receive more
+ * data than desired due to the interrupt latency. An interrupt fires
+ * when the second-to-last byte has been received. This interrupt tells
+ * the hardware to stop receiving data. If the latency of this interrupt
+ * is longer than one transaction of the byte on the I2C bus, then the
+ * hardware automatically ACKs the following bytes until the interrupt
+ * is serviced or the RX FIFO becomes full.
+ * * For slave mode, the drawback is that the slave only NACKs
+ * the master when the RX FIFO becomes full, NOT when the slave write
+ * firmware buffer becomes full.
+ * \n In either master or slave mode, all received extra bytes are dropped.
+ * \note The useRxFifo option is not available if acceptAddrInFifo is true.
+ */
+ bool useRxFifo;
+
+ /**
+ * The SCB provides a TX FIFO in hardware (consult the selected device
+ * datasheet to get the actual FIFO size). The useTxFifo option defines how the
+ * driver firmware loads data into the TX FIFO:
+ * * If this option is enabled, the TX FIFO is fully loaded with data and the
+ * interrupt is enabled to keep the TX FIFO loaded until the end of the transaction.
+ * * If this option is disabled, a single byte is loaded into the TX FIFO and
+ * the interrupt enabled to load the next byte when the TX FIFO becomes empty
+ * (so each byte requires interrupt processing).
+ * \n <b>Typically, this option should be enabled</b> to keep the TX FIFO loaded with
+ * data and reduce the probability of clock stretching. When there is no data
+ * to transaction, clock stretching is applied (the transaction is delayed) until
+ * the data is loaded. When this option is enabled, the number of interrupts required
+ * to process the transaction is significantly reduced because several
+ * bytes are handled at once.
+ * \n <b>The drawback of enabling useTxFifo</b> is that the abort operation clears
+ * the TX FIFO. The TX FIFO clear operation also clears the shift
+ * register. As a result the shifter may be cleared in the middle of a byte
+ * transaction, corrupting it. The remaining bits to transaction within the
+ * corrupted byte are complemented with 1s. If this is an issue,
+ * then do not enable this option.
+ */
+ bool useTxFifo;
+
+ /**
+ * The 7-bit right justified slave address, used only for the slave mode
+ */
+ uint8_t slaveAddress;
+
+ /**
+ * The slave address mask, bit 0, must always be 0. It is used only for the
+ * slave mode
+ */
+ uint8_t slaveAddressMask;
+
+ /**
+ * True - the slave address is accepted in the RX FIFO, false - the slave
+ * addresses are not accepted in the RX FIFO
+ */
+ bool acceptAddrInFifo;
+
+ /**
+ * True - accept the general call address; false - ignore the general
+ * call address.
+ */
+ bool ackGeneralAddr;
+
+ /**
+ * When set, the slave will wake the device from Deep Sleep on an address
+ * match (the device datasheet must be consulted to determine which SCBs
+ * support this mode)
+ */
+ bool enableWakeFromSleep;
+} cy_stc_scb_i2c_config_t;
+
+/** I2C context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_i2c_context
+{
+ /** \cond INTERNAL */
+ bool useRxFifo; /**< Stores RX FIFO configuration */
+ bool useTxFifo; /**< Stores TX FIFO configuration */
+
+ volatile uint32_t state; /**< The driver state */
+
+ volatile uint32_t masterStatus; /**< The master status */
+ bool masterPause; /**< Stores how the master ends the transaction */
+ bool masterRdDir; /**< The direction of the master transaction */
+
+ uint8_t *masterBuffer; /**< The pointer to the master buffer (either for a transmit or a receive operation) */
+ uint32_t masterBufferSize; /**< The current master buffer size */
+ volatile uint32_t masterBufferIdx; /**< The current location in the master buffer */
+ volatile uint32_t masterNumBytes; /**< The number of bytes to send or receive */
+
+ volatile uint32_t slaveStatus; /**< The slave status */
+ volatile bool slaveRdBufEmpty; /**< Tracks slave Read buffer empty event */
+
+ uint8_t *slaveTxBuffer; /**< The pointer to the slave transmit buffer (a master reads from it) */
+ uint32_t slaveTxBufferSize; /**< The current slave transmit buffer size */
+ volatile uint32_t slaveTxBufferIdx; /**< The current location in the slave buffer */
+ volatile uint32_t slaveTxBufferCnt; /**< The number of transferred bytes */
+
+ uint8_t *slaveRxBuffer; /**< The pointer to the slave receive buffer (a master writes into it) */
+ uint32_t slaveRxBufferSize; /**< The current slave receive buffer size */
+ volatile uint32_t slaveRxBufferIdx; /**< The current location in the slave buffer */
+
+ /**
+ * The pointer to an event callback that is called when any of
+ * \ref group_scb_i2c_macros_callback_events occurs
+ */
+ cy_cb_scb_i2c_handle_events_t cbEvents;
+
+ /**
+ * The pointer to an address callback that is called when any of
+ * \ref group_scb_i2c_macros_addr_callback_events occurs (applicable only
+ * for the slave)
+ */
+ cy_cb_scb_i2c_handle_addr_t cbAddr;
+
+ /** \endcond */
+} cy_stc_scb_i2c_context_t;
+
+/** The I2C Master transfer structure */
+typedef struct cy_stc_scb_i2c_master_xfer_config
+{
+ /** The 7-bit right justified slave address to communicate with */
+ uint8_t slaveAddress;
+
+ /**
+ * The pointer to the buffer for data to read from the slave or with
+ * data to write into the slave
+ */
+ uint8_t *buffer;
+
+ /** The size of the buffer */
+ uint32_t bufferSize;
+
+ /**
+ * The transfer operation is pending - the stop condition will not
+ * be generated
+ */
+ bool xferPending;
+} cy_stc_scb_i2c_master_xfer_config_t;
+/** \} group_scb_i2c_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_scb_i2c_general_functions
+* \{
+*/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config,
+ cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_DeInit(CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base);
+void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+
+uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t scbClockHz);
+uint32_t Cy_SCB_I2C_GetDataRate(CySCB_Type const *base, uint32_t scbClockHz);
+
+__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress(CySCB_Type *base, uint8_t addr);
+__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask);
+__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle (CySCB_Type *base, uint32_t clockCycles);
+__STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles);
+
+__STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy(CySCB_Type const *base);
+/** \} group_scb_i2c_general_functions */
+
+/**
+* \addtogroup group_scb_i2c_slave_functions
+* \{
+*/
+void Cy_SCB_I2C_SlaveConfigReadBuf (CySCB_Type const *base, uint8_t *buffer, uint32_t size,
+ cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_SlaveAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_SlaveConfigWriteBuf(CySCB_Type const *base, uint8_t *buffer, uint32_t size,
+ cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_SlaveAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+
+uint32_t Cy_SCB_I2C_SlaveGetStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
+uint32_t Cy_SCB_I2C_SlaveClearReadStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t *context);
+uint32_t Cy_SCB_I2C_SlaveClearWriteStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context);
+
+uint32_t Cy_SCB_I2C_SlaveGetReadTransferCount (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
+uint32_t Cy_SCB_I2C_SlaveGetWriteTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
+/** \} group_scb_i2c_slave_functions */
+
+/**
+* \addtogroup group_scb_i2c_master_high_level_functions
+* \{
+*/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t *xferConfig,
+ cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_MasterAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead (CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t* xferConfig,
+ cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_MasterAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+uint32_t Cy_SCB_I2C_MasterGetStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
+uint32_t Cy_SCB_I2C_MasterGetTransferCount (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
+/** \} group_scb_i2c_master_low_high_functions */
+
+/**
+* \addtogroup group_scb_i2c_master_low_level_functions
+* \{
+*/
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStart (CySCB_Type *base, uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
+ uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base, uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
+ uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStop (CySCB_Type *base,uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterReadByte (CySCB_Type *base, cy_en_scb_i2c_command_t ackNack, uint8_t *byte,
+ uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
+cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte (CySCB_Type *base, uint8_t byte, uint32_t timeoutMs,
+ cy_stc_scb_i2c_context_t *context);
+/** \} group_scb_i2c_master_low_level_functions */
+
+/**
+* \addtogroup group_scb_i2c_interrupt_functions
+* \{
+*/
+void Cy_SCB_I2C_Interrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_SlaveInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+void Cy_SCB_I2C_MasterInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, cy_cb_scb_i2c_handle_events_t callback,
+ cy_stc_scb_i2c_context_t *context);
+__STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback (CySCB_Type const *base, cy_cb_scb_i2c_handle_addr_t callback,
+ cy_stc_scb_i2c_context_t *context);
+/** \} group_scb_i2c_interrupt_functions */
+
+/**
+* \addtogroup group_scb_i2c_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_I2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_scb_i2c_low_power_functions */
+
+
+/***************************************
+* API Constants
+***************************************/
+
+/**
+* \addtogroup group_scb_i2c_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_i2c_macros_slave_status I2C Slave Status
+* Each I2C slave status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+* \{
+*/
+/** There is a read transaction in progress */
+#define CY_SCB_I2C_SLAVE_RD_BUSY (0x00000001UL)
+
+/**
+* All read data has been loaded into the TX FIFO, applicable only if
+* the TX FIFO is used
+*/
+#define CY_SCB_I2C_SLAVE_RD_IN_FIFO (0x00000002UL)
+
+/**
+* The master has finished reading data from the slave
+*/
+#define CY_SCB_I2C_SLAVE_RD_CMPLT (0x00000004UL)
+
+/**
+* Set when the master tried to read more bytes than available in the configured
+* read buffer. The slave is not able to finish the transaction and sends
+* \ref CY_SCB_I2C_DEFAULT_TX.
+*/
+#define CY_SCB_I2C_SLAVE_RD_UNDRFL (0x00000008UL)
+
+/** There is a write transaction in progress */
+#define CY_SCB_I2C_SLAVE_WR_BUSY (0x00000010UL)
+
+/**
+* The master has finished writing data into the slave
+*/
+#define CY_SCB_I2C_SLAVE_WR_CMPLT (0x00000020UL)
+
+/**
+* The master attempted to write more bytes than space available in the
+* configured Write buffer. Note that all subsequent bytes are dropped.
+*/
+#define CY_SCB_I2C_SLAVE_WR_OVRFL (0x00000040UL)
+
+/** The slave lost arbitration, and the transaction was aborted */
+#define CY_SCB_I2C_SLAVE_ARB_LOST (0x00000080UL)
+
+/**
+* The slave captured an error on the bus during a master transaction (source
+* of error is misplaced Start or Stop).
+*/
+#define CY_SCB_I2C_SLAVE_BUS_ERR (0x00000100UL)
+/** \} group_scb_i2c_macros_slave_status */
+
+/**
+* \defgroup group_scb_i2c_macros_master_status I2C Master Status
+* Each I2C master status is encoded in a separate bit, therefore multiple
+* bits may be set to indicate the current status.
+* \{
+*/
+
+/**
+* The master is busy executing operation started by \ref Cy_SCB_I2C_MasterRead
+* or \ref Cy_SCB_I2C_MasterWrite
+*/
+#define CY_SCB_I2C_MASTER_BUSY (0x00010000UL)
+
+/**
+* All Write data has been loaded into the TX FIFO
+*/
+#define CY_SCB_I2C_MASTER_WR_IN_FIFO (0x00020000UL)
+
+/** The slave NACKed the address. */
+#define CY_SCB_I2C_MASTER_ADDR_NAK (0x00100000UL)
+
+/** Write completed before all bytes were sent (last byte was NAKed)
+*/
+#define CY_SCB_I2C_MASTER_DATA_NAK (0x00200000UL)
+
+/** The master lost arbitration, the transaction was aborted */
+#define CY_SCB_I2C_MASTER_ARB_LOST (0x00400000UL)
+
+/**
+* The master detected an erroneous start or stop, the transaction was aborted
+*/
+#define CY_SCB_I2C_MASTER_BUS_ERR (0x00800000UL)
+
+/**
+* The master transaction was aborted and the slave transaction is on-going
+* because the slave was addressed before the master generated a start
+*/
+#define CY_SCB_I2C_MASTER_ABORT_START (0x01000000UL)
+/** \} group_scb_i2c_macros_master_status */
+
+/**
+* \defgroup group_scb_i2c_macros_callback_events I2C Callback Events
+* \{
+* Each event is encoded in a separate bit, and therefore it is possible to
+* notify about multiple events.
+*/
+/**
+* Indicates that the slave was addressed and the master wants to read data.
+* This event can be used to configure the slave Read buffer.
+*/
+#define CY_SCB_I2C_SLAVE_READ_EVENT (0x00000001UL)
+
+/**
+* Indicates that the slave was addressed and the master wants to write data.
+* This event can be used to configure the slave Write buffer.
+*/
+#define CY_SCB_I2C_SLAVE_WRITE_EVENT (0x00000002UL)
+
+/**
+* All slave data from the configured Read buffer has been loaded into the
+* TX FIFO. The content of the Read buffer can be modified. Applicable only
+* if the TX FIFO is used.
+*/
+#define CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT (0x00000004UL)
+
+/**
+* The master has read all data out of the configured Read buffer.
+* This event can be used to configure the next Read buffer. If the buffer
+* remains empty, the \ref CY_SCB_I2C_DEFAULT_TX bytes are returned to the master.
+*/
+#define CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT (0x00000008UL)
+
+/**
+* Indicates the master completed reading from the slave (set by the master NAK
+* or Stop)
+*/
+#define CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT (0x00000010UL)
+
+/**
+* Indicates the master completed writing to the slave (set by the master Stop
+* or Restart)
+*/
+#define CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT (0x00000020UL)
+
+/**
+* Indicates the I2C hardware detected an error.
+* Check \ref Cy_SCB_I2C_SlaveGetStatus to determine the source of the error.
+*/
+#define CY_SCB_I2C_SLAVE_ERR_EVENT (0x00000040UL)
+
+/**
+* All data specified by \ref Cy_SCB_I2C_MasterWrite have been loaded
+* into the TX FIFO. The content of the master buffer can be modified.
+* Applicable only if the TX FIFO is used.
+*/
+#define CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT (0x00010000UL)
+
+/** The master write started by \ref Cy_SCB_I2C_MasterWrite is complete */
+#define CY_SCB_I2C_MASTER_WR_CMPLT_EVENT (0x00020000UL)
+
+/** The master read started by \ref Cy_SCB_I2C_MasterRead is complete */
+#define CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL)
+
+/**
+* Indicates the I2C hardware has detected an error. It occurs together with
+* \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT
+* depends on the direction of the transfer.
+* Check \ref Cy_SCB_I2C_MasterGetStatus to determine the source of the error.
+*/
+#define CY_SCB_I2C_MASTER_ERR_EVENT (0x00080000UL)
+/** \} group_scb_i2c_macros_callback_events */
+
+/**
+* \defgroup group_scb_i2c_macros_addr_callback_events I2C Address Callback Events
+* Each event is encoded in a separate bit and therefore it is possible to
+* notify about multiple events.
+* \{
+*/
+/**
+* Indicates the slave was addressed by the general call address
+*/
+#define CY_SCB_I2C_GENERAL_CALL_EVENT (0x01UL)
+
+/**
+* The slave address is in the RX FIFO.
+* Note that the address must be read from the RX FIFO using the
+* \ref Cy_SCB_ReadRxFifo function.
+*/
+#define CY_SCB_I2C_ADDR_IN_FIFO_EVENT (0x02UL)
+/** \} group_scb_i2c_macros_addr_callback_events */
+
+/**
+* This value is returned by the slave when there is no data in the
+* Read buffer
+*/
+#define CY_SCB_I2C_DEFAULT_TX (0xFFUL)
+
+
+/***************************************
+* Internal Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+/* Slave statuses */
+#define CY_SCB_I2C_SLAVE_RD_CLEAR (CY_SCB_I2C_SLAVE_RD_CMPLT | CY_SCB_I2C_SLAVE_RD_IN_FIFO | \
+ CY_SCB_I2C_SLAVE_RD_UNDRFL | CY_SCB_I2C_SLAVE_ARB_LOST | \
+ CY_SCB_I2C_SLAVE_BUS_ERR)
+
+#define CY_SCB_I2C_SLAVE_WR_CLEAR (CY_SCB_I2C_SLAVE_WR_CMPLT | CY_SCB_I2C_SLAVE_WR_OVRFL | \
+ CY_SCB_I2C_SLAVE_ARB_LOST | CY_SCB_I2C_SLAVE_BUS_ERR)
+
+/* Master error statuses */
+#define CY_SCB_I2C_MASTER_ERR (CY_SCB_I2C_MASTER_ABORT_START | CY_SCB_I2C_MASTER_ADDR_NAK | \
+ CY_SCB_I2C_MASTER_DATA_NAK | CY_SCB_I2C_MASTER_BUS_ERR | \
+ CY_SCB_I2C_MASTER_ARB_LOST)
+
+/* Master interrupt masks */
+#define CY_SCB_I2C_MASTER_INTR (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_BUS_ERROR | \
+ CY_SCB_MASTER_INTR_I2C_NACK | CY_SCB_MASTER_INTR_I2C_STOP)
+
+#define CY_SCB_I2C_MASTER_INTR_ALL (CY_SCB_I2C_MASTER_INTR | CY_SCB_MASTER_INTR_I2C_ACK)
+
+#define CY_SCB_I2C_MASTER_INTR_ERR (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
+
+#define CY_SCB_I2C_MASTER_INTR_CMPLT (CY_SCB_I2C_MASTER_INTR_ERR | CY_SCB_MASTER_INTR_I2C_STOP)
+
+/* Master statuses. */
+#define CY_SCB_I2C_MASTER_TX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_NACK | \
+ CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
+
+#define CY_SCB_I2C_MASTER_RX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
+
+#define CY_SCB_I2C_MASTER_STOP_DONE (CY_SCB_MASTER_INTR_I2C_STOP | \
+ CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
+
+#define CY_SCB_I2C_MASTER_TIMEOUT_DONE (0x80000000UL)
+
+/* The slave interrupt mask */
+#define CY_SCB_I2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
+ CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | \
+ CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+
+#define CY_SCB_I2C_SLAVE_INTR_NO_STOP (CY_SCB_I2C_SLAVE_INTR & (uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP)
+
+#define CY_SCB_I2C_SLAVE_INTR_ADDR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR)
+
+#define CY_SCB_I2C_SLAVE_ADDR_DONE (CY_SCB_I2C_SLAVE_INTR_ADDR)
+
+#define CY_SCB_I2C_SLAVE_INTR_NO_ADDR (CY_SCB_I2C_SLAVE_INTR & (uint32_t) ~CY_SCB_I2C_SLAVE_INTR_ADDR)
+
+#define CY_SCB_I2C_SLAVE_INTR_TX (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW)
+
+#define CY_SCB_I2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
+
+/* I2C states */
+#define CY_SCB_I2C_IDLE (0x10000000UL)
+#define CY_SCB_I2C_IDLE_MASK (0x10000000UL)
+
+/* Master states */
+#define CY_SCB_I2C_MASTER_ACTIVE (0x00100000UL)
+#define CY_SCB_I2C_MASTER_WAIT (0x10100000UL)
+#define CY_SCB_I2C_MASTER_RX0 (0x00110000UL)
+#define CY_SCB_I2C_MASTER_RX1 (0x00120000UL)
+#define CY_SCB_I2C_MASTER_ADDR (0x10130000UL)
+#define CY_SCB_I2C_MASTER_TX (0x00140000UL)
+#define CY_SCB_I2C_MASTER_TX_DONE (0x00150000UL)
+#define CY_SCB_I2C_MASTER_STOP (0x00160000UL)
+#define CY_SCB_I2C_MASTER_WAIT_STOP (0x00170000UL)
+#define CY_SCB_I2C_MASTER_CMPLT (0x00180000UL)
+
+/* Slave states */
+#define CY_SCB_I2C_SLAVE_ACTIVE (0x00001000UL)
+#define CY_SCB_I2C_SLAVE_RX_MASK (0x00001001UL)
+#define CY_SCB_I2C_SLAVE_RX (0x00001001UL)
+#define CY_SCB_I2C_SLAVE_TX (0x00001002UL)
+
+/* FIFO size */
+#define CY_SCB_I2C_FIFO_SIZE(base) CY_SCB_FIFO_SIZE(base)
+#define CY_SCB_I2C_HALF_FIFO_SIZE(base) (CY_SCB_FIFO_SIZE(base) / 2UL)
+
+#define CY_SCB_I2C_DEFAULT_RETURN (0xFFUL)
+
+/* Convert the timeout in milliseconds to microseconds */
+#define CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs) ((timeoutMs) * 1000UL)
+
+/* I2C data rates max (Hz): standard, fast and fast plus modes */
+#define CY_SCB_I2C_STD_DATA_RATE (100000U)
+#define CY_SCB_I2C_FST_DATA_RATE (400000U)
+#define CY_SCB_I2C_FSTP_DATA_RATE (1000000U)
+
+/* Slave clock limits */
+#define CY_SCB_I2C_SLAVE_STD_CLK_MIN (1550000U)
+#define CY_SCB_I2C_SLAVE_STD_CLK_MAX (12800000U)
+#define CY_SCB_I2C_SLAVE_FST_CLK_MIN (7820000U)
+#define CY_SCB_I2C_SLAVE_FST_CLK_MAX (15380000U)
+#define CY_SCB_I2C_SLAVE_FSTP_CLK_MIN (15840000U)
+#define CY_SCB_I2C_SLAVE_FSTP_CLK_MAX (89000000U)
+
+/* Master clock (Hz) and duty cycle limits for standard mode */
+#define CY_SCB_I2C_MASTER_STD_CLK_MIN (1550000U)
+#define CY_SCB_I2C_MASTER_STD_CLK_MAX (3200000U)
+#define CY_SCB_I2C_MASTER_STD_LOW_PHASE_MIN (8U)
+#define CY_SCB_I2C_MASTER_STD_HIGH_PHASE_MIN (8U)
+
+/* Master clock (Hz) and duty cycle limits for fast mode */
+#define CY_SCB_I2C_MASTER_FST_CLK_MIN (7820000U)
+#define CY_SCB_I2C_MASTER_FST_CLK_MAX (10000000U)
+#define CY_SCB_I2C_MASTER_FST_LOW_PHASE_MIN (13U)
+#define CY_SCB_I2C_MASTER_FST_HIGH_PHASE_MIN (8U)
+
+/* Master clock (Hz) and duty cycle limits for fast plus mode */
+#define CY_SCB_I2C_MASTER_FSTP_CLK_MIN (14320000U)
+#define CY_SCB_I2C_MASTER_FSTP_CLK_MAX (25800000U)
+#define CY_SCB_I2C_MASTER_FSTP_LOW_PHASE_MIN (9U)
+#define CY_SCB_I2C_MASTER_FSTP_HIGH_PHASE_MIN (6U)
+
+/* SCL low and high time in ns. Takes into account tF and tR */
+#define CY_SCB_I2C_MASTER_STD_SCL_LOW (5000U) /* tLOW + tF = 4700 + 300 */
+#define CY_SCB_I2C_MASTER_STD_SCL_HIGH (5000U) /* tHIGH + tR = 4000 + 1000 */
+#define CY_SCB_I2C_MASTER_FST_SCL_LOW (1600U) /* tLOW + tF = 1300 + 300 */
+#define CY_SCB_I2C_MASTER_FST_SCL_HIGH (900U) /* tHIGH + tR = 600 + 300 */
+#define CY_SCB_I2C_MASTER_FSTP_SCL_LOW (620U) /* tLOW + tF = 500 + 120 */
+#define CY_SCB_I2C_MASTER_FSTP_SCL_HIGH (380U) /* tHIGH + tR = 260 + 120 */
+
+/* Master duty cycle limits */
+#define CY_SCB_I2C_LOW_PHASE_MAX (16U)
+#define CY_SCB_I2C_HIGH_PHASE_MAX (16U)
+#define CY_SCB_I2C_DUTY_CYCLE_MAX (CY_SCB_I2C_LOW_PHASE_MAX + CY_SCB_I2C_HIGH_PHASE_MAX)
+
+/* Analog filter settings. */
+#define CY_SCB_I2C_ENABLE_ANALOG_FITLER (CY_SCB_I2C_CFG_DEF_VAL)
+#define CY_SCB_I2C_DISABLE_ANALOG_FITLER (CY_SCB_I2C_CFG_DEF_VAL & \
+ (uint32_t) ~(SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk | \
+ SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk))
+
+#define CY_SCB_I2C_IS_MODE_VALID(mode) ( (CY_SCB_I2C_SLAVE == (mode)) || \
+ (CY_SCB_I2C_MASTER == (mode)) || \
+ (CY_SCB_I2C_MASTER_SLAVE == (mode)) )
+
+#define CY_SCB_I2C_IS_RW_BIT_VALID(dir) ( (CY_SCB_I2C_WRITE_XFER == (dir)) || \
+ (CY_SCB_I2C_READ_XFER == (dir)) )
+
+#define CY_SCB_I2C_IS_RESPONSE_VALID(cmd) ( (CY_SCB_I2C_ACK == (cmd)) || \
+ (CY_SCB_I2C_NAK == (cmd)) )
+
+#define CY_SCB_I2C_IS_ADDR_MASK_VALID(mask) ( (0U == ((mask) & 0x01U)) )
+
+#define CY_SCB_I2C_IS_DATA_RATE_VALID(dataRateHz) ( ((dataRateHz) > 0UL) && \
+ ((dataRateHz) <= CY_SCB_I2C_FSTP_DATA_RATE) )
+
+#define CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs) ( (timeoutMs) <= (0xFFFFFFFFUL / 1000UL) )
+#define CY_SCB_I2C_IS_LOW_PHASE_CYCLES_VALID(clockCycles) ( ((clockCycles) >= 7UL) && ((clockCycles) <= 16UL) )
+#define CY_SCB_I2C_IS_HIGH_PHASE_CYCLES_VALID(clockCycles) ( ((clockCycles) >= 5UL) && ((clockCycles) <= 16UL) )
+
+/** \endcond */
+
+/** \} group_scb_i2c_macros */
+
+
+/***************************************
+* In-line Function Implementation
+***************************************/
+
+/**
+* \addtogroup group_scb_i2c_general_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the I2C operation
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base)
+{
+ base->CTRL |= SCB_CTRL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_IsBusBusy
+****************************************************************************//**
+*
+* Checks whether the I2C bus is busy.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \return
+* A bus status: busy or not busy.
+*
+* \note
+* After the SCB block is enabled or reset, the valid bus busy-status returns
+* after half of the SCL period.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy(CySCB_Type const *base)
+{
+ return _FLD2BOOL(SCB_I2C_STATUS_BUS_BUSY, base->I2C_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveSetAddress
+****************************************************************************//**
+*
+* Sets the slave address for the I2C slave.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param addr
+* The 7-bit right justified slave address.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress(CySCB_Type *base, uint8_t addr)
+{
+ CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr));
+
+ base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveGetAddress
+****************************************************************************//**
+*
+* Returns the slave address of the I2C slave.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \return
+* The 7-bit right justified slave address.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const *base)
+{
+ return (_FLD2VAL(SCB_RX_MATCH_ADDR, base->RX_MATCH) >> 1UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveSetAddressMask
+****************************************************************************//**
+*
+* Sets the slave address mask for the I2C slave. The LSBit must always be 0.
+* In all other bit positions a 1 indicates that the incoming address must match
+* the corresponding bit in the slave address. A 0 in the mask means that the
+* incoming address does not need to match.
+* Example Slave Address = 0x0C. Slave Address Mask = 0x08. This means that the
+* hardware will accept both 0x08 and 0x0C as valid addresses.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param addrMask
+* The 8-bit address mask, the upper 7 bits correspond to the slave address.
+* LSBit must always be 0.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask)
+{
+ CY_ASSERT_L2(CY_SCB_I2C_IS_ADDR_MASK_VALID(addrMask));
+
+ base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_MASK, ((uint32_t) addrMask));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_SlaveGetAddressMask
+****************************************************************************//**
+*
+* Returns the slave address mask.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \return
+* The 8-bit address mask, the upper 7 bits correspond to the slave address.
+* LSBit must always be 0.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_RX_MATCH_MASK, base->RX_MATCH);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterSetLowPhaseDutyCycle
+****************************************************************************//**
+*
+* This function sets the number of SCB clock cycles in the low phase of SCL.
+* If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values
+* specified in this function are overwritten.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param clockCycles
+* The number of SCB clock cycles in the low phase of SCL.
+* The valid range is 7 to 16.
+*
+* \note
+* This function should be used at your own risk. Changing the number of clock
+* cycles in a phase of SCL may violate the I2C specification. Make this
+* change only while the block is disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles)
+{
+ CY_ASSERT_L2(CY_SCB_I2C_IS_LOW_PHASE_CYCLES_VALID(clockCycles));
+
+ base->I2C_CTRL = _CLR_SET_FLD32U(base->I2C_CTRL, SCB_I2C_CTRL_LOW_PHASE_OVS, (clockCycles - 1UL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_MasterSetHighPhaseDutyCycle
+****************************************************************************//**
+*
+* This function sets the number of SCB clock cycles in the high phase of SCL.
+* If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values
+* specified in this function get overwritten.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param clockCycles
+* The number of SCB clock cycles in the high phase of SCL.
+* The valid range is 5 to 16.
+*
+* \note
+* This function should be used at your own risk. Changing the number of clock
+* cycles in a phase of SCL may violate the I2C specification. Make this
+* change only while the block is disabled.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles)
+{
+ CY_ASSERT_L2(CY_SCB_I2C_IS_HIGH_PHASE_CYCLES_VALID(clockCycles));
+
+ base->I2C_CTRL = _CLR_SET_FLD32U(base->I2C_CTRL, SCB_I2C_CTRL_HIGH_PHASE_OVS, (clockCycles - 1UL));
+}
+/** \} group_scb_i2c_general_functions */
+
+/**
+* \addtogroup group_scb_i2c_interrupt_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_RegisterEventCallback
+****************************************************************************//**
+*
+* Registers a callback function that notifies that
+* \ref group_scb_i2c_macros_callback_events occurred in the
+* \ref Cy_SCB_I2C_Interrupt.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param callback
+* The pointer to a callback function.
+* See \ref cy_cb_scb_i2c_handle_events_t for the function prototype.
+*
+* \param context
+* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
+* the user. The structure is used while the I2C operation for internal
+* configuration and data retention. The user should not modify anything in
+* this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base,
+ cy_cb_scb_i2c_handle_events_t callback, cy_stc_scb_i2c_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->cbEvents = callback;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_I2C_RegisterAddrCallback
+****************************************************************************//**
+*
+* Registers a callback function that notifies that
+* \ref group_scb_i2c_macros_addr_callback_events occurred in the
+* \ref Cy_SCB_I2C_Interrupt.
+*
+* \param base
+* The pointer to the I2C SCB instance.
+*
+* \param callback
+* The pointer to a callback function.
+* See \ref cy_cb_scb_i2c_handle_addr_t for the function prototype.
+*
+* \param context
+* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
+* the user. The structure is used during the I2C operation for internal
+* configuration and data retention. The user should not modify anything in
+* this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to a callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback(CySCB_Type const *base,
+ cy_cb_scb_i2c_handle_addr_t callback, cy_stc_scb_i2c_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->cbAddr = callback;
+}
+/** \} group_scb_i2c_interrupt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_i2c */
+
+#endif /* (CY_SCB_I2C_H) */
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1037 @@
+/***************************************************************************//**
+* \file cy_scb_spi.c
+* \version 2.10
+*
+* Provides SPI API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_scb_spi.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Static functions */
+static void HandleTransmit(CySCB_Type *base, cy_stc_scb_spi_context_t *context);
+static void HandleReceive (CySCB_Type *base, cy_stc_scb_spi_context_t *context);
+static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size);
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Init
+****************************************************************************//**
+*
+* Initializes the SCB for SPI operation.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param config
+* The pointer to the configuration structure \ref cy_stc_scb_spi_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only SPI functions that do not require context will be used to pass NULL
+* as pointer to context.
+*
+* \return
+* \ref cy_en_scb_spi_status_t
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, cy_stc_scb_spi_context_t *context)
+{
+ /* Input parameters verification */
+ if ((NULL == base) || (NULL == config))
+ {
+ return CY_SCB_SPI_BAD_PARAM;
+ }
+
+ if ((config->spiMode == CY_SCB_SPI_SLAVE) && (!SCB_IS_SPI_SLAVE_CAPABLE(base)))
+ {
+ return CY_SCB_SPI_BAD_PARAM;
+ }
+
+ if ((config->spiMode == CY_SCB_SPI_MASTER) && (!SCB_IS_SPI_MASTER_CAPABLE(base)))
+ {
+ return CY_SCB_SPI_BAD_PARAM;
+ }
+
+ if ((config->enableWakeFromSleep) && (!SCB_IS_SPI_DS_CAPABLE(base)))
+ {
+ return CY_SCB_SPI_BAD_PARAM;
+ }
+
+ CY_ASSERT_L3(CY_SCB_SPI_IS_MODE_VALID (config->spiMode));
+ CY_ASSERT_L3(CY_SCB_SPI_IS_SUB_MODE_VALID (config->subMode));
+ CY_ASSERT_L3(CY_SCB_SPI_IS_SCLK_MODE_VALID(config->sclkMode));
+
+ CY_ASSERT_L2(CY_SCB_SPI_IS_OVERSAMPLE_VALID (config->oversample, config->spiMode));
+ CY_ASSERT_L2(CY_SCB_SPI_IS_SS_POLARITY_VALID(config->ssPolarity));
+ CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->rxDataWidth));
+ CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->txDataWidth));
+ CY_ASSERT_L2(CY_SCB_SPI_IS_BOTH_DATA_WIDTH_VALID(config->subMode, config->rxDataWidth, config->txDataWidth));
+
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_SPI_RX_INTR_MASK));
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_SPI_TX_INTR_MASK));
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->masterSlaveIntEnableMask, CY_SCB_SPI_MASTER_SLAVE_INTR_MASK));
+
+ uint32_t locSclkMode = CY_SCB_SPI_GetSclkMode(config->subMode, config->sclkMode);
+
+ bool byteMode = (config->rxDataWidth <= CY_SCB_BYTE_WIDTH) && (config->txDataWidth <= CY_SCB_BYTE_WIDTH);
+
+ /* Configure an SPI interface */
+ base->CTRL = _BOOL2FLD(SCB_CTRL_BYTE_MODE, byteMode) |
+ _BOOL2FLD(SCB_CTRL_EC_AM_MODE, config->enableWakeFromSleep) |
+ _VAL2FLD(SCB_CTRL_OVS, (config->oversample - 1UL)) |
+ _VAL2FLD(SCB_CTRL_MODE, CY_SCB_CTRL_MODE_SPI);
+
+ /* Configure SCB_CTRL.BYTE_MODE then verify levels */
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel));
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel));
+
+ base->SPI_CTRL = _BOOL2FLD(SCB_SPI_CTRL_SSEL_CONTINUOUS, (!config->enableTransferSeperation)) |
+ _BOOL2FLD(SCB_SPI_CTRL_SELECT_PRECEDE, (CY_SCB_SPI_TI_PRECEDES == config->subMode)) |
+ _BOOL2FLD(SCB_SPI_CTRL_LATE_MISO_SAMPLE, config->enableMisoLateSample) |
+ _BOOL2FLD(SCB_SPI_CTRL_SCLK_CONTINUOUS, config->enableFreeRunSclk) |
+ _BOOL2FLD(SCB_SPI_CTRL_MASTER_MODE, (CY_SCB_SPI_MASTER == config->spiMode)) |
+ _VAL2FLD(CY_SCB_SPI_CTRL_CLK_MODE, locSclkMode) |
+ _VAL2FLD(CY_SCB_SPI_CTRL_SSEL_POLARITY, config->ssPolarity) |
+ _VAL2FLD(SCB_SPI_CTRL_MODE, (uint32_t) config->subMode);
+
+ /* Configure the RX direction */
+ base->RX_CTRL = _BOOL2FLD(SCB_RX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _BOOL2FLD(SCB_RX_CTRL_MEDIAN, config->enableInputFilter) |
+ _VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, (config->rxDataWidth - 1UL));
+
+ base->RX_FIFO_CTRL = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel);
+
+ /* Configure the TX direction */
+ base->TX_CTRL = _BOOL2FLD(SCB_TX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, (config->txDataWidth - 1UL));
+
+ base->TX_FIFO_CTRL = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel);
+
+ /* Set up interrupt sources */
+ base->INTR_RX_MASK = (config->rxFifoIntEnableMask & CY_SCB_SPI_RX_INTR_MASK);
+ base->INTR_TX_MASK = (config->txFifoIntEnableMask & CY_SCB_SPI_TX_INTR_MASK);
+ base->INTR_M = (config->masterSlaveIntEnableMask & CY_SCB_SPI_MASTER_DONE);
+ base->INTR_S = (config->masterSlaveIntEnableMask & CY_SCB_SPI_SLAVE_ERR);
+ base->INTR_SPI_EC_MASK = 0UL;
+
+ /* Initialize the context */
+ if (NULL != context)
+ {
+ context->status = 0UL;
+
+ context->txBufIdx = 0UL;
+ context->rxBufIdx = 0UL;
+
+ context->cbEvents = NULL;
+
+ #if !defined(NDEBUG)
+ /* Put an initialization key into the initKey variable to verify
+ * context initialization in the transfer API.
+ */
+ context->initKey = CY_SCB_SPI_INIT_KEY;
+ #endif /* !(NDEBUG) */
+ }
+
+ return CY_SCB_SPI_SUCCESS;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_DeInit
+****************************************************************************//**
+*
+* De-initializes the SCB block; returns the register values to default.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_SPI_DeInit(CySCB_Type *base)
+{
+ /* SPI interface */
+ base->CTRL = CY_SCB_CTRL_DEF_VAL;
+ base->SPI_CTRL = CY_SCB_SPI_CTRL_DEF_VAL;
+
+ /* RX direction */
+ base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL;
+ base->RX_FIFO_CTRL = 0UL;
+
+ /* TX direction */
+ base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL;
+ base->TX_FIFO_CTRL = 0UL;
+
+ /* Disable all interrupt sources */
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+ base->INTR_S_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Disable
+****************************************************************************//**
+*
+* Disables the SCB block, clears context statuses, and disables
+* TX and RX interrupt sources.
+* Note that after the block is disabled, the TX and RX FIFOs and
+* hardware statuses are cleared. Also, the hardware stops driving the output
+* and ignores the input.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only SPI functions that do not require context will be used to pass NULL
+* as pointer to context.
+*
+* \note
+* Calling this function when the SPI is busy (master preforms data transfer or
+* slave communicates with the master) may cause transfer corruption because the
+* hardware stops driving the outputs and ignores the inputs.
+* Ensure that the SPI is not busy before calling this
+* function.
+*
+*******************************************************************************/
+void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
+{
+ base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ if (NULL != context)
+ {
+ context->status = 0UL;
+
+ context->rxBufIdx = 0UL;
+ context->txBufIdx = 0UL;
+ }
+
+ /* Disable RX and TX interrupt sources for the slave because
+ * RX overflow and TX underflow are kept enabled after the 1st call of
+ * Cy_SCB_SPI_Transfer().
+ */
+ if (!_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL))
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB SPI into and out of
+* Deep Sleep mode. It prevents the device from entering Deep Sleep mode
+* if the SPI slave or master is actively communicating, or there is any data
+* in the TX or RX FIFOs.
+* The following behavior of the SPI SCB depends on whether the SCB block is
+* wakeup-capable or not:
+* * The SCB is <b>wakeup-capable</b>: any transfer intended to the slave wakes up
+* the device from Deep Sleep mode. The slave responds with 0xFF to the transfer
+* and incoming data is ignored.
+* If the transfer occurs before the device enters Deep Sleep mode, the device
+* will not enter Deep Sleep mode and incoming data is stored in the RX FIFO.
+* The SCB clock is disabled before entering Deep Sleep and enabled after the
+* device exits Deep Sleep mode. The SCB clock must be enabled after exiting
+* Deep Sleep mode and after the source of hf_clk[0] gets stable, this includes
+* the FLL/PLL. The SysClk callback ensures that hf_clk[0] gets stable and
+* it must be called before Cy_SCB_SPI_DeepSleepCallback. The SCB clock
+* disabling may lead to corrupted data in the RX FIFO. Clear the RX FIFO
+* after this callback is executed. If the transfer occurs before the device
+* enters Deep Sleep mode, the device will not enter Deep Sleep mode and
+* incoming data will be stored in the RX FIFO. \n
+* Only the SPI slave can be configured to be a wakeup source from Deep Sleep
+* mode.
+* * The SCB is not <b>wakeup-capable</b>: the SPI is disabled. It is enabled when
+* the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep
+* mode. While the SPI is disabled, it stops driving the outputs and ignores the
+* inputs. Any incoming data is ignored.
+*
+* This function must be called during execution of \ref Cy_SysPm_DeepSleep.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the SPI slave is configured to be a wakeup source
+* from Deep Sleep mode, this function must be copied and modified by the user.
+* The SPI clock disable code must be inserted in the \ref CY_SYSPM_BEFORE_TRANSITION
+* and clock enable code in the \ref CY_SYSPM_AFTER_TRANSITION mode processing.
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_spi_context_t *locContext = (cy_stc_scb_spi_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check whether the High-level API is not busy executing the transfer
+ * operation.
+ */
+ if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext)))
+ {
+ /* If the SPI bus is not busy, all data elements are transferred
+ * on the bus from the TX FIFO and shifter and the RX FIFOs are
+ * empty - the SPI is ready to enter Deep Sleep mode.
+ */
+ if (!Cy_SCB_SPI_IsBusBusy(locBase))
+ {
+ if (Cy_SCB_SPI_IsTxComplete(locBase))
+ {
+ if (0UL == Cy_SCB_SPI_GetNumInRxFifo(locBase))
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: clear the SPI
+ * wakeup interrupt source because it triggers
+ * during Active mode communication and make
+ * sure that a new transfer is not started after
+ * clearing.
+ */
+ Cy_SCB_ClearSpiInterrupt(locBase, CY_SCB_SPI_INTR_WAKEUP);
+
+ if (!Cy_SCB_SPI_IsBusBusy(locBase))
+ {
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: disable the
+ * SPI. The master and slave stop driving the
+ * bus until the SPI is enabled. This happens
+ * when the device fails to enter Deep Sleep
+ * mode or it is awakened from Deep Sleep mode.
+ */
+ Cy_SCB_SPI_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ }
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Deep Sleep mode. Restore
+ * Active mode configuration.
+ */
+
+ if (!_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is NOT wakeup-capable: enable the SPI to operate */
+ Cy_SCB_SPI_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* This code executes inside the critical section and enabling the
+ * active interrupt source makes the interrupt pending in the NVIC.
+ * However, the interrupt processing is delayed until the code exits
+ * the critical section. The pending interrupt force WFI instruction
+ * does nothing and the device remains in Active mode.
+ */
+
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* The SCB is wakeup-capable: enable the SPI wakeup interrupt
+ * source. If any transaction happens, the wakeup interrupt
+ * becomes pending and prevents entering Deep Sleep mode.
+ */
+ Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
+
+ /* Disable SCB clock */
+ locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper entering Deep Sleep mode the SPI clock must be disabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, locBase->CTRL))
+ {
+ /* Enable SCB clock */
+ locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
+
+ /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
+ * for proper exiting Deep Sleep mode, the SPI clock must be enabled.
+ * This code must be inserted by the user because the driver
+ * does not have access to the clock.
+ */
+
+ /* The SCB is wakeup-capable: disable the SPI wakeup interrupt
+ * source
+ */
+ Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+ else
+ {
+ /* The SCB is NOT wakeup-capable: enable the SPI to operate */
+ Cy_SCB_SPI_Enable(locBase);
+ }
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB SPI into Hibernate mode.
+* It prevents the device from entering Hibernate mode if the SPI slave or
+* master is actively communicating, or there is any data in the TX or RX FIFOs.
+* If the SPI is ready to enter Hibernate mode, it is disabled. If the device
+* failed to enter Hibernate mode, the SPI is enabled. While the SPI is
+* disabled, it stops driving the outputs and ignores the inputs.
+* Any incoming data is ignored.
+*
+* This function must be called during execution of \ref Cy_SysPm_Hibernate.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_spi_context_t *locContext = (cy_stc_scb_spi_context_t *) callbackParams->context;
+
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check whether the High-level API is not busy executing the transfer
+ * operation.
+ */
+ if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & Cy_SCB_SPI_GetTransferStatus(locBase, locContext)))
+ {
+ /* If the SPI bus is not busy, all data elements are transferred
+ * on the bus from the TX FIFO and shifter and the RX FIFOs are
+ * empty - the SPI is ready to enter Hibernate mode.
+ */
+ if (!Cy_SCB_SPI_IsBusBusy(locBase))
+ {
+ if (Cy_SCB_SPI_IsTxComplete(locBase))
+ {
+ if (0UL == Cy_SCB_SPI_GetNumInRxFifo(locBase))
+ {
+ /* Disable the SPI. The master or slave stops
+ * driving the bus until the SPI is enabled.
+ * This happens if the device failed to enter
+ * Hibernate mode.
+ */
+ Cy_SCB_SPI_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Hibernate mode. Restore Active
+ * mode configuration.
+ */
+
+ /* Enable the SPI to operate */
+ Cy_SCB_SPI_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* The SCB is not capable of waking up from Hibernate mode:
+ * do nothing.
+ */
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/************************* High-Level Functions ********************************
+* The following functions are considered high-level. They provide the layer of
+* intelligence to the SCB. These functions require interrupts.
+* Low-level and high-level functions must not be mixed because low-level API
+* can adversely affect the operation of high-level functions.
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Transfer
+****************************************************************************//**
+*
+* This function starts an SPI transfer operation.
+* It configures transmit and receive buffers for an SPI transfer.
+* If the data that will be received is not important, pass NULL as rxBuffer.
+* If the data that will be transmitted is not important, pass NULL as txBuffer
+* and then the \ref CY_SCB_SPI_DEFAULT_TX is sent out as each data element.
+* Note that passing NULL as rxBuffer and txBuffer are considered invalid cases.
+*
+* After the function configures TX and RX interrupt sources, it returns and
+* \ref Cy_SCB_SPI_Interrupt manages further data transfer.
+*
+* * In the master mode, the transfer operation starts after calling this
+* function
+* * In the slave mode, the transfer registers and will start when
+* the master request arrives.
+*
+* When the transfer operation is completed (requested number of data elements
+* sent and received), the \ref CY_SCB_SPI_TRANSFER_ACTIVE status is cleared
+* and the \ref CY_SCB_SPI_TRANSFER_CMPLT_EVENT event is generated.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param txBuffer
+* The pointer of the buffer with data to transmit.
+* The item size is defined by the data type that depends on the configured
+* TX data width.
+*
+* \param rxBuffer
+* The pointer to the buffer to store received data.
+* The item size is defined by the data type that depends on the configured
+* RX data width.
+*
+* \param size
+* The number of data elements to transmit and receive.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_spi_status_t
+*
+* \note
+* * The buffers must not be modified and must stay allocated until the end of the
+* transfer.
+* * This function overrides all RX and TX FIFO interrupt sources and changes
+* the RX and TX FIFO level.
+*
+*******************************************************************************/
+cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, void *rxBuffer, uint32_t size,
+ cy_stc_scb_spi_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_SPI_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_SPI_IS_BUFFER_VALID(txBuffer, rxBuffer, size));
+
+ cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_TRANSFER_BUSY;
+
+ /* Check whether there are no active transfer requests */
+ if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & context->status))
+ {
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+
+ /* Set up the context */
+ context->status = CY_SCB_SPI_TRANSFER_ACTIVE;
+
+ context->txBuf = txBuffer;
+ context->txBufSize = size;
+ context->txBufIdx = 0UL;
+
+ context->rxBuf = rxBuffer;
+ context->rxBufSize = size;
+ context->rxBufIdx = 0UL;
+
+ /* Set the TX interrupt when half of FIFO was transmitted */
+ Cy_SCB_SetTxFifoLevel(base, fifoSize / 2UL);
+
+ if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL))
+ {
+ /* Trigger an RX interrupt:
+ * - If the transfer size is equal to or less than FIFO, trigger at the end of the transfer.
+ * - If the transfer size is greater than FIFO, trigger 1 byte earlier than the TX interrupt.
+ */
+ Cy_SCB_SetRxFifoLevel(base, (size > fifoSize) ? ((fifoSize / 2UL) - 2UL) : (size - 1UL));
+
+ Cy_SCB_SetMasterInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ /* Enable interrupt sources to perform a transfer */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+ else
+ {
+ /* Trigger an RX interrupt:
+ * - If the transfer size is equal to or less than half of FIFO, trigger ??at the end of the transfer.
+ * - If the transfer size is greater than half of FIFO, trigger 1 byte earlier than a TX interrupt.
+ */
+ Cy_SCB_SetRxFifoLevel(base, (size > (fifoSize / 2UL)) ? ((fifoSize / 2UL) - 2UL) : (size - 1UL));
+
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR);
+
+ /* Enable interrupt sources to perform a transfer */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW);
+ }
+
+ retStatus = CY_SCB_SPI_SUCCESS;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_AbortTransfer
+****************************************************************************//**
+*
+* Aborts the current SPI transfer.
+* It disables the transmit and RX interrupt sources, clears the TX
+* and RX FIFOs and the status.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* In the slave mode and after abort of transfer operation master continue
+* sending data it gets into RX FIFO and TX FIFO is underflow as there is
+* nothing to send. To drop this data, RX FIFO must be cleared when
+* the transfer is complete. Otherwise, received data will be kept and
+* copied to the buffer when \ref Cy_SCB_SPI_Transfer is called.
+*
+* \sideeffect
+* The transmit FIFO clear operation also clears the shift register, so that
+* the shifter can be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as "ones" on the bus.
+*
+*******************************************************************************/
+void Cy_SCB_SPI_AbortTransfer(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
+{
+ /* Disable interrupt sources */
+ Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL))
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+ else
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_OVERFLOW);
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW);
+ }
+
+ /* Clear FIFOs */
+ Cy_SCB_SPI_ClearTxFifo(base);
+ Cy_SCB_SPI_ClearRxFifo(base);
+
+ /* Clear the status to allow a new transfer */
+ context->status = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetNumTransfered
+****************************************************************************//**
+*
+* Returns the number of data elements transferred since the last call to \ref
+* Cy_SCB_SPI_Transfer.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements transferred.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_SPI_GetNumTransfered(CySCB_Type const *base, cy_stc_scb_spi_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->rxBufIdx);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetTransferStatus
+****************************************************************************//**
+*
+* Returns the status of the transfer operation started by
+* \ref Cy_SCB_SPI_Transfer.
+* This status is a bit mask and the value returned may have a multiple-bit set.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_spi_macros_xfer_status.
+*
+* \note
+* The status is cleared by calling \ref Cy_SCB_SPI_Transfer or
+* \ref Cy_SCB_SPI_AbortTransfer.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base, cy_stc_scb_spi_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Interrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in the SPI mode.
+* This function must be called inside the user-defined interrupt service
+* routine for \ref Cy_SCB_SPI_Transfer to work.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
+{
+ bool locXferErr = false;
+
+ /* Wake up on the slave select condition */
+ if (0UL != (CY_SCB_SPI_INTR_WAKEUP & Cy_SCB_GetSpiInterruptStatusMasked(base)))
+ {
+ Cy_SCB_ClearSpiInterrupt(base, CY_SCB_SPI_INTR_WAKEUP);
+ }
+
+ /* The slave error condition */
+ if (0UL != (CY_SCB_SLAVE_INTR_SPI_BUS_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base)))
+ {
+ locXferErr = true;
+ context->status |= CY_SCB_SPI_SLAVE_TRANSFER_ERR;
+
+ Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR);
+ }
+
+ /* The RX overflow error condition */
+ if (0UL != (CY_SCB_RX_INTR_OVERFLOW & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ locXferErr = true;
+ context->status |= CY_SCB_SPI_TRANSFER_OVERFLOW;
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_OVERFLOW);
+ }
+
+ /* The TX underflow error condition or slave complete data transfer */
+ if (0UL != (CY_SCB_TX_INTR_UNDERFLOW & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ locXferErr = true;
+ context->status |= CY_SCB_SPI_TRANSFER_UNDERFLOW;
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);
+ }
+
+ /* Report an error, use a callback */
+ if (locXferErr)
+ {
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_SPI_TRANSFER_ERR_EVENT);
+ }
+ }
+
+ /* RX direction */
+ if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ HandleReceive(base, context);
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+
+ /* TX direction */
+ if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ HandleTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ /* The transfer is complete: all data is loaded in the TX FIFO
+ * and all data is read from the RX FIFO
+ */
+ if ((0UL != (context->status & CY_SCB_SPI_TRANSFER_ACTIVE)) &&
+ (0UL == context->rxBufSize) && (0UL == context->txBufSize))
+ {
+ /* The transfer is complete */
+ context->status &= (uint32_t) ~CY_SCB_SPI_TRANSFER_ACTIVE;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_SPI_TRANSFER_CMPLT_EVENT);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleReceive
+****************************************************************************//**
+*
+* Reads data from RX FIFO into the buffer provided by \ref Cy_SCB_SPI_Transfer.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleReceive(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
+{
+ /* Get data in RX FIFO */
+ uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
+
+ /* Adjust the number to read */
+ if (numToCopy > context->rxBufSize)
+ {
+ numToCopy = context->rxBufSize;
+ }
+
+ /* Move the buffer */
+ context->rxBufIdx += numToCopy;
+ context->rxBufSize -= numToCopy;
+
+ /* Read data from RX FIFO */
+ if (NULL != context->rxBuf)
+ {
+ uint8_t *buf = (uint8_t *) context->rxBuf;
+
+ Cy_SCB_ReadArrayNoCheck(base, context->rxBuf, numToCopy);
+
+ buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numToCopy) : (2UL * numToCopy))];
+ context->rxBuf = (void *) buf;
+ }
+ else
+ {
+ /* Discard read data. */
+ DiscardArrayNoCheck(base, numToCopy);
+ }
+
+ if (0UL == context->rxBufSize)
+ {
+ /* Disable the RX level interrupt */
+ Cy_SCB_SetRxInterruptMask(base, (Cy_SCB_GetRxInterruptMask(base) & (uint32_t) ~CY_SCB_RX_INTR_LEVEL));
+ }
+ else
+ {
+ uint32_t level = (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) ?
+ Cy_SCB_GetFifoSize(base) : (Cy_SCB_GetFifoSize(base) / 2UL);
+
+ if (context->rxBufSize < level)
+ {
+ Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL));
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleTransmit
+****************************************************************************//**
+*
+* Loads TX FIFO with data provided by \ref Cy_SCB_SPI_Transfer.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleTransmit(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
+{
+ uint32_t numToCopy;
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+
+ numToCopy = fifoSize - Cy_SCB_GetNumInTxFifo(base);
+
+ /* Adjust the number to load */
+ if (numToCopy > context->txBufSize)
+ {
+ numToCopy = context->txBufSize;
+ }
+
+ /* Move the buffer */
+ context->txBufIdx += numToCopy;
+ context->txBufSize -= numToCopy;
+
+ /* Load TX FIFO with data */
+ if (NULL != context->txBuf)
+ {
+ uint8_t *buf = (uint8_t *) context->txBuf;
+
+ Cy_SCB_WriteArrayNoCheck(base, context->txBuf, numToCopy);
+
+ buf = &buf[(Cy_SCB_IsTxDataWidthByte(base) ? (numToCopy) : (2UL * numToCopy))];
+ context->txBuf = (void *) buf;
+ }
+ else
+ {
+ Cy_SCB_WriteDefaultArrayNoCheck(base, CY_SCB_SPI_DEFAULT_TX, numToCopy);
+ }
+
+ if (0UL == context->txBufSize)
+ {
+ /* Data is transferred into TX FIFO */
+ context->status |= CY_SCB_SPI_TRANSFER_IN_FIFO;
+
+ /* Disable the TX level interrupt */
+ Cy_SCB_SetTxInterruptMask(base, (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL));
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_SPI_TRANSFER_IN_FIFO_EVENT);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: DiscardArrayNoCheck
+****************************************************************************//**
+*
+* Reads the number of data elements from the SPI RX FIFO. The read data is
+* discarded. Before calling this function, make sure that RX FIFO has
+* enough data elements to read.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param size
+* The number of data elements to read.
+*
+*******************************************************************************/
+static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size)
+{
+ while (size > 0UL)
+ {
+ (void) Cy_SCB_SPI_Read(base);
+ --size;
+ }
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1543 @@
+/***************************************************************************//**
+* \file cy_scb_spi.h
+* \version 2.10
+*
+* Provides SPI API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_spi
+* \{
+* Driver API for SPI Bus Peripheral.
+*
+* Three different SPI protocols or modes are supported:
+* * The original SPI protocol as defined by Motorola.
+* * TI: Uses a short pulse on "spi_select" to indicate a start of transaction.
+* * National Semiconductor (Microwire): Transmissions and Receptions occur
+* separately.
+* In addition to the standard 8-bit word length, the component supports a
+* configurable 4- to 16-bit data width for communicating at non-standard SPI
+* data widths.
+*
+* \section group_scb_spi_configuration Configuration Considerations
+* The SPI driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_spi_config
+* * \ref group_scb_spi_pins
+* * \ref group_scb_spi_clock
+* * \ref group_scb_spi_data_rate
+* * \ref group_scb_spi_intr
+* * \ref group_scb_spi_enable
+*
+* \note
+* The SPI driver is built on top of the SCB hardware block. The SCB1 instance is
+* used as an example for all code snippets. Modify the code to match your
+* design.
+*
+* \subsection group_scb_spi_config Configure SPI
+* To set up the SPI slave driver, provide the configuration parameters in the
+* \ref cy_stc_scb_spi_config_t structure. For example: provide spiMode,
+* subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other
+* parameters are optional for operation. To initialize the driver, call
+* \ref Cy_SCB_SPI_Init function providing a pointer to the filled
+* \ref cy_stc_scb_spi_config_t structure and allocated \ref cy_stc_scb_spi_context_t.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG
+*
+* \subsection group_scb_spi_pins Assign and Configure Pins
+* Only dedicated SCB pins can be used for SPI operation. The HSIOM
+* register must be configured to connect block to the pins. Also the SPI output
+* pins must be configured in Strong Drive mode and SPI input pins in
+* Digital High-Z:
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_PINS
+*
+* \note
+* The SCB stops driving pins when it is disabled or enters low power mode (except
+* Alternate Active or Sleep). To keep the pins' states, they should be reconfigured or
+* be frozen.
+*
+* \subsection group_scb_spi_clock Assign Clock Divider
+* The clock source must be connected to the SCB block to oversample input and
+* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
+* source clock of this divider must be Clk_Peri)</b></em>. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_ASSIGN_CLOCK
+*
+* \subsection group_scb_spi_data_rate Configure Data Rate
+* To get the SPI slave to operate with the desired data rate, the source clock must be
+* fast enough to provide sufficient oversampling. Therefore, the clock divider
+* must be configured to provide desired clock frequency. Use the
+* \ref group_sysclk driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_DATA_RATE_SLAVE
+*
+* To get the SPI master to operate with the desired data rate, the source clock frequency
+* and the SCLK (SPI clock) period must be configured. Use the
+* \ref group_sysclk driver API to configure source clock frequency. Set the
+* <em><b>oversample parameter in configuration structure</b></em> to define number of SCB
+* clocks in one SCLK period. When this value is even, the first and second phases
+* of the SCLK period are the same. Otherwise, the first phase is one SCB clock
+* cycle longer than the second phase. The level of the first phase of the clock
+* period depends on CPOL settings: 0 - low level and 1 - high level.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_CFG_DATA_RATE_MASTER
+*
+* Refer to the technical reference manual (TRM) section SPI sub-section
+* Oversampling and Bit Rate to get information about how to configure SPI to run with
+* desired data rate.
+*
+* \subsection group_scb_spi_intr Configure Interrupt
+* The interrupt is optional for the SPI operation. To configure the interrupt,
+* the \ref Cy_SCB_SPI_Interrupt function must be called in the interrupt
+* handler for the selected SCB instance. Also, this interrupt must be enabled
+* in the NVIC.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_INTR_A
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_INTR_B
+*
+* \subsection group_scb_spi_enable Enable SPI
+* Finally, enable the SPI operation calling \ref Cy_SCB_SPI_Enable.
+* For the slave, this means that SPI device starts respond to the transfers.
+* For the master, it is ready to execute transfers.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_ENABLE
+*
+* \section group_scb_spi_use_cases Common Use Cases
+* The SPI API is the same for the master and slave mode operation and
+* is divided into two categories: \ref group_scb_spi_low_level_functions
+* and \ref group_scb_spi_high_level_functions. \n
+* <em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level
+* API can adversely affect the operation of a High-Level API.</em>
+*
+* \subsection group_scb_spi_ll Low-Level API
+* The \ref group_scb_spi_low_level_functions API allows
+* interacting directly with the hardware and do not use interrupt.
+* These functions do not require context for operation. Thus, NULL can be
+* passed in \ref Cy_SCB_SPI_Init and \ref Cy_SCB_SPI_Disable instead of
+* a pointer to the context structure.
+*
+* * To write data into the TX FIFO, use one of the provided functions:
+* \ref Cy_SCB_SPI_Write, \ref Cy_SCB_SPI_WriteArray or
+* \ref Cy_SCB_SPI_WriteArrayBlocking.
+* Note that in the master mode, putting data into the TX FIFO starts a
+* transfer. Due to the SPI nature, the received data is put into the RX FIFO.
+*
+* * To read data from the RX FIFO, use one of the provided functions:
+* \ref Cy_SCB_SPI_Read or \ref Cy_SCB_SPI_ReadArray.
+*
+* * The statuses can be polled using: \ref Cy_SCB_SPI_GetRxFifoStatus,
+* \ref Cy_SCB_SPI_GetTxFifoStatus and \ref Cy_SCB_SPI_GetSlaveMasterStatus.
+* <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status
+* is set, it must be cleared.</em> Note that there are statuses evaluated as level.
+* These statuses remain set until an event is true. Therefore, after the clear
+* operation, the status is cleared but then it is restored (if the event is still
+* true).
+* For example: the TX FIFO empty interrupt source can be cleared when the
+* TX FIFO is not empty. Put at least two data elements (one goes to the
+* shifter and next to FIFO) before clearing this status. \n
+* Also, following functions can be used for polling as well
+* \ref Cy_SCB_SPI_IsBusBusy, \ref Cy_SCB_SPI_IsTxComplete,
+* \ref Cy_SCB_SPI_GetNumInRxFifo and \ref Cy_SCB_SPI_GetNumInTxFifo.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_TRANFER_DATA_LL
+*
+* \subsection group_scb_spi_hl High-Level API
+* The \ref group_scb_spi_high_level_functions API uses an interrupt to execute
+* a transfer. Call \ref Cy_SCB_SPI_Transfer to start communication: for the
+* master mode, a transfer to the slave starts but for the slave mode,
+* the Read and Write buffers are prepared for the following communication
+* with the master.
+* After a transfer is started, the \ref Cy_SCB_SPI_Interrupt handles the
+* transfer until its completion. Therefore, it must be called inside the
+* user interrupt handler to make the High-Level API work. To monitor the status
+* of the transfer operation, use \ref Cy_SCB_SPI_GetTransferStatus.
+* Alternatively, use \ref Cy_SCB_SPI_RegisterCallback to register a callback
+* function to be notified about \ref group_scb_spi_macros_callback_events.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\spi_snippets.c SPI_TRANFER_DATA
+*
+* \section group_scb_spi_dma_trig DMA Trigger
+* The SCB provides TX and RX output trigger signals that can be routed to the
+* DMA controller inputs. These signals are assigned based on the data availability
+* in the TX and RX FIFOs appropriately.
+*
+* * The RX trigger signal remains active until the number of data
+* elements in the RX FIFO is greater than the value of RX FIFO level. Use
+* function \ref Cy_SCB_SetRxFifoLevel or set configuration structure
+* rxFifoTriggerLevel parameter to configure RX FIFO level value. \n
+* <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0.
+* The RX trigger signal remains active until DMA does not read all data from
+* the RX FIFO.</em>
+*
+* * The TX trigger signal remains active until the number of data elements
+* in the TX FIFO is less than the value of TX FIFO level. Use function
+* \ref Cy_SCB_SetTxFifoLevel or set configuration structure txFifoTriggerLevel
+* parameter to configure TX FIFO level value. \n
+* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
+* is 7. The TX trigger signal remains active until DMA does not load TX FIFO
+* with 7 data elements (note that after the first TX load operation, the data
+* element goes to the shift register and TX FIFO remains empty).</em>
+*
+* To route SCB TX or RX trigger signals to the DMA controller, use \ref group_trigmux
+* driver API.
+*
+* \note
+* To properly handle DMA level request signal activation and de-activation from the SCB
+* peripheral block the DMA Descriptor typically must be configured to re-trigger
+* after 16 Clk_Slow cycles.
+*
+* \section group_scb_spi_lp Low Power Support
+* The SPI driver provides the callback functions to handle power mode transition.
+* The callback \ref Cy_SCB_SPI_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_SPI_HibernateCallback
+* must be called during execution of \ref Cy_SysPm_Hibernate. To trigger the
+* callback execution, the callback must be registered before calling the
+* power mode transition function. Refer to \ref group_syspm driver for more
+* information about power mode transitions and callback registration.
+*
+* The SPI master is disabled during Deep Sleep and Hibernate and stops driving
+* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is
+* High-Z, which can cause unexpected behavior of the SPI Slave due to possible
+* glitches on these lines. These pins must be set to the inactive state before
+* entering Deep Sleep or Hibernate mode. To do that, configure the SPI master
+* pins output to drive the inactive state and High-Speed Input Output
+* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
+* driver API). The pins configuration must be restored after exiting Deep Sleep
+* mode to return the SPI master control of the pins (after exiting Hibernate
+* mode, the system init code does the same).
+* Note that the SPI master must be enabled to drive the pins during
+* configuration change not to cause glitches on the lines. Copy either or
+* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback
+* as appropriate, and make the changes described above inside the function.
+* Alternately, external pull-up or pull-down resistors can be connected
+* to the appropriate SPI lines to keep them inactive during Deep-Sleep or
+* Hibernate.
+*
+* \note
+* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
+* For proper operation, when the SPI slave is configured to be a wakeup
+* source from Deep Sleep mode, the \ref Cy_SCB_SPI_DeepSleepCallback must be
+* copied and modified. Refer to the function description to get the details.
+*
+* \section group_scb_spi_more_information More Information
+* For more information on the SCB peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_scb_spi_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>
+* * The pointer to the buffer memory is void to allow handling
+* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
+* The cast operation is safe because the configuration is verified
+* before operation is performed.
+* * The functions \ref Cy_SCB_SPI_DeepSleepCallback and
+* \ref Cy_SCB_SPI_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.</td>
+* </tr>
+* <tr>
+* <td>13.7</td>
+* <td>R</td>
+* <td>Boolean operations whose results are invariant shall not be
+* permitted.</td>
+* <td>The SCB block parameters can be a constant false or true depends on
+* the selected device and cause this violation.</td>
+* </tr>
+* <tr>
+* <td>14.1</td>
+* <td>R</td>
+* <td>There shall be no unreachable code.</td>
+* <td>The SCB block parameters can be a constant false or true depends on
+* the selected device and cause code to be unreachable.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is done to improve
+* code clarity when returning error status code if input parameters
+* validation is failed.</td>
+* </tr>
+* </table>
+*
+* \section group_scb_spi_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td>None.</td>
+* <td>SCB I2C driver updated.</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>Fixed SPI callback notification when error event occurred.</td>
+* <td>The SPI callback passed incorrect event value if error event occurred.</td>
+* </tr>
+* <tr>
+* <td>Added parameters validation for public API.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Replaced variables that have limited range of values with enumerated
+* types.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added missing "cy_cb_" to the callback function type names.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_scb_spi_macros Macros
+* \defgroup group_scb_spi_functions Functions
+* \{
+* \defgroup group_scb_spi_general_functions General
+* \defgroup group_scb_spi_high_level_functions High-Level
+* \defgroup group_scb_spi_low_level_functions Low-Level
+* \defgroup group_scb_spi_interrupt_functions Interrupt
+* \defgroup group_scb_spi_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_spi_data_structures Data Structures
+* \defgroup group_scb_spi_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_SPI_H)
+#define CY_SCB_SPI_H
+
+#include "cy_scb_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_scb_spi_enums
+* \{
+*/
+
+/** SPI status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_SPI_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_SPI_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_SPI_ID | 1U),
+
+ /**
+ * The SPI is busy processing a transfer. Call \ref Cy_SCB_SPI_Transfer
+ * function again once that transfer is completed or aborted.
+ */
+ CY_SCB_SPI_TRANSFER_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_SPI_ID | 2U)
+} cy_en_scb_spi_status_t;
+
+/** SPI Modes */
+typedef enum
+{
+ CY_SCB_SPI_SLAVE, /**< Configures SCB for SPI Slave operation */
+ CY_SCB_SPI_MASTER, /**< Configures SCB for SPI Master operation */
+} cy_en_scb_spi_mode_t;
+
+/** SPI Submodes */
+typedef enum
+{
+ /** Configures an SPI for a standard Motorola SPI operation */
+ CY_SCB_SPI_MOTOROLA = 0x0U,
+
+ /**
+ * Configures the SPI for the TI SPI operation. In the TI mode, the slave
+ * select is a pulse. In this case, the pulse coincides with the first bit.
+ */
+ CY_SCB_SPI_TI_COINCIDES = 0x01U,
+
+ /**
+ * Configures an SPI for the National SPI operation. This is a half-duplex
+ * mode of operation.
+ */
+ CY_SCB_SPI_NATIONAL = 0x02U,
+
+ /**
+ * Configures an SPI for the TI SPI operation, in the TI mode. The slave
+ * select is a pulse. In this case the pulse precedes the first bit.
+ */
+ CY_SCB_SPI_TI_PRECEDES = 0x05U,
+} cy_en_scb_spi_sub_mode_t;
+
+/** SPI SCLK Modes */
+typedef enum
+{
+ CY_SCB_SPI_CPHA0_CPOL0 = 0U, /**< Clock is active low, data is changed on first edge */
+ CY_SCB_SPI_CPHA0_CPOL1 = 1U, /**< Clock is active high, data is changed on first edge */
+ CY_SCB_SPI_CPHA1_CPOL0 = 2U, /**< Clock is active low, data is changed on second edge */
+ CY_SCB_SPI_CPHA1_CPOL1 = 3U, /**< Clock is active high, data is changed on second edge */
+} cy_en_scb_spi_sclk_mode_t;
+
+/** SPI Slave Selects */
+typedef enum
+{
+ CY_SCB_SPI_SLAVE_SELECT0 = 0U, /**< Master will use Slave Select 0 */
+ CY_SCB_SPI_SLAVE_SELECT1 = 1U, /**< Master will use Slave Select 1 */
+ CY_SCB_SPI_SLAVE_SELECT2 = 2U, /**< Master will use Slave Select 2 */
+ CY_SCB_SPI_SLAVE_SELECT3 = 3U, /**< Master will use Slave Select 3 */
+} cy_en_scb_spi_slave_select_t;
+
+/** SPI Polarity */
+typedef enum
+{
+ CY_SCB_SPI_ACTIVE_LOW = 0U, /**< Signal in question is active low */
+ CY_SCB_SPI_ACTIVE_HIGH = 1U, /**< Signal in question is active high */
+} cy_en_scb_spi_polarity_t;
+
+/** \} group_scb_spi_enums */
+
+
+/***************************************
+* Type Definitions
+***************************************/
+
+/**
+* \addtogroup group_scb_spi_data_structures
+* \{
+*/
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_SCB_SPI_Interrupt to notify the user about occurrences of
+* \ref group_scb_spi_macros_callback_events.
+*/
+typedef void (* cy_cb_scb_spi_handle_events_t)(uint32_t event);
+
+
+/** SPI configuration structure */
+typedef struct cy_stc_scb_spi_config
+{
+ /** Specifies the mode of operation */
+ cy_en_scb_spi_mode_t spiMode;
+
+ /** Specifies the submode of SPI operation */
+ cy_en_scb_spi_sub_mode_t subMode;
+
+ /**
+ * Configures the SCLK operation for Motorola sub-mode, ignored for all
+ * other submodes
+ */
+ cy_en_scb_spi_sclk_mode_t sclkMode;
+
+ /**
+ * Oversample factor for SPI.
+ * * For the master mode, the data rate is the SCB clock / oversample
+ * (valid range is 4-16).
+ * * For the slave mode, the oversample value is ignored. The data rate is
+ * determined by the SCB clock frequency. See the device datasheet for
+ * more details.
+ */
+ uint32_t oversample;
+
+ /**
+ * The width of RX data (valid range 4-16). It must be the same as
+ * \ref txDataWidth except in National sub-mode.
+ */
+ uint32_t rxDataWidth;
+
+ /**
+ * The width of TX data (valid range 4-16). It must be the same as
+ * \ref rxDataWidth except in National sub-mode.
+ */
+ uint32_t txDataWidth;
+
+ /**
+ * Enables the hardware to shift out the data element MSB first, otherwise,
+ * LSB first
+ */
+ bool enableMsbFirst;
+
+ /**
+ * Enables the master to generate a continuous SCLK regardless of whether
+ * there is data to send
+ */
+ bool enableFreeRunSclk;
+
+ /**
+ * Enables a digital 3-tap median filter to be applied to the input
+ * of the RX FIFO to filter glitches on the line.
+ */
+ bool enableInputFilter;
+
+ /**
+ * Enables the master to sample MISO line one half clock later to allow
+ * better timings.
+ */
+ bool enableMisoLateSample;
+
+ /**
+ * Enables the master to transmit each data element separated by a
+ * de-assertion of the slave select line (only applicable for the master
+ * mode)
+ */
+ bool enableTransferSeperation;
+
+ /**
+ * Sets active polarity of each SS line.
+ * This is a bit mask: bit 0 corresponds to SS0 and so on to SS3.
+ * 1 means active high, a 0 means active low.
+ */
+ uint32_t ssPolarity;
+
+ /**
+ * When set, the slave will wake the device when the slave select line
+ * becomes active.
+ * Note that not all SCBs support this mode. Consult the device
+ * datasheet to determine which SCBs support wake from Deep Sleep.
+ */
+ bool enableWakeFromSleep;
+
+ /**
+ * When there are more entries in the RX FIFO, then at this level
+ * the RX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls the \ref CY_SCB_SPI_RX_TRIGGER interrupt source.
+ */
+ uint32_t rxFifoTriggerLevel;
+
+ /**
+ * Bits set in this mask will allow events to cause an interrupt
+ * (See \ref group_scb_spi_macros_rx_fifo_status for the set of constant)
+ */
+ uint32_t rxFifoIntEnableMask;
+
+ /**
+ * When there are fewer entries in the TX FIFO, then at this level
+ * the TX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls the \ref CY_SCB_SPI_TX_TRIGGER interrupt source.
+ */
+ uint32_t txFifoTriggerLevel;
+
+ /**
+ * Bits set in this mask allow events to cause an interrupt
+ * (See \ref group_scb_spi_macros_tx_fifo_status for the set of constants)
+ */
+ uint32_t txFifoIntEnableMask;
+
+ /**
+ * Bits set in this mask allow events to cause an interrupt
+ * (See \ref group_scb_spi_macros_master_slave_status for the set of
+ * constants)
+ */
+ uint32_t masterSlaveIntEnableMask;
+
+}cy_stc_scb_spi_config_t;
+
+/** SPI context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_spi_context
+{
+ /** \cond INTERNAL */
+ uint32_t volatile status; /**< The receive status */
+
+ void *rxBuf; /**< The pointer to the receive buffer */
+ uint32_t rxBufSize; /**< The receive buffer size */
+ uint32_t volatile rxBufIdx; /**< The current location in the receive buffer */
+
+ void *txBuf; /**< The pointer to the transmit buffer */
+ uint32_t txBufSize; /**< The transmit buffer size */
+ uint32_t volatile txBufIdx; /**< The current location in the transmit buffer */
+
+ /**
+ * The pointer to an event callback that is called when any of
+ * \ref group_scb_spi_macros_callback_events occurs
+ */
+ cy_cb_scb_spi_handle_events_t cbEvents;
+
+#if !defined(NDEBUG)
+ uint32_t initKey; /**< Tracks the context initialization */
+#endif /* !(NDEBUG) */
+ /** \endcond */
+} cy_stc_scb_spi_context_t;
+
+/** \} group_scb_spi_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_scb_spi_general_functions
+* \{
+*/
+cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config,
+ cy_stc_scb_spi_context_t *context);
+void Cy_SCB_SPI_DeInit (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base);
+void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelect(CySCB_Type *base,
+ cy_en_scb_spi_slave_select_t slaveSelect);
+__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base,
+ cy_en_scb_spi_slave_select_t slaveSelect,
+ cy_en_scb_spi_polarity_t polarity);
+
+__STATIC_INLINE bool Cy_SCB_SPI_IsBusBusy(CySCB_Type const *base);
+/** \} group_scb_spi_general_functions */
+
+/**
+* \addtogroup group_scb_spi_high_level_functions
+* \{
+*/
+cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, void *rxBuffer, uint32_t size,
+ cy_stc_scb_spi_context_t *context);
+void Cy_SCB_SPI_AbortTransfer (CySCB_Type *base, cy_stc_scb_spi_context_t *context);
+uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base, cy_stc_scb_spi_context_t const *context);
+uint32_t Cy_SCB_SPI_GetNumTransfered (CySCB_Type const *base, cy_stc_scb_spi_context_t const *context);
+/** \} group_scb_spi_high_level_functions */
+
+/**
+* \addtogroup group_scb_spi_low_level_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_Read (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_SPI_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_Write (CySCB_Type *base, uint32_t data);
+__STATIC_INLINE uint32_t Cy_SCB_SPI_WriteArray(CySCB_Type *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_SPI_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetTxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetRxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetSlaveMasterStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInTxFifo(CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_SPI_IsTxComplete (CySCB_Type const *base);
+
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInRxFifo(CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifo(CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifo(CySCB_Type *base);
+/** \} group_scb_spi_low_level_functions */
+
+/**
+* \addtogroup group_scb_spi_interrupt_functions
+* \{
+*/
+void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_SPI_RegisterCallback(CySCB_Type const *base, cy_cb_scb_spi_handle_events_t callback,
+ cy_stc_scb_spi_context_t *context);
+/** \} group_scb_spi_interrupt_functions */
+
+/**
+* \addtogroup group_scb_spi_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_scb_spi_low_power_functions */
+
+
+/***************************************
+* API Constants
+***************************************/
+
+/**
+* \addtogroup group_scb_spi_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_spi_macros_tx_fifo_status SPI TX FIFO Statuses
+* Each SPI TX FIFO status is encoded in a separate bit. Therefore multiple bits
+* may be set to indicate the current status.
+* \{
+*/
+/** The number of entries in the TX FIFO is less than the TX FIFO trigger level
+* value
+*/
+#define CY_SCB_SPI_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk)
+
+/** The TX FIFO is not full, there is a space for more data */
+#define CY_SCB_SPI_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk)
+
+/**
+* The TX FIFO is empty, note that there may still be data in the shift register.
+*/
+#define CY_SCB_SPI_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk)
+
+/** An attempt to write to the full TX FIFO */
+#define CY_SCB_SPI_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk)
+
+/**
+* Applicable only for the slave mode. The master tried to read more
+* data elements than available.
+*/
+#define CY_SCB_SPI_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
+/** \} group_scb_spi_macros_tx_fifo_status */
+
+/**
+* \defgroup group_scb_spi_macros_rx_fifo_status SPI RX FIFO Statuses
+* \{
+* Each SPI RX FIFO status is encoded in a separate bit. Therefore, multiple
+* bits may be set to indicate the current status.
+*/
+/** The number of entries in the RX FIFO is more than the RX FIFO trigger
+* level value.
+*/
+#define CY_SCB_SPI_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk)
+
+/** The RX FIFO is not empty, there is data to read */
+#define CY_SCB_SPI_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk)
+
+/**
+* The RX FIFO is full. There is no more space for additional data.
+* Any additional data will be dropped.
+*/
+#define CY_SCB_SPI_RX_FULL (SCB_INTR_RX_FULL_Msk)
+
+/**
+* The RX FIFO was full and there was an attempt to write to it.
+* This additional data was dropped.
+*/
+#define CY_SCB_SPI_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/** An attempt to read from an empty RX FIFO */
+#define CY_SCB_SPI_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk)
+/** \} group_scb_spi_macros_rx_fifo_status */
+
+/**
+* \defgroup group_scb_spi_macros_master_slave_status SPI Master and Slave Statuses
+* \{
+*/
+/** The slave was deselected at the wrong time */
+#define CY_SCB_SPI_SLAVE_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk)
+
+/** The master has transmitted all data elements from FIFO and shifter */
+#define CY_SCB_SPI_MASTER_DONE (SCB_INTR_M_SPI_DONE_Msk)
+/** \} group_scb_spi_macros_master_slave_status */
+
+/**
+* \defgroup group_scb_spi_macros_xfer_status SPI Transfer Status
+* \{
+* Each SPI transfer status is encoded in a separate bit, therefore multiple bits
+* may be set to indicate the current status.
+*/
+/**
+* Transfer operation started by \ref Cy_SCB_SPI_Transfer is in progress
+*/
+#define CY_SCB_SPI_TRANSFER_ACTIVE (0x01UL)
+
+/**
+* All data elements specified by \ref Cy_SCB_SPI_Transfer for transmission
+* have been loaded into the TX FIFO
+*/
+#define CY_SCB_SPI_TRANSFER_IN_FIFO (0x02UL)
+
+/** The slave was deselected at the wrong time. */
+#define CY_SCB_SPI_SLAVE_TRANSFER_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk)
+
+/**
+* RX FIFO was full and there was an attempt to write to it.
+* This additional data was dropped.
+*/
+#define CY_SCB_SPI_TRANSFER_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/**
+* Applicable only for the slave mode. The master tried to read more
+* data elements than available in the TX FIFO.
+*/
+#define CY_SCB_SPI_TRANSFER_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
+/** \} group_scb_spi_macros_xfer_status */
+
+/**
+* \defgroup group_scb_spi_macros_callback_events SPI Callback Events
+* \{
+* Only single event is notified by the callback.
+*/
+/**
+* All data elements specified by \ref Cy_SCB_SPI_Transfer for transmission
+* have been loaded into the TX FIFO
+*/
+#define CY_SCB_SPI_TRANSFER_IN_FIFO_EVENT (0x01U)
+
+/** The transfer operation started by \ref Cy_SCB_SPI_Transfer is complete */
+#define CY_SCB_SPI_TRANSFER_CMPLT_EVENT (0x02U)
+
+/**
+* An error occurred during the transfer. This includes overflow, underflow
+* and a transfer error. Check \ref Cy_SCB_SPI_GetTransferStatus.
+*/
+#define CY_SCB_SPI_TRANSFER_ERR_EVENT (0x04U)
+/** \} group_scb_spi_macros_callback_events */
+
+
+/** Default TX value when no TX buffer is defined */
+#define CY_SCB_SPI_DEFAULT_TX (0x0000FFFFUL)
+
+/** Data returned by the hardware when an empty RX FIFO is read */
+#define CY_SCB_SPI_RX_NO_DATA (0xFFFFFFFFUL)
+
+
+/***************************************
+* Internal Constants
+***************************************/
+
+/** \cond INTERNAL */
+#define CY_SCB_SPI_RX_INTR_MASK (CY_SCB_SPI_RX_TRIGGER | CY_SCB_SPI_RX_NOT_EMPTY | CY_SCB_SPI_RX_FULL | \
+ CY_SCB_SPI_RX_OVERFLOW | CY_SCB_SPI_RX_UNDERFLOW)
+
+#define CY_SCB_SPI_TX_INTR_MASK (CY_SCB_SPI_TX_TRIGGER | CY_SCB_SPI_TX_NOT_FULL | CY_SCB_SPI_TX_EMPTY | \
+ CY_SCB_SPI_TX_OVERFLOW | CY_SCB_SPI_TX_UNDERFLOW)
+
+#define CY_SCB_SPI_MASTER_SLAVE_INTR_MASK (CY_SCB_SPI_MASTER_DONE | CY_SCB_SPI_SLAVE_ERR)
+
+#define CY_SCB_SPI_TRANSFER_ERR (CY_SCB_SPI_SLAVE_TRANSFER_ERR | CY_SCB_SPI_TRANSFER_OVERFLOW | \
+ CY_SCB_SPI_TRANSFER_UNDERFLOW)
+
+#define CY_SCB_SPI_INIT_KEY (0x00ABCDEFUL)
+
+#define CY_SCB_SPI_IS_MODE_VALID(mode) ( (CY_SCB_SPI_SLAVE == (mode)) || \
+ (CY_SCB_SPI_MASTER == (mode)) )
+
+#define CY_SCB_SPI_IS_SUB_MODE_VALID(subMode) ( (CY_SCB_SPI_MOTOROLA == (subMode)) || \
+ (CY_SCB_SPI_TI_COINCIDES == (subMode)) || \
+ (CY_SCB_SPI_TI_PRECEDES == (subMode)) || \
+ (CY_SCB_SPI_NATIONAL == (subMode)) )
+
+#define CY_SCB_SPI_IS_SCLK_MODE_VALID(clkMode) ( (CY_SCB_SPI_CPHA0_CPOL0 == (clkMode)) || \
+ (CY_SCB_SPI_CPHA0_CPOL1 == (clkMode)) || \
+ (CY_SCB_SPI_CPHA1_CPOL0 == (clkMode)) || \
+ (CY_SCB_SPI_CPHA1_CPOL1 == (clkMode)) )
+
+#define CY_SCB_SPI_IS_POLARITY_VALID(polarity) ( (CY_SCB_SPI_ACTIVE_LOW == (polarity)) || \
+ (CY_SCB_SPI_ACTIVE_HIGH == (polarity)) )
+
+#define CY_SCB_SPI_IS_SLAVE_SEL_VALID(ss) ( (CY_SCB_SPI_SLAVE_SELECT0 == (ss)) || \
+ (CY_SCB_SPI_SLAVE_SELECT1 == (ss)) || \
+ (CY_SCB_SPI_SLAVE_SELECT2 == (ss)) || \
+ (CY_SCB_SPI_SLAVE_SELECT3 == (ss)) )
+
+#define CY_SCB_SPI_IS_OVERSAMPLE_VALID(ovs, mode) ( (CY_SCB_SPI_MASTER == (mode)) ? (((ovs) >= 2UL) && ((ovs) <= 16UL)) : true )
+#define CY_SCB_SPI_IS_DATA_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL) )
+#define CY_SCB_SPI_IS_SS_POLARITY_VALID(polarity) ( (0UL == ((polarity) & (~0x0FUL))) )
+#define CY_SCB_SPI_IS_BUFFER_VALID(txBuffer, rxBuffer, size) ( ((size) > 0UL) && \
+ (false == ((NULL == (txBuffer)) && (NULL == (rxBuffer)))) )
+
+#define CY_SCB_SPI_IS_BOTH_DATA_WIDTH_VALID(subMode, rxWidth, txWidth) ( (CY_SCB_SPI_NATIONAL != (subMode)) ? \
+ ((rxWidth) == (txWidth)) : true )
+
+/** \endcond */
+
+/** \} group_scb_spi_macros */
+
+
+/***************************************
+* In-line Function Implementation
+***************************************/
+
+/**
+* \addtogroup group_scb_spi_general_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the SPI operation.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base)
+{
+ base->CTRL |= SCB_CTRL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_IsBusBusy
+****************************************************************************//**
+*
+* Returns whether the SPI bus is busy or not. The bus busy is determined using
+* the slave select signal.
+* * Motorola and National Semiconductor sub-modes: the bus is busy after the
+* slave select line is activated and lasts until the slave select line is
+* deactivated.
+* * Texas Instrument sub-modes: The bus is busy at the moment of the initial
+* pulse on the slave select line and lasts until the transfer is complete.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* True - the bus is busy; false - the bus is idle.
+*
+* \note
+* * The SPI master does not assign the slave select line immediately after
+* the first data element is written into the TX FIFO. It takes up to two SCLK
+* clocks to assign the slave select line. Before this happens, the bus
+* is considered idle.
+* * If the SPI master is configured to separate a data elements transfer,
+* the bus is busy during each element transfer and is free between them.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_SPI_IsBusBusy(CySCB_Type const *base)
+{
+ return _FLD2BOOL(SCB_SPI_STATUS_BUS_BUSY, base->SPI_STATUS);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_SetActiveSlaveSelect
+****************************************************************************//**
+*
+* Selects an active slave select line from one of four available.
+* This function is applicable for the master and slave.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param slaveSelect
+* The slave select line number.
+* See \ref cy_en_scb_spi_slave_select_t for the set of constants.
+*
+* \note
+* The SCB be idle or disabled before calling this function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelect(CySCB_Type *base, cy_en_scb_spi_slave_select_t slaveSelect)
+{
+ CY_ASSERT_L3(CY_SCB_SPI_IS_SLAVE_SEL_VALID(slaveSelect));
+
+ base->SPI_CTRL = _CLR_SET_FLD32U(base->SPI_CTRL, SCB_SPI_CTRL_SSEL, (uint32_t) slaveSelect);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_SetActiveSlaveSelectPolarity
+****************************************************************************//**
+*
+* Sets the active polarity for the slave select line.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param slaveSelect
+* The slave select line number.
+* See \ref cy_en_scb_spi_slave_select_t for the set of constants.
+*
+* \param polarity
+* The polarity of the slave select line.
+* See \ref cy_en_scb_spi_polarity_t for the set of constants.
+*
+* \note
+* The SCB be idle or disabled before calling this function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base,
+ cy_en_scb_spi_slave_select_t slaveSelect,
+ cy_en_scb_spi_polarity_t polarity)
+{
+ CY_ASSERT_L3(CY_SCB_SPI_IS_SLAVE_SEL_VALID(slaveSelect));
+ CY_ASSERT_L3(CY_SCB_SPI_IS_POLARITY_VALID (polarity));
+
+ uint32_t mask = _VAL2FLD(CY_SCB_SPI_CTRL_SSEL_POLARITY, (0x01UL << slaveSelect));
+
+ if (CY_SCB_SPI_ACTIVE_HIGH != polarity)
+ {
+ base->SPI_CTRL |= (uint32_t) mask;
+ }
+ else
+ {
+ base->SPI_CTRL &= (uint32_t) ~mask;
+ }
+}
+/** \} group_scb_spi_general_functions */
+
+
+/**
+* \addtogroup group_scb_spi_low_level_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetRxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the RX FIFO.
+* Clear the active statuses to let the SCB hardware update them.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* \ref group_scb_spi_macros_rx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetRxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_SPI_RX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ClearRxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the RX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param clearMask
+* The mask of which statuses to clear.
+* See \ref group_scb_spi_macros_rx_fifo_status for the set of constants.
+*
+* \note
+* * This status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level sensitive statuses such as \ref CY_SCB_SPI_RX_TRIGGER,
+* \ref CY_SCB_SPI_RX_NOT_EMPTY and \ref CY_SCB_SPI_RX_FULL set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SPI_RX_INTR_MASK));
+
+ Cy_SCB_ClearRxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetNumInRxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the SPI RX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* The number of data elements in the RX FIFO.
+* The size of a data element defined by the configured RX data width.
+*
+* \note
+* This number does not include any data currently in the RX shifter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInRxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ClearRxFifo
+****************************************************************************//**
+*
+* Clears all data out of the SPI RX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \sideeffect
+* Any data currently in the shifter is cleared and lost.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetTxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the TX FIFO.
+* Clear the active statuses to let the SCB hardware update them.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* \ref group_scb_spi_macros_tx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetTxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_SPI_TX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ClearTxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param clearMask
+* The mask of which statuses to clear.
+* See \ref group_scb_spi_macros_tx_fifo_status for the set of constants.
+*
+* \note
+* * The status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level sensitive statuses such as \ref CY_SCB_SPI_TX_TRIGGER,
+* \ref CY_SCB_SPI_TX_EMPTY and \ref CY_SCB_SPI_TX_NOT_FULL set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SPI_TX_INTR_MASK));
+
+ Cy_SCB_ClearTxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetNumInTxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the SPI TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* The number of data elements in the TX FIFO.
+* The size of a data element defined by the configured TX data width.
+*
+* \note
+* This number does not include any data currently in the TX shifter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInTxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInTxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_IsTxComplete
+****************************************************************************//**
+*
+* Checks whether the TX FIFO and Shifter are empty and there is no more data to send
+*
+* \param base
+* Pointer to the SPI SCB instance.
+*
+* \return
+* If true, transmission complete. If false, transmission is not complete.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_SPI_IsTxComplete(CySCB_Type const *base)
+{
+ return Cy_SCB_IsTxComplete(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ClearTxFifo
+****************************************************************************//**
+*
+* Clears all data out of the SPI TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \sideeffect
+* The TX FIFO clear operation also clears the shift register, so that
+* the shifter can be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as 1s on the bus.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearTxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_GetSlaveMasterStatus
+****************************************************************************//**
+*
+* Returns the current status of either the slave or the master, depending
+* on the configured SPI mode.
+* Clear the active statuses to let the SCB hardware update them.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* \ref group_scb_spi_macros_master_slave_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_GetSlaveMasterStatus(CySCB_Type const *base)
+{
+ uint32_t retStatus;
+
+ if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL))
+ {
+ retStatus = (Cy_SCB_GetMasterInterruptStatus(base) & CY_SCB_MASTER_INTR_SPI_DONE);
+ }
+ else
+ {
+ retStatus = (Cy_SCB_GetSlaveInterruptStatus(base) & CY_SCB_SLAVE_INTR_SPI_BUS_ERROR);
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ClearSlaveMasterStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of either the slave or the master.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param clearMask
+* The mask of which statuses to clear.
+* See \ref group_scb_spi_macros_master_slave_status for the set of constants.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL))
+ {
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_MASTER_INTR_SPI_DONE));
+
+ Cy_SCB_ClearMasterInterrupt(base, clearMask);
+ }
+ else
+ {
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR));
+
+ Cy_SCB_ClearSlaveInterrupt(base, clearMask);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Read
+****************************************************************************//**
+*
+* Reads a single data element from the SPI RX FIFO.
+* This function does not check whether the RX FIFO has data before reading it.
+* If the RX FIFO is empty, the function returns \ref CY_SCB_SPI_RX_NO_DATA.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \return
+* Data from the RX FIFO.
+* The data element size is defined by the configured RX data width.
+*
+* \note
+* * This function only reads data available in the RX FIFO. It does not
+* initiate an SPI transfer.
+* * When in the master mode, writes data into the TX FIFO and waits until
+* the transfer is completed before getting data from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_Read(CySCB_Type const *base)
+{
+ return Cy_SCB_ReadRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_ReadArray
+****************************************************************************//**
+*
+* Reads an array of data out of the SPI RX FIFO.
+* This function does not block. It returns how many data elements were read
+* from the RX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param buffer
+* The pointer to the location to place data read from the RX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* RX data width.
+*
+* \param size
+* The number of data elements to read from the RX FIFO.
+*
+* \return
+* The number of data elements read from the RX FIFO.
+*
+* \note
+* * This function only reads data available in the RX FIFO. It does not
+* initiate an SPI transfer.
+* * When in the master mode, writes data into the TX FIFO and waits until
+* the transfer is completed before getting data from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_ReadArray(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_ReadArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_Write
+****************************************************************************//**
+*
+* Places a single data element in the SPI TX FIFO.
+* This function does not block. It returns how many data elements were placed
+* in the TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param data
+* Data to put in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \return
+* The number of data elements placed in the TX FIFO: 0 or 1.
+*
+* \note
+* * When in the master mode, writing data into the TX FIFO starts an SPI
+* transfer.
+* * When in the slave mode, writing data into the TX FIFO does not start
+* an SPI transfer. The data is loaded in the TX FIFO and will be sent
+* to the master on its request.
+* * The SPI interface is full-duplex, therefore reads and writes occur
+* at the same time. Thus for every data element transferred out of the
+* TX FIFO, one is transferred into the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_Write(CySCB_Type *base, uint32_t data)
+{
+ return Cy_SCB_Write(base, data);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_WriteArray
+****************************************************************************//**
+*
+* Places an array of data in the SPI TX FIFO. This function does not
+* block. It returns how many data elements were placed in the TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param buffer
+* The pointer to the data to place in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \return
+* The number of data elements placed in the TX FIFO.
+*
+* \note
+* * When in the master mode, writing data into the TX FIFO starts an SPI
+* transfer.
+* * When in the slave mode, writing data into the TX FIFO does not start
+* an SPI transfer. The data is loaded in the TX FIFO and will be sent to
+* the master on its request.
+* * The SPI interface is full-duplex, therefore reads and writes occur
+* at the same time. Thus for every data element transferred out of the
+* TX FIFO, one is transferred into the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_SPI_WriteArray(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_WriteArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_WriteArrayBlocking
+****************************************************************************//**
+*
+* Places an array of data in the SPI TX FIFO. This function blocks
+* until the number of data elements specified by size is placed in the SPI
+* TX FIFO.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to write into the TX FIFO.
+*
+* \note
+* * When in the master mode, writing data into the TX FIFO starts an SPI
+* transfer.
+* * When in the slave mode, writing data into the TX FIFO does not start
+* an SPI transfer. The data is loaded in the TX FIFO and will be sent to
+* the master on its request.
+* * The SPI interface is full-duplex, therefore reads and writes occur
+* at the same time. Thus for every data element transferred out of the
+* TX FIFO, one is transferred into the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ Cy_SCB_WriteArrayBlocking(base, buffer, size);
+}
+/** \} group_scb_spi_low_level_functions */
+
+
+/**
+* \addtogroup group_scb_spi_interrupt_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_SPI_RegisterCallback
+****************************************************************************//**
+*
+* Registers a callback function, which notifies that
+* \ref group_scb_spi_macros_callback_events occurred in the
+* \ref Cy_SCB_SPI_Interrupt.
+*
+* \param base
+* The pointer to the SPI SCB instance.
+*
+* \param callback
+* The pointer to the callback function.
+* See \ref cy_cb_scb_spi_handle_events_t for the function prototype.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated
+* by the user. The structure is used during the SPI operation for internal
+* configuration and data retention. The user should not modify anything
+* in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_SPI_RegisterCallback(CySCB_Type const *base,
+ cy_cb_scb_spi_handle_events_t callback, cy_stc_scb_spi_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->cbEvents = callback;
+}
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Function Name: CY_SCB_SPI_GetSclkMode
+****************************************************************************//**
+*
+* Return correct SCLK mode depends on selected sub mode.
+*
+* \param subMode
+* \ref cy_en_scb_spi_sub_mode_t
+*
+* \param sclkMode
+* \ref cy_en_scb_spi_sclk_mode_t
+*
+* \return
+* \ref cy_en_scb_spi_sclk_mode_t
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t CY_SCB_SPI_GetSclkMode(cy_en_scb_spi_sub_mode_t subMode , cy_en_scb_spi_sclk_mode_t sclkMode)
+{
+ switch (subMode)
+ {
+ case CY_SCB_SPI_TI_PRECEDES:
+ case CY_SCB_SPI_TI_COINCIDES:
+ return (uint32_t) CY_SCB_SPI_CPHA1_CPOL0;
+
+ case CY_SCB_SPI_NATIONAL:
+ return (uint32_t) CY_SCB_SPI_CPHA0_CPOL0;
+
+ case CY_SCB_SPI_MOTOROLA:
+ return (uint32_t) sclkMode;
+
+ default:
+ return (uint32_t) sclkMode;
+ }
+}
+/** \endcond */
+
+/** \} group_scb_spi_interrupt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_spi */
+
+#endif /* (CY_SCB_SPI_H) */
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_uart.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1392 @@
+/***************************************************************************//**
+* \file cy_scb_uart.c
+* \version 2.10
+*
+* Provides UART API implementation of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_scb_uart.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Static functions */
+static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+static void HandleRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Init
+****************************************************************************//**
+*
+* Initializes the SCB for UART operation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param config
+* The pointer to configuration structure \ref cy_stc_scb_uart_config_t.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only UART functions which do not require context will be used pass NULL
+* as pointer to context.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config, cy_stc_scb_uart_context_t *context)
+{
+ if ((NULL == base) || (NULL == config))
+ {
+ return CY_SCB_UART_BAD_PARAM;
+ }
+
+ if (!SCB_IS_UART_CAPABLE(base))
+ {
+ return CY_SCB_UART_BAD_PARAM;
+ }
+
+ CY_ASSERT_L3(CY_SCB_UART_IS_MODE_VALID (config->uartMode));
+ CY_ASSERT_L3(CY_SCB_UART_IS_STOP_BITS_VALID(config->stopBits));
+ CY_ASSERT_L3(CY_SCB_UART_IS_PARITY_VALID (config->parity));
+ CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->ctsPolarity));
+ CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->rtsPolarity));
+
+ CY_ASSERT_L2(CY_SCB_UART_IS_OVERSAMPLE_VALID (config->oversample, config->uartMode, config->irdaEnableLowPowerReceiver));
+ CY_ASSERT_L2(CY_SCB_UART_IS_DATA_WIDTH_VALID (config->dataWidth));
+ CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_VALID (config->receiverAddress));
+ CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_MASK_VALID(config->receiverAddressMask));
+ CY_ASSERT_L2(CY_SCB_UART_IS_MUTLI_PROC_VALID (config->enableMutliProcessorMode, config->uartMode, config->dataWidth,
+ config->parity));
+
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_UART_RX_INTR_MASK));
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_UART_TX_INTR_MASK));
+
+ uint32_t ovs;
+
+ if ((CY_SCB_UART_IRDA == config->uartMode) && (!config->irdaEnableLowPowerReceiver))
+ {
+ /* For Normal IrDA mode oversampling is always zero */
+ ovs = 0UL;
+ }
+ else
+ {
+ ovs = (config->oversample - 1UL);
+ }
+
+ /* Configure the UART interface */
+ base->CTRL = _BOOL2FLD(SCB_CTRL_ADDR_ACCEPT, config->acceptAddrInFifo) |
+ _BOOL2FLD(SCB_CTRL_BYTE_MODE, (config->dataWidth <= CY_SCB_BYTE_WIDTH)) |
+ _VAL2FLD(SCB_CTRL_OVS, ovs) |
+ _VAL2FLD(SCB_CTRL_MODE, CY_SCB_CTRL_MODE_UART);
+
+ /* Configure SCB_CTRL.BYTE_MODE then verify levels */
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel));
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel));
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rtsRxFifoLevel));
+
+ base->UART_CTRL = _VAL2FLD(SCB_UART_CTRL_MODE, (uint32_t) config->uartMode);
+
+ /* Configure the RX direction */
+ base->UART_RX_CTRL = _BOOL2FLD(SCB_UART_RX_CTRL_POLARITY, config->irdaInvertRx) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_MP_MODE, config->enableMutliProcessorMode) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR, config->dropOnParityError) |
+ _BOOL2FLD(SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR, config->dropOnFrameError) |
+ _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, (config->breakWidth - 1UL)) |
+ _VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, ((uint32_t) config->stopBits) - 1UL) |
+ _VAL2FLD(CY_SCB_UART_RX_CTRL_SET_PARITY, (uint32_t) config->parity);
+
+ base->RX_CTRL = _BOOL2FLD(SCB_RX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _BOOL2FLD(SCB_RX_CTRL_MEDIAN, ((config->enableInputFilter) || \
+ (config->uartMode == CY_SCB_UART_IRDA))) |
+ _VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL));
+
+ base->RX_MATCH = _VAL2FLD(SCB_RX_MATCH_ADDR, config->receiverAddress) |
+ _VAL2FLD(SCB_RX_MATCH_MASK, config->receiverAddressMask);
+
+ /* Configure SCB_CTRL.RX_CTRL then verify break width */
+ CY_ASSERT_L2(CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, config->breakWidth));
+
+ /* Configure the TX direction */
+ base->UART_TX_CTRL = _BOOL2FLD(SCB_UART_TX_CTRL_RETRY_ON_NACK, ((config->smartCardRetryOnNack) && \
+ (config->uartMode == CY_SCB_UART_SMARTCARD))) |
+ _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, ((uint32_t) config->stopBits) - 1UL) |
+ _VAL2FLD(CY_SCB_UART_TX_CTRL_SET_PARITY, (uint32_t) config->parity);
+
+ base->TX_CTRL = _BOOL2FLD(SCB_TX_CTRL_MSB_FIRST, config->enableMsbFirst) |
+ _VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL)) |
+ _BOOL2FLD(SCB_TX_CTRL_OPEN_DRAIN, (config->uartMode == CY_SCB_UART_SMARTCARD));
+
+ base->RX_FIFO_CTRL = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel);
+
+ /* Configure the flow control */
+ base->UART_FLOW_CTRL = _BOOL2FLD(SCB_UART_FLOW_CTRL_CTS_ENABLED, config->enableCts) |
+ _BOOL2FLD(SCB_UART_FLOW_CTRL_CTS_POLARITY, (CY_SCB_UART_ACTIVE_HIGH == config->ctsPolarity)) |
+ _BOOL2FLD(SCB_UART_FLOW_CTRL_RTS_POLARITY, (CY_SCB_UART_ACTIVE_HIGH == config->rtsPolarity)) |
+ _VAL2FLD(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, config->rtsRxFifoLevel);
+
+ base->TX_FIFO_CTRL = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel);
+
+ /* Set up interrupt sources */
+ base->INTR_RX_MASK = (config->rxFifoIntEnableMask & CY_SCB_UART_RX_INTR_MASK);
+ base->INTR_TX_MASK = (config->txFifoIntEnableMask & CY_SCB_UART_TX_INTR_MASK);
+
+ /* Initialize context */
+ if (NULL != context)
+ {
+ context->rxStatus = 0UL;
+ context->txStatus = 0UL;
+
+ context->rxRingBuf = NULL;
+ context->rxRingBufSize = 0UL;
+
+ context->rxBufIdx = 0UL;
+ context->txLeftToTransmit = 0UL;
+
+ context->cbEvents = NULL;
+
+ #if !defined(NDEBUG)
+ /* Put an initialization key into the initKey variable to verify
+ * context initialization in the transfer API.
+ */
+ context->initKey = CY_SCB_UART_INIT_KEY;
+ #endif /* !(NDEBUG) */
+ }
+
+ return CY_SCB_UART_SUCCESS;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DeInit
+****************************************************************************//**
+*
+* De-initializes the SCB block. Returns the register values to default.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \note
+* Ensure that the SCB block is disabled before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_UART_DeInit(CySCB_Type *base)
+{
+ /* De-initialize the UART interface */
+ base->CTRL = CY_SCB_CTRL_DEF_VAL;
+ base->UART_CTRL = CY_SCB_UART_CTRL_DEF_VAL;
+
+ /* De-initialize the RX direction */
+ base->UART_RX_CTRL = 0UL;
+ base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL;
+ base->RX_FIFO_CTRL = 0UL;
+ base->RX_MATCH = 0UL;
+
+ /* De-initialize the TX direction */
+ base->UART_TX_CTRL = 0UL;
+ base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL;
+ base->TX_FIFO_CTRL = 0UL;
+
+ /* De-initialize the flow control */
+ base->UART_FLOW_CTRL = 0UL;
+
+ /* De-initialize the interrupt sources */
+ base->INTR_SPI_EC_MASK = 0UL;
+ base->INTR_I2C_EC_MASK = 0UL;
+ base->INTR_RX_MASK = 0UL;
+ base->INTR_TX_MASK = 0UL;
+ base->INTR_M_MASK = 0UL;
+ base->INTR_S_MASK = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Disable
+****************************************************************************//**
+*
+* Disables the SCB block and clears context statuses.
+* Note that after the block is disabled, the TX and RX FIFOs and
+* hardware statuses are cleared. Also, the hardware stops driving the
+* output and ignores the input.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+* If only UART functions that do not require context will be used to pass NULL
+* as pointer to context.
+*
+* \note
+* Calling this function when the UART is busy (transmitter preforms data
+* transfer or receiver is in the middle of data reception) may result transfer
+* corruption because the hardware stops driving the outputs and ignores
+* the inputs.
+* Ensure that the UART is not busy before calling this function.
+*
+*******************************************************************************/
+void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
+
+ if (NULL != context)
+ {
+ context->rxStatus = 0UL;
+ context->txStatus = 0UL;
+
+ context->rxBufIdx = 0UL;
+ context->txLeftToTransmit = 0UL;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB UART into and out of
+* Deep Sleep mode. It prevents the device from entering Deep Sleep
+* mode if the UART is transmitting data or has any data in the RX FIFO. If the
+* UART is ready to enter Deep Sleep mode, it is disabled. The UART is enabled
+* when the device fails to enter Deep Sleep mode or it is awakened from
+* Deep Sleep mode. While the UART is disabled, it stops driving the outputs
+* and ignores the inputs. Any incoming data is ignored.
+*
+* This function must be called during execution of \ref Cy_SysPm_DeepSleep,
+* to do it, register this function as a callback before calling
+* \ref Cy_SysPm_DeepSleep : specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t retStatus = CY_SYSPM_FAIL;
+
+ CySCB_Type *locBase = (CySCB_Type *) callbackParams->base;
+ cy_stc_scb_uart_context_t *locContext = (cy_stc_scb_uart_context_t *) callbackParams->context;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check whether the High-level API is not busy executing the transmit
+ * or receive operation.
+ */
+ if ((0UL == (CY_SCB_UART_TRANSMIT_ACTIVE & Cy_SCB_UART_GetTransmitStatus(locBase, locContext))) &&
+ (0UL == (CY_SCB_UART_RECEIVE_ACTIVE & Cy_SCB_UART_GetReceiveStatus (locBase, locContext))))
+ {
+ /* If all data elements are transmitted from the TX FIFO and
+ * shifter and the RX FIFO is empty: the UART is ready to enter
+ * Deep Sleep mode.
+ */
+ if (Cy_SCB_UART_IsTxComplete(locBase))
+ {
+ if (0UL == Cy_SCB_UART_GetNumInRxFifo(locBase))
+ {
+ /* Disable the UART. The transmitter stops driving the
+ * lines and the receiver stops receiving data until
+ * the UART is enabled.
+ * This happens when the device failed to enter Deep
+ * Sleep or it is awaken from Deep Sleep mode.
+ */
+ Cy_SCB_UART_Disable(locBase, locContext);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* The other driver is not ready for Deep Sleep mode. Restore the
+ * Active mode configuration.
+ */
+
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ /* Do noting: the UART is not capable of waking up from
+ * Deep Sleep mode.
+ */
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(locBase);
+
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SCB UART into Hibernate mode.
+* It prevents the device from entering Hibernate mode if the UART is
+* transmitting data or has any data in the RX FIFO. If the UART is ready
+* to enter Hibernate mode, it is disabled. If the device fails to enter
+* Hibernate mode, the UART is enabled. While the UART is disabled, it stops
+* driving the outputs and ignores the inputs. Any incoming data is ignored.
+*
+* This function must be called during execution of \ref Cy_SysPm_Hibernate.
+* To do it, register this function as a callback before calling
+* \ref Cy_SysPm_Hibernate : specify \ref CY_SYSPM_HIBERNATE as the callback type
+* and call \ref Cy_SysPm_RegisterCallback.
+*
+* \param callbackParams
+* The pointer to the callback parameters structure
+* \ref cy_stc_syspm_callback_params_t.
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ return Cy_SCB_UART_DeepSleepCallback(callbackParams);
+}
+
+
+/************************* High-Level Functions ********************************
+* The following functions are considered high-level. They provide the layer of
+* intelligence to the SCB. These functions require interrupts.
+* Low-level and high-level functions must not be mixed because low-level API
+* can adversely affect the operation of high-level functions.
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_StartRingBuffer
+****************************************************************************//**
+*
+* Starts the receive ring buffer operation.
+* The RX interrupt source is configured to get data from the RX
+* FIFO and put into the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to the user defined ring buffer.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The size of the receive ring buffer.
+* Note that one data element is used for internal use, so if the size is 32,
+* then only 31 data elements are used for data storage.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The buffer must not be modified and stay allocated while the ring buffer
+* operates.
+* * This function overrides the RX interrupt sources and changes the
+* RX FIFO level.
+*
+*******************************************************************************/
+void Cy_SCB_UART_StartRingBuffer(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ if ((NULL != buffer) && (size > 0UL))
+ {
+ uint32_t halfFifoSize = (Cy_SCB_GetFifoSize(base) / 2UL);
+
+ context->rxRingBuf = buffer;
+ context->rxRingBufSize = size;
+ context->rxRingBufHead = 0UL;
+ context->rxRingBufTail = 0UL;
+
+ /* Set up an RX interrupt to handle the ring buffer */
+ Cy_SCB_SetRxFifoLevel(base, (size >= halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL));
+
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_StopRingBuffer
+****************************************************************************//**
+*
+* Stops receiving data into the ring buffer and clears the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_StopRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ Cy_SCB_SetRxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ Cy_SCB_UART_ClearRingBuffer(base, context);
+
+ context->rxRingBuf = NULL;
+ context->rxRingBufSize = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInRingBuffer
+****************************************************************************//**
+*
+* Returns the number of data elements in the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements in the receive ring buffer.
+*
+* \note
+* One data element is used for internal use, so when the buffer is full,
+* this function returns (Ring Buffer size - 1).
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ uint32_t size;
+ uint32_t locHead = context->rxRingBufHead;
+
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ if (locHead >= context->rxRingBufTail)
+ {
+ size = (locHead - context->rxRingBufTail);
+ }
+ else
+ {
+ size = (locHead + (context->rxBufSize - context->rxRingBufTail));
+ }
+
+ return (size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRingBuffer
+****************************************************************************//**
+*
+* Clears the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_ClearRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->rxRingBufHead = context->rxRingBufTail;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Receive
+****************************************************************************//**
+*
+* This function starts a UART receive operation.
+* It configures the receive interrupt sources to get data available in the
+* receive FIFO and returns. The \ref Cy_SCB_UART_Interrupt manages the further
+* data transfer.
+*
+* If the ring buffer is enabled, this function first reads data from the ring
+* buffer. If there is more data to receive, it configures the receive interrupt
+* sources to copy the remaining bytes from the RX FIFO when they arrive.
+*
+* When the receive operation is completed (requested number of data elements
+* received) the \ref CY_SCB_UART_RECEIVE_ACTIVE status is cleared and
+* the \ref CY_SCB_UART_RECEIVE_DONE_EVENT event is generated.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to buffer to store received data.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to receive.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* * The buffer must not be modified and stay allocated until end of the
+* receive operation.
+* * This function overrides the RX interrupt sources and changes the
+* RX FIFO level.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ cy_en_scb_uart_status_t retStatus = CY_SCB_UART_RECEIVE_BUSY;
+
+ /* check whether there are no active transfer requests */
+ if (0UL == (context->rxStatus & CY_SCB_UART_RECEIVE_ACTIVE))
+ {
+ uint8_t *tmpBuf = (uint8_t *) buffer;
+ uint32_t numToCopy = 0UL;
+
+ /* Disable the RX interrupt source to stop the ring buffer update */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ if (NULL != context->rxRingBuf)
+ {
+ /* Get the items available in the ring buffer */
+ numToCopy = Cy_SCB_UART_GetNumInRingBuffer(base, context);
+
+ if (numToCopy > 0UL)
+ {
+ uint32_t idx;
+ uint32_t locTail = context->rxRingBufTail;
+ bool byteMode = Cy_SCB_IsRxDataWidthByte(base);
+
+ /* Adjust the number of items to be read */
+ if (numToCopy > size)
+ {
+ numToCopy = size;
+ }
+
+ /* Copy the data elements from the ring buffer */
+ for (idx = 0UL; idx < numToCopy; ++idx)
+ {
+ ++locTail;
+
+ if (locTail == context->rxRingBufSize)
+ {
+ locTail = 0UL;
+ }
+
+ if (byteMode)
+ {
+ uint8_t *buf = (uint8_t *) buffer;
+ buf[idx] = ((uint8_t *) context->rxRingBuf)[locTail];
+ }
+ else
+ {
+ uint16_t *buf = (uint16_t *) buffer;
+ buf[idx] = ((uint16_t *) context->rxRingBuf)[locTail];
+ }
+ }
+
+ /* Update the ring buffer tail after data has been copied */
+ context->rxRingBufTail = locTail;
+
+ /* Update with the copied bytes */
+ size -= numToCopy;
+ context->rxBufIdx = numToCopy;
+
+ /* Check whether all requested data has been read from the ring buffer */
+ if (0UL == size)
+ {
+ /* Enable the RX-error interrupt sources to update the error status */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RECEIVE_ERR);
+
+ /* Call a completion callback if there was no abort receive called
+ * in the interrupt. The abort clears the number of the received bytes.
+ */
+ if (context->rxBufIdx > 0UL)
+ {
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT);
+ }
+ }
+
+ /* Continue receiving data in the ring buffer */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ else
+ {
+ tmpBuf = &tmpBuf[(byteMode) ? (numToCopy) : (2UL * numToCopy)];
+ }
+ }
+ }
+
+ /* Set up a direct RX FIFO receive */
+ if (size > 0UL)
+ {
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+
+ /* Set up context */
+ context->rxStatus = CY_SCB_UART_RECEIVE_ACTIVE;
+
+ context->rxBuf = (void *) tmpBuf;
+ context->rxBufSize = size;
+ context->rxBufIdx = numToCopy;
+
+ /* Set the RX FIFO level to the trigger interrupt */
+ Cy_SCB_SetRxFifoLevel(base, (size > halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL));
+
+ /* Enable the RX interrupt sources to continue data reading */
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RX_INTR);
+ }
+
+ retStatus = CY_SCB_UART_SUCCESS;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_AbortReceive
+****************************************************************************//**
+*
+* Abort the current receive operation by clearing the receive status.
+* * If the ring buffer is disabled, the receive interrupt sources are disabled.
+* * If the ring buffer is enabled, the receive interrupt source is configured
+* to get data from the receive FIFO and put it into the ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \note
+* * The RX FIFO and ring buffer are not cleared after abort of receive
+* operation.
+* * If after the abort of the receive operation the transmitter continues
+* sending data, it gets into the RX FIFO. To drop this data, the RX FIFO
+* and ring buffer (if enabled) must be cleared when the transmitter
+* stops sending data. Otherwise, received data will be kept and copied
+* to the buffer when \ref Cy_SCB_UART_Receive is called.
+*
+*******************************************************************************/
+void Cy_SCB_UART_AbortReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ if (NULL == context->rxRingBuf)
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ context->rxBufSize = 0UL;
+ context->rxBufIdx = 0UL;
+
+ context->rxStatus = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumReceived
+****************************************************************************//**
+*
+* Returns the number of data elements received since the last call to \ref
+* Cy_SCB_UART_Receive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements received.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumReceived(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->rxBufIdx);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetReceiveStatus
+****************************************************************************//**
+*
+* Returns the status of the receive operation.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_uart_macros_receive_status.
+*
+* \note
+* The status is only cleared by calling \ref Cy_SCB_UART_Receive again.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->rxStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Transmit
+****************************************************************************//**
+*
+* This function starts a UART transmit operation.
+* It configures the transmit interrupt sources and returns.
+* The \ref Cy_SCB_UART_Interrupt manages the further data transfer.
+*
+* When the transmit operation is completed (requested number of data elements
+* sent on the bus), the \ref CY_SCB_UART_TRANSMIT_ACTIVE status is cleared and
+* the \ref CY_SCB_UART_TRANSMIT_DONE_EVENT event is generated.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* Pointer to user data to place in transmit buffer.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to transmit.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref cy_en_scb_uart_status_t
+*
+* \note
+* * The buffer must not be modified and must stay allocated until its content is
+* copied into the TX FIFO.
+* * This function overrides the TX FIFO interrupt sources and changes the
+* TX FIFO level.
+*
+*******************************************************************************/
+cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size, cy_stc_scb_uart_context_t *context)
+{
+ CY_ASSERT_L1(NULL != context);
+ CY_ASSERT_L1(CY_SCB_UART_INIT_KEY == context->initKey);
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ cy_en_scb_uart_status_t retStatus = CY_SCB_UART_TRANSMIT_BUSY;
+
+ /* Check whether there are no active transfer requests */
+ if (0UL == (CY_SCB_UART_TRANSMIT_ACTIVE & context->txStatus))
+ {
+ /* Set up context */
+ context->txStatus = CY_SCB_UART_TRANSMIT_ACTIVE;
+
+ context->txBuf = buffer;
+ context->txBufSize = size;
+
+ /* Set the level in TX FIFO to start a transfer */
+ Cy_SCB_SetTxFifoLevel(base, (Cy_SCB_GetFifoSize(base) / 2UL));
+
+ /* Enable the interrupt sources */
+ if (((uint32_t) CY_SCB_UART_SMARTCARD) == _FLD2VAL(SCB_UART_CTRL_MODE, base->UART_CTRL))
+ {
+ /* Transfer data into TX FIFO and track SmartCard-specific errors */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_UART_TX_INTR);
+ }
+ else
+ {
+ /* Transfer data into TX FIFO */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ retStatus = CY_SCB_UART_SUCCESS;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_AbortTransmit
+****************************************************************************//**
+*
+* Aborts the current transmit operation.
+* It disables the transmit interrupt sources and clears the transmit FIFO
+* and status.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \sideeffect
+* The transmit FIFO clear operation also clears the shift register, so that
+* the shifter can be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as "ones" on the bus.
+*
+*******************************************************************************/
+void Cy_SCB_UART_AbortTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ Cy_SCB_UART_ClearTxFifo(base);
+
+ context->txBufSize = 0UL;
+ context->txLeftToTransmit = 0UL;
+
+ context->txStatus = 0UL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumLeftToTransmit
+****************************************************************************//**
+*
+* Returns the number of data elements left to transmit since the last call to
+* \ref Cy_SCB_UART_Transmit.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* The number of data elements left to transmit.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->txLeftToTransmit);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetTransmitStatus
+****************************************************************************//**
+*
+* Returns the status of the transmit operation.
+* This status is a bit mask and the value returned may have multiple bits set.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+* \return
+* \ref group_scb_uart_macros_transmit_status.
+*
+* \note
+* The status is only cleared by calling \ref Cy_SCB_UART_Transmit or
+* \ref Cy_SCB_UART_AbortTransmit.
+*
+*******************************************************************************/
+uint32_t Cy_SCB_UART_GetTransmitStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ return (context->txStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_SendBreakBlocking
+****************************************************************************//**
+*
+* Sends a break condition (logic low) of specified width on UART TX line.
+* Blocks until break is completed. Only call this function when UART TX FIFO
+* and shifter are empty.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param breakWidth
+* Width of break condition. Valid range is the TX data width (4 to 16 bits)
+*
+* \note
+* Before sending break all UART TX interrupt sources are disabled. The state
+* of UART TX interrupt sources is restored before function returns.
+*
+* \sideeffect
+* If this function is called while there is data in the TX FIFO or shifter that
+* data will be shifted out in packets the size of breakWidth.
+*
+*******************************************************************************/
+void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth)
+{
+ uint32_t txCtrlReg;
+ uint32_t txIntrReg;
+
+ CY_ASSERT_L2(CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(breakWidth));
+
+ /* Disable all UART TX interrupt sources and clear UART TX Done history */
+ txIntrReg = Cy_SCB_GetTxInterruptMask(base);
+ Cy_SCB_SetTxInterruptMask(base, 0UL);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UART_DONE);
+
+ /* Store TX_CTRL configuration */
+ txCtrlReg = base->TX_CTRL;
+
+ /* Set break width: start bit adds one 0 bit */
+ base->TX_CTRL = _CLR_SET_FLD32U(base->TX_CTRL, SCB_TX_CTRL_DATA_WIDTH, (breakWidth - 1UL));
+
+ /* Generate break */
+ Cy_SCB_WriteTxFifo(base, 0UL);
+
+ /* Wait for break completion */
+ while (0UL == (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_TX_INTR_UART_DONE))
+ {
+ }
+
+ /* Clear all UART TX interrupt sources */
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_MASK);
+
+ /* Restore TX data width and interrupt sources */
+ base->TX_CTRL = txCtrlReg;
+ Cy_SCB_SetTxInterruptMask(base, txIntrReg);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Interrupt
+****************************************************************************//**
+*
+* This is the interrupt function for the SCB configured in the UART mode.
+* This function must be called inside a user-defined interrupt service
+* routine to make \ref Cy_SCB_UART_Transmit and \ref Cy_SCB_UART_Receive
+* work.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ if (0UL != (CY_SCB_RX_INTR & Cy_SCB_GetInterruptCause(base)))
+ {
+ /* Get RX error events: a frame error, parity error, and overflow */
+ uint32_t locRxErr = (CY_SCB_UART_RECEIVE_ERR & Cy_SCB_GetRxInterruptStatusMasked(base));
+
+ /* Handle the error conditions */
+ if (0UL != locRxErr)
+ {
+ context->rxStatus |= locRxErr;
+
+ Cy_SCB_ClearRxInterrupt(base, locRxErr);
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_ERR_EVENT);
+ }
+ }
+
+ /* Break the detect */
+ if (0UL != (CY_SCB_RX_INTR_UART_BREAK_DETECT & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ context->rxStatus |= CY_SCB_UART_RECEIVE_BREAK_DETECT;
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_UART_BREAK_DETECT);
+ }
+
+ /* Copy the received data */
+ if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
+ {
+ if (context->rxBufSize > 0UL)
+ {
+ HandleDataReceive(base, context);
+ }
+ else
+ {
+ if (NULL != context->rxRingBuf)
+ {
+ HandleRingBuffer(base, context);
+ }
+ }
+
+ Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ }
+
+ if (0UL != (CY_SCB_TX_INTR & Cy_SCB_GetInterruptCause(base)))
+ {
+ uint32_t locTxErr = (CY_SCB_UART_TRANSMIT_ERR & Cy_SCB_GetTxInterruptStatusMasked(base));
+
+ /* Handle the TX error conditions */
+ if (0UL != locTxErr)
+ {
+ context->txStatus |= locTxErr;
+ Cy_SCB_ClearTxInterrupt(base, locTxErr);
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_ERR_EVENT);
+ }
+ }
+
+ /* Load data to transmit */
+ if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ HandleDataTransmit(base, context);
+
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
+ }
+
+ /* Handle the TX complete */
+ if (0UL != (CY_SCB_TX_INTR_UART_DONE & Cy_SCB_GetTxInterruptStatusMasked(base)))
+ {
+ /* Disable all TX interrupt sources */
+ Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ context->txStatus &= (uint32_t) ~CY_SCB_UART_TRANSMIT_ACTIVE;
+ context->txLeftToTransmit = 0UL;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_DONE_EVENT);
+ }
+ }
+ }
+}
+
+
+
+/*******************************************************************************
+* Function Name: HandleDataReceive
+****************************************************************************//**
+*
+* Reads data from the receive FIFO into the buffer provided by
+* \ref Cy_SCB_UART_Receive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t numCopied;
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+
+ /* Get data from RX FIFO */
+ numCopied = Cy_SCB_UART_GetArray(base, context->rxBuf, context->rxBufSize);
+
+ /* Move the buffer */
+ context->rxBufIdx += numCopied;
+ context->rxBufSize -= numCopied;
+
+ if (0UL == context->rxBufSize)
+ {
+ if (NULL != context->rxRingBuf)
+ {
+ /* Adjust the level to proceed with the ring buffer */
+ Cy_SCB_SetRxFifoLevel(base, (context->rxRingBufSize >= halfFifoSize) ?
+ (halfFifoSize - 1UL) : (context->rxRingBufSize - 1UL));
+
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
+ }
+ else
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+ }
+
+ /* Update the status */
+ context->rxStatus &= (uint32_t) ~CY_SCB_UART_RECEIVE_ACTIVE;
+
+ /* Notify that receive is done in a callback */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT);
+ }
+ }
+ else
+ {
+ uint8_t *buf = (uint8_t *) context->rxBuf;
+
+ buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))];
+ context->rxBuf = (void *) buf;
+
+ if (context->rxBufSize < halfFifoSize)
+ {
+ /* Set the RX FIFO level to trigger an interrupt */
+ Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL));
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleRingBuffer
+****************************************************************************//**
+*
+* Reads data from the receive FIFO into the receive ring buffer.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL;
+ uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base);
+ uint32_t locHead = context->rxRingBufHead;
+ uint32_t rxData;
+
+ /* Get data into the ring buffer */
+ while (numToCopy > 0UL)
+ {
+ ++locHead;
+
+ if (locHead == context->rxRingBufSize)
+ {
+ locHead = 0UL;
+ }
+
+ if (locHead == context->rxRingBufTail)
+ {
+ /* The ring buffer is full, trigger a callback */
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_RB_FULL_EVENT);
+ }
+
+ /* The ring buffer is still full. Disable the RX interrupt not to put data into the ring buffer.
+ * The data is stored in the RX FIFO until it overflows. Revert the head index.
+ */
+ if (locHead == context->rxRingBufTail)
+ {
+ Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
+
+ locHead = (locHead > 0UL) ? (locHead - 1UL) : (context->rxRingBufSize - 1UL);
+ break;
+ }
+ }
+
+ /* Get data from RX FIFO. */
+ rxData = Cy_SCB_ReadRxFifo(base);
+
+ /* Put a data item in the ring buffer */
+ if (Cy_SCB_IsRxDataWidthByte(base))
+ {
+ ((uint8_t *) context->rxRingBuf)[locHead] = (uint8_t) rxData;
+ }
+ else
+ {
+ ((uint16_t *) context->rxRingBuf)[locHead] = (uint16_t) rxData;
+ }
+
+ --numToCopy;
+ }
+
+ /* Update the head index */
+ context->rxRingBufHead = locHead;
+
+ /* Get free entries in the ring buffer */
+ numToCopy = context->rxRingBufSize - Cy_SCB_UART_GetNumInRingBuffer(base, context);
+
+ if (numToCopy < halfFifoSize)
+ {
+ /* Adjust the level to copy to the ring buffer */
+ uint32_t level = (numToCopy > 0UL) ? (numToCopy - 1UL) : 0UL;
+ Cy_SCB_SetRxFifoLevel(base, level);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: HandleDataTransmit
+****************************************************************************//**
+*
+* Loads the transmit FIFO with data provided by \ref Cy_SCB_UART_Transmit.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user must not modify anything
+* in this structure.
+*
+*******************************************************************************/
+static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
+{
+ uint32_t numToCopy;
+ uint32_t fifoSize = Cy_SCB_GetFifoSize(base);
+ bool byteMode = Cy_SCB_IsTxDataWidthByte(base);
+
+ if (context->txBufSize > 1UL)
+ {
+ uint8_t *buf = (uint8_t *) context->txBuf;
+
+ /* Get the number of items left for transmission */
+ context->txLeftToTransmit = context->txBufSize;
+
+ /* Put data into TX FIFO */
+ numToCopy = Cy_SCB_UART_PutArray(base, context->txBuf, (context->txBufSize - 1UL));
+
+ /* Move the buffer */
+ context->txBufSize -= numToCopy;
+
+ buf = &buf[(byteMode) ? (numToCopy) : (2UL * numToCopy)];
+ context->txBuf = (void *) buf;
+ }
+
+ /* Put the last data item into TX FIFO */
+ if ((fifoSize != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->txBufSize))
+ {
+ uint32_t txData;
+ uint32_t intrStatus;
+
+ context->txBufSize = 0UL;
+
+ /* Get the last item from the buffer */
+ txData = (uint32_t) ((byteMode) ? ((uint8_t *) context->txBuf)[0UL] :
+ ((uint16_t *) context->txBuf)[0UL]);
+
+ /* Put the last data element and make sure that "TX done" will happen for it */
+ intrStatus = Cy_SysLib_EnterCriticalSection();
+
+ Cy_SCB_WriteTxFifo(base, txData);
+ Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UART_DONE);
+
+ Cy_SysLib_ExitCriticalSection(intrStatus);
+
+ /* Disable the level interrupt source and enable "transfer done" */
+ Cy_SCB_SetTxInterruptMask(base, (CY_SCB_TX_INTR_UART_DONE |
+ (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL)));
+
+ /* Data is copied into TX FIFO */
+ context->txStatus |= CY_SCB_UART_TRANSMIT_IN_FIFO;
+
+ if (NULL != context->cbEvents)
+ {
+ context->cbEvents(CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT);
+ }
+ }
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_uart.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1540 @@
+/***************************************************************************//**
+* \file cy_scb_uart.h
+* \version 2.10
+*
+* Provides UART API declarations of the SCB driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \addtogroup group_scb_uart
+* \{
+* Driver API for UART
+*
+* UART - Universal Synchronous/Asynchronous Receiver/Transmitter,
+* commonly referred to as RS-232.
+*
+* Three different UART-like serial interface protocols are supported:
+* * UART - the standard mode with an optional UART Hardware flow control.
+* * SmartCard - the transfer is similar to the UART transfer,
+* but a NACK (negative acknowledgment) may be sent from the
+* receiver to the transmitter. Both transmitter and receiver drive the same
+* line, although never at the same time.
+* * IrDA - the Infra-red Data Association protocol adds a modulation
+* scheme to the UART signaling. At the transmitter, bits are modulated.
+* At the receiver, bits are demodulated. The modulation scheme uses the
+* Return-to-Zero-Inverted (RZI) format. Bit value "0" is signaled by a
+* short "1" pulse on the line and bit value "1" is signaled by holding
+* the line to "0".
+*
+* \section group_scb_uart_configuration Configuration Considerations
+* The UART driver configuration can be divided to number of sequential
+* steps listed below:
+* * \ref group_scb_uart_config
+* * \ref group_scb_uart_pins
+* * \ref group_scb_uart_clock
+* * \ref group_scb_uart_data_rate
+* * \ref group_scb_uart_intr
+* * \ref group_scb_uart_enable
+*
+* \note
+* UART driver is built on top of the SCB hardware block. The SCB5 instance is
+* used as an example for all code snippets. Modify the code to match your
+* design.
+*
+* \subsection group_scb_uart_config Configure UART
+* To set up the UART slave driver, provide the configuration parameters in the
+* \ref cy_stc_scb_uart_config_t structure. For example: provide uartMode,
+* oversample, dataWidth, enableMsbFirst, parity, and stopBits. The other
+* parameters are optional for operation. To initialize the driver,
+* call \ref Cy_SCB_UART_Init function providing a pointer to the filled
+* \ref cy_stc_scb_uart_config_t structure and allocated \ref cy_stc_scb_uart_context_t.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_CFG
+*
+* \subsection group_scb_uart_pins Assign and Configure Pins
+* Only dedicated SCB pins can be used for UART operation. The HSIOM
+* register must be configured to connect the block to the pins. Also the UART output
+* pins must be configured in Strong Drive mode and UART input pins in
+* Digital High-Z:
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_CFG_PINS
+*
+* \note
+* The SCB stops driving pins when it is disabled or enters low power mode (except
+* Alternate Active or Sleep). To keep the pins' states, they should be reconfigured or
+* be frozen.
+*
+* \subsection group_scb_uart_clock Assign Clock Divider
+* The clock source must be connected to the SCB block to oversample input and
+* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
+* source clock of this divider must be Clk_Peri)</b></em>. Use the \ref group_sysclk
+* driver API to do that.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_CFG_ASSIGN_CLOCK
+*
+* \subsection group_scb_uart_data_rate Configure Baud Rate
+* To get the UART to operate with the desired baud rate, the source clock frequency
+* and the oversample must be configured. Use the \ref group_sysclk driver API
+* to configure source clock frequency. Set the <em><b>oversample parameter
+* in configuration structure</b></em> to define the number of the SCB clocks
+* within one UART bit-time.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_CFG_DATA_RATE
+*
+* Refer to the technical reference manual (TRM) section UART sub-section
+* Clocking and Oversampling to get information about how to configure the UART to run with
+* desired baud rate.
+*
+* \subsection group_scb_uart_intr Configure Interrupt
+* The interrupt is optional for the UART operation. To configure interrupt
+* the \ref Cy_SCB_UART_Interrupt function must be called in the interrupt
+* handler for the selected SCB instance. Also, this interrupt must be enabled
+* in the NVIC.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_INTR_A
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_INTR_B
+*
+* \subsection group_scb_uart_enable Enable UART
+* Finally, enable the UART operation calling \ref Cy_SCB_UART_Enable.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_ENABLE
+
+* \section group_scb_uart_use_cases Common Use Cases
+* The UART API is divided into two categories: \ref group_scb_spi_low_level_functions
+* and \ref group_scb_spi_high_level_functions. \n
+* <em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level
+* API can adversely affect the operation of a High-Level API.</em>
+*
+* \subsection group_scb_uart_ll Low-Level API
+* The \ref group_scb_uart_low_level_functions API allows
+* interacting directly with the hardware and do not use interrupt.
+* These functions do not require context for operation, thus NULL can be
+* passed in \ref Cy_SCB_UART_Init and \ref Cy_SCB_UART_Disable instead of
+* a pointer to the context structure.
+*
+* * To write data into the TX FIFO, use one of the provided functions:
+* \ref Cy_SCB_UART_Put, \ref Cy_SCB_UART_PutArray,
+* \ref Cy_SCB_UART_PutArrayBlocking or \ref Cy_SCB_UART_PutString.
+* Note that putting data into the TX FIFO starts data transfer.
+*
+* * To read data from the RX FIFO, use one of the provided functions:
+* \ref Cy_SCB_UART_Get, \ref Cy_SCB_UART_GetArray or
+* \ref Cy_SCB_UART_GetArrayBlocking.
+*
+* * The statuses can be polled using: \ref Cy_SCB_UART_GetRxFifoStatus and
+* \ref Cy_SCB_UART_GetTxFifoStatus.
+* <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status
+* is set, it must be cleared.</em> Note that there are statuses evaluated as level.
+* These statuses remain set until an event is true. Therefore, after the clear
+* operation, the status is cleared but then it is restored (if event is still
+* true).
+* For example: the TX FIFO empty interrupt source can be cleared when the
+* TX FIFO is not empty. Put at least two data elements (one goes to the
+* shifter and next to FIFO) before clearing this status. \n
+* Also, following functions can be used for polling as well
+* \ref Cy_SCB_UART_IsTxComplete, \ref Cy_SCB_UART_GetNumInRxFifo and
+* \ref Cy_SCB_UART_GetNumInTxFifo.
+*
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_TRANSMIT_DATA_LL
+*
+* \subsection group_scb_uart_hl High-Level API
+
+* The \ref group_scb_uart_high_level_functions API uses an interrupt to
+* execute transfer. Call \ref Cy_SCB_UART_Transmit to start transmission.
+* Call \ref Cy_SCB_UART_Receive to start receive operation. After the
+* operation is started the \ref Cy_SCB_UART_Interrupt handles the data
+* transfer until its completion.
+* Therefore \ref Cy_SCB_UART_Interrupt must be called inside the
+* interrupt handler to make the High-Level API work. To monitor status
+* of transmit operation, use \ref Cy_SCB_UART_GetTransmitStatus and
+* \ref Cy_SCB_UART_GetReceiveStatus to monitor receive status appropriately.
+* Alternatively use \ref Cy_SCB_UART_RegisterCallback to register callback
+* function to be notified about \ref group_scb_uart_macros_callback_events.
+*
+* <b>Receive Operation</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_RECEIVE_DATA_HL
+*
+* <b>Transmit Operation</b>
+* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\uart_snippets.c UART_TRANSMIT_DATA_HL
+*
+* There is also capability to insert a receive ring buffer that operates between
+* the RX FIFO and the user buffer. The received data is copied into the ring
+* buffer from the RX FIFO. This process runs in the background after the ring
+* buffer operation is started by \ref Cy_SCB_UART_StartRingBuffer.
+* When \ref Cy_SCB_UART_Receive is called, it first reads data from the ring
+* buffer and then sets up an interrupt to receive more data if the required
+* amount has not yet been read.
+*
+* \section group_scb_uart_dma_trig DMA Trigger
+* The SCB provides TX and RX output trigger signals that can be routed to the
+* DMA controller inputs. These signals are assigned based on the data availability
+* in the TX and RX FIFOs appropriately.
+*
+* * The RX trigger signal remains active until the number of data
+* elements in the RX FIFO is greater than the value of RX FIFO level. Use
+* function \ref Cy_SCB_SetRxFifoLevel or set configuration structure
+* rxFifoTriggerLevel parameter to configure RX FIFO level value. \n
+* <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0.
+* The RX trigger signal remains active until DMA does not read all data from
+* the RX FIFO.</em>
+*
+* * The TX trigger signal remains active until the number of data elements
+* in the TX FIFO is less than the value of TX FIFO level. Use function
+* \ref Cy_SCB_SetTxFifoLevel or set configuration structure txFifoTriggerLevel
+* parameter to configure TX FIFO level value. \n
+* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
+* is 7. The TX trigger signal remains active until DMA does not load TX FIFO
+* with 7 data elements (note that after the first TX load operation, the data
+* element goes to the shift register and TX FIFO remains empty).</em>
+*
+* To route SCB TX or RX trigger signals to DMA controller use \ref group_trigmux
+* driver API.
+*
+* \note
+* To properly handle DMA level request signal activation and de-activation from the SCB
+* peripheral block the DMA Descriptor typically must be configured to re-trigger
+* after 16 Clk_Slow cycles.
+*
+* \section group_scb_uart_lp Low Power Support
+* The UART driver provides the callback functions to handle power mode
+* transition. The callback \ref Cy_SCB_UART_DeepSleepCallback must be called
+* during execution of \ref Cy_SysPm_DeepSleep; \ref Cy_SCB_UART_HibernateCallback
+* must be called during execution of \ref Cy_SysPm_Hibernate. To trigger the
+* callback execution, the callback must be registered before calling the
+* power mode transition function. Refer to \ref group_syspm driver for more
+* information about power mode transitions and callback registration.
+*
+* The UART is disabled during Deep Sleep and Hibernate and stops driving
+* the output pins. The state of the UART output pins TX and RTS is High-Z,
+* which can cause unexpected behavior of the UART receiver due to possible
+* glitches on these lines. These pins must be set to the inactive state before
+* entering Deep Sleep or Hibernate mode. To do that, configure the UART
+* pins output to drive the inactive state and High-Speed Input Output
+* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
+* driver API). The pins configuration must be restored after exiting Deep Sleep
+* mode to return the UART control of the pins (after exiting Hibernate mode,
+* the system init code does the same).
+* Note that the UART must be enabled to drive the pins during configuration
+* change not to cause glitches on the lines. Copy either or both
+* \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback as
+* appropriate, and make the changes described above inside the function.
+* Alternately, external pull-up or pull-down resistors can be connected
+* to the appropriate UART lines to keep them inactive during Deep-Sleep or
+* Hibernate.
+*
+* \section group_scb_uart_more_information More Information
+*
+* For more information on the SCB peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_scb_uart_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>A cast should not be performed between a pointer to object type and
+* a different pointer to object type.</td>
+* <td>
+* * The pointer to the buffer memory is void to allow handling different
+* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
+* The cast operation is safe because the configuration is verified
+* before operation is performed.
+* * The functions \ref Cy_SCB_UART_DeepSleepCallback and
+* \ref Cy_SCB_UART_HibernateCallback are callback of
+* \ref cy_en_syspm_status_t type. The cast operation safety in these
+* functions becomes the user's responsibility because pointers are
+* initialized when callback is registered in SysPm driver.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* <tr>
+* <td>14.7</td>
+* <td>R</td>
+* <td>A function shall have a single point of exit at the end of the
+* function.</td>
+* <td>The functions can return from several points. This is done to improve
+* code clarity when returning error status code if input parameters
+* validation fails.</td>
+* </tr>
+* </table>
+*
+* \section group_scb_uart_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td>None.</td>
+* <td>SCB I2C driver updated.</td>
+* </tr>
+* <tr>
+* <td rowspan="5">2.0</td>
+* <td>Added parameters validation for public API.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Replaced variables that have limited range of values with enumerated
+* types.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added missing "cy_cb_" to the callback function type names.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition
+* generation.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and
+* \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering
+* low power mode when RX FIFO is not empty.</td>
+* <td>The callbacks allowed entering device into low power mode when RX FIFO
+* had data.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version.</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_scb_uart_macros Macros
+* \defgroup group_scb_uart_functions Functions
+* \{
+* \defgroup group_scb_uart_general_functions General
+* \defgroup group_scb_uart_high_level_functions High-Level
+* \defgroup group_scb_uart_low_level_functions Low-Level
+* \defgroup group_scb_uart_interrupt_functions Interrupt
+* \defgroup group_scb_uart_low_power_functions Low Power Callbacks
+* \}
+* \defgroup group_scb_uart_data_structures Data Structures
+* \defgroup group_scb_uart_enums Enumerated Types
+*/
+
+#if !defined(CY_SCB_UART_H)
+#define CY_SCB_UART_H
+
+#include "cy_scb_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Enumerated Types
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_enums
+* \{
+*/
+
+/** UART status codes */
+typedef enum
+{
+ /** Operation completed successfully */
+ CY_SCB_UART_SUCCESS = 0U,
+
+ /** One or more of input parameters are invalid */
+ CY_SCB_UART_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 1U),
+
+ /**
+ * The UART is busy processing a transmit operation.
+ * Call \ref Cy_SCB_UART_Receive function again once that operation
+ * is completed or aborted.
+ */
+ CY_SCB_UART_RECEIVE_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 2U),
+
+ /**
+ * The UART is busy processing a receive operation.
+ * Call \ref Cy_SCB_UART_Transmit function again once that operation
+ * is completed or aborted.
+ */
+ CY_SCB_UART_TRANSMIT_BUSY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 3U)
+} cy_en_scb_uart_status_t;
+
+/** UART Mode */
+typedef enum
+{
+ CY_SCB_UART_STANDARD = 0U, /**< Configures the SCB for Standard UART operation */
+ CY_SCB_UART_SMARTCARD = 1U, /**< Configures the SCB for SmartCard operation */
+ CY_SCB_UART_IRDA = 2U, /**< Configures the SCB for IrDA operation */
+} cy_en_scb_uart_mode_t;
+
+/** UART Stop Bits */
+typedef enum
+{
+ CY_SCB_UART_STOP_BITS_1 = 2U, /**< UART looks for 1 Stop Bit */
+ CY_SCB_UART_STOP_BITS_1_5 = 3U, /**< UART looks for 1.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_2 = 4U, /**< UART looks for 2 Stop Bits */
+ CY_SCB_UART_STOP_BITS_2_5 = 5U, /**< UART looks for 2.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_3 = 6U, /**< UART looks for 3 Stop Bits */
+ CY_SCB_UART_STOP_BITS_3_5 = 7U, /**< UART looks for 3.5 Stop Bits */
+ CY_SCB_UART_STOP_BITS_4 = 8U, /**< UART looks for 4 Stop Bits */
+} cy_en_scb_uart_stop_bits_t;
+
+/** UART Parity */
+typedef enum
+{
+ CY_SCB_UART_PARITY_NONE = 0U, /**< UART has no parity check */
+ CY_SCB_UART_PARITY_EVEN = 2U, /**< UART has even parity check */
+ CY_SCB_UART_PARITY_ODD = 3U, /**< UART has odd parity check */
+} cy_en_scb_uart_parity_t;
+
+/** UART Polarity */
+typedef enum
+{
+ CY_SCB_UART_ACTIVE_LOW = 0U, /**< Signal is active low */
+ CY_SCB_UART_ACTIVE_HIGH = 1U, /**< Signal is active high */
+} cy_en_scb_uart_polarity_t;
+/** \} group_scb_uart_enums */
+
+
+/***************************************
+* Type Definitions
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_data_structures
+* \{
+*/
+
+/**
+* Provides the typedef for the callback function called in the
+* \ref Cy_SCB_UART_Interrupt to notify the user about occurrences of
+* \ref group_scb_uart_macros_callback_events.
+*/
+typedef void (* cy_cb_scb_uart_handle_events_t)(uint32_t event);
+
+/** UART configuration structure */
+typedef struct stc_scb_uart_config
+{
+ /** Specifies the UART's mode of operation */
+ cy_en_scb_uart_mode_t uartMode;
+
+ /**
+ * Oversample factor for UART.
+ * * The UART baud rate is the SCB Clock frequency / oversample
+ * (valid range is 8-16).
+ * * For IrDA, the oversample is always 16, unless
+ * \ref irdaEnableLowPowerReceiver is enabled. Then the oversample is
+ * reduced to the \ref group_scb_uart_macros_irda_lp_ovs set.
+ */
+ uint32_t oversample;
+
+ /** The width of UART data (valid range is 5 to 9) */
+ uint32_t dataWidth;
+
+ /**
+ * Enables the hardware to shift out data element MSB first; otherwise,
+ * LSB first
+ */
+ bool enableMsbFirst;
+
+ /**
+ * Specifies the number of stop bits in the UART transaction, in half-bit
+ * increments
+ */
+ cy_en_scb_uart_stop_bits_t stopBits;
+
+ /** Configures the UART parity */
+ cy_en_scb_uart_parity_t parity;
+
+ /**
+ * Enables a digital 3-tap median filter to be applied to the input
+ * of the RX FIFO to filter glitches on the line (for IrDA, this parameter
+ * is ignored)
+ *
+ */
+ bool enableInputFilter;
+
+ /**
+ * Enables the hardware to drop data in the RX FIFO when a parity error is
+ * detected
+ */
+ bool dropOnParityError;
+
+ /**
+ * Enables the hardware to drop data in the RX FIFO when a frame error is
+ * detected
+ */
+ bool dropOnFrameError;
+
+ /**
+ * Enables the UART operation in Multi-Processor mode which requires
+ * dataWidth to be 9 bits (the 9th bit is used to indicate address byte)
+ */
+ bool enableMutliProcessorMode;
+
+ /**
+ * If Multi Processor mode is enabled, this is the address of the RX
+ * FIFO. If the address matches, data is accepted into the FIFO. If
+ * it does not match, the data is ignored.
+ */
+ uint32_t receiverAddress;
+
+ /**
+ * This is the address mask for the Multi Processor address. 1 indicates
+ * that the incoming address must match the corresponding bit in the slave
+ * address. A 0 in the mask indicates that the incoming address does
+ * not need to match.
+ */
+ uint32_t receiverAddressMask;
+
+ /**
+ * Enables the hardware to accept the matching address in the RX FIFO.
+ * This is useful when the device supports more than one address.
+ */
+ bool acceptAddrInFifo;
+
+ /** Inverts the IrDA RX input */
+ bool irdaInvertRx;
+
+ /**
+ * Enables the low-power receive for IrDA mode.
+ * Note that the transmission must be disabled if this mode is enabled.
+ */
+ bool irdaEnableLowPowerReceiver;
+
+ /**
+ * Enables retransmission of the frame placed in the TX FIFO when
+ * NACK is received in SmartCard mode (for Standard and IrDA , this parameter
+ * is ignored)
+ */
+ bool smartCardRetryOnNack;
+
+ /**
+ * Enables the usage of the CTS input signal for the transmitter. The
+ * transmitter waits for CTS to be active before sending data
+ */
+ bool enableCts;
+
+ /** Sets the CTS Polarity */
+ cy_en_scb_uart_polarity_t ctsPolarity;
+
+ /**
+ * When the RX FIFO has fewer entries than rtsRxFifoLevel, the
+ * RTS signal is active (note to disable RTS, set this field to zero)
+ */
+ uint32_t rtsRxFifoLevel;
+
+ /** Sets the RTS Polarity */
+ cy_en_scb_uart_polarity_t rtsPolarity;
+
+ /** Specifies the number of bits to detect a break condition */
+ uint32_t breakWidth;
+
+ /**
+ * When there are more entries in the RX FIFO than this level
+ * the RX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls the \ref CY_SCB_UART_RX_TRIGGER interrupt source.
+ */
+ uint32_t rxFifoTriggerLevel;
+
+ /**
+ * The bits set in this mask allow the event to cause an interrupt
+ * (See \ref group_scb_uart_macros_rx_fifo_status for the set of constants)
+ */
+ uint32_t rxFifoIntEnableMask;
+
+ /**
+ * When there are fewer entries in the TX FIFO then this level
+ * the TX trigger output goes high. This output can be connected
+ * to a DMA channel through a trigger mux.
+ * Also, it controls \ref CY_SCB_UART_TX_TRIGGER interrupt source.
+ */
+ uint32_t txFifoTriggerLevel;
+
+ /**
+ * Bits set in this mask allows the event to cause an interrupt
+ * (See \ref group_scb_uart_macros_tx_fifo_status for the set of constants)
+ */
+ uint32_t txFifoIntEnableMask;
+} cy_stc_scb_uart_config_t;
+
+/** UART context structure.
+* All fields for the context structure are internal. Firmware never reads or
+* writes these values. Firmware allocates the structure and provides the
+* address of the structure to the driver in function calls. Firmware must
+* ensure that the defined instance of this structure remains in scope
+* while the drive is in use.
+*/
+typedef struct cy_stc_scb_uart_context
+{
+ /** \cond INTERNAL */
+ uint32_t volatile txStatus; /**< The transmit status */
+ uint32_t volatile rxStatus; /**< The receive status */
+
+ void *rxRingBuf; /**< The pointer to the ring buffer */
+ uint32_t rxRingBufSize; /**< The ring buffer size */
+ uint32_t volatile rxRingBufHead; /**< The ring buffer head index */
+ uint32_t volatile rxRingBufTail; /**< The ring buffer tail index */
+
+ void *rxBuf; /**< The pointer to the receive buffer */
+ uint32_t rxBufSize; /**< The receive buffer size */
+ uint32_t volatile rxBufIdx; /**< The current location in the receive buffer */
+
+ void *txBuf; /**< The pointer to the transmit buffer */
+ uint32_t txBufSize; /**< The transmit buffer size */
+ uint32_t volatile txLeftToTransmit; /**< The number of data elements left to be transmitted */
+
+ /** The pointer to an event callback that is called when any of
+ * \ref group_scb_uart_macros_callback_events occurs
+ */
+ cy_cb_scb_uart_handle_events_t cbEvents;
+
+#if !defined(NDEBUG)
+ uint32_t initKey; /**< Tracks the context initialization */
+#endif /* !(NDEBUG) */
+ /** \endcond */
+} cy_stc_scb_uart_context_t;
+/** \} group_scb_uart_data_structures */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_general_functions
+* \{
+*/
+cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_DeInit (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base);
+void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_UART_EnableCts (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_DisableCts (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base);
+/** \} group_scb_uart_general_functions */
+
+/**
+* \addtogroup group_scb_uart_high_level_functions
+* \{
+*/
+void Cy_SCB_UART_StartRingBuffer (CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_StopRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+void Cy_SCB_UART_ClearRingBuffer (CySCB_Type const *base, cy_stc_scb_uart_context_t *context);
+
+cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_AbortReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+uint32_t Cy_SCB_UART_GetNumReceived (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+
+cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *buffer, uint32_t size,
+ cy_stc_scb_uart_context_t *context);
+void Cy_SCB_UART_AbortTransmit (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+uint32_t Cy_SCB_UART_GetTransmitStatus (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context);
+/** \} group_scb_uart_high_level_functions */
+
+/**
+* \addtogroup group_scb_uart_low_level_functions
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Put (CySCB_Type *base, uint32_t data);
+__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray (CySCB_Type *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_PutString (CySCB_Type *base, char_t const string[]);
+void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_Get (CySCB_Type const *base);
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray (CySCB_Type const *base, void *buffer, uint32_t size);
+__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus (CySCB_Type const *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo (CySCB_Type const *base);
+__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete (CySCB_Type const *base);
+
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo (CySCB_Type const *base);
+
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo (CySCB_Type *base);
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo (CySCB_Type *base);
+/** \} group_scb_uart_low_level_functions */
+
+/**
+* \addtogroup group_scb_uart_interrupt_functions
+* \{
+*/
+void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
+
+__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, cy_cb_scb_uart_handle_events_t callback,
+ cy_stc_scb_uart_context_t *context);
+/** \} group_scb_uart_interrupt_functions */
+
+/**
+* \addtogroup group_scb_uart_low_power_functions
+* \{
+*/
+cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_scb_uart_low_power_functions */
+
+
+/***************************************
+* API Constants
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_macros
+* \{
+*/
+
+/**
+* \defgroup group_scb_uart_macros_irda_lp_ovs UART IRDA Low Power Oversample factors
+* \{
+*/
+#define CY_SCB_UART_IRDA_LP_OVS16 (1UL) /**< IrDA in low-power mode oversampled by 16 */
+#define CY_SCB_UART_IRDA_LP_OVS32 (2UL) /**< IrDA in low-power mode oversampled by 32 */
+#define CY_SCB_UART_IRDA_LP_OVS48 (3UL) /**< IrDA in low-power mode oversampled by 48 */
+#define CY_SCB_UART_IRDA_LP_OVS96 (4UL) /**< IrDA in low-power mode oversampled by 96 */
+#define CY_SCB_UART_IRDA_LP_OVS192 (5UL) /**< IrDA in low-power mode oversampled by 192 */
+#define CY_SCB_UART_IRDA_LP_OVS768 (6UL) /**< IrDA in low-power mode oversampled by 768 */
+#define CY_SCB_UART_IRDA_LP_OVS1536 (7UL) /**< IrDA in low-power mode oversampled by 1536 */
+/** \} group_scb_uart_macros_irda_lp_ovs */
+
+/**
+* \defgroup group_scb_uart_macros_rx_fifo_status UART Receive FIFO status.
+* \{
+*/
+/** The number of entries in the RX FIFO is more than the RX FIFO trigger level
+* value
+*/
+#define CY_SCB_UART_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk)
+
+/** The RX FIFO is not empty, there is data to read */
+#define CY_SCB_UART_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk)
+
+/**
+* The RX FIFO is full, there is no more space for additional data, and
+* any additional data will be dropped
+*/
+#define CY_SCB_UART_RX_FULL (SCB_INTR_RX_FULL_Msk)
+
+/**
+* The RX FIFO was full and there was an attempt to write to it.
+* That additional data was dropped.
+*/
+#define CY_SCB_UART_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/** An attempt to read from an empty RX FIFO */
+#define CY_SCB_UART_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk)
+
+/** The RX FIFO detected a frame error, either a stop or stop-bit error */
+#define CY_SCB_UART_RX_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
+
+/** The RX FIFO detected a parity error */
+#define CY_SCB_UART_RX_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
+
+/** The RX FIFO detected a break transmission from the transmitter */
+#define CY_SCB_UART_RX_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
+/** \} group_scb_uart_macros_rx_fifo_status */
+
+/**
+* \defgroup group_scb_uart_macros_tx_fifo_status UART TX FIFO Statuses
+* \{
+*/
+/** The number of entries in the TX FIFO is less than the TX FIFO trigger level
+* value
+*/
+#define CY_SCB_UART_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk)
+
+/** The TX FIFO is not full, there is a space for more data */
+#define CY_SCB_UART_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk)
+
+/** The TX FIFO is empty, note there may still be data in the shift register.*/
+#define CY_SCB_UART_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk)
+
+/** An attempt to write to the full TX FIFO */
+#define CY_SCB_UART_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk)
+
+/** An attempt to read from an empty transmitter FIFO (hardware reads). */
+#define CY_SCB_UART_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk)
+
+/** All data has been transmitted out of the FIFO, including shifter */
+#define CY_SCB_UART_TX_DONE (SCB_INTR_TX_UART_DONE_Msk)
+
+/** SmartCard only: the transmitter received a NACK */
+#define CY_SCB_UART_TX_NACK (SCB_INTR_TX_UART_NACK_Msk)
+
+/** SmartCard only: the transmitter lost arbitration */
+#define CY_SCB_UART_TX_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
+/** \} group_scb_uart_macros_tx_fifo_status */
+
+/**
+* \defgroup group_scb_uart_macros_receive_status UART Receive Statuses
+* \{
+*/
+/** The receive operation started by \ref Cy_SCB_UART_Receive is in progress */
+#define CY_SCB_UART_RECEIVE_ACTIVE (0x01UL)
+
+/**
+* The hardware RX FIFO was full and there was an attempt to write to it.
+* That additional data was dropped.
+*/
+#define CY_SCB_UART_RECEIVE_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk)
+
+/** The receive hardware detected a frame error, either a start or
+* stop bit error
+*/
+#define CY_SCB_UART_RECEIVE_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk)
+
+/** The receive hardware detected a parity error */
+#define CY_SCB_UART_RECEIVE_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk)
+
+/** The receive hardware detected a break transmission from transmitter */
+#define CY_SCB_UART_RECEIVE_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk)
+/** \} group_scb_uart_macros_receive_status */
+
+/**
+* \defgroup group_scb_uart_macros_transmit_status UART Transmit Status
+* \{
+*/
+/** The transmit operation started by \ref Cy_SCB_UART_Transmit is in progress */
+#define CY_SCB_UART_TRANSMIT_ACTIVE (0x01UL)
+
+/**
+* All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
+* into the TX FIFO
+*/
+#define CY_SCB_UART_TRANSMIT_IN_FIFO (0x02UL)
+
+/** SmartCard only: the transmitter received a NACK */
+#define CY_SCB_UART_TRANSMIT_NACK (SCB_INTR_TX_UART_NACK_Msk)
+
+/** SmartCard only: the transmitter lost arbitration */
+#define CY_SCB_UART_TRANSMIT_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk)
+/** \} group_scb_uart_macros_transmit_status */
+
+/**
+* \defgroup group_scb_uart_macros_callback_events UART Callback Events
+* \{
+* Only single event is notified by the callback.
+*/
+/**
+* All data elements specified by \ref Cy_SCB_UART_Transmit have been loaded
+* into the TX FIFO
+*/
+#define CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT (0x01UL)
+
+/** The transmit operation started by \ref Cy_SCB_UART_Transmit is complete */
+#define CY_SCB_UART_TRANSMIT_DONE_EVENT (0x02UL)
+
+/** The receive operation started by \ref Cy_SCB_UART_Receive is complete */
+#define CY_SCB_UART_RECEIVE_DONE_EVENT (0x04UL)
+
+/**
+* The ring buffer is full, there is no more space for additional data.
+* Additional data is stored in the RX FIFO until it becomes full, at which
+* point data is dropped.
+*/
+#define CY_SCB_UART_RB_FULL_EVENT (0x08UL)
+
+/**
+* An error was detected during the receive operation. This includes overflow,
+* frame error, or parity error. Check \ref Cy_SCB_UART_GetReceiveStatus to
+* determine the source of the error.
+*/
+#define CY_SCB_UART_RECEIVE_ERR_EVENT (0x10UL)
+
+/**
+* An error was detected during the transmit operation. This includes a NACK
+* or lost arbitration. Check \ref Cy_SCB_UART_GetTransmitStatus to determine
+* the source of the error
+*/
+#define CY_SCB_UART_TRANSMIT_ERR_EVENT (0x20UL)
+/** \} group_scb_uart_macros_callback_events */
+
+/** Data returned by the hardware when an empty RX FIFO is read */
+#define CY_SCB_UART_RX_NO_DATA (0xFFFFFFFFUL)
+
+
+/***************************************
+* Internal Constants
+***************************************/
+
+/** \cond INTERNAL */
+#define CY_SCB_UART_TX_INTR_MASK (CY_SCB_UART_TX_TRIGGER | CY_SCB_UART_TX_NOT_FULL | CY_SCB_UART_TX_EMPTY | \
+ CY_SCB_UART_TX_OVERFLOW | CY_SCB_UART_TX_UNDERFLOW | CY_SCB_UART_TX_DONE | \
+ CY_SCB_UART_TX_NACK | CY_SCB_UART_TX_ARB_LOST)
+
+#define CY_SCB_UART_RX_INTR_MASK (CY_SCB_UART_RX_TRIGGER | CY_SCB_UART_RX_NOT_EMPTY | CY_SCB_UART_RX_FULL | \
+ CY_SCB_UART_RX_OVERFLOW | CY_SCB_UART_RX_UNDERFLOW | CY_SCB_UART_RX_ERR_FRAME | \
+ CY_SCB_UART_RX_ERR_PARITY | CY_SCB_UART_RX_BREAK_DETECT)
+
+#define CY_SCB_UART_TX_INTR (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_UART_RX_INTR (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
+ CY_SCB_RX_INTR_UART_PARITY_ERROR | CY_SCB_RX_INTR_UART_BREAK_DETECT)
+
+#define CY_SCB_UART_RECEIVE_ERR (CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \
+ CY_SCB_RX_INTR_UART_PARITY_ERROR)
+
+#define CY_SCB_UART_TRANSMIT_ERR (CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
+
+#define CY_SCB_UART_INIT_KEY (0x00ABCDEFUL)
+
+#define CY_SCB_UART_IS_MODE_VALID(mode) ( (CY_SCB_UART_STANDARD == (mode)) || \
+ (CY_SCB_UART_SMARTCARD == (mode)) || \
+ (CY_SCB_UART_IRDA == (mode)) )
+
+#define CY_SCB_UART_IS_STOP_BITS_VALID(stopBits) ( (CY_SCB_UART_STOP_BITS_1 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_1_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_2 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_2_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_3 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_3_5 == (stopBits)) || \
+ (CY_SCB_UART_STOP_BITS_4 == (stopBits)) )
+
+#define CY_SCB_UART_IS_PARITY_VALID(parity) ( (CY_SCB_UART_PARITY_NONE == (parity)) || \
+ (CY_SCB_UART_PARITY_EVEN == (parity)) || \
+ (CY_SCB_UART_PARITY_ODD == (parity)) )
+
+#define CY_SCB_UART_IS_POLARITY_VALID(polarity) ( (CY_SCB_UART_ACTIVE_LOW == (polarity)) || \
+ (CY_SCB_UART_ACTIVE_HIGH == (polarity)) )
+
+#define CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) ( (CY_SCB_UART_IRDA_LP_OVS16 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS32 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS48 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS96 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS192 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS768 == (ovs)) || \
+ (CY_SCB_UART_IRDA_LP_OVS1536 == (ovs)) )
+
+#define CY_SCB_UART_IS_ADDRESS_VALID(addr) ((addr) <= 0xFFUL)
+#define CY_SCB_UART_IS_ADDRESS_MASK_VALID(mask) ((mask) <= 0xFFUL)
+#define CY_SCB_UART_IS_DATA_WIDTH_VALID(width) ( ((width) >= 5UL) && ((width) <= 9UL) )
+#define CY_SCB_UART_IS_OVERSAMPLE_VALID(ovs, mode, lpRx) ( ((CY_SCB_UART_STANDARD == (mode)) || (CY_SCB_UART_SMARTCARD == (mode))) ? \
+ (((ovs) >= 8UL) && ((ovs) <= 16UL)) : \
+ ((lpRx) ? CY_SCB_UART_IS_IRDA_LP_OVS_VALID(ovs) : true) )
+
+#define CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, width) ( ((width) >= (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, (base)->RX_CTRL) + 3UL)) && \
+ ((width) <= 16UL) )
+#define CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL) )
+
+#define CY_SCB_UART_IS_MUTLI_PROC_VALID(mp, mode, width, parity) ( (mp) ? ((CY_SCB_UART_STANDARD == (mode)) && ((width) == 9UL) && \
+ (CY_SCB_UART_PARITY_NONE == (parity))) : true)
+/** \endcond */
+
+/** \} group_scb_uart_macros */
+
+
+/***************************************
+* In-line Function Implementation
+***************************************/
+
+/**
+* \addtogroup group_scb_uart_general_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Enable
+****************************************************************************//**
+*
+* Enables the SCB block for the UART operation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base)
+{
+ base->CTRL |= SCB_CTRL_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_EnableCts
+****************************************************************************//**
+*
+* Enables the Clear to Send (CTS) input for the UART. The UART will not transmit
+* data while this signal is inactive.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_EnableCts(CySCB_Type *base)
+{
+ base->UART_FLOW_CTRL |= SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DisableCts
+****************************************************************************//**
+*
+* Disables the Clear to Send (CTS) input for the UART.
+* See \ref Cy_SCB_UART_EnableCts for the details.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_DisableCts(CySCB_Type *base)
+{
+ base->UART_FLOW_CTRL &= (uint32_t) ~SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_SetRtsFifoLevel
+****************************************************************************//**
+*
+* Sets a level for the Ready To Send (RTS) signal activation.
+* When the number of data elements in the receive FIFO is below this level,
+* then the RTS output is active. Otherwise, the RTS signal is inactive.
+* To disable the RTS signal generation, set this level to zero.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param level
+* The level in the RX FIFO for RTS signal activation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
+
+ base->UART_FLOW_CTRL = _CLR_SET_FLD32U(base->UART_FLOW_CTRL, SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, level);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetRtsFifoLevel
+****************************************************************************//**
+*
+* Returns the level in the RX FIFO for the RTS signal activation.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The level in the RX FIFO for RTS signal activation.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base)
+{
+ return _FLD2VAL(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, base->UART_FLOW_CTRL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_EnableSkipStart
+****************************************************************************//**
+*
+* Enables the skip start-bit functionality.
+* The UART hardware does not synchronize to a start but synchronizes to
+* the first rising edge. To create a rising edge, the first data bit must
+* be a 1. This feature is useful when the Start edge is used to wake the
+* device through a GPIO interrupt.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \note
+* The skip start-bit feature is applied whenever the UART is disabled due
+* to entrance into Deep Sleep or after calling \ref Cy_SCB_UART_Disable.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart(CySCB_Type *base)
+{
+ base->UART_RX_CTRL |= SCB_UART_RX_CTRL_SKIP_START_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_DisableSkipStart
+****************************************************************************//**
+*
+* Disable the skip start-bit functionality.
+* See \ref Cy_SCB_UART_EnableSkipStart for the details.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base)
+{
+ base->UART_RX_CTRL &= (uint32_t) ~SCB_UART_RX_CTRL_SKIP_START_Msk;
+}
+/** \} group_scb_uart_general_functions */
+
+
+/**
+* \addtogroup group_scb_uart_low_level_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Get
+****************************************************************************//**
+*
+* Reads a single data element from the UART RX FIFO.
+* This function does not check whether the RX FIFO has data before reading it.
+* If the RX FIFO is empty, the function returns \ref CY_SCB_UART_RX_NO_DATA.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* Data from the RX FIFO.
+* The data element size is defined by the configured data width.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Get(CySCB_Type const *base)
+{
+ return Cy_SCB_ReadRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetArray
+****************************************************************************//**
+*
+* Reads an array of data out of the UART RX FIFO.
+* This function does not block. It returns how many data elements were read
+* from the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to the location to place the data read from the RX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the RX FIFO.
+*
+* \return
+* The number of data elements read from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_ReadArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetArrayBlocking
+****************************************************************************//**
+*
+* Reads an array of data out of the UART RX FIFO.
+* This function blocks until the number of data elements specified by the
+* size has been read from the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to the location to place the data read from the RX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to read from the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ Cy_SCB_ReadArrayBlocking(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetRxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the RX FIFO.
+* Clears the active statuses to let the SCB hardware update them.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* \ref group_scb_uart_macros_rx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_UART_RX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param clearMask
+* The mask whose statuses to clear.
+* See \ref group_scb_uart_macros_rx_fifo_status for the set of constants.
+*
+* \note
+* * This status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level-sensitive statuses such as \ref CY_SCB_UART_RX_TRIGGER,
+* \ref CY_SCB_UART_RX_NOT_EMPTY and \ref CY_SCB_UART_RX_FULL are set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_RX_INTR_MASK));
+
+ Cy_SCB_ClearRxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInRxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the UART RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The number of data elements in the RX FIFO.
+* The size of date element defined by the configured data width.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInRxFifo(base);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearRxFifo
+****************************************************************************//**
+*
+* Clears all data out of the UART RX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \sideeffect
+* Any data currently in the shifter is cleared and lost.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearRxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_Put
+****************************************************************************//**
+*
+* Places a single data element in the UART TX FIFO.
+* This function does not block and returns how many data elements were placed
+* in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param data
+* Data to put in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \return
+* The number of data elements placed in the TX FIFO: 0 or 1.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_Put(CySCB_Type *base, uint32_t data)
+{
+ return Cy_SCB_Write(base, data);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutArray
+****************************************************************************//**
+*
+* Places an array of data in the UART TX FIFO.
+* This function does not block. It returns how many data elements were
+* placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* TX data width.
+*
+* \param size
+* The number of data elements to TX.
+*
+* \return
+* The number of data elements placed in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ return Cy_SCB_WriteArray(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutArrayBlocking
+****************************************************************************//**
+*
+* Places an array of data in the UART TX FIFO.
+* This function blocks until the number of data elements specified by the size
+* is placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param buffer
+* The pointer to data to place in the TX FIFO.
+* The item size is defined by the data type, which depends on the configured
+* data width.
+*
+* \param size
+* The number of data elements to write into the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size)
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(buffer, size));
+
+ Cy_SCB_WriteArrayBlocking(base, buffer, size);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_PutString
+****************************************************************************//**
+*
+* Places a NULL terminated string in the UART TX FIFO.
+* This function blocks until the entire string is placed in the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param string
+* The pointer to the null terminated string array.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_PutString(CySCB_Type *base, char_t const string[])
+{
+ CY_ASSERT_L1(CY_SCB_IS_BUFFER_VALID(string, 1UL));
+
+ Cy_SCB_WriteString(base, string);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetTxFifoStatus
+****************************************************************************//**
+*
+* Returns the current status of the TX FIFO.
+* Clear the active statuses to let the SCB hardware update them.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* \ref group_scb_uart_macros_tx_fifo_status
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus(CySCB_Type const *base)
+{
+ return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_UART_TX_INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearTxFifoStatus
+****************************************************************************//**
+*
+* Clears the selected statuses of the TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param clearMask
+* The mask whose statuses to clear.
+* See \ref group_scb_uart_macros_tx_fifo_status for the set of constants.
+*
+* \note
+* * The status is also used for interrupt generation, so clearing it also
+* clears the interrupt sources.
+* * Level-sensitive statuses such as \ref CY_SCB_UART_TX_TRIGGER,
+* \ref CY_SCB_UART_TX_EMPTY and \ref CY_SCB_UART_TX_NOT_FULL are set high again after
+* being cleared if the condition remains true.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask)
+{
+ CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_TX_INTR_MASK));
+
+ Cy_SCB_ClearTxInterrupt(base, clearMask);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_GetNumInTxFifo
+****************************************************************************//**
+*
+* Returns the number of data elements in the UART TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \return
+* The number of data elements in the TX FIFO.
+* The size of date element defined by the configured data width.
+*
+* \note
+* This number does not include any data currently in the TX shifter.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo(CySCB_Type const *base)
+{
+ return Cy_SCB_GetNumInTxFifo(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_IsTxComplete
+****************************************************************************//**
+*
+* Checks whether the TX FIFO and Shifter are empty and there is no more data to send
+*
+* \param base
+* Pointer to the UART SCB instance.
+*
+* \return
+* If true, transmission complete. If false, transmission is not complete.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete(CySCB_Type const *base)
+{
+ return Cy_SCB_IsTxComplete(base);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_ClearTxFifo
+****************************************************************************//**
+*
+* Clears all data out of the UART TX FIFO.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \sideeffect
+* The TX FIFO clear operation also clears the shift register, so that
+* the shifter could be cleared in the middle of a data element transfer,
+* corrupting it. The data element corruption means that all bits that have
+* not been transmitted are transmitted as 1s on the bus.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo(CySCB_Type *base)
+{
+ Cy_SCB_ClearTxFifo(base);
+}
+/** \} group_scb_uart_low_level_functions */
+
+/**
+* \addtogroup group_scb_uart_interrupt_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SCB_UART_RegisterCallback
+****************************************************************************//**
+*
+* Registers a callback function that notifies that
+* \ref group_scb_uart_macros_callback_events occurred in the
+* \ref Cy_SCB_UART_Interrupt.
+*
+* \param base
+* The pointer to the UART SCB instance.
+*
+* \param callback
+* The pointer to the callback function.
+* See \ref cy_cb_scb_uart_handle_events_t for the function prototype.
+*
+* \param context
+* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated
+* by the user. The structure is used during the UART operation for internal
+* configuration and data retention. The user should not modify anything
+* in this structure.
+*
+* \note
+* To remove the callback, pass NULL as the pointer to the callback function.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base,
+ cy_cb_scb_uart_handle_events_t callback, cy_stc_scb_uart_context_t *context)
+{
+ /* Suppress a compiler warning about unused variables */
+ (void) base;
+
+ context->cbEvents = callback;
+}
+/** \} group_scb_uart_interrupt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_scb_uart */
+
+#endif /* (CY_SCB_UART_H) */
+
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1407 @@
+/***************************************************************************//**
+* \file cy_smif.c
+* \version 1.10.1
+*
+* \brief
+* This file provides the source code for the SMIF driver APIs.
+*
+* Note:
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_smif.h"
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Init
+****************************************************************************//**
+*
+* This function initializes the SMIF block as a communication block. The user
+* must ensure that the SMIF interrupt is disabled while this function
+* is called. Enabling the interrupts can lead to triggering in the middle
+* of the initialization operation, which can lead to erroneous initialization.
+*
+* As parameters, this function takes the SMIF register base address and a
+* context structure along with the configuration needed for the SMIF block,
+* stored in a config
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param config
+* Passes a configuration structure that configures the SMIF block for operation.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param timeout
+* A timeout in microseconds for blocking APIs in use.
+*
+*
+* \note Make sure that the interrupts are initialized and disabled.
+*
+* \return
+* - \ref CY_SMIF_BAD_PARAM
+* - \ref CY_SMIF_SUCCESS
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
+ cy_stc_smif_config_t const *config,
+ uint32_t timeout,
+ cy_stc_smif_context_t *context)
+{
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ if((NULL != base) && (NULL != config) && (NULL != context))
+ {
+ /* Copy the base address of the SMIF and the SMIF Device block
+ * registers to the context.
+ */
+ context->timeout = timeout;
+
+ /* Configure the initial interrupt mask */
+ /* Disable the TR_TX_REQ and TR_RX_REQ interrupts */
+ Cy_SMIF_SetInterruptMask(base, Cy_SMIF_GetInterruptMask(base)
+ & ~(SMIF_INTR_TR_TX_REQ_Msk | SMIF_INTR_TR_RX_REQ_Msk));
+
+ /* Check config structure */
+ CY_ASSERT_L3(CY_SMIF_MODE_VALID(config->mode));
+ CY_ASSERT_L3(CY_SMIF_CLOCK_SEL_VALID(config->rxClockSel));
+ CY_ASSERT_L2(CY_SMIF_DESELECT_DELAY_VALID(config->deselectDelay));
+ CY_ASSERT_L3(CY_SMIF_BLOCK_EVENT_VALID(config->blockEvent));
+
+ /* Configure the SMIF interface */
+ base->CTL = (uint32_t)(_VAL2FLD(SMIF_CTL_XIP_MODE, config->mode) |
+ _VAL2FLD(SMIF_CTL_CLOCK_IF_RX_SEL, config->rxClockSel) |
+ _VAL2FLD(SMIF_CTL_DESELECT_DELAY, config->deselectDelay) |
+ _VAL2FLD(SMIF_CTL_BLOCK, config->blockEvent) );
+
+ /* Read the register to flush the buffer */
+ (void) base->CTL;
+
+ result = CY_SMIF_SUCCESS;
+ }
+
+ return result;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_DeInit
+****************************************************************************//**
+*
+* This function de-initializes the SMIF block to default values.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \note The SMIF must be disabled before calling the function. Call
+* \ref Cy_SMIF_Disable
+*
+*******************************************************************************/
+void Cy_SMIF_DeInit(SMIF_Type *base)
+{
+ uint32_t idx;
+
+ /* Configure the SMIF interface to default values.
+ * The default value is 0.
+ */
+ base->CTL = CY_SMIF_CTL_REG_DEFAULT;
+ base->TX_DATA_FIFO_CTL = 0U;
+ base->RX_DATA_FIFO_CTL = 0U;
+ base->INTR_MASK = 0U;
+ for(idx = 0UL; idx < SMIF_DEVICE_NR; idx++)
+ {
+ base->DEVICE[idx].CTL = 0U;
+
+ /* Read the register to flush the buffer */
+ (void) base->DEVICE[idx].CTL;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetMode
+****************************************************************************//**
+*
+* Sets the mode of operation for the SMIF. The mode of operation can be the XIP
+* mode where the slave devices are mapped as memories and are directly accessed
+* from the PSoC register map. In the MMIO mode, the SMIF block acts as a simple
+* SPI engine.
+*
+* \note Interrupt and triggers and not working in XIP mode, see TRM for details
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param mode
+* The mode of the SMIF operation.
+*
+*******************************************************************************/
+void Cy_SMIF_SetMode(SMIF_Type *base, cy_en_smif_mode_t mode)
+{
+ CY_ASSERT_L3(CY_SMIF_MODE_VALID(mode));
+
+ /* Set the register SMIF.CTL.XIP_MODE = TRUE */
+ if (CY_SMIF_NORMAL == mode)
+ {
+ base->CTL &= ~ SMIF_CTL_XIP_MODE_Msk;
+ }
+ else
+ {
+ base->CTL |= SMIF_CTL_XIP_MODE_Msk;
+ }
+
+ /* Read the register to flush the buffer */
+ (void) base->CTL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetMode
+****************************************************************************//**
+*
+* Reads the mode of operation for the SMIF. The mode of operation can be the
+* XIP mode where the slave devices are mapped as memories and are directly
+* accessed from the PSoC register map. In the MMIO mode, the SMIF block acts as
+* a simple SPI engine.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return The mode of SMIF operation (see \ref cy_en_smif_mode_t).
+*
+*******************************************************************************/
+cy_en_smif_mode_t Cy_SMIF_GetMode(SMIF_Type const *base)
+{
+ cy_en_smif_mode_t result = CY_SMIF_NORMAL;
+
+ /* Read the register SMIF.CTL.XIP_MODE*/
+ if (0U != (base->CTL & SMIF_CTL_XIP_MODE_Msk))
+ {
+ result = CY_SMIF_MEMORY;
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetDataSelect
+****************************************************************************//**
+*
+* This function configures the data select option for a specific slave. The
+* selection provides pre-set combinations for connecting the SMIF data lines to
+* the GPIOs.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param slaveSelect
+* The slave device ID. This number is either CY_SMIF_SLAVE_SELECT_0 or
+* CY_SMIF_SLAVE_SELECT_1 or CY_SMIF_SLAVE_SELECT_2 or CY_SMIF_SLAVE_SELECT_3
+* (\ref cy_en_smif_slave_select_t). It defines the slave select line to be used
+* during the transmission.
+*
+* \param dataSelect
+* This parameter selects the data select option. \ref cy_en_smif_data_select_t
+*
+*******************************************************************************/
+void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect,
+ cy_en_smif_data_select_t dataSelect)
+{
+ SMIF_DEVICE_Type volatile *device;
+
+ CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(slaveSelect));
+ CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(dataSelect));
+
+ /* Connect the slave to its data lines */
+ device = Cy_SMIF_GetDeviceBySlot(base, slaveSelect);
+
+ if(NULL != device)
+ {
+ device->CTL = _CLR_SET_FLD32U(device->CTL, SMIF_DEVICE_CTL_DATA_SEL,
+ (uint32_t)dataSelect);
+
+ /* Read the register to flush the buffer */
+ (void) device->CTL;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_TransmitCommand()
+****************************************************************************//**
+*
+* This function transmits a command byte followed by a parameter which is
+* typically an address field. The transfer is implemented using the TX FIFO.
+* This function also asserts the slave select line.
+* A command to a memory device generally starts with a command byte
+* transmission. This function sets up the slave lines for the rest of the
+* command structure. The \ref Cy_SMIF_TransmitCommand is called before \ref
+* Cy_SMIF_TransmitData or \ref Cy_SMIF_ReceiveData is called. When enabled, the
+* cmpltTxfr parameter in the function will de-assert the slave select line at
+* the end of the function execution.
+*
+* \note This function blocks until all the command and associated parameters
+* have been transmitted over the SMIF block or timeout expire.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cmd
+* The command byte to be transmitted.
+*
+* \param cmdTxfrWidth
+* The width of command byte transfer \ref cy_en_smif_txfr_width_t.
+*
+* \param cmdParam
+* This is the pointer to an array that has bytes to be transmitted
+* after the command byte. Typically, this field has the address bytes
+* associated with the memory command.
+*
+* \param paramSize
+* The size of the cmdParam array.
+*
+* \param paramTxfrWidth
+* The width of parameter transfer \ref cy_en_smif_txfr_width_t.
+*
+* \param slaveSelect
+* Denotes the number of the slave device to which the transfer is made.
+* (0, 1, 2 or 4 - the bit defines which slave to enable) Two-bit enable is
+* possible only for the Double Quad SPI mode.
+*
+* \param cmpltTxfr
+* Specifies if the slave select line must be de-asserted after transferring
+* the last byte in the parameter array. Typically, this field is set to 0 when
+* this function succeed through \ref Cy_SMIF_TransmitData or \ref
+* Cy_SMIF_ReceiveData.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \return A status of the command transmit.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
+ uint8_t cmd,
+ cy_en_smif_txfr_width_t cmdTxfrWidth,
+ uint8_t const cmdParam[],
+ uint32_t paramSize,
+ cy_en_smif_txfr_width_t paramTxfrWidth,
+ cy_en_smif_slave_select_t slaveSelect,
+ uint32_t cmpltTxfr,
+ cy_stc_smif_context_t const *context)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_SUCCESS;
+
+ /* Check input values */
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(cmdTxfrWidth));
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(paramTxfrWidth));
+ CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(slaveSelect));
+ CY_ASSERT_L1(CY_SMIF_CMD_PARAM_VALID(cmdParam, paramSize));
+
+ uint8_t bufIndex = 0U;
+ /* The common part of a command and parameter transfer */
+ uint32_t const constCmdPart = (
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_SS, slaveSelect));
+ uint32_t timeoutUnits = context->timeout;
+
+ /* Send the command byte */
+ base->TX_CMD_FIFO_WR = constCmdPart |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t) cmdTxfrWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TXDATA, (uint32_t) cmd) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_LAST_BYTE,
+ ((0UL == paramSize) ? cmpltTxfr : 0UL)) ;
+
+ /* Send the command parameters (usually address) in the blocking mode */
+ while ((bufIndex < paramSize) && (CY_SMIF_EXCEED_TIMEOUT != result))
+ {
+ /* Check if there is at least one free entry in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ base->TX_CMD_FIFO_WR = constCmdPart|
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TXDATA,
+ (uint32_t) cmdParam[bufIndex]) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH,
+ (uint32_t) paramTxfrWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_LAST_BYTE,
+ ((((uint32_t)bufIndex + 1UL) < paramSize) ?
+ 0UL : cmpltTxfr));
+
+ bufIndex++;
+ }
+ result = Cy_SMIF_TimeoutRun(&timeoutUnits);
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_TransmitData
+****************************************************************************//**
+*
+* This function is used to transmit data using the SMIF interface. This
+* function uses the TX Data FIFO to implement the transmit functionality. The
+* function sets up an interrupt to trigger the TX Data FIFO and uses that
+* interrupt to fill the TX Data FIFO until all the data is transmitted. At the
+* end of the transmission, the TxCmpltCb is executed.
+*
+* \note This function is to be preceded by \ref Cy_SMIF_TransmitCommand where
+* the slave select is selected. The slave is de-asserted at the end of a
+* transmit. The function triggers the transfer and the transfer itself utilizes
+* the interrupt for FIFO operations in the background. Thus, frequent
+* interrupts will be executed after this function is triggered.
+* Since this API is non-blocking and sets up the interrupt to act on the data
+* FIFO, ensure there will be no another instance of the function called
+* before the current instance has completed execution.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param txBuffer
+* The pointer to the data to be transferred. If this pointer is a NULL, then the
+* function does not enable the interrupt. This use case is typically used when
+* the FIFO is handled outside the interrupt and is managed in either a
+* polling-based code or a DMA. The user would handle the FIFO management in a
+* DMA or a polling-based code.
+*
+* \note If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation.
+* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
+* valid.
+*
+* \param size
+* The size of txBuffer. Must be > 0.
+*
+* \param transferWidth
+* The width of transfer \ref cy_en_smif_txfr_width_t.
+*
+* \param TxCmpltCb
+* The callback executed at the end of a transmission. NULL interpreted as no
+* callback.
+*
+* \return A status of a transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base,
+ uint8_t* txBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t TxCmpltCb,
+ cy_stc_smif_context_t *context)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ /* Check input values */
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
+
+ if(size > 0U)
+ {
+ result = CY_SMIF_CMD_FIFO_FULL;
+ /* Check if there are enough free entries in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ /* Enter the transmitting mode */
+ base->TX_CMD_FIFO_WR =
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_COUNT_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, ((uint32_t)(size - 1U)));
+
+ if (NULL != txBuffer)
+ {
+ /* Move the parameters to the global variables */
+ context->txBufferAddress = (uint8_t*)txBuffer;
+ context->txBufferSize = size;
+ context->txBufferCounter = size;
+ context->txCmpltCb = TxCmpltCb;
+ context->transferStatus = (uint32_t) CY_SMIF_SEND_BUSY;
+
+ /* Enable the TR_TX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(base,
+ Cy_SMIF_GetInterruptMask(base) | SMIF_INTR_TR_TX_REQ_Msk);
+ }
+ result = CY_SMIF_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_TransmitDataBlocking
+****************************************************************************//**
+*
+* This function implements the transmit data phase in the memory command. The
+* data is transmitted using the Tx Data FIFO and the TX_COUNT command. This
+* function blocks until completion. The function does not use the interrupts and
+* will use CPU to monitor the FIFO status and move data accordingly. The
+* function returns only on completion.
+*
+* \note Since this API is blocking, ensure that other transfers finished and it
+* will not be called during non-blocking transfer.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param txBuffer
+* The pointer to the data to be transferred. If this pointer is a NULL, then the
+* function does not fill TX_FIFO. The user would handle the FIFO management in a
+* DMA or a polling-based code.
+*
+* \note If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation.
+* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
+* valid.
+*
+* \param size
+* The size of txBuffer. Must be > 0.
+*
+* \param transferWidth
+* The width of transfer \ref cy_en_smif_txfr_width_t.
+*
+* \return A status of a transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
+ uint8_t *txBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ /* Check input values */
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
+
+ if(size > 0U)
+ {
+ result = CY_SMIF_CMD_FIFO_FULL;
+ /* Check if there are enough free entries in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ /* Enter the transmitting mode */
+ base->TX_CMD_FIFO_WR =
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_TX_COUNT_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_TX_COUNT, ((uint32_t)(size - 1U)));
+
+ result = CY_SMIF_SUCCESS;
+
+ if (NULL != txBuffer)
+ {
+ uint32_t timeoutUnits = context->timeout;
+ cy_stc_smif_context_t contextLoc;
+
+ /* initialize parameters for Cy_SMIF_PushTxFifo */
+ contextLoc.txBufferAddress = (uint8_t*)txBuffer;
+ contextLoc.txBufferCounter = size;
+ contextLoc.txCmpltCb = NULL;
+ contextLoc.transferStatus = (uint32_t) CY_SMIF_SEND_BUSY;
+
+ while (((uint32_t) CY_SMIF_SEND_BUSY == contextLoc.transferStatus) &&
+ (CY_SMIF_EXCEED_TIMEOUT != result))
+ {
+ Cy_SMIF_PushTxFifo(base, &contextLoc);
+ result = Cy_SMIF_TimeoutRun(&timeoutUnits);
+ }
+ }
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_ReceiveData
+****************************************************************************//**
+*
+* This function implements the receive data phase in the memory command. The
+* data is received into the RX Data FIFO using the RX_COUNT command. This
+* function sets up the interrupt to trigger on the RX Data FIFO level, and the
+* data is fetched from the RX Data FIFO to the rxBuffer as it gets filled. This
+* function does not block until completion. The completion will trigger the call
+* back function.
+*
+* \note This function is to be preceded by \ref Cy_SMIF_TransmitCommand. The
+* slave select is de-asserted at the end of the receive.
+* The function triggers the transfer and the transfer itself utilizes the
+* interrupt for FIFO operations in the background. Thus, frequent
+* interrupts will be executed after this function is triggered.
+* This API is non-blocking and sets up the interrupt to act on the data
+* FIFO, ensure there will be no another instance of the function called
+* before the current instance has completed execution.
+*
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param rxBuffer
+* The pointer to the variable where the receive data is stored. If this pointer
+* is a NULL, then the function does not enable the interrupt. This use case is
+* typically used when the FIFO is handled outside the interrupt and is managed
+* in either a polling-based code or a DMA. The user would handle the FIFO
+* management in a DMA or a polling-based code.
+*
+* \note If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation.
+* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
+* valid.
+*
+* \param size
+* The size of data to be received. Must be > 0.
+*
+* \param transferWidth
+* The width of transfer \ref cy_en_smif_txfr_width_t.
+*
+* \param RxCmpltCb
+* The callback executed at the end of a reception. NULL interpreted as no
+* callback.
+*
+* \return A status of a reception.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base,
+ uint8_t *rxBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t RxCmpltCb,
+ cy_stc_smif_context_t *context)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ /* Check input values */
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
+
+ if(size > 0U)
+ {
+ result = CY_SMIF_CMD_FIFO_FULL;
+ /* Check if there are enough free entries in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ /* Enter the receiving mode */
+ base->TX_CMD_FIFO_WR =
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_RX_COUNT_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, ((uint32_t)(size - 1U)));
+
+ if (NULL != rxBuffer)
+ {
+ /* Move the parameters to the global variables */
+ context->rxBufferAddress = (uint8_t*)rxBuffer;
+ context->rxBufferSize = size;
+ context->rxBufferCounter = size;
+ context->rxCmpltCb = RxCmpltCb;
+ context->transferStatus = (uint32_t) CY_SMIF_REC_BUSY;
+
+ /* Enable the TR_RX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(base,
+ Cy_SMIF_GetInterruptMask(base) | SMIF_INTR_TR_RX_REQ_Msk);
+ }
+ result = CY_SMIF_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_ReceiveDataBlocking
+****************************************************************************//**
+*
+* This function implements the receive data phase in the memory command. The
+* data is received into the RX Data FIFO using the RX_COUNT command. This
+* function blocks until completion. The function does not use the interrupts and
+* will use CPU to monitor the FIFO status and move data accordingly. The
+* function returns only on completion.
+*
+* \note This function is to be preceded by \ref Cy_SMIF_TransmitCommand. The
+* slave select is de-asserted at the end of the receive. Ensure there is
+* no another transfers.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param rxBuffer
+* The pointer to the variable where the receive data is stored. If this pointer
+* is a NULL, then the function does not enable the interrupt. This use case is
+* typically used when the FIFO is handled outside the interrupt and is managed
+* in either a polling-based code or a DMA. The user would handle the FIFO
+* management in a DMA or a polling-based code.
+*
+* \note If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation.
+* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
+* valid.
+*
+* \param size
+* The size of data to be received. Must be > 0.
+*
+* \param transferWidth
+* The width of transfer \ref cy_en_smif_txfr_width_t.
+*
+* \return A status of a reception.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base,
+ uint8_t *rxBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ /* Check input values */
+ CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
+
+ if(size > 0U)
+ {
+ result = CY_SMIF_CMD_FIFO_FULL;
+ /* Check if there are enough free entries in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ /* Enter the receiving mode */
+ base->TX_CMD_FIFO_WR =
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE, CY_SMIF_CMD_FIFO_RX_COUNT_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH, (uint32_t)transferWidth) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_RX_COUNT, ((uint32_t)(size - 1U)));
+ result = CY_SMIF_SUCCESS;
+
+ if (NULL != rxBuffer)
+ {
+
+ uint32_t timeoutUnits = context->timeout;
+ cy_stc_smif_context_t contextLoc;
+
+ /* initialize parameters for Cy_SMIF_PushTxFifo */
+ contextLoc.rxBufferAddress = (uint8_t*)rxBuffer;
+ contextLoc.rxBufferCounter = size;
+ contextLoc.rxCmpltCb = NULL;
+ contextLoc.transferStatus = (uint32_t) CY_SMIF_REC_BUSY;
+
+ while (((uint32_t) CY_SMIF_REC_BUSY == contextLoc.transferStatus) &&
+ (CY_SMIF_EXCEED_TIMEOUT != result))
+ {
+ Cy_SMIF_PopRxFifo(base, &contextLoc);
+ result = Cy_SMIF_TimeoutRun(&timeoutUnits);
+ }
+ }
+ }
+ }
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SendDummyCycles()
+****************************************************************************//**
+*
+* This function sends dummy-clock cycles. The data lines are tri-stated during
+* the dummy cycles.
+*
+* \note This function is to be preceded by \ref Cy_SMIF_TransmitCommand.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cycles
+* The number of dummy cycles. Must be > 0.
+*
+* \return A status of dummy cycles sending.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base,
+ uint32_t cycles)
+{
+ /* The return variable */
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ if (cycles > 0U)
+ {
+ result = CY_SMIF_CMD_FIFO_FULL;
+ /* Check if there are enough free entries in TX_CMD_FIFO */
+ if (Cy_SMIF_GetCmdFifoStatus(base) < CY_SMIF_TX_CMD_FIFO_STATUS_RANGE)
+ {
+ /* Send the dummy bytes */
+ base->TX_CMD_FIFO_WR =
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE,
+ CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE) |
+ _VAL2FLD(CY_SMIF_CMD_FIFO_WR_DUMMY, ((uint32_t)(cycles-1U)));
+
+
+ result = CY_SMIF_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetTxfrStatus
+****************************************************************************//**
+*
+* This function provides the status of the transfer. This function is used to
+* poll for the status of the TransmitData or receiveData function. When this
+* function is called to determine the status of ongoing
+* \ref Cy_SMIF_ReceiveData() or \ref Cy_SMIF_TransmitData(), the returned status
+* is only valid if the functions passed a non-NULL buffer to transmit or
+* receive respectively. If the pointer passed to \ref Cy_SMIF_ReceiveData()
+* or \ref Cy_SMIF_TransmitData() is a NULL, then the code/DMA outside this
+* driver will take care of the transfer and the Cy_GetTxfrStatus() will return
+* an erroneous result.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \return Returns the transfer status. \ref cy_en_smif_txfr_status_t
+*
+*******************************************************************************/
+uint32_t Cy_SMIF_GetTxfrStatus(SMIF_Type *base,
+ cy_stc_smif_context_t const *context)
+{
+ return (context->transferStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Enable
+****************************************************************************//**
+*
+* Enables the operation of the SMIF block.
+*
+* \note This function only enables the SMIF IP. The interrupts associated with
+* the SMIF will need to be separately enabled using the interrupt driver.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+*******************************************************************************/
+void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context)
+{
+ /* Global variables initialization */
+ context->txBufferAddress = 0U;
+ context->txBufferSize = 0U;
+ context->txBufferCounter = 0U;
+ context->rxBufferAddress = 0U;
+ context->rxBufferSize = 0U;
+ context->rxBufferCounter = 0U;
+ context->transferStatus = (uint32_t)CY_SMIF_STARTED;
+
+ base->CTL |= SMIF_CTL_ENABLED_Msk;
+
+ /* Read the register to flush the buffer */
+ (void) base->CTL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Encrypt()
+****************************************************************************//**
+*
+* Uses the Encryption engine to create an encrypted result when the input, key
+* and data arrays are provided. The AES-128 encryption of the address with the
+* key, fetching the result and XOR with the data array are all done in the
+* function. The operational scheme is the following:
+* data = XOR(AES128(address, key), data)
+* Decryption is done using the input data-array identically to the encryption.
+* In the XIP mode, encryption and decryption are done without calling this
+* function. The operational scheme in the XIP mode is the same. The address
+* parameter in the XIP mode equals the actual address in the PSoC memory map.
+* The SMIF encryption engine is designed for code storage.
+* For data storage, the encryption key can be changed.
+* For sensitive data, the Crypto block is used.
+*
+* \note The API does not have access to the encryption key. The key must be
+* placed in the register before calling this API. The crypto routine
+* that can access the key storage area is recommended. This crypto routine is
+* typically a protection context 0 function.
+*
+* \note This is a blocking API. The API waits for encryption completion. Will
+* exit if a timeout is set (not equal to 0) and expired.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \param address
+* The address that gets encrypted is a masked 16-byte block address. The 32-bit
+* address with the last 4 bits masked is placed as the last 4 bytes in the
+* 128-bit input. The rest of the higher bit for the 128 bits are padded zeros.
+* PA[127:0]:
+* PA[3:0] = 0
+* PA[7:4] = ADDR[7:4].
+* PA[15:8] = ADDR[15:8].
+* PA[23:16] = ADDR[23:16].
+* PA[31:24] = ADDR[31:24].
+* The other twelve of the sixteen plain text address bytes of PA[127:0] are "0":
+* PA[127:32] = "0".
+*
+* \param data
+* This is the location where the input data-array is passed while the function
+* is called. This array gets populated with the result after encryption is
+* completed.
+*
+* \param size
+* Provides a size of the array.
+*
+* \return A status of the command transmit.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
+ uint32_t address,
+ uint8_t data[],
+ uint32_t size,
+ cy_stc_smif_context_t const *context)
+{
+ uint32_t bufIndex;
+ cy_en_smif_status_t status = CY_SMIF_BAD_PARAM;
+ uint32_t timeoutUnits = context->timeout;
+
+ CY_ASSERT_L2(size > 0U);
+
+ if((NULL != data) && ((address & (~CY_SMIF_CRYPTO_ADDR_MASK)) == 0UL) )
+ {
+ status = CY_SMIF_SUCCESS;
+ /* Fill the output array */
+ for(bufIndex = 0U; bufIndex < (size / CY_SMIF_AES128_BYTES); bufIndex++)
+ {
+ uint32_t dataIndex = bufIndex * CY_SMIF_AES128_BYTES;
+ uint8_t cryptoOut[CY_SMIF_AES128_BYTES];
+ uint32_t outIndex;
+
+ /* Fill the input field */
+ base->CRYPTO_INPUT0 = (uint32_t) (address +
+ ((bufIndex * CY_SMIF_AES128_BYTES) & CY_SMIF_CRYPTO_ADDR_MASK));
+
+ /* Start the encryption */
+ base->CRYPTO_CMD &= ~SMIF_CRYPTO_CMD_START_Msk;
+ base->CRYPTO_CMD = (uint32_t)(_VAL2FLD(SMIF_CRYPTO_CMD_START,
+ CY_SMIF_CRYPTO_START));
+
+ while((CY_SMIF_CRYPTO_COMPLETED != _FLD2VAL(SMIF_CRYPTO_CMD_START,
+ base->CRYPTO_CMD)) &&
+ (CY_SMIF_EXCEED_TIMEOUT != status))
+ {
+ /* Wait until the encryption is completed and check the
+ * timeout
+ */
+ status = Cy_SMIF_TimeoutRun(&timeoutUnits);
+ }
+
+ if (CY_SMIF_EXCEED_TIMEOUT == status)
+ {
+ break;
+ }
+
+ Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT0,
+ &cryptoOut[CY_SMIF_CRYPTO_FIRST_WORD] , true);
+ Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT1,
+ &cryptoOut[CY_SMIF_CRYPTO_SECOND_WORD], true);
+ Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT2,
+ &cryptoOut[CY_SMIF_CRYPTO_THIRD_WORD] , true);
+ Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT3,
+ &cryptoOut[CY_SMIF_CRYPTO_FOURTH_WORD], true);
+
+ for(outIndex = 0U; outIndex < CY_SMIF_AES128_BYTES; outIndex++)
+ {
+ data[dataIndex + outIndex] ^= cryptoOut[outIndex];
+ }
+ }
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_CacheEnable
+****************************************************************************//**
+*
+* This function is used to enable the fast cache, the slow cache or both.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cacheType
+* Holds the type of the cache to be modified. \ref cy_en_smif_cache_en_t
+*
+* \return A status of function completion.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base,
+ cy_en_smif_cache_en_t cacheType)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ switch (cacheType)
+ {
+ case CY_SMIF_CACHE_SLOW:
+ base->SLOW_CA_CTL |= SMIF_SLOW_CA_CTL_ENABLED_Msk;
+ break;
+ case CY_SMIF_CACHE_FAST:
+ base->FAST_CA_CTL |= SMIF_FAST_CA_CTL_ENABLED_Msk;
+ break;
+ case CY_SMIF_CACHE_BOTH:
+ base->SLOW_CA_CTL |= SMIF_SLOW_CA_CTL_ENABLED_Msk;
+ base->FAST_CA_CTL |= SMIF_FAST_CA_CTL_ENABLED_Msk;
+ break;
+ default:
+ /* A user error*/
+ status = CY_SMIF_BAD_PARAM;
+ break;
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_CacheDisable
+****************************************************************************//**
+*
+* This function is used to disable the fast cache, the slow cache or both
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cacheType
+* Holds the type of the cache to be modified. \ref cy_en_smif_cache_en_t
+*
+* \return A status of function completion.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base,
+ cy_en_smif_cache_en_t cacheType)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ switch (cacheType)
+ {
+ case CY_SMIF_CACHE_SLOW:
+ base->SLOW_CA_CTL &= ~SMIF_SLOW_CA_CTL_ENABLED_Msk;
+ break;
+ case CY_SMIF_CACHE_FAST:
+ base->FAST_CA_CTL &= ~SMIF_FAST_CA_CTL_ENABLED_Msk;
+ break;
+ case CY_SMIF_CACHE_BOTH:
+ base->SLOW_CA_CTL &= ~SMIF_SLOW_CA_CTL_ENABLED_Msk;
+ base->FAST_CA_CTL &= ~SMIF_FAST_CA_CTL_ENABLED_Msk;
+ break;
+ default:
+ /* User error*/
+ status = CY_SMIF_BAD_PARAM;
+ break;
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_CachePrefetchingEnable
+****************************************************************************//**
+*
+* This function is used to enable pre-fetching for the fast cache, the slow
+* cache or both.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cacheType
+* Holds the type of the cache to be modified. \ref cy_en_smif_cache_en_t
+*
+* \return A status of function completion.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingEnable(SMIF_Type *base,
+ cy_en_smif_cache_en_t cacheType)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ switch (cacheType)
+ {
+ case CY_SMIF_CACHE_SLOW:
+ base->SLOW_CA_CTL |= SMIF_SLOW_CA_CTL_PREF_EN_Msk;
+ break;
+ case CY_SMIF_CACHE_FAST:
+ base->FAST_CA_CTL |= SMIF_FAST_CA_CTL_PREF_EN_Msk;
+ break;
+ case CY_SMIF_CACHE_BOTH:
+ base->SLOW_CA_CTL |= SMIF_SLOW_CA_CTL_PREF_EN_Msk;
+ base->FAST_CA_CTL |= SMIF_FAST_CA_CTL_PREF_EN_Msk;
+ break;
+ default:
+ /* A user error*/
+ status = CY_SMIF_BAD_PARAM;
+ break;
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_CachePrefetchingDisable
+****************************************************************************//**
+*
+* This function is used to disable pre-fetching for the fast cache, the slow
+* cache or both
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cacheType
+* Holds the type of the cache to be modified. \ref cy_en_smif_cache_en_t
+*
+* \return A status of function completion.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base,
+ cy_en_smif_cache_en_t cacheType)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ switch (cacheType)
+ {
+ case CY_SMIF_CACHE_SLOW:
+ base->SLOW_CA_CTL &= ~SMIF_SLOW_CA_CTL_PREF_EN_Msk;
+ break;
+ case CY_SMIF_CACHE_FAST:
+ base->FAST_CA_CTL &= ~SMIF_FAST_CA_CTL_PREF_EN_Msk;
+ break;
+ case CY_SMIF_CACHE_BOTH:
+ base->SLOW_CA_CTL &= ~SMIF_SLOW_CA_CTL_PREF_EN_Msk;
+ base->FAST_CA_CTL &= ~SMIF_FAST_CA_CTL_PREF_EN_Msk;
+ break;
+ default:
+ /* A user error*/
+ status = CY_SMIF_BAD_PARAM;
+ break;
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_CacheInvalidate
+****************************************************************************//**
+*
+* This function is used to invalidate/clear the fast cache, the slow cache or
+* both
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param cacheType
+* Holds the type of the cache to be modified. \ref cy_en_smif_cache_en_t
+*
+* \return A status of function completion.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base,
+ cy_en_smif_cache_en_t cacheType)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ switch (cacheType)
+ {
+ case CY_SMIF_CACHE_SLOW:
+ base->SLOW_CA_CMD |= SMIF_SLOW_CA_CMD_INV_Msk;
+ break;
+ case CY_SMIF_CACHE_FAST:
+ base->FAST_CA_CMD |= SMIF_FAST_CA_CMD_INV_Msk;
+ break;
+ case CY_SMIF_CACHE_BOTH:
+ base->SLOW_CA_CMD |= SMIF_SLOW_CA_CMD_INV_Msk;
+ base->FAST_CA_CMD |= SMIF_FAST_CA_CMD_INV_Msk;
+ break;
+ default:
+ /* A user error*/
+ status = CY_SMIF_BAD_PARAM;
+ break;
+ }
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_DeepSleepCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SMIF into and out of Deep
+* Sleep mode. It prevents the device from entering DeepSleep if SMIF is actively
+* communicating, or there is any data in the TX or RX FIFOs, or SMIF is in
+* memory mode.
+*
+* This function should be called while execution of \ref Cy_SysPm_DeepSleep
+* therefore must be registered as a callback before the call. To register it
+* call \ref Cy_SysPm_RegisterCallback and specify \ref CY_SYSPM_DEEPSLEEP
+* as the callback type.
+*
+* \note
+* This API is template and user should add code for external memory enter/exit
+* low power mode.
+*
+* \param callbackParams
+* The pointer to the structure with SMIF SysPm callback parameters (pointer to
+* SMIF registers, context and call mode \ref cy_stc_syspm_callback_params_t).
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+* Example setup of SysPM deep sleep and hibernate mode
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF SysPM Callback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SMIF_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t retStatus = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L1(NULL != callbackParams);
+
+ SMIF_Type *locBase = (SMIF_Type *) callbackParams->base;
+ cy_stc_smif_context_t *locContext = (cy_stc_smif_context_t *) callbackParams->context;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check if API is not busy executing transfer operation */
+ /* If SPI bus is not busy, all data elements are transferred on
+ * the bus from the TX FIFO and shifter and the RX FIFIOs is
+ * empty - the SPI is ready enter Deep Sleep.
+ */
+ bool checkFail = (CY_SMIF_REC_BUSY == (cy_en_smif_txfr_status_t)
+ Cy_SMIF_GetTxfrStatus(locBase, locContext));
+ checkFail = (Cy_SMIF_BusyCheck(locBase)) || checkFail;
+ checkFail = (Cy_SMIF_GetMode(locBase) == CY_SMIF_MEMORY) || checkFail;
+
+ if (checkFail)
+ {
+ retStatus = CY_SYSPM_FAIL;
+ }
+ else
+ {
+ Cy_SMIF_Disable(locBase);
+ retStatus = CY_SYSPM_SUCCESS;
+ }
+ /* Add check memory that memory not in progress */
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* Other driver is not ready for Deep Sleep. Restore Active mode
+ * configuration.
+ */
+ Cy_SMIF_Enable(locBase, locContext);
+
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* This code executes inside critical section and enabling active
+ * interrupt source makes interrupt pending in the NVIC. However
+ * interrupt processing is delayed until code exists critical
+ * section. The pending interrupt force WFI instruction does
+ * nothing and device remains in the active mode.
+ */
+
+ /* Put external memory in low power mode */
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* Put external memory in active mode */
+ Cy_SMIF_Enable(locBase, locContext);
+ }
+ break;
+
+ default:
+ retStatus = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_HibernateCallback
+****************************************************************************//**
+*
+* This function handles the transition of the SMIF into Hibernate mode.
+* It prevents the device from entering Hibernate if the SMIF
+* is actively communicating, or there is any data in the TX or RX FIFO, or SMIF
+* is in memory mode.
+*
+* This function should be called during execution of \ref Cy_SysPm_Hibernate
+* therefore it must be registered as a callback before the call. To register it
+* call \ref Cy_SysPm_RegisterCallback and specify \ref CY_SYSPM_HIBERNATE
+* as the callback type.
+*
+* \note
+* This API is template and user should add code for external memory enter/exit
+* low power mode.
+*
+* \param callbackParams
+* The pointer to the structure with SMIF SysPm callback parameters (pointer to
+* SMIF registers, context and call mode \ref cy_stc_syspm_callback_params_t).
+*
+* \return
+* \ref cy_en_syspm_status_t
+*
+* Example setup of SysPM deep sleep and hibernate mode
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF SysPM Callback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ cy_en_syspm_status_t retStatus = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L1(NULL != callbackParams);
+
+ SMIF_Type *locBase = (SMIF_Type *) callbackParams->base;
+ cy_stc_smif_context_t *locContext = (cy_stc_smif_context_t *) callbackParams->context;
+
+ switch(callbackParams->mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ /* Check if API is not busy executing transfer operation
+ * If SPI bus is not busy, all data elements are transferred on
+ * the bus from the TX FIFO and shifter and the RX FIFIOs is
+ * empty - the SPI is ready enter Deep Sleep.
+ */
+ bool checkFail = (CY_SMIF_REC_BUSY == (cy_en_smif_txfr_status_t)
+ Cy_SMIF_GetTxfrStatus(locBase, locContext));
+ checkFail = (Cy_SMIF_BusyCheck(locBase)) || checkFail;
+ checkFail = (Cy_SMIF_GetMode(locBase) == CY_SMIF_MEMORY) || checkFail;
+
+ if (checkFail)
+ {
+ retStatus = CY_SYSPM_FAIL;
+
+ }
+ else
+ {
+ retStatus = CY_SYSPM_SUCCESS;
+ Cy_SMIF_Disable(locBase);
+ }
+ /* Add check memory that memory not in progress */
+ }
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ /* Other driver is not ready for Deep Sleep. Restore Active mode
+ * configuration.
+ */
+ Cy_SMIF_Enable(locBase, locContext);
+
+ }
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ /* Put external memory in low power mode */
+ }
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ Cy_SMIF_Enable(locBase, locContext);
+ /* Put external memory in active mode */
+
+ }
+ break;
+
+ default:
+ retStatus = CY_SYSPM_FAIL;
+ break;
+ }
+
+ return (retStatus);
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1429 @@
+/***************************************************************************//**
+* \file cy_smif.h
+* \version 1.10.1
+*
+* Provides an API declaration of the Cypress SMIF driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_smif Serial Memory Interface (SMIF)
+* \{
+* The SPI-based communication interface for external memory devices.
+*
+* SMIF: Serial Memory Interface: This IP block implements an SPI-based
+* communication interface for interfacing external memory devices to PSoC. The SMIF
+* supports Octal-SPI, Dual Quad-SPI, Quad-SPI, DSPI, and SPI.
+*
+* Features
+* - Standard SPI Master interface
+* - Supports Single/Dual/Quad/Octal SPI Memories
+* - Supports Dual-Quad SPI mode
+* - Design-time configurable support for multiple (up to 4) external serial
+* memory devices
+* - eXecute-In-Place (XIP) operation mode for both read and write accesses
+* with 4KB XIP read cache and on-the-fly encryption and decryption
+* - Supports external serial memory initialization via Serial Flash
+* Discoverable Parameters (SFDP) standard
+* - Support for SPI clock frequencies up to 80 MHz
+*
+*
+* The primary usage model for the SMIF is that of an external memory interface.
+* The SMIF is capable of interfacing with different types of memory, up to four
+* types.
+*
+* \b SMIF driver is divided in next layers
+* - cy_smif.h API
+* - cy_smif_memslot.h API
+* - SMIF configuration structures
+*
+* The SMIF API is divided into the low-level functions and memory-slot functions. Use
+* the low level API for the SMIF block initialization and for implementing a generic
+* SPI communication interface using the SMIF block.
+*
+* The memory slot API has functions to implement the basic memory operations such as
+* program, read, erase etc. These functions are implemented using the memory
+* parameters in the memory device configuration data structure. The memory-slot
+* initialization API initializes all the memory slots based on the settings in the
+* array.
+*
+* \image html smif_1_0_p01_layers.png
+*
+* SMIF Configuration Tool is a stand-alone application, which is a part of PDL
+* and could be found in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool
+* (e.g. for PDL 3.0.0 and Windows OS PDL/3.0.0/tools/win/SMIFConfigurationTool). Tool
+* generates *.c and *.h file with configuration structures. These configuration
+* structures are input parameters for cy_smif_memslot API level
+*
+* \warning The driver is not responsible for external memory persistence. You cannot edit
+* a buffer during the Read/Write operations. If there is a memory error, the SMIF ip block
+* can require a reset. To determine if this has happened, check the SMIF
+* busy status using Cy_SMIF_BusyCheck() and implement a timeout. Reset the SMIF
+* block by toggling CTL.ENABLED. Then reconfigure the SMIF block.
+*
+* For the Write operation, check that the SMIF driver has completed
+* transferring by calling Cy_SMIF_BusyCheck(). Also, check that the memory is
+* available with Cy_SMIF_Memslot_IsBusy() before proceeding.
+*
+* Simple example of external flash memory programming using low level SMIF API.
+* All steps mentioned in example below are incorporated in
+* \ref Cy_SMIF_Memslot_CmdWriteEnable(), \ref Cy_SMIF_Memslot_CmdProgram(), and
+* \ref Cy_SMIF_Memslot_IsBusy() of the
+* \ref group_smif_mem_slot_functions "memory slot level API".
+* \warning Example is simplified, without checks of error conditions.
+* \note Flash memories need erase operation before programming. Refer to
+* external memory datasheet for specific memory commands.
+*
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_API: Write example
+*
+* For the Read operation, before accessing the read buffer, check that it is ready
+* by calling Cy_SMIF_GetTxFifoStatus().
+*
+* Simple example of external flash memory read using low level SMIF API. All
+* steps mentioned in example below are incorporated in
+* \ref Cy_SMIF_Memslot_CmdRead() of the
+* \ref group_smif_mem_slot_functions "memory slot level API".
+* \warning Example is simplified, without checks of error conditions.
+* \note Refer to external memory datasheet for specific memory commands.
+*
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_API: Read example
+*
+* The user should invalidate the cache by calling Cy_SMIF_CacheInvalidate() when
+* switching from the MMIO mode to XIP mode.
+*
+* \section group_smif_configuration Configuration Considerations
+*
+* PDL API has common parameters: base, context, config described in
+* \ref page_getting_started_pdl_design "PDL Design" section.
+*
+* See the documentation for Cy_SMIF_Init() and Cy_SMIF_Memslot_Init() for details
+* on the required configuration structures and other initialization topics.
+*
+* The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/Dual
+* Quad-SPI/Octal-SPI communication interface using the SMIF block. This
+* interface can be used to implement special commands like Program/Erase of
+* flash, memory device configuration, sleep mode entry for memory devices or
+* other special commands specific to the memory device. The transfer width
+* (SPI/DSP/Quad-SPI/Octal-SPI) of a transmission is a parameter set for each
+* transmit/receive operation. So these can be changed at run time.
+*
+* In a typical memory interface with flash memory, the SMIF is used in the
+* memory mode when reading from the memory and it switches to the normal mode when
+* writing to flash memory.
+* A typical memory device has multiple types of commands.
+*
+* The SMIF interface can be used to transmit different types of commands. Each
+* command has different phases: command, dummy cycles, and transmit and receive
+* data which require separate APIs.
+*
+* \subsection group_smif_init SMIF Initialization
+* Create interrupt function and allocate memory for SMIF context
+* structure
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_INIT: context and interrupt
+* SMIF driver initialization for low level API usage (cysmif.h)
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_INIT: low level
+* Additional steps to initialize SMIF driver for memory slot level API usage
+* (cy_smif_memslot.h).
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_INIT: memslot level
+* \note Example does not include initialization of all needed configuration
+* structures (\ref cy_stc_smif_mem_device_cfg_t, \ref cy_stc_smif_mem_cmd_t).
+* SMIF Configuration tool generates all configuration structures needed for
+* memslot level API usage.
+*
+* \subsection group_smif_xip_init SMIF XIP Initialization
+* The eXecute In Place (XIP) is a mode of operation where read or write commands
+* to the memory device are directed through the SMIF without any use of API
+* function calls. In this mode the SMIF block maps the AHB bus-accesses to
+* external memory device addresses to make it behave similar to internal memory.
+* This allows the CPU to execute code directly from external memory. This mode
+* is not limited to code and is suitable also for data read and write accesses.
+* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_INIT: XIP
+* \note Example of input parameters initialization is in \ref group_smif_init
+* section.
+* \warning Functions that called from external memory should be declared with
+* long call attribute.
+*
+* \section group_smif_more_information More Information
+*
+* More information regarding the Serial Memory Interface can be found in the component
+* datasheet and the Technical Reference Manual (TRM).
+* More information regarding the SMIF Configuration Tool are in SMIF
+* Configuration Tool User Guide located in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool/
+* folder
+*
+* \section group_smif_MISRA MISRA-C Compliance]
+* <table class="doxtable">
+* <tr>
+* <th>MISRA rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>11.4</td>
+* <td>A</td>
+* <td>The cast is be performed between a pointer to the object type and a different pointer to the object type.</td>
+* <td>The cast from the pointer to void to the pointer to an unsigned integer does not have any unintended effect, as
+* it is a consequence of the definition of a structure based on hardware registers.</td>
+* </tr>
+* <tr>
+* <td>11.5</td>
+* <td>R</td>
+* <td>Not performed, the cast that removes any const or volatile qualification from the type addressed by a pointer.</td>
+* <td>The removal of the volatile qualification inside the function has no side effects.</td>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements will either:
+* a) have at least one-side effect however executed, or
+* b) cause control flow to change</td>
+* <td>The readback of the register is required by the hardware.</td>
+* </tr>
+* </table>
+*
+* \section group_smif_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Added Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.10</td>
+* <td>Fix write to external memory from CM0+ core. Add checks of API input parameters.
+* Minor documentation updates</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_smif_macros Macros
+* \{
+* \defgroup group_smif_macros_status Status Macros
+* \defgroup group_smif_macros_cmd Command Macros
+* \defgroup group_smif_macros_flags External Memory Flags
+* \defgroup group_smif_macros_sfdp SFDP Macros
+* \defgroup group_smif_macros_isr Interrupt Macros
+* \}
+* \defgroup group_smif_functions Functions
+* \{
+* \defgroup group_smif_low_level_functions Low Level Functions
+* \{
+* Basic flow for read/write commands using \ref Cy_SMIF_TransmitCommand
+* \ref Cy_SMIF_TransmitData \ref Cy_SMIF_ReceiveData
+* \ref Cy_SMIF_SendDummyCycles
+*
+* \image html smif_1_0_p03_rw_cmd.png
+*
+* \}
+* \defgroup group_smif_mem_slot_functions Memory Slot Functions
+* \defgroup group_smif_functions_syspm_callback Low Power Callback
+* \}
+* \defgroup group_smif_data_structures Data Structures
+* \{
+* \defgroup group_smif_data_structures_memslot SMIF Memory Description Structures
+* General hierarchy of memory structures are:
+* \image html smif_1_0_p02_memslot_stc.png
+* Top structure is \ref cy_stc_smif_block_config_t, which could have links up to
+* 4 \ref cy_stc_smif_mem_config_t which describes each connected to the SMIF
+* external memory.
+* \}
+* \defgroup group_smif_enums Enumerated Types
+*/
+
+#if !defined(CY_SMIF_H)
+#define CY_SMIF_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+#include "cy_device_headers.h"
+
+#ifndef CY_IP_MXSMIF
+ #error "The SMIF driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Constants
+****************************************/
+
+/**
+* \addtogroup group_smif_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_SMIF_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_SMIF_DRV_VERSION_MINOR 10
+
+/** One microsecond timeout for Cy_SMIF_TimeoutRun() */
+#define CY_SMIF_WAIT_1_UNIT (1U)
+
+/** The SMIF driver ID, reported as part of an unsuccessful API return status
+ * \ref cy_en_smif_status_t */
+#define CY_SMIF_ID CY_PDL_DRV_ID(0x2CU)
+
+
+/**
+* \addtogroup group_smif_macros_isr
+* \{
+*/
+
+/** Enable XIP_ALIGNMENT_ERROR interrupt see TRM for details */
+#define CY_SMIF_ALIGNMENT_ERROR (SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk)
+/** Enable RX_DATA_FIFO_UNDERFLOW interrupt see TRM for details */
+#define CY_SMIF_RX_DATA_FIFO_UNDERFLOW (SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk)
+/** Enable TX_DATA_FIFO_OVERFLOW interrupt see TRM for details */
+#define CY_SMIF_TX_DATA_FIFO_OVERFLOW (SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk)
+/** Enable TX_CMD_FIFO_OVERFLOW interrupt see TRM for details */
+#define CY_SMIF_TX_COMMAND_FIFO_OVERFLOW (SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk)
+/** Enable TR_TX_REQ interrupt see TRM for details */
+#define CY_SMIF_TX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_TX_REQ_Msk)
+/** Enable TR_RX_REQ interrupt see TRM for details */
+#define CY_SMIF_RX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_RX_REQ_Msk)
+
+/** \} group_smif_macros_isr */
+
+/** \cond INTERNAL */
+
+#define CY_SMIF_CMD_FIFO_TX_MODE (0UL)
+#define CY_SMIF_CMD_FIFO_TX_COUNT_MODE (1UL)
+#define CY_SMIF_CMD_FIFO_RX_COUNT_MODE (2UL)
+#define CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE (3UL)
+
+#define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (4U)
+#define CY_SMIF_TX_DATA_FIFO_STATUS_RANGE (8U)
+#define CY_SMIF_RX_DATA_FIFO_STATUS_RANGE (8U)
+
+#define CY_SMIF_ONE_BYTE (1U)
+#define CY_SMIF_TWO_BYTES (2U)
+#define CY_SMIF_THREE_BYTES (3U)
+#define CY_SMIF_FOUR_BYTES (4U)
+#define CY_SMIF_FIVE_BYTES (5U)
+#define CY_SMIF_SIX_BYTES (6U)
+#define CY_SMIF_SEVEN_BYTES (7U)
+#define CY_SMIF_EIGHT_BYTES (8U)
+
+#define CY_SMIF_CRYPTO_FIRST_WORD (0U)
+#define CY_SMIF_CRYPTO_SECOND_WORD (4U)
+#define CY_SMIF_CRYPTO_THIRD_WORD (8U)
+#define CY_SMIF_CRYPTO_FOURTH_WORD (12U)
+
+#define CY_SMIF_CRYPTO_START (1UL)
+#define CY_SMIF_CRYPTO_COMPLETED (0UL)
+#define CY_SMIF_CRYPTO_ADDR_MASK (0xFFFFFFF0UL)
+#define CY_SMIF_AES128_BYTES (16U)
+
+#define CY_SMIF_CTL_REG_DEFAULT (0x00000300U) /* 3 - [13:12] CLOCK_IF_RX_SEL */
+
+#define CY_SMIF_SFDP_FAIL (0x08U)
+#define CY_SMIF_SFDP_FAIL_SS0_POS (0x00U)
+#define CY_SMIF_SFDP_FAIL_SS1_POS (0x01U)
+#define CY_SMIF_SFDP_FAIL_SS2_POS (0x02U)
+#define CY_SMIF_SFDP_FAIL_SS3_POS (0x03U)
+
+#define CY_SMIF_MAX_DESELECT_DELAY (7U)
+#define CY_SMIF_MAX_TX_TR_LEVEL (8U)
+#define CY_SMIF_MAX_RX_TR_LEVEL (8U)
+
+#define CY_SMIF_MODE_VALID(mode) ((CY_SMIF_NORMAL == (cy_en_smif_mode_t)(mode)) || \
+ (CY_SMIF_MEMORY == (cy_en_smif_mode_t)(mode)))
+#define CY_SMIF_BLOCK_EVENT_VALID(event) ((CY_SMIF_BUS_ERROR == (cy_en_smif_error_event_t)(event)) || \
+ (CY_SMIF_WAIT_STATES == (cy_en_smif_error_event_t)(event)))
+#define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_INV_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
+ (CY_SMIF_SEL_INV_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))
+
+#define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY)
+#define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_1 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_2 == (ss)) || \
+ (CY_SMIF_SLAVE_SELECT_3 == (ss)))
+#define CY_SMIF_DATA_SEL_VALID(ss) ((CY_SMIF_DATA_SEL0 == (ss)) || \
+ (CY_SMIF_DATA_SEL1 == (ss)) || \
+ (CY_SMIF_DATA_SEL2 == (ss)) || \
+ (CY_SMIF_DATA_SEL3 == (ss)))
+#define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \
+ (CY_SMIF_WIDTH_DUAL == (width)) || \
+ (CY_SMIF_WIDTH_QUAD == (width)) || \
+ (CY_SMIF_WIDTH_OCTAL == (width)))
+#define CY_SMIF_CMD_PARAM_VALID(param, paramSize) (((paramSize) > 0U)? (NULL != (param)) : (true))
+
+/***************************************
+* Command FIFO Register
+***************************************/
+
+/* SMIF->TX_CMD_FIFO_WR */
+#define CY_SMIF_TX_CMD_FIFO_WR_MODE_POS (18U) /* [19:18] Command data mode */
+#define CY_SMIF_TX_CMD_FIFO_WR_WIDTH_POS (16U) /* [17:16] Transfer width */
+#define CY_SMIF_TX_CMD_FIFO_WR_LAST_BYTE_POS (15U) /* [15] Last byte */
+#define CY_SMIF_TX_CMD_FIFO_WR_SS_POS (8U) /* [11:8] Slave select */
+#define CY_SMIF_TX_CMD_FIFO_WR_TXDATA_POS (0U) /* [0] Transmitted byte */
+#define CY_SMIF_TX_CMD_FIFO_WR_DUMMY_POS (0U) /* [0] Dummy count */
+#define CY_SMIF_TX_CMD_FIFO_WR_TX_COUNT_POS (0U) /* [0] TX count */
+#define CY_SMIF_TX_CMD_FIFO_WR_RX_COUNT_POS (0U) /* [0] RX count */
+
+/* SMIF->TX_CMD_FIFO_WR Commands Fields */
+#define CY_SMIF_CMD_FIFO_WR_MODE_Pos (18UL) /* [19:18] Command data mode */
+#define CY_SMIF_CMD_FIFO_WR_MODE_Msk (0x000C0000UL) /* DATA[19:18] Command data mode */
+
+#define CY_SMIF_CMD_FIFO_WR_WIDTH_Pos (16UL) /* [17:16] Transfer width */
+#define CY_SMIF_CMD_FIFO_WR_WIDTH_Msk (0x00030000UL) /* DATA[17:16] Transfer width */
+
+#define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Pos (15UL) /* [15] Last byte */
+#define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Msk (0x00008000UL) /* DATA[15] Last byte */
+
+#define CY_SMIF_CMD_FIFO_WR_SS_Pos (8UL) /* [11:8] Slave select */
+#define CY_SMIF_CMD_FIFO_WR_SS_Msk (0x00000F00UL) /* DATA[11:8] Slave select */
+
+#define CY_SMIF_CMD_FIFO_WR_TXDATA_Pos (0UL) /* [0] Transmitted byte */
+#define CY_SMIF_CMD_FIFO_WR_TXDATA_Msk (0x000000FFUL) /* DATA[7:0] Transmitted byte */
+#define CY_SMIF_CMD_FIFO_WR_DUMMY_Pos (0UL) /* [0] Dummy count */
+#define CY_SMIF_CMD_FIFO_WR_DUMMY_Msk (0x0000FFFFUL) /* DATA[15:0] Dummy count */
+#define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] TX count */
+#define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Pos (0UL) /* [0] TX count */
+#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk (0x0003FFFFUL) /* DATA[17:0] RX count */
+#define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Pos (0UL) /* [0] RX count */
+
+/** \endcond*/
+/** \} group_smif_macros */
+
+
+/**
+* \addtogroup group_smif_enums
+* \{
+*/
+
+/** The Transfer width options for the command, data, the address and the mode. */
+typedef enum
+{
+ CY_SMIF_WIDTH_SINGLE = 0U, /**< Normal SPI mode. */
+ CY_SMIF_WIDTH_DUAL = 1U, /**< Dual SPI mode. */
+ CY_SMIF_WIDTH_QUAD = 2U, /**< Quad SPI mode. */
+ CY_SMIF_WIDTH_OCTAL = 3U /**< Octal SPI mode. */
+} cy_en_smif_txfr_width_t;
+
+/** The SMIF error-event selection. */
+typedef enum
+{
+ /**< Generates a bus error. */
+ CY_SMIF_BUS_ERROR = 0UL,
+ /** Stalls the bus with the wait states. This option will increase the
+ * interrupt latency.
+ */
+ CY_SMIF_WAIT_STATES = 1UL
+} cy_en_smif_error_event_t;
+
+/** The data line-selection options for a slave device. */
+typedef enum
+{
+ /**
+ * smif.spi_data[0] = DATA0, smif.spi_data[1] = DATA1, ..., smif.spi_data[7] = DATA7.
+ * This value is allowed for the SPI, DSPI, quad-SPI, dual quad-SPI, and octal-SPI modes.
+ */
+ CY_SMIF_DATA_SEL0 = 0,
+ /**
+ * smif.spi_data[2] = DATA0, smif.spi_data[3] = DATA1.
+ * This value is only allowed for the SPI and DSPI modes.
+ */
+ CY_SMIF_DATA_SEL1 = 1,
+ /**
+ * smif.spi_data[4] = DATA0, smif.spi_data[5] = DATA1, ..., smif.spi_data[7] = DATA3.
+ * This value is only allowed for the SPI, DSPI, quad-SPI and dual quad-SPI modes.
+ */
+ CY_SMIF_DATA_SEL2 = 2,
+ /**
+ * smif.spi_data[6] = DATA0, smif.spi_data[7] = DATA1.
+ * This value is only allowed for the SPI and DSPI modes.
+ */
+ CY_SMIF_DATA_SEL3 = 3
+} cy_en_smif_data_select_t;
+
+/** The SMIF modes to work with an external memory. */
+typedef enum
+{
+ CY_SMIF_NORMAL, /**< Command mode (MMIO mode). */
+ CY_SMIF_MEMORY /**< XIP (eXecute In Place) mode. */
+} cy_en_smif_mode_t;
+
+/** The SMIF transfer status return values. */
+typedef enum
+{
+ CY_SMIF_STARTED, /**< The SMIF started. */
+ CY_SMIF_SEND_CMPLT, /**< The data transmission is complete. */
+ CY_SMIF_SEND_BUSY, /**< The data transmission is in progress. */
+ CY_SMIF_REC_CMPLT, /**< The data reception is completed. */
+ CY_SMIF_REC_BUSY, /**< The data reception is in progress. */
+ CY_SMIF_XIP_ERROR, /**< An XIP alignment error. */
+ CY_SMIF_CMD_ERROR, /**< A TX CMD FIFO overflow. */
+ CY_SMIF_TX_ERROR, /**< A TX DATA FIFO overflow. */
+ CY_SMIF_RX_ERROR /**< An RX DATA FIFO underflow. */
+
+} cy_en_smif_txfr_status_t;
+
+/** The SMIF API return values. */
+typedef enum
+{
+ CY_SMIF_SUCCESS = 0x00U, /**< Successful SMIF operation. */
+ CY_SMIF_CMD_FIFO_FULL = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x01U, /**< The command is cancelled. The command FIFO is full. */
+ CY_SMIF_EXCEED_TIMEOUT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x02U, /**< The SMIF operation timeout exceeded. */
+ /**
+ * The device does not have a QE bit. The device detects
+ * 1-1-4 and 1-4-4 Reads based on the instruction.
+ */
+ CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U,
+ CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */
+ CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */
+ /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS),
+ /** Failed to initialize the slave select 1 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS1_FAILED = CY_SMIF_ID | CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS1_POS),
+ /** Failed to initialize the slave select 2 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS2_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS2_POS),
+ /** Failed to initialize the slave select 3 external memory by auto detection (SFDP). */
+ CY_SMIF_SFDP_SS3_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
+ ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS3_POS)
+
+} cy_en_smif_status_t;
+
+/** The SMIF slave select definitions for the driver API. Each slave select is
+ * represented by an enumeration that has the bit corresponding to the slave
+ * select number set. */
+typedef enum
+{
+ CY_SMIF_SLAVE_SELECT_0 = 1U, /**< The SMIF slave select 0 */
+ CY_SMIF_SLAVE_SELECT_1 = 2U, /**< The SMIF slave select 1 */
+ CY_SMIF_SLAVE_SELECT_2 = 4U, /**< The SMIF slave select 2 */
+ CY_SMIF_SLAVE_SELECT_3 = 8U /**< The SMIF slave select 3 */
+} cy_en_smif_slave_select_t;
+
+/** Specifies the clock source for the receiver clock. */
+typedef enum
+{
+ CY_SMIF_SEL_INTERNAL_CLK = 0U, /**< The SMIF internal clock */
+ CY_SMIF_SEL_INV_INTERNAL_CLK = 1U, /**< The SMIF internal inverted clock */
+ CY_SMIF_SEL_FEEDBACK_CLK = 2U, /**< The SMIF feedback clock */
+ CY_SMIF_SEL_INV_FEEDBACK_CLK = 3U /**< The SMIF feedback inverted clock */
+} cy_en_smif_clk_select_t;
+
+/** Specifies enabled type of SMIF cache. */
+typedef enum
+{
+ CY_SMIF_CACHE_SLOW = 1U, /**< The SMIF slow cache (in the clk_slow domain) see TRM for details */
+ CY_SMIF_CACHE_FAST = 2U, /**< The SMIF fast cache (in the clk_fast domain) see TRM for details */
+ CY_SMIF_CACHE_BOTH = 3U /**< The SMIF both caches */
+} cy_en_smif_cache_en_t;
+
+/** \} group_smif_enums */
+
+
+/**
+* \addtogroup group_smif_data_structures
+* \{
+*/
+
+/***************************************************************************//**
+*
+* The SMIF user callback function type called at the end of a transfer.
+*
+* \param event
+* The event which caused a callback call.
+*
+*******************************************************************************/
+typedef void (*cy_smif_event_cb_t)(uint32_t event);
+
+
+/** The SMIF configuration structure. */
+typedef struct
+{
+ uint32_t mode; /**< Specifies the mode of operation \ref cy_en_smif_mode_t. */
+ uint32_t deselectDelay; /**< Specifies the minimum duration of SPI de-selection between SPI transfers:
+ * - "0": 1 clock cycle.
+ * - "1": 2 clock cycles.
+ * - "2": 3 clock cycles.
+ * - "3": 4 clock cycles.
+ * - "4": 5 clock cycles.
+ * - "5": 6 clock cycles.
+ * - "6": 7 clock cycles.
+ * - "7": 8 clock cycles. */
+ uint32_t rxClockSel; /**< Specifies the clock source for the receiver
+ * clock \ref cy_en_smif_clk_select_t. */
+ uint32_t blockEvent; /**< Specifies what happens when there is a Read
+ * from an empty RX FIFO or a Write to a full
+ * TX FIFO. \ref cy_en_smif_error_event_t. */
+} cy_stc_smif_config_t;
+
+/** The SMIF internal context data. The user must not modify it. */
+typedef struct
+{
+ uint8_t volatile * volatile txBufferAddress; /**< The pointer to the data to transfer */
+ uint32_t txBufferSize; /**< The size of the data to transmit in bytes */
+ /**
+ * The transfer counter. The number of the transmitted bytes = txBufferSize - txBufferCounter
+ */
+ uint32_t volatile txBufferCounter;
+ uint8_t volatile * volatile rxBufferAddress; /**< The pointer to the variable where the received data is stored */
+ uint32_t rxBufferSize; /**< The size of the data to be received in bytes */
+ /**
+ * The transfer counter. The number of the received bytes = rxBufferSize - rxBufferCounter
+ */
+ uint32_t volatile rxBufferCounter;
+ /**
+ * The status of the transfer. The transmitting / receiving is completed / in progress
+ */
+ uint32_t volatile transferStatus;
+ cy_smif_event_cb_t volatile txCmpltCb; /**< The user-defined callback executed at the completion of a transmission */
+ cy_smif_event_cb_t volatile rxCmpltCb; /**< The user-defined callback executed at the completion of a reception */
+ /**
+ * The timeout in microseconds for the blocking functions. This timeout value applies to all blocking APIs.
+ */
+ uint32_t timeout;
+} cy_stc_smif_context_t;
+
+/** \} group_smif_data_structures */
+
+
+/**
+* \addtogroup group_smif_low_level_functions
+* \{
+*/
+
+cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base, cy_stc_smif_config_t const *config,
+ uint32_t timeout,
+ cy_stc_smif_context_t *context);
+void Cy_SMIF_DeInit(SMIF_Type *base);
+void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect,
+ cy_en_smif_data_select_t dataSelect);
+void Cy_SMIF_SetMode(SMIF_Type *base, cy_en_smif_mode_t mode);
+cy_en_smif_mode_t Cy_SMIF_GetMode(SMIF_Type const *base);
+cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
+ uint8_t cmd,
+ cy_en_smif_txfr_width_t cmdTxfrWidth,
+ uint8_t const cmdParam[], uint32_t paramSize,
+ cy_en_smif_txfr_width_t paramTxfrWidth,
+ cy_en_smif_slave_select_t slaveSelect, uint32_t cmpltTxfr,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base,
+ uint8_t *txBuffer, uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t TxCmpltCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
+ uint8_t *txBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base,
+ uint8_t *rxBuffer, uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_smif_event_cb_t RxCmpltCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base,
+ uint8_t *rxBuffer,
+ uint32_t size,
+ cy_en_smif_txfr_width_t transferWidth,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base, uint32_t cycles);
+uint32_t Cy_SMIF_GetTxfrStatus(SMIF_Type *base, cy_stc_smif_context_t const *context);
+void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context);
+__STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base);
+__STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base);
+__STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt);
+__STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
+__STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
+__STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base);
+__STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base);
+cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
+ uint32_t address,
+ uint8_t data[],
+ uint32_t size,
+ cy_stc_smif_context_t const *context);
+__STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base);
+__STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base, cy_en_smif_cache_en_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base, cy_en_smif_cache_en_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingEnable(SMIF_Type *base, cy_en_smif_cache_en_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base, cy_en_smif_cache_en_t cacheType);
+cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base, cy_en_smif_cache_en_t cacheType);
+
+/** \addtogroup group_smif_functions_syspm_callback
+* The driver supports SysPm callback for Deep Sleep and Hibernate transition.
+* \{
+*/
+cy_en_syspm_status_t Cy_SMIF_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} */
+
+
+/***************************************
+* Internal SMIF function declarations
+****************************************/
+/** \cond INTERNAL */
+__STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Writes transmitted data into the FIFO. */
+__STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Reads received data from the FIFO. */
+__STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes);
+__STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes);
+__STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits);
+__STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
+ cy_en_smif_slave_select_t slaveSelect);
+/** \endcond*/
+
+/** \} group_smif_low_level_functions */
+
+
+/**
+* \addtogroup group_smif_low_level_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Disable
+****************************************************************************//**
+*
+* Disables the operation of the SMIF block. The SMIF block can be disabled only
+* when it is not in the active state. Use the Cy_SMIF_BusyCheck() API to check
+* it before calling this API.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base)
+{
+ base->CTL &= ~SMIF_CTL_ENABLED_Msk;
+
+ /* The void Read of the CTL register to handle buffering */
+ (void) base->CTL;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetInterruptMask
+****************************************************************************//**
+*
+* This function is used to set an interrupt mask for the SMIF Interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* This is the mask for different source options that can be masked. See
+* \ref group_smif_macros_isr "Interrupt Macros" for possible values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt)
+{
+ base->INTR_MASK = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptMask
+****************************************************************************//**
+*
+* This function is used to read an interrupt mask for the SMIF Interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the mask set for the SMIF interrupt.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base)
+{
+ return (base->INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* This function is used to read an active masked interrupt. This function can
+* be used in the interrupt service-routine to find which source triggered the
+* interrupt.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns a word with bits set at positions corresponding to the
+* interrupts triggered in the system.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base)
+{
+ return (base->INTR_MASKED);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetInterruptStatus
+****************************************************************************//**
+*
+* This function is used to read an active interrupt. This status is the unmasked
+* result, so will also show interrupts that will not generate active interrupts.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns a word with bits set at positions corresponding to the
+* interrupts triggered in the system.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base)
+{
+ return (base->INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetInterrupt
+****************************************************************************//**
+*
+* This function is used to set an interrupt source. This function can be used
+* to activate interrupts through the software.
+*
+* \note Interrupt sources set using this interrupt will generate interrupts only
+* if they are not masked.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* An encoded integer with a bit set corresponding to the interrupt to be
+* triggered. See \ref group_smif_macros_isr "Interrupt Macros" for possible
+* values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt)
+{
+ base->INTR_SET = interrupt;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_ClearInterrupt
+****************************************************************************//**
+*
+* This function is used to clear an interrupt source. This function can be used
+* in the user code to clear all pending interrupts.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param interrupt
+* An encoded integer with a bit set corresponding to the interrupt that must
+* be cleared. See \ref group_smif_macros_isr "Interrupt Macros" for possible
+* values.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt)
+{
+ base->INTR = interrupt;
+ /* Ensure that the initial Write has been flushed out to the hardware. */
+ interrupt = base->INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetTxFifoTriggerLevel()
+****************************************************************************//**
+*
+* This function is used to set a trigger level for the TX FIFO. This value must
+* be an integer between 0 and 7. For the normal mode only.
+* The triggering is active when TX_DATA_FIFO_STATUS <= level.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param level
+* The trigger level to set (0-8).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(level <= CY_SMIF_MAX_TX_TR_LEVEL);
+ base->TX_DATA_FIFO_CTL = level;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_SetRxFifoTriggerLevel()
+****************************************************************************//**
+*
+* This function is used to set a trigger level for the RX FIFO. This value must
+* be an integer between 0 and 7. For the normal mode only.
+* The triggering is active when RX_DATA_FIFOSTATUS > level.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param level
+* The trigger level to set(0-8).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
+{
+ CY_ASSERT_L2(level <= CY_SMIF_MAX_RX_TR_LEVEL);
+ base->RX_DATA_FIFO_CTL = level;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetCmdFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the CMD FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the CMD FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_TX_CMD_FIFO_STATUS_USED3, base->TX_CMD_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetTxFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the TX FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_TX_DATA_FIFO_STATUS_USED4, base->TX_DATA_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetRxFifoStatus()
+****************************************************************************//**
+*
+* This function is used to read the status of the RX FIFO.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns the number of the entries in the RX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base)
+{
+ return (_FLD2VAL(SMIF_RX_DATA_FIFO_STATUS_USED4, base->RX_DATA_FIFO_STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_BusyCheck
+****************************************************************************//**
+*
+* This function provides the status of the IP block (False - not busy,
+* True - busy).
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \return Returns an IP block status.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base)
+{
+ return (1ul == _FLD2VAL(SMIF_STATUS_BUSY, base->STATUS));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Interrupt
+****************************************************************************//**
+*
+* The Interrupt Service Routine for the SMIF. The interrupt code will be
+* responsible for the FIFO operations on FIFO interrupts during ongoing transfers.
+* The user must place a call to this interrupt function in the interrupt
+* routine corresponding to the interrupt attached to the SMIF. If the
+* user does not do this, will break: the functionality of all the API functions in
+* the SMIF driver that use SMIF interrupts to affect transfers.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* \globalvars
+* - context->txBufferAddress - The pointer to the data to be transferred.
+*
+* - context->txBufferSize - The size of txBuffer.
+*
+* - context->txBufferCounter - The number of data entries left to be transferred.
+*
+* All the Global variables described above are used when the Software Buffer is
+* used.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context)
+{
+ uint32_t interruptStatus = Cy_SMIF_GetInterruptStatusMasked(base);
+
+ /* Check which interrupt occurred */
+ if (0U != (interruptStatus & SMIF_INTR_TR_TX_REQ_Msk))
+ {
+ /* Send data */
+ Cy_SMIF_PushTxFifo(base, context);
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_TX_REQ_Msk);
+ }
+ else if (0U != (interruptStatus & SMIF_INTR_TR_RX_REQ_Msk))
+ {
+ /* Receive data */
+ Cy_SMIF_PopRxFifo(base, context);
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_RX_REQ_Msk);
+ }
+ else if (0U != (interruptStatus & SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk))
+ {
+ /* An XIP alignment error */
+ context->transferStatus = (uint32_t) CY_SMIF_XIP_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk))
+ {
+ /* TX CMD FIFO overflow */
+ context->transferStatus = (uint32_t) CY_SMIF_CMD_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk))
+ {
+ /* A TX DATA FIFO overflow */
+ context->transferStatus = (uint32_t) CY_SMIF_TX_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk);
+ }
+
+ else if (0U != (interruptStatus & SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk))
+ {
+ /* RX DATA FIFO underflow */
+ context->transferStatus = (uint32_t) CY_SMIF_RX_ERROR;
+
+ Cy_SMIF_ClearInterrupt(base, SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk);
+ }
+ else
+ {
+ /* Processing of errors */
+ }
+}
+
+
+/***************************************
+* Internal SMIF in-line functions
+****************************************/
+
+/** \cond INTERNAL */
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PushTxFifo
+***************************************************************************//***
+*
+* \internal
+*
+* \param baseaddr
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* This function writes data in the TX FIFO SMIF buffer by 4, 2, or 1 bytes based
+* on the residual number of bytes and the available space in the TX FIFO.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
+{
+ /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be sent */
+ uint32_t writeBytes;
+ uint32_t freeFifoBytes;
+ uint32_t buffCounter = context->txBufferCounter;
+ uint8_t *buff = (uint8_t*) context->txBufferAddress;
+
+ freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
+ writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
+
+ /* Check that after a FIFO Write, no data/FIFO space remains */
+ while (0U != writeBytes)
+ {
+ /* The first main use case for long transfers */
+ if (writeBytes == CY_SMIF_EIGHT_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[4U], true);
+ }
+ /* The second main use case for short transfers */
+ else if(writeBytes == CY_SMIF_ONE_BYTE)
+ {
+ baseaddr->TX_DATA_FIFO_WR1 = buff[0U];
+ }
+ else if(writeBytes == CY_SMIF_TWO_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR2 = Cy_SMIF_PackBytesArray(&buff[0U], false);
+ }
+ else if(writeBytes == CY_SMIF_THREE_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR2 = Cy_SMIF_PackBytesArray(&buff[0U], false);
+ baseaddr->TX_DATA_FIFO_WR1 = buff[2U];
+ }
+ else if(writeBytes == CY_SMIF_FOUR_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ }
+ else if(writeBytes == CY_SMIF_FIVE_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ baseaddr->TX_DATA_FIFO_WR1 = buff[4U];
+ }
+ else if(writeBytes == CY_SMIF_SIX_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ baseaddr->TX_DATA_FIFO_WR2 = Cy_SMIF_PackBytesArray(&buff[4U], false);
+ }
+ else if(writeBytes == CY_SMIF_SEVEN_BYTES)
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ baseaddr->TX_DATA_FIFO_WR2 = Cy_SMIF_PackBytesArray(&buff[4U], false);
+ baseaddr->TX_DATA_FIFO_WR1 = buff[6U];
+ }
+ else /* The future IP block with FIFO > 8*/
+ {
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[0U], true);
+ baseaddr->TX_DATA_FIFO_WR4 = Cy_SMIF_PackBytesArray(&buff[4U], true);
+ writeBytes = CY_SMIF_EIGHT_BYTES;
+ }
+ buff = &buff[writeBytes];
+ buffCounter -= writeBytes;
+ /* Check if we already got new data in TX_FIFO*/
+ freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
+ writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
+ }
+
+ /* Save changes in the context */
+ context->rxBufferAddress = buff;
+ context->rxBufferCounter = buffCounter;
+
+ /* Check if all bytes are sent */
+ if (0u == buffCounter)
+ {
+ /* Disable the TR_TX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(baseaddr,
+ Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_TX_REQ_Msk);
+
+ context->transferStatus = (uint32_t) CY_SMIF_SEND_CMPLT;
+ if (NULL != context->txCmpltCb)
+ {
+ context->txCmpltCb((uint32_t) CY_SMIF_SEND_CMPLT);
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PopRxFifo
+***************************************************************************//***
+*
+* \internal
+*
+* \param baseaddr
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* Passes a configuration structure that contains the transfer parameters of the
+* SMIF block.
+*
+* This function reads data from the RX FIFO SMIF buffer by 4, 2, or 1 bytes
+* based on the data availability in the RX FIFO and amount of bytes to be
+* received.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
+{
+ /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be received */
+ uint32_t readBytes;
+ uint32_t loadedFifoBytes;
+ uint32_t buffCounter = context->rxBufferCounter;
+ uint8_t *buff = (uint8_t*) context->rxBufferAddress;
+
+ loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
+ readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
+
+ /* Check that after a FIFO Read, no new data is available */
+ while (0U != readBytes)
+ {
+ if (readBytes == CY_SMIF_EIGHT_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[4U], true);
+ }
+ else if(readBytes == CY_SMIF_ONE_BYTE)
+ {
+ buff[0U] = (uint8_t)baseaddr->RX_DATA_FIFO_RD1;
+ }
+ else if(readBytes == CY_SMIF_TWO_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD2, &buff[0U], false);
+ }
+ else if(readBytes == CY_SMIF_THREE_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD2, &buff[0U], false);
+ buff[2U] = (uint8_t)baseaddr->RX_DATA_FIFO_RD1;
+ }
+ else if(readBytes == CY_SMIF_FOUR_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ }
+ else if(readBytes == CY_SMIF_FIVE_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ buff[4U] = (uint8_t)baseaddr->RX_DATA_FIFO_RD1;
+ }
+ else if(readBytes == CY_SMIF_SIX_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD2, &buff[4U], false);
+ }
+ else if(readBytes == CY_SMIF_SEVEN_BYTES)
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD2, &buff[4U], false);
+ buff[6U] = (uint8_t)baseaddr->RX_DATA_FIFO_RD1;
+ }
+ else /* The IP block FIFO > 8*/
+ {
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[0U], true);
+ Cy_SMIF_UnPackByteArray(baseaddr->RX_DATA_FIFO_RD4, &buff[4U], true);
+ readBytes = CY_SMIF_EIGHT_BYTES;
+ }
+
+ buff = &buff[readBytes];
+ buffCounter -= readBytes;
+ /* Check if we already got new data in RX_FIFO*/
+ loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
+ readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
+ }
+
+ /* Save changes in the context */
+ context->rxBufferAddress = buff;
+ context->rxBufferCounter = buffCounter;
+
+ /* Check if all bytes are received */
+ if (0UL == buffCounter)
+ {
+ /* Disable the TR_RX_REQ interrupt */
+ Cy_SMIF_SetInterruptMask(baseaddr,
+ Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_RX_REQ_Msk);
+ context->transferStatus = (uint32_t) CY_SMIF_REC_CMPLT;
+ if (NULL != context->rxCmpltCb)
+ {
+ context->rxCmpltCb((uint32_t) CY_SMIF_REC_CMPLT);
+ }
+ }
+
+ context->rxBufferCounter = buffCounter;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_PackBytesArray
+***************************************************************************//***
+*
+* \internal
+*
+* This function packs 0-numBytes of the buff byte array into a 4-byte value.
+*
+* \param buff
+* The byte array to pack.
+*
+* \param fourBytes
+* - The True pack is for a 32-bit value.
+* - The False pack is for a 16-bit value.
+*
+* \return
+* The 4-byte value packed from the byte array.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes)
+{
+ uint32_t result = 0UL;
+
+ result = ((uint32_t)buff[1UL] << 8UL) | (uint32_t)buff[0UL];
+
+ if(fourBytes)
+ {
+ result |= ((uint32_t)buff[3UL] << 24UL) | ((uint32_t)buff[2UL] << 16UL);
+ }
+
+ return result;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_UnPackByteArray
+***************************************************************************//***
+*
+* \internal
+*
+* This function unpacks 0-numBytes from a 4-byte value into the byte array outBuff.
+*
+* \param smifReg
+* The 4-byte value to unpack.
+*
+* \param outBuff
+* The byte array to fill.
+*
+* \param fourBytes
+* - The True unpack is for a 32-bit value.
+* - The False unpack is for a 16-bit value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes)
+{
+ outBuff[0UL] = (uint8_t)(inValue & 0xFFUL);
+ outBuff[1UL] = (uint8_t)((inValue >> 8UL ) & 0xFFUL);
+
+ if(fourBytes)
+ {
+ outBuff[2UL] = (uint8_t)((inValue >> 16UL) & 0xFFUL);
+ outBuff[3UL] = (uint8_t)((inValue >> 24UL) & 0xFFUL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_TimeoutRun
+****************************************************************************//**
+*
+* \internal
+*
+* This function checks if the timeout is expired. Use the Cy_SysLib_DelayUs() function for
+* implementation.
+*
+* \param timeoutUnits
+* The pointer to the timeout. The timeout measured in microseconds is multiplied by
+* CY_SMIF_WAIT_1_UNIT.
+*
+* \return
+* A timeout status:
+* - \ref CY_SMIF_SUCCESS - The timeout has not expired or input timeoutUnits is 0.
+* - \ref CY_SMIF_EXCEED_TIMEOUT - The timeout has expired.
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits)
+{
+ cy_en_smif_status_t status = CY_SMIF_SUCCESS;
+ if (*timeoutUnits > 0u)
+ {
+ Cy_SysLib_DelayUs(CY_SMIF_WAIT_1_UNIT);
+ --(*timeoutUnits);
+ status = (0u == (*timeoutUnits))? CY_SMIF_EXCEED_TIMEOUT: CY_SMIF_SUCCESS;
+ }
+ return status;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_GetDeviceBySlot
+****************************************************************************//**
+*
+* \internal
+* This function returns the address of the SMIF device registers structure by the slave
+* slot number.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param slaveSlot
+* The slave device ID. This number is either CY_SMIF_SLAVE_SELECT_0 or
+* CY_SMIF_SLAVE_SELECT_1 or CY_SMIF_SLAVE_SELECT_2 or CY_SMIF_SLAVE_SELECT_3
+* (\ref cy_en_smif_slave_select_t). It defines the slave-select line to use
+* during the transmission.
+*
+*******************************************************************************/
+__STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
+ cy_en_smif_slave_select_t slaveSelect)
+{
+ SMIF_DEVICE_Type volatile *device;
+ /* Connect the slave to its data lines */
+ switch (slaveSelect)
+ {
+ case CY_SMIF_SLAVE_SELECT_0:
+ device = &(base->DEVICE[0]);
+ break;
+ case CY_SMIF_SLAVE_SELECT_1:
+ device = &(base->DEVICE[1]);
+ break;
+ case CY_SMIF_SLAVE_SELECT_2:
+ device = &(base->DEVICE[2]);
+ break;
+ case CY_SMIF_SLAVE_SELECT_3:
+ device = &(base->DEVICE[3]);
+ break;
+ default:
+ /* A user error*/
+ device = NULL;
+ break;
+ }
+
+ return device;
+}
+
+/** \endcond */
+/** \} group_smif_low_level_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* (CY_SMIF_H) */
+
+/** \} group_smif */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif_memslot.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1373 @@
+/***************************************************************************//**
+* \file cy_smif_memslot.c
+* \version 1.10.1
+*
+* \brief
+* This file provides the source code for the memory-level APIs of the SMIF driver.
+*
+* Note:
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_smif_memslot.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+* Function Prototypes
+***************************************/
+static void Cy_SMIF_Memslot_XipRegInit(SMIF_DEVICE_Type volatile *dev,
+ cy_stc_smif_mem_config_t const * memCfg);
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_Init
+****************************************************************************//**
+*
+* This function initializes the slots of the memory device in the SMIF
+* configuration. After this initialization, the memory slave devices are
+* automatically mapped into the PSoC memory map. The function needs the SMIF
+* to be running in the memory mode to have the memory mapped into the PSoC
+* address space. This function is typically called in the System initialization
+* phase to initialize all the memory-mapped SMIF devices.
+* This function only configures the memory device portion of the SMIF
+* initialization and therefore assumes that the SMIF blocks initialization is
+* achieved using Cy_SMIF_Init(). The cy_stc_smif_context_t context structure
+* returned from Cy_SMIF_Init() is passed as a parameter to this function.
+* This function calls the \ref Cy_SMIF_Memslot_SfdpDetect() function for each
+* element of the \ref cy_stc_smif_mem_config_t memConfig array and fills the memory
+* parameters if the autoDetectSfdp field is enabled in \ref cy_stc_smif_mem_config_t.
+* The filled memConfig is a part of the \ref cy_stc_smif_block_config_t * blockConfig
+* structure. The function expects that all the requirements of
+* \ref Cy_SMIF_Memslot_SfdpDetect() is provided.
+*
+* \param base
+* The address of the slave-slot device register to initialize.
+*
+* \param context
+* The SMIF internal context structure of the block.
+*
+* \param blockConfig
+* The configuration structure array that configures the SMIF memory device to be
+* mapped into the PSoC memory map. \ref cy_stc_smif_mem_config_t
+*
+* \return The memory slot initialization status.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base,
+ cy_stc_smif_block_config_t * const blockConfig,
+ cy_stc_smif_context_t *context)
+{
+ SMIF_DEVICE_Type volatile * device;
+ cy_stc_smif_mem_config_t const * memCfg;
+ uint32_t result = (uint32_t)CY_SMIF_BAD_PARAM;
+ uint32_t sfdpRes =(uint32_t)CY_SMIF_SUCCESS;
+ uint32_t idx;
+
+ if ((NULL != base) && (NULL != blockConfig) && (NULL != blockConfig->memConfig)
+ && (NULL != context) && (0U != blockConfig->memCount))
+ {
+ uint32_t size = blockConfig->memCount;
+ cy_stc_smif_mem_config_t** extMemCfg = blockConfig->memConfig;
+
+ result = (uint32_t)CY_SMIF_SUCCESS;
+ for(idx = 0UL; idx < size; idx++)
+ {
+ memCfg = extMemCfg[idx];
+ if (NULL != memCfg)
+ {
+ /* Check smif memory slot configuration*/
+ CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(memCfg->slaveSelect));
+ CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(memCfg->dataSelect));
+ CY_ASSERT_L1(NULL != memCfg->deviceCfg);
+ CY_ASSERT_L2(CY_SMIF_MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes));
+
+ device = Cy_SMIF_GetDeviceBySlot(base, memCfg->slaveSelect);
+ if (NULL != device)
+ {
+ /* The slave-slot initialization of the device control register.
+ * Cy_SMIF_Memslot_SfdpDetect() must work */
+ device->CTL = _CLR_SET_FLD32U(device->CTL,
+ SMIF_DEVICE_CTL_DATA_SEL,
+ (uint32_t)memCfg->dataSelect);
+ uint32_t sfdpRet = (uint32_t)CY_SMIF_SUCCESS;
+ if (0U != (memCfg->flags & CY_SMIF_FLAG_DETECT_SFDP))
+ {
+ sfdpRet = (uint32_t)Cy_SMIF_Memslot_SfdpDetect(base,
+ memCfg->deviceCfg,
+ memCfg->slaveSelect,
+ memCfg->dataSelect,
+ context);
+ if((uint32_t)CY_SMIF_SUCCESS != sfdpRet)
+ {
+ sfdpRes |= ((uint32_t)CY_SMIF_SFDP_FAIL << idx);
+ }
+ }
+ if (((uint32_t)CY_SMIF_SUCCESS == sfdpRet) &&
+ (0U != (memCfg->flags & CY_SMIF_FLAG_MEMORY_MAPPED)))
+ {
+ /* Check valid parameters for XIP */
+ CY_ASSERT_L3(CY_SMIF_MEM_ADDR_VALID( memCfg->baseAddress, memCfg->memMappedSize));
+ CY_ASSERT_L3(CY_SMIF_MEM_MAPPED_SIZE_VALID( memCfg->memMappedSize));
+
+ Cy_SMIF_Memslot_XipRegInit(device, memCfg);
+
+ /* The device control register initialization */
+ device->CTL = (memCfg->flags & CY_SMIF_FLAG_WR_EN) |
+ (memCfg->flags & CY_SMIF_FLAG_CRYPTO_EN) |
+ _VAL2FLD(SMIF_DEVICE_CTL_DATA_SEL, (uint32_t)memCfg->dataSelect) |
+ SMIF_DEVICE_CTL_ENABLED_Msk;
+ }
+
+ /* Read the register to flush the buffer */
+ (void) device->CTL;
+ }
+ else
+ {
+ result = (uint32_t)CY_SMIF_BAD_PARAM;
+ break;
+ }
+ }
+ }
+ }
+ if((uint32_t)CY_SMIF_SUCCESS != sfdpRes)
+ {
+ result = CY_SMIF_ID | CY_PDL_STATUS_ERROR | sfdpRes;
+ }
+ return (cy_en_smif_status_t) result;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_XipRegInit
+****************************************************************************//**
+*
+* \internal
+* This function initializes the memory device registers used for the XIP mode of
+* the specified device.
+*
+* \param dev
+* The SMIF memory device registers structure. \ref SMIF_DEVICE_Type
+*
+* \param memCfg
+* The memory configuration structure that configures the SMIF memory device to
+* map into the PSoC memory map. \ref cy_stc_smif_mem_config_t
+*
+*******************************************************************************/
+static void Cy_SMIF_Memslot_XipRegInit(SMIF_DEVICE_Type volatile *dev,
+ cy_stc_smif_mem_config_t const * memCfg)
+{
+ cy_stc_smif_mem_device_cfg_t const * devCfg = memCfg->deviceCfg;
+ cy_stc_smif_mem_cmd_t const * read = devCfg->readCmd;
+ cy_stc_smif_mem_cmd_t const * prog = devCfg->programCmd;
+
+ dev->ADDR = (SMIF_DEVICE_ADDR_ADDR_Msk & memCfg->baseAddress);
+ /* Convert the size in the mask*/
+ dev->MASK = (SMIF_DEVICE_MASK_MASK_Msk & (~(memCfg->memMappedSize) + 1UL));
+
+ dev->ADDR_CTL = _VAL2FLD(SMIF_DEVICE_ADDR_CTL_SIZE2, (devCfg->numOfAddrBytes - 1UL)) |
+ ((0UL != memCfg->dualQuadSlots)? SMIF_DEVICE_ADDR_CTL_DIV2_Msk: 0UL);
+
+ dev->RD_CMD_CTL = (CY_SMIF_NO_COMMAND_OR_MODE != read->command)?
+ (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->command) |
+ _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->cmdWidth) |
+ SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk)
+ : 0U;
+
+ dev->RD_ADDR_CTL = _VAL2FLD(SMIF_DEVICE_RD_ADDR_CTL_WIDTH, (uint32_t)read->addrWidth);
+
+ dev->RD_MODE_CTL = (CY_SMIF_NO_COMMAND_OR_MODE != read->mode)?
+ (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->mode) |
+ _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->modeWidth)|
+ SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk)
+ : 0U;
+
+ dev->RD_DUMMY_CTL = (0UL != read->dummyCycles)?
+ (_VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_SIZE5, (read->dummyCycles - 1UL)) |
+ SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk)
+ : 0U;
+
+ dev->RD_DATA_CTL = _VAL2FLD(SMIF_DEVICE_RD_DATA_CTL_WIDTH, (uint32_t)read->dataWidth);
+
+ dev->WR_CMD_CTL = (CY_SMIF_NO_COMMAND_OR_MODE != prog->command)?
+ (_VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->command) |
+ _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->cmdWidth)|
+ SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk)
+ : 0U;
+
+ dev->WR_ADDR_CTL = _VAL2FLD(SMIF_DEVICE_WR_ADDR_CTL_WIDTH, (uint32_t)prog->addrWidth);
+
+ dev->WR_MODE_CTL = (CY_SMIF_NO_COMMAND_OR_MODE != prog->mode)?
+ (_VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->mode) |
+ _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->modeWidth)|
+ SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk)
+ : 0UL;
+
+ dev->WR_DUMMY_CTL = (0UL != prog->dummyCycles)?
+ (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_SIZE5, (prog->dummyCycles - 1UL)) |
+ SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk)
+ : 0U;
+
+ dev->WR_DATA_CTL = _VAL2FLD(SMIF_DEVICE_WR_DATA_CTL_WIDTH, (uint32_t)prog->dataWidth);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_MemoryDeInit
+****************************************************************************//**
+*
+* This function de-initializes all slave slots of the memory device to their default
+* values.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+*******************************************************************************/
+void Cy_SMIF_Memslot_DeInit(SMIF_Type *base)
+{
+ /* Configure the SMIF device slots to the default values. The default value is 0 */
+ uint32_t deviceIndex;
+
+ for(deviceIndex = 0UL; deviceIndex < (uint32_t)SMIF_DEVICE_NR; deviceIndex++)
+ {
+ base->DEVICE[deviceIndex].CTL = 0U;
+ base->DEVICE[deviceIndex].ADDR = 0U;
+ base->DEVICE[deviceIndex].MASK = 0U;
+ base->DEVICE[deviceIndex].ADDR_CTL = 0U;
+ base->DEVICE[deviceIndex].RD_CMD_CTL = 0U;
+ base->DEVICE[deviceIndex].RD_ADDR_CTL = 0U;
+ base->DEVICE[deviceIndex].RD_MODE_CTL = 0U;
+ base->DEVICE[deviceIndex].RD_DUMMY_CTL = 0U;
+ base->DEVICE[deviceIndex].RD_DATA_CTL = 0U;
+ base->DEVICE[deviceIndex].WR_CMD_CTL = 0U;
+ base->DEVICE[deviceIndex].WR_ADDR_CTL = 0U;
+ base->DEVICE[deviceIndex].WR_MODE_CTL = 0U;
+ base->DEVICE[deviceIndex].WR_DUMMY_CTL = 0U;
+ base->DEVICE[deviceIndex].WR_DATA_CTL = 0U;
+
+ /* Read the register to flush the buffer */
+ (void) base->DEVICE[deviceIndex].CTL;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdWriteEnable
+****************************************************************************//**
+*
+* This function sends the Write Enable command to the memory device.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* The Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode,
+* this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data. \ref cy_stc_smif_context_t
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \return A status of the command transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteEnable(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context)
+{
+ /* The memory Write Enable */
+ cy_stc_smif_mem_cmd_t* writeEn = memDevice->deviceCfg->writeEnCmd;
+
+ CY_ASSERT_L1(NULL != writeEn);
+
+ return Cy_SMIF_TransmitCommand( base, (uint8_t) writeEn->command,
+ writeEn->cmdWidth,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_txfr_width_t)CY_SMIF_CMD_WITHOUT_PARAM,
+ memDevice->slaveSelect,
+ CY_SMIF_TX_LAST_BYTE,
+ context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdWriteDisable
+****************************************************************************//**
+*
+* This function sends a Write Disable command to the memory device.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode
+* this API should be called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data. \ref cy_stc_smif_context_t
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \return A status of the command transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteDisable(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context)
+{
+ cy_stc_smif_mem_cmd_t* writeDis = memDevice->deviceCfg->writeDisCmd;
+
+ CY_ASSERT_L1(NULL != writeDis);
+
+ /* The memory write disable */
+ return Cy_SMIF_TransmitCommand( base, (uint8_t)writeDis->command,
+ writeDis->cmdWidth,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_txfr_width_t) CY_SMIF_CMD_WITHOUT_PARAM,
+ memDevice->slaveSelect,
+ CY_SMIF_TX_LAST_BYTE,
+ context);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_IsBusy
+****************************************************************************//**
+*
+* This function checks if the status of the memory device is busy.
+* This is done by reading the status register and the corresponding bit
+* (stsRegBusyMask). This function is a blocking function until the status
+* register from the memory is read.
+*
+* \note In the dual quad mode, this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \return A status of the memory device.
+* - True - The device is busy or a timeout occurs.
+* - False - The device is not busy.
+*
+*******************************************************************************/
+bool Cy_SMIF_Memslot_IsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t *memDevice,
+ cy_stc_smif_context_t const *context)
+{
+ uint8_t status = 1U;
+ cy_en_smif_status_t readStsResult;
+ cy_stc_smif_mem_device_cfg_t* device = memDevice->deviceCfg;
+
+ CY_ASSERT_L1(NULL != device->readStsRegWipCmd);
+
+ readStsResult = Cy_SMIF_Memslot_CmdReadSts(base, memDevice, &status,
+ (uint8_t)device->readStsRegWipCmd->command,
+ context);
+
+ if (CY_SMIF_SUCCESS == readStsResult)
+ {
+ /* Masked not busy bits in returned status */
+ status &= (uint8_t)device->stsRegBusyMask;
+ }
+
+ return (0U != status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_QuadEnable
+****************************************************************************//**
+*
+* This function enables the memory device for the quad mode of operation.
+* This command must be executed before sending Quad SPI commands to the
+* memory device.
+*
+* \note In the dual quad mode, this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \return A status of the command.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_NO_QE_BIT
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_QuadEnable(SMIF_Type *base,
+ cy_stc_smif_mem_config_t *memDevice,
+ cy_stc_smif_context_t const *context)
+{
+ cy_en_smif_status_t result;
+ uint8_t statusReg[CY_SMIF_QE_BIT_STS_REG2_T1] = {0U};
+ cy_stc_smif_mem_device_cfg_t* device = memDevice->deviceCfg;
+
+ /* Check that command exists */
+ CY_ASSERT_L1(NULL != device->readStsRegQeCmd);
+ CY_ASSERT_L1(NULL != device->writeStsRegQeCmd);
+ CY_ASSERT_L1(NULL != device->readStsRegWipCmd);
+
+ uint8_t readQeCmd = (uint8_t)device->readStsRegQeCmd->command;
+ uint8_t writeQeCmd = (uint8_t)device->writeStsRegQeCmd->command;
+ uint8_t readWipCmd = (uint8_t)device->readStsRegWipCmd->command;
+
+ result = Cy_SMIF_Memslot_CmdReadSts(base, memDevice, &statusReg[0U],
+ readQeCmd, context);
+
+ if (CY_SMIF_SUCCESS == result)
+ {
+ uint32_t qeMask = device->stsRegQuadEnableMask;
+
+ switch(qeMask)
+ {
+ case CY_SMIF_SFDP_QE_BIT_6_OF_SR_1:
+ statusReg[0U] |= (uint8_t)qeMask;
+ result = Cy_SMIF_Memslot_CmdWriteSts(base, memDevice,
+ &statusReg[0U], writeQeCmd, context);
+ break;
+ case CY_SMIF_SFDP_QE_BIT_1_OF_SR_2:
+ /* Read status register 1 with the assumption that WIP is always in
+ * status register 1 */
+ result = Cy_SMIF_Memslot_CmdReadSts(base, memDevice,
+ &statusReg[0U], readWipCmd, context);
+ if (CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_Memslot_CmdReadSts(base, memDevice,
+ &statusReg[1U], readQeCmd, context);
+ if (CY_SMIF_SUCCESS == result)
+ {
+ statusReg[1U] |= (uint8_t)qeMask;
+ result = Cy_SMIF_Memslot_CmdWriteSts(base, memDevice,
+ statusReg, writeQeCmd, context);
+ }
+ }
+ break;
+ case CY_SMIF_SFDP_QE_BIT_7_OF_SR_2:
+ result = Cy_SMIF_Memslot_CmdReadSts(base, memDevice,
+ &statusReg[1U], readQeCmd, context);
+ if (CY_SMIF_SUCCESS == result)
+ {
+ statusReg[1U] |= (uint8_t)qeMask;
+ result = Cy_SMIF_Memslot_CmdWriteSts(base, memDevice,
+ &statusReg[1U], writeQeCmd, context);
+ }
+ break;
+ default:
+ result = CY_SMIF_NO_QE_BIT;
+ break;
+ }
+
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdReadSts
+****************************************************************************//**
+*
+* This function reads the status register. This function is a blocking function,
+* it will block the execution flow until the status register is read.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* the Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode,
+* this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \param status
+* The status register value returned by the external memory.
+*
+* \param command
+* The command required to read the status/configuration register.
+*
+* \return A status of the command reception.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdReadSts(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t *status,
+ uint8_t command,
+ cy_stc_smif_context_t const *context)
+{
+ cy_en_smif_status_t result;
+
+ /* Read the memory status register */
+ result = Cy_SMIF_TransmitCommand( base, command, CY_SMIF_WIDTH_SINGLE,
+ CY_SMIF_CMD_WITHOUT_PARAM, CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_txfr_width_t) CY_SMIF_CMD_WITHOUT_PARAM,
+ memDevice->slaveSelect, CY_SMIF_TX_NOT_LAST_BYTE, context);
+
+ if (CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_ReceiveDataBlocking( base, status,
+ CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, context);
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdWriteSts
+****************************************************************************//**
+*
+* This function writes the status register. This is a blocking function, it will
+* block the execution flow until the command transmission is completed.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* The Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode,
+* this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data. \ref cy_stc_smif_context_t
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \param status
+* The status to write into the status register.
+*
+* \param command
+* The command to write into the status/configuration register.
+*
+* \return A status of the command transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteSts(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ void const *status,
+ uint8_t command,
+ cy_stc_smif_context_t const *context)
+{
+ cy_en_smif_status_t result;
+
+ /* The Write Enable */
+ result = Cy_SMIF_Memslot_CmdWriteEnable(base, memDevice, context);
+
+ /* The Write Status */
+ if (CY_SMIF_SUCCESS == result)
+ {
+ uint32_t size;
+ uint32_t qeMask = memDevice->deviceCfg->stsRegQuadEnableMask;
+
+ size = ( CY_SMIF_SFDP_QE_BIT_1_OF_SR_2 == qeMask)? CY_SMIF_WRITE_TWO_BYTES:
+ CY_SMIF_WRITE_ONE_BYTE;
+ result = Cy_SMIF_TransmitCommand( base, command, CY_SMIF_WIDTH_SINGLE,
+ (uint8_t const *)status, size, CY_SMIF_WIDTH_SINGLE,
+ memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context);
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdChipErase
+****************************************************************************//**
+*
+* This function performs a chip erase of the external memory. The Write Enable
+* command is called before this API.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode,
+* this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data. \ref cy_stc_smif_context_t
+*
+* \param memDevice
+* The device to which the command is sent
+*
+* \return A status of the command transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdChipErase(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context)
+{
+ cy_en_smif_status_t result;
+
+ cy_stc_smif_mem_cmd_t *cmdErase = memDevice->deviceCfg->chipEraseCmd;
+ CY_ASSERT_L1(NULL != cmdErase);
+
+ result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command,
+ cmdErase->cmdWidth, CY_SMIF_CMD_WITHOUT_PARAM,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_txfr_width_t) CY_SMIF_CMD_WITHOUT_PARAM,
+ memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context);
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdSectorErase
+****************************************************************************//**
+*
+* This function performs a block Erase of the external memory. The Write Enable
+* command is called before this API.
+*
+* \note This function uses the low-level Cy_SMIF_TransmitCommand() API.
+* The Cy_SMIF_TransmitCommand() API works in a blocking mode. In the dual quad mode,
+* this API is called for each memory.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data. \ref cy_stc_smif_context_t
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \param sectorAddr
+* The sector address to erase.
+*
+* \return A status of the command transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_BAD_PARAM
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base,
+ cy_stc_smif_mem_config_t *memDevice,
+ uint8_t const *sectorAddr,
+ cy_stc_smif_context_t const *context)
+{
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+
+ if (NULL != sectorAddr)
+ {
+
+ cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg;
+ cy_stc_smif_mem_cmd_t *cmdErase = device->eraseCmd;
+
+ CY_ASSERT_L1(NULL != cmdErase);
+
+ result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command,
+ cmdErase->cmdWidth, sectorAddr, device->numOfAddrBytes,
+ cmdErase->cmdWidth, memDevice->slaveSelect,
+ CY_SMIF_TX_LAST_BYTE, context);
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdProgram
+****************************************************************************//**
+*
+* This function performs the Program operation.
+*
+* \note This function uses the Cy_SMIF_TransmitCommand() API.
+* The Cy_SMIF_TransmitCommand() API works in the blocking mode. In the dual quad mode,
+* this API works with both types of memory simultaneously.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \param addr
+* The address to program.
+*
+* \param writeBuff
+* The pointer to the data to program. If this pointer is a NULL, then the
+* function does not enable the interrupt. This use case is typically used when
+* the FIFO is handled outside the interrupt and is managed in either a
+* polling-based code or a DMA. The user would handle the FIFO management
+* in a DMA or a polling-based code.
+* If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation
+* \ref Cy_SMIF_TransmitData().
+*
+*
+* \param size
+* The size of data to program. The user must ensure that the data size
+* does not exceed the page size.
+*
+* \param cmdCmpltCb
+* The callback function to call after the transfer completion. NULL interpreted
+* as no callback.
+*
+* \return A status of a transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t const *addr,
+ uint8_t* writeBuff,
+ uint32_t size,
+ cy_smif_event_cb_t cmdCmpltCb,
+ cy_stc_smif_context_t *context)
+{
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+ cy_en_smif_slave_select_t slaveSelected;
+
+ cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg;
+ cy_stc_smif_mem_cmd_t *cmdProg = device->programCmd;
+
+ CY_ASSERT_L1(NULL != cmdProg);
+
+ if ((NULL != addr) && (size <= device->programSize))
+ {
+ slaveSelected = (0U == memDevice->dualQuadSlots)? memDevice->slaveSelect :
+ (cy_en_smif_slave_select_t)memDevice->dualQuadSlots;
+ /* The page program command */
+ result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdProg->command,
+ cmdProg->cmdWidth, addr, device->numOfAddrBytes,
+ cmdProg->addrWidth, slaveSelected, CY_SMIF_TX_NOT_LAST_BYTE,
+ context);
+
+ if((CY_SMIF_SUCCESS == result) && (cmdProg->dummyCycles > 0U))
+ {
+ result = Cy_SMIF_SendDummyCycles(base, cmdProg->dummyCycles);
+ }
+
+ if(CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_TransmitData( base, writeBuff, size,
+ cmdProg->dataWidth, cmdCmpltCb, context);
+ }
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_CmdRead
+****************************************************************************//**
+*
+* This function performs the Read operation.
+*
+* \note This function uses the Cy_SMIF_TransmitCommand() API.
+* The Cy_SMIF_TransmitCommand() API works in the blocking mode. In the dual quad mode,
+* this API works with both types of memory simultaneously.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param memDevice
+* The device to which the command is sent.
+*
+* \param addr
+* The address to read.
+*
+* \param readBuff
+* The pointer to the variable where the read data is stored. If this pointer is
+* a NULL, then the function does not enable the interrupt. This use case is
+* typically used when the FIFO is handled outside the interrupt and is managed
+* in either a polling-based code or a DMA. The user would handle the FIFO
+* management in a DMA or a polling-based code.
+* If the user provides a NULL pointer in this function and does not handle
+* the FIFO transaction, this could either stall or timeout the operation
+* \ref Cy_SMIF_TransmitData().
+*
+* \param size
+* The size of data to read.
+*
+* \param cmdCmpltCb
+* The callback function to call after the transfer completion. NULL interpreted
+* as no callback.
+*
+* \return A status of the transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_BAD_PARAM
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdRead(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t const *addr,
+ uint8_t* readBuff,
+ uint32_t size,
+ cy_smif_event_cb_t cmdCmpltCb,
+ cy_stc_smif_context_t *context)
+{
+ cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
+ cy_en_smif_slave_select_t slaveSelected;
+ cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg;
+ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd;
+
+ if (NULL != addr)
+ {
+ slaveSelected = (0U == memDevice->dualQuadSlots)? memDevice->slaveSelect :
+ (cy_en_smif_slave_select_t)memDevice->dualQuadSlots;
+
+ result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdRead->command,
+ cmdRead->cmdWidth, addr, device->numOfAddrBytes,
+ cmdRead->addrWidth, slaveSelected, CY_SMIF_TX_NOT_LAST_BYTE,
+ context);
+
+ if((CY_SMIF_SUCCESS == result) && (0U < cmdRead->dummyCycles))
+ {
+ result = Cy_SMIF_SendDummyCycles(base, cmdRead->dummyCycles);
+ }
+
+ if((CY_SMIF_SUCCESS == result) && (CY_SMIF_NO_COMMAND_OR_MODE != cmdRead->mode))
+ {
+ result = Cy_SMIF_TransmitCommand(base, (uint8_t)cmdRead->mode,
+ cmdRead->dataWidth, CY_SMIF_CMD_WITHOUT_PARAM,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_txfr_width_t) CY_SMIF_CMD_WITHOUT_PARAM,
+ (cy_en_smif_slave_select_t)slaveSelected,
+ CY_SMIF_TX_NOT_LAST_BYTE, context);
+ }
+
+ if(CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_ReceiveData(base, readBuff, size,
+ cmdRead->dataWidth, cmdCmpltCb, context);
+ }
+ }
+
+ return(result);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SMIF_Memslot_SfdpDetect
+****************************************************************************//**
+*
+* This function detects the device signature for SFDP devices.
+* Refer to the SFDP spec (JESD216B) for details.
+* The function asks the device using an SPI and then populates the relevant
+* parameters for \ref cy_stc_smif_mem_device_cfg_t.
+*
+* \note This function is a blocking function and blocks until the structure data
+* is read and returned. This function uses \ref Cy_SMIF_TransmitCommand()
+* If there is no support for SFDP in the memory device, the API returns an
+* error condition. The function requires:
+* - SMIF initialized and enabled to work in the normal mode;
+* - readSfdpCmd field of \ref cy_stc_smif_mem_device_cfg_t is enabled.
+*
+* \note The SFDP detect takes into account the types of the SPI supported by the
+* memory device and also the dataSelect option selected to choose which SPI mode
+* (SPI, DSPI, QSPI) to load into the structures. The algorithm prefers
+* QSPI>DSPI>SPI, provided there is support for it in the memory device and the
+* dataSelect selected by the user.
+*
+* \param base
+* Holds the base address of the SMIF block registers.
+*
+* \param context
+* The internal SMIF context data.
+*
+* \param device
+* The device structure instance declared by the user. This is where the detected
+* parameters are stored and returned.
+*
+* \param slaveSelect
+* The slave select line for the device.
+*
+* \param dataSelect
+* The data line selection options for a slave device.
+*
+* \return A status of the transmission.
+* - \ref CY_SMIF_SUCCESS
+* - \ref CY_SMIF_CMD_FIFO_FULL
+* - \ref CY_SMIF_NO_SFDP_SUPPORT
+* - \ref CY_SMIF_EXCEED_TIMEOUT
+*
+*******************************************************************************/
+cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
+ cy_stc_smif_mem_device_cfg_t *device,
+ cy_en_smif_slave_select_t slaveSelect,
+ cy_en_smif_data_select_t dataSelect,
+ cy_stc_smif_context_t *context)
+{
+ /* Check input parameters */
+ CY_ASSERT_L1(NULL != device);
+ CY_ASSERT_L1(NULL != device->readSfdpCmd);
+
+ uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH];
+ uint8_t sfdpAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U};
+ cy_en_smif_status_t result;
+ cy_stc_smif_mem_cmd_t *cmdSfdp = device->readSfdpCmd;
+
+ /* Slave slot initialization */
+ Cy_SMIF_SetDataSelect(base, slaveSelect, dataSelect);
+
+ result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdSfdp->command,
+ cmdSfdp->cmdWidth, sfdpAddress, CY_SMIF_SFDP_ADDRESS_LENGTH,
+ cmdSfdp->addrWidth, slaveSelect, CY_SMIF_TX_NOT_LAST_BYTE,
+ context);
+ if(CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_SendDummyCycles(base, cmdSfdp->dummyCycles);
+ }
+
+ if(CY_SMIF_SUCCESS == result)
+ {
+ result = Cy_SMIF_ReceiveData( base, sfdpBuffer, CY_SMIF_SFDP_LENGTH,
+ cmdSfdp->dataWidth, NULL, context);
+ }
+
+ if (CY_SMIF_SUCCESS == result)
+ {
+ uint32_t cmdTimeout = context->timeout;
+ while (((uint32_t) CY_SMIF_REC_CMPLT != context->transferStatus) &&
+ (CY_SMIF_EXCEED_TIMEOUT != result))
+ {
+ /* Wait until the Read of the SFDP operation is completed. */
+ result = Cy_SMIF_TimeoutRun(&cmdTimeout);
+ }
+ }
+
+ if (CY_SMIF_SUCCESS == result)
+ {
+ if((sfdpBuffer[CY_SMIF_SFDP_SING_BYTE_00] == (uint8_t)'S') &&
+ (sfdpBuffer[CY_SMIF_SFDP_SING_BYTE_01] == (uint8_t)'F') &&
+ (sfdpBuffer[CY_SMIF_SFDP_SING_BYTE_02] == (uint8_t)'D') &&
+ (sfdpBuffer[CY_SMIF_SFDP_SING_BYTE_03] == (uint8_t)'P') &&
+ (sfdpBuffer[CY_SMIF_SFDP_MINOR_REV] >= CY_SMIF_SFDP_JEDEC_REV_B) &&
+ (sfdpBuffer[CY_SMIF_SFDP_MAJOR_REV] == CY_SMIF_SFDP_MAJOR_REV_1))
+ {
+ /* The address of the JEDEC basic flash parameter table */
+ uint8_t offset = sfdpBuffer[CY_SMIF_SFDP_PARAM_TABLE_PTR];
+ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd;
+
+ /* The number of address bytes used by the memory slave device */
+ uint32_t sfdpDataIndex = CY_SMIF_SFDP_BFPT_BYTE_02 + (uint32_t)offset;
+ uint32_t sfdpAddrCode = _FLD2VAL(CY_SMIF_SFDP_ADDRESS_BYTES,
+ (uint32_t)sfdpBuffer
+ [sfdpDataIndex]);
+ switch(sfdpAddrCode)
+ {
+ case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE:
+ device->numOfAddrBytes = CY_SMIF_THREE_BYTES_ADDR;
+ break;
+ case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE:
+ device->numOfAddrBytes = CY_SMIF_THREE_BYTES_ADDR;
+ break;
+ case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE:
+ device->numOfAddrBytes = CY_SMIF_FOUR_BYTES_ADDR;
+ break;
+ default:
+ break;
+ }
+
+ /* Erase Time Type 1*/
+ uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[(offset/CY_SMIF_BYTES_IN_WORD) +
+ CY_SMIF_JEDEC_BFPT_10TH_DWORD];
+ uint32_t eraseUnits = _FLD2VAL(CY_SMIF_SFDP_ERASE_T1_UNITS, readEraseTime);
+ uint32_t eraseCount = _FLD2VAL(CY_SMIF_SFDP_ERASE_T1_COUNT, readEraseTime);
+ uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime);
+ uint32_t eraseMs = 0U;
+
+ switch (eraseUnits)
+ {
+ case CY_SMIF_SFDP_UNIT_0:
+ eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS;
+ break;
+ case CY_SMIF_SFDP_UNIT_1:
+ eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS;
+ break;
+ case CY_SMIF_SFDP_UNIT_2:
+ eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS;
+ break;
+ case CY_SMIF_SFDP_UNIT_3:
+ eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S;
+ break;
+ default:
+ /* An unsupported SFDP value */
+ break;
+ }
+ /* Convert typical time to max time */
+ device->eraseTime = ((eraseCount + 1U) * eraseMs) * (2U * (eraseMul + 1U));
+
+
+ /* Chip Erase Time*/
+ uint32_t chipEraseProgTime = ((uint32_t*)sfdpBuffer)[(offset/CY_SMIF_BYTES_IN_WORD) +
+ CY_SMIF_JEDEC_BFPT_11TH_DWORD];
+ uint32_t chipEraseUnits = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_UNITS, chipEraseProgTime);
+ uint32_t chipEraseCount = _FLD2VAL(CY_SMIF_SFDP_CHIP_ERASE_COUNT, chipEraseProgTime);
+ uint32_t chipEraseMs = 0U;
+
+ switch (chipEraseUnits)
+ {
+ case CY_SMIF_SFDP_UNIT_0:
+ chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS;
+ break;
+ case CY_SMIF_SFDP_UNIT_1:
+ chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS;
+ break;
+ case CY_SMIF_SFDP_UNIT_2:
+ chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_4S;
+ break;
+ case CY_SMIF_SFDP_UNIT_3:
+ chipEraseMs = CY_SMIF_SFDP_CHIP_ERASE_TIME_64S;
+ break;
+ default:
+ /* An unsupported SFDP value*/
+ break;
+ }
+ /* Convert typical time to max time */
+ device->chipEraseTime = ((chipEraseCount + 1U)*chipEraseMs) * (2U *(eraseMul + 1U));
+
+ /* Page Program Time*/
+ uint32_t programTimeUnits = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_UNITS, chipEraseProgTime);
+ uint32_t programTimeCount = _FLD2VAL(CY_SMIF_SFDP_PAGE_PROG_COUNT, chipEraseProgTime);
+ uint32_t progMul = _FLD2VAL(CY_SMIF_SFDP_PROG_MUL_COUNT, chipEraseProgTime);
+ uint32_t progUs;
+
+ if (CY_SMIF_SFDP_UNIT_0 == programTimeUnits)
+ {
+ progUs = CY_SMIF_SFDP_PROG_TIME_8US;
+ }
+ else
+ {
+ progUs = CY_SMIF_SFDP_PROG_TIME_64US;
+ }
+ /* Convert typical time to max time */
+ device->programTime = ((programTimeCount + 1U) * progUs) * (2U * (progMul + 1U));
+
+
+ /* The size of the external memory */
+ uint32_t locSize = Cy_SMIF_PackBytesArray(&sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_04 +
+ offset], true);
+
+ if (0UL == (locSize & CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk))
+ {
+ device->memSize = (locSize + 1UL)/CY_SMIF_BITS_IN_BYTE;
+ }
+ else
+ {
+ device->memSize = (locSize - CY_SMIF_BITS_IN_BYTE_ABOVE_4GB) |
+ CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk;
+ }
+
+ /* The page size */
+ device->programSize = 0x01UL << _FLD2VAL(CY_SMIF_SFDP_PAGE_SIZE,
+ (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_28 + offset]);
+
+ /* The size of the Erase sector */
+ device->eraseSize = (0x01UL << (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + offset]);
+
+ /* This specifies the Read command. The preference order Quad>Dual>SPI */
+ if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_4_4,
+ ((uint32_t) sfdpBuffer[sfdpDataIndex])) == 1UL) &&
+ (CY_SMIF_DATA_SEL1 != dataSelect) &&
+ (CY_SMIF_DATA_SEL3 != dataSelect))
+ {
+ /* The 8-bit command. 4 x I/O Read command */
+ cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_09 + offset];
+
+ /* The width of the command transfer */
+ cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The width of the address transfer */
+ cmdRead->addrWidth = CY_SMIF_WIDTH_QUAD;
+
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ if ((_FLD2VAL(CY_SMIF_SFDP_1_4_4_MODE_CYCLES,
+ (uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_08 + offset])) == 0U)
+ {
+ cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+ }
+ else
+ {
+ cmdRead->mode = CY_SMIF_READ_MODE_BYTE;
+ }
+
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES, (uint32_t) sfdpBuffer
+ [CY_SMIF_SFDP_BFPT_BYTE_08 + offset]);
+
+ /* The width of the data transfer*/
+ cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD;
+ }
+ else
+ {
+ if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_4,
+ ((uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL) &&
+ (CY_SMIF_DATA_SEL1 != dataSelect) &&
+ (CY_SMIF_DATA_SEL3 != dataSelect))
+ {
+ /* The 8-bit command. 4 x I/O Read command */
+ cmdRead->command =
+ sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0B + offset];
+
+ /* The width of the command transfer */
+ cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The width of the address transfer */
+ cmdRead->addrWidth = CY_SMIF_WIDTH_QUAD;
+
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ if ((_FLD2VAL(CY_SMIF_SFDP_1_1_4_MODE_CYCLES, (uint32_t) sfdpBuffer
+ [CY_SMIF_SFDP_BFPT_BYTE_0A + offset])) == 0U)
+ {
+ cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+ }
+ else
+ {
+ cmdRead->mode = CY_SMIF_READ_MODE_BYTE;
+ }
+
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES,
+ (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0A + offset]);
+
+ /* The width of the data transfer*/
+ cmdRead->dataWidth = CY_SMIF_WIDTH_QUAD;
+ }
+ else
+ {
+ if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_2_2,
+ (uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL)
+ {
+ /* The 8-bit command. 2 x I/O Read command */
+ cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0F + offset];
+
+ /* The width of the command transfer */
+ cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The width of the address transfer */
+ cmdRead->addrWidth = CY_SMIF_WIDTH_DUAL;
+
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ if ((_FLD2VAL(CY_SMIF_SFDP_1_2_2_MODE_CYCLES, (uint32_t)
+ sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0E + offset])) == 0U)
+ {
+ cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+ }
+ else
+ {
+ cmdRead->mode = CY_SMIF_READ_MODE_BYTE;
+ }
+
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES,
+ (uint32_t) sfdpBuffer [CY_SMIF_SFDP_BFPT_BYTE_0E + offset]);
+
+ /* The width of the data transfer*/
+ cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL;
+ }
+ else
+ {
+ if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_1_2,
+ (uint32_t)sfdpBuffer[sfdpDataIndex])) == 1UL)
+ {
+ /* The 8-bit command. 2 x I/O Read command */
+ cmdRead->command = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0D + offset];
+
+ /* The width of the command transfer */
+ cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The width of the address transfer */
+ cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ if ((_FLD2VAL(CY_SMIF_SFDP_1_1_2_MODE_CYCLES, (uint32_t)
+ sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C + offset])) == 0U)
+ {
+ cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+ }
+ else
+ {
+ cmdRead->mode = CY_SMIF_READ_MODE_BYTE;
+ }
+
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cmdRead->dummyCycles = _FLD2VAL(CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES,
+ (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_0C + offset]);
+
+ /* The width of the data transfer*/
+ cmdRead->dataWidth = CY_SMIF_WIDTH_DUAL;
+ }
+ else
+ {
+ /* The 8-bit command. 1 x I/O Read command */
+ cmdRead->command = CY_SMIF_SINGLE_READ_CMD;
+
+ /* The width of the command transfer */
+ cmdRead->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The width of the address transfer */
+ cmdRead->addrWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The 8 bit-mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ cmdRead->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cmdRead->dummyCycles = 0U;
+
+ /* The width of the data transfer*/
+ cmdRead->dataWidth = CY_SMIF_WIDTH_SINGLE;
+ }
+ }
+ }
+ }
+
+ /* The Write Enable command */
+ /* The 8-bit command. Write Enable */
+ device->writeEnCmd->command = CY_SMIF_WR_ENABLE_CMD;
+ /* The width of the command transfer */
+ device->writeEnCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The Write Disable command */
+ /* The 8-bit command. Write Disable */
+ device->writeDisCmd->command = CY_SMIF_WR_DISABLE_CMD;
+ /* The width of the command transfer */
+ device->writeDisCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The chip Erase command */
+ /* The 8-bit command. Chip Erase */
+ device->chipEraseCmd->command = CY_SMIF_CHIP_ERASE_CMD;
+ /* The width of the command transfer */
+ device->chipEraseCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The sector Erase command */
+ /* The 8-bit command. The sector Erase */
+ device->eraseCmd->command =
+ sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1D + offset];
+ /* The width of the command transfer */
+ device->eraseCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+ /* The width of the address transfer */
+ device->eraseCmd->addrWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* This specifies the program command */
+ /* The 8-bit command. 1 x I/O Program command */
+ device->programCmd->command = CY_SMIF_SINGLE_PROGRAM_CMD;
+ /* The width of the command transfer */
+ device->programCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+ /* The width of the address transfer */
+ device->programCmd->addrWidth = CY_SMIF_WIDTH_SINGLE;
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ device->programCmd->mode = CY_SMIF_NO_COMMAND_OR_MODE;
+ /* The number of the dummy cycles. A zero value suggests no dummy cycles */
+ device->programCmd->dummyCycles = 0U;
+ /* The width of the data transfer*/
+ device->programCmd->dataWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The busy mask for the status registers */
+ device->stsRegBusyMask = CY_SMIF_STS_REG_BUSY_MASK;
+
+ /* The command to read the WIP-containing status register */
+ /* The 8-bit command. WIP RDSR */
+ device->readStsRegWipCmd->command = CY_SMIF_RD_STS_REG1_CMD;
+ /* The width of the command transfer */
+ device->readStsRegWipCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The command to write into the QE-containing status register */
+ /* The width of the command transfer */
+ device->writeStsRegQeCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
+
+ /* The QE mask for the status registers */
+ switch (_FLD2VAL(CY_SMIF_SFDP_QE_REQUIREMENTS, (uint32_t)sfdpBuffer
+ [CY_SMIF_SFDP_BFPT_BYTE_3A + offset]))
+ {
+ case CY_SMIF_SFDP_QER_0:
+ device->stsRegQuadEnableMask = CY_SMIF_NO_COMMAND_OR_MODE;
+ device->writeStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE;
+ device->readStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE;
+ break;
+ case CY_SMIF_SFDP_QER_1:
+ case CY_SMIF_SFDP_QER_4:
+ case CY_SMIF_SFDP_QER_5:
+ device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2;
+
+ /* The command to write into the QE-containing status register */
+ /* The 8-bit command. QE WRSR */
+ device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD;
+ device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T1_CMD;
+ break;
+ case CY_SMIF_SFDP_QER_2:
+ device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_6_OF_SR_1;
+
+ /* The command to write into the QE-containing status register */
+ /* The 8-bit command. QE WRSR */
+ device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG1_CMD;
+ device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG1_CMD;
+ break;
+ case CY_SMIF_SFDP_QER_3:
+ device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_7_OF_SR_2;
+
+ /* The command to write into the QE-containing status register */
+ /* The 8-bit command. QE WRSR */
+ device->writeStsRegQeCmd->command = CY_SMIF_WR_STS_REG2_CMD;
+ device->readStsRegQeCmd->command = CY_SMIF_RD_STS_REG2_T2_CMD;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ result = CY_SMIF_NO_SFDP_SUPPORT;
+ }
+ }
+
+ return(result);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif_memslot.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,423 @@
+/***************************************************************************//**
+* \file cy_smif_memslot.h
+* \version 1.10.1
+*
+* \brief
+* This file provides the constants and parameter values for the memory-level
+* APIs of the SMIF driver.
+*
+* Note:
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_SMIF_MEMORYSLOT_H)
+#define CY_SMIF_MEMORYSLOT_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+#include "cy_smif.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/**
+* \addtogroup group_smif_macros_status
+* \{
+*/
+
+/***************************************
+* Constants
+****************************************/
+#define CY_SMIF_DEVICE_BUSY (1U) /**< The external memory is busy */
+#define CY_SMIF_DEVICE_READY (0U) /**< The external memory is ready */
+
+/** \} group_smif_macros_status */
+
+/**
+* \addtogroup group_smif_macros_cmd
+* \{
+*/
+#define CY_SMIF_CMD_WITHOUT_PARAM (0U) /**< No parameter */
+#define CY_SMIF_TX_LAST_BYTE (1U) /**< The last byte in the command transmission
+ * (SS is set high after the transmission)
+ */
+#define CY_SMIF_TX_NOT_LAST_BYTE (0U) /**< Not the last byte in the command transmission
+ * (SS remains low after the transmission)
+ */
+#define CY_SMIF_READ_ONE_BYTE (1U) /**< Read 1 byte */
+#define CY_SMIF_WRITE_ONE_BYTE (1U) /**< Write 1 byte */
+#define CY_SMIF_WRITE_TWO_BYTES (2U) /**< Write 2 bytes */
+#define CY_SMIF_ONE_WORD (4U) /**< 4 bytes */
+
+#define CY_SMIF_DUAL_QUAD_DISABLED (0U) /**< The dual quad transmission mode is disabled */
+#define CY_SMIF_DUAL_QUAD_ENABLED (1U) /**< The dual quad transmission mode is enabled */
+
+
+/** \} group_smif_macros_status */
+
+/**
+* \addtogroup group_smif_macros_flags
+* \{
+*/
+
+#define CY_SMIF_FLAG_ALL_DISABLED (0U) /**< All memory configuration flags are disabled */
+/** Enables the write capability for the memory slave in the memory-mapped
+ * mode. Valid when the memory-mapped mode is enabled */
+#define CY_SMIF_FLAG_WR_EN (SMIF_DEVICE_CTL_WR_EN_Msk)
+/** Determines if the device is memory-mapped. If enabled, this memory slot will
+ * be initialized in System init */
+#define CY_SMIF_FLAG_MEMORY_MAPPED (2U)
+#define CY_SMIF_FLAG_DETECT_SFDP (4U) /**< Enables the Autodetect using the SFDP */
+/** Enables the crypto support for this memory slave. All access to the
+* memory device goes through the encryption/decryption
+* Valid when the memory-mapped mode is enabled */
+#define CY_SMIF_FLAG_CRYPTO_EN (SMIF_DEVICE_CTL_CRYPTO_EN_Msk)
+
+/** \} group_smif_macros_flags */
+
+/**
+* \addtogroup group_smif_macros_sfdp
+* \{
+*/
+
+/***************************************
+* SFDP constants
+****************************************/
+#define CY_SMIF_SFDP_ADDRESS_LENGTH (0x03U) /**< The length of the SFDP address */
+#define CY_SMIF_SFDP_LENGTH (0xFFU) /**< The length of the SFDP */
+#define CY_SMIF_SFDP_SING_BYTE_00 (0x00U) /**< The SFDP Signature byte 0x00. Should be "S" */
+#define CY_SMIF_SFDP_SING_BYTE_01 (0x01U) /**< The SFDP Signature byte 0x01. Should be "F" */
+#define CY_SMIF_SFDP_SING_BYTE_02 (0x02U) /**< The SFDP Signature byte 0x02. Should be "D" */
+#define CY_SMIF_SFDP_SING_BYTE_03 (0x03U) /**< The SFDP Signature byte 0x03. Should be "P" */
+#define CY_SMIF_SFDP_MINOR_REV (0x04U) /**< The SFDP Header byte 0x04. Defines the JEDEC JESD216 Revision */
+#define CY_SMIF_SFDP_MAJOR_REV (0x05U) /**< The SFDP Header byte 0x05. Defines the SFDP Major Revision */
+#define CY_SMIF_SFDP_MAJOR_REV_1 (0x01U) /**< The SFDP Major Revision is 1 */
+#define CY_SMIF_SFDP_JEDEC_REV_B (0x06U) /**< The JEDEC JESD216 Revision is B */
+#define CY_SMIF_SFDP_PARAM_TABLE_PTR (0x0CU) /**< Specifies the start of the JEDEC Basic Flash
+ * Parameter Table in the SFDP structure
+ */
+#define CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE (0x00U) /**< Code for the SFDP Address Bytes Number 3 */
+#define CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE (0x01U) /**< Code for the SFDP Address Bytes Number 3 or 4 */
+#define CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE (0x02U) /**< Code for the SFDP Address Bytes Number 4 */
+#define CY_SMIF_THREE_BYTES_ADDR (0x03U) /**< The address Bytes Number is 3 */
+#define CY_SMIF_FOUR_BYTES_ADDR (0x04U) /**< The address Bytes Number is 4 */
+#define CY_SMIF_READ_MODE_BYTE (0x5AU) /**< The mode byte for the SMIF read */
+#define CY_SMIF_WR_STS_REG1_CMD (0x01U) /**< The write status register 1 command */
+#define CY_SMIF_SINGLE_PROGRAM_CMD (0x02U) /**< The command for a single SMIF program */
+#define CY_SMIF_SINGLE_READ_CMD (0x03U) /**< The command for a single SMIF read */
+#define CY_SMIF_WR_DISABLE_CMD (0x04U) /**< The Write Disable command */
+#define CY_SMIF_RD_STS_REG1_CMD (0x05U) /**< The read status register 1 command */
+#define CY_SMIF_WR_ENABLE_CMD (0x06U) /**< The Write Enable command */
+#define CY_SMIF_RD_STS_REG2_T1_CMD (0x35U) /**< The read status register 2 type 1 command */
+#define CY_SMIF_WR_STS_REG2_CMD (0x3EU) /**< The write status register 2 command */
+#define CY_SMIF_RD_STS_REG2_T2_CMD (0x3FU) /**< The read status register 2 type 2 command */
+#define CY_SMIF_CHIP_ERASE_CMD (0x60U) /**< The Chip Erase command */
+#define CY_SMIF_QE_BIT_STS_REG2_T1 (0x02U) /**< The QE bit is in status register 2 type 1.
+ * It should be written as the second byte.
+ */
+#define CY_SMIF_SFDP_ERASE_TIME_1MS (1U) /**< Units of Erase Typical Time in ms */
+#define CY_SMIF_SFDP_ERASE_TIME_16MS (16U) /**< Units of Erase Typical Time in ms */
+#define CY_SMIF_SFDP_ERASE_TIME_128MS (128U) /**< Units of Erase Typical Time in ms */
+#define CY_SMIF_SFDP_ERASE_TIME_1S (1000U) /**< Units of Erase Typical Time in ms */
+
+#define CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS (16U) /**< Units of Chip Erase Typical Time in ms */
+#define CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS (256U) /**< Units of Chip Erase Typical Time in ms */
+#define CY_SMIF_SFDP_CHIP_ERASE_TIME_4S (4000U) /**< Units of Chip Erase Typical Time in ms */
+#define CY_SMIF_SFDP_CHIP_ERASE_TIME_64S (64000U) /**< Units of Chip Erase Typical Time in ms */
+
+#define CY_SMIF_SFDP_PROG_TIME_8US (8U) /**< Units of Page Program Typical Time in us */
+#define CY_SMIF_SFDP_PROG_TIME_64US (64U) /**< Units of Page Program Typical Time in us */
+
+#define CY_SMIF_SFDP_UNIT_0 (0U) /**< Units of Basic Flash Parameter Table Time Parameters */
+#define CY_SMIF_SFDP_UNIT_1 (1U) /**< Units of Basic Flash Parameter Table Time Parameters */
+#define CY_SMIF_SFDP_UNIT_2 (2U) /**< Units of Basic Flash Parameter Table Time Parameters */
+#define CY_SMIF_SFDP_UNIT_3 (3U) /**< Units of Basic Flash Parameter Table Time Parameters */
+
+
+#define CY_SMIF_STS_REG_BUSY_MASK (0x01U) /**< The busy mask for the status registers */
+#define CY_SMIF_NO_COMMAND_OR_MODE (0xFFFFFFFFUL) /**< No command or mode present */
+#define CY_SMIF_SFDP_QER_0 (0x00UL) /**< The quad Enable Requirements case 0 */
+#define CY_SMIF_SFDP_QER_1 (0x01UL) /**< The quad Enable Requirements case 1 */
+#define CY_SMIF_SFDP_QER_2 (0x02UL) /**< The quad Enable Requirements case 2 */
+#define CY_SMIF_SFDP_QER_3 (0x03UL) /**< The quad Enable Requirements case 3 */
+#define CY_SMIF_SFDP_QER_4 (0x04UL) /**< The quad Enable Requirements case 4 */
+#define CY_SMIF_SFDP_QER_5 (0x05UL) /**< The quad Enable Requirements case 5 */
+#define CY_SMIF_SFDP_QE_BIT_1_OF_SR_2 (0x02UL) /**< The QE is bit 1 of the status register 2 */
+#define CY_SMIF_SFDP_QE_BIT_6_OF_SR_1 (0x40UL) /**< The QE is bit 6 of the status register 1 */
+#define CY_SMIF_SFDP_QE_BIT_7_OF_SR_2 (0x80UL) /**< The QE is bit 7 of the status register 2 */
+#define CY_SMIF_SFDP_BFPT_BYTE_02 (0x02U) /**< The byte 0x02 of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_04 (0x04U) /**< The byte 0x04 of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_08 (0x08U) /**< The byte 0x08 of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_09 (0x09U) /**< The byte 0x09 of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0A (0x0AU) /**< The byte 0x0A of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0B (0x0BU) /**< The byte 0x0B of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0C (0x0CU) /**< The byte 0x0C of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0D (0x0DU) /**< The byte 0x0D of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0E (0x0EU) /**< The byte 0x0E of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_0F (0x0FU) /**< The byte 0x0F of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_1C (0x1CU) /**< The byte 0x1C of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_1D (0x1DU) /**< The byte 0x1D of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */
+#define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */
+
+#define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */
+#define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */
+
+/* ---------------------------- 1st DWORD ---------------------------- */
+#define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */
+#define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */
+#define CY_SMIF_SFDP_FAST_READ_1_4_4_Pos (5UL) /**< The SFDP 1-4-4 fast read support (Bit 5) */
+#define CY_SMIF_SFDP_FAST_READ_1_4_4_Msk (0x20UL) /**< The SFDP 1-4-4 fast read support (Bitfield-Mask: 0x01) */
+#define CY_SMIF_SFDP_FAST_READ_1_2_2_Pos (4UL) /**< The SFDP 1-2-2 fast read support (Bit 4) */
+#define CY_SMIF_SFDP_FAST_READ_1_2_2_Msk (0x10UL) /**< The SFDP 1-2-2 fast read support (Bitfield-Mask: 0x01) */
+#define CY_SMIF_SFDP_ADDRESS_BYTES_Pos (1UL) /**< The SFDP number of address bytes (Bit 1) */
+#define CY_SMIF_SFDP_ADDRESS_BYTES_Msk (0x06UL) /**< The SFDP number of address bytes (Bitfield-Mask: 0x03) */
+#define CY_SMIF_SFDP_FAST_READ_1_1_2_Pos (0UL) /**< The SFDP 1-1-2 fast read support (Bit 0) */
+#define CY_SMIF_SFDP_FAST_READ_1_1_2_Msk (0x01UL) /**< The SFDP 1-1-2 fast read support (Bitfield-Mask: 0x01) */
+
+/* ---------------------------- 2nd DWORD ---------------------------- */
+#define CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk (0x80000000UL) /**< Flash memory density bit define if it >= 4 Gbit or <= 2Gbit*/
+
+/* ---------------------------- 3rd DWORD ---------------------------- */
+#define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bit 0) */
+#define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */
+#define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bit 5) */
+#define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bitfield-Mask: 0x07) */
+#define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bit 0) */
+#define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */
+#define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bit 5) */
+#define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bitfield-Mask: 0x07) */
+
+/* ---------------------------- 4th DWORD ---------------------------- */
+#define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bit 0) */
+#define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */
+#define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bit 5) */
+#define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bitfield-Mask: 0x07) */
+#define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bit 0) */
+#define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */
+#define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bit 5) */
+#define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bitfield-Mask: 0x07) */
+
+/* ---------------------------- 10th DWORD --------------------------- */
+#define CY_SMIF_SFDP_ERASE_T1_COUNT_Pos (4UL) /**< Erase Type 1 Erase, Typical time: count (Bits 8:4) */
+#define CY_SMIF_SFDP_ERASE_T1_COUNT_Msk (0x1F0UL) /**< Erase Type 1 Erase, Typical time: count (Bitfield-Mask ) */
+#define CY_SMIF_SFDP_ERASE_T1_UNITS_Pos (9UL) /**< Erase Type 1 Erase, Typical time: units (Bits 10:9) */
+#define CY_SMIF_SFDP_ERASE_T1_UNITS_Msk (0x600UL) /**< Erase Type 1 Erase, Typical time: units (Bitfield-Mask ) */
+#define CY_SMIF_SFDP_ERASE_MUL_COUNT_Pos (0UL) /**< Multiplier from typical erase time to maximum erase time (Bits 3:0) */
+#define CY_SMIF_SFDP_ERASE_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical erase time to maximum erase time (Bitfield-Mask ) */
+
+
+/* ---------------------------- 11th DWORD --------------------------- */
+#define CY_SMIF_SFDP_PAGE_SIZE_Pos (4UL) /**< The SFDP page size (Bit 4) */
+#define CY_SMIF_SFDP_PAGE_SIZE_Msk (0xF0UL) /**< The SFDP page size (Bitfield-Mask: 0x0F) */
+#define CY_SMIF_SFDP_PAGE_PROG_COUNT_Pos (8UL) /**< The SFDP Chip Page Program Typical time: count (Bits 12:8) */
+#define CY_SMIF_SFDP_PAGE_PROG_COUNT_Msk (0x1F00UL) /**< The SFDP Chip Page Program Typical time: count (Bitfield-Mask)*/
+#define CY_SMIF_SFDP_PAGE_PROG_UNITS_Pos (13UL) /**< The SFDP Chip Page Program Typical time: units (Bit 13) */
+#define CY_SMIF_SFDP_PAGE_PROG_UNITS_Msk (0x2000UL) /**< The SFDP Chip Page Program Typical time: units (Bitfield-Mask)*/
+#define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Pos (24UL) /**< The SFDP Chip Erase Typical time: count (Bits 28:24) */
+#define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Msk (0x1F000000UL) /**< The SFDP Chip Erase Typical time: count (Bitfield-Mask) */
+#define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Pos (29UL) /**< The SFDP Chip Erase Typical time: units (Bits 29:30) */
+#define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Msk (0x60000000UL) /**< The SFDP Chip Erase Typical time: units (Bitfield-Mask) */
+#define CY_SMIF_SFDP_PROG_MUL_COUNT_Pos (0UL) /**< Multiplier from typical time to max time for Page or byte program (Bits 3:0) */
+#define CY_SMIF_SFDP_PROG_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical time to max time for Page or byte program (Bitfield-Mask) */
+
+/* ---------------------------- 15th DWORD --------------------------- */
+#define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */
+#define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */
+
+/** \cond INTERNAL */
+
+#define CY_SMIF_BYTES_IN_WORD (4U)
+#define CY_SMIF_BITS_IN_BYTE (8U)
+#define CY_SMIF_BITS_IN_BYTE_ABOVE_4GB (3U) /** density of memory above 4GBit stored as poser of 2 */
+
+
+#define CY_SMIF_MEM_ADDR_VALID(addr, size) (0U == ((addr)%(size))) /* This address must be a multiple of the SMIF XIP memory size */
+#define CY_SMIF_MEM_MAPPED_SIZE_VALID(size) (((size) >= 0x10000U) && (0U == ((size)&((size)-1U))) ) /* must be a power of 2 and greater or equal than 64 KB */
+#define CY_SMIF_MEM_ADDR_SIZE_VALID(addrSize) ((0U < (addrSize)) && ((addrSize) <= 4U))
+
+
+/** \endcond*/
+/** \} group_smif_macros_sfdp */
+
+
+/**
+* \addtogroup group_smif_data_structures_memslot
+* \{
+*/
+
+/** This command structure is used to store the Read/Write command
+ * configuration. */
+typedef struct
+{
+ uint32_t command; /**< The 8-bit command. This value is 0xFFFFFFFF when there is no command present */
+ cy_en_smif_txfr_width_t cmdWidth; /**< The width of the command transfer */
+ cy_en_smif_txfr_width_t addrWidth; /**< The width of the address transfer */
+ uint32_t mode; /**< The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
+ cy_en_smif_txfr_width_t modeWidth; /**< The width of the mode transfer */
+ uint32_t dummyCycles; /**< The number of the dummy cycles. A zero value suggests no dummy cycles */
+ cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */
+} cy_stc_smif_mem_cmd_t;
+
+
+/**
+*
+* This configuration structure of the SMIF memory device is used to store
+* device-specific parameters.
+* These parameters are used to set up the memory mode initialization and the
+* memory API.
+*/
+typedef struct
+{
+ uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the
+ * memory slave device, valid values 1-4 */
+ uint32_t memSize; /**< The size of the memory */
+ cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */
+ cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */
+ cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */
+ cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */
+ uint32_t eraseSize; /**< This specifies the sector size of each Erase */
+ cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */
+ cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */
+ uint32_t programSize; /**< This specifies the page size for programming */
+ cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */
+ cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */
+ cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */
+ cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */
+ uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */
+ uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */
+ uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */
+ uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */
+ uint32_t programTime; /**< Max time for page program cycle time in us */
+} cy_stc_smif_mem_device_cfg_t;
+
+
+/**
+*
+* This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation.
+* This data structure is stored in a fixed location in the flash. The data structure is required
+* for the initialization of the SMIF in the SystemInit.
+*/
+typedef struct
+{
+ /** Determines the slave select where the memory device is placed */
+ cy_en_smif_slave_select_t slaveSelect;
+ /** Determines if the device is memory-mapped, enables the Autodetect
+ * using the SFDP, enables the write capability, or enables the crypto
+ * support for this memory slave */
+ uint32_t flags;
+ /** The data-line selection options for a slave device */
+ cy_en_smif_data_select_t dataSelect;
+ /** The base address the memory slave is mapped to in the PSoC memory map.
+ * This address must be a multiple of the SMIF XIP memory size/capacity. The
+ * SMIF XIP memory region should NOT overlap with other memory regions
+ * (with exception to dual quad mode). Valid when the memory-mapped mode is
+ * enabled.
+ */
+ uint32_t baseAddress;
+ /** The size/capacity allocated in the PSoC memory map for the memory slave
+ * device. The capacity is allocated from the base address. The capacity
+ * must be a power of 2 and greater or equal than 64 KB. Valid when
+ * memory-mapped mode is enabled
+ */
+ uint32_t memMappedSize;
+ /** Defines if this memory device is one of the devices in the dual quad SPI
+ * configuration. Equals the sum of the slave-slot numbers. */
+ uint32_t dualQuadSlots;
+ cy_stc_smif_mem_device_cfg_t* deviceCfg; /**< The configuration of the device */
+} cy_stc_smif_mem_config_t;
+
+
+/**
+*
+* This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation.
+* This data structure is stored in a fixed location in the flash. The data structure is required
+* for the initialization of the SMIF in the SystemInit.
+*/
+typedef struct
+{
+ uint32_t memCount; /**< The number of SMIF memory defined */
+ cy_stc_smif_mem_config_t** memConfig; /**< The pointer to the array of the memory configuration structures of size Memory_count */
+ uint32_t majorVersion; /**< The version of the SMIF driver */
+ uint32_t minorVersion; /**< The version of the SMIF Driver */
+} cy_stc_smif_block_config_t;
+
+
+/** \} group_smif_data_structures_memslot */
+
+
+/**
+* \addtogroup group_smif_mem_slot_functions
+* \{
+*/
+cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base,
+ cy_stc_smif_block_config_t * const blockConfig,
+ cy_stc_smif_context_t *context);
+void Cy_SMIF_Memslot_DeInit(SMIF_Type *base);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteEnable( SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteDisable(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context);
+bool Cy_SMIF_Memslot_IsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t *memDevice,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_QuadEnable(SMIF_Type *base,
+ cy_stc_smif_mem_config_t *memDevice,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdReadSts(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t *status, uint8_t command,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteSts(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ void const *status, uint8_t command,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdChipErase(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base,
+ cy_stc_smif_mem_config_t *memDevice,
+ uint8_t const *sectorAddr,
+ cy_stc_smif_context_t const *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t const *addr,
+ uint8_t *writeBuff,
+ uint32_t size,
+ cy_smif_event_cb_t cmdCmpltCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_CmdRead(SMIF_Type *base,
+ cy_stc_smif_mem_config_t const *memDevice,
+ uint8_t const *addr,
+ uint8_t *readBuff,
+ uint32_t size,
+ cy_smif_event_cb_t cmdCmpltCb,
+ cy_stc_smif_context_t *context);
+cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
+ cy_stc_smif_mem_device_cfg_t *device,
+ cy_en_smif_slave_select_t slaveSelect,
+ cy_en_smif_data_select_t dataSelect,
+ cy_stc_smif_context_t *context);
+
+
+/** \} group_smif_mem_slot_functions */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* (CY_SMIF_MEMORYSLOT_H) */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysanalog/cy_sysanalog.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,100 @@
+/***************************************************************************//**
+* \file cy_sysanalog.c
+* \version 1.0
+*
+* Provides the public functions for the API for the SAR driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "cy_sysanalog.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Configure the AREF to use the local Vref and local IZTAT. Can be used with \ref Cy_SysAnalog_Init. */
+const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_Local =
+{
+ /*.startup */ CY_SYSANALOG_STARTUP_FAST,
+ /*.iztat */ CY_SYSANALOG_IZTAT_SOURCE_LOCAL,
+ /*.vref */ CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V,
+ /*.deepSleep */ CY_SYSANALOG_DEEPSLEEP_DISABLE,
+};
+
+/* Configure the AREF to use the SRSS Vref and SRSS IZTAT. Can be used with \ref Cy_SysAnalog_Init. */
+const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_SRSS =
+{
+ /*.startup */ CY_SYSANALOG_STARTUP_FAST,
+ /*.iztat */ CY_SYSANALOG_IZTAT_SOURCE_SRSS,
+ /*.vref */ CY_SYSANALOG_VREF_SOURCE_SRSS,
+ /*.deepSleep */ CY_SYSANALOG_DEEPSLEEP_DISABLE,
+};
+
+/* Configure the AREF to use the external Vref and local IZTAT. Can be used with \ref Cy_SysAnalog_Init. */
+const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_External =
+{
+ /*.startup */ CY_SYSANALOG_STARTUP_FAST,
+ /*.iztat */ CY_SYSANALOG_IZTAT_SOURCE_LOCAL,
+ /*.vref */ CY_SYSANALOG_VREF_SOURCE_EXTERNAL,
+ /*.deepSleep */ CY_SYSANALOG_DEEPSLEEP_DISABLE,
+};
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_Init
+****************************************************************************//**
+*
+* Initialize the AREF block.
+*
+* \param config
+* Pointer to structure containing configuration data. See \ref cy_stc_sysanalog_config_t
+*
+* \return
+* - \ref CY_SYSANALOG_SUCCESS : initialization complete
+* - \ref CY_SYSANALOG_BAD_PARAM : input pointers are null, initialization incomplete
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_INIT
+*
+*******************************************************************************/
+cy_en_sysanalog_status_t Cy_SysAnalog_Init(const cy_stc_sysanalog_config_t *config)
+{
+ CY_ASSERT_L1(NULL != config);
+
+ cy_en_sysanalog_status_t result;
+ uint32_t ctrlReg = CY_SYSANALOG_DEINIT;
+
+ if (NULL == config)
+ {
+ result = CY_SYSANALOG_BAD_PARAM;
+ }
+ else
+ {
+ CY_ASSERT_L3(CY_SYSANALOG_STARTUP(config->startup));
+ CY_ASSERT_L3(CY_SYSANALOG_DEEPSLEEP(config->deepSleep));
+ CY_ASSERT_L3(CY_SYSANALOG_VREF(config->vref));
+ CY_ASSERT_L3(CY_SYSANALOG_IZTAT(config->iztat));
+
+ ctrlReg = (uint32_t) config->startup \
+ | CY_SYSANALOG_DEFAULT_BIAS_SCALE \
+ | (uint32_t) config->iztat \
+ | (uint32_t) config->vref \
+ | (uint32_t) config->deepSleep;
+
+ PASS_AREF->AREF_CTRL = ctrlReg;
+
+ result = CY_SYSANALOG_SUCCESS;
+ }
+
+ return result;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysanalog/cy_sysanalog.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,589 @@
+/***************************************************************************//**
+* \file cy_sysanalog.h
+* \version 1.0
+*
+* Header file for the system level analog reference driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_sysanalog System Analog Reference Block (SysAnalog)
+* \{
+*
+* This driver provides an interface for configuring the Analog Reference (AREF) block
+* and querying the INTR_CAUSE register of the PASS.
+*
+* The AREF block has the following features:
+*
+* - Generates a voltage reference (VREF) from one of three sources:
+* - Local 1.2 V reference (<b>low noise, optimized for analog performance</b>)
+* - Reference from the SRSS (high noise, not recommended for analog performance)
+* - An external pin
+* - Generates a 1 uA "zero dependency to absolute temperature" (IZTAT) current reference
+* that is independent of temperature variations. It can come from one of two sources:
+* - Local reference (<b>low noise, optimized for analog performance</b>)
+* - Reference from the SRSS (high noise, not recommended for analog performance)
+* - Generates a "proportional to absolute temperature" (IPTAT) current reference
+* - Option to enable local references in Deep Sleep mode
+*
+* The locally generated references are the recommended sources for blocks in the PASS because
+* they have tighter accuracy, temperature stability, and lower noise than the SRSS references.
+* The SRSS references can be used to save power if the low accuracy and higher noise can be tolerated.
+*
+* \image html aref_block_diagram.png
+* \image latex aref_block_diagram.png
+*
+* The outputs of the AREF are consumed by multiple blocks in the PASS and by the CapSense (CSDv2) block.
+* In some cases, these blocks have the option of using the references from the AREF. This selection would be
+* in the respective drivers for these blocks. In some cases, these blocks require the references from the
+* AREF to function.
+*
+* <table class="doxtable">
+* <tr><th>AREF Output</th><th>\ref group_sar "SAR"</th><th>\ref group_ctdac "CTDAC"</th><th>\ref group_ctb "CTB"</th><th>CSDv2</th></tr>
+* <tr>
+* <td>VREF</td>
+* <td>optional</td>
+* <td>optional</td>
+* <td>--</td>
+* <td>optional</td>
+* </tr>
+* <tr>
+* <td>IZTAT</td>
+* <td><b>required</b></td>
+* <td>--</td>
+* <td>optional</td>
+* <td>optional</td>
+* </tr>
+* <tr>
+* <td>IPTAT</td>
+* <td>--</td>
+* <td>--</td>
+* <td><b>required</b></td>
+* <td>--</td>
+* </tr>
+* </table>
+*
+* This driver provides a function to query the INTR_CAUSE register of the PASS.
+* There are two interrupts in the PASS:
+*
+* -# one global interrupt for all CTBs (up to 4)
+* -# one global interrupt for all CTDACs (up to 4)
+*
+* Because the interrupts are global, the INTR_CAUSE register is needed to query which hardware instance
+* triggered the interrupt.
+*
+* \section group_sysanalog_usage Usage
+*
+* \subsection group_sysanalog_usage_init Initialization
+*
+* To configure the AREF, call \ref Cy_SysAnalog_Init and provide a pointer
+* to the configuration structure, \ref cy_stc_sysanalog_config_t. Three predefined structures
+* are provided in this driver to cover a majority of use cases:
+*
+* - \ref Cy_SysAnalog_Fast_Local <b>(recommended for analog performance)</b>
+* - \ref Cy_SysAnalog_Fast_SRSS
+* - \ref Cy_SysAnalog_Fast_External
+*
+* After initialization, call \ref Cy_SysAnalog_Enable to enable the hardware.
+*
+* \subsection group_sysanalog_usage_dsop Deep Sleep Operation
+*
+* The AREF current and voltage references can be enabled to operate in Deep Sleep mode
+* with \ref Cy_SysAnalog_SetDeepSleepMode. There are four options for Deep Sleep operation:
+*
+* - \ref CY_SYSANALOG_DEEPSLEEP_DISABLE : Disable AREF IP block
+* - \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_1 : Enable IPTAT generator for fast wakeup from Deep Sleep mode. IPTAT outputs for CTBs are disabled.
+* - \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_2 : Enable IPTAT generator and IPTAT outputs for CTB
+* - \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF : Enable all generators and outputs: IPTAT, IZTAT, and VREF
+*
+* Recall that the CTB requires the IPTAT reference. For the CTB to operate at the 1 uA current mode in Deep Sleep mode,
+* the AREF must be enabled for \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. For the CTB to operate at the 100 nA
+* current mode in Deep Sleep mode, the AREF must be enabled for \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_2 minimum. In this
+* lower current mode, the AREF IPTAT must be redirected to the CTB IZTAT. See the high level function \ref
+* Cy_CTB_SetCurrentMode in the CTB PDL driver.
+*
+* If the CTDAC is configured to use the VREF in Deep Sleep mode, the AREF must be enabled for \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF.
+*
+* \note
+* The SRSS references are not available to the AREF in Deep Sleep mode. When operating
+* in Deep Sleep mode, the local or external references must be selected.
+*
+* \section group_sysanalog_more_information More Information
+*
+* For more information on the AREF, refer to the technical reference manual (TRM).
+*
+* \section group_sysanalog_MISRA MISRA-C Compliance]
+*
+* This driver does not have any specific deviations.
+*
+* \section group_sysanalog_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sysanalog_macros Macros
+* \defgroup group_sysanalog_functions Functions
+* \defgroup group_sysanalog_globals Global Variables
+* \defgroup group_sysanalog_data_structures Data Structures
+* \defgroup group_sysanalog_enums Enumerated Types
+*/
+
+#if !defined(CY_SYSANALOG_H)
+#define CY_SYSANALOG_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+
+#ifndef CY_IP_MXS40PASS
+ #error "The SysAnalog driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/** \addtogroup group_sysanalog_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SYSANALOG_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_SYSANALOG_DRV_VERSION_MINOR 0
+
+/** PASS driver identifier */
+#define CY_SYSANALOG_ID CY_PDL_DRV_ID(0x17u)
+
+/** \cond INTERNAL */
+#define CY_SYSANALOG_DEINIT (0uL) /**< De-init value for PASS register */
+#define CY_SYSANALOG_DEFAULT_BIAS_SCALE (1uL << PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos) /**< Default AREF bias current scale of 250 nA */
+
+/**< Macros for conditions used in CY_ASSERT calls */
+#define CY_SYSANALOG_STARTUP(startup) (((startup) == CY_SYSANALOG_STARTUP_NORMAL) || ((startup) == CY_SYSANALOG_STARTUP_FAST))
+#define CY_SYSANALOG_DEEPSLEEP(deepSleep) (((deepSleep) == CY_SYSANALOG_DEEPSLEEP_DISABLE) \
+ || ((deepSleep) == CY_SYSANALOG_DEEPSLEEP_IPTAT_1) \
+ || ((deepSleep) == CY_SYSANALOG_DEEPSLEEP_IPTAT_2) \
+ || ((deepSleep) == CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF))
+#define CY_SYSANALOG_VREF(vref) (((vref) == CY_SYSANALOG_VREF_SOURCE_SRSS) \
+ || ((vref) == CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V) \
+ || ((vref) == CY_SYSANALOG_VREF_SOURCE_EXTERNAL))
+#define CY_SYSANALOG_IZTAT(iztat) (((iztat) == CY_SYSANALOG_IZTAT_SOURCE_SRSS) || ((iztat) == CY_SYSANALOG_IZTAT_SOURCE_LOCAL))
+
+/** \endcond */
+
+/** \} group_sysanalog_macros */
+
+/** \addtogroup group_sysanalog_enums
+* \{
+*/
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/** The AREF status/error code definitions */
+typedef enum
+{
+ CY_SYSANALOG_SUCCESS = 0x00uL, /**< Successful */
+ CY_SYSANALOG_BAD_PARAM = CY_SYSANALOG_ID | CY_PDL_STATUS_ERROR | 0x01uL /**< Invalid input parameters */
+}cy_en_sysanalog_status_t;
+
+/** Aref startup mode from power on reset and from Deep Sleep wakeup
+*
+* To achieve the fast startup time (10 us) from Deep Sleep wakeup, the IPTAT generators must be
+* enabled in Deep Sleep mode (see \ref cy_en_sysanalog_deep_sleep_t).
+*
+* The fast startup is the recommended mode.
+*/
+typedef enum
+{
+ CY_SYSANALOG_STARTUP_NORMAL = 0u, /**< Normal startup */
+ CY_SYSANALOG_STARTUP_FAST = 1u << PASS_AREF_AREF_CTRL_AREF_MODE_Pos /**< Fast startup (10 us) - recommended */
+}cy_en_sysanalog_startup_t;
+
+/** AREF voltage reference sources
+*
+* The voltage reference can come from three sources:
+* - the locally generated 1.2 V reference
+* - the SRSS which provides a 0.8 V reference (not available in Deep Sleep mode)
+* - an external device pin
+*/
+typedef enum
+{
+ CY_SYSANALOG_VREF_SOURCE_SRSS = 0u, /**< Use 0.8 V Vref from SRSS. Low accuracy high noise source that is not intended for analog subsystems. */
+ CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V = 1u << PASS_AREF_AREF_CTRL_VREF_SEL_Pos, /**< Use locally generated 1.2 V Vref */
+ CY_SYSANALOG_VREF_SOURCE_EXTERNAL = 2u << PASS_AREF_AREF_CTRL_VREF_SEL_Pos /**< Use externally supplied Vref */
+}cy_en_sysanalog_vref_source_t;
+
+
+/** AREF IZTAT sources
+*
+* The AREF generates a 1 uA "Zero dependency To Absolute Temperature" (IZTAT) current reference
+* that is independent of temperature variations. It can come from one of two sources:
+* - Local reference (1 uA)
+* - Reference from the SRSS (250 nA that is gained by 4. Not available in Deep Sleep mode)
+*/
+typedef enum
+{
+ CY_SYSANALOG_IZTAT_SOURCE_SRSS = 0u, /**< Use 250 nA IZTAT from SRSS and gain by 4 to output 1 uA*/
+ CY_SYSANALOG_IZTAT_SOURCE_LOCAL = 1u << PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos /**< Use locally generated 1 uA IZTAT */
+}cy_en_sysanalog_iztat_source_t;
+
+/** AREF Deep Sleep mode
+*
+* Configure what part of the AREF block is enabled in Deep Sleep mode.
+* - Disable AREF IP block
+* - Enable IPTAT generator for fast wakeup from Deep Sleep mode.
+* IPTAT outputs for CTBs are disabled.
+* - Enable IPTAT generator and IPTAT outputs for CTB
+* - Enable all generators and outputs: IPTAT, IZTAT, and VREF
+*/
+typedef enum
+{
+ CY_SYSANALOG_DEEPSLEEP_DISABLE = 0u, /**< Disable AREF IP block */
+ CY_SYSANALOG_DEEPSLEEP_IPTAT_1 = PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | \
+ (1uL << PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos), /**< Enable IPTAT generator for fast wakeup from Deep Sleep mode
+ IPTAT outputs for CTBs are disabled. */
+ CY_SYSANALOG_DEEPSLEEP_IPTAT_2 = PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | \
+ (2uL << PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos), /**< Enable IPTAT generator and IPTAT outputs for CTB */
+ CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF = PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | \
+ (3uL << PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos) /**< Enable all generators and outputs: IPTAT, IZTAT, and VREF */
+}cy_en_sysanalog_deep_sleep_t;
+
+/** Interrupt cause sources
+*
+* There are two interrupts in the PASS:
+* -# one global interrupt for all CTBs
+* -# one global interrupt for all CTDACs
+*
+* A device could potentially have more than one instance of each IP block,
+* CTB or CTDAC. To find out which instance
+* caused the interrupt, call \ref Cy_SysAnalog_GetIntrCause and compare the returned
+* result with one of these enum values.
+*/
+typedef enum
+{
+ CY_SYSANALOG_INTR_CAUSE_CTB0 = PASS_INTR_CAUSE_CTB0_INT_Msk, /**< Interrupt cause mask for CTB0 */
+ CY_SYSANALOG_INTR_CAUSE_CTB1 = PASS_INTR_CAUSE_CTB1_INT_Msk, /**< Interrupt cause mask for CTB1 */
+ CY_SYSANALOG_INTR_CAUSE_CTB2 = PASS_INTR_CAUSE_CTB2_INT_Msk, /**< Interrupt cause mask for CTB2 */
+ CY_SYSANALOG_INTR_CAUSE_CTB3 = PASS_INTR_CAUSE_CTB3_INT_Msk, /**< Interrupt cause mask for CTB3 */
+ CY_SYSANALOG_INTR_CAUSE_CTDAC0 = PASS_INTR_CAUSE_CTDAC0_INT_Msk, /**< Interrupt cause mask for CTDAC0 */
+ CY_SYSANALOG_INTR_CAUSE_CTDAC1 = PASS_INTR_CAUSE_CTDAC1_INT_Msk, /**< Interrupt cause mask for CTDAC1 */
+ CY_SYSANALOG_INTR_CAUSE_CTDAC2 = PASS_INTR_CAUSE_CTDAC2_INT_Msk, /**< Interrupt cause mask for CTDAC2 */
+ CY_SYSANALOG_INTR_CAUSE_CTDAC3 = PASS_INTR_CAUSE_CTDAC3_INT_Msk /**< Interrupt cause mask for CTDAC3 */
+}cy_en_sysanalog_intr_cause_t;
+
+/** \} group_sysanalog_enums */
+
+/** \addtogroup group_sysanalog_data_structures
+* \{
+*/
+
+/***************************************
+* Configuration Structures
+***************************************/
+
+/** Structure to configure the entire AREF block */
+typedef struct
+{
+ cy_en_sysanalog_startup_t startup; /**< AREF normal or fast start */
+ cy_en_sysanalog_iztat_source_t iztat; /**< AREF 1uA IZTAT source: Local or SRSS */
+ cy_en_sysanalog_vref_source_t vref; /**< AREF Vref: Local, SRSS, or external pin */
+ cy_en_sysanalog_deep_sleep_t deepSleep; /**< AREF Deep Sleep mode */
+}cy_stc_sysanalog_config_t;
+
+/** \} group_sysanalog_data_structures */
+
+/** \addtogroup group_sysanalog_globals
+* \{
+*/
+/***************************************
+* Global Constants
+***************************************/
+
+/** Configure the AREF to use the local Vref and local IZTAT. Can be used with \ref Cy_SysAnalog_Init.
+* Other configuration options are set to:
+* - .startup = CY_PASS_AREF_MODE_FAST
+* - .deepSleep = CY_PASS_AREF_DEEPSLEEP_DISABLE
+*/
+extern const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_Local;
+
+/** Configure the AREF to use the SRSS Vref and SRSS IZTAT. Can be used with \ref Cy_SysAnalog_Init.
+* Other configuration options are set to:
+* - .startup = CY_PASS_AREF_MODE_FAST
+* - .deepSleep = CY_PASS_AREF_DEEPSLEEP_DISABLE
+*/
+extern const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_SRSS;
+
+/** Configure the AREF to use the external Vref and local IZTAT. Can be used with \ref Cy_SysAnalog_Init.
+* Other configuration options are set to:
+* - .startup = CY_PASS_AREF_MODE_FAST
+* - .deepSleep = CY_PASS_AREF_DEEPSLEEP_DISABLE
+*/
+extern const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_External;
+
+/** \} group_sysanalog_globals */
+
+/** \addtogroup group_sysanalog_functions
+* \{
+*/
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+cy_en_sysanalog_status_t Cy_SysAnalog_Init(const cy_stc_sysanalog_config_t *config);
+__STATIC_INLINE void Cy_SysAnalog_DeInit(void);
+__STATIC_INLINE uint32_t Cy_SysAnalog_GetIntrCause(void);
+__STATIC_INLINE void Cy_SysAnalog_SetDeepSleepMode(cy_en_sysanalog_deep_sleep_t deepSleep);
+__STATIC_INLINE cy_en_sysanalog_deep_sleep_t Cy_SysAnalog_GetDeepSleepMode(void);
+__STATIC_INLINE void Cy_SysAnalog_Enable(void);
+__STATIC_INLINE void Cy_SysAnalog_Disable(void);
+__STATIC_INLINE void Cy_SysAnalog_SetArefMode(cy_en_sysanalog_startup_t startup);
+__STATIC_INLINE void Cy_SysAnalog_VrefSelect(cy_en_sysanalog_vref_source_t vref);
+__STATIC_INLINE void Cy_SysAnalog_IztatSelect(cy_en_sysanalog_iztat_source_t iztat);
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_DeInit
+****************************************************************************//**
+*
+* Reset AREF configuration back to power on reset defaults.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_DEINIT
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_DeInit(void)
+{
+ PASS_AREF->AREF_CTRL = CY_SYSANALOG_DEINIT;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_GetIntrCause
+****************************************************************************//**
+*
+* Return the PASS interrupt cause register value.
+*
+* There are two interrupts in the PASS:
+* -# A global interrupt for all CTBs (up to 4)
+* -# A global interrupt for all CTDACs (up to 4)
+*
+* Compare this returned value with the enum values in \ref cy_en_sysanalog_intr_cause_t
+* to determine which block caused/triggered the interrupt.
+*
+* \return uint32_t
+* Interrupt cause register value.
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_GET_INTR_CAUSE
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysAnalog_GetIntrCause(void)
+{
+ return PASS->INTR_CAUSE;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_SetDeepSleepMode
+****************************************************************************//**
+*
+* Set what parts of the AREF are enabled in Deep Sleep mode.
+* - Disable AREF IP block
+* - Enable IPTAT generator for fast wakeup from Deep Sleep mode.
+* IPTAT outputs for CTBs are disabled.
+* - Enable IPTAT generator and IPTAT outputs for CTB
+* - Enable all generators and outputs: IPTAT, IZTAT, and VREF
+*
+* \note
+* The SRSS references are not available to the AREF in Deep Sleep mode. When operating
+* in Deep Sleep mode, the local or external references must be selected.
+*
+* \param deepSleep
+* Select a value from \ref cy_en_sysanalog_deep_sleep_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_SET_DEEPSLEEP_MODE
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_SetDeepSleepMode(cy_en_sysanalog_deep_sleep_t deepSleep)
+{
+ CY_ASSERT_L3(CY_SYSANALOG_DEEPSLEEP(deepSleep));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~(PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk)) | \
+ (uint32_t) deepSleep;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_GetDeepSleepMode
+****************************************************************************//**
+*
+* Return Deep Sleep mode configuration as set by \ref Cy_SysAnalog_SetDeepSleepMode
+*
+* \return
+* A value from \ref cy_en_sysanalog_deep_sleep_t
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_GET_DEEPSLEEP_MODE
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysanalog_deep_sleep_t Cy_SysAnalog_GetDeepSleepMode(void)
+{
+ return (cy_en_sysanalog_deep_sleep_t) (uint32_t) (PASS_AREF->AREF_CTRL & (PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_Enable
+****************************************************************************//**
+*
+* Enable the AREF hardware block.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_ENABLE
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_Enable(void)
+{
+ PASS_AREF->AREF_CTRL |= PASS_AREF_AREF_CTRL_ENABLED_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_Disable
+****************************************************************************//**
+*
+* Disable the AREF hardware block.
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_DISABLE
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_Disable(void)
+{
+ PASS_AREF->AREF_CTRL &= ~PASS_AREF_AREF_CTRL_ENABLED_Msk;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_SetArefMode
+****************************************************************************//**
+*
+* Set the AREF startup mode from power on reset or from Deep Sleep wakeup.
+* The AREF can startup in a normal or fast mode.
+*
+* If fast startup is desired from Deep Sleep wakeup, the IPTAT generators must be enabled during
+* Deep Sleep. This is a minimum Deep Sleep mode setting of \ref CY_SYSANALOG_DEEPSLEEP_IPTAT_1
+* (see also \ref Cy_SysAnalog_SetDeepSleepMode).
+*
+* \param startup
+* Value from enum \ref cy_en_sysanalog_startup_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_SET_AREF_MODE
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_SetArefMode(cy_en_sysanalog_startup_t startup)
+{
+ CY_ASSERT_L3(CY_SYSANALOG_STARTUP(startup));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_AREF_MODE_Msk) | (uint32_t) startup;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_VrefSelect
+****************************************************************************//**
+*
+* Set the source for the Vref. The Vref can come from:
+* - the locally generated 1.2 V reference
+* - the SRSS, which provides a 0.8 V reference (not available to the AREF in Deep Sleep mode)
+* - an external device pin
+*
+* The locally generated reference has higher accuracy, more stability over temperature,
+* and lower noise than the SRSS reference.
+*
+* \param vref
+* Value from enum \ref cy_en_sysanalog_vref_source_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_VREF_SELECT
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_VrefSelect(cy_en_sysanalog_vref_source_t vref)
+{
+ CY_ASSERT_L3(CY_SYSANALOG_VREF(vref));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_VREF_SEL_Msk) | (uint32_t) vref;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysAnalog_IztatSelect
+****************************************************************************//**
+*
+* Set the source for the 1 uA IZTAT. The IZTAT can come from:
+* - the locally generated IZTAT
+* - the SRSS (not available to the AREF in Deep Sleep mode)
+*
+* The locally generated reference has higher accuracy, more stability over temperature,
+* and lower noise than the SRSS reference.
+*
+* \param iztat
+* Value from enum \ref cy_en_sysanalog_iztat_source_t
+*
+* \return None
+*
+* \funcusage
+*
+* \snippet sysanalog_sut_01.cydsn/main_cm0p.c SYSANA_SNIPPET_IZTAT_SELECT
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysAnalog_IztatSelect(cy_en_sysanalog_iztat_source_t iztat)
+{
+ CY_ASSERT_L3(CY_SYSANALOG_IZTAT(iztat));
+
+ PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk) | (uint32_t) iztat;
+}
+
+/** \} group_sysanalog_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /** !defined(CY_SYSANALOG_H) */
+
+/** \} group_sysanalog */
+
+/* [] END OF FILE */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysclk/cy_sysclk.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1739 @@
+/***************************************************************************//**
+* \file cy_sysclk.c
+* \version 1.10.1
+*
+* Provides an API implementation of the sysclk driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+
+#include "cy_sysclk.h"
+#include "syslib/cy_syslib.h"
+#include <math.h>
+#include <stdlib.h>
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/* # of elements in an array */
+#define CY_SYSCLK_N_ELMTS(a) (sizeof(a) / sizeof((a)[0]))
+
+/* ========================================================================== */
+/* =========================== ECO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_eco_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoConfigure
+****************************************************************************//**
+*
+* Configures the external crystal oscillator (ECO) trim bits based on crystal
+* characteristics. This function should be called only when the ECO is disabled.
+*
+* \param freq Operating frequency of the crystal in Hz.
+*
+* \param cLoad Crystal load capacitance in pF.
+*
+* \param esr Effective series resistance of the crystal in ohms.
+*
+* \param driveLevel Crystal drive level in uW.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - ECO configuration completed successfully<br>
+* CY_SYSCLK_BAD_PARAM - One or more invalid parameters<br>
+* CY_SYSCLK_INVALID_STATE - ECO already enabled
+*
+* \note
+* The following calculations are implemented, generally in floating point:
+*
+* \verbatim
+* freqMHz = freq / 1000000
+* max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad
+* gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000
+* Number of amplifier sections = INT(gm_min / 4.5)
+*
+* As a result of the above calculations, max amplitude must be >= 0.5, and the
+* number of amplifier sections must be <= 3, otherwise this function returns with
+* a parameter error.
+*
+* atrim = if (max amplitude < 0.5) then error
+* else 2 * the following:
+* max amplitude < 0.6: 0
+* max amplitude < 0.7: 1
+* max amplitude < 0.8: 2
+* max amplitude < 0.9: 3
+* max amplitude < 1.15: 5
+* max amplitude < 1.275: 6
+* max amplitude >= 1.275: 7
+* wdtrim = if (max amplitude < 0.5) then error
+* else 2 * the following:
+* max amplitude < 1.2: INT(5 * max amplitude) - 2
+* max amplitude >= 1.2: 3
+* gtrim = if (number of amplifier sections > 3) then error
+* else the following:
+* number of amplifier sections > 1: number of amplifier sections
+* number of amplifier sections = 1: 0
+* number of amplifier sections < 1: 1
+* rtrim = if (gtrim = error) then error
+* else the following:
+* freqMHz > 26.8: 0
+* freqMHz > 23.33: 1
+* freqMHz > 16.5: 2
+* freqMHz <= 16.5: 3
+* ftrim = if (atrim = error) then error
+* else INT(atrim / 2)
+* \endverbatim
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_EcoConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel)
+{
+ /* error if ECO is not disabled - any of the 3 enable bits are set */
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_INVALID_STATE;
+ if ((SRSS->CLK_ECO_CONFIG & 0xE0000000ul) == 0ul)
+ {
+ /* calculate intemediate values */
+ float32_t freqMHz = (float32_t)freq / 1000000.0f;
+ float32_t maxAmplitude =
+ (1000.0f * ((float32_t)sqrt((float64_t)((float32_t)driveLevel / (2.0f * (float32_t)esr))))) /
+ (3.14f * freqMHz * (float32_t)cLoad);
+ float32_t gm_min =
+ (788.8f /*5 * 4 * 3.14 * 3.14 * 4*/ * freqMHz * freqMHz * (float32_t)cLoad * (float32_t)cLoad) /
+ 1000000000.0f;
+ uint32_t nAmpSections = (uint32_t)(gm_min / 4.5f);
+
+ /* Error if input parameters cause erroneous intermediate values. */
+ rtnval = CY_SYSCLK_BAD_PARAM;
+ if ((maxAmplitude >= 0.5f) && (nAmpSections <= 3ul))
+ {
+ uint32_t atrim, wdtrim, gtrim, rtrim, ftrim, reg;
+
+ atrim = 2ul * ((maxAmplitude < 0.6f) ? 0ul :
+ ((maxAmplitude < 0.7f) ? 1ul :
+ ((maxAmplitude < 0.8f) ? 2ul :
+ ((maxAmplitude < 0.9f) ? 3ul :
+ ((maxAmplitude < 1.15f) ? 5ul :
+ ((maxAmplitude < 1.275f) ? 6ul : 7ul))))));
+
+ wdtrim = 2ul * ((maxAmplitude < 1.2f) ? (uint32_t)(5.0f * maxAmplitude) - 2ul : 3ul);
+
+ gtrim = ((nAmpSections > 1ul) ? nAmpSections :
+ ((nAmpSections == 1ul) ? 0ul : 1ul));
+
+ rtrim = ((freqMHz > 26.8f) ? 0ul :
+ ((freqMHz > 23.33f) ? 1ul :
+ ((freqMHz > 16.5f) ? 2ul : 3ul)));
+
+ ftrim = atrim / 2ul;
+
+ /* update all fields of trim control register with one write, without
+ changing the ITRIM field in bits [21:16]:
+ gtrim: bits [13:12]
+ rtrim: bits [11:10]
+ ftrim: bits [9:8]
+ atrim: bits [7:4]
+ wdtrim: bits [2:0]
+ */
+ reg = (SRSS->CLK_TRIM_ECO_CTL & ~0x3FFFul);
+ reg |= (gtrim & 3ul) << 12;
+ reg |= (rtrim & 3ul) << 10;
+ reg |= (ftrim & 3ul) << 8;
+ reg |= (atrim & 0x0Ful) << 4;
+ reg |= (wdtrim & 7ul);
+ SRSS->CLK_TRIM_ECO_CTL = reg;
+
+ rtnval = CY_SYSCLK_SUCCESS;
+ } /* if valid parameters */
+ } /* if ECO not enabled */
+
+ return (rtnval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoEnable
+****************************************************************************//**
+*
+* Enables the external crystal oscillator (ECO). This function should be called
+* after \ref Cy_SysClk_EcoConfigure.
+*
+* \param timeoutus Amount of time in microseconds to wait for the ECO to lock.
+* If a lock does not occur, the ECO is stopped. To avoid waiting for a lock, set
+* this parameter to 0.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - ECO locked<br>
+* CY_SYSCLK_TIMEOUT - ECO timed out and did not lock
+* CY_SYSCLK_INVALID_STATE - ECO already enabled
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_EcoEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_INVALID_STATE;
+
+ /* invalid state error if ECO is already enabled */
+ if (_FLD2VAL(SRSS_CLK_ECO_CONFIG_ECO_EN, SRSS->CLK_ECO_CONFIG) == 0ul) /* 1 = enabled */
+ {
+ /* first set ECO enable */
+ SRSS->CLK_ECO_CONFIG |= _VAL2FLD(SRSS_CLK_ECO_CONFIG_ECO_EN, 1ul); /* 1 = enable */
+
+ /* now do the timeout wait for ECO_STATUS, bit ECO_OK */
+ for (;
+ ((_FLD2VAL(SRSS_CLK_ECO_STATUS_ECO_READY, SRSS->CLK_ECO_STATUS) == 0ul)) &&(timeoutus != 0ul);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1u);
+ }
+ rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS);
+ }
+ return (rtnval);
+}
+/** \} group_sysclk_eco_funcs */
+
+
+/* ========================================================================== */
+/* ==================== INPUT MULTIPLEXER SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_path_src_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPathSetSource
+****************************************************************************//**
+*
+* Configures the source for the specified clock path.
+*
+* \param clkPath Selects which clock path to configure; 0 is the first clock
+* path, which is the FLL.
+*
+* \param source \ref cy_en_clkpath_in_sources_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note
+* If calling this function changes an FLL or PLL input frequency, disable the FLL
+* or PLL before calling this function. After calling this function, call the FLL
+* or PLL configure function, for example \ref Cy_SysClk_FllConfigure().
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPathSetSource
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((clkPath < SRSS_NUM_CLKPATH) &&
+ ((source <= CY_SYSCLK_CLKPATH_IN_DSIMUX) ||
+ ((CY_SYSCLK_CLKPATH_IN_DSI <= source) && (source <= CY_SYSCLK_CLKPATH_IN_PILO))))
+ {
+ if (source >= CY_SYSCLK_CLKPATH_IN_DSI)
+ {
+ SRSS->CLK_DSI_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_DSI_SELECT_DSI_MUX, (uint32_t)source);
+ SRSS->CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)CY_SYSCLK_CLKPATH_IN_DSIMUX);
+ }
+ else
+ {
+ SRSS->CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)source);
+ }
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPathGetSource
+****************************************************************************//**
+*
+* Reports which source is selected for the path mux.
+*
+* \param clkPath Selects which clock path to report; 0 is the first clock path,
+* which is the FLL.
+*
+* \return \ref cy_en_clkpath_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPathGetSource
+*
+*******************************************************************************/
+cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath)
+{
+ CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH);
+ cy_en_clkpath_in_sources_t rtnval =
+ (cy_en_clkpath_in_sources_t )_FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[clkPath]);
+ if (rtnval == CY_SYSCLK_CLKPATH_IN_DSIMUX)
+ {
+ rtnval = (cy_en_clkpath_in_sources_t)(CY_SYSCLK_CLKPATH_IN_DSI |
+ (_FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[clkPath])));
+ }
+ return rtnval;
+}
+/** \} group_sysclk_path_src_funcs */
+
+
+/* ========================================================================== */
+/* =========================== FLL SECTION ============================ */
+/* ========================================================================== */
+/* min and max FLL output frequencies, in Hz */
+#define CY_SYSCLK_MIN_FLL_CCO_OUTPUT_FREQ 48000000ul
+#define CY_SYSCLK_MIN_FLL_OUTPUT_FREQ (CY_SYSCLK_MIN_FLL_CCO_OUTPUT_FREQ / 2u)
+#define CY_SYSCLK_MAX_FLL_OUTPUT_FREQ 100000000ul
+
+/**
+* \addtogroup group_sysclk_fll_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllConfigure
+****************************************************************************//**
+*
+* Configures the FLL, for best accuracy optimization.
+*
+* \param inputFreq frequency of input source, in Hz
+*
+* \param outputFreq Desired FLL output frequency, in Hz. Allowable range is
+* 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide
+* by 2 option is required.
+*
+* \param outputMode \ref cy_en_fll_pll_output_mode_t
+* If output mode is bypass, then the output frequency equals the input source
+* frequency regardless of the frequency parameter values.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - FLL successfully configured<br>
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled<br>
+* CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range
+*
+* \note
+* Call this function after changing the FLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+* \note
+* Do not call this function when the FLL is enabled. If it is, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode)
+{
+ cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS;
+
+ /* check for errors */
+ if (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG) != 0u) /* 1 = enabled */
+ {
+ returnStatus = CY_SYSCLK_INVALID_STATE;
+ }
+ else if ((outputFreq < CY_SYSCLK_MIN_FLL_OUTPUT_FREQ) || (CY_SYSCLK_MAX_FLL_OUTPUT_FREQ < outputFreq)) /* invalid output frequency */
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else if (((float32_t)outputFreq / (float32_t)inputFreq) < 2.2f) /* check output/input frequency ratio */
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else
+ { /* return status is OK */
+ }
+
+ /* no error */
+ if (returnStatus == CY_SYSCLK_SUCCESS) /* no errors */
+ {
+ /* If output mode is bypass (input routed directly to output), then done.
+ The output frequency equals the input frequency regardless of the
+ frequency parameters. */
+ if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ cy_stc_fll_manual_config_t config;
+ uint32_t ccoFreq;
+ bool wcoSource = ((Cy_SysClk_ClkPathGetSource(0ul/*FLL*/) == CY_SYSCLK_CLKPATH_IN_WCO) ? true : false);
+
+ config.outputMode = outputMode;
+ /* 1. Output division by 2 is always required. */
+ config.enableOutputDiv = (bool)(1ul);
+ /* 2. Compute the target CCO frequency from the target output frequency and output division. */
+ ccoFreq = outputFreq * ((uint32_t)(config.enableOutputDiv) + 1ul);
+ /* 3. Compute the CCO range value from the CCO frequency */
+ config.ccoRange = ((ccoFreq >= 150339200ul) ? CY_SYSCLK_FLL_CCO_RANGE4 :
+ ((ccoFreq >= 113009380ul) ? CY_SYSCLK_FLL_CCO_RANGE3 :
+ ((ccoFreq >= 84948700ul) ? CY_SYSCLK_FLL_CCO_RANGE2 :
+ ((ccoFreq >= 63855600ul) ? CY_SYSCLK_FLL_CCO_RANGE1 : CY_SYSCLK_FLL_CCO_RANGE0))));
+ {
+ /* constants indexed by ccoRange */
+ const float32_t trimSteps[] = {0.0011034f, 0.001102f, 0.0011f, 0.0011f, 0.00117062f};
+ const float32_t fMargin[] = {43600000.0f, 58100000.0f, 77200000.0f, 103000000.0f, 132000000.0f};
+
+ /* 4. Compute the FLL reference divider value.
+ refDiv is a constant if the WCO is the FLL source, otherwise the formula is
+ refDiv = ROUNDUP((inputFreq / outputFreq) * 250) */
+ config.refDiv = wcoSource ? 19u :
+ ((uint16_t)ceilf(((float32_t)inputFreq / (float32_t)outputFreq) * 250.0f));
+ /* 5. Compute the FLL multiplier value.
+ Formula is fllMult = ccoFreq / (inputFreq / refDiv) */
+ config.fllMult = CY_SYSCLK_DIV_ROUNDUP(ccoFreq, CY_SYSCLK_DIV_ROUND(inputFreq, config.refDiv));
+ /* 6. Compute the lock tolerance.
+ Formula is lock tolerance = 1.5 * fllMult * (((1 + CCO accuracy) / (1 - source clock accuracy)) - 1)
+ We assume CCO accuracy is 0.25%.
+ We assume the source clock accuracy = 1%. This is the accuracy of the IMO.
+ Therefore the formula is lock tolerance = 1.5 * fllMult * 0.012626 = 0.018939 * fllMult */
+ config.lockTolerance = (uint16_t)ceilf((float32_t)(config.fllMult) * 0.018939f);
+ /* 7. Compute the CCO igain and pgain. */
+ {
+ /* intermediate parameters */
+ float32_t kcco = (trimSteps[config.ccoRange] * fMargin[config.ccoRange]) / 1000.0f;
+ float32_t ki_p = (0.85f / (kcco * ((float32_t)(config.refDiv) / (float32_t)inputFreq))) / 1000.0f;
+
+ /* igain and pgain bitfield values correspond to: 1/256, 1/128, ..., 4, 8 */
+ const float32_t gains[] = {0.00390625f, 0.0078125f, 0.015625f, 0.03125f, 0.0625f, 0.125f, 0.25f,
+ 0.5f, 1.0f, 2.0f, 4.0f, 8.0f};
+
+ /* find the largest IGAIN value that is less than or equal to ki_p */
+ for(config.igain = CY_SYSCLK_N_ELMTS(gains) - 1ul;
+ (gains[config.igain] > ki_p) && (config.igain != 0ul); config.igain--){}
+ /* decrement igain if the WCO is the FLL source */
+ if (wcoSource && (config.igain > 0u))
+ {
+ config.igain--;
+ }
+ /* then find the largest PGAIN value that is less than or equal to ki_p - gains[igain] */
+ for(config.pgain = CY_SYSCLK_N_ELMTS(gains) - 1ul;
+ (gains[config.pgain] > (ki_p - gains[config.igain])) && (config.pgain != 0ul);
+ config.pgain--){}
+ /* decrement pgain if the WCO is the FLL source */
+ if (wcoSource && (config.pgain > 0u))
+ {
+ config.pgain--;
+ }
+ }
+ /* 8. Compute the CCO_FREQ bits in CLK_FLL_CONFIG4 register. */
+ config.cco_Freq = (uint16_t)
+ (floor(log((float32_t)ccoFreq / fMargin[config.ccoRange]) /
+ log(1.0f + trimSteps[config.ccoRange])));
+ }
+ /* 9. Compute the settling count, using a 1-usec settling time.
+ Use a constant if the WCO is the FLL source. */
+ {
+ float32_t ttref = (float32_t)config.refDiv / ((float32_t)inputFreq / 1000.0f);
+ float32_t testval = 6000.0f / (float32_t)outputFreq;
+ float32_t divval = ceil((float32_t)inputFreq * 0.000001f);
+ float32_t altval = ceil((divval / ttref) + 1.0f);
+ config.settlingCount = (uint16)(wcoSource ? 200u :
+ ((ttref > testval) ? divval :
+ ((divval > altval) ? divval : altval)));
+ }
+ /* configure FLL based on calculated values */
+ returnStatus = Cy_SysClk_FllManualConfigure(&config);
+ } /* if not bypass output mode */
+
+ else
+ { /* bypass mode */
+ /* update CLK_FLL_CONFIG3 register with divide by 2 parameter */
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)outputMode);
+ }
+ } /* if no error */
+
+ return (returnStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllManualConfigure
+****************************************************************************//**
+*
+* Manually configures the FLL based on user inputs.
+*
+* \param config \ref cy_stc_fll_manual_config_t
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - FLL successfully configured<br>
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled
+*
+* \note
+* Call this function after changing the FLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+* \note
+* Do not call this function when the FLL is enabled. If it is, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllManualConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS;
+
+ CY_ASSERT_L1(config != NULL);
+ /* check for errors */
+ if (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG) != 0u) /* 1 = enabled */
+ {
+ returnStatus = CY_SYSCLK_INVALID_STATE;
+ }
+ else
+ { /* return status is OK */
+ }
+
+ /* no error */
+ if (returnStatus == CY_SYSCLK_SUCCESS) /* no errors */
+ {
+ /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos));
+ uint32_t reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult);
+ /* no assert check for enableOutputDiv, because it's a type boolean */
+ SRSS->CLK_FLL_CONFIG = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, (uint32_t)(config->enableOutputDiv));
+
+ /* update CLK_FLL_CONFIG2 register with 2 parameters */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos));
+ CY_ASSERT_L1(config->lockTolerance <= (SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk >> SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos));
+ reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv);
+ SRSS->CLK_FLL_CONFIG2 = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, config->lockTolerance);
+
+ /* update CLK_FLL_CONFIG3 register with 4 parameters */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->igain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos));
+ CY_ASSERT_L1(config->pgain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos));
+ CY_ASSERT_L1(config->settlingCount <= (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos));
+ reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain);
+ reg |= _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, config->pgain);
+ reg |= _VAL2FLD(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, config->settlingCount);
+ SRSS->CLK_FLL_CONFIG3 = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)(config->outputMode));
+
+ /* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */
+ /* asserts just check for bitfield overflow */
+ CY_ASSERT_L1(config->ccoRange <= (SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos));
+ CY_ASSERT_L1(config->cco_Freq <= (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos));
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange));
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq));
+ } /* if no error */
+
+ return (returnStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllGetConfiguration
+****************************************************************************//**
+*
+* Reports the FLL configuration settings.
+*
+* \param config \ref cy_stc_fll_manual_config_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllGetConfiguration
+*
+*******************************************************************************/
+void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config)
+{
+ CY_ASSERT_L1(config != NULL);
+ /* read 2 parameters from CLK_FLL_CONFIG register */
+ uint32_t tempReg = SRSS->CLK_FLL_CONFIG;
+ config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg);
+ config->enableOutputDiv = (bool)_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, tempReg);
+ /* read 2 parameters from CLK_FLL_CONFIG2 register */
+ tempReg = SRSS->CLK_FLL_CONFIG2;
+ config->refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg);
+ config->lockTolerance = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, tempReg);
+ /* read 4 parameters from CLK_FLL_CONFIG3 register */
+ tempReg = SRSS->CLK_FLL_CONFIG3;
+ config->igain = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, tempReg);
+ config->pgain = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, tempReg);
+ config->settlingCount = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, tempReg);
+ config->outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, tempReg);
+ /* read 1 parameter from CLK_FLL_CONFIG4 register */
+ config->ccoRange = (cy_en_fll_cco_ranges_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_RANGE, SRSS->CLK_FLL_CONFIG4);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllEnable
+****************************************************************************//**
+*
+* Enables the FLL. The FLL should be configured before calling this function.
+*
+* \param timeoutus amount of time in micro seconds to wait for FLL to lock.
+* If lock doesn't occur, FLL is stopped. To avoid waiting for lock set this to 0,
+* and manually check for lock using \ref Cy_SysClk_FllLocked.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - FLL successfully enabled<br>
+* CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock
+*
+* \note
+* While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT.
+* After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t rtnval;
+ bool nonZeroTimeout = (timeoutus != 0ul);
+
+ /* first set the CCO enable bit */
+ SRSS->CLK_FLL_CONFIG4 |= _VAL2FLD(SRSS_CLK_FLL_CONFIG4_CCO_ENABLE, 1ul); /* 1 = enable */
+
+ /* Wait until CCO is ready */
+ for (; (_FLD2VAL(SRSS_CLK_FLL_STATUS_CCO_READY, SRSS->CLK_FLL_STATUS) == 0ul) &&
+ (timeoutus != 0ul);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1u);
+ }
+
+ /* Set the FLL bypass mode to 2 */
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+
+ /* Set the FLL enable bit, if CCO is ready */
+ if ((!nonZeroTimeout) || (nonZeroTimeout && (timeoutus != 0ul)))
+ {
+ SRSS->CLK_FLL_CONFIG |= _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, 1ul); /* 1 = enable */
+ }
+
+ /* now do the timeout wait for FLL_STATUS, bit LOCKED */
+ for (; (_FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS) == 0ul) &&
+ (timeoutus != 0ul);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1u);
+ }
+
+ /* If lock doesn't occur, FLL is stopped. */
+ if (nonZeroTimeout && (timeoutus == 0ul))
+ {
+ (void)Cy_SysClk_FllDisable();
+ }
+ else
+ { /* Lock occurred; we need to clear the unlock occurred bit.
+ Do so by writing a 1 to it. */
+ SRSS->CLK_FLL_STATUS = _VAL2FLD(SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED, 1ul);
+ /* Set the FLL bypass mode to 3 */
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL,
+ (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+
+ rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS);
+ return rtnval;
+}
+/** \} group_sysclk_fll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PLL SECTION ============================ */
+/* ========================================================================== */
+/** \cond INTERNAL */
+/* PLL OUTPUT_DIV bitfield allowable range */
+#define MIN_OUTPUT_DIV 2UL
+#define MAX_OUTPUT_DIV 16UL
+
+/* PLL REFERENCE_DIV bitfield allowable range */
+#define MIN_REF_DIV 1UL
+#define MAX_REF_DIV 18UL
+
+/* PLL FEEDBACK_DIV bitfield allowable ranges, LF and normal modes */
+#define MIN_FB_DIV_LF 19UL
+#define MAX_FB_DIV_LF 56UL
+#define MIN_FB_DIV_NORM 22UL
+#define MAX_FB_DIV_NORM 112UL
+/* PLL FEEDBACK_DIV bitfield allowable range selection */
+#define MIN_FB_DIV ((config->lfMode) ? MIN_FB_DIV_LF : MIN_FB_DIV_NORM)
+#define MAX_FB_DIV ((config->lfMode) ? MAX_FB_DIV_LF : MAX_FB_DIV_NORM)
+
+/* PLL Fvco range allowable ranges, LF and normal modes */
+#define MIN_FVCO_LF 170000000UL
+#define MAX_FVCO_LF 200000000UL
+#define MIN_FVCO_NORM 200000000UL
+#define MAX_FVCO_NORM 400000000UL
+/* PLL Fvco range selection */
+#define MIN_FVCO ((config->lfMode) ? MIN_FVCO_LF : MIN_FVCO_NORM)
+#define MAX_FVCO ((config->lfMode) ? MAX_FVCO_LF : MAX_FVCO_NORM)
+
+/* PLL input and output frequency limits */
+#define MIN_IN_FREQ 4000000UL
+#define MAX_IN_FREQ 64000000UL
+#define MIN_OUT_FREQ ((config->lfMode) ? (MIN_FVCO_LF / MAX_OUTPUT_DIV) : (MIN_FVCO_NORM / MAX_OUTPUT_DIV))
+#define MAX_OUT_FREQ CY_HF_CLK_MAX_FREQ
+/** \endcond */
+
+/**
+* \addtogroup group_sysclk_pll_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllConfigure
+****************************************************************************//**
+*
+* Configures a given PLL.
+* The configuration formula used is:
+* Fout = pll_clk * (P / Q / div_out), where:
+* Fout is the desired output frequency
+* pll_clk is the frequency of the input source
+* P is the feedback divider. Its value is in bitfield FEEDBACK_DIV.
+* Q is the reference divider. Its value is in bitfield REFERENCE_DIV.
+* div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.
+*
+* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_config_t
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - PLL successfully configured<br>
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled<br>
+* CY_SYSCLK_BAD_PARAM - invalid clock path number, or input or desired output frequency is out of valid range
+*
+* \note
+* Call this function after changing the PLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+* \note
+* Do not call this function when the PLL is enabled. If it is, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config)
+{
+ cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS;
+
+ /* check for error */
+ if ((clkPath == 0ul) || (clkPath > SRSS_NUM_PLL)) /* invalid clock path number */
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else if (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[clkPath - 1ul]) != 0u) /* 1 = enabled */
+ {
+ returnStatus = CY_SYSCLK_INVALID_STATE;
+ }
+ /* invalid input frequency */
+ else if (((config->inputFreq) < MIN_IN_FREQ) || (MAX_IN_FREQ < (config->inputFreq)))
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ /* invalid output frequency */
+ else if (((config->outputFreq) < MIN_OUT_FREQ) || (MAX_OUT_FREQ < (config->outputFreq)))
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else
+ { /* returnStatus is OK */
+ }
+
+ /* no errors */
+ if (returnStatus == CY_SYSCLK_SUCCESS)
+ {
+ cy_stc_pll_manual_config_t manualConfig;
+ manualConfig.feedbackDiv = 0ul;
+ manualConfig.referenceDiv = 0ul;
+ manualConfig.outputDiv = 0ul;
+
+ /* If output mode is bypass (input routed directly to output), then done.
+ The output frequency equals the input frequency regardless of the
+ frequency parameters. */
+ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ /* for each possible value of OUTPUT_DIV and REFERENCE_DIV (Q), try
+ to find a value for FEEDBACK_DIV (P) that gives an output frequency
+ as close as possible to the desired output frequency. */
+ uint32_t p, q, out;
+ uint32_t foutBest = 0ul; /* to ensure at least one pass through the for loops below */
+
+ /* REFERENCE_DIV (Q) selection */
+ for (q = MIN_REF_DIV; (q <= MAX_REF_DIV) && (foutBest != (config->outputFreq)); q++)
+ {
+ /* FEEDBACK_DIV (P) selection */
+ for (p = MIN_FB_DIV; (p <= MAX_FB_DIV) && (foutBest != (config->outputFreq)); p++)
+ {
+ /* Calculate the intermediate Fvco, and make sure that it's in range. */
+ uint32_t fvco = (uint32_t)(((uint64_t)(config->inputFreq) * (uint64_t)p) / (uint64_t)q);
+ if ((MIN_FVCO <= fvco) && (fvco <= MAX_FVCO))
+ {
+ /* OUTPUT_DIV selection */
+ for (out = MIN_OUTPUT_DIV; (out <= MAX_OUTPUT_DIV) && (foutBest != (config->outputFreq)); out++)
+ {
+ /* Calculate what output frequency will actually be produced.
+ If it's closer to the target than what we have so far, then save it. */
+ uint32_t fout = ((p * config->inputFreq) / q) / out;
+ if ((uint32_t)abs((int32_t)fout - (int32_t)(config->outputFreq)) <
+ (uint32_t)abs((int32_t)foutBest - (int32_t)(config->outputFreq)))
+ {
+ foutBest = fout;
+ manualConfig.feedbackDiv = p;
+ manualConfig.referenceDiv = q;
+ manualConfig.outputDiv = out;
+ }
+ }
+ }
+ }
+ }
+ /* exit loops if foutBest equals outputFreq */
+ } /* if not bypass output mode */
+
+ /* configure PLL based on calculated values */
+ manualConfig.lfMode = config->lfMode;
+ manualConfig.outputMode = config->outputMode;
+ returnStatus = Cy_SysClk_PllManualConfigure(clkPath, &manualConfig);
+
+ } /* if no error */
+
+ return (returnStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllManualConfigure
+****************************************************************************//**
+*
+* Manually configures a PLL based on user inputs.
+*
+* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_manual_config_t
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - PLL successfully configured<br>
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled<br>
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \note
+* Call this function after changing the PLL input frequency, for example if
+* \ref Cy_SysClk_ClkPathSetSource() is called.
+* \note
+* Do not call this function when the PLL is enabled. If it is, then this function
+* returns immediately with an error return value and no register updates.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllManualConfigure
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS;
+
+ /* check for errors */
+ if ((clkPath == 0ul) || (clkPath > SRSS_NUM_PLL)) /* invalid clock path number */
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else if (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[clkPath - 1ul]) != 0u) /* 1 = enabled */
+ {
+ returnStatus = CY_SYSCLK_INVALID_STATE;
+ }
+ /* valid divider bitfield values */
+ else if ((config->outputDiv < MIN_OUTPUT_DIV) || (MAX_OUTPUT_DIV < config->outputDiv) ||
+ (config->referenceDiv < MIN_REF_DIV) || (MAX_REF_DIV < config->referenceDiv) ||
+ (config->feedbackDiv < (config->lfMode ? MIN_FB_DIV_LF : MIN_FB_DIV)) ||
+ ((config->lfMode ? MAX_FB_DIV_LF : MAX_FB_DIV) < config->feedbackDiv))
+ {
+ returnStatus = CY_SYSCLK_BAD_PARAM;
+ }
+ else
+ { /* returnStatus is OK */
+ }
+
+ /* no errors */
+ if (returnStatus == CY_SYSCLK_SUCCESS)
+ {
+ clkPath--; /* to correctly access PLL config registers structure */
+ /* If output mode is bypass (input routed directly to output), then done.
+ The output frequency equals the input frequency regardless of the frequency parameters. */
+ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
+ {
+ SRSS->CLK_PLL_CONFIG[clkPath] =
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, (uint32_t)(config->feedbackDiv)) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, (uint32_t)(config->referenceDiv)) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, (uint32_t)(config->outputDiv)) |
+ _VAL2FLD(SRSS_CLK_PLL_CONFIG_PLL_LF_MODE, (uint32_t)(config->lfMode));
+ }
+
+ CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->outputMode);
+ } /* if no error */
+
+ return (returnStatus);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllGetConfiguration
+****************************************************************************//**
+*
+* Reports configuration settings for a PLL.
+*
+* \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid.
+*
+* \param config \ref cy_stc_pll_manual_config_t
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - PLL data successfully reported<br>
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllGetConfiguration
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config)
+{
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_BAD_PARAM;
+ if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL))
+ {
+ uint32_t tempReg = SRSS->CLK_PLL_CONFIG[clkPath - 1ul];
+ config->feedbackDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, tempReg);
+ config->referenceDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, tempReg);
+ config->outputDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, tempReg);
+ config->lfMode = (bool)_FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, tempReg);
+ config->outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, tempReg);
+ rtnval = CY_SYSCLK_SUCCESS;
+ }
+ return (rtnval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllEnable
+****************************************************************************//**
+*
+* Enables the PLL. The PLL should be configured before calling this function.
+*
+* \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid.
+*
+* \param timeoutus amount of time in microseconds to wait for the PLL to lock.
+* If lock doesn't occur, PLL is stopped. To avoid waiting for lock set this to 0,
+* and manually check for lock using \ref Cy_SysClk_PllLocked.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - PLL successfully enabled<br>
+* CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock<br>
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllEnable
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_BAD_PARAM;
+ if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL))
+ {
+ clkPath--; /* to correctly access PLL config and status registers structures */
+ /* first set the PLL enable bit */
+ SRSS->CLK_PLL_CONFIG[clkPath] |= _VAL2FLD(SRSS_CLK_PLL_CONFIG_ENABLE, 1ul); /* 1 = enable */
+
+ /* now do the timeout wait for PLL_STATUS, bit LOCKED */
+ for (; (_FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[clkPath]) == 0ul) &&
+ (timeoutus != 0ul);
+ timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1u);
+ }
+ rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS);
+ }
+ return (rtnval);
+}
+/** \} group_sysclk_pll_funcs */
+
+
+/* ========================================================================== */
+/* ==================== Clock Measurement section ===================== */
+/* ========================================================================== */
+
+/* Cy_SysClk_StartClkMeasurementCounters() input parameter saved for use later in other functions. */
+static uint32_t clk1Count1;
+
+/* These variables act as locks to prevent collisions between clock measurement and entry into
+ DeepSleep mode. See Cy_SysClk_DeepSleep(). */
+static bool clkCounting = false;
+static bool preventCounting = false;
+
+/**
+* \addtogroup group_sysclk_calclk_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_StartClkMeasurementCounters
+****************************************************************************//**
+*
+* Assigns clocks to the clock measurement counters, and starts counting. The counters
+* let you measure a clock frequency using another clock as a reference. There are two
+* counters.
+*
+* - One counter (counter1), which is clocked by clock1, is loaded with an initial
+* value and counts down to zero.
+* - The second counter (counter2), which is clocked by clock2, counts up until
+* the first counter reaches zero.
+*
+* Either clock1 or clock2 can be a reference clock; the other clock becomes the
+* measured clock. The reference clock frequency is always known.<br>
+* After calling this function, call \ref Cy_SysClk_ClkMeasurementCountersDone()
+* to determine when counting is done, that is, counter1 has counted down to zero.
+* Then call \ref Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency
+* of the measured clock.
+*
+* \param clock1 The clock for counter1
+*
+* \param count1 The initial value for counter1, from which counter1 counts down to zero.
+*
+* \param clock2 The clock for counter2
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_INVALID_STATE if already doing a measurement<br>
+* CY_SYSCLK_BAD_PARAM if invalid clock input parameter<br>
+* else CY_SYSCLK_SUCCESS
+*
+* \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF.
+* If clock2 frequency is greater than clock1, make sure that count1 is low enough
+* that counter2 does not overflow before counter1 reaches zero.
+* \note The time to complete a measurement is count1 / clock1 frequency.
+* \note The clocks for both counters must have a nonzero frequency, or
+* \ref Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the
+* previous measurement.
+* \note Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement;
+* the measured clock frequency may not be accurate.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_StartClkMeasurementCounters
+*
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2)
+{
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_INVALID_STATE;
+
+ if ((!preventCounting) /* don't start a measurement if about to enter DeepSleep mode */ ||
+ (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1) != 0ul/*1 = done*/))
+ {
+ /* Connect the indicated clocks to the respective counters.
+
+ if clock1 is a slow clock,
+ select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL0, and SRSS_CLK_OUTPUT_FAST.FAST_SEL0 = SLOW_SEL0
+ else if clock1 is a fast clock,
+ select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL0,
+ else error, do nothing and return.
+
+ if clock2 is a slow clock,
+ select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL1, and SRSS_CLK_OUTPUT_FAST.FAST_SEL1 = SLOW_SEL1
+ else if clock2 is a fast clock,
+ select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL1,
+ else error, do nothing and return.
+ */
+ rtnval = CY_SYSCLK_BAD_PARAM;
+ if ((clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK) && (clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK) &&
+ (count1 <= (SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk >> SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos)))
+ {
+ /* Disallow entry into DeepSleep mode while counting. */
+ clkCounting = true;
+
+ if (clock1 < CY_SYSCLK_MEAS_CLK_FAST_CLKS)
+ { /* slow clock */
+ SRSS->CLK_OUTPUT_SLOW = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_SLOW, SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, (uint32_t)clock1);
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0, 7ul/*slow_sel0 output*/);
+ }
+ else
+ { /* fast clock */
+ if (clock1 < CY_SYSCLK_MEAS_CLK_PATH_CLKS)
+ { /* ECO, EXT, ALTHF */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (uint32_t)clock1);
+ }
+ else
+ { /* PATH or CLKHF */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0,
+ (((uint32_t)clock1 >> 8) & 0x0Ful) /*use enum bits [11:8]*/);
+ if (clock1 < CY_SYSCLK_MEAS_CLK_CLKHFS)
+ { /* PATH select */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_PATH_SEL0,
+ ((uint32_t)clock1 & 0x0Ful) /*use enum bits [3:0]*/);
+ }
+ else
+ { /* CLKHF select */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0,
+ ((uint32_t)clock1 & 0x0Ful) /*use enum bits [3:0]*/);
+ }
+ }
+ } /* clock1 fast clock */
+
+ if (clock2 < CY_SYSCLK_MEAS_CLK_FAST_CLKS)
+ { /* slow clock */
+ SRSS->CLK_OUTPUT_SLOW = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_SLOW, SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, (uint32_t)clock2);
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1, 7ul/*slow_sel1 output*/);
+ }
+ else
+ { /* fast clock */
+ if (clock2 < CY_SYSCLK_MEAS_CLK_PATH_CLKS)
+ { /* ECO, EXT, ALTHF */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (uint32_t)clock2);
+ }
+ else
+ { /* PATH or CLKHF */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1,
+ (((uint32_t)clock2 >> 8) & 0x0Ful) /*use enum bits [11:8]*/);
+ if (clock2 < CY_SYSCLK_MEAS_CLK_CLKHFS)
+ { /* PATH select */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_PATH_SEL1,
+ ((uint32_t)clock2 & 0x0Ful) /*use enum bits [3:0]*/);
+ }
+ else
+ { /* CLKHF select */
+ SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1,
+ ((uint32_t)clock2 & 0x0Ful) /*use enum bits [3:0]*/);
+ }
+ }
+ } /* clock2 fast clock */
+
+ rtnval = CY_SYSCLK_SUCCESS;
+
+ /* Save this input parameter for use later, in other functions.
+ No error checking is done on this parameter.*/
+ clk1Count1 = count1;
+
+ /* Counting starts when counter1 is written with a nonzero value. */
+ SRSS->CLK_CAL_CNT1 = clk1Count1;
+ } /* if (clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK && clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK) */
+ } /* if (not done) */
+ return (rtnval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMeasurementCountersGetFreq
+****************************************************************************//**
+*
+* Calculates the frequency of the indicated measured clock (clock1 or clock2).
+*
+* - If clock1 is the measured clock, its frequency is:<br>
+* clock1 frequency = (count1 / count2) * clock2 frequency
+* - If clock2 is the measured clock, its frequency is:<br>
+* clock2 frequency = (count2 / count1) * clock1 frequency
+*
+* Call this function only after counting is done; see \ref Cy_SysClk_ClkMeasurementCountersDone().
+*
+* \param measuredClock False (0) if the measured clock is clock1, true (1)
+* if the measured clock is clock2.
+*
+* \param refClkFreq The reference clock frequency (clock1 or clock2).
+*
+* \return The frequency of the measured clock, in Hz.
+*
+* \funcusage
+* Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.
+*
+*******************************************************************************/
+uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq)
+{
+ volatile uint64_t rtnval = (uint64_t)_FLD2VAL(SRSS_CLK_CAL_CNT2_CAL_COUNTER2, SRSS->CLK_CAL_CNT2);
+
+ /* Done counting; allow entry into DeepSleep mode. */
+ clkCounting = false;
+
+ if (!measuredClock)
+ { /* clock1 is the measured clock */
+ if (rtnval != 0u) /* avoid divide by zero */
+ {
+ rtnval = CY_SYSCLK_DIV_ROUND((uint64_t)clk1Count1 * (uint64_t)refClkFreq, rtnval);
+ }
+ }
+ else
+ { /* clock2 is the measured clock */
+ rtnval = CY_SYSCLK_DIV_ROUND(rtnval * (uint64_t)refClkFreq, (uint64_t)clk1Count1 );
+ }
+ return ((uint32_t)rtnval);
+}
+/** \} group_sysclk_calclk_funcs */
+
+
+/* ========================================================================== */
+/* ========================== TRIM SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_trim_funcs
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloTrim
+****************************************************************************//**
+*
+* Trims the ILO to be as close to 32,768 Hz as possible.
+*
+* \param iloFreq current ILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters
+* and other measurement functions to obtain the current frequency of the ILO.
+*
+* \return Change in trim value; 0 if done, that is, no change in trim value.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_IloTrim
+*
+*******************************************************************************/
+/** \cond INTERNAL */
+/* target frequency */
+#define CY_SYSCLK_ILO_TARGET_FREQ 32768u
+/** \endcond */
+
+int32_t Cy_SysClk_IloTrim(uint32_t iloFreq)
+{
+ /* Nominal trim step size is 1.5% of "the frequency". Using the target frequency. */
+ const uint32_t trimStep = CY_SYSCLK_DIV_ROUND((uint32_t)CY_SYSCLK_ILO_TARGET_FREQ * 15ul, 1000ul);
+
+ uint32_t newTrim = 0ul;
+ uint32_t curTrim = 0ul;
+
+ /* Do nothing if iloFreq is already within one trim step from the target */
+ uint32_t diff = (uint32_t)abs((int32_t)iloFreq - (int32_t)CY_SYSCLK_ILO_TARGET_FREQ);
+ if (diff >= trimStep)
+ {
+ curTrim = _FLD2VAL(SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, SRSS->CLK_TRIM_ILO_CTL);
+ if (iloFreq > CY_SYSCLK_ILO_TARGET_FREQ)
+ { /* iloFreq is too high. Reduce the trim value */
+ newTrim = curTrim - CY_SYSCLK_DIV_ROUND(iloFreq - CY_SYSCLK_ILO_TARGET_FREQ, trimStep);
+ }
+ else
+ { /* iloFreq too low. Increase the trim value. */
+ newTrim = curTrim + CY_SYSCLK_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ - iloFreq, trimStep);
+ }
+
+ /* Update the trim value */
+ CY_SYSCLK_CLR_SET(SRSS->CLK_TRIM_ILO_CTL, SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, newTrim);
+ }
+ return (int32_t)(curTrim - newTrim);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloTrim
+****************************************************************************//**
+*
+* Trims the PILO to be as close to 32,768 Hz as possible.
+*
+* \param piloFreq current PILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters
+* and other measurement functions to obtain the current frequency of the PILO.
+*
+* \return Change in trim value; 0 if done, that is, no change in trim value.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PiloTrim
+*
+*******************************************************************************/
+/** \cond INTERNAL */
+/* target frequency */
+#define CY_SYSCLK_PILO_TARGET_FREQ 32768ul
+/* nominal trim step size */
+#define CY_SYSCLK_PILO_TRIM_STEP 5ul
+/** \endcond */
+
+int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq)
+{
+ uint32_t newTrim = 0ul;
+ uint32_t curTrim = 0ul;
+
+ /* Do nothing if piloFreq is already within one trim step from the target */
+ uint32_t diff = (uint32_t)abs((int32_t)piloFreq - (int32_t)CY_SYSCLK_PILO_TARGET_FREQ);
+ if (diff >= CY_SYSCLK_PILO_TRIM_STEP)
+ {
+ curTrim = Cy_SysClk_PiloGetTrim();
+ if (piloFreq > CY_SYSCLK_PILO_TARGET_FREQ)
+ { /* piloFreq too high. Decrease the trim value. */
+ newTrim = curTrim - CY_SYSCLK_DIV_ROUND(piloFreq - CY_SYSCLK_PILO_TARGET_FREQ, CY_SYSCLK_PILO_TRIM_STEP);
+ if ((int32_t)newTrim < 0) /* limit underflow */
+ {
+ newTrim = 0;
+ }
+ }
+ else
+ { /* piloFreq too low. Increase the trim value. */
+ newTrim = curTrim + CY_SYSCLK_DIV_ROUND(CY_SYSCLK_PILO_TARGET_FREQ - piloFreq, CY_SYSCLK_PILO_TRIM_STEP);
+ if (newTrim >= SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk) /* limit overflow */
+ {
+ newTrim = SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk;
+ }
+ }
+ Cy_SysClk_PiloSetTrim(newTrim);
+ }
+
+ return (int32_t)(curTrim - newTrim);
+}
+/** \} group_sysclk_trim_funcs */
+
+
+/* ========================================================================== */
+/* ====================== POWER MANAGEMENT SECTION ==================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pm_funcs
+* \{
+*/
+/** \cond INTERNAL */
+/* timeout count for use in function Cy_SysClk_DeepSleepCallback() is sufficiently large for ~1 second at 100 MHz */
+#define TIMEOUTK 5000000ul
+/** \endcond */
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_DeepSleepCallback
+****************************************************************************//**
+*
+* Callback function to be used when entering chip deep-sleep mode. This function is
+* applicable for when either the FLL or the PLL is enabled. It performs the following:
+*
+* 1. Before entering deep-sleep, the clock configuration is saved in SRAM. If the
+* FLL/PLL source is the ECO, then the source is updated to the IMO.
+* 2. Upon wakeup from deep-sleep, the function restores the configuration and
+* waits for the FLL/PLL to regain their frequency locks.
+*
+* The function prevents entry into DeepSleep mode if the measurement counters
+* are currently counting; see \ref Cy_SysClk_StartClkMeasurementCounters.
+*
+* This function can be called during execution of \ref Cy_SysPm_DeepSleep.
+* To do so, register this function as a callback before calling
+* \ref Cy_SysPm_DeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback
+* type and call \ref Cy_SysPm_RegisterCallback.
+*
+* \note This function must be the last callback function that is registered.
+* Doing so minimizes the time spent on low power mode entry and exit. In the case
+* where the ECO sources the FLL/PLL, this also allows the ECO to stabilize before
+* reconnecting it to the FLL or PLL.
+*
+* \param callbackParams
+* structure with the syspm callback parameters,
+* see \ref cy_stc_syspm_callback_params_t.
+*
+* \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing
+* a clock measurement, otherwise Fail. Timeout if timeout waiting for FLL or a PLL
+* to regain its frequency lock.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_DeepSleepCallback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
+{
+ /* bitmapped paths and roots that may be affected by FLL or PLL being sourced by ECO */
+ static uint16_t changedSourcePaths;
+
+ cy_en_syspm_status_t rtnval = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L1(callbackParams != NULL);
+
+ /* Entry into DeepSleep mode tests */
+ if (callbackParams->mode == CY_SYSPM_CHECK_READY)
+ {
+ /* Don't allow entry into DeepSleep mode if currently measuring a frequency. */
+ if (clkCounting)
+ {
+ rtnval = CY_SYSPM_FAIL;
+ }
+ else
+ { /* Indicating that we can go into DeepSleep. Before doing so ... */
+ uint32_t fllpll; /* 0 = FLL, all other values = a PLL */
+
+ /* initialize record of changed paths */
+ changedSourcePaths = 0u;
+
+ /* for FLL and each PLL, */
+ for (fllpll = 0ul; fllpll < (SRSS_NUM_PLL + 1ul); fllpll++)
+ {
+ /* If FLL or PLL is enabled, */
+ if (0ul != ((fllpll == 0ul) ? (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG)) :
+ (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[fllpll - 1ul]))))
+ {
+ /* and the FLL or PLL has ECO as a source, */
+ if (Cy_SysClk_ClkPathGetSource(fllpll) == CY_SYSCLK_CLKPATH_IN_ECO)
+ {
+ /* Change this FLL or PLL source to IMO */
+ (void)Cy_SysClk_ClkPathSetSource(fllpll, CY_SYSCLK_CLKPATH_IN_IMO);
+ /* keep a record that this FLL or PLL's source was changed from ECO */
+ changedSourcePaths |= (uint16_t)(1u << fllpll);
+ }
+
+ /* Set the FLL/PLL bypass mode to 2 */
+ if(fllpll == 0UL)
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+ else
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[fllpll - 1ul], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT);
+ }
+ }
+ }
+
+ /* Prevent starting a new clock measurement until after we've come back from DeepSleep. */
+ preventCounting = true;
+ }
+ }
+
+ /* After return from DeepSleep, for each FLL and PLL, if needed, restore the source to ECO.
+ And block until the FLL or PLL has regained its frequency locks. */
+ else if (callbackParams->mode == CY_SYSPM_AFTER_TRANSITION)
+ {
+ /* if any FLL/PLL was sourced by the ECO, timeout wait for the ECO to become fully stabilized again. */
+ if (changedSourcePaths != 0u)
+ {
+ uint32_t timeout;
+ /* Cy_SysClk_EcoGetStatus()return value 2ul = fully stabilized */
+ for (timeout = TIMEOUTK; (timeout != 0ul) && (Cy_SysClk_EcoGetStatus() != 2ul); timeout--){}
+ if (timeout == 0ul)
+ {
+ rtnval = CY_SYSPM_TIMEOUT;
+ }
+ }
+
+ if(rtnval == CY_SYSPM_SUCCESS)
+ {
+ /* for FLL and each PLL, */
+ uint32_t fllpll; /* 0 = FLL, all other values = a PLL */
+ for (fllpll = 0ul; fllpll < (SRSS_NUM_PLL + 1ul); fllpll++)
+ {
+ /* If FLL or PLL is enabled, */
+ if (0ul != ((fllpll == 0ul) ? (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG)) :
+ (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[fllpll - 1ul]))))
+ {
+ /* check the record that this FLL or PLL's source was changed from ECO */
+ if ((changedSourcePaths & (uint16_t)(1u << fllpll)) != 0u)
+ {
+ /* Change this FLL or PLL source back to ECO */
+ (void)Cy_SysClk_ClkPathSetSource(fllpll, CY_SYSCLK_CLKPATH_IN_ECO);
+ }
+
+ /* Timeout wait for FLL or PLL to regain lock. */
+ uint32_t timout;
+ for (timout = TIMEOUTK; timout != 0ul; timout--)
+ {
+ if (true == ((fllpll == 0ul) ? Cy_SysClk_FllLocked() : Cy_SysClk_PllLocked(fllpll)))
+ {
+ break;
+ }
+ }
+ if (timout == 0ul)
+ {
+ rtnval = CY_SYSPM_TIMEOUT;
+ }
+ else
+ {
+ /* Set the FLL/PLL bypass mode to 3 */
+ if(fllpll == 0UL)
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+ else
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[fllpll - 1ul], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT);
+ }
+ }
+ }
+ }
+ }
+
+ /* Allow clock measurement. */
+ preventCounting = false;
+ }
+
+ /* No other modes need be checked. */
+ else
+ {
+ }
+
+ return rtnval;
+}
+/** \} group_sysclk_pm_funcs */
+
+
+/* ========================================================================== */
+/* =========================== WCO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_wco_funcs
+* \{
+*/
+#if (SRSS_WCOCSV_PRESENT != 0) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoConfigureCsv
+****************************************************************************//**
+*
+* Configure the WCO clock supervisor (CSV).
+*
+* \param config \ref cy_stc_wco_csv_config_t
+*
+* \note
+* If loss detection is enabled, writes to other register bits are ignored.
+* Therefore loss detection is disabled before writing the config structure
+* members to the CTL register. Note that one of the config structure members is
+* an enable bit.
+*******************************************************************************/
+void Cy_SysClk_WcoConfigureCsv(const cy_stc_wco_csv_config_t *config)
+{
+ CY_ASSERT_L1(config != NULL);
+ CY_ASSERT_L3(config->supervisorClock <= CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO);
+ CY_ASSERT_L3(config->lossWindow <= CY_SYSCLK_CSV_LOSS_512_CYCLES);
+ CY_ASSERT_L3(config->lossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET);
+
+ /* First clear all bits, including the enable bit; disable loss detection. */
+ SRSS->CLK_CSV_WCO_CTL = 0ul;
+ /* Then write the structure elements (which include an enable bit) to the register. */
+ SRSS->CLK_CSV_WCO_CTL = _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_MUX, (uint32_t)config->supervisorClock) |
+ _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_WINDOW, (uint32_t)(config->lossWindow)) |
+ _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_ACTION, (uint32_t)(config->lossAction)) |
+ _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_EN, config->enableLossDetection);
+}
+#endif /* (SRSS_WCOCSV_PRESENT != 0) || defined(CY_DOXYGEN) */
+/** \} group_sysclk_wco_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clkHf[n] SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_hf_funcs
+* \{
+*/
+#if (SRSS_MASK_HFCSV != 0) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfConfigureCsv
+****************************************************************************//**
+*
+* Configures the clkHf clock supervisor (CSV).
+*
+* \param clkHf selects which clkHf CSV to configure.
+*
+* \param config \ref cy_stc_clkhf_csv_config_t
+*
+* \return Error / status code: CY_SYSCLK_INVALID_STATE if clkHf CSV is not present
+* in the device, else CY_SYSCLK_SUCCESS
+*
+* \note
+* If loss detection is enabled, writes to other register bits are ignored.
+* Therefore loss detection is disabled before writing the config structure
+* members to the CTL register. Note that one of the config structure members is
+* an enable bit.
+*******************************************************************************/
+cy_en_sysclk_status_t Cy_SysClk_ClkHfConfigureCsv(uint32_t clkHf, const cy_stc_clkhf_csv_config_t *config)
+{
+ CY_ASSERT_L1(clkHf < SRSS_NUM_HFROOT);
+ CY_ASSERT_L1(config != NULL);
+ CY_ASSERT_L3(config->supervisorClock <= CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF);
+ CY_ASSERT_L3(config->frequencyAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET);
+ CY_ASSERT_L3(config->lossWindow <= CY_SYSCLK_CSV_LOSS_512_CYCLES);
+ CY_ASSERT_L3(config->lossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET);
+
+ /* First update the limit bits; this can be done regardless of enable state. */
+ SRSS->CLK_CSV[clkHf].HF_LIMIT = _VAL2FLD(CLK_CSV_HF_LIMIT_UPPER_LIMIT, config->frequencyUpperLimit) |
+ _VAL2FLD(CLK_CSV_HF_LIMIT_LOWER_LIMIT, config->frequencyLowerLimit);
+ /* Then clear all CTL register bits, including the enable bit; disable loss detection. */
+ SRSS->CLK_CSV[clkHf].HF_CTL = 0ul;
+ /* Finally, write the structure elements (which include an enable bit) to the CTL register. */
+ SRSS->CLK_CSV[clkHf].HF_CTL = _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_EN, config->enableLossDetection) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_ACTION, (uint32_t)(config->lossAction)) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_EN, config->enableFrequencyFaultDetection) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_ACTION, (uint32_t)(config->frequencyAction)) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_WINDOW, (uint32_t)(config->lossWindow)) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_MUX, (uint32_t)(config->supervisorClock)) |
+ _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_WINDOW, config->supervisingWindow);
+ return CY_SYSCLK_SUCCESS; /* placeholder */
+}
+#endif /* (SRSS_MASK_HFCSV != 0) || defined(CY_DOXYGEN) */
+/** \} group_sysclk_clk_hf_funcs */
+
+
+/* ========================================================================== */
+/* ===================== clk_peripherals SECTION ====================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_peripheral_funcs
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetFrequency
+****************************************************************************//**
+*
+* Reports the frequency of the output of a given peripheral divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return The frequency, in Hz.
+*
+* \note
+* The reported frequency may be zero, which indicates unknown. This happens if
+* the source input is clk_ext, ECO, clk_althf, dsi_out, or clk_altlf.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphGetFrequency
+*
+*******************************************************************************/
+uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ uint32_t rtnval = 0ul; /* 0 = unknown frequency */
+
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)));
+
+ /* FLL or PLL configuration parameters */
+ union
+ {
+ cy_stc_fll_manual_config_t fll;
+ struct
+ {
+ uint8_t feedbackDiv;
+ uint8_t referenceDiv;
+ uint8_t outputDiv;
+ } pll;
+ } fllpll = {0ul};
+
+ /* variables holding intermediate clock sources and dividers */
+ cy_en_fll_pll_output_mode_t mode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO; /* FLL or PLL mode; n/a for direct */
+ bool locked = 0; /* FLL or PLL lock status; n/a for direct */
+ cy_en_clkpath_in_sources_t source; /* source input for path (FLL, PLL, or direct) */
+ uint32_t source_freq; /* source clock frequency, in Hz */
+ cy_en_clkhf_in_sources_t path; /* source input for root 0 (clkHf[0]) */
+ uint32_t path_freq = 0ul; /* path (FLL, PLL, or direct) frequency, in Hz */
+ uint32_t root_div; /* root prescaler (1/2/4/8) */
+ uint32_t clkHf0_div; /* clkHf[0] predivider to clk_peri */
+
+ /* clk_peri divider to selected peripheral clock */
+ struct
+ {
+ uint32_t integer;
+ uint32_t frac;
+ } clkdiv = {0ul, 0ul};
+
+ /* Start by finding the source input for root 0 (clkHf[0]) */
+ path = Cy_SysClk_ClkHfGetSource(0ul);
+
+ if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */
+ {
+ Cy_SysClk_FllGetConfiguration(&fllpll.fll);
+ source = Cy_SysClk_ClkPathGetSource(0ul);
+ mode = fllpll.fll.outputMode;
+ locked = Cy_SysClk_FllLocked();
+ }
+ else if ((uint32_t)path <= (uint32_t)SRSS_NUM_PLL) /* PLL? (always path 1 - N)*/
+ {
+ cy_stc_pll_manual_config_t config;
+ (void)Cy_SysClk_PllGetConfiguration((uint32_t)path, &config);
+ fllpll.pll.feedbackDiv = config.feedbackDiv;
+ fllpll.pll.referenceDiv = config.referenceDiv;
+ fllpll.pll.outputDiv = config.outputDiv;
+ mode = config.outputMode;
+ source = Cy_SysClk_ClkPathGetSource((uint32_t)path);
+ locked = Cy_SysClk_PllLocked((uint32_t)path);
+ }
+ else /* assume clk_path < SRSS_NUM_CLKPATH */
+ { /* Direct select path. Use PLL function to get the source. */
+ source = Cy_SysClk_ClkPathGetSource((uint32_t)path);
+ }
+
+ /* get the frequency of the source, i.e., the path mux input */
+ switch(source)
+ {
+ case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */
+ source_freq = 8000000ul; /*Hz*/
+ break;
+ case CY_SYSCLK_CLKPATH_IN_ILO: /* ILO and WCO frequencies are nominally 32.768 kHz */
+ case CY_SYSCLK_CLKPATH_IN_WCO:
+ source_freq = 32768ul; /*Hz*/
+ break;
+ default:
+ /* don't know the frequency of clk_ext, ECO, clk_althf, dsi_out, or clk_altlf */
+ source_freq = 0ul; /* unknown frequency */
+ break;
+ }
+ if (source_freq != 0ul)
+ {
+ /* Calculate the path frequency */
+ if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */
+ {
+ path_freq = source_freq; /* for bypass mode */
+ /* if not bypass mode, apply the dividers calculation */
+ if ((mode == CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT) || ((mode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) && (locked != 0ul)))
+ {
+ /* Ffll_out = Ffll_clk * FLL_MULT / FLL_REF_DIV / (FLL_OUTPUT_DIV + 1), where:
+ * FLL_MULT, REFERENCE_DIV, and OUTPUT_DIV are FLL configuration register bitfields
+ * Check for possible divide by 0.
+ */
+ if (fllpll.fll.refDiv != 0ul)
+ {
+ path_freq = (uint32_t)(((uint64_t)path_freq * (uint64_t)fllpll.fll.fllMult) /
+ (uint64_t)fllpll.fll.refDiv) /
+ ((uint32_t)(fllpll.fll.enableOutputDiv) + 1ul);
+ }
+ else
+ {
+ path_freq = 0ul; /* error, one of the divisors is 0 */
+ }
+ }
+ }
+ else if ((uint32_t)path <= (uint32_t)SRSS_NUM_PLL) /* PLL? (always path 1 - N)*/
+ {
+ path_freq = source_freq; /* for bypass mode */
+ /* if not bypass mode, apply the dividers calculation */
+ if ((mode == CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT) || ((mode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) && (locked != 0ul)))
+ {
+ /* Fpll_out = Fpll_clk * FEEDBACK_DIV / REFERENCE_DIV / OUTPUT_DIV, where:
+ * FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV are PLL configuration register bitfields
+ * Check for possible divide by 0.
+ */
+ if ((fllpll.pll.referenceDiv != 0ul) && (fllpll.pll.outputDiv != 0ul))
+ {
+ path_freq = (uint32_t)(((uint64_t)source_freq * (uint64_t)fllpll.pll.feedbackDiv) /
+ (uint64_t)fllpll.pll.referenceDiv) /
+ (uint32_t)fllpll.pll.outputDiv;
+ }
+ else
+ {
+ path_freq = 0ul; /* error, one of the divisors is 0 */
+ }
+ }
+ }
+ else /* assume clk_path < SRSS_NUM_CLKPATH */
+ { /* direct select path */
+ path_freq = source_freq;
+ }
+
+ /* get the prescaler value for root 0, or clkHf[0]: 1/2/4/8 */
+ root_div = 1ul << (uint32_t)Cy_SysClk_ClkHfGetDivider(0ul);
+
+ /* get the predivider value for clkHf[0] to clk_peri */
+ clkHf0_div = (uint32_t)Cy_SysClk_ClkPeriGetDivider() + 1ul;
+
+ /* get the divider value for clk_peri to the selected peripheral clock */
+ switch(dividerType)
+ {
+ case CY_SYSCLK_DIV_8_BIT:
+ case CY_SYSCLK_DIV_16_BIT:
+ clkdiv.integer = (uint32_t)Cy_SysClk_PeriphGetDivider(dividerType, dividerNum);
+ /* frac = 0 means it's an integer divider */
+ break;
+ case CY_SYSCLK_DIV_16_5_BIT:
+ case CY_SYSCLK_DIV_24_5_BIT:
+ (void)Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &clkdiv.integer, &clkdiv.frac);
+ break;
+ default:
+ break;
+ }
+ /* Divide the path input frequency down, and return the result.
+ Stepping through the following code shows the frequency at each stage.
+ */
+ rtnval = path_freq / root_div; /* clkHf[0] frequency */
+ rtnval /= clkHf0_div; /* clk_peri frequency */
+ /* For fractional dividers, the divider is (int + 1) + frac/32.
+ * Use the fractional value to round the divider to the nearest integer.
+ */
+ rtnval /= (clkdiv.integer + 1ul + ((clkdiv.frac >= 16ul) ? 1ul : 0ul)); /* peripheral divider output frequency */
+ }
+
+ return rtnval;
+}
+/** \} group_sysclk_clk_peripheral_funcs */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysclk/cy_sysclk.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2736 @@
+/***************************************************************************//**
+* \file cy_sysclk.h
+* \version 1.10.1
+*
+* Provides an API declaration of the sysclk driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_sysclk System Clock (SysClk)
+* \{
+* The System Clock (SysClk) driver contains the API for configuring system and
+* peripheral clocks. Firmware uses the API to configure , enable, or disable
+* a clock.
+*
+* The clock system includes a variety of resources that can vary per device, including:
+* - Internal clock sources such as internal oscillators
+* - External clock sources such as crystal oscillators or a signal on an I/O pin
+* - Generated clocks such as an FLL, a PLL, and peripheral clocks
+*
+* Consult the Technical Reference Manual for your device for details of the
+* clock system.
+*
+* The PDL defines clock system capabilities in:\n
+* devices\<family\>/<series\>/include\<series\>_config.h. (E.g.
+* devices/psoc6/psoc63/include/psoc63_config.h).
+* User-configurable clock speeds are defined in the file system_<series>.h.
+*
+* As an illustration of the clocking system, the following diagram shows the
+* PSoC 63 series clock tree. The actual tree may vary depending on the device series.
+* 
+*
+* The sysclk driver supports multiple peripheral clocks, as well as the fast
+* clock, slow clock, backup domain clock, timer clock, and pump clock. The API
+* for any given clock contains the functions to manage that clock. Functions
+* for clock measurement and trimming are also provided.
+*
+* \section group_sysclk_configuration Configuration Considerations
+* The availability of clock functions depend on the availability of the chip
+* resources that support those functions. Consult the device TRM before
+* attempting to use these functions.
+*
+* LPActive and LPSleep power modes limit the maximum clock frequency allowed
+* on the device. Refer to the SysPm driver and the TRM for details.
+*
+* \section group_sysclk_more_information More Information
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_sysclk_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>1.2</td>
+* <td>R</td>
+* <td>No reliance on undefined behavior.</td>
+* <td>Calculation of an absolute value in the FLL and PLL configuration.</td>
+* </tr>
+* <tr>
+* <td>5.6</td>
+* <td>R</td>
+* <td>No identifier in one name space should have the same spelling as an identifier in another name space, with the
+* exception of structure member and union member names.</td>
+* <td>The "mode" and "retval" are used as a structure/union member they are a label, tag or ordinary
+* identifier.</td>
+* </tr>
+* <tr>
+* <td>10.1</td>
+* <td>R</td>
+* <td>The value of an expression of integer type shall not be implicitly converted to a different, underlying type
+* if the expression is complex.</td>
+* <td>Use of a Cypress defined macro to access memory mapped objects.
+* Use of a Cypress defined macro to divide with rounding.</td>
+* </tr>
+* <tr>
+* <td>10.2</td>
+* <td>R</td>
+* <td>The value of an expression of floating type shall not be implicitly converted to a different type if:
+* a) it is not a conversion to a wider floating type, or
+* b) the expression is complex, or
+* c) the expression is a function argument, or
+* d) the expression is a return expression.</td>
+* <td>The operands of this relational operator are expressions of different "essential type" categories
+* (enum and unsigned).</td>
+* </tr>
+* <tr>
+* <td>10.3</td>
+* <td>R</td>
+* <td>A composite integer expression is being cast to a wider type.</td>
+* <td>Use of a Cypress defined macro to access memory-mapped objects. Calculating the clock parameters.</td>
+* </tr>
+* <tr>
+* <td>10.4</td>
+* <td>R</td>
+* <td>A composite floating point expression is being cast to double, or unsigned.</td>
+* <td>Use of the C library sqrt() function. Casting a floating-point calculation result to an integer.</td>
+* </tr>
+* <tr>
+* <td>10.5</td>
+* <td>R</td>
+* <td>The value of an expression of integer type shall not be implicitly converted to a different, underlying type
+* if the expression is complex.</td>
+* <td>Use of a Cypress defined macro to access memory-mapped objects.</td>
+* </tr>
+* <tr>
+* <td>12.1</td>
+* <td>A</td>
+* <td>Extra parentheses recommended.</td>
+* <td>Ternary operator uses constants; extra parentheses not needed.</td>
+* </tr>
+* <tr>
+* <td>12.2</td>
+* <td>A</td>
+* <td>The value of an expression must be the same under any order of evaluation that the standard permits.</td>
+* <td>The "rtnval" is modified more than once between the sequence points - the evaluation order is not specified.</td>
+* </tr>
+* <tr>
+* <td>12.4</td>
+* <td>A</td>
+* <td>The right hand operand of a logical && or || operator shall not contain side effects.</td>
+* <td>No side effect in this case.</td>
+* </tr>
+* <tr>
+* <td>13.4</td>
+* <td>R</td>
+* <td>The controlling expression of a for statement shall not contain any objects of floating type.</td>
+* <td>Scanning through a list of floating point values.</td>
+* </tr>
+* <tr>
+* <td>16.7</td>
+* <td>R</td>
+* <td>The object addressed by the pointer parameter is not modified and so the pointer could be of
+* type 'pointer to const'.</td>
+* <td>The callback function for system power management (SysPm) must be of generic callback type that
+* contains non-const pointer parameter.</td>
+* </tr>
+* <tr>
+* <td>18.4</td>
+* <td>R</td>
+* <td>Unions shall not be used.</td>
+* <td>The clock path in \ref Cy_SysClk_PeriphGetFrequency() uses either FLL or PLL.</td>
+* </tr>
+* <tr>
+* <td>19.4</td>
+* <td>R</td>
+* <td>Macros shall only expand to a limited set of constructs.</td>
+* <td>The macro CY_SYSCLK_CLR_SET uses a concatenate operation,
+* so one of the macro parameters cannot be enclosed in parentheses.</td>
+* </tr>
+* </table>
+*
+*
+* \section group_sysclk_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10.1</td>
+* <td>Renamed Power Management section to Low Power Callback section</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td rowspan="5">1.10</td>
+* <td>Updated FLL parameter calculation</td>
+* <td>Support low frequency sources</td>
+* </tr>
+* <tr>
+* <td>Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions</td>
+* <td>Support PILO manual trims</td>
+* </tr>
+* <tr>
+* <td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1</td>
+* <td>Feature is not supported in SRSS v1</td>
+* </tr>
+* <tr>
+* <td>Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings</td>
+* <td>The function should return when the lock is established or a timeout has occurred</td>
+* </tr>
+* <tr>
+* <td>General documentation updates</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sysclk_macros Macros
+* \{
+* \}
+* \defgroup group_sysclk_enums General Enumerated Types
+* \{
+* \defgroup group_sysclk_returns Function return values
+* \}
+* \defgroup group_sysclk_eco External Crystal Oscillator (ECO)
+* \{
+* The External Crystal Oscillator (ECO) is a clock source that consists
+* of an oscillator circuit that drives an external crystal through its
+* dedicated ECO pins. The ECO is a source clock that can be used to
+* source one or more clock paths (Refer to \ref group_sysclk_path_src).
+* These clock paths can then source the processors and peripherals in
+* the device.
+*
+* The ECO relies on the presence of an external crystal. The pins
+* connected to this crystal must be configured to operate in analog
+* drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO).
+*
+* \defgroup group_sysclk_eco_funcs Functions
+* \}
+* \defgroup group_sysclk_path_src Clock Path Source
+* \{
+* Clock paths are a series of multiplexers that allow a source clock
+* to drive multiple clocking resources down the chain. These paths are
+* used for active domain clocks that are not operational during chip
+* deep-sleep, hibernate and off modes. Illustrated below is a diagram
+* of the clock paths for the PSoC 63 series, showing the first three
+* clock paths. The source clocks for these paths are highlighted in
+* the red box.
+*
+* - IMO: 8 MHz Internal Main Oscillator (Default)
+* - EXTCLK: External clock (signal brought in through dedicated pins)
+* - ECO: External Crystal Oscillator (requires external crystal on dedicated pins)
+* - ALTHF: Select on-chip signals (e.g. BLE ECO)
+* - Digital Signal (DSI): Digital signal from a UDB source
+*
+* Some clock paths such as path 0 and path 1 have additional resources
+* that can be utilized to provide a higher frequency clock. For example,
+* path 0 source clock can be used as the reference clock for the FLL and
+* path 1 source clock can be used as the reference clock for the PLL.
+*
+* 
+*
+* \note The PDL driver cannot configure a clock path to use Digital Signal
+* Interconnect (DSI) outputs as sources. This must be done through DSI
+* configuration tool such as PSoC Creator.
+*
+* \defgroup group_sysclk_path_src_funcs Functions
+* \defgroup group_sysclk_path_src_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_fll Frequency Locked Loop (FLL)
+* \{
+* The FLL is a clock generation circuit that can be used to produce a
+* higher frequency clock from a reference clock. The output clock exhibits
+* some characteristics of the reference clock such as the accuracy of the
+* source. However other attributes such as the clock phase are not preserved.
+* The FLL is similar in purpose to a (Phase locked loop) PLL but they are
+* not equivalent.
+*
+* - They may have different frequency ranges.
+* - The FLL starts up (locks) faster and consumes less current than the PLL.
+* - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz).
+* - The FLL does not lock phase. The hardware consist of a counter with a
+* current-controlled oscillator (CCO). The counter counts the number of output
+* clock edges in a reference clock period and adjusts the CCO until the
+* expected ratio is achieved (locked). After initial lock, the CCO is
+* adjusted dynamically to keep the ratio within tolerance. The lock tolerance
+* is user-adjustable.
+* 
+*
+* The SysClk driver supports two models for configuring the FLL. The first
+* model is to call the Cy_SysClk_FllConfigure() function, which calculates the
+* necessary parameters for the FLL at run-time. This may be necessary for dynamic
+* run-time changes to the FLL. However this method is slow as it needs to perform
+* the calculation before configuring the FLL. The other model is to call
+* Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values.
+* This method is faster but requires prior knowledge of the necessary parameters.
+* Consult the device TRM for the FLL calculation equations.
+*
+* \defgroup group_sysclk_fll_funcs Functions
+* \defgroup group_sysclk_fll_structs Data Structures
+* \defgroup group_sysclk_fll_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_pll Phase Locked Loop (PLL)
+* \{
+* The PLL is a clock generation circuit that can be used to produce a
+* higher frequency clock from a reference clock. The output clock exhibits
+* characteristics of the reference clock such as the accuracy of the source
+* and its phase. The PLL is similar in purpose to a (Frequency locked loop) FLL
+* but they are not equivalent.
+*
+* - They may have different frequency ranges.
+* - The PLL starts up more slowly and consumes more current than the FLL.
+* - The PLL requires a higher frequency source clock than PLL.
+* 
+*
+* The SysClk driver supports two models for configuring the PLL. The first
+* model is to call the Cy_SysClk_PllConfigure() function, which calculates the
+* necessary parameters for the PLL at run-time. This may be necessary for dynamic
+* run-time changes to the PLL. However this method is slow as it needs to perform
+* the calculation before configuring the PLL. The other model is to call
+* Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values.
+* This method is faster but requires prior knowledge of the necessary parameters.
+* Consult the device TRM for the PLL calculation equations.
+*
+* \defgroup group_sysclk_pll_funcs Functions
+* \defgroup group_sysclk_pll_structs Data Structures
+* \}
+* \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO)
+* \{
+* The ILO operates with no external components and outputs a stable clock at
+* 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is
+* available in all power modes and can be used as a source for the Backup domain clock.
+* 
+*
+* To ensure the ILO remains active in Hibernate mode, and across power-on-reset
+* (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn().
+*
+* Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using
+* a higher precision clock source. Use the \ref group_sysclk_calclk API to measure
+* the current ILO frequency before trimming.
+*
+* \note The ILO is always the source clock for the \ref group_wdt. Therefore:
+* - The WDT must be unlocked when making an ILO function call in the PDL
+* - It is recommended to always have the ILO enabled
+*
+* \defgroup group_sysclk_ilo_funcs Functions
+* \}
+* \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO)
+* \{
+* PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO".
+* When periodically calibrated using a high-accuracy clock such as the
+* \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency.
+* The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes.
+* It is not available in Hibernate mode.
+*
+* The PILO can be used as a source for the \ref group_sysclk_clk_lf. However,
+* because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode
+* when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or
+* \ref group_sysclk_wco "WCO" should be used when hibernate operation is required.
+*
+* 
+*
+* Periodic calibration to a high-accuracy clock (such as ECO) is required to
+* maintain accuracy. The application should use the functions described in the
+* \ref group_sysclk_calclk API to measure the current PILO frequency before trimming.
+*
+* \defgroup group_sysclk_pilo_funcs Functions
+* \}
+* \defgroup group_sysclk_calclk Clock Measurement
+* \{
+* These functions measure the frequency of a specified clock relative to a
+* reference clock. They are typically called in the following order:
+*
+* 1. Specify the measured clock, the count, and the reference clock
+* 2. Start the counters
+* 3. Wait for the measurement counter to finish counting
+* 4. Retrieve the measured frequency
+*
+* \note These functions may also be used as part of a clock trimming
+* process. Refer to the \ref group_sysclk_trim "Clock Trim" API.
+*
+* \defgroup group_sysclk_calclk_funcs Functions
+* \defgroup group_sysclk_calclk_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_trim Clock Trim (ILO, PILO)
+* \{
+* These functions perform a single trim operation on the ILO or PILO. Each
+* function's parameter is the actual frequency of the clock. To measure the
+* frequency, use the functions described in the \ref group_sysclk_calclk API.
+*
+* To trim the clock as close as possible to the target frequency, multiple
+* calls to the trim function may be needed. A typical usage example is to:
+* 1. Call the clock measurement functions to get the actual frequency of the clock
+* 2. Call the trim function, passing in the measured frequency
+* 3. Repeat the above until the trim function reports that the clock is trimmed to within limits.
+*
+* \defgroup group_sysclk_trim_funcs Functions
+* \}
+* \defgroup group_sysclk_pm Low Power Callback
+* \{
+* Entering and exiting low power modes require compatible clock configurations
+* to be set before entering low power and restored upon wake-up and exit. The
+* SysClk driver provides a Cy_SysClk_DeepSleepCallback() function to support
+* deep-sleep mode entry.
+*
+* This function can be called either by itself before initiating low-power mode
+* entry or it can be used in conjunction with the SysPm driver as a registered
+* callback. To do so, register this function as a callback before calling
+* Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type,
+* and call Cy_SysPm_RegisterCallback().
+*
+* \note If the FLL or PLL source is the ECO, this function must be called.
+*
+* \defgroup group_sysclk_pm_funcs Functions
+* \}
+* \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO)
+* \{
+* The WCO is a highly accurate 32.768 kHz clock source capable of operating
+* in all power modes (excluding the Off mode). It is the primary clock source for
+* the backup domain clock, which is used by the real-time clock (RTC). The
+* WCO can also be used as a source for the low-frequency clock to support other
+* low power mode peripherals.
+*
+* 
+*
+* The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN,
+* SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the
+* HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where
+* an external 32.768 kHz square wave is brought in directly through the
+* SRSS_WCO_OUT_PIN pin.
+*
+* Some devices support a built-in clock supervisor (CSV) in the WCO. The clock
+* supervisor detects if the WCO has been lost; that is, the WCO is no longer
+* producing clock pulses. The CSV does this by checking to ensure there is at
+* least one WCO clock pulse within a certain time window. The ILO or PILO can be
+* the supervising clock. Firmware can configure the CSV to trigger a fault,
+* a reset, or both after specified cycles of the supervising clock.
+*
+* \defgroup group_sysclk_wco_funcs Functions
+* \defgroup group_sysclk_wco_structs Data Structures
+* \defgroup group_sysclk_wco_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_hf High-Frequency Clocks
+* \{
+* Multiple high frequency clocks (CLK_HF) are available in the device. For example,
+* PSoC 63 series has five high-frequency root clocks. Each CLK_HF has a particular
+* connection and chip-specific destination on the device.
+*
+* |Name |Description |
+* |:--------|:-------------------------------------------------------|
+* |CLK_HF[0]| Root clock for CPUs, PERI, and AHB infrastructure |
+* |CLK_HF[1]| Root clock for the PDM/PCM and I2S audio subsystem |
+* |CLK_HF[2]| Root clock for the Serial Memory Interface subsystem |
+* |CLK_HF[3]| Root clock for USB communications |
+* |CLK_HF[4]| Clock output on clk_ext pin (when used as an output) |
+*
+* 
+*
+* High frequency clocks are sourced by path clocks, which should be configured
+* first. An exception to this rule is CLK_HF[0], which cannot be disabled.
+* This divided clock drives the core processors and the peripherals in the system.
+* In order to update its clock source, CLK_HF[0] source must be selected without
+* disabling the clock.
+*
+* 
+*
+* Some devices support a clock supervisor (CSV) for each root clock. These
+* can detect frequency loss, or monitor that the clock frequency stays within
+* a specified range. The possible supervising clocks are IMO, ECO, or ALTHF.
+* Loss detection and frequency monitoring can be enabled or disabled independently.
+* Each has its own programmable action that occurs on detection of an error.
+*
+* \defgroup group_sysclk_clk_hf_funcs Functions
+* \defgroup group_sysclk_clk_hf_structs Data Structures
+* \defgroup group_sysclk_clk_hf_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_fast Fast Clock
+* \{
+* The fast clock drives the "fast" processor (e.g. Cortex-M4 processor in PSoC 6).
+* This clock is sourced by CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks").
+* A divider value of 1~256 can be used to further divide the CLK_HF[0] to a
+* desired clock speed for the processor.
+*
+* 
+*
+* \defgroup group_sysclk_clk_fast_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_peri Peripheral Clock
+* \{
+* The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks").
+* It is the source clock for the \ref group_sysclk_clk_slow, and most active domain
+* peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256
+* can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals.
+*
+* 
+*
+* \defgroup group_sysclk_clk_peri_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers
+* \{
+* There are multiple peripheral clock dividers that, in effect, create
+* multiple separate peripheral clocks. The available dividers vary per device
+* series. As an example, for the PSoC 63 series there are 29 dividers:
+*
+* - eight 8-bit dividers
+* - sixteen 16-bit dividers
+* - four fractional 16.5-bit dividers (16 integer bits, 5 fractional bits)
+* - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits)
+*
+* The five fractional bits supports further precision in 1/32nd increments. For
+* example, a divider with an integer value of 3 and a fractional value of
+* 4 (4/32) results in a divider of 3.125. Fractional dividers are useful when
+* a high-precision clock is required, for example, for a UART/SPI serial
+* interface.
+*
+* 
+*
+* Each peripheral can connect to any one of the programmable dividers. A
+* particular peripheral clock divider can drive multiple peripherals.
+*
+* The SysClk driver also supports phase aligning two peripheral clock dividers using
+* Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer
+* and fractional dividers. The divider to which a second divider is aligned
+* must already be enabled.
+*
+* \defgroup group_sysclk_clk_peripheral_funcs Functions
+* \defgroup group_sysclk_clk_peripheral_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_slow Slow Clock
+* \{
+* The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6).
+* This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is
+* a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider
+* value of 1~256 can be used to further divide the Peri clock to a desired clock speed
+* for the processor.
+*
+* 
+*
+* \defgroup group_sysclk_clk_slow_funcs Functions
+* \}
+* \defgroup group_sysclk_clk_lf Low-Frequency Clock
+* \{
+* The low-frequency clock is the source clock for the \ref group_mcwdt
+* and can be the source clock for \ref group_sysclk_clk_bak, which drives the
+* \ref group_rtc.
+*
+* The low-frequency clock has three possible source clocks:
+* \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and
+* \ref group_sysclk_wco "WCO".
+*
+* 
+*
+* \defgroup group_sysclk_clk_lf_funcs Functions
+* \defgroup group_sysclk_clk_lf_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_timer Timer Clock
+* \{
+* The timer clock can be a source for the alternative clock driving
+* the \ref group_arm_system_timer. It can also be used as a reference clock
+* for a counter in the \ref group_energy_profiler "Energy Profiler".
+*
+* The timer clock is a divided clock of either the IMO or CLK_HF[0]
+* (\ref group_sysclk_clk_hf "HF Clocks").
+*
+* \defgroup group_sysclk_clk_timer_funcs Functions
+* \defgroup group_sysclk_clk_timer_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_pump Pump Clock
+* \{
+* The pump clock is a clock source used to provide analog precision in low voltage
+* applications. Depedning on the usage scenario, it may be required to drive the
+* internal voltage pump for the Continuous Time Block mini (CTBm) in the analog
+* subsystem. The pump clock is a divided clock of one of the clock paths
+* (\ref group_sysclk_path_src).
+*
+* \defgroup group_sysclk_clk_pump_funcs Functions
+* \defgroup group_sysclk_clk_pump_enums Enumerated Types
+* \}
+* \defgroup group_sysclk_clk_bak Backup Domain Clock
+* \{
+* The backup domain clock drives the \ref group_rtc.
+* This clock has two possible source clocks: \ref group_sysclk_wco "WCO"
+* or the \ref group_sysclk_clk_lf. In turn the low frequency clock is sourced by
+* \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", or
+* \ref group_sysclk_wco "WCO". Typically the ILO is not suitable as an RTC source,
+* because of its low accuracy. However the ILO does operate in hibernate mode and
+* may be used as an alterative to the WCO with a tradeoff in precision.
+*
+* \defgroup group_sysclk_clk_bak_funcs Functions
+* \defgroup group_sysclk_clk_bak_enums Enumerated Types
+* \}
+*/
+
+#if !defined(__CY_SYSCLK_H__)
+#define __CY_SYSCLK_H__
+
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+#include "syspm/cy_syspm.h"
+#include <stdbool.h>
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+* \addtogroup group_sysclk_macros
+* \{
+*/
+/** Driver major version */
+#define CY_SYSCLK_DRV_VERSION_MAJOR 1
+/** Driver minor version */
+#define CY_SYSCLK_DRV_VERSION_MINOR 10
+/** Sysclk driver identifier */
+#define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U)
+
+/** \} group_sysclk_macros */
+
+/**
+* \addtogroup group_sysclk_returns
+* \{
+*/
+/** Defines general-purpose function return values. */
+typedef enum
+{
+ CY_SYSCLK_SUCCESS = 0u, /**< Command completed with no errors */
+ CY_SYSCLK_BAD_PARAM = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 1u), /**< Invalid function input parameter */
+ CY_SYSCLK_TIMEOUT = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 2u), /**< Timeout occurred */
+ CY_SYSCLK_INVALID_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 3u) /**< Clock is in an invalid state */
+} cy_en_sysclk_status_t;
+/** \} group_sysclk_returns */
+
+/** \cond INTERNAL */
+/* Generates shorter code for setting register bitfields */
+#define CY_SYSCLK_CLR_SET(reg, field, value) (reg) = _CLR_SET_FLD32U((reg), field, (value))
+/* Calculate a / b with rounding to the nearest integer. a and b must have the same sign. */
+#define CY_SYSCLK_DIV_ROUND(a, b) (((a) + ((b) / 2u)) / (b))
+/* Calculate a / b with rounding up if remainder != 0. a and b must both be positive. */
+#define CY_SYSCLK_DIV_ROUNDUP(a, b) ((((a) - 1u) / (b)) + 1u)
+/** \endcond */
+
+
+/* ========================================================================== */
+/* =========================== ECO SECTION ============================ */
+/* ========================================================================== */
+
+/**
+* \addtogroup group_sysclk_macros
+* \{
+*/
+
+/**
+* \defgroup group_sysclk_ecostatus ECO status
+* \{
+* Constants used for expressing ECO status.
+*/
+#define CY_SYSCLK_ECOSTAT_AMPLITUDE 0UL /**< \brief ECO does not have sufficient amplitude */
+#define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */
+#define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */
+/** \} */
+
+/** \} group_sysclk_macros */
+
+/**
+* \addtogroup group_sysclk_eco_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel);
+cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus);
+__STATIC_INLINE void Cy_SysClk_EcoDisable(void);
+__STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoDisable
+****************************************************************************//**
+*
+* Disables the external crystal oscillator (ECO). This function should not be
+* called if the ECO is sourcing clkHf[0].
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_EcoDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_EcoDisable(void)
+{
+ SRSS->CLK_ECO_CONFIG &= ~_VAL2FLD(SRSS_CLK_ECO_CONFIG_ECO_EN, 1u); /* 0 = disable */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_EcoGetStatus
+****************************************************************************//**
+*
+* Reports the current status of the external crystal oscillator (ECO).
+*
+* \return
+* CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude<br>
+* CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications<br>
+* CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_EcoGetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void)
+{
+ uint32_t retval = (SRSS->CLK_ECO_STATUS & 3ul); /* bit 0 = ECO_OK, bit 1 = ECO_READY */
+ /* if ECO is not ready, just report the ECO_OK bit. Otherwise report 2 = ECO ready */
+ return (((retval & 2ul) == 0) ? retval : 2ul);
+}
+/** \} group_sysclk_eco_funcs */
+
+
+/* ========================================================================== */
+/* ==================== INPUT MULTIPLEXER SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_path_src_enums
+* \{
+*/
+/**
+* Input multiplexer clock sources
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKPATH_IN_IMO = 0u, /**< Select the IMO as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_EXT = 1u, /**< Select the EXT as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_ECO = 2u, /**< Select the ECO as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_ALTHF = 3u, /**< Select the ALTHF as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_DSIMUX = 4u, /**< Select the DSI MUX output as the output of the path mux */
+ CY_SYSCLK_CLKPATH_IN_DSI = 0x100u, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_ILO = 0x110u, /**< Select the ILO (16) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_WCO = 0x111u, /**< Select the WCO (17) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112u, /**< Select the ALTLF (18) as the output of the DSI mux and path mux */
+ CY_SYSCLK_CLKPATH_IN_PILO = 0x113u /**< Select the PILO (19) as the output of the DSI mux and path mux */
+} cy_en_clkpath_in_sources_t;
+/** \} group_sysclk_path_src_enums */
+
+/**
+* \addtogroup group_sysclk_path_src_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source);
+cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath);
+/** \} group_sysclk_path_src_funcs */
+
+
+/* ========================================================================== */
+/* =========================== FLL SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_fll_enums
+* \{
+*/
+/** FLL and PLL output mode.
+* See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL.
+*/
+typedef enum
+{
+ CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0u, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked. */
+ CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1u, /**< Same as AUTO */
+ CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2u, /**< Output FLL/PLL input source regardless of lock status. */
+ CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3u /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable. */
+} cy_en_fll_pll_output_mode_t;
+
+/** FLL current-controlled oscillator (CCO) frequency ranges.
+* See register CLK_FLL_CONFIG4, bits CCO_RANGE.
+*/
+typedef enum
+{
+ CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz. */
+ CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz. */
+ CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz. */
+ CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz. */
+ CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz. */
+} cy_en_fll_cco_ranges_t;
+/** \} group_sysclk_fll_enums */
+
+/**
+* \addtogroup group_sysclk_fll_structs
+* \{
+*/
+/** Structure containing information for manual configuration of FLL.
+*/
+typedef struct
+{
+ uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */
+ uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */
+ cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */
+ bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */
+ uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */
+ uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */
+ uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */
+ uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */
+ uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */
+} cy_stc_fll_manual_config_t;
+/** \} group_sysclk_fll_structs */
+
+/**
+* \addtogroup group_sysclk_fll_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode);
+cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config);
+void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_FllLocked(void);
+#if (CY_IP_MXS40SRSS_VERSION != 1) || defined(CY_DOXYGEN)
+__STATIC_INLINE bool Cy_SysClk_FllLostLock(void);
+#endif
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllLocked
+****************************************************************************//**
+*
+* Reports whether or not the FLL is locked.
+*
+* \return
+* false = not locked<br>
+* true = locked
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllLocked
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_FllLocked(void)
+{
+ return (bool)(_FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
+}
+
+#if (CY_IP_MXS40SRSS_VERSION != 1) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllLostLock
+****************************************************************************//**
+*
+* Reports whether or not the FLL lost its lock since the last time this function
+* was called. Clears the lost lock indicator.
+*
+* \return
+* false = did not lose lock<br>
+* true = lost lock
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllLostLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_FllLostLock(void)
+{
+ uint32_t retval = _FLD2VAL(SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED, SRSS->CLK_FLL_STATUS);
+ /* write a 1 to clear the unlock occurred bit */
+ SRSS->CLK_FLL_STATUS = _VAL2FLD(SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED, 1u);
+ return ((bool)retval);
+}
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_FllDisable
+****************************************************************************//**
+*
+* Disables the FLL and the CCO.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_FllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void)
+{
+ SRSS->CLK_FLL_CONFIG &= ~_VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, 1u); /* 0 = disable */
+ SRSS->CLK_FLL_CONFIG4 &= ~_VAL2FLD(SRSS_CLK_FLL_CONFIG4_CCO_ENABLE, 1u); /* 0 = disable */
+ return CY_SYSCLK_SUCCESS;
+}
+/** \} group_sysclk_fll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PLL SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pll_structs
+* \{
+*/
+/** Structure containing information for configuration of a PLL.
+*/
+typedef struct
+{
+ uint32_t inputFreq; /**< frequency of PLL source, in Hz */
+ uint32_t outputFreq; /**< frequency of PLL output, in Hz */
+ bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */
+} cy_stc_pll_config_t;
+
+/** Structure containing information for manual configuration of a PLL.
+*/
+typedef struct
+{
+ uint8_t feedbackDiv; /**< CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */
+ uint8_t referenceDiv; /**< CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */
+ uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */
+ bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */
+ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */
+} cy_stc_pll_manual_config_t;
+/** \} group_sysclk_pll_structs */
+
+/**
+* \addtogroup group_sysclk_pll_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config);
+cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath);
+__STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllLocked
+****************************************************************************//**
+*
+* Reports whether or not the selected PLL is locked.
+*
+* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid.
+*
+* \return
+* false = not locked<br>
+* true = locked
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllLocked
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath)
+{
+ CY_ASSERT_L1((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL));
+ return (bool)(_FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[clkPath - 1ul]));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllLostLock
+****************************************************************************//**
+*
+* Reports whether or not the selected PLL lost its lock since the last time this
+* function was called. Clears the lost lock indicator.
+*
+* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid.
+*
+* \return
+* false = did not lose lock<br>
+* true = lost lock
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllLostLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath)
+{
+ uint32_t retval = 0ul;
+
+ CY_ASSERT_L1((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL));
+
+ retval = _FLD2VAL(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, SRSS->CLK_PLL_STATUS[clkPath - 1ul]);
+ /* write a 1 to clear the unlock occurred bit */
+ SRSS->CLK_PLL_STATUS[clkPath - 1ul] = _VAL2FLD(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, 1u);
+ return ((bool)retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PllDisable
+****************************************************************************//**
+*
+* Disables the selected PLL.
+*
+* \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - PLL successfully disabled<br>
+* CY_SYSCLK_BAD_PARAM - invalid clock path number
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PllDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL))
+ {
+ SRSS->CLK_PLL_CONFIG[clkPath - 1ul] &= ~_VAL2FLD(SRSS_CLK_PLL_CONFIG_ENABLE, 1u); /* 0 = disable */
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+/** \} group_sysclk_pll_funcs */
+
+
+/* ========================================================================== */
+/* =========================== ILO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_ilo_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_IloEnable(void);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void);
+__STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloEnable
+****************************************************************************//**
+*
+* Enables the ILO.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_IloEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_IloEnable(void)
+{
+ SRSS->CLK_ILO_CONFIG |= _VAL2FLD(SRSS_CLK_ILO_CONFIG_ENABLE, 1u); /* 1 = enable */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloDisable
+****************************************************************************//**
+*
+* Disables the ILO. ILO can't be disabled if WDT is enabled.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - ILO successfully disabled<br>
+* CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled.
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+* Do not call this function if the WDT is enabled, because the WDT is clocked by
+* the ILO.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_IloDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_INVALID_STATE;
+ if (_FLD2VAL(SRSS_WDT_CTL_WDT_EN, SRSS->WDT_CTL) == 0ul) /* 0 = disabled */
+ {
+ SRSS->CLK_ILO_CONFIG &= ~_VAL2FLD(SRSS_CLK_ILO_CONFIG_ENABLE, 1u); /* 0 = disable */
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return retval;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_IloHibernateOn
+****************************************************************************//**
+*
+* Controls whether the ILO stays on during a hibernate, or through an XRES or
+* brown-out detect (BOD) event.
+*
+* \param on
+* true = ILO stays on during hibernate or across XRES/BOD.<br>
+* false = ILO turns off for hibernate or XRES/BOD.
+*
+* \note Writes to the register/bit are ignored if the watchdog (WDT) is locked.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_IloHibernateOn
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on)
+{
+ CY_SYSCLK_CLR_SET(SRSS->CLK_ILO_CONFIG, SRSS_CLK_ILO_CONFIG_ILO_BACKUP, (uint32_t)on);
+}
+/** \} group_sysclk_ilo_funcs */
+
+
+/* ========================================================================== */
+/* =========================== PILO SECTION =========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pilo_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_PiloEnable(void);
+__STATIC_INLINE void Cy_SysClk_PiloDisable(void);
+__STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal);
+__STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloEnable
+****************************************************************************//**
+*
+* Enables the PILO.
+*
+* \note This function blocks for 1 millisecond between enabling the PILO and
+* releasing the PILO reset.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PiloEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloEnable(void)
+{
+ SRSS->CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1u); /* 1 = enable */
+ Cy_SysLib_Delay(1/*msec*/);
+ /* release the reset and enable clock output */
+ SRSS->CLK_PILO_CONFIG |= (_VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_RESET_N, 1u) |
+ _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, 1u));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloDisable
+****************************************************************************//**
+*
+* Disables the PILO.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PiloDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloDisable(void)
+{
+ /* Clear PILO_EN, PILO_RESET_N, and PILO_CLK_EN bitfields. This disables the
+ PILO and holds the PILO in a reset state. */
+ SRSS->CLK_PILO_CONFIG &= ~(_VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1u) |
+ _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_RESET_N, 1u) |
+ _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, 1u));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloSetTrim
+****************************************************************************//**
+*
+* Sets the PILO trim bits, which adjusts the PILO frequency. This is typically
+* done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters().
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PiloSetTrim
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal)
+{
+ CY_SYSCLK_CLR_SET(SRSS->CLK_PILO_CONFIG, SRSS_CLK_PILO_CONFIG_PILO_FFREQ, trimVal);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PiloGetTrim
+****************************************************************************//**
+*
+* Reports the current PILO trim bits value.
+*
+* \funcusage
+* Refer to the Cy_SysClk_PiloSetTrim() function usage.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void)
+{
+ return (_FLD2VAL(SRSS_CLK_PILO_CONFIG_PILO_FFREQ, SRSS->CLK_PILO_CONFIG));
+}
+/** \} group_sysclk_pilo_funcs */
+
+
+/* ========================================================================== */
+/* ==================== CLOCK MEASUREMENT SECTION ===================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_calclk_enums
+* \{
+*/
+/** Defines all possible clock sources. */
+typedef enum
+{
+ CY_SYSCLK_MEAS_CLK_ILO = 1u,
+ CY_SYSCLK_MEAS_CLK_WCO = 2u,
+ CY_SYSCLK_MEAS_CLK_BAK = 3u,
+ CY_SYSCLK_MEAS_CLK_ALTLF = 4u,
+ CY_SYSCLK_MEAS_CLK_LFCLK = 5u,
+ CY_SYSCLK_MEAS_CLK_IMO = 6u,
+ CY_SYSCLK_MEAS_CLK_PILO = 8u,
+ CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100u,
+ CY_SYSCLK_MEAS_CLK_ECO = 0x101u,
+ CY_SYSCLK_MEAS_CLK_EXT = 0x102u,
+ CY_SYSCLK_MEAS_CLK_ALTHF = 0x103u,
+ CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500u,
+ CY_SYSCLK_MEAS_CLK_PATH0 = 0x500u,
+ CY_SYSCLK_MEAS_CLK_PATH1 = 0x501u,
+ CY_SYSCLK_MEAS_CLK_PATH2 = 0x502u,
+ CY_SYSCLK_MEAS_CLK_PATH3 = 0x503u,
+ CY_SYSCLK_MEAS_CLK_PATH4 = 0x504u,
+ CY_SYSCLK_MEAS_CLK_PATH5 = 0x505u,
+ CY_SYSCLK_MEAS_CLK_PATH6 = 0x506u,
+ CY_SYSCLK_MEAS_CLK_PATH7 = 0x507u,
+ CY_SYSCLK_MEAS_CLK_PATH8 = 0x508u,
+ CY_SYSCLK_MEAS_CLK_PATH9 = 0x509u,
+ CY_SYSCLK_MEAS_CLK_PATH10 = 0x50Au,
+ CY_SYSCLK_MEAS_CLK_PATH11 = 0x50Bu,
+ CY_SYSCLK_MEAS_CLK_PATH12 = 0x50Cu,
+ CY_SYSCLK_MEAS_CLK_PATH13 = 0x50Du,
+ CY_SYSCLK_MEAS_CLK_PATH14 = 0x50Eu,
+ CY_SYSCLK_MEAS_CLK_PATH15 = 0x50Fu,
+ CY_SYSCLK_MEAS_CLK_CLKHFS = 0x600u,
+ CY_SYSCLK_MEAS_CLK_CLKHF0 = 0x600u,
+ CY_SYSCLK_MEAS_CLK_CLKHF1 = 0x601u,
+ CY_SYSCLK_MEAS_CLK_CLKHF2 = 0x602u,
+ CY_SYSCLK_MEAS_CLK_CLKHF3 = 0x603u,
+ CY_SYSCLK_MEAS_CLK_CLKHF4 = 0x604u,
+ CY_SYSCLK_MEAS_CLK_CLKHF5 = 0x605u,
+ CY_SYSCLK_MEAS_CLK_CLKHF6 = 0x606u,
+ CY_SYSCLK_MEAS_CLK_CLKHF7 = 0x607u,
+ CY_SYSCLK_MEAS_CLK_CLKHF8 = 0x608u,
+ CY_SYSCLK_MEAS_CLK_CLKHF9 = 0x609u,
+ CY_SYSCLK_MEAS_CLK_CLKHF10 = 0x60Au,
+ CY_SYSCLK_MEAS_CLK_CLKHF11 = 0x60Bu,
+ CY_SYSCLK_MEAS_CLK_CLKHF12 = 0x60Cu,
+ CY_SYSCLK_MEAS_CLK_CLKHF13 = 0x60Du,
+ CY_SYSCLK_MEAS_CLK_CLKHF14 = 0x60Eu,
+ CY_SYSCLK_MEAS_CLK_CLKHF15 = 0x60Fu,
+ CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610u
+} cy_en_meas_clks_t;
+/** \} group_sysclk_calclk_enums */
+
+/**
+* \addtogroup group_sysclk_calclk_funcs
+* \{
+*/
+cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2);
+__STATIC_INLINE bool Cy_SysClk_ClkMeasurementCountersDone(void);
+uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkMeasurementCountersDone
+****************************************************************************//**
+*
+* Checks if clock measurement counting is done, that is, counter1 has counted down
+* to zero. Call \ref Cy_SysClk_StartClkMeasurementCounters() before calling this function.
+*
+* \return Status of calibration counters:<br>
+* true = done<br>
+* false = not done
+*
+* \funcusage
+* Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_ClkMeasurementCountersDone(void)
+{
+ return (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1)); /* 1 = done */
+}
+/** \} group_sysclk_calclk_funcs */
+
+
+/* ========================================================================== */
+/* ========================== TRIM SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_trim_funcs
+* \{
+*/
+int32_t Cy_SysClk_IloTrim(uint32_t iloFreq);
+int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq);
+/** \} group_sysclk_trim_funcs */
+
+
+/* ========================================================================== */
+/* ====================== POWER MANAGEMENT SECTION ==================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_pm_funcs
+* \{
+*/
+cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams);
+/** \} group_sysclk_pm_funcs */
+
+
+/* ========================================================================== */
+/* =========================== WCO SECTION ============================ */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_wco_enums
+* \{
+*/
+/** WCO bypass modes */
+typedef enum
+{
+ CY_SYSCLK_WCO_NOT_BYPASSED = 0u, /**< WCO is not bypassed crystal is used */
+ CY_SYSCLK_WCO_BYPASSED = 1u /**< WCO is bypassed external clock must be supplied on XTAL pin */
+} cy_en_wco_bypass_modes_t;
+
+/** WCO CSV supervisor clock selections */
+typedef enum
+{
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, /**< WCO CSV supervisor clock source is the ILO */
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, /**< WCO CSV supervisor clock source is the alternate low-frequency clock (ALTLF) */
+ CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO /**< WCO CSV supervisor clock source is the PILO */
+} cy_en_wco_csv_supervisor_clock_t;
+
+/**
+* Clock supervisor clock loss window. There must be one clock of the supervised
+* clock within this many clocks of the supervising clock.
+* See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW.
+*/
+typedef enum
+{
+ CY_SYSCLK_CSV_LOSS_4_CYCLES = 0u, /**< 1 clock must be seen within 4 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_8_CYCLES = 1u, /**< 1 clock must be seen within 8 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_16_CYCLES = 2u, /**< 1 clock must be seen within 16 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_32_CYCLES = 3u, /**< 1 clock must be seen within 32 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_64_CYCLES = 4u, /**< 1 clock must be seen within 64 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_128_CYCLES = 5u, /**< 1 clock must be seen within 128 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_256_CYCLES = 6u, /**< 1 clock must be seen within 256 cycles of the supervising clock. */
+ CY_SYSCLK_CSV_LOSS_512_CYCLES = 7u /**< 1 clock must be seen within 512 cycles of the supervising clock. */
+} cy_en_csv_loss_window_t;
+
+/**
+* Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION].
+*/
+typedef enum
+{
+ CY_SYSCLK_CSV_ERROR_IGNORE = 0u, /**< Ignore the error reported by the clock supervisor. */
+ CY_SYSCLK_CSV_ERROR_FAULT = 1u, /**< Trigger a fault when an error is reported by the clock supervisor. */
+ CY_SYSCLK_CSV_ERROR_RESET = 2u, /**< Trigger a reset when an error is reported by the clock supervisor. */
+ CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3u /**< Trigger a fault then reset when an error is reported by the supervisor. */
+} cy_en_csv_error_actions_t;
+/** \} group_sysclk_wco_enums */
+
+/**
+* \addtogroup group_sysclk_wco_structs
+* \{
+*/
+/**
+* This structure is used to configure the clock supervisor for the WCO.
+*/
+typedef struct
+{
+ cy_en_wco_csv_supervisor_clock_t supervisorClock; /**< supervisor clock selection */
+ bool enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored. */
+ cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */
+ cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */
+} cy_stc_wco_csv_config_t;
+/** \} group_sysclk_wco_structs */
+
+/**
+* \addtogroup group_sysclk_wco_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus);
+__STATIC_INLINE bool Cy_SysClk_WcoOkay(void);
+__STATIC_INLINE void Cy_SysClk_WcoDisable(void);
+__STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass);
+#if (SRSS_WCOCSV_PRESENT != 0) || defined(CY_DOXYGEN)
+ void Cy_SysClk_WcoConfigureCsv(const cy_stc_wco_csv_config_t *config);
+#endif /* (SRSS_WCOCSV_PRESENT != 0) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoEnable
+****************************************************************************//**
+*
+* Enables the WCO.
+*
+* \param timeoutus amount of time in microseconds to wait for the WCO to be ready.
+* If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0,
+* and manually check if WCO is okay using \ref Cy_SysClk_WcoOkay.
+*
+* \return Error / status code:<br>
+* CY_SYSCLK_SUCCESS - WCO successfully enabled<br>
+* CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_WcoEnable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus)
+{
+ cy_en_sysclk_status_t rtnval = CY_SYSCLK_TIMEOUT;
+
+ /* first set the WCO enable bit */
+ BACKUP->CTL |= _VAL2FLD(BACKUP_CTL_WCO_EN, 1u); /* 1 = enable */
+
+ /* now do the timeout wait for STATUS, bit WCO_OK */
+ for (; (Cy_SysClk_WcoOkay() == false) && (timeoutus != 0ul); timeoutus--)
+ {
+ Cy_SysLib_DelayUs(1u);
+ }
+ if (timeoutus != 0ul)
+ {
+ rtnval = CY_SYSCLK_SUCCESS;
+ }
+
+ return (rtnval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoOkay
+****************************************************************************//**
+*
+* Reports the status of the WCO_OK bit.
+*
+* \return
+* true = okay<br>
+* false = not okay
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_WcoOkay
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_WcoOkay(void)
+{
+ return (bool)(_FLD2VAL(BACKUP_STATUS_WCO_OK, BACKUP->STATUS));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoDisable
+****************************************************************************//**
+*
+* Disables the WCO.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_WcoDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_WcoDisable(void)
+{
+ BACKUP->CTL &= ~_VAL2FLD(BACKUP_CTL_WCO_EN, 1u); /* 0 = disable */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_WcoBypass
+****************************************************************************//**
+*
+* Sets whether the WCO is bypassed or not. If it is bypassed, then a 32-kHz clock
+* must be provided on the wco_out pin.
+*
+* \param bypass \ref cy_en_wco_bypass_modes_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_WcoBypass
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass)
+{
+ CY_SYSCLK_CLR_SET(BACKUP->CTL, BACKUP_CTL_WCO_BYPASS, bypass);
+}
+/** \} group_sysclk_wco_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clkHf[n] SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_hf_enums
+* \{
+*/
+/**
+* Selects which clkHf input, or root mux, to configure.
+* See CLK_ROOT_SELECT registers, bits ROOT_MUX.
+* Used with functions \ref Cy_SysClk_ClkHfSetSource and \ref Cy_SysClk_ClkHfGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0u, /**< clkHf input is Clock Path 0 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1u, /**< clkHf input is Clock Path 1 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2u, /**< clkHf input is Clock Path 2 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3u, /**< clkHf input is Clock Path 3 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4u, /**< clkHf input is Clock Path 4 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5u, /**< clkHf input is Clock Path 5 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6u, /**< clkHf input is Clock Path 6 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7u, /**< clkHf input is Clock Path 7 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8u, /**< clkHf input is Clock Path 8 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9u, /**< clkHf input is Clock Path 9 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10u, /**< clkHf input is Clock Path 10 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11u, /**< clkHf input is Clock Path 11 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12u, /**< clkHf input is Clock Path 12 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13u, /**< clkHf input is Clock Path 13 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14u, /**< clkHf input is Clock Path 14 */
+ CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15u, /**< clkHf input is Clock Path 15 */
+} cy_en_clkhf_in_sources_t;
+
+
+/**
+* clkHf divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV.
+* Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKHF_NO_DIVIDE = 0u, /**< don't divide clkHf. */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1u, /**< divide clkHf by 2 */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2u, /**< divide clkHf by 4 */
+ CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3u /**< divide clkHf by 8 */
+} cy_en_clkhf_dividers_t;
+
+/**
+* clkHf clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX].
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0u, /**< Supervising clock is the IMO. */
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1u, /**< Supervising clock is the external clock */
+ CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2u /**< Supervising clock is clk_althf */
+} cy_en_clkhf_csv_supervisor_clock_t;
+/** \} group_sysclk_clk_hf_enums */
+
+/**
+* \addtogroup group_sysclk_clk_hf_structs
+* \{SupervisingWindow
+*/
+/**
+* This structure is used to configure the clock supervisor for clkHf.
+*/
+typedef struct
+{
+ cy_en_clkhf_csv_supervisor_clock_t supervisorClock; /**< \ref cy_en_clkhf_csv_supervisor_clock_t */
+ uint16_t supervisingWindow; /**< Number of supervising clock cycles */
+ bool enableFrequencyFaultDetection; /**< 1= enabled, 0= disabled */
+ uint16_t frequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */
+ uint16_t frequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */
+ cy_en_csv_error_actions_t frequencyAction; /**< \ref cy_en_csv_error_actions_t */
+ bool enableLossDetection; /**< 1= enabled, 0= disabled */
+ cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */
+ cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */
+} cy_stc_clkhf_csv_config_t;
+/** \} group_sysclk_clk_hf_structs */
+
+/**
+* \addtogroup group_sysclk_clk_hf_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source);
+__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider);
+__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf);
+#if (SRSS_MASK_HFCSV != 0) || defined(CY_DOXYGEN)
+ cy_en_sysclk_status_t Cy_SysClk_ClkHfConfigureCsv(uint32_t clkHf, const cy_stc_clkhf_csv_config_t *config);
+#endif /* (SRSS_MASK_HFCSV != 0) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfEnable
+****************************************************************************//**
+*
+* Enables the selected clkHf.
+*
+* \param clkHf Selects which clkHf to enable.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfEnable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (clkHf < SRSS_NUM_HFROOT)
+ {
+ SRSS->CLK_ROOT_SELECT[clkHf] |= _VAL2FLD(SRSS_CLK_ROOT_SELECT_ENABLE, 1ul); /* 1 = enable */
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfDisable
+****************************************************************************//**
+*
+* Disables the selected clkHf.
+*
+* \param clkHf Selects which clkHf to enable.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note clkHf[0] cannot be disabled.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfDisable
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((0ul < clkHf) && (clkHf < SRSS_NUM_HFROOT))
+ {
+ SRSS->CLK_ROOT_SELECT[clkHf] &= ~_VAL2FLD(SRSS_CLK_ROOT_SELECT_ENABLE, 1ul); /* 0 = disable */
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfSetSource
+****************************************************************************//**
+*
+* Selects the source of the selected clkHf.
+*
+* \param clkHf selects which clkHf mux to configure.
+*
+* \param source \ref cy_en_clkhf_in_sources_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((clkHf < SRSS_NUM_HFROOT) && (source <= CY_SYSCLK_CLKHF_IN_CLKPATH15))
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_MUX, source);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfGetSource
+****************************************************************************//**
+*
+* Reports the source of the selected clkHf.
+*
+* \param clkHf selects which clkHf to get the source of.
+*
+* \return \ref cy_en_clkhf_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf)
+{
+ CY_ASSERT_L1(clkHf < SRSS_NUM_HFROOT);
+ return (cy_en_clkhf_in_sources_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[clkHf]));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfSetDivider
+****************************************************************************//**
+*
+* Sets the pre-divider for a clkHf.
+*
+* \param clkHf selects which clkHf divider to configure.
+*
+* \param divider \ref cy_en_clkhf_dividers_t
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((clkHf < SRSS_NUM_HFROOT) && (divider <= CY_SYSCLK_CLKHF_DIVIDE_BY_8))
+ {
+ CY_SYSCLK_CLR_SET(SRSS->CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_DIV, divider);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkHfGetDivider
+****************************************************************************//**
+*
+* Reports the pre-divider value for a clkHf.
+*
+* \param clkHf selects which clkHf to check divider of.
+*
+* \return \ref cy_en_clkhf_dividers_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkHfSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf)
+{
+ CY_ASSERT_L1(clkHf < SRSS_NUM_HFROOT);
+ return (cy_en_clkhf_dividers_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[clkHf]));
+}
+/** \} group_sysclk_clk_hf_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_fast SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_fast_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkFastSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the fast clock, which sources the main processor.
+* The source of this divider is clkHf[0].
+*
+* \param divider divider value between 0 and 255.
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkFastSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider)
+{
+ CY_SYSCLK_CLR_SET(CPUSS->CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, (uint32_t)divider);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkFastGetDivider
+****************************************************************************//**
+*
+* Returns the clock divider for the fast clock.
+*
+* \return The divider value for the fast clock.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkFastSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkFastGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_fast_funcs */
+
+
+/* ========================================================================== */
+/* ======================== clk_peri SECTION ========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_peri_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPeriSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the peripheral clock tree. All peripheral clock
+* dividers are sourced from this clock. Also the Cortex M0+ clock divider is
+* sourced from this clock. The source of this divider is clkHf[0]
+*
+* \param divider divider value between 0 and 255
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPeriSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider)
+{
+ CY_SYSCLK_CLR_SET(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, (uint32_t)divider);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPeriGetDivider
+****************************************************************************//**
+*
+* Returns the clock divider of the peripheral (peri) clock.
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPeriSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkPeriGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_peri_funcs */
+
+
+/* ========================================================================== */
+/* ===================== clk_peripherals SECTION ====================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_peripheral_enums
+* \{
+*/
+/** Programmable clock divider types */
+typedef enum
+{
+ CY_SYSCLK_DIV_8_BIT = 0u, /**< Divider Type is an 8 bit divider */
+ CY_SYSCLK_DIV_16_BIT = 1u, /**< Divider Type is a 16 bit divider */
+ CY_SYSCLK_DIV_16_5_BIT = 2u, /**< Divider Type is a 16.5 bit fractional divider */
+ CY_SYSCLK_DIV_24_5_BIT = 3u /**< Divider Type is a 24.5 bit fractional divider */
+} cy_en_divider_types_t;
+/** \} group_sysclk_clk_peripheral_enums */
+
+/**
+* \addtogroup group_sysclk_clk_peripheral_funcs
+* \{
+*/
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue);
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue);
+__STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA);
+__STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphSetDivider
+****************************************************************************//**
+*
+* Sets one of the programmable clock dividers. This is only used for integer
+* dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum the divider number.
+*
+* \param dividerValue divider value
+* Causes integer division of (divider value + 1), or division by 1 to 256
+* (8-bit divider) or 1 to 65536 (16-bit divider).
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType,
+ uint32_t dividerNum, uint32_t dividerValue)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (dividerType == CY_SYSCLK_DIV_8_BIT)
+ {
+ if ((dividerNum < PERI_DIV_8_NR) &&
+ (dividerValue <= (PERI_DIV_8_CTL_INT8_DIV_Msk >> PERI_DIV_8_CTL_INT8_DIV_Pos)))
+ {
+ CY_SYSCLK_CLR_SET(PERI->DIV_8_CTL[dividerNum], PERI_DIV_8_CTL_INT8_DIV, dividerValue);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else if (dividerType == CY_SYSCLK_DIV_16_BIT)
+ {
+ if ((dividerNum < PERI_DIV_16_NR) &&
+ (dividerValue <= (PERI_DIV_16_CTL_INT16_DIV_Msk >> PERI_DIV_16_CTL_INT16_DIV_Pos)))
+ {
+ CY_SYSCLK_CLR_SET(PERI->DIV_16_CTL[dividerNum], PERI_DIV_16_CTL_INT16_DIV, dividerValue);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else
+ { /* return bad parameter */
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetDivider
+****************************************************************************//**
+*
+* Returns the integer divider value for the specified divider. One works for
+* integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional
+* divider value
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256
+* (8-bit divider) or 1 to 65536 (16-bit divider).
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ uint32_t retval;
+
+ CY_ASSERT_L1(dividerType <= CY_SYSCLK_DIV_16_BIT);
+
+ if (dividerType == CY_SYSCLK_DIV_8_BIT)
+ {
+ CY_ASSERT_L1(dividerNum < PERI_DIV_8_NR);
+ retval = _FLD2VAL(PERI_DIV_8_CTL_INT8_DIV, PERI->DIV_8_CTL[dividerNum]);
+ }
+ else
+ { /* 16-bit divider */
+ CY_ASSERT_L1(dividerNum < PERI_DIV_16_NR);
+ retval = _FLD2VAL(PERI_DIV_16_CTL_INT16_DIV, PERI->DIV_16_CTL[dividerNum]);
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphSetFracDivider
+****************************************************************************//**
+*
+* Sets one of the programmable clock dividers. This function should only be used
+* for fractional clock dividers.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \param dividerIntValue the integer divider value
+* The source of the divider is peri_clk, which is a divided version of hf_clk[0].
+* The divider value causes integer division of (divider value + 1), or division
+* by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider).
+*
+* \param dividerFracValue the fraction part of the divider
+* The fractional divider can be 1-32, thus it divides the clock by 1/32 for each
+* count. To divide the clock by 11/32nds set this value to 11.
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphSetFracDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ uint32_t dividerIntValue, uint32_t dividerFracValue)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (dividerType == CY_SYSCLK_DIV_16_5_BIT)
+ {
+ if ((dividerNum < PERI_DIV_16_5_NR) &&
+ (dividerIntValue <= (PERI_DIV_16_5_CTL_INT16_DIV_Msk >> PERI_DIV_16_5_CTL_INT16_DIV_Pos)) &&
+ (dividerFracValue <= (PERI_DIV_16_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_16_5_CTL_FRAC5_DIV_Pos)))
+ {
+ CY_SYSCLK_CLR_SET(PERI->DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_INT16_DIV, dividerIntValue);
+ CY_SYSCLK_CLR_SET(PERI->DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_FRAC5_DIV, dividerFracValue);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else if (dividerType == CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if ((dividerNum < PERI_DIV_24_5_NR) &&
+ (dividerIntValue <= (PERI_DIV_24_5_CTL_INT24_DIV_Msk >> PERI_DIV_24_5_CTL_INT24_DIV_Pos)) &&
+ (dividerFracValue <= (PERI_DIV_24_5_CTL_FRAC5_DIV_Msk >> PERI_DIV_24_5_CTL_FRAC5_DIV_Pos)))
+ {
+ CY_SYSCLK_CLR_SET(PERI->DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_INT24_DIV, dividerIntValue);
+ CY_SYSCLK_CLR_SET(PERI->DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_FRAC5_DIV, dividerFracValue);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ else
+ { /* return bad parameter */
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetFracDivider
+****************************************************************************//**
+*
+* Reports the integer and fractional parts of the divider
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \param *dividerIntValue pointer to return integer divider value
+*
+* \param *dividerFracValue pointer to return fractional divider value
+*
+* \return None. Loads pointed-to variables.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphSetFracDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ uint32_t *dividerIntValue, uint32_t *dividerFracValue)
+{
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_16_5_BIT) || (dividerType == CY_SYSCLK_DIV_24_5_BIT)) &&
+ (dividerIntValue != NULL) && (dividerFracValue != NULL));
+
+ if (dividerType == CY_SYSCLK_DIV_16_5_BIT)
+ {
+ CY_ASSERT_L1(dividerNum < PERI_DIV_16_5_NR);
+ *dividerIntValue = _FLD2VAL(PERI_DIV_16_5_CTL_INT16_DIV, PERI->DIV_16_5_CTL[dividerNum]);
+ *dividerFracValue = _FLD2VAL(PERI_DIV_16_5_CTL_FRAC5_DIV, PERI->DIV_16_5_CTL[dividerNum]);
+ }
+ else
+ { /* 24.5-bit divider */
+ CY_ASSERT_L1(dividerNum < PERI_DIV_24_5_NR);
+ *dividerIntValue = _FLD2VAL(PERI_DIV_24_5_CTL_INT24_DIV, PERI->DIV_24_5_CTL[dividerNum]);
+ *dividerFracValue = _FLD2VAL(PERI_DIV_24_5_CTL_FRAC5_DIV, PERI->DIV_24_5_CTL[dividerNum]);
+ }
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphAssignDivider
+****************************************************************************//**
+*
+* Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB.
+*
+* \param ipBlock specifies ip block to connect the clock divider to.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \return \ref cy_en_sysclk_status_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphAssignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock,
+ cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if ((ipBlock < PERI_CLOCK_NR) && (dividerType <= CY_SYSCLK_DIV_24_5_BIT))
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ PERI->CLOCK_CTL[ipBlock] = _VAL2FLD(PERI_CLOCK_CTL_TYPE_SEL, dividerType) |
+ _VAL2FLD(PERI_CLOCK_CTL_DIV_SEL, dividerNum);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetAssignedDivider
+****************************************************************************//**
+*
+* Reports which clock divider is assigned to a selected IP block.
+*
+* \param ipBlock specifies ip block to connect the clock divider to.
+*
+* \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider
+* number within that type
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphAssignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock)
+{
+ CY_ASSERT_L1(ipBlock < PERI_CLOCK_NR);
+ return PERI->CLOCK_CTL[ipBlock] & 0xFFul; /* bits [7:6] = TYPE_SEL, bits[5:0] = DIV_SEL */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphEnableDivider
+****************************************************************************//**
+*
+* Enables the selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t
+*
+* \param dividerNum specifies which divider of the selected type to configure
+*
+* \note This function also sets the phase alignment bits such that the enabled
+* divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider()
+* for information on how to phase-align a divider after it is enabled.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphEnableDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (dividerType <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ /* specify the divider, make the reference = clk_peri, and enable the divider */
+ PERI->DIV_CMD = PERI_DIV_CMD_ENABLE_Msk |
+ PERI_DIV_CMD_PA_TYPE_SEL_Msk |
+ PERI_DIV_CMD_PA_DIV_SEL_Msk |
+ _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(PERI_DIV_CMD_DIV_SEL, dividerNum);
+ (void)PERI->DIV_CMD; /* dummy read to handle buffered writes */
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphDisableDivider
+****************************************************************************//**
+*
+* Disables a selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphDisableDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (dividerType <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)))
+ {
+ /* specify the divider and disable it */
+ PERI->DIV_CMD = _VAL2FLD(PERI_DIV_CMD_DISABLE, 1u) /* 1 = disable */ |
+ _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(PERI_DIV_CMD_DIV_SEL, dividerNum);
+ retval = CY_SYSCLK_SUCCESS;
+ }
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider
+****************************************************************************//**
+*
+* First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider),
+* then aligns that divider to another programmable divider, and enables the
+* selected divider. The divider to align to must already be enabled in order
+* to align a divider to it.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t.
+*
+* \param dividerNumPA divider number of type specified to phase align to.
+*
+* \note
+* To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA
+* to 63.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_sysclk_status_t
+ Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum,
+ cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA)
+{
+ cy_en_sysclk_status_t retval = CY_SYSCLK_BAD_PARAM;
+ if (dividerTypePA <= CY_SYSCLK_DIV_24_5_BIT)
+ {
+ if (((dividerTypePA == CY_SYSCLK_DIV_8_BIT) && (dividerNumPA < PERI_DIV_8_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_16_BIT) && (dividerNumPA < PERI_DIV_16_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_16_5_BIT) && (dividerNumPA < PERI_DIV_16_5_NR)) ||
+ ((dividerTypePA == CY_SYSCLK_DIV_24_5_BIT) && ((dividerNumPA < PERI_DIV_24_5_NR) || (dividerNumPA == 63u))))
+ {
+ /* First, disable the divider that is to be phase-aligned.
+ The other two parameters are checked in that function;
+ if they're not valid, the divider is not disabled. */
+ retval = Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum);
+ if (retval == CY_SYSCLK_SUCCESS)
+ {
+ /* Then, specify the reference divider, and the divider, and enable the divider. */
+ PERI->DIV_CMD = _VAL2FLD(PERI_DIV_CMD_ENABLE, 1u) /* 1 = enable */ |
+ _VAL2FLD(PERI_DIV_CMD_PA_TYPE_SEL, dividerTypePA) |
+ _VAL2FLD(PERI_DIV_CMD_PA_DIV_SEL, dividerNumPA) |
+ _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, dividerType) |
+ _VAL2FLD(PERI_DIV_CMD_DIV_SEL, dividerNum);
+ }
+ }
+ }
+ return (retval);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_PeriphGetDividerEnabled
+****************************************************************************//**
+*
+* Reports the enabled/disabled atate of the selected divider.
+*
+* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t.
+*
+* \param dividerNum specifies which divider of the selected type to configure.
+*
+* \return The enabled/disabled state;<br>
+* false = disabled<br>
+* true = enabled
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_PeriphGetDividerEnabled
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum)
+{
+ uint32_t retval = 0ul;
+
+ CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_BIT) && (dividerNum < PERI_DIV_16_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_16_5_BIT) && (dividerNum < PERI_DIV_16_5_NR)) ||
+ ((dividerType == CY_SYSCLK_DIV_24_5_BIT) && (dividerNum < PERI_DIV_24_5_NR)));
+
+ switch(dividerType)
+ {
+ case CY_SYSCLK_DIV_8_BIT:
+ retval = _FLD2VAL(PERI_DIV_8_CTL_EN, PERI->DIV_8_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_16_BIT:
+ retval = _FLD2VAL(PERI_DIV_16_CTL_EN, PERI->DIV_16_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_16_5_BIT:
+ retval = _FLD2VAL(PERI_DIV_16_5_CTL_EN, PERI->DIV_16_5_CTL[dividerNum]);
+ break;
+ case CY_SYSCLK_DIV_24_5_BIT:
+ retval = _FLD2VAL(PERI_DIV_24_5_CTL_EN, PERI->DIV_24_5_CTL[dividerNum]);
+ break;
+ default:
+ break;
+ }
+ return ((bool)retval);
+}
+/** \} group_sysclk_clk_peripheral_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_slow SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_slow_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkSlowSetDivider
+****************************************************************************//**
+*
+* Sets the clock divider for the slow clock. The source of this clock is the
+* peripheral clock (clkPeri), which is sourced from clkHf[0].
+*
+* \param divider Divider value between 0 and 255.
+* Causes integer division of (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkSlowSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider)
+{
+ CY_SYSCLK_CLR_SET(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, (uint32_t)divider);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkSlowGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the slow clock.
+*
+* \return The divider value.
+* The integer division done is by (divider value + 1), or division by 1 to 256.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkSlowSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkSlowGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL));
+}
+/** \} group_sysclk_clk_slow_funcs */
+
+
+/* ========================================================================== */
+/* =========================== clkLf SECTION ========================== */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_lf_enums
+* \{
+*/
+/**
+* Low frequency (clkLf) input sources. See CLK_SELECT register, LFCLK_SEL bits.
+* Used with functions \ref Cy_SysClk_ClkLfSetSource, and \ref Cy_SysClk_ClkLfGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKLF_IN_ILO = 0u, /**< clkLf is sourced by the internal low speed oscillator (ILO) */
+ CY_SYSCLK_CLKLF_IN_WCO = 1u, /**< clkLf is sourced by the watch crystal oscillator (WCO) */
+ CY_SYSCLK_CLKLF_IN_ALTLF = 2u, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */
+ CY_SYSCLK_CLKLF_IN_PILO = 3u /**< clkLf is sourced by the precision low speed oscillator (PILO) */
+} cy_en_clklf_in_sources_t;
+/** \} group_sysclk_clk_lf_enums */
+
+/**
+* \addtogroup group_sysclk_clk_lf_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source);
+__STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkLfSetSource
+****************************************************************************//**
+*
+* Sets the source for the low frequency clock(clkLf).
+*
+* \param source \ref cy_en_clklf_in_sources_t
+*
+* \note The watchdog timer (WDT) must be unlocked before calling this function.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkLfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_CLKLF_IN_PILO);
+ CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkLfGetSource
+****************************************************************************//**
+*
+* Reports the source for the low frequency clock (clkLf).
+*
+* \return \ref cy_en_clklf_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkLfSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void)
+{
+ return (cy_en_clklf_in_sources_t)(_FLD2VAL(SRSS_CLK_SELECT_LFCLK_SEL, SRSS->CLK_SELECT));
+}
+/** \} group_sysclk_clk_lf_funcs */
+
+
+/* ========================================================================== */
+/* ======================== clk_timer SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_timer_enums
+* \{
+*/
+/**
+* Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL
+* and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and
+* \ref Cy_SysClk_ClkTimerGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_CLKTIMER_IN_IMO = 0u, /**< clk_timer is sourced by the internal main oscillator (IMO) */
+ CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 1u, /**< clk_timer is sourced by clkHf[0] undivided */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101u, /**< clk_timer is sourced by clkHf[0] divided by 2 */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201u, /**< clk_timer is sourced by clkHf[0] divided by 4 */
+ CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301u /**< clk_timer is sourced by clkHf[0] divided by 8 */
+} cy_en_clktimer_in_sources_t;
+/** \} group_sysclk_clk_timer_enums */
+
+/**
+* \addtogroup group_sysclk_clk_timer_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source);
+__STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider);
+__STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void);
+__STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerSetSource
+****************************************************************************//**
+*
+* Sets the source for the timer clock (clk_timer). The timer clock can be used
+* as a source for SYSTICK as an alternate clock and one or more of the energy
+* profiler counters.
+*
+* \param source \ref cy_en_clktimer_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_CLKTIMER_IN_HF0_DIV8);
+ /* set both fields TIMER_SEL and TIMER_HF0_DIV with the same input value */
+ SRSS->CLK_TIMER_CTL =
+ (SRSS->CLK_TIMER_CTL & ~(SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk)) |
+ (uint32_t)source;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerGetSource
+****************************************************************************//**
+*
+* Reports the source for the timer clock (clk_timer).
+*
+* \return \ref cy_en_clktimer_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void)
+{
+ /* return both fields TIMER_SEL and TIMER_HF0_DIV as a single combined value */
+ return (cy_en_clktimer_in_sources_t)
+ (SRSS->CLK_TIMER_CTL & (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerSetDivider
+****************************************************************************//**
+*
+* Sets the divider for the timer clock (clk_timer).
+*
+* \param divider Divider value; valid range is 0 to 255. Divides the selected
+* source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1).
+*
+* \note
+* Do not change the divider value while the timer clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider)
+{
+ CY_SYSCLK_CLR_SET(SRSS->CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, (uint32_t)divider);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the timer clock (clk_timer).
+*
+* \return The divider value
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void)
+{
+ return ((uint8_t)_FLD2VAL(SRSS_CLK_TIMER_CTL_TIMER_DIV, SRSS->CLK_TIMER_CTL));
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerEnable
+****************************************************************************//**
+*
+* Enables the timer clock (clk_timer). The timer clock can be used as a source
+* for SYSTICK and one or more of the energy profiler counters.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void)
+{
+ SRSS->CLK_TIMER_CTL |= _VAL2FLD(SRSS_CLK_TIMER_CTL_ENABLE, 1ul); /* 1 = enable */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkTimerDisable
+****************************************************************************//**
+*
+* Disables the timer clock (clk_timer).
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkTimerDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void)
+{
+ SRSS->CLK_TIMER_CTL &= ~_VAL2FLD(SRSS_CLK_TIMER_CTL_ENABLE, 1ul); /* 0 = disable */
+}
+/** \} group_sysclk_clk_timer_funcs */
+
+
+/* ========================================================================== */
+/* ========================= clk_pump SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_pump_enums
+* \{
+*/
+/**
+* Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits.
+* Used with functions \ref Cy_SysClk_ClkPumpSetSource, and
+* \ref Cy_SysClk_ClkPumpGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */
+ CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */
+ CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */
+ CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */
+ CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */
+ CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */
+ CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */
+ CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */
+ CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */
+ CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */
+ CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */
+ CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */
+ CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */
+ CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */
+ CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */
+ CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */
+} cy_en_clkpump_in_sources_t;
+
+/**
+* Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits.
+* Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and
+* \ref Cy_SysClk_ClkPumpGetDivider.
+*/
+typedef enum
+{
+ CY_SYSCLK_PUMP_NO_DIV, /**< No division on pump clock */
+ CY_SYSCLK_PUMP_DIV_2, /**< Pump clock divided by 2 */
+ CY_SYSCLK_PUMP_DIV_4, /**< Pump clock divided by 4 */
+ CY_SYSCLK_PUMP_DIV_8, /**< Pump clock divided by 8 */
+ CY_SYSCLK_PUMP_DIV_16 /**< Pump clock divided by 16 */
+} cy_en_clkpump_divide_t;
+/** \} group_sysclk_clk_pump_enums */
+
+/**
+* \addtogroup group_sysclk_clk_pump_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source);
+__STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider);
+__STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void);
+__STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpSetSource
+****************************************************************************//**
+*
+* Sets the source for the pump clock (clk_pump). The pump clock can be used for
+* the analog pumps in the CTBm block.
+*
+* \param source \ref cy_en_clkpump_in_sources_t
+*
+* \note
+* Do not change the source while the pump clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_PUMP_IN_CLKPATH15);
+ CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpGetSource
+****************************************************************************//**
+*
+* Reports the source for the pump clock (clk_pump).
+*
+* \return \ref cy_en_clkpump_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void)
+{
+ return (cy_en_clkpump_in_sources_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_SEL, SRSS->CLK_SELECT);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpSetDivider
+****************************************************************************//**
+*
+* Sets the divider of the pump clock (clk_pump).
+*
+* \param divider \ref cy_en_clkpump_divide_t
+*
+* \note
+* Do not change the divider value while the pump clock is enabled.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider)
+{
+ CY_ASSERT_L3(divider <= (SRSS_CLK_SELECT_PUMP_DIV_Msk >> SRSS_CLK_SELECT_PUMP_DIV_Pos));
+ CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpGetDivider
+****************************************************************************//**
+*
+* Reports the divider value for the pump clock (clk_pump).
+*
+* \return \ref cy_en_clkpump_divide_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpSetDivider
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void)
+{
+ return (cy_en_clkpump_divide_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_DIV, SRSS->CLK_SELECT);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpEnable
+****************************************************************************//**
+*
+* Enables the pump clock (clk_pump). The pump clock can be used for the analog
+* pumps in the CTBm block.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void)
+{
+ SRSS->CLK_SELECT |= _VAL2FLD(SRSS_CLK_SELECT_PUMP_ENABLE, 1ul); /* 1 = enable */
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkPumpDisable
+****************************************************************************//**
+*
+* Disables the pump clock (clk_pump).
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkPumpDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void)
+{
+ SRSS->CLK_SELECT &= ~_VAL2FLD(SRSS_CLK_SELECT_PUMP_ENABLE, 1ul); /* 0 = disable */
+}
+/** \} group_sysclk_clk_pump_funcs */
+
+
+/* ========================================================================== */
+/* ========================== clk_bak SECTION ========================= */
+/* ========================================================================== */
+/**
+* \addtogroup group_sysclk_clk_bak_enums
+* \{
+*/
+/**
+* Backup domain clock (clk_bak) input sources. See BACKUP->CTL register,
+* CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and
+* \ref Cy_SysClk_ClkBakGetSource.
+*/
+typedef enum
+{
+ CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */
+ CY_SYSCLK_BAK_IN_CLKLF /**< Backup domain clock input is clkLf */
+} cy_en_clkbak_in_sources_t;
+/** \} group_sysclk_clk_bak_enums */
+
+/**
+* \addtogroup group_sysclk_clk_bak_funcs
+* \{
+*/
+__STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source);
+__STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void);
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkBakSetSource
+****************************************************************************//**
+*
+* Sets the source for the backup domain clock (clk_bak).
+*
+* \param source \ref cy_en_clkbak_in_sources_t
+*
+* \note
+* clkLf is not available in all power modes. For this reason, WCO is the
+* preferred source. If the WCO is routed through the clkLf multiplexer
+* (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf.
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkBakSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source)
+{
+ CY_ASSERT_L3(source <= CY_SYSCLK_BAK_IN_CLKLF);
+ CY_SYSCLK_CLR_SET(BACKUP->CTL, BACKUP_CTL_CLK_SEL, source);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysClk_ClkBakGetSource
+****************************************************************************//**
+*
+* Reports the source for the backup domain clock (clk_bak).
+*
+* \return \ref cy_en_clkbak_in_sources_t
+*
+* \funcusage
+* \snippet sysclk/sysclk_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysClk_ClkBakSetSource
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void)
+{
+ return (cy_en_clkbak_in_sources_t)_FLD2VAL(BACKUP_CTL_CLK_SEL, BACKUP->CTL);
+}
+/** \} group_sysclk_clk_bak_funcs */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* __CY_SYSCLK_H__ */
+
+/** \} group_sysclk */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysint/cy_sysint.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,309 @@
+/***************************************************************************//**
+* \file cy_sysint.c
+* \version 1.10
+*
+* \brief
+* Provides an API implementation of the SysInt driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_sysint.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_Init
+****************************************************************************//**
+*
+* \brief Initializes the referenced interrupt by setting the priority and the
+* interrupt vector.
+*
+* Note that the interrupt vector will only be relocated if the vector table was
+* moved to __ramVectors in SRAM. Otherwise it is ignored.
+*
+* Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt.
+*
+* \param config
+* Interrupt configuration structure
+*
+* \param userIsr
+* Address of the ISR
+*
+* \return
+* Initialization status
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_Init
+*
+*******************************************************************************/
+cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr)
+{
+ cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
+
+ if(NULL != config)
+ {
+ CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
+
+ #if (CY_CPU_CORTEX_M0P)
+ if (config->intrSrc > SysTick_IRQn)
+ {
+ /* Configure the interrupt mux */
+ Cy_SysInt_SetIntSource(config->intrSrc, config->cm0pSrc);
+ }
+ #endif
+
+ NVIC_SetPriority(config->intrSrc, config->intrPriority);
+
+ /* Only set the new vector if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
+
+ (void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
+ }
+ }
+ else
+ {
+ status = CY_SYSINT_BAD_PARAM;
+ }
+
+ return(status);
+}
+
+
+#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetIntSource
+****************************************************************************//**
+*
+* \brief Configures the interrupt mux for the specified CM0+ NVIC channel.
+*
+* Setting this value to "disconnected_IRQn" (240) disconnects the interrupt
+* source and will effectively deactivate the interrupt.
+*
+* \param intrSrc
+* NVIC mux number connected to the NVIC channel of the CM0+ core
+*
+* \param cm0pSrc
+* Device interrupt to be routed to the NVIC mux
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetIntSource
+*
+*******************************************************************************/
+void Cy_SysInt_SetIntSource(IRQn_Type intrSrc, cy_en_intr_t cm0pSrc)
+{
+ /* Calculation of variables and masks */
+ uint32_t regPos = (uint32_t)intrSrc >> CY_SYSINT_CM0P_MUX_SHIFT;
+ uint32_t bitPos = ((uint32_t)intrSrc - (uint32_t)(regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
+ uint32_t bitMask = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitPos);
+ uint32_t bitMaskClr = (uint32_t)(~bitMask);
+ uint32_t bitMaskSet = (((uint32_t)cm0pSrc << bitPos) & bitMask);
+
+ uint32_t tempReg;
+
+ switch(regPos)
+ {
+ case CY_SYSINT_CM0P_MUX0:
+ tempReg = CPUSS->CM0_INT_CTL0 & bitMaskClr;
+ CPUSS->CM0_INT_CTL0 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX1:
+ tempReg = CPUSS->CM0_INT_CTL1 & bitMaskClr;
+ CPUSS->CM0_INT_CTL1 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX2:
+ tempReg = CPUSS->CM0_INT_CTL2 & bitMaskClr;
+ CPUSS->CM0_INT_CTL2 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX3:
+ tempReg = CPUSS->CM0_INT_CTL3 & bitMaskClr;
+ CPUSS->CM0_INT_CTL3 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX4:
+ tempReg = CPUSS->CM0_INT_CTL4 & bitMaskClr;
+ CPUSS->CM0_INT_CTL4 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX5:
+ tempReg = CPUSS->CM0_INT_CTL5 & bitMaskClr;
+ CPUSS->CM0_INT_CTL5 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX6:
+ tempReg = CPUSS->CM0_INT_CTL6 & bitMaskClr;
+ CPUSS->CM0_INT_CTL6 = tempReg | bitMaskSet;
+ break;
+ case CY_SYSINT_CM0P_MUX7:
+ tempReg = CPUSS->CM0_INT_CTL7 & bitMaskClr;
+ CPUSS->CM0_INT_CTL7 = tempReg | bitMaskSet;
+ break;
+ default:
+ break;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetIntSource
+****************************************************************************//**
+*
+* \brief Gets the interrupt source of CM0+ NVIC channel.
+*
+* \param intrSrc
+* NVIC mux number connected to the NVIC channel of the CM0+ core
+*
+* \return
+* Device interrupt source connected to the NVIC mux. A returned value of
+* "disconnected_IRQn" (240) indicates that the interrupt source is disconnected.
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetIntSource
+*
+*******************************************************************************/
+cy_en_intr_t Cy_SysInt_GetIntSource(IRQn_Type intrSrc)
+{
+ /* Calculation of variables */
+ uint32_t regPos = (uint32_t)intrSrc >> CY_SYSINT_CM0P_MUX_SHIFT;
+ uint32_t bitPos = ((uint32_t)intrSrc - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE;
+ uint32_t bitMask = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitPos);
+
+ cy_en_intr_t srcVal = disconnected_IRQn;
+ uint32_t tempReg = 0UL;
+
+ switch(regPos)
+ {
+ case CY_SYSINT_CM0P_MUX0:
+ tempReg = (CPUSS->CM0_INT_CTL0 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX1:
+ tempReg = (CPUSS->CM0_INT_CTL1 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX2:
+ tempReg = (CPUSS->CM0_INT_CTL2 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX3:
+ tempReg = (CPUSS->CM0_INT_CTL3 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX4:
+ tempReg = (CPUSS->CM0_INT_CTL4 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX5:
+ tempReg = (CPUSS->CM0_INT_CTL5 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX6:
+ tempReg = (CPUSS->CM0_INT_CTL6 & bitMask) >> bitPos;
+ break;
+ case CY_SYSINT_CM0P_MUX7:
+ tempReg = (CPUSS->CM0_INT_CTL7 & bitMask) >> bitPos;
+ break;
+ default:
+ break;
+ }
+
+ srcVal = (cy_en_intr_t)tempReg;
+ return (srcVal);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetVector
+****************************************************************************//**
+*
+* \brief Changes the ISR vector for the Interrupt.
+*
+* Note that for CM0+, this function sets the interrupt vector for the interrupt
+* mux output feeding into the NVIC.
+*
+* Note that this function relies on the assumption that the vector table is
+* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will
+* return the address of the default ISR location in Flash vector table.
+*
+* \param intrSrc
+* Interrrupt source
+*
+* \param userIsr
+* Address of the ISR to set in the interrupt vector table
+*
+* \return
+* Previous address of the ISR in the interrupt vector table, before the
+* function call
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetVector
+*
+*******************************************************************************/
+cy_israddress Cy_SysInt_SetVector(IRQn_Type intrSrc, cy_israddress userIsr)
+{
+ cy_israddress prevIsr;
+
+ /* Only set the new vector if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
+
+ prevIsr = __ramVectors[CY_INT_IRQ_BASE + intrSrc];
+ __ramVectors[CY_INT_IRQ_BASE + intrSrc] = userIsr;
+ }
+ else
+ {
+ prevIsr = __Vectors[CY_INT_IRQ_BASE + intrSrc];
+ }
+
+ return prevIsr;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetVector
+****************************************************************************//**
+*
+* \brief Gets the address of the current ISR vector for the Interrupt.
+*
+* Note that for CM0+, this function returns the interrupt vector for the
+* interrupt mux output feeding into the NVIC.
+*
+* Note that this function relies on the assumption that the vector table is
+* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM.
+*
+* \param intrSrc
+* Interrupt source
+*
+* \return
+* Address of the ISR in the interrupt vector table
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetVector
+*
+*******************************************************************************/
+cy_israddress Cy_SysInt_GetVector(IRQn_Type intrSrc)
+{
+ cy_israddress currIsr;
+
+ /* Only return the SRAM ISR address if it was moved to __ramVectors */
+ if (SCB->VTOR == (uint32_t)&__ramVectors)
+ {
+ currIsr = __ramVectors[CY_INT_IRQ_BASE + intrSrc];
+ }
+ else
+ {
+ currIsr = __Vectors[CY_INT_IRQ_BASE + intrSrc];
+ }
+
+ return currIsr;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysint/cy_sysint.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,394 @@
+/***************************************************************************//**
+* \file cy_sysint.h
+* \version 1.10
+*
+* \brief
+* Provides an API declaration of the SysInt driver
+*
+********************************************************************************
+* \copyright
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_sysint System Interrupt (SysInt)
+* \{
+* The SysInt driver provides an API to configure the device peripheral interrupts.
+* It provides a lightweight interface to complement
+* the <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html">CMSIS core NVIC API</a>.
+* The provided functions are applicable for all cores in a device and they can
+* be used to configure and connect device peripheral interrupts to one or more
+* cores.
+*
+* \section group_sysint_driver_usage Driver Usage
+*
+* \subsection group_sysint_initialization Initialization
+*
+* Interrupt numbers are defined in a device-specific header file, such as
+* cy8c68237bz_ble.h.
+*
+* To configure an interrupt, call Cy_SysInt_Init(). Populate
+* the configuration structure (cy_stc_sysint_t) and pass it as a parameter
+* along with the ISR address. This initializes the interrupt and
+* instructs the CPU to jump to the specified ISR vector upon a valid trigger.
+*
+* On the Cortex M4, system interrupt source 'n' is connected to the
+* corresponding IRQn. Deep-sleep capable interrupts are allocated to deep-sleep
+* capable IRQn channels.
+*
+* The CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device
+* interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer
+* at each of the 32 NVIC channels. The configuration structure (cy_stc_sysint_t)
+* must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC
+* mux (intrSrc). CM0+ NVIC channels 0-2 and 30-31 are reserved for system use.
+*
+* In addition, on the CM0+ core, a deep-sleep capable interrupt must be routed
+* to a deep-sleep capable IRQn channel. Otherwise it won't work. The device
+* header file identifies which IRQn channels are deep-sleep capable.
+*
+* \subsection group_sysint_enable Enable
+*
+* After initializing an interrupt, use the CMSIS Core
+* <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ()</a> function
+* to enable it. Given an initialization structure named config,
+* the function should be called as follows:
+* \code
+* NVIC_EnableIRQ(config.intrSrc)
+* \endcode
+*
+* \subsection group_sysint_service Writing an interrupt service routine
+*
+* Servicing interrupts in the Peripheral Drivers should follow a prescribed
+* recipe to ensure all interrupts are serviced and duplicate interrupts are not
+* received. Any peripheral-specific register that must be written to clear the
+* source of the interrupt should be written as soon as possible in the interrupt
+* service routine. However, note that due to buffering on the output bus to the
+* peripherals, the write clearing the interrupt may be delayed. After performing
+* the normal interrupt service that should respond to the interrupting
+* condition, the interrupt register that was initially written to clear the
+* register should be read before returning from the interrupt service routine.
+* This read ensures that the initial write has been flushed out to the hardware.
+* Note, no additional processing should be performed based on the result of this
+* read, as this read is just intended to ensure the write operation is flushed.
+*
+* This final read may indicate a pending interrupt. What this means is that in
+* the interval between when the write actually happened at the peripheral and
+* when the read actually happened at the peripheral, an interrupting condition
+* occurred. This is ok and a return from the interrupt is still the correct
+* action. As soon as conditions warrant, meaning interrupts are enabled and
+* there are no higher priority interrupts pending, the interrupt will be
+* triggered again to service the additional condition.
+*
+* \section group_sysint_section_configuration_considerations Configuration Considerations
+*
+* CM0+ <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">NVIC IRQn</a>
+* channels 0-2 and 30-31 are reserved for system use, inter-processor communication,
+* and the crypto driver. Other IRQn channels (3-29) are available to the user application.
+*
+* Deep-sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR
+* parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the
+* capability to trigger deep-sleep interrupts. A deep-sleep capable interrupt source
+* must be connected to one of these muxes to be able to trigger in deep-sleep.
+* Refer to the IRQn_Type definition in the device header.
+*
+* The default interrupt handler functions are defined as weak functions in the
+* startup file. Defining these in the user application will allow the linker to
+* place them in the Flash vector table. This avoids the need for a RAM vector table.
+* However in this scenario, interrupt handler re-location at run-time is not possible,
+* unless the vector table is relocated to RAM.
+*
+* \section group_sysint_more_information More Information
+*
+* Refer to the technical reference manual (TRM) and the device datasheet.
+*
+* \section group_sysint_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>A</td>
+* <td>Nested comments are not recognized in the ISO standard.</td>
+* <td>
+* The comments provide the useful WEB link to the additional documentation.</td>
+* </tr>
+* <tr>
+* <td>8.12</td>
+* <td>R</td>
+* <td>Array declared with unknown size.</td>
+* <td>
+* __Vectors and __ramVectors arrays can have the different size depend on the selected device.</td>
+* </tr>
+* </table>
+*
+* \section group_sysint_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10</td>
+* <td>Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ().</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_sysint_macros Macros
+* \defgroup group_sysint_globals Global variables
+* \defgroup group_sysint_functions Functions
+* \defgroup group_sysint_data_structures Data Structures
+* \defgroup group_sysint_enums Enumerated Types
+*/
+
+
+#if !defined(CY_SYSINT_H)
+#define CY_SYSINT_H
+
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+* Global Variable
+***************************************/
+
+/**
+* \addtogroup group_sysint_globals
+* \{
+*/
+
+extern const cy_israddress __Vectors[]; /**< Vector table in Flash */
+extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */
+
+/** \} group_sysint_globals */
+
+
+/***************************************
+* Global Interrupt
+***************************************/
+
+/**
+* \addtogroup group_sysint_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SYSINT_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_SYSINT_DRV_VERSION_MINOR 10
+
+/** SysInt driver ID */
+#define CY_SYSINT_ID CY_PDL_DRV_ID(0x15u)
+
+/** \} group_sysint_macros */
+
+
+/***************************************
+* Enumeration
+***************************************/
+
+/**
+* \addtogroup group_sysint_enums
+* \{
+*/
+
+/**
+* SysInt Driver error codes
+*/
+typedef enum
+{
+ CY_SYSINT_SUCCESS = 0x00u, /**< Returned successful */
+ CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
+} cy_en_sysint_status_t;
+
+/** \} group_sysint_enums */
+
+
+/***************************************
+* Configuration Structure
+***************************************/
+
+/**
+* \addtogroup group_sysint_data_structures
+* \{
+*/
+
+/**
+* Initialization configuration structure for a single interrupt channel
+*/
+typedef struct {
+ IRQn_Type intrSrc; /**< Interrupt source */
+#if (CY_CPU_CORTEX_M0P)
+ cy_en_intr_t cm0pSrc; /**< (CM0+ only) Maps cm0pSrc device interrupts to intrSrc */
+#endif
+ uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */
+} cy_stc_sysint_t;
+
+/** \} group_sysint_data_structures */
+
+
+/***************************************
+* Constants
+***************************************/
+
+/** \cond INTERNAL */
+
+#define CY_INT_IRQ_BASE (16u) /**< Start location of interrupts in the vector table */
+#define CY_SYSINT_STATE_MASK (1ul) /**< Mask for interrupt state */
+#define CY_SYSINT_STIR_MASK (0xfful) /**< Mask for software trigger interrupt register */
+#define CY_SYSINT_CM0P_MUX_MASK (0xfful) /**< CM0+ NVIC multiplexer mask */
+#define CY_SYSINT_CM0P_MUX_SHIFT (2u) /**< CM0+ NVIC multiplexer shift */
+#define CY_SYSINT_CM0P_MUX_SCALE (3u) /**< CM0+ NVIC multiplexer scaling value */
+
+#define CY_SYSINT_CM0P_MUX0 (0u) /**< CM0+ NVIC multiplexer register 0 */
+#define CY_SYSINT_CM0P_MUX1 (1u) /**< CM0+ NVIC multiplexer register 1 */
+#define CY_SYSINT_CM0P_MUX2 (2u) /**< CM0+ NVIC multiplexer register 2 */
+#define CY_SYSINT_CM0P_MUX3 (3u) /**< CM0+ NVIC multiplexer register 3 */
+#define CY_SYSINT_CM0P_MUX4 (4u) /**< CM0+ NVIC multiplexer register 4 */
+#define CY_SYSINT_CM0P_MUX5 (5u) /**< CM0+ NVIC multiplexer register 5 */
+#define CY_SYSINT_CM0P_MUX6 (6u) /**< CM0+ NVIC multiplexer register 6 */
+#define CY_SYSINT_CM0P_MUX7 (7u) /**< CM0+ NVIC multiplexer register 7 */
+
+/* Parameter validation macros */
+#define CY_SYSINT_IS_PRIORITY_VALID(intrPriority) ((uint32_t)(1UL << __NVIC_PRIO_BITS) > (intrPriority))
+#define CY_SYSINT_IS_VECTOR_VALID(userIsr) (NULL != (userIsr))
+
+/** \endcond */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_sysint_functions
+* \{
+*/
+cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr);
+cy_israddress Cy_SysInt_SetVector(IRQn_Type intrSrc, cy_israddress userIsr);
+cy_israddress Cy_SysInt_GetVector(IRQn_Type intrSrc);
+__STATIC_INLINE void Cy_SysInt_SetIntSourceNMI(IRQn_Type intrSrc);
+__STATIC_INLINE IRQn_Type Cy_SysInt_GetIntSourceNMI(void);
+#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+ void Cy_SysInt_SetIntSource(IRQn_Type intrSrc, cy_en_intr_t cm0pSrc);
+ cy_en_intr_t Cy_SysInt_GetIntSource(IRQn_Type intrSrc);
+#else
+ __STATIC_INLINE void Cy_SysInt_SoftwareTrig(IRQn_Type intrSrc);
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SetIntSourceNMI
+****************************************************************************//**
+*
+* \brief Sets the interrupt source of NMI.
+*
+* The interrupt source must be a positive number. Setting the value to
+* "unconnected_IRQn" (240) disconnects the interrupt source from the NMI.
+*
+* \param intrSrc
+* Interrupt source
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetIntSourceNMI
+*
+* \note The CM0+ NMI is used for performing system calls that execute out of ROM.
+* Hence modification of the NMI source is strongly discouraged. However if it
+* must be updated, the NMI source must be provided from the cy_en_intr_t enum
+* as it is a direct connection to the interrupt source.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysInt_SetIntSourceNMI(IRQn_Type intrSrc)
+{
+ #if CY_CPU_CORTEX_M0P
+ CPUSS->CM0_NMI_CTL = (uint32_t)intrSrc;
+ #else
+ CPUSS->CM4_NMI_CTL = (uint32_t)intrSrc;
+ #endif
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetIntSourceNMI
+****************************************************************************//**
+*
+* \brief Gets the interrupt source of the NMI.
+*
+* \return
+* Interrupt Source. A value of "unconnected_IRQn" (240) means that there is no
+* interrupt source for the NMI, and it can be only be triggered through software.
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SetIntSourceNMI
+*
+*******************************************************************************/
+__STATIC_INLINE IRQn_Type Cy_SysInt_GetIntSourceNMI(void)
+{
+ #if CY_CPU_CORTEX_M0P
+ return (IRQn_Type)(CPUSS->CM0_NMI_CTL);
+ #else
+ return (IRQn_Type)(CPUSS->CM4_NMI_CTL);
+ #endif
+}
+
+
+#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_SoftwareTrig
+****************************************************************************//**
+*
+* \brief Triggers an interrupt using software (Not applicable for CM0+).
+*
+* \param intrSrc
+* Interrupt source
+*
+* \funcusage
+* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_SoftwareTrig
+*
+* \note Only privileged software can enable unprivileged access to the
+* Software Trigger Interrupt Register (STIR).
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysInt_SoftwareTrig(IRQn_Type intrSrc)
+{
+ NVIC->STIR = (uint32_t)intrSrc & CY_SYSINT_STIR_MASK;
+}
+
+#endif
+
+/*******************************************************************************
+* Function Name: Cy_SysInt_GetState
+****************************************************************************//**
+*
+* This function is deprecated. It invokes the NVIC_GetEnableIRQ function.
+*
+*******************************************************************************/
+#define Cy_SysInt_GetState NVIC_GetEnableIRQ
+
+/** \} group_sysint_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_SYSINT_H */
+
+/** \} group_sysint */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syslib/TOOLCHAIN_ARM_STD/cy_syslib_mdk.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,100 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmRv.s +; \version 2.0.1 +; +; \brief Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + +;------------------------------------------------------------------------------- +; Function Name: Cy_SysLib_DelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32_t cycles: The number of cycles to delay. +; +;------------------------------------------------------------------------------- +; void Cy_SysLib_DelayCycles(uint32_t cycles) + ALIGN 8 +Cy_SysLib_DelayCycles FUNCTION + EXPORT Cy_SysLib_DelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to the nearest multiple of 4. + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags. + BEQ Cy_DelayCycles_done ; 2 2 Skip if 0. +Cy_DelayCycles_loop + ADDS r0, r0, #1 ; 1 2 Increment the counter. + SUBS r0, r0, #2 ; 1 2 Decrement the counter by 2. + BNE Cy_DelayCycles_loop ; 2 2 2 CPU cycles (if branch is taken). + NOP ; 1 2 Loop alignment padding. +Cy_DelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: Cy_SysLib_EnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +; indicating whether interrupts were previously enabled. +; +; Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +; enable bit with interrupts still enabled. The test and set of the interrupt +; bits are not atomic. Therefore, to avoid a corrupting processor state, it must +; be the policy that all interrupt routines restore the interrupt enable bits as +; they were found on entry. +; +; Return: +; uint8_t +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8_t Cy_SysLib_EnterCriticalSection(void) +Cy_SysLib_EnterCriticalSection FUNCTION + EXPORT Cy_SysLib_EnterCriticalSection + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable the interrupts. + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: Cy_SysLib_ExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; Cy_SysLib_ExitCriticalSection re-enables interrupts if they were enabled +; before Cy_SysLib_EnterCriticalSection was called. The argument should be the +; value returned from Cy_SysLib_EnterCriticalSection. +; +; Parameters: +; uint8_t savedIntrStatus: +; The saved interrupt status returned by the Cy_SysLib_EnterCriticalSection +; function. +; +;------------------------------------------------------------------------------- +; void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) +Cy_SysLib_ExitCriticalSection FUNCTION + EXPORT Cy_SysLib_ExitCriticalSection + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + ENDFUNC + + END + +; [] END OF FILE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syslib/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,99 @@ +/***************************************************************************//** +* \file cy_syslib_core_armcc.s +* \version 2.0.1 +* +* \brief Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: Cy_SysLib_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void Cy_SysLib_DelayCycles(uint32_t cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global Cy_SysLib_DelayCycles +.func Cy_SysLib_DelayCycles, Cy_SysLib_DelayCycles +.type Cy_SysLib_DelayCycles, %function +.thumb_func +Cy_SysLib_DelayCycles: /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ Cy_DelayCycles_done /* 2 2 Skip if 0 */ +Cy_DelayCycles_loop: +/* For CM0+ branch instruction takes 2 CPU cycles */ + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE Cy_DelayCycles_loop /* 2 2 2 CPU cycles (if branch is taken)*/ + NOP /* 1 2 Loop alignment padding */ +Cy_DelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ +.endfunc + + +/******************************************************************************* +* Function Name: Cy_SysLib_EnterCriticalSection +****************************************************************************//** +* +* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t Cy_SysLib_EnterCriticalSection(void) */ +.global Cy_SysLib_EnterCriticalSection +.func Cy_SysLib_EnterCriticalSection, Cy_SysLib_EnterCriticalSection +.type Cy_SysLib_EnterCriticalSection, %function +.thumb_func +Cy_SysLib_EnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: Cy_SysLib_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value +* returned from \ref Cy_SysLib_EnterCriticalSection(). +* +* \param uint8_t savedIntrStatus: +* Saved interrupt status returned by the \ref Cy_SysLib_EnterCriticalSection(). +* +*******************************************************************************/ +/* void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) */ +.global Cy_SysLib_ExitCriticalSection +.func Cy_SysLib_ExitCriticalSection, Cy_SysLib_ExitCriticalSection +.type Cy_SysLib_ExitCriticalSection, %function +.thumb_func +Cy_SysLib_ExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + +/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syslib/TOOLCHAIN_IAR/cy_syslib_iar.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,89 @@ +/***************************************************************************//** +* \file cy_syslib_iar.s +* \version 2.0.1 +* +* \brief Assembly routines for IAR Embedded Workbench IDE. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + SECTION .text:CODE:ROOT(4) + PUBLIC Cy_SysLib_DelayCycles + PUBLIC Cy_SysLib_EnterCriticalSection + PUBLIC Cy_SysLib_ExitCriticalSection + THUMB + + +/******************************************************************************* +* Function Name: Cy_SysLib_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void Cy_SysLib_DelayCycles(uint32_t cycles) */ + +Cy_SysLib_DelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ Cy_DelayCycles_done +Cy_DelayCycles_loop: + ADDS r0, r0, #1 + SUBS r0, r0, #2 + BNE Cy_DelayCycles_loop + NOP +Cy_DelayCycles_done: + BX lr + + +/******************************************************************************* +* Function Name: Cy_SysLib_EnterCriticalSection +****************************************************************************//** +* +* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. The test and set of the interrupt +* bits are not atomic. Therefore, to avoid corrupting processor state, it must +* be the policy that all interrupt routines restore the interrupt enable bits +* as they were found on entry. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t Cy_SysLib_EnterCriticalSection(void) */ + +Cy_SysLib_EnterCriticalSection: + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable interrupts. + BX lr + +/******************************************************************************* +* Function Name: Cy_SysLib_ExitCriticalSection +****************************************************************************//** +* +* Cy_SysLib_ExitCriticalSection re-enables the interrupts if they were enabled +* before Cy_SysLib_EnterCriticalSection was called. The argument should be the +* value returned from Cy_SysLib_EnterCriticalSection. +* +* \param uint8_t savedIntrStatus: +* The saved interrupt status returned by the +* \ref Cy_SysLib_EnterCriticalSection(). +* +*******************************************************************************/ +/* void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) */ + +Cy_SysLib_ExitCriticalSection: + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syslib/cy_syslib.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,588 @@
+/***************************************************************************//**
+* \file cy_syslib.c
+* \version 2.0.1
+*
+* Description:
+* Provides system API implementation for the SysLib driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_syslib.h"
+#include "ipc/cy_ipc_drv.h"
+#if !defined(NDEBUG)
+ #include <string.h>
+#endif /* NDEBUG */
+
+/* Flash wait states (LP mode at 1.1v) */
+#define CY_SYSLIB_FLASH_LP_WS_0_FREQ_MAX ( 29UL)
+#define CY_SYSLIB_FLASH_LP_WS_1_FREQ_MAX ( 58UL)
+#define CY_SYSLIB_FLASH_LP_WS_2_FREQ_MAX ( 87UL)
+#define CY_SYSLIB_FLASH_LP_WS_3_FREQ_MAX (120UL)
+#define CY_SYSLIB_FLASH_LP_WS_4_FREQ_MAX (150UL)
+
+/* Flash wait states (ULP mode at 0.9v) */
+#define CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX ( 16UL)
+#define CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX ( 33UL)
+#define CY_SYSLIB_FLASH_ULP_WS_2_FREQ_MAX ( 50UL)
+
+/* ROM and SRAM wait states for the slow clock domain (LP mode at 1.1v) */
+#define CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX (100UL)
+#define CY_SYSLIB_LP_SLOW_WS_1_FREQ_MAX (120UL)
+
+/* ROM and SRAM wait states for the slow clock domain (ULP mode at 0.9v) */
+#define CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX ( 25UL)
+#define CY_SYSLIB_ULP_SLOW_WS_1_FREQ_MAX ( 50UL)
+
+
+#if !defined(NDEBUG)
+ CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE];
+ CY_NOINIT uint32_t cy_assertLine;
+#endif /* NDEBUG */
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ CY_NOINIT cy_stc_fault_frame_t cy_faultFrame;
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+#if defined(__ARMCC_VERSION)
+ static __ASM void Cy_SysLib_AsmInfiniteLoop(void) { b . };
+#endif /* (__ARMCC_VERSION) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_Delay
+****************************************************************************//**
+*
+* The function delays by the specified number of milliseconds.
+* By default, the number of cycles to delay is calculated based on the
+* \ref SystemCoreClock.
+*
+* \param milliseconds The number of milliseconds to delay.
+*
+* \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay.
+* If the function parameter (milliseconds) is bigger than
+* CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent
+* an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API.
+*
+*******************************************************************************/
+void Cy_SysLib_Delay(uint32_t milliseconds)
+{
+ while(milliseconds > CY_DELAY_MS_OVERFLOW)
+ {
+ /* This loop prevents an overflow in value passed to Cy_SysLib_DelayCycles() API.
+ * At 100 MHz, (milliseconds * cy_delayFreqKhz) product overflows
+ * in case if milliseconds parameter is more than 42 seconds.
+ */
+ Cy_SysLib_DelayCycles(cy_delay32kMs);
+ milliseconds -= CY_DELAY_MS_OVERFLOW;
+ }
+
+ Cy_SysLib_DelayCycles(milliseconds * cy_delayFreqKhz);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_DelayUs
+****************************************************************************//**
+*
+* The function delays by the specified number of microseconds.
+* By default, the number of cycles to delay is calculated based on the
+* \ref SystemCoreClock.
+*
+* \param microseconds The number of microseconds to delay.
+*
+* \note If the CPU frequency is a small non-integer number, the actual delay
+* can be up to twice as long as the nominal value. The actual delay
+* cannot be shorter than the nominal one.
+*
+*******************************************************************************/
+void Cy_SysLib_DelayUs(uint16_t microseconds)
+{
+ Cy_SysLib_DelayCycles((uint32_t) microseconds * cy_delayFreqMhz);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_Halt
+****************************************************************************//**
+*
+* This function halts the CPU but only the CPU which calls the function.
+* It doesn't affect other CPUs.
+*
+* \param reason The value to be used during debugging.
+*
+* \note The function executes the BKPT instruction for halting CPU and is
+* intended to be used for the debug purpose. A regular use case requires
+* Debugger attachment before the function call.
+* The BKPT instruction causes the CPU to enter the Debug state. Debug
+* tools can use this to investigate the system state, when the
+* instruction at a particular address is reached.
+*
+* \note Execution of a BKPT instruction without a debugger attached produces
+* a fault. The fault results in the HardFault exception being taken
+* or causes a Lockup state if it occurs in the NMI or HardFault handler.
+* The default HardFault handler make a software reset if the build option
+* is the release mode (NDEBUG). If the build option is the debug mode,
+* the system will stay in the infinite loop of the
+* \ref Cy_SysLib_ProcessingFault() function.
+*
+*******************************************************************************/
+__NO_RETURN void Cy_SysLib_Halt(uint32_t reason)
+{
+ if(0U != reason)
+ {
+ /* To remove an unreferenced local variable warning */
+ }
+
+ #if defined (__ARMCC_VERSION)
+ __breakpoint(0x0);
+ #elif defined(__GNUC__)
+ __asm(" bkpt 1");
+ #elif defined (__ICCARM__)
+ __asm(" bkpt 1");
+ #else
+ #error "An unsupported toolchain"
+ #endif /* (__ARMCC_VERSION) */
+
+ while(1) {}
+}
+
+
+#if !defined(NDEBUG) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Macro Name: Cy_SysLib_AssertFailed
+****************************************************************************//**
+*
+* This function stores the ASSERT location of the file name (including path
+* to file) and line number in a non-zero init area for debugging. Also it calls
+* the \ref Cy_SysLib_Halt() function to halt the processor.
+*
+* \param file The file name of the ASSERT location.
+* \param line The line number of the ASSERT location.
+*
+* \note A stored file name and line number could be accessed by
+* cy_assertFileName and cy_assertLine global variables.
+* \note This function has the WEAK option, so the user can redefine
+* the function for a custom processing.
+*
+*******************************************************************************/
+__WEAK void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line)
+{
+ (void) strncpy(cy_assertFileName, file, CY_MAX_FILE_NAME_SIZE);
+ cy_assertLine = line;
+ Cy_SysLib_Halt(0UL);
+}
+#endif /* !defined(NDEBUG) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ClearFlashCacheAndBuffer
+****************************************************************************//**
+*
+* This function invalidates the flash cache and buffer. It ensures the valid
+* data is read from flash instead of using outdated data from the cache.
+* The caches' LRU structure is also reset to their default state.
+*
+* \note The operation takes a maximum of three clock cycles on the slowest of
+* the clk_slow and clk_fast clocks.
+*
+*******************************************************************************/
+void Cy_SysLib_ClearFlashCacheAndBuffer(void)
+{
+ FLASHC->FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ResetBackupDomain
+****************************************************************************//**
+*
+* This function resets the backup domain power to avoid the ILO glitch. The
+* glitch can occur when the device is reset due to POR/BOD/XRES while
+* the backup voltage is supplied into the system.
+*
+* \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
+* when the reset is complete. After setting the register, this function
+* reads the register immediately for returning the result of the backup
+* domain reset state. The reading register is important because the Read
+* itself takes multiple AHB clock cycles, and the reset is actually
+* finishing during that time.
+*
+* \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
+* Otherwise returns CY_SYSLIB_INVALID_STATE.
+*
+*******************************************************************************/
+cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void)
+{
+ BACKUP->RESET = BACKUP_RESET_RESET_Msk;
+
+ return ( ((BACKUP->RESET & BACKUP_RESET_RESET_Msk) == 0UL) ? CY_SYSLIB_SUCCESS : CY_SYSLIB_INVALID_STATE );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetResetReason
+****************************************************************************//**
+*
+* The function returns the cause for the latest reset(s) that occurred in
+* the system. The reset causes include an HFCLK error, system faults, and
+* device reset on a wakeup from Hibernate mode.
+* The return results are consolidated reset causes from reading RES_CAUSE,
+* RES_CAUSE2 and PWR_HIBERNATE token registers.
+*
+* \return The cause of a system reset.
+*
+* | Name | Value
+* |-------------------------------|---------------------
+* | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0)
+* | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1)
+* | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2)
+* | CY_SYSLIB_RESET_CSV_WCO_LOSS | 0x00008 (bit3)
+* | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4)
+* | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5)
+* | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6)
+* | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7)
+* | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8)
+* | CY_SYSLIB_RESET_HFCLK_LOSS | 0x10000 (bit16)
+* | CY_SYSLIB_RESET_HFCLK_ERR | 0x20000 (bit17)
+* | CY_SYSLIB_RESET_HIB_WAKEUP | 0x40000 (bit18)
+*
+* \note CY_SYSLIB_RESET_CSV_WCO_LOSS, CY_SYSLIB_RESET_HFCLK_LOSS and
+* CY_SYSLIB_RESET_HFCLK_ERR causes of a system reset available only if
+* WCO CSV present in the device.
+*
+*******************************************************************************/
+uint32_t Cy_SysLib_GetResetReason(void)
+{
+ uint32_t retVal = SRSS->RES_CAUSE;
+
+#if (SRSS_WCOCSV_PRESENT != 0U)
+ uint32_t resCause2 = SRSS->RES_CAUSE2;
+
+ retVal |= ((CY_LO16(resCause2) > 0U) ? CY_SYSLIB_RESET_HFCLK_LOSS : 0U) |
+ ((CY_HI16(resCause2) > 0U) ? CY_SYSLIB_RESET_HFCLK_ERR : 0U);
+#endif /* (SRSS_WCOCSV_PRESENT != 0U) */
+
+ if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS->PWR_HIBERNATE))
+ {
+ retVal |= CY_SYSLIB_RESET_HIB_WAKEUP;
+ }
+
+ return (retVal);
+}
+
+
+#if (SRSS_WCOCSV_PRESENT != 0U) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetNumHfclkResetCause
+****************************************************************************//**
+*
+* This function returns the number of HF_CLK which is a reset cause (RES_CAUSE2)
+* by a loss or an error of the high frequency clock.
+*
+* The Clock supervisors (CSV) can make a reset as CSV_FREQ_ACTION setting
+* when a CSV frequency anomaly is detected. The function returns the index
+* of HF_CLK, if a reset occurred due to an anomaly HF_CLK. There are two
+* different options for monitoring on HF_CLK which are a frequency loss
+* and a frequency error.
+*
+* \return
+* - The number HF_CLK from Clock Supervisor High Frequency Loss: Bits[15:0]
+* - The number HF_CLK from Clock Supervisor High Frequency error: Bits[31:16]
+*
+*******************************************************************************/
+uint32_t Cy_SysLib_GetNumHfclkResetCause(void)
+{
+ return (SRSS->RES_CAUSE2);
+}
+#endif /* (SRSS_WCOCSV_PRESENT != 0U) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ClearResetReason
+****************************************************************************//**
+*
+* This function clears the values of RES_CAUSE and RES_CAUSE2. Also it clears
+* PWR_HIBERNATE token, which indicates reset event on waking up from HIBERNATE.
+*
+*******************************************************************************/
+void Cy_SysLib_ClearResetReason(void)
+{
+ /* RES_CAUSE and RES_CAUSE2 register's bits are RW1C (every bit is cleared upon writing 1),
+ * so write all ones to clear all the reset reasons.
+ */
+ SRSS->RES_CAUSE = 0xFFFFFFFFU;
+ SRSS->RES_CAUSE2 = 0xFFFFFFFFU;
+
+ if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS->PWR_HIBERNATE))
+ {
+ /* Clears PWR_HIBERNATE token */
+ SRSS->PWR_HIBERNATE &= ~SRSS_PWR_HIBERNATE_TOKEN_Msk;
+ }
+}
+
+
+#if (CY_CPU_CORTEX_M0P) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysLib_SoftResetCM4
+****************************************************************************//**
+*
+* This function performs a CM4 Core software reset using the CM4_PWR_CTL
+* register. The register is accessed by CM0 Core by using a command transferred
+* to SROM API through the IPC channel. When the command is sent, the API waits
+* for the IPC channel release.
+*
+* \note This function should be called only when the CM4 core is in Deep
+* Sleep mode.
+* \note This function will not reset CM0+ Core.
+* \note This function waits for an IPC channel release state.
+*
+*******************************************************************************/
+void Cy_SysLib_SoftResetCM4(void)
+{
+ static uint32_t msg = CY_IPC_DATA_FOR_CM4_SOFT_RESET;
+
+ /* Tries to acquire the IPC structure and pass the arguments to SROM API.
+ * SROM API parameters:
+ * ipcPtr: IPC_STRUCT0 - IPC Structure 0 reserved for M0+ Secure Access.
+ * notifyEvent_Intr: 1U - IPC Interrupt Structure 1 is used for Releasing IPC 0 (M0+ NMI Handler).
+ * msgPtr: &msg - The address of SRAM with the API's parameters.
+ */
+ if(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT0, 1U, (void *) &msg))
+ {
+ CY_ASSERT(0U != 0U);
+ }
+
+ while(Cy_IPC_Drv_IsLockAcquired(IPC_STRUCT0))
+ {
+ /* Waits until SROM API runs the command (sent over the IPC channel) and releases the IPC_STRUCT0. */
+ }
+}
+#endif /* CY_CPU_CORTEX_M0P || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetUniqueId
+****************************************************************************//**
+*
+* This function returns the silicon unique ID.
+* The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, Die Sort#, Die Minor
+* and Die Year.
+*
+* \return A combined 64-bit unique ID.
+* [63:57] - DIE_YEAR
+* [56:56] - DIE_MINOR
+* [55:48] - DIE_SORT
+* [47:40] - DIE_Y
+* [39:32] - DIE_X
+* [31:24] - DIE_WAFER
+* [23:16] - DIE_LOT[2]
+* [15: 8] - DIE_LOT[1]
+* [ 7: 0] - DIE_LOT[0]
+*
+*******************************************************************************/
+uint64_t Cy_SysLib_GetUniqueId(void)
+{
+ uint32_t uniqueIdHi;
+ uint32_t uniqueIdLo;
+
+ uniqueIdHi = ((uint32_t) SFLASH->DIE_YEAR << (CY_UNIQUE_ID_DIE_YEAR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ (((uint32_t)SFLASH->DIE_MINOR & 1U) << (CY_UNIQUE_ID_DIE_MINOR_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH->DIE_SORT << (CY_UNIQUE_ID_DIE_SORT_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH->DIE_Y << (CY_UNIQUE_ID_DIE_Y_Pos - CY_UNIQUE_ID_DIE_X_Pos)) |
+ ((uint32_t) SFLASH->DIE_X);
+
+ uniqueIdLo = ((uint32_t) SFLASH->DIE_WAFER << CY_UNIQUE_ID_DIE_WAFER_Pos) |
+ ((uint32_t) SFLASH->DIE_LOT[2U] << CY_UNIQUE_ID_DIE_LOT_2_Pos) |
+ ((uint32_t) SFLASH->DIE_LOT[1U] << CY_UNIQUE_ID_DIE_LOT_1_Pos) |
+ ((uint32_t) SFLASH->DIE_LOT[0U]);
+
+ return (((uint64_t) uniqueIdHi << CY_UNIQUE_ID_DIE_X_Pos) | uniqueIdLo);
+}
+
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysLib_FaultHandler
+****************************************************************************//**
+*
+* This function stores the ARM Cortex registers into a non-zero init area for
+* debugging. This function calls Cy_SysLib_ProcessingFault() after storing all
+* information.
+*
+* \param faultStackAddr The address of the stack pointer, indicates the lowest
+* address in the fault stack frame to be stored.
+* \note This function stores the fault stack frame only for the first occurred
+* fault.
+* \note The PDL doesn't provide an API to analyze the stored register
+* values. The user has to add additional functions for the analysis,
+* if necessary.
+* \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled.
+* By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the
+* Fault Handler.
+* If there is a necessity to save memory or have some specific custom
+* handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as
+* CY_ARM_FAULT_DEBUG_DISABLED. To do this, the following definition should
+* be added to the compiler Command Line (through the project Build
+* Settings): "-D CY_ARM_FAULT_DEBUG=0".
+*
+*******************************************************************************/
+void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr)
+{
+ /* Stores general registers */
+ cy_faultFrame.r0 = faultStackAddr[CY_R0_Pos];
+ cy_faultFrame.r1 = faultStackAddr[CY_R1_Pos];
+ cy_faultFrame.r2 = faultStackAddr[CY_R2_Pos];
+ cy_faultFrame.r3 = faultStackAddr[CY_R3_Pos];
+ cy_faultFrame.r12 = faultStackAddr[CY_R12_Pos];
+ cy_faultFrame.lr = faultStackAddr[CY_LR_Pos];
+ cy_faultFrame.pc = faultStackAddr[CY_PC_Pos];
+ cy_faultFrame.psr = faultStackAddr[CY_PSR_Pos];
+
+ #if (CY_CPU_CORTEX_M4)
+ /* Stores the Configurable Fault Status Register state with the fault cause */
+ cy_faultFrame.cfsr.cfsrReg = SCB->CFSR;
+ /* Stores the Hard Fault Status Register */
+ cy_faultFrame.hfsr.hfsrReg = SCB->HFSR;
+ /* Stores the System Handler Control and State Register */
+ cy_faultFrame.shcsr.shcsrReg = SCB->SHCSR;
+ /* Store MemMange fault address */
+ cy_faultFrame.mmfar = SCB->MMFAR;
+ /* Store Bus fault address */
+ cy_faultFrame.bfar = SCB->BFAR;
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ /* Checks cumulative exception bits for floating-point exceptions */
+ if(0U != (__get_FPSCR() & (CY_FPSCR_IXC_Msk | CY_FPSCR_IDC_Msk)))
+ {
+ cy_faultFrame.s0 = faultStackAddr[CY_S0_Pos];
+ cy_faultFrame.s1 = faultStackAddr[CY_S1_Pos];
+ cy_faultFrame.s2 = faultStackAddr[CY_S2_Pos];
+ cy_faultFrame.s3 = faultStackAddr[CY_S3_Pos];
+ cy_faultFrame.s4 = faultStackAddr[CY_S4_Pos];
+ cy_faultFrame.s5 = faultStackAddr[CY_S5_Pos];
+ cy_faultFrame.s6 = faultStackAddr[CY_S6_Pos];
+ cy_faultFrame.s7 = faultStackAddr[CY_S7_Pos];
+ cy_faultFrame.s8 = faultStackAddr[CY_S8_Pos];
+ cy_faultFrame.s9 = faultStackAddr[CY_S9_Pos];
+ cy_faultFrame.s10 = faultStackAddr[CY_S10_Pos];
+ cy_faultFrame.s11 = faultStackAddr[CY_S11_Pos];
+ cy_faultFrame.s12 = faultStackAddr[CY_S12_Pos];
+ cy_faultFrame.s13 = faultStackAddr[CY_S13_Pos];
+ cy_faultFrame.s14 = faultStackAddr[CY_S14_Pos];
+ cy_faultFrame.s15 = faultStackAddr[CY_S15_Pos];
+ cy_faultFrame.fpscr = faultStackAddr[CY_FPSCR_Pos];
+ }
+ #endif /* __FPU_PRESENT */
+ #endif /* CY_CPU_CORTEX_M4 */
+
+ Cy_SysLib_ProcessingFault();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ProcessingFault
+****************************************************************************//**
+*
+* This function determines how to process the current fault state. By default
+* in case of exception the system will stay in the infinite loop of this
+* function.
+*
+* \note This function has the WEAK option, so the user can redefine the function
+* behavior for a custom processing.
+* For example, the function redefinition could be constructed from fault
+* stack processing and NVIC_SystemReset() function call.
+*
+*******************************************************************************/
+__WEAK void Cy_SysLib_ProcessingFault(void)
+{
+ #if defined(__ARMCC_VERSION)
+ /* Assembly implementation of an infinite loop
+ * is used for the armcc compiler to preserve the call stack.
+ * Otherwise, the compiler destroys the call stack,
+ * because treats this API as a no return function.
+ */
+ Cy_SysLib_AsmInfiniteLoop();
+ #else
+ while(1) {}
+ #endif /* (__ARMCC_VERSION) */
+}
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_SetWaitStates
+****************************************************************************//**
+*
+* Sets the number of clock cycles the cache will wait for, before it samples
+* data coming back from ROM, SRAM, and Flash.
+*
+* Call this function before increasing the HFClk0 High Frequency clock.
+* Call this function optionally after lowering the HFClk0 High Frequency clock
+* in order to improve the CPU performance.
+*
+* Also, call this function before switching the core supply regulator voltage
+* (LDO or SIMO Buck) from 1.1V to 0.9V.
+* Call this function optionally after switching the core supply regulator
+* voltage from 0.9V to 1.1V in order to improve the CPU performance.
+*
+* \param ulpMode The device power mode.
+* true if the device should be switched to the ULP mode (nominal
+* voltage of the core supply regulator should be switched to 0.9V);
+* false if the device should be switched to the LP mode (nominal
+* voltage of the core supply regulator should be switched to 1.1V).
+*
+* \note Refer to the device TRM for the low power modes description.
+*
+* \param clkHfMHz The HFClk0 clock frequency in MHz. Specifying a frequency
+* above the supported maximum will set the wait states as for
+* the maximum frequency.
+*
+*******************************************************************************/
+void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz)
+{
+ uint32_t waitStates;
+ uint32_t freqMax;
+
+ freqMax = ulpMode ? CY_SYSLIB_ULP_SLOW_WS_0_FREQ_MAX : CY_SYSLIB_LP_SLOW_WS_0_FREQ_MAX;
+ waitStates = (clkHfMHz <= freqMax) ? 0UL : 1UL;
+
+ /* ROM */
+ CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates);
+ CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_FAST_WS, 0UL);
+
+ /* SRAM */
+ CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates);
+ CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, 0UL);
+ #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL)
+ CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates);
+ CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_FAST_WS, 0UL);
+ #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */
+ #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL)
+ CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates);
+ CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_FAST_WS, 0UL);
+ #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */
+
+ /* Flash */
+ if (ulpMode)
+ {
+ waitStates = (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX) ? 0UL :
+ ((clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX) ? 1UL : 2UL);
+ }
+ else
+ {
+ waitStates = (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_0_FREQ_MAX) ? 0UL :
+ ((clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_1_FREQ_MAX) ? 1UL :
+ ((clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_2_FREQ_MAX) ? 2UL :
+ ((clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_3_FREQ_MAX) ? 3UL : 4UL)));
+ }
+
+ FLASHC->FLASH_CTL = _CLR_SET_FLD32U(FLASHC->FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates);
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syslib/cy_syslib.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,988 @@
+/***************************************************************************//**
+* \file cy_syslib.h
+* \version 2.0.1
+*
+* Provides an API declaration of the SysLib driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_syslib System Library (SysLib)
+* \{
+* The system libraries provide APIs that can be called in the user application
+* to handle the timing, logical checking or register.
+*
+* The SysLib driver contains a set of different system functions. These functions
+* can be called in the application routine. Major features of the system library:
+* * Delay functions
+* * The register Read/Write macro
+* * Assert and Halt
+* * Assert Classes and Levels
+* * A software reset
+* * Reading the reset cause
+* * An API to invalidate the flash cache and buffer
+* * Data manipulation macro
+* * A variable type definition from MISRA-C which specifies signedness
+* * Cross compiler compatible attributes
+* * Getting a silicon-unique ID API
+* * Setting wait states API
+* * Resetting the backup domain API
+* * APIs to serve Fault handler
+*
+* \section group_syslib_configuration Configuration Considerations
+* <b> Assertion Usage </b> <br />
+* Use the CY_ASSERT() macro to check expressions that must be true as long as the
+* program is running correctly. It is a convenient way to insert sanity checks.
+* The CY_ASSERT() macro is defined in the cy_syslib.h file which is part of
+* the PDL library. The behavior of the macro is as follows: if the expression
+* passed to the macro is false, output an error message that includes the file
+* name and line number, and then halts the CPU. \n
+* In case of fault, the CY_ASSERT() macro calls the Cy_SysLib_AssertFailed() function.
+* This is a weakly linked function. The default implementation stores the file
+* name and line number of the ASSERT into global variables, cy_assertFileName
+* and cy_assertLine . It then calls the Cy_SysLib_Halt() function.
+* \note Firmware can redefine the Cy_SysLib_AssertFailed() function for custom processing.
+*
+* The PDL source code uses this assert mechanism extensively. It is recommended
+* that you enable asserts when debugging firmware. \n
+* <b> Assertion Classes and Levels </b> <br />
+* The PDL defines three assert classes, which correspond to different kinds
+* of parameters. There is a corresponding assert "level" for each class.
+* <table class="doxtable">
+* <tr><th>Class Macro</th><th>Level Macro</th><th>Type of check</th></tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_1</td>
+* <td>CY_ASSERT_L1</td>
+* <td>A parameter that could change between different PSoC devices
+* (e.g. the number of clock paths)</td>
+* </tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_2</td>
+* <td>CY_ASSERT_L2</td>
+* <td>A parameter that has fixed limits such as a counter period</td>
+* </tr>
+* <tr>
+* <td>CY_ASSERT_CLASS_3</td>
+* <td>CY_ASSERT_L3</td>
+* <td>A parameter that is an enum constant</td>
+* </tr>
+* </table>
+* Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL.
+* This is a compiler command line argument, similar to how the DEBUG / NDEBUG
+* macro is passed. \n
+* Enabling any class also enables any lower-numbered class.
+* CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three
+* classes. The following example shows the command-line option to enable all
+* the assert levels:
+* \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode
+* \note The use of special characters, such as spaces, parenthesis, etc. must
+* be protected with quotes.
+*
+* After CY_ASSERT_LEVEL is defined, firmware can use
+* one of the three level macros to make an assertion. For example, if the
+* parameter can vary between devices, firmware uses the L1 macro.
+* \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode
+* If the parameter has bounds, firmware uses L2.
+* \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode
+* If the parameter is an enum, firmware uses L3.
+* \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode
+* Each check uses the appropriate level macro for the kind of parameter being checked.
+* If a particular assert class/level is not enabled, then the assert does nothing.
+*
+* \section group_syslib_more_information More Information
+* Refer to the technical reference manual (TRM).
+*
+* \section group_syslib_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>18.4</td>
+* <td>R</td>
+* <td>Unions shall not be used.</td>
+* <td>The unions are used for CFSR, HFSR and SHCSR Fault Status Registers
+* content access as a word in code and as a structure during debug.</td>
+* </tr>
+* <tr>
+* <td>19.13</td>
+* <td>A</td>
+* <td>The # and ## operators should not be used.</td>
+* <td>The ## preprocessor operator is used in macros to form the field mask.</td>
+* </tr>
+* </table>
+*
+* \section group_syslib_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.0.1</td>
+* <td>Minor documentation edits</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>
+* Added Cy_SysLib_ResetBackupDomain() API implementation. \n
+* Added CY_NOINLINE attribute implementation. \n
+* Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n
+* Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n
+* Optimized Cy_SysLib_SetWaitStates() API implementation.
+* </td>
+* <td>Improvements made based on usability feedback.</td>
+* </tr>
+* <tr>
+* <td>Added Assertion Classes and Levels.</td>
+* <td>For error checking, parameter validation and status returns in the PDL API.</td>
+* </tr>
+* <tr>
+* <td>Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.</td>
+* <td>To store debug information into a non-zero init area for future analysis.</td>
+* </tr>
+* <tr>
+* <td>Removed CY_WEAK attribute implementation.</td>
+* <td>CMSIS __WEAK attribute should be used instead.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_syslib_macros Macros
+* \defgroup group_syslib_functions Functions
+* \defgroup group_syslib_data_structures Data Structures
+* \defgroup group_syslib_enumerated_types Enumerated Types
+*
+*/
+
+#if !defined(_CY_SYSLIB_H_)
+#define _CY_SYSLIB_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
+#if defined( __ICCARM__ )
+ /* Suppress the warning for multiple volatile variables in an expression. */
+ /* This is common for driver's code and the usage is not order-dependent. */
+ #pragma diag_suppress=Pa082
+#endif /* defined( __ICCARM__ ) */
+
+/**
+* \addtogroup group_syslib_macros
+* \{
+*/
+
+/******************************************************************************
+* Macros
+*****************************************************************************/
+
+#define CY_CPU_CORTEX_M0P (__CORTEX_M == 0) /**< CM0+ core CPU Code */
+#define CY_CPU_CORTEX_M4 (__CORTEX_M == 4) /**< CM4 core CPU Code */
+
+/** The macro to disable the Fault Handler */
+#define CY_ARM_FAULT_DEBUG_DISABLED (0U)
+/** The macro to enable the Fault Handler */
+#define CY_ARM_FAULT_DEBUG_ENABLED (1U)
+
+#if !defined(CY_ARM_FAULT_DEBUG)
+ /** The macro defines if the Fault Handler is enabled. Enabled by default. */
+ #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
+#endif /* CY_ARM_FAULT_DEBUG */
+
+/**
+* \defgroup group_syslib_macros_status_codes Status codes
+* \{
+* Function status type codes
+*/
+#define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */
+#define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */
+#define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */
+#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
+#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
+#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
+#define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */
+/** Get the software PDL module ID */
+#define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos))
+#define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */
+/** \} group_syslib_macros_status_codes */
+
+/** \} group_syslib_macros */
+
+/**
+* \addtogroup group_syslib_enumerated_types
+* \{
+*/
+
+/** The SysLib status code structure. */
+typedef enum
+{
+ CY_SYSLIB_SUCCESS = 0x00UL, /**< The success status code */
+ CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< The bad parameter status code */
+ CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The time out status code */
+ CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< The invalid state status code */
+ CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */
+} cy_en_syslib_status_t;
+
+/** \} group_syslib_enumerated_types */
+/**
+* \addtogroup group_syslib_data_structures
+* \{
+*/
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ #if (CY_CPU_CORTEX_M4)
+ /** Configurable Fault Status Register - CFSR */
+ typedef struct
+ {
+ /** MemManage Fault Status Sub-register - MMFSR */
+ uint32_t iaccViol : 1; /**< MemManage Fault - The instruction access violation flag */
+ uint32_t daccViol : 1; /**< MemManage Fault - The data access violation flag */
+ uint32_t reserved1 : 1; /**< Reserved */
+ uint32_t mUnstkErr : 1; /**< MemManage Fault - Unstacking for a return from exception */
+ uint32_t mStkErr : 1; /**< MemManage Fault - MemManage fault on stacking for exception entry */
+ uint32_t mlspErr : 1; /**< MemManage Fault - MemManage fault occurred during floating-point lazy state preservation */
+ uint32_t reserved2 : 1; /**< Reserved */
+ uint32_t mmarValid : 1; /**< MemManage Fault - The MemManage Address register valid flag */
+ /** Bus Fault Status Sub-register - UFSR */
+ uint32_t iBusErr : 1; /**< Bus Fault - The instruction bus error */
+ uint32_t precisErr : 1; /**< Bus Fault - The precise Data bus error */
+ uint32_t imprecisErr : 1; /**< Bus Fault - The imprecise data bus error */
+ uint32_t unstkErr : 1; /**< Bus Fault - Unstacking for an exception return has caused one or more bus faults */
+ uint32_t stkErr : 1; /**< Bus Fault - Stacking for an exception entry has caused one or more bus faults */
+ uint32_t lspErr : 1; /**< Bus Fault - A bus fault occurred during the floating-point lazy state */
+ uint32_t reserved3 : 1; /**< Reserved */
+ uint32_t bfarValid : 1; /**< Bus Fault - The bus fault address register valid flag */
+ /** Usage Fault Status Sub-register - UFSR */
+ uint32_t undefInstr : 1; /**< Usage Fault - An undefined instruction */
+ uint32_t invState : 1; /**< Usage Fault - The invalid state */
+ uint32_t invPC : 1; /**< Usage Fault - An invalid PC */
+ uint32_t noCP : 1; /**< Usage Fault - No coprocessor */
+ uint32_t reserved4 : 4; /**< Reserved */
+ uint32_t unaligned : 1; /**< Usage Fault - Unaligned access */
+ uint32_t divByZero : 1; /**< Usage Fault - Divide by zero */
+ uint32_t reserved5 : 6; /**< Reserved */
+ } cy_stc_fault_cfsr_t;
+
+ /** Hard Fault Status Register - HFSR */
+ typedef struct
+ {
+ uint32_t reserved1 : 1; /**< Reserved. */
+ uint32_t vectTbl : 1; /**< HFSR - Indicates a bus fault on a vector table read during exception processing */
+ uint32_t reserved2 : 28; /**< Reserved. */
+ uint32_t forced : 1; /**< HFSR - Indicates a forced hard fault */
+ uint32_t debugEvt : 1; /**< HFSR - Reserved for the debug use. */
+ } cy_stc_fault_hfsr_t;
+
+ /** System Handler Control and State Register - SHCSR */
+ typedef struct
+ {
+ uint32_t memFaultAct : 1; /**< SHCSR - The MemManage exception active bit, reads as 1 if the exception is active */
+ uint32_t busFaultAct : 1; /**< SHCSR - The BusFault exception active bit, reads as 1 if the exception is active */
+ uint32_t reserved1 : 1; /**< Reserved. */
+ uint32_t usgFaultAct : 1; /**< SHCSR - The UsageFault exception active bit, reads as 1 if the exception is active */
+ uint32_t reserved2 : 3; /**< Reserved. */
+ uint32_t svCallAct : 1; /**< SHCSR - The SVCall active bit, reads as 1 if the SVC call is active */
+ uint32_t monitorAct : 1; /**< SHCSR - The debug monitor active bit, reads as 1 if the debug monitor is active */
+ uint32_t reserved3 : 1; /**< Reserved. */
+ uint32_t pendSVAct : 1; /**< SHCSR - The PendSV exception active bit, reads as 1 if the exception is active */
+ uint32_t sysTickAct : 1; /**< SHCSR - The SysTick exception active bit, reads as 1 if the exception is active */
+ uint32_t usgFaultPended : 1; /**< SHCSR - The UsageFault exception pending bit, reads as 1 if the exception is pending */
+ uint32_t memFaultPended : 1; /**< SHCSR - The MemManage exception pending bit, reads as 1 if the exception is pending */
+ uint32_t busFaultPended : 1; /**< SHCSR - The BusFault exception pending bit, reads as 1 if the exception is pending */
+ uint32_t svCallPended : 1; /**< SHCSR - The SVCall pending bit, reads as 1 if the exception is pending */
+ uint32_t memFaultEna : 1; /**< SHCSR - The MemManage enable bit, set to 1 to enable */
+ uint32_t busFaultEna : 1; /**< SHCSR - The BusFault enable bit, set to 1 to enable */
+ uint32_t usgFaultEna : 1; /**< SHCSR - The UsageFault enable bit, set to 1 to enable */
+ uint32_t reserved4 : 13; /**< Reserved */
+ } cy_stc_fault_shcsr_t;
+ #endif /* CY_CPU_CORTEX_M4 */
+
+ /** The fault configuration structure. */
+ typedef struct
+ {
+ uint32_t r0; /**< R0 register content */
+ uint32_t r1; /**< R1 register content */
+ uint32_t r2; /**< R2 register content */
+ uint32_t r3; /**< R3 register content */
+ uint32_t r12; /**< R12 register content */
+ uint32_t lr; /**< LR register content */
+ uint32_t pc; /**< PC register content */
+ uint32_t psr; /**< PSR register content */
+ #if (CY_CPU_CORTEX_M4)
+ union
+ {
+ uint32_t cfsrReg; /**< CFSR register content as a word */
+ cy_stc_fault_cfsr_t cfsrBits; /**< CFSR register content as a structure */
+ } cfsr;
+ union
+ {
+ uint32_t hfsrReg; /**< HFSR register content as a word */
+ cy_stc_fault_hfsr_t hfsrBits; /**< HFSR register content as a structure */
+ } hfsr;
+ union
+ {
+ uint32_t shcsrReg; /**< SHCSR register content as a word */
+ cy_stc_fault_shcsr_t shcsrBits; /**< SHCSR register content as a structure */
+ } shcsr;
+ uint32_t mmfar; /**< MMFAR register content */
+ uint32_t bfar; /**< BFAR register content */
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ uint32_t s0; /**< FPU S0 register content */
+ uint32_t s1; /**< FPU S1 register content */
+ uint32_t s2; /**< FPU S2 register content */
+ uint32_t s3; /**< FPU S3 register content */
+ uint32_t s4; /**< FPU S4 register content */
+ uint32_t s5; /**< FPU S5 register content */
+ uint32_t s6; /**< FPU S6 register content */
+ uint32_t s7; /**< FPU S7 register content */
+ uint32_t s8; /**< FPU S8 register content */
+ uint32_t s9; /**< FPU S9 register content */
+ uint32_t s10; /**< FPU S10 register content */
+ uint32_t s11; /**< FPU S11 register content */
+ uint32_t s12; /**< FPU S12 register content */
+ uint32_t s13; /**< FPU S13 register content */
+ uint32_t s14; /**< FPU S14 register content */
+ uint32_t s15; /**< FPU S15 register content */
+ uint32_t fpscr; /**< FPU FPSCR register content */
+ #endif /* __FPU_PRESENT */
+ #endif /* CY_CPU_CORTEX_M4 */
+ } cy_stc_fault_frame_t;
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+/** \} group_syslib_data_structures */
+
+/**
+* \addtogroup group_syslib_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_SYSLIB_DRV_VERSION_MAJOR 2
+
+/** The driver minor version */
+#define CY_SYSLIB_DRV_VERSION_MINOR 0
+
+
+/*******************************************************************************
+* Data manipulation defines
+*******************************************************************************/
+
+/** Get the lower 8 bits of a 16-bit value. */
+#define CY_LO8(x) ((uint8_t) ((x) & 0xFFU))
+/** Get the upper 8 bits of a 16-bit value. */
+#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8U))
+
+/** Get the lower 16 bits of a 32-bit value. */
+#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFU))
+/** Get the upper 16 bits of a 32-bit value. */
+#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16U))
+
+/** Swap the byte ordering of a 16-bit value */
+#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8U) | (((x) >> 8U) & 0x00FFU)))
+
+/** Swap the byte ordering of a 32-bit value */
+#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24U) & 0x000000FFU) | (((x) & 0x00FF0000U) >> 8U) | \
+ (((x) & 0x0000FF00U) << 8U) | ((x) << 24U)))
+
+/** Swap the byte ordering of a 64-bit value */
+#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32U) | \
+ CY_SWAP_ENDIAN32((uint32_t)((x) >> 32U))))
+
+
+/*******************************************************************************
+* Memory model definitions
+*******************************************************************************/
+#if defined(__ARMCC_VERSION)
+ /** To create cross compiler compatible code, use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN
+ * attributes at the first place of declaration/definition.
+ * For example: CY_NOINIT uint32_t noinitVar;
+ */
+ #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
+ #define CY_SECTION(name) __attribute__ ((section(name)))
+ #define CY_UNUSED __attribute__ ((unused))
+ #define CY_NOINLINE __attribute__ ((noinline))
+ /* Specifies the minimum alignment (in bytes) for variables of the specified type. */
+ #define CY_ALIGN(align) __ALIGNED(align)
+#elif defined (__GNUC__)
+ #define CY_NOINIT __attribute__ ((section(".noinit")))
+ #define CY_SECTION(name) __attribute__ ((section(name)))
+ #define CY_UNUSED __attribute__ ((unused))
+ #define CY_NOINLINE __attribute__ ((noinline))
+ #define CY_ALIGN(align) __ALIGNED(align)
+#elif defined (__ICCARM__)
+ #define CY_PRAGMA(x) _Pragma(#x)
+ #define CY_NOINIT __no_init
+ #define CY_SECTION(name) CY_PRAGMA(location = name)
+ #define CY_UNUSED
+ #define CY_NOINLINE CY_PRAGMA(optimize = no_inline)
+ #if (__VER__ < 8010001)
+ #define CY_ALIGN(align) CY_PRAGMA(data_alignment = align)
+ #else
+ #define CY_ALIGN(align) __ALIGNED(align)
+ #endif /* (__VER__ < 8010001) */
+#else
+ #error "An unsupported toolchain"
+#endif /* (__ARMCC_VERSION) */
+
+typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */
+#if defined (__ICCARM__)
+ typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem;
+#endif /* defined (__ICCARM__) */
+
+/* MISRA rule 6.3 recommends using specific-length typedef for the basic
+ * numerical types of signed and unsigned variants of char, float, and double.
+ */
+typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */
+typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */
+typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */
+
+#if !defined(NDEBUG)
+ /** The max size of the file name which stores the ASSERT location */
+ #define CY_MAX_FILE_NAME_SIZE (24U)
+ extern CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE]; /**< The assert buffer */
+ extern CY_NOINIT uint32_t cy_assertLine; /**< The assert line value */
+#endif /* NDEBUG */
+
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
+ #define CY_R0_Pos (0U) /**< The position of the R0 content in a fault structure */
+ #define CY_R1_Pos (1U) /**< The position of the R1 content in a fault structure */
+ #define CY_R2_Pos (2U) /**< The position of the R2 content in a fault structure */
+ #define CY_R3_Pos (3U) /**< The position of the R3 content in a fault structure */
+ #define CY_R12_Pos (4U) /**< The position of the R12 content in a fault structure */
+ #define CY_LR_Pos (5U) /**< The position of the LR content in a fault structure */
+ #define CY_PC_Pos (6U) /**< The position of the PC content in a fault structure */
+ #define CY_PSR_Pos (7U) /**< The position of the PSR content in a fault structure */
+ #if (CY_CPU_CORTEX_M4) && ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)))
+ #define CY_FPSCR_IXC_Msk (0x00000010U) /**< The cumulative exception bit for floating-point exceptions */
+ #define CY_FPSCR_IDC_Msk (0x00000080U) /**< The cumulative exception bit for floating-point exceptions */
+ #define CY_S0_Pos (8U) /**< The position of the FPU S0 content in a fault structure */
+ #define CY_S1_Pos (9U) /**< The position of the FPU S1 content in a fault structure */
+ #define CY_S2_Pos (10U) /**< The position of the FPU S2 content in a fault structure */
+ #define CY_S3_Pos (11U) /**< The position of the FPU S3 content in a fault structure */
+ #define CY_S4_Pos (12U) /**< The position of the FPU S4 content in a fault structure */
+ #define CY_S5_Pos (13U) /**< The position of the FPU S5 content in a fault structure */
+ #define CY_S6_Pos (14U) /**< The position of the FPU S6 content in a fault structure */
+ #define CY_S7_Pos (15U) /**< The position of the FPU S7 content in a fault structure */
+ #define CY_S8_Pos (16U) /**< The position of the FPU S8 content in a fault structure */
+ #define CY_S9_Pos (17U) /**< The position of the FPU S9 content in a fault structure */
+ #define CY_S10_Pos (18U) /**< The position of the FPU S10 content in a fault structure */
+ #define CY_S11_Pos (19U) /**< The position of the FPU S11 content in a fault structure */
+ #define CY_S12_Pos (20U) /**< The position of the FPU S12 content in a fault structure */
+ #define CY_S13_Pos (21U) /**< The position of the FPU S13 content in a fault structure */
+ #define CY_S14_Pos (22U) /**< The position of the FPU S14 content in a fault structure */
+ #define CY_S15_Pos (23U) /**< The position of the FPU S15 content in a fault structure */
+ #define CY_FPSCR_Pos (24U) /**< The position of the FPU FPSCR content in a fault structure */
+ #endif /* CY_CPU_CORTEX_M4 && __FPU_PRESENT */
+
+ extern CY_NOINIT cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG8(addr)
+****************************************************************************//**
+*
+* Reads the 8-bit value from the specified address. This function can't be
+* used to access the Core register, otherwise a fault occurs.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG8(addr, value)
+****************************************************************************//**
+*
+* Writes an 8-bit value to the specified address. This function can't be
+* used to access the Core register, otherwise a fault occurs.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value))
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG16(addr)
+****************************************************************************//**
+*
+* Reads the 16-bit value from the specified address.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG16(addr, value)
+****************************************************************************//**
+*
+* Writes the 16-bit value to the specified address.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value))
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG24(addr)
+****************************************************************************//**
+*
+* Reads the 24-bit value from the specified address.
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG24(addr) (uint32_t) ((*((const volatile uint8_t *)(addr))) | \
+ (uint32_t) ((*((const volatile uint8_t *)(addr) + 1)) << 8U) | \
+ (uint32_t) ((*((const volatile uint8_t *)(addr) + 2)) << 16U))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG24(addr, value)
+****************************************************************************//**
+*
+* Writes the 24-bit value to the specified address.
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG24(addr, value) do \
+ { \
+ (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \
+ (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8U); \
+ (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16U); \
+ } \
+ while(0)
+
+
+/*******************************************************************************
+* Macro Name: CY_GET_REG32(addr)
+****************************************************************************//**
+*
+* Reads the 32-bit value from the specified register. The address is the little
+* endian order (LSB in lowest address).
+*
+* \param addr The register address.
+*
+* \return The read value.
+*
+*******************************************************************************/
+#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr)))
+
+
+/*******************************************************************************
+* Macro Name: CY_SET_REG32(addr, value)
+****************************************************************************//**
+*
+* Writes the 32-bit value to the specified register. The address is the little
+* endian order (LSB in lowest address).
+*
+* \param addr The register address.
+*
+* \param value The value to write.
+*
+*******************************************************************************/
+#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value))
+
+
+/**
+* \defgroup group_syslib_macros_assert Assert Classes and Levels
+* \{
+* Defines for the Assert Classes and Levels
+*/
+
+/**
+* Class 1 - The highest class, safety-critical functions which rely on parameters that could be
+* changed between different PSoC devices
+*/
+#define CY_ASSERT_CLASS_1 (1U)
+
+/** Class 2 - Functions that have fixed limits such as counter periods (16-bits/32-bits etc.) */
+#define CY_ASSERT_CLASS_2 (2U)
+
+/** Class 3 - Functions that accept enums as constant parameters */
+#define CY_ASSERT_CLASS_3 (3U)
+
+#ifndef CY_ASSERT_LEVEL
+ /** The user-definable assert level from compiler command-line argument (similarly to DEBUG / NDEBUG) */
+ #define CY_ASSERT_LEVEL CY_ASSERT_CLASS_3
+#endif /* CY_ASSERT_LEVEL */
+
+#if (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1)
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) do{} while(0) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) do{} while(0) /**< Assert Level 3 */
+#elif (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_2)
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) do{} while(0) /**< Assert Level 3 */
+#else /* Default is Level 3 */
+ #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
+ #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
+ #define CY_ASSERT_L3(x) CY_ASSERT(x) /**< Assert Level 3 */
+#endif /* CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1 */
+
+/** \} group_syslib_macros_assert */
+
+
+/*******************************************************************************
+* Macro Name: CY_ASSERT
+****************************************************************************//**
+*
+* The macro that evaluates the expression and, if it is false (evaluates to 0),
+* the processor is halted. Cy_SysLib_AssertFailed() is called when the logical
+* expression is false to store the ASSERT location and halt the processor.
+*
+* \param x The logical expression. Asserts if false.
+* \note This macro is evaluated unless NDEBUG is not defined.
+* If NDEBUG is defined, just empty do while cycle is generated for this
+* macro for the sake of consistency and to avoid MISRA violation.
+* NDEBUG is defined by default for a Release build setting and not defined
+* for a Debug build setting.
+*
+*******************************************************************************/
+#if !defined(NDEBUG)
+ #define CY_ASSERT(x) do \
+ { \
+ if(!(x)) \
+ { \
+ Cy_SysLib_AssertFailed((char_t *) __FILE__, (uint32_t) __LINE__); \
+ } \
+ } while(0)
+#else
+ #define CY_ASSERT(x) do \
+ { \
+ } while(0)
+#endif /* !defined(NDEBUG) */
+
+
+/*******************************************************************************
+* Macro Name: _CLR_SET_FLD32U
+****************************************************************************//**
+*
+* The macro for setting a register with a name field and value for providing
+* get-clear-modify-write operations.
+* Returns a resulting value to be assigned to the register.
+*
+*******************************************************************************/
+#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value)))
+
+
+/*******************************************************************************
+* Macro Name: _BOOL2FLD
+****************************************************************************//**
+*
+* Returns a field mask if the value is not false.
+* Returns 0, if the value is false.
+*
+*******************************************************************************/
+#define _BOOL2FLD(field, value) (((value) != false) ? (field ## _Msk) : 0UL)
+
+
+/*******************************************************************************
+* Macro Name: _FLD2BOOL
+****************************************************************************//**
+*
+* Returns true, if the value includes the field mask.
+* Returns false, if the value doesn't include the field mask.
+*
+*******************************************************************************/
+#define _FLD2BOOL(field, value) (((value) & (field ## _Msk)) != 0UL)
+
+
+/******************************************************************************
+* Constants
+*****************************************************************************/
+/** Defines a 32-kHz clock delay */
+#define CY_DELAY_MS_OVERFLOW (0x8000U)
+
+/**
+* \defgroup group_syslib_macros_reset_cause Reset cause
+* \{
+* Define RESET_CAUSE mask values
+*/
+/** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_HWWDT (0x0001U)
+/** The fault logging system requested a reset from its Active logic. */
+#define CY_SYSLIB_RESET_ACT_FAULT (0x0002U)
+/** The fault logging system requested a reset from its Deep-Sleep logic. */
+#define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U)
+/** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */
+#define CY_SYSLIB_RESET_SOFT (0x0010U)
+/** The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT0 (0x0020U)
+/** The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT1 (0x0040U)
+/** The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT2 (0x0080U)
+/** The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. */
+#define CY_SYSLIB_RESET_SWWDT3 (0x0100U)
+/** The reset has occurred on a wakeup from Hibernate power mode. */
+#define CY_SYSLIB_RESET_HIB_WAKEUP (0x40000UL)
+#if (SRSS_WCOCSV_PRESENT != 0U)
+ /** The clock supervision logic requested a reset due to the loss of a watch-crystal clock. */
+ #define CY_SYSLIB_RESET_CSV_WCO_LOSS (0x0008U)
+ /** The clock supervision logic requested a reset due to the loss of a high-frequency clock. */
+ #define CY_SYSLIB_RESET_HFCLK_LOSS (0x10000UL)
+ /** The clock supervision logic requested a reset due to the frequency error of a high-frequency clock. */
+ #define CY_SYSLIB_RESET_HFCLK_ERR (0x20000UL)
+#endif /* (SRSS_WCOCSV_PRESENT != 0U) */
+
+/** \} group_syslib_macros_reset_cause */
+
+/** Bit[31:24] Opcode = 0x1B (SoftReset)
+ * Bit[7:1] Type = 1 (Only CM4 reset)
+ */
+#define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
+
+/**
+* \defgroup group_syslib_macros_unique_id Unique ID
+* \{
+* Unique ID fields positions
+*/
+#define CY_UNIQUE_ID_DIE_YEAR_Pos (57U) /**< The position of the DIE_YEAR field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_MINOR_Pos (56U) /**< The position of the DIE_MINOR field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_SORT_Pos (48U) /**< The position of the DIE_SORT field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_Y_Pos (40U) /**< The position of the DIE_Y field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_X_Pos (32U) /**< The position of the DIE_X field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_WAFER_Pos (24U) /**< The position of the DIE_WAFER field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_2_Pos (16U) /**< The position of the DIE_LOT_2 field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_1_Pos (8U) /**< The position of the DIE_LOT_1 field in the silicon Unique ID */
+#define CY_UNIQUE_ID_DIE_LOT_0_Pos (0U) /**< The position of the DIE_LOT_0 field in the silicon Unique ID */
+
+/** \} group_syslib_macros_unique_id */
+
+/** \} group_syslib_macros */
+
+/******************************************************************************
+* Function prototypes
+******************************************************************************/
+
+/**
+* \addtogroup group_syslib_functions
+* \{
+*/
+
+void Cy_SysLib_Delay(uint32_t milliseconds);
+void Cy_SysLib_DelayUs(uint16_t microseconds);
+/** Delays for the specified number of cycles.
+ * The function is implemented in the assembler for each supported compiler.
+ * \param cycles The number of cycles to delay.
+ */
+void Cy_SysLib_DelayCycles(uint32_t cycles);
+__NO_RETURN void Cy_SysLib_Halt(uint32_t reason);
+#if !defined(NDEBUG) || defined(CY_DOXYGEN)
+ void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line);
+#endif /* !defined(NDEBUG) || defined(CY_DOXYGEN) */
+void Cy_SysLib_ClearFlashCacheAndBuffer(void);
+cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void);
+uint32_t Cy_SysLib_GetResetReason(void);
+#if (SRSS_WCOCSV_PRESENT != 0U) || defined(CY_DOXYGEN)
+ uint32_t Cy_SysLib_GetNumHfclkResetCause(void);
+#endif /* (SRSS_WCOCSV_PRESENT != 0U) || defined(CY_DOXYGEN) */
+void Cy_SysLib_ClearResetReason(void);
+uint64_t Cy_SysLib_GetUniqueId(void);
+#if (CY_CPU_CORTEX_M0P)
+ void Cy_SysLib_SoftResetCM4(void);
+#endif /* CY_CPU_CORTEX_M0P */
+#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
+ void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr);
+ void Cy_SysLib_ProcessingFault(void);
+#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
+void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_EnterCriticalSection
+****************************************************************************//**
+*
+* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
+* indicating whether the interrupts were previously enabled.
+*
+* \return Returns the current interrupt status. Returns 0 if the interrupts
+* were previously enabled or 1 if the interrupts were previously
+* disabled.
+*
+* \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
+* enable bit with interrupts still enabled.
+*
+*******************************************************************************/
+uint32_t Cy_SysLib_EnterCriticalSection(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_ExitCriticalSection
+****************************************************************************//**
+*
+* Re-enables the interrupts if they were enabled before
+* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
+* returned from \ref Cy_SysLib_EnterCriticalSection().
+*
+* \param savedIntrStatus Puts the saved interrupts status returned by
+* the \ref Cy_SysLib_EnterCriticalSection().
+*
+*******************************************************************************/
+void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus);
+
+
+/** \cond INTERNAL */
+#define CY_SYSLIB_DEVICE_REV_0A (0x21U) /**< The device TO *A Revision ID */
+#define CY_SYSLIB_DEVICE_PSOC6ABLE2 (0x100U) /**< The PSoC6 BLE2 device Family ID */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetDeviceRevision
+****************************************************************************//**
+*
+* This function returns a device Revision ID.
+*
+* \return A device Revision ID.
+*
+*******************************************************************************/
+__STATIC_INLINE uint8_t Cy_SysLib_GetDeviceRevision(void)
+{
+ return ((SFLASH->SI_REVISION_ID == 0UL) ? CY_SYSLIB_DEVICE_REV_0A : SFLASH->SI_REVISION_ID);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysLib_GetDevice
+****************************************************************************//**
+*
+* This function returns a device Family ID.
+*
+* \return A device Family ID.
+*
+*******************************************************************************/
+__STATIC_INLINE uint16_t Cy_SysLib_GetDevice(void)
+{
+ return ((SFLASH->FAMILY_ID == 0UL) ? CY_SYSLIB_DEVICE_PSOC6ABLE2 : SFLASH->FAMILY_ID);
+}
+
+
+typedef uint32_t cy_status;
+/** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */
+typedef uint32_t cystatus;
+typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */
+typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */
+typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */
+typedef int8_t int8; /**< Alias to int8_t for backward compatibility */
+typedef int16_t int16; /**< Alias to int16_t for backward compatibility */
+typedef int32_t int32; /**< Alias to int32_t for backward compatibility */
+typedef float float32; /**< Alias to float for backward compatibility */
+typedef double float64; /**< Alias to double for backward compatibility */
+typedef int64_t int64; /**< Alias to int64_t for backward compatibility */
+typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */
+/* Signed or unsigned depending on the compiler selection */
+typedef char char8; /**< Alias to char for backward compatibility */
+typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */
+typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */
+typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */
+
+/** The ARM 32-bit Return error / status code for backward compatibility.
+* Do not use them in your code.
+*/
+#define CY_RET_SUCCESS (0x00U) /* Successful */
+#define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */
+#define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */
+#define CY_RET_MEMORY (0x03U) /* A memory-related failure */
+#define CY_RET_LOCKED (0x04U) /* A resource lock failure */
+#define CY_RET_EMPTY (0x05U) /* No more objects available */
+#define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
+#define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
+#define CY_RET_FINISHED (0x08U) /* Operation is completed */
+#define CY_RET_CANCELED (0x09U) /* Operation is canceled */
+#define CY_RET_TIMEOUT (0x10U) /* Operation timed out */
+#define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
+#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */
+
+/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components.
+* Do not use them in your code.
+*/
+#define CYRET_SUCCESS (0x00U) /* Successful */
+#define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */
+#define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */
+#define CYRET_MEMORY (0x03U) /* A memory-related failure */
+#define CYRET_LOCKED (0x04U) /* A resource lock failure */
+#define CYRET_EMPTY (0x05U) /* No more objects available */
+#define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
+#define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
+#define CYRET_FINISHED (0x08U) /* Operation is completed */
+#define CYRET_CANCELED (0x09U) /* Operation is canceled */
+#define CYRET_TIMEOUT (0x10U) /* Operation timed out */
+#define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
+#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */
+
+/** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
+typedef void (* cyisraddress)(void);
+#if defined (__ICCARM__)
+ /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
+ typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
+#endif /* defined (__ICCARM__) */
+
+/** The backward compatibility define for the CyDelay() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelay Cy_SysLib_Delay
+/** The backward compatibility define for the CyDelayUs() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelayUs Cy_SysLib_DelayUs
+/** The backward compatibility define for the CyDelayCycles() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyDelayCycles Cy_SysLib_DelayCycles
+/** The backward compatibility define for the CyEnterCriticalSection() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyEnterCriticalSection() ((uint8_t) Cy_SysLib_EnterCriticalSection())
+/** The backward compatibility define for the CyExitCriticalSection() API for the UDB components.
+* Do not use it in your code.
+*/
+#define CyExitCriticalSection(x) (Cy_SysLib_ExitCriticalSection((uint32_t) (x)))
+/** \endcond */
+
+/** \} group_syslib_functions */
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
+
+#endif /* _CY_SYSLIB_H_ */
+
+/** \} group_syslib */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syspm/cy_syspm.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2652 @@
+/***************************************************************************//**
+* \file cy_syspm.c
+* \version 2.10
+*
+* This driver provides the source code for API power management.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "cy_syspm.h"
+
+/*******************************************************************************
+* Internal Variables
+*******************************************************************************/
+static cy_stc_syspm_callback_t* callbackRoot = NULL;
+static cy_stc_syspm_callback_t* callbackListLast = NULL;
+static uint32_t curRegisteredCallbacks = 0U;
+
+#if(0u != CY_CPU_CORTEX_M4)
+ static bool wasEventSent = false;
+#endif /* (0u != CY_CPU_CORTEX_M4) */
+
+
+/*******************************************************************************
+* Internal Functions
+*******************************************************************************/
+#ifdef CY_IP_MXUDB
+ static void SaveRegisters(cy_stc_syspm_backup_regs_t *regs);
+ static void RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs);
+#endif /* CY_IP_MXUDB */
+
+static void EnterDeepSleep(cy_en_syspm_waitfor_t waitFor);
+
+static void SetReadMarginTrimUlp(void);
+static void SetReadMarginTrimLp(void);
+static void SetWriteAssistTrimUlp(void);
+static void SetWriteAssistTrimLp(void);
+
+static void SetVoltageBitForFlash(void);
+static void ClearVoltageBitForFlash(void);
+
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+ static void Cy_EnterDeepSleep(cy_en_syspm_waitfor_t waitFor);
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+
+
+/*******************************************************************************
+* Internal Defines
+*******************************************************************************/
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+
+ /** The internal define for clock divider */
+ #define SYSPM_CLK_DIVIDER (9U)
+
+ /* Mask for the fast clock divider value */
+ #define SYSPM_FAST_CLK_DIV_Msk (0xFF000000UL)
+
+ /* Position for the fast clock divider value */
+ #define SYSPM_FAST_CLK_DIV_Pos (24UL)
+
+ /* Mask for the slow clock divider value */
+ #define SYSPM_SLOW_CLK_DIV_Msk (0x00FF0000UL)
+
+ /* Position for the slow clock divider value */
+ #define SYSPM_SLOW_CLK_DIV_Pos (16UL)
+
+ #if(0u != CY_CPU_CORTEX_M4)
+ #define CUR_CORE_DP_MASK (0x01UL)
+ #define OTHER_CORE_DP_MASK (0x02UL)
+ #else
+ #define CUR_CORE_DP_MASK (0x02UL)
+ #define OTHER_CORE_DP_MASK (0x01UL)
+ #endif
+
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+
+/* Redefine for sflash region */
+#define DELAY_DONE_FLAG FLASHC
+
+/* Slow control register */
+#define TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40260108U)
+
+/* Slow output register */
+#define CLK_OUTPUT_SLOW_REG (*(volatile uint32_t *) 0x40260518U)
+
+/* Fast control register */
+#define TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U)
+
+/* Counter register */
+#define CLK_CAL_CNT1_REG (*(volatile uint32_t *) 0x4026051CU)
+
+#ifdef CY_IP_MXUDB
+
+ /* The UDB placement on MMIO slave level */
+ #define PERI_UDB_SLAVE_ENABLED ((uint32_t) (1UL << CY_MMIO_UDB_SLAVE_NR))
+#endif /* CY_IP_MXUDB */
+
+/** The definition for the delay of the LDO after its output
+* voltage is changed
+*/
+#define LDO_STABILIZATION_DELAY_US (9U)
+
+/* Define for the IPC structure used by syspm driver */
+#define SYSPM_IPC_STC IPC_STRUCT7
+
+/** Define to indicate that a 10 us delay is needed */
+#define NEED_DELAY (0x0U)
+
+/** Define to set the IMO to count a 10 us delay after exiting Deep Sleep */
+#define TST_DDFT_SLOW_CTL_MASK (0x00001F1EU)
+
+/** Slow output register */
+#define CLK_OUTPUT_SLOW_MASK (0x06U)
+
+/** Slow control register */
+#define TST_DDFT_FAST_CTL_MASK (62U)
+
+/** Load value for the timer to count delay after exiting Deep Sleep */
+#define IMO_10US_DELAY (68U)
+
+/** Define to indicate that the clock is finished counting */
+#define CLK_CAL_CNT1_DONE ((uint32_t) ((uint32_t) 1U << CLK_CAL_CNT1_DONE_POS))
+
+/** Define to indicate that the clock is finished counting */
+#define CLK_CAL_CNT1_DONE_POS (31U)
+
+/** Define to indicate that a 10 us delay was done after exiting Deep Sleep */
+#define DELAY_DONE (0xAAAAAAAAU)
+
+/** Define for transitional 0.95 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_0_95V (0x0BU)
+
+/** Define for transitional 1.1 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_1_1V (0x17U)
+
+/** Define for transitional 1.15 V for the LDO regulator */
+#define LDO_OUT_VOLTAGE_1_15V (0x1BU)
+
+#if(0u != SRSS_BUCKCTL_PRESENT)
+
+ /** Define for transitional 0.95 V for buck regulator */
+ #define BUCK_OUT1_VOLTAGE_0_95V (3U)
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+
+/* These defines will be removed and SFLASH registers used instead */
+
+/** Trim define for ROM in LP mode */
+#define CPUSS_TRIM_ROM_LP (0x00000013U)
+
+/** Trim define for RAM in LP mode */
+#define CPUSS_TRIM_RAM_LP (0x00004013U)
+
+/** Trim define for ROM in ULP mode */
+#define CPUSS_TRIM_ROM_ULP (0x00000012U)
+
+/** Trim define for RAM in ULP mode */
+#define CPUSS_TRIM_RAM_ULP (0x00006012U)
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ReadStatus
+****************************************************************************//**
+*
+* Reads the status of the core(s).
+*
+* \return The current power mode. See \ref group_syspm_return_status.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_ReadStatus
+*
+*******************************************************************************/
+uint32_t Cy_SysPm_ReadStatus(void)
+{
+ uint32_t interruptState;
+ uint32_t pmStatus = 0U;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+#if(0u != CY_IP_M4CPUSS)
+
+ /* Check whether CM4 is in Deep Sleep mode*/
+ if((0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS->CM4_STATUS)) &&
+ (0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPDEEP, CPUSS->CM4_STATUS)))
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_DEEPSLEEP;
+ }
+ /* Check whether CM4 is in Sleep mode*/
+ else if(0U != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS->CM4_STATUS))
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_SLEEP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM4_ACTIVE;
+ }
+#endif /* (0u != CY_IP_M4CPUSS) */
+
+ /* Check whether CM0p is in Deep Sleep mode*/
+ if((0U != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS->CM0_STATUS)) &&
+ (0U != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPDEEP, CPUSS->CM0_STATUS)))
+ {
+ pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_DEEPSLEEP;
+ }
+ /* Check whether CM0p is in Sleep mode*/
+ else if (0U != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS->CM0_STATUS))
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM0_SLEEP;
+ }
+ else
+ {
+ pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE;
+ }
+
+ /* Check whether the device is in Low Power mode by reading
+ * the Active Reference status
+ */
+ if(0U != (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL)))
+ {
+ pmStatus |= CY_SYSPM_STATUS_SYSTEM_LOWPOWER;
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ return(pmStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Sleep
+****************************************************************************//**
+*
+* Sets a CPU core to Sleep mode.
+*
+* Puts the core into Sleep power mode, if none of callback functions were
+* registered.
+*
+* For more details about switching into Sleep power mode and debug,
+* refer to the device TRM.
+*
+* If at least one callback function with the CY_SYSPM_SLEEP type was registered,
+* the next algorithm is executed:
+* Prior to entering Sleep mode, all callback functions of the CY_SYSPM_SLEEP
+* type with the CY_SYSPM_CHECK_READY parameter are called. This allows the driver
+* to signal whether it is ready to enter the Low Power mode. If any of the
+* callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY parameter
+* returns CY_SYSPM_FAIL, the remaining callback of the CY_SYSPM_SLEEP type with
+* the CY_SYSPM_CHECK_READY parameter calls are skipped.
+* After CY_SYSPM_FAIL, all the CY_SYSPM_SLEEP callbacks with
+* the CY_SYSPM_CHECK_FAIL parameter are executed. These are the callbacks
+* of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY
+* parameter that were previously executed before getting CY_SYSPM_FAIL.
+* The Sleep mode is not entered and the Cy_SysPm_Sleep() function returns
+* CY_SYSPM_FAIL.
+*
+* If all of the callbacks of the CY_SYSPM_SLEEP type with the
+* CY_SYSPM_CHECK_READY parameter calls return CY_SYSPM_SUCCESS, then all
+* callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_FAIL parameters
+* calls are skipped. Also, all callbacks of the CY_SYSPM_SLEEP type and
+* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed, allowing the
+* peripherals to prepare for Sleep. The CPU then enters Sleep mode.
+* This is a CPU-centric power mode. This means that the CPU has entered Sleep
+* mode and its main clock is removed. It is identical to Active from a
+* peripheral point of view. Any enabled interrupt can cause a wakeup from
+* Sleep mode.
+*
+* After a wakeup from Sleep, all of the registered callbacks of the
+* CY_SYSPM_SLEEP type and with the CY_SYSPM_AFTER_TRANSITION parameter are
+* executed to return the peripherals to Active operation. The Cy_SysPm_Sleep()
+* function returns CY_SYSPM_SUCCESS.
+* No callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_BEFORE_TRANSITION
+* parameter or callbacks of the CY_SYSPM_SLEEP type and
+* CY_SYSPM_AFTER_TRANSITION parameter callbacks are executed if Sleep mode
+* is not entered.
+*
+* \note The last callback that returned CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL.
+*
+* The return values from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* \ref cy_en_syspm_callback_mode_t, except the CY_SYSPM_CHECK_READY, are ignored
+*
+* \param waitFor Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \sideeffect
+* This function clears the Event Register of CM4 core after wakeup from WFE.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Sleep
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_Sleep(cy_en_syspm_waitfor_t waitFor)
+{
+ uint32_t interruptState;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
+
+ /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */
+ if(0U != curRegisteredCallbacks)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The device (core) can switch into the sleep power mode only when
+ * all executed registered callback functions with the CY_SYSPM_CHECK_READY
+ * parameter returned CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with
+ * CY_SYSPM_BEFORE_TRANSITION parameter. The return value should be
+ * CY_SYSPM_SUCCESS.
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* The CPU enters the Sleep power mode upon execution of WFI/WFE */
+ SCB->SCR = _CLR_SET_FLD32U((SCB->SCR), SCB_SCR_SLEEPDEEP, 0U);
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+
+ #if(0u != CY_CPU_CORTEX_M4)
+
+ /* For the CM4 core, the WFE instructions are called twice.
+ * The second WFE call clears the Event register of CM4 core.
+ * Cypress ID #279077.
+ */
+ if(wasEventSent)
+ {
+ __WFE();
+ }
+
+ wasEventSent = true;
+ #endif /* (0u != CY_CPU_CORTEX_M4) */
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_AFTER_TRANSITION parameter. The return value should be
+ * CY_SYSPM_SUCCESS.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_DeepSleep
+****************************************************************************//**
+*
+* Sets a CPU core to the Deep Sleep mode.
+*
+* Puts the core into the Deep Sleep power mode. Prior to entering the Deep Sleep
+* mode, all callbacks of the CY_SYSPM_DEEPSLEEP type with the
+* CY_SYSPM_CHECK_READY parameter registered callbacks are called, allowing the
+* driver to signal whether it is ready to enter the power mode. If any
+* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter call returns
+* CY_SYSPM_FAIL, the remaining callback CY_SYSPM_DEEPSLEEP type with the
+* CY_SYSPM_CHECK_READY parameter calls are skipped. After a CY_SYSPM_FAIL, all
+* of the callbacks of the CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_FAIL
+* parameter are executed that correspond to the callbacks with
+* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_READY parameter calls that
+* occurred up to the point of failure.
+* The Deep Sleep mode is not entered and the Cy_SysPm_DeepSleep() function
+* returns CY_SYSPM_FAIL.
+*
+* If all callbacks of the CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY
+* parameter calls return CY_SYSPM_SUCCESS, then all callbacks of the
+* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_FAIL parameter calls are
+* skipped and all callbacks of the CY_SYSPM_DEEPSLEEP type with the
+* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed, allowing the
+* peripherals to prepare for Deep Sleep.
+* The Deep Sleep mode is then entered. Any enabled interrupt can cause a wakeup
+* from the Deep Sleep mode.
+*
+* \note The last callback which returned CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL.
+*
+* The return values from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* If the firmware attempts to enter this mode before the system is ready (that
+* is, when PWR_CONTROL.LPM_READY = 0), then the device will go into the (LP)
+* Sleep mode instead and automatically enter Deep Sleep mode when the
+* system is ready.
+*
+* The system puts the whole device into Deep Sleep mode when all the
+* processor(s) is (are) in Deep Sleep, there are no busy peripherals, the
+* debugger is not active, and the Deep Sleep circuits are
+* ready (PWR_CONTROL.LPM_READY=1).
+*
+* The peripherals that do not need a clock or that receive a clock from their
+* external interface (e.g. I2C/SPI) continue operating. All circuits using the
+* current from Vccdpslp supply are under the current limitation, which is
+* controlled by the Deep Sleep regulator.
+*
+* Wakeup occurs when an interrupt asserts from a Deep Sleep active peripheral.
+* For more details, see the corresponding peripheral's datasheet.
+*
+* \note
+* For multi-core devices, the second core, which did not participate in
+* device wakeup, continues to execute the Deep Sleep instructions. Any Deep Sleep
+* capable interrupt routed to this core can wake it.
+*
+* For more details about switching into the Deep Sleep power mode and debug,
+* refer to the device TRM.
+*
+* A normal wakeup from the Deep Sleep power mode returns to either LPActive or
+* Active, depending on the previous state and programmed behavior for the
+* particular wakeup interrupt.
+*
+* After wakeup from Deep Sleep, all of the registered callbacks with
+* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_AFTER_TRANSITION are executed to return
+* peripherals to Active operation. The Cy_SysPm_DeepSleep() function returns
+* CY_SYSPM_SUCCESS. No callbacks are executed with CY_SYSPM_DEEPSLEEP type with
+* CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter, if
+* Deep Sleep mode was not entered.
+*
+* \param waitFor Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+* \sideeffect
+* This side effect is applicable only for devices with UDB IP block available.
+* You can obtain unpredictable behavior of the UDB block after the device wakeup
+* from Deep Sleep.
+* Unpredictable behavior scenario:
+* * The first core saves non-retained UDB configuration registers and goes into
+* the Deep Sleep (Cy_SysPm_DeepSleep() function).
+* * These non-retained UDB configuration registers are modified in runtime by
+* another (second) active core.
+* * The second core saves non-retained UDB configuration registers and goes into
+* the Deep Sleep (Cy_SysPm_DeepSleep() function).
+* These conditions save different values of the non-retained UDB configuration
+* registers. The prevented scenario: on the first core wakeup, these registers
+* are restored by the values saved on the first core. After the second core
+* wakeup, these registers are "reconfigured" by the values saved on the second
+* core.
+* Be aware of this situation.
+*
+* \sideeffect
+* This function clears the Event Register of CM4 core after wakeup from WFE.
+*
+* \sideeffect
+* This side effect is applicable only for rev-08 of the CY8CKIT-062.
+* The function changes the slow and fast clock dividers to
+* SYSPM_CLK_DIVIDER right before entering into Deep Sleep and restores
+* these dividers after wakeup.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \note
+* The FLL/PLL are not restored right before the CPU starts executing the
+* instructions after Deep Sleep. This can affect the peripheral which is
+* driven by PLL/FLL. Ensure that the PLL/FLL were properly restored (locked)
+* after the wakeup from Deep Sleep. Refer to the
+* \ref group_sysclk driver documentation driver for the information how to
+* read the PLL/FLL lock statuses.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_DeepSleep
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_DeepSleep(cy_en_syspm_waitfor_t waitFor)
+{
+ uint32_t interruptState;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor));
+
+ /* Call the registered callback functions with
+ * the CY_SYSPM_CHECK_READY parameter.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The device (core) can switch into the Deep Sleep power mode only when
+ * all executed registered callback functions with the CY_SYSPM_CHECK_READY
+ * parameter returned CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter. The return value should be
+ * CY_SYSPM_SUCCESS.
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ #ifdef CY_IP_MXUDB
+
+ static cy_stc_syspm_backup_regs_t regs;
+
+ /* Check whether the UDB disabled on MMIO level */
+ if (0UL != (PERI->GR[CY_MMIO_UDB_GROUP_NR].SL_CTL & PERI_UDB_SLAVE_ENABLED))
+ {
+
+ /* Save non-retained registers */
+ SaveRegisters(®s);
+ }
+ #endif /* CY_IP_MXUDB */
+
+ #if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+
+ if (CY_SYSLIB_DEVICE_REV_0A == (uint32_t) Cy_SysLib_GetDeviceRevision())
+ {
+ Cy_EnterDeepSleep(waitFor);
+ }
+ else
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+ {
+ cy_en_syspm_ldo_voltage_t curLdoVoltage;
+
+ curLdoVoltage = Cy_SysPm_LdoGetVoltage();
+
+ /* Configure additional wakeup delay from Deep Sleep
+ * for 1.1 V LDO. Cypress ID #290172.
+ */
+ if ((Cy_SysPm_LdoIsEnabled()) && (CY_SYSPM_LDO_VOLTAGE_1_1V == curLdoVoltage))
+ {
+ SRSS->PWR_TRIM_WAKE_CTL = CY_SYSPM_SFLASH->PWR_TRIM_WAKE_CTL;
+ }
+ else
+ {
+ SRSS->PWR_TRIM_WAKE_CTL = 0UL;
+ }
+
+ /* Set the core into Deep Sleep */
+ EnterDeepSleep(waitFor);
+ }
+
+ #ifdef CY_IP_MXUDB
+
+ /* Do not restore the UDB if it is disabled on MMIO level */
+ if (0UL != (PERI->GR[CY_MMIO_UDB_GROUP_NR].SL_CTL & PERI_UDB_SLAVE_ENABLED))
+ {
+ /* Restore non-retained registers */
+ RestoreRegisters(®s);
+ }
+ #endif /* CY_IP_MXUDB */
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Hibernate
+****************************************************************************//**
+*
+* Sets the device into Hibernate mode.
+*
+* Puts the core into the Hibernate power mode. Prior to entering Hibernate
+* mode, all callbacks of the CY_SYSPM_HIBERNATE type are executed.
+* First, callbacks of the CY_SYSPM_HIBERNATE type and with
+* CY_SYSPM_CHECK_READY parameter are called, allowing the driver to signal if it
+* is not ready to enter the power mode. If any of the callbacks of the
+* CY_SYSPM_HIBERNATE type with the CY_SYSPM_CHECK_READY parameter call returns
+* CY_SYSPM_FAIL, the remaining CY_SYSPM_HIBERNATE callbacks with the
+* CY_SYSPM_CHECK_READY parameter calls are skipped. After CY_SYSPM_FAIL, all
+* of the CY_SYSPM_HIBERNATE callbacks with CY_SYSPM_CHECK_FAIL parameter are
+* executed that correspond to the CY_SYSPM_HIBERNATE callbacks with
+* CY_SYSPM_CHECK_READY parameter calls that occurred up to the point of failure.
+* Hibernate mode is not entered and the Cy_SysPm_Hibernate() function
+* returns CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_CHECK_READY parameter
+* calls return CY_SYSPM_SUCCESS, then all CY_SYSPM_HIBERNATE callbacks with
+* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_HIBERNATE callbacks
+* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed allowing the
+* peripherals to prepare for Hibernate. The I/O output state is frozen and
+* Hibernate mode is then entered. In Hibernate mode, all internal supplies
+* are off and no internal state is retained. There is no handshake with the
+* CPUs and the chip will enter Hibernate immediately.
+*
+* The I/O output state is frozen and Hibernate mode is then
+* entered. In Hibernate mode, all internal supplies are off and no
+* internal state is retained.
+* For multi-core devices there is no handshake with the CPUs and the chip
+* will enter Hibernate power mode immediately.
+*
+* \note The last callback that returned CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL.
+*
+* The return values from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* A wakeup from Hibernate is triggered by toggling the wakeup pin(s), a WDT
+* match, or back-up domain alarm expiration, depending on how the they were
+* configured. A wakeup causes a normal boot procedure.
+* To configure the wakeup pin(s), a Digital Input Pin must be configured, and
+* resistively pulled up or down to the inverse state of the wakeup polarity. To
+* distinguish a wakeup from Hibernate mode and a general reset event, the
+* Cy_SysLib_GetResetReason() function can be used. The wakeup pin and low-power
+* comparators are active-low by default. The wakeup pin or the LPComparators
+* polarity can be changed with the \ref Cy_SysPm_SetHibernateWakeupSource() function.
+* This function call will not return if Hibernate mode is entered.
+* The CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_AFTER_TRANSITION parameter
+* are never executed.
+*
+* This function freezes the I/O cells implicitly. Entering
+* Hibernate mode before freezing the I/O cells is not possible. The I/O cells remain frozen
+* after waking from Hibernate mode until the firmware unfreezes them
+* with a \ref Cy_SysPm_IoUnfreeze() function call.
+*
+* \return
+* Entered status, see \ref cy_en_syspm_status_t.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Hibernate
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_Hibernate(void)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The device (core) can switch into Hibernate power mode only when
+ * all executed registered callback functions with CY_SYSPM_CHECK_READY
+ * parameter returned CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION
+ * parameter. Return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysLib_EnterCriticalSection();
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Preserve the token that will retain through a wakeup sequence
+ * thus could be used by Cy_SysLib_GetResetReason() to differentiate
+ * Wakeup from a general reset event.
+ * Preserve the wakeup source(s) configuration.
+ */
+ SRSS->PWR_HIBERNATE =
+ (SRSS->PWR_HIBERNATE & CY_SYSPM_PWR_WAKEUP_HIB_MASK) | CY_SYSPM_PWR_TOKEN_HIBERNATE;
+
+ /* Freeze I/O-Cells to save I/O-Cell state */
+ Cy_SysPm_IoFreeze();
+
+ SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_SET_HIBERNATE;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS->PWR_HIBERNATE;
+
+ /* Wait for transition */
+ __WFI();
+
+ /* The callback functions calls with the CY_SYSPM_AFTER_TRANSITION
+ * parameter in the Hibernate power mode are not applicable as device
+ * wake-up was made on device reboot.
+ */
+
+ /* A wakeup from Hibernate is performed by toggling of the wakeup
+ * pins, or WDT matches, or Backup domain alarm expires. This depends on what
+ * item is configured in the hibernate register. After a wakeup event, a
+ * normal Boot procedure occurs.
+ * There is no need to exit from the critical section.
+ */
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_EnterLowPowerMode
+****************************************************************************//**
+*
+* This function switches only the supply regulators into Low Power mode.
+* You must configure
+* clocks and/or peripherals to meet current load limitations in LP Active.
+* For more details about power modes and current load limitations refer to
+* the device technical reference manual (TRM).
+*
+* The LPActive mode is similar to the Active mode.
+* The difference is that the current is limited and some functions have limited
+* features/performance.
+*
+* The key feature of the Low Power mode is the limited current. Restrictions are
+* placed on the clock frequencies and allow the peripherals to achieve
+* a current limit.
+*
+* Before entering Low Power mode, you must configure the system so
+* the total current drawn from Vccd is less that the value presented in the
+* technical reference manual (TRM). Refer to the TRM for the maximum load for
+* low power operation and clock limitations in Low Power mode with different
+* core supply regulator voltages.
+*
+* * Peripherals can use the knowledge of the LPActive mode to make
+* trade-offs that consume less current. For more details, see the corresponding
+* peripherals' datasheet.
+* * High-speed clock sources are available with the appropriate pre-divider
+* settings to limit the system current.
+* Refer to the TRM for the maximum frequency values for low power operation
+* using different Core Regulators' output voltages.
+*
+* This function puts the device into Low Power mode. Prior to entering Low Power mode,
+* all the registered CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with CY_SYSPM_CHECK_READY
+* parameter are called. This allows the driver to signal if it is not ready to
+* enter Low Power mode. If any CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the
+* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining
+* CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the CY_SYSPM_CHECK_READY parameter
+* calls are skipped.
+*
+* After a CY_SYSPM_FAIL, all of the CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with
+* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the
+* CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls
+* that occurred up to the point of failure. Low Power mode is not entered and
+* the Cy_SysPm_EnterLowPowerMode() function returns CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the CY_SYSPM_CHECK_READY
+* parameter calls return CY_SYSPM_SUCCESS, then all CY_SYSPM_ENTER_LOWPOWER_MODE
+* callbacks with CY_SYSPM_CHECK_FAIL calls are skipped and all
+* CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the CY_SYSPM_BEFORE_TRANSITION parameter
+* calls are executed. This allows the peripherals to prepare for low power.
+* Low Power mode is then entered.
+*
+* After entering Low Power mode, all of the registered
+* CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the CY_SYSPM_AFTER_TRANSITION parameter
+* are executed to complete preparing the peripherals for low power operation.
+* The Cy_SysPm_EnterLowPowerMode() function returns CY_SYSPM_SUCCESS.
+* No CY_SYSPM_ENTER_LOWPOWER_MODE callbacks with the CY_SYSPM_BEFORE_TRANSITION or
+* CY_SYSPM_AFTER_TRANSITION parameter are executed, if Low Power mode is not
+* entered.
+*
+* \note The last callback that returned CY_SYSPM_FAIL is not executed with
+* the CY_SYSPM_CHECK_FAIL parameter because of the FAIL.
+*
+* The return values from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* \note The callbacks are not executed if the device is already not in
+* Low Power mode.
+*
+* \return
+* See \ref cy_en_syspm_status_t. <br>
+* CY_SYSPM_SUCCESS - Entered the LPActive mode or the device is already
+* in LPActive.<br>
+* CY_SYSPM_FAIL - The LPActive mode is not entered or low power circuits
+* are not ready to enter Low Power mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_EnterLowPowerMode
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_EnterLowPowerMode(void)
+{
+ uint32_t interruptState;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ /* Check whether device is in the low power mode. */
+ if(0U == (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL)))
+ {
+ /* The entering into the low power mode is permitted when low
+ * power circuits are ready to enter into the low power mode.
+ */
+ if(0U != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS->PWR_CTL))
+ {
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LOWPOWER_MODE, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The device (core) can switch into the low power mode only when
+ * all executed registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter returned CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter. The return value
+ * should be CY_SYSPM_SUCCESS.
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LOWPOWER_MODE, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Configure the low-power operating mode for LDO regulator */
+ if(Cy_SysPm_LdoIsEnabled())
+ {
+ SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_LINREG_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_BGREF_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_VREFBUF_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_IREF_LPMODE, 1U));
+ }
+ else
+ {
+ /* Configure the low-power operating mode for Buck regulator */
+ SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_BGREF_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_VREFBUF_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_IREF_LPMODE, 1U));
+ }
+
+ /* This wait time allows the circuits to remove their dependence on
+ * the Active mode circuits, such as Active Reference.
+ */
+ Cy_SysLib_DelayUs(CY_SYSPM_ACTIVE_TO_LP_WAIT_US);
+
+ /* Disabling active reference */
+ SRSS->PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_ACT_REF_DIS, 1U);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call the registered callback functions with the
+ * CY_SYSPM_AFTER_TRANSITION parameter. The return value
+ * should be CY_SYSPM_SUCCESS.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LOWPOWER_MODE, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LOWPOWER_MODE, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ }
+ else
+ {
+ retVal = CY_SYSPM_FAIL;
+ }
+ }
+ else
+ {
+ /* Do nothing because the device is already in Low Power mode. */
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ExitLowPowerMode
+****************************************************************************//**
+*
+* Exits the device from Low Power mode.
+*
+* Returns the device to the Active mode. In the Active power mode, the operating
+* current can be increased to the normal mode limit. The clock frequencies also
+* can be increased to the normal mode limit. Refer to the device TRM for the
+* current and frequency limitations in the Active power mode.
+*
+* Prior to exiting Low Power mode, all the registered CY_SYSPM_EXIT_LOWPOWER_MODE
+* callbacks with the CY_SYSPM_CHECK_READY parameter are called. This allows
+* the driver to signal if it is not ready to exit
+* Low Power mode. If any CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with
+* the CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining
+* CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with the CY_SYSPM_CHECK_READY parameter calls
+* are skipped. After a CY_SYSPM_FAIL, all of the CY_SYSPM_EXIT_LOWPOWER_MODE callbacks
+* with CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the
+* CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls that
+* occurred up to the point of failure. Active mode is not entered and the
+* Cy_SysPm_ExitLowPowerMode() function returns CY_SYSPM_FAIL.
+*
+* If all CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with CY_SYSPM_CHECK_READY calls return
+* CY_SYSPM_SUCCESS, then all the CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with
+* the CY_SYSPM_CHECK_FAIL parameter calls are skipped and all
+* CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with the CY_SYSPM_BEFORE_TRANSITION parameter
+* calls are executed allowing the peripherals to prepare for Active mode.
+* Low Power mode is then exited.
+*
+* After exiting Low Power mode, all of the registered callbacks that have
+* type CY_SYSPM_EXIT_LOWPOWER_MODE are executed with the CY_SYSPM_AFTER_TRANSITION
+* parameter to complete preparing the peripherals for Active mode operation.
+* The Cy_SysPm_ExitLowPowerMode() function returns CY_SYSPM_SUCCESS.
+* No CY_SYSPM_EXIT_LOWPOWER_MODE callbacks with the CY_SYSPM_BEFORE_TRANSITION or
+* CY_SYSPM_AFTER_TRANSITION parameter are executed if Low Power mode is
+* not exited.
+*
+* \note The last callback that returned CY_SYSPM_FAIL is not executed with the
+* CY_SYSPM_CHECK_FAIL parameter because of the FAIL.
+*
+* The return values from executed callback functions with the
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* modes are ignored.
+*
+* \note The callbacks are not executed if the device is not already in Low
+* Power mode.
+*
+* \return
+* See \ref cy_en_syspm_status_t. <br>
+* CY_SYSPM_SUCCESS - Exited from the LPActive power mode, or the device is
+* already in Active mode. <br>
+* CY_SYSPM_FAIL - Exit from the LPActive mode is not done.
+*
+* \warning This function blocks as it waits until Active Reference is ready
+* to enter to the normal mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_ExitLowPowerMode
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_ExitLowPowerMode(void)
+{
+ uint32_t interruptState;
+ uint32_t timeOut = CY_SYSPM_WAIT_DELAY_TRYES;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+
+ /* Check if the device is in the low power mode */
+ if(0U != (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL)))
+ {
+ /* Call the registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ retVal = Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LOWPOWER_MODE, CY_SYSPM_CHECK_READY);
+ }
+
+ /* The device (core) can switch into the Low Power mode only in the
+ * condition that all executed registered callback functions with the
+ * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS.
+ */
+ if(retVal == CY_SYSPM_SUCCESS)
+ {
+ /* Call the registered callback functions with the
+ * CY_SYSPM_BEFORE_TRANSITION parameter. The return value should be
+ * CY_SYSPM_SUCCESS.
+ */
+ interruptState = Cy_SysLib_EnterCriticalSection();
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LOWPOWER_MODE, CY_SYSPM_BEFORE_TRANSITION);
+ }
+
+ /* Set the normal operation mode for LDO regulator if
+ * it is enabled
+ */
+ if(Cy_SysPm_LdoIsEnabled())
+ {
+ SRSS->PWR_CTL &= ((uint32_t)~(SRSS_PWR_CTL_LINREG_LPMODE_Msk));
+ }
+
+ /* Configure the normal operating mode for the POR/BOD circuits and
+ * for the Bandgap Voltage and Current References
+ */
+ SRSS->PWR_CTL &= ((uint32_t)~(_VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_ACT_REF_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_VREFBUF_LPMODE, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_IREF_LPMODE, 1U)));
+
+ /* This wait time allows setting Active Reference */
+ Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US);
+
+ while((0U == _FLD2VAL(SRSS_PWR_CTL_ACT_REF_OK, SRSS->PWR_CTL)) && (0U != timeOut))
+ {
+ timeOut--;
+ }
+
+ if(0U == timeOut)
+ {
+ retVal = CY_SYSPM_TIMEOUT;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+ else
+ {
+ /* Configure the normal operation mode */
+ SRSS->PWR_CTL &= ((uint32_t) (~SRSS_PWR_CTL_BGREF_LPMODE_Msk));
+
+ /* This wait time allows setting Active Reference */
+ Cy_SysLib_DelayUs(CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ /* Call registered callback functions with CY_SYSPM_AFTER_TRANSITION
+ * parameter. Return value should be CY_SYSPM_SUCCESS.
+ */
+ if(0U != curRegisteredCallbacks)
+ {
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LOWPOWER_MODE, CY_SYSPM_AFTER_TRANSITION);
+ }
+ }
+
+ }
+ else
+ {
+ /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to
+ * undo everything done in the callback with the CY_SYSPM_CHECK_READY
+ * parameter. The return value should be CY_SYSPM_SUCCESS.
+ */
+ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LOWPOWER_MODE, CY_SYSPM_CHECK_FAIL);
+ retVal = CY_SYSPM_FAIL;
+ }
+ }
+ else
+ {
+ /* Do nothing because the device is already in the Active power mode */
+ }
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SleepOnExit
+****************************************************************************//**
+*
+* This function configures the Sleep-on-exit feature of the core.
+*
+* This API sets the SLEEPONEXIT bit of the SCR register.
+*
+* When the Sleep-on-exit feature is enabled (SLEEPONEXIT bit is set),
+* the core wakes up to service the interrupt and then immediately goes
+* back to sleep. Because of this, the unstacking process is not carried out, so
+* this feature is useful for the interrupt driven application and helps to
+* reduce the unnecessary stack push and pop operations.
+* The core does not go to sleep if the interrupt handler returns to
+* another interrupt handler (nested interrupt).
+* You can use this feature in applications that require only the core to run
+* when an interrupt occurs.
+*
+* When the Sleep-on-exit feature is disabled (SLEEPONEXIT bit is cleared),
+* the core returns back to the main thread after servicing the interrupt
+* without going back to sleep.
+*
+* Refer to the ARM documentation about the Sleep-on-exit feature and
+* SLEEPONEXIT of the SCR register.
+*
+* \param enable
+* true - enable Sleep-on-exit feature <br> false - disable
+* Sleep-on-exit feature.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_SleepOnExit
+*
+*******************************************************************************/
+void Cy_SysPm_SleepOnExit(bool enable)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ if(enable)
+ {
+ /* Enable Sleep-on-exit mode */
+ SCB->SCR |= _VAL2FLD(SCB_SCR_SLEEPONEXIT, 1U);
+ }
+ else
+ {
+ /* Disable Sleep-on-exit mode */
+ SCB->SCR &= ((uint32_t) ~(SCB_SCR_SLEEPONEXIT_Msk));
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_SetHibernateWakeupSource
+****************************************************************************//**
+*
+* This function configures sources to wake up the device from the Hibernate
+* power mode. Such sources can be wakeup pins, LPComparators, Watchdog (WDT)
+* interrupt, or a Real-Time clock (RTC) alarm (interrupt).
+*
+* Wakeup pins:
+*
+* A wakeup is supported by up to two pins with programmable polarity. These pins
+* may be connected to the I/O pins or on-chip peripherals under some conditions.
+* Setting the wakeup pin to this level will cause a wakeup from Hibernate
+* mode. The wakeup pins are active/low by default.
+*
+* LPComparators:
+*
+* A wakeup is supported by up to two LPComps with programmable polarity. These
+* LPComp may be connected to the I/O pins or on-chip peripherals under some
+* conditions.
+* Setting the LPComp to this level will cause a wakeup from Hibernate
+* mode. The wakeup LPComp are active-low by default.
+*
+* \note The low-power comparators should be configured and enabled before
+* switching into the hibernate low power mode. Refer to the LPComp
+* driver description for more details.
+*
+* Watchdog Timer:
+*
+* \note The WDT should be configured and enabled before entering into the
+* Hibernate power mode.
+*
+* A wakeup is performed by a WDT interrupt and a normal boot procedure
+* after a device reset. The device can wake up from Hibernate after a WDT
+* device reset, if the WDT was configured to wake up, the device on its
+* interrupt and WDT was enabled.
+*
+* Real-time Clock:
+*
+* A wakeup is performed by the RTC alarm and a normal boot procedure
+* after a device reset.
+* Refer to the Real-Time Clock (RTC) driver description for more details.
+*
+* For information about wakeup sources and their assignment in the specific
+* families devices, refer to the appropriate device TRM.
+*
+* \param wakeupSource
+* The source to be configured as a wakeup source from
+* the Hibernate power mode, see \ref cy_en_syspm_hibernate_wakeup_source_t.
+* The input parameters values can be ORed. For example, if you want to set
+* LPComp0 (active high) and WDT, call this function:
+* Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT).
+*
+* \warning Do not call this function with different polarity levels for the same
+* wakeup source. For example, do not call a function like this:
+* Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_LOW, CY_SYSPM_HIBERNATE_LPCOMP0_HIGH);
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_SetHibernateWakeupSource
+*
+*******************************************************************************/
+void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
+
+ /* Reconfigure the wake-up pins and LPComp polarity based on the input */
+ if(0U != ((uint32_t) wakeupSource & CY_SYSPM_WAKEUP_LPCOMP0))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_LPCOMP0_BIT));
+ }
+
+ if(0U != ((uint32_t) wakeupSource & CY_SYSPM_WAKEUP_LPCOMP1))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_LPCOMP1_BIT));
+ }
+
+ if(0U != ((uint32_t) wakeupSource & CY_SYSPM_WAKEUP_PIN0))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_PIN0_BIT));
+ }
+
+ if(0U != ((uint32_t) wakeupSource & CY_SYSPM_WAKEUP_PIN1))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_PIN1_BIT));
+ }
+
+ SRSS->PWR_HIBERNATE |= ((uint32_t) wakeupSource);
+
+ /* Read register to make sure it is settled */
+ (void) SRSS->PWR_HIBERNATE;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ClearHibernateWakeupSource
+****************************************************************************//**
+*
+* This function disables a wakeup source that was previously configured to
+* wake up the device from the hibernate power mode.
+*
+* \param wakeupSource
+* For the source to be disabled, see \ref cy_en_syspm_hibernate_wakeup_source_t.
+* The input parameters values can be ORed. For example, if you want to disable
+* LPComp0 (active high) and WDT call this function:
+* Cy_SysPm_ClearHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT).
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_ClearHibernateWakeupSource
+*
+*******************************************************************************/
+void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource)
+{
+ uint32_t clearWakeupSource;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource));
+
+ if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource))
+ {
+ /* Clear the high active level of the requested sources */
+ if((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH == ((uint32_t) wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP0_HIGH))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_LPCOMP0_BIT));
+ }
+
+ if((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == ((uint32_t) wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_LPCOMP1_BIT));
+ }
+
+ if((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == ((uint32_t) wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_PIN0_BIT));
+ }
+
+ if((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == ((uint32_t) wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH))
+ {
+ SRSS->PWR_HIBERNATE &=
+ ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, CY_SYSPM_WAKEUP_PIN1_BIT));
+ }
+ }
+
+ /* Remove the polarity bits from the input value */
+ clearWakeupSource = ((uint32_t) wakeupSource & ((uint32_t) ~ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk));
+
+ SRSS->PWR_HIBERNATE &= ((uint32_t) ~ clearWakeupSource);
+
+ /* Read register to make sure it is settled */
+ (void) SRSS->PWR_HIBERNATE;
+}
+
+
+#if(0u != SRSS_BUCKCTL_PRESENT)
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckEnable
+ ****************************************************************************//**
+ *
+ * Switch the power supply regulator to Buck regulator instead of the LDO.
+ * The Buck core regulator provides output voltage(s) using one external
+ * inductor and can supply Vccd with higher efficiency than the LDO under some
+ * conditions, such as high external supply voltage.
+ *
+ * Before changing from LDO to Buck, ensure that the circuit board has
+ * connected Vccbuck1 to Vccd and also populated the
+ * necessary external components for the Buck regulator, including an
+ * inductor and a capacitor for each output.
+ * Refer to the device TRM for more details.
+ *
+ * When changing from a higher voltage to a lower voltage
+ * (from LDO 1.1V to Buck 0.9V), ensure that:
+ * * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+ * and slow clock are under the ULP limitations.
+ * * The total current consumption is under the ULP limitations.
+ *
+ * * The appropriate wait states values are set for the flash using
+ * the Cy_SysLib_SetWaitStates() function as explained below.
+ *
+ * <b>Setting wait states values for flash</b>
+ *
+ * The flash access time when the core output voltage is 0.9 V (nominal) is
+ * longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+ * be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+ * wait state values for flash.
+ *
+ * To change from a higher voltage (LDO 1.1 V) to a lower voltage (Buck 0.9 V),
+ * call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+ * the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+ *
+ * To change from a lower voltage (LDO 0.9 V) to a higher voltage (Buck 1.1 V),
+ * calling the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function is to set
+ * the wait states is optional, but can be done to improve the performance.
+ * The clock frequency may now be increased up to LP mode for a new voltage.
+ *
+ * \note 1. The final Buck output is set to 0.9 V (nominal) - the flash works
+ * in the Read-only operation.
+ * \note 2. The final Buck output is set to 1.1 V (nominal) - the flash works
+ * in the Read and Write operations.
+ * \note 3. The actual device Vccd voltage can be different from the nominal
+ * voltage because the actual voltage value depends on the conditions
+ * including the load current.
+ *
+ * \warning There is no way to go back to the LDO after the
+ * Buck regulator supplies a core. The function switches off the LDO.
+ *
+ * For more details refer to the \ref group_syspm_managing_core_regulators
+ * section.
+ * Refer to the \ref group_syslib driver for more details about setting the wait
+ * states.
+ *
+ * \note
+ * The function is applicable for devices with the Buck regulator.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckEnable
+ *
+ *******************************************************************************/
+ void Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage)
+ {
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage));
+
+ uint32_t interruptState;
+ cy_en_syspm_ldo_voltage_t curLdoVoltage;
+
+ curLdoVoltage = Cy_SysPm_LdoGetVoltage();
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* When the LDO is 1.1V and final target Buck 0.9V need to update the
+ * RAM and ROM trim values
+ */
+ if ((CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) && (CY_SYSPM_LDO_VOLTAGE_1_1V == curLdoVoltage))
+ {
+ /* Set the analog signal bit for the flash before the voltage is
+ * changed from 1.1V to 0.9V
+ */
+ SetVoltageBitForFlash();
+
+ /* Update read-write margin value for the ULP mode */
+ SetReadMarginTrimUlp();
+
+ /* Reduce LDO output voltage to 0.95 V nominal */
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+
+ /* Update write assist value for the ULP mode */
+ SetWriteAssistTrimUlp();
+ }
+ /* When the LDO is 0.9V and final target Buck 1.1 V need to update the
+ * RAM and ROM trim values
+ */
+ else if ((CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V == voltage) && (CY_SYSPM_LDO_VOLTAGE_0_9V == curLdoVoltage))
+ {
+ /* Increase LDO to 0.95 V */
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+
+ /* Wait until regulator is stable */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Update write assist value for the LP mode */
+ SetWriteAssistTrimLp();
+
+ /* Increase LDO to 1.1 V */
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_1V);
+
+ /* Wait until regulator is stable */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Update read-write margin value for the LP mode */
+ SetReadMarginTrimLp();
+
+ /* Set the LDO 1.15V as final Buck output is 1.1 V */
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_15V);
+
+ /* Clear the analog signal bit for the flash before the voltage is
+ * changed from 1.1 V to 0.9 V
+ */
+ ClearVoltageBitForFlash();
+ }
+ /* If LDO is 0.9V and final Buck is 0.9V increase the LDO on 50 mV*/
+ else if ((CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) && (CY_SYSPM_LDO_VOLTAGE_0_9V == curLdoVoltage))
+ {
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+ }
+ /* If LDO is 1.1V and final Buck is 1.1 V increase the LDO on 50 mV*/
+ else
+ {
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_15V);
+ }
+
+ /* A delay for the supply to stabilize at the new higher voltage */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Disable the Deep Sleep, nWell, and Retention regulators */
+ SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) |
+ _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U));
+
+ /* Configure the Buck regulator */
+ SRSS->PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage);
+
+ /* Check whether the Buck regulator is already enabled */
+ if(!Cy_SysPm_BuckIsEnabled())
+ {
+ SRSS->PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U);
+ }
+
+ SRSS->PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, 1U);
+
+ /* Wait until Buck output 1 is stable */
+ Cy_SysLib_DelayUs(CY_SYSPM_BUCK_CORE_SUPPLY_STABLE_US);
+
+ /* Disable the LDO, because Vbuckout1 and LDO are shorted */
+ SRSS->PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckSetVoltage1
+ ****************************************************************************//**
+ *
+ * Sets the output 1 voltage for the Buck regulator that can supply core(s).
+ * This output can supply cores instead of the LDO.
+ *
+ * When changing from a higher voltage to a lower voltage, ensure that:
+ * * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+ * and slow clock are under the \ref group_syspm_ulp_limitations.
+ * * The total current consumption is under the \ref group_syspm_ulp_limitations.
+ *
+ * * The appropriate wait states values are set for the flash using
+ * the Cy_SysLib_SetWaitStates() function as explained below.
+ *
+ * <b>Setting wait states values for flash</b>
+ *
+ * The flash access time when the core output voltage is 0.9 V (nominal) is
+ * longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+ * be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+ * wait state values for flash.
+ *
+ * To change from a higher voltage to a lower voltage 0.9 V (nominal),
+ * call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+ * the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+ *
+ * To change from a lower voltage to a higher voltage 1.1 V (nominal), calling
+ * the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function is to set the
+ * wait states is optional, but can be done to improve the performance.
+ * The clock frequency may now be increased up to
+ * \ref group_syspm_lp_limitations for a new voltage.
+ *
+ * \note 1. The output is set to 0.9 V (nominal) - the flash works in the
+ * Read-only operation.
+ * \note 2. The output is set to 1.1 V (nominal) - the flash works in the Read
+ * and Write operations.
+ * \note 3. The actual device Vccd voltage can be different from the nominal
+ * voltage because the actual voltage value depends on the conditions
+ * including the load current.
+ *
+ * For more details refer to the \ref group_syspm_managing_core_regulators
+ * section.
+ * Refer to the \ref group_syslib driver for more details about setting the
+ * wait states.
+ *
+ * \param voltage
+ * The desired output 1 regulator voltage (Vccbuck1).
+ * See \ref cy_en_syspm_buck_voltage1_t
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+ *
+ *******************************************************************************/
+ void Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage)
+ {
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage));
+
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Check whether the required voltage is equal to the current voltage */
+ if (voltage != Cy_SysPm_BuckGetVoltage1())
+ {
+
+ if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage)
+ {
+ /* Set the analog signal bit for the flash before the voltage is
+ * changed from 1.1 V to 0.9 V
+ */
+ SetVoltageBitForFlash();
+
+ /* Update read-write margin value for the ULP mode */
+ SetReadMarginTrimUlp();
+
+ /* Reduce Buck output voltage to 0.95V nominal */
+ SRSS->PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V);
+
+ /* Update write assist value for the ULP mode */
+ SetWriteAssistTrimUlp();
+ }
+ else
+ {
+ /* Increase Buck output voltage to 0.95 V nominal */
+ SRSS->PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V);
+
+ /* Wait until regulator is stable */
+ Cy_SysLib_DelayUs(BUCK_STABILIZATION_DELAY_US);
+
+ /* Update write assist value for the LP mode */
+ SetWriteAssistTrimLp();
+ }
+
+ /* The system may continue operating while the voltage on Vccd
+ * discharges to the new voltage. The time it takes to reach the
+ * new voltage depends on the conditions, including the load current
+ * on Vccd and the external capacitor size.
+ */
+ SRSS->PWR_BUCK_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage);
+
+ /* Delay to stabilize at the new voltage is required only
+ * when changing from a lower voltage to a higher voltage.
+ */
+ if(CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V == voltage)
+ {
+ Cy_SysLib_DelayUs(BUCK_STABILIZATION_DELAY_US);
+
+ /* Update read-write margin value for the LP mode */
+ SetReadMarginTrimLp();
+
+ /* Set analog signal bit for flash before voltage is changed
+ * from 0.9 V to 1.1 V.
+ */
+ ClearVoltageBitForFlash();
+ }
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckIsOutputEnabled
+ ****************************************************************************//**
+ *
+ * This function gets the current output status of the Buck outputs.
+ *
+ * \param output
+ * The Buck regulator output. See \ref cy_en_syspm_buck_out_t.
+ *
+ * \return
+ * The current state of the requested output. True if the requested output
+ * is enabled.
+ * False if the requested output is disabled.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckIsOutputEnabled
+ *
+ *******************************************************************************/
+ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output)
+ {
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_OUTPUT_VALID(output));
+
+ bool retVal = false;
+
+ if (output == CY_SYSPM_BUCK_VBUCK_1)
+ {
+ retVal = (_FLD2BOOL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, SRSS->PWR_BUCK_CTL));
+ }
+
+ #if (0u != SRSS_SIMOBUCK_PRESENT)
+ if(output == CY_SYSPM_BUCK_VRF)
+ {
+ retVal = ((0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS->PWR_BUCK_CTL2)) ||
+ (0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, SRSS->PWR_BUCK_CTL2)));
+ }
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+
+ return(retVal);
+ }
+
+ #if(0u != SRSS_SIMOBUCK_PRESENT)
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckEnableVoltage2
+ ****************************************************************************//**
+ *
+ * Enable the output 2 voltage (Vbuckrf) of the SIMO Buck regulator.
+ * The output 2 voltage (Vbuckrf) of the Buck regulator is used to supply
+ * the BLE HW block.
+ * When the Buck regulator is switched off, the function enables the
+ * regulator and after it, enables output 2.
+ *
+ * \note The function does not affect Buck output 1 that can supply
+ * a core.
+ *
+ * \warning The function does not select the Buck output 2 voltage and
+ * does not set/clear the HW-controlled bit for Buck output 2. Call
+ * Cy_SysPm_BuckSetVoltage2() or Cy_SysPm_BuckSetVoltage2HwControl() to
+ * configure the Buck output 2.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckEnableVoltage2
+ *
+ *******************************************************************************/
+ void Cy_SysPm_BuckEnableVoltage2(void)
+ {
+ if(!Cy_SysPm_BuckIsEnabled())
+ {
+ /* Enable the SIMO Buck regulator */
+ SRSS->PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U);
+ }
+
+ /* Enable the SIMO Buck output 2 */
+ SRSS->PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U);
+
+ /* Wait until the output is stable */
+ Cy_SysLib_DelayUs(CY_SYSPM_BUCK_BLE_SUPPLY_STABLE_US);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckSetVoltage2
+ ****************************************************************************//**
+ *
+ * This function sets output voltage 2 of the SIMO Buck regulator.
+ *
+ * \param voltage
+ * The voltage of the Buck regulator output 2.
+ * See \ref cy_en_syspm_buck_voltage2_t.
+ *
+ * \param waitToSettle
+ * True - Enable the 200 us delay after setting a higher voltage.
+ * False - Disable the 200 us delay after setting a higher voltage.
+ *
+ * \warning You must enable the delay (waitToSettle = true)
+ * while changing from a lower voltage to a higher voltage.
+ *
+ * \note The 200 us delay is required only when changing from a
+ * lower voltage to a higher voltage. Changing from a higher voltage to a lower one,
+ * the delay is not required.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckSetVoltage2
+ *
+ *******************************************************************************/
+ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle)
+ {
+ uint32_t curVoltage;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage));
+
+ /* Get the current voltage */
+ curVoltage = (uint32_t) Cy_SysPm_BuckGetVoltage2();
+
+ if((uint32_t) voltage != curVoltage)
+ {
+ SRSS->PWR_BUCK_CTL2 =
+ _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage);
+
+ /* Delay to stabilize at the new voltage is required only
+ * when changing from a lower voltage to a higher voltage.
+ */
+ if(waitToSettle && ((uint32_t) voltage > curVoltage))
+ {
+ Cy_SysLib_DelayUs(BUCK_STABILIZATION_DELAY_US);
+ }
+ }
+ }
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoSetVoltage
+****************************************************************************//**
+*
+* Set an output voltage on the LDO.
+*
+* When changing from a higher voltage to a lower voltage, ensure that:
+* * The device maximum operating frequency for all the Clk_HF paths, peripheral,
+* and slow clock are under the \ref group_syspm_ulp_limitations.
+* * The total current consumption is under the \ref group_syspm_ulp_limitations.
+* * The appropriate wait states values are set for the flash using
+* the Cy_SysLib_SetWaitStates() function as explained below.
+*
+* <b>Setting wait states values for Flash</b>
+*
+* The flash access time when the core output voltage is 0.9 V (nominal) is
+* longer than at 1.1 V (nominal). Therefore, the number of the wait states must
+* be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate
+* wait state values for flash.
+*
+* To change from a higher voltage to a lower voltage 0.9 V (nominal),
+* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing
+* the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz.
+*
+* To change from a lower voltage to a higher voltage 1.1 V (nominal), calling
+* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function is to set the
+* wait states is optional, but can be done to improve the performance.
+* The clock frequency may now be increased up to \ref group_syspm_lp_limitations
+* for a new voltage.
+*
+* \note 1. The output is set to 0.9 V (nominal) - the flash works in the
+* Read-only operation.
+* \note 2. The output is set to 1.1 V (nominal) - the flash works in the Read
+* and Write operations.
+* \note 3. The actual device Vccd voltage can be different from the nominal
+* voltage because the actual voltage value depends on the conditions
+* including the load current.
+*
+* For more details refer to the \ref group_syspm_managing_core_regulators
+* section.
+* Refer to the \ref group_syslib driver for more details about setting the wait
+* states.
+*
+* \param voltage
+* The desired output regulator voltage.
+* See \ref cy_en_syspm_ldo_voltage_t voltage
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+void Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage));
+
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ if (Cy_SysPm_LdoGetVoltage() != voltage)
+ {
+ uint32_t trimVoltage;
+
+ if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage)
+ {
+ /* Set the analog signal bit for the flash before the voltage is changed
+ * from 1.1 V to 0.9 V. Store trimmed voltage value into the local variable
+ */
+ SetVoltageBitForFlash();
+
+ /* Update read-write margin value for the ULP mode */
+ SetReadMarginTrimUlp();
+
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+
+ /* Update write assist value for the ULP mode */
+ SetWriteAssistTrimUlp();
+
+ trimVoltage = SFLASH->LDO_0P9V_TRIM;
+ }
+ else
+ {
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V);
+
+ /* A delay for the supply to stabilize at the new higher voltage */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Update write assist value for the LP mode */
+ SetWriteAssistTrimLp();
+
+ trimVoltage = SFLASH->LDO_1P1V_TRIM;
+ }
+
+ /* The system may continue operating while the voltage on Vccd
+ * discharges to the new voltage. The time it takes to reach the
+ * new voltage depends on the conditions, including the load current on
+ * Vccd and the external capacitor size
+ */
+ SRSS->PWR_TRIM_PWRSYS_CTL =
+ _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, trimVoltage);
+
+ if (CY_SYSPM_LDO_VOLTAGE_1_1V == voltage)
+ {
+ /* A delay for the supply to stabilize at the new higher voltage */
+ Cy_SysLib_DelayUs(LDO_STABILIZATION_DELAY_US);
+
+ /* Update read-write margin value for the LP mode */
+ SetReadMarginTrimLp();
+
+ /* Set the analog signal bit to the flash macro register after
+ * the output voltage is 1.1 V
+ */
+ ClearVoltageBitForFlash();
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_RegisterCallback
+****************************************************************************//**
+*
+* Registers a new syspm callback.
+*
+* A callback is a function called after an event in the driver or
+* middleware module has occurred. The handler callback API will be executed if
+* the specific event occurs. See \ref cy_stc_syspm_callback_t.
+*
+* \note The registered callbacks are executed in two orders, based on callback
+* mode \ref cy_en_syspm_callback_mode_t. For modes CY_SYSPM_CHECK_READY and
+* CY_SYSPM_BEFORE_TRANSITION, the order is this: the first registered callback
+* will be always the first executed. And the last registered callback will be
+* executed as the last callback. For modes CY_SYSPM_AFTER_TRANSITION and
+* CY_SYSPM_CHECK_FAIL, the order is this: the first registered callback will be
+* always the last executed. And the last registered callback will be executed
+* as the first callback.
+*
+* \param handler
+* The address of the syspm callback structure.
+* See \ref cy_stc_syspm_callback_t.
+* \note Do not modify the registered structure in run-time.
+*
+* \return
+* True if a callback was registered; <br>
+* False if a callback was not registered or maximum callbacks were registered.
+*
+* It is allowed to register up to 32 callbacks.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Func_Declaration
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Params_Declaration
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Structure_Declaration
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Func_Implementation
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_RegisterCallback
+*
+*******************************************************************************/
+bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler)
+{
+ uint32_t interruptState;
+ bool retStatus = false;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Check if the maximum callbacks were registered and verify input */
+ retStatus = ((handler != NULL) && (curRegisteredCallbacks < CY_SYSPM_CALLBACKS_NUMBER_MAX));
+
+ if (retStatus)
+ {
+ if ((handler->callbackParams != NULL) && (handler->callback != NULL))
+ {
+ cy_stc_syspm_callback_t* curCallback = callbackRoot;
+ cy_stc_syspm_callback_t* lastRegCallback = NULL;
+
+ /* Search last registered callback item */
+ while (curCallback != NULL)
+ {
+ if (curCallback == handler)
+ {
+ /* Do not register already registered callback item */
+ retStatus = false;
+ break;
+ }
+
+ /* Safe callback before switching into the next item */
+ lastRegCallback = curCallback;
+
+ curCallback = curCallback->nextItm;
+ }
+
+ /* Link requested callback item to the linked list */
+ if (retStatus)
+ {
+ if (callbackRoot == NULL)
+ {
+ /* Link first callback item to the linked list */
+ callbackRoot = handler;
+ }
+ else
+ {
+ /* Link requested item to previous item */
+ lastRegCallback->nextItm = handler;
+ }
+
+ /* Update links to next and previous callback items of requested
+ * callback item
+ */
+ handler->prevItm = lastRegCallback;
+ handler->nextItm = NULL;
+ callbackListLast = handler;
+
+ /* Increment the value with number of registered callbacks */
+ ++curRegisteredCallbacks;
+ }
+ }
+ else
+ {
+ retStatus = false;
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_UnregisterCallback
+****************************************************************************//**
+*
+* This function unregisters a callback.
+*
+* The registered callback can be unregistered. Otherwise, false will be
+* returned.
+*
+* \param handler The item that should be unregistered.
+* See \ref cy_stc_syspm_callback_t.
+*
+* \return
+* True if on success <br>
+* False if it was not unregistered or no callbacks were registered.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_UnregisterCallback
+*
+*******************************************************************************/
+bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler)
+{
+ uint32_t interruptState;
+ bool retStatus = false;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Check if there was at least one callback registered */
+ if (curRegisteredCallbacks > 0UL)
+ {
+ cy_stc_syspm_callback_t* curCallback = callbackRoot;
+
+ /* Search requested callback item in the linked list */
+ while (curCallback != NULL)
+ {
+ /* Requested callback is found */
+ if (curCallback == handler)
+ {
+ retStatus = true;
+ break;
+ }
+
+ /* Go to next callback item in the linked list */
+ curCallback = curCallback->nextItm;
+ }
+
+ if (retStatus)
+ {
+ /* Update links of related to unregistered callback items */
+ if (handler->nextItm != NULL)
+ {
+ handler->nextItm->prevItm = handler->prevItm;
+ }
+ if (handler->prevItm != NULL)
+ {
+ handler->prevItm->nextItm = handler->nextItm;
+ }
+
+ /* Requested callback was first in the list */
+ if (callbackRoot == handler)
+ {
+ callbackRoot = callbackRoot->nextItm;
+ }
+
+ /* Requested callback was last in the list */
+ if (callbackListLast == handler)
+ {
+ callbackListLast = handler->prevItm;
+ }
+
+ /* Decrement the value with number of registered callbacks */
+ --curRegisteredCallbacks;
+ }
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+
+ return(retStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_ExecuteCallback
+****************************************************************************//**
+*
+* The function executes all registered callbacks with provided type and mode.
+* \note This low-level function is being used by \ref Cy_SysPm_Sleep,
+* \ref Cy_SysPm_DeepSleep, \ref Cy_SysPm_Hibernate, \ref Cy_SysPm_EnterLowPowerMode
+* and \ref Cy_SysPm_ExitLowPowerMode API functions, however might be also useful as
+* an independent API function in some custom applications.
+* \note The registered callbacks will be executed in order based on
+* \ref cy_en_syspm_callback_type_t value.
+* The are possible two orders of callbacks execution: <br>
+* * From first registered to last registered. Such order is relevant to
+* callbacks with mode CY_SYSPM_CHECK_READY and CY_SYSPM_BEFORE_TRANSITION.
+* * Backward flow execution: from last executed callback to the
+* first registered. Such order is relevant to callbacks with mode
+* CY_SYSPM_AFTER_TRANSITION and CY_SYSPM_CHECK_FAIL. Note that, the last
+* registered callback function is skipped with mode CY_SYSPM_CHECK_FAIL. This
+* is because the callback that returned CY_SYSPM_FAIL already knows that it failed.
+*
+* If no callbacks are registered, returns CY_SYSPM_SUCCESS.
+*
+* \param type
+* The callback type. See \ref cy_en_syspm_callback_type_t.
+*
+* \param mode
+* The callback mode. See \ref cy_en_syspm_callback_mode_t.
+*
+* \note
+* If mode is CY_SYSPM_CHECK_READY or CY_SYSPM_BEFORE_TRANSITION the
+* all required callbacks would be executed in order from first
+* registered to last registered.
+* If mode is CY_SYSPM_CHECK_FAIL or CY_SYSPM_AFTER_TRANSITION the
+* all required callbacks would be executed in order from last executed callback
+* to first registered.
+*
+* \return
+* CY_SYSPM_SUCCESS Callback successfully completed or nor callbacks registered.
+* CY_SYSPM_FAIL one of executed callback(s) returned fail.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_ExecuteCallback
+*
+*******************************************************************************/
+cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode)
+{
+ static cy_stc_syspm_callback_t* lastExecutedCallback = NULL;
+ cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS;
+ cy_stc_syspm_callback_t* curCallback;
+ cy_stc_syspm_callback_params_t curParams;
+
+ CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type));
+ CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode));
+
+ if((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY))
+ {
+ /* Execute registered callbacks with order from first registered to the
+ * last registered. The modes defined in the .skipMode element are not
+ * executed
+ */
+ curCallback = callbackRoot;
+ while((curCallback != NULL) && (retVal != CY_SYSPM_FAIL))
+ {
+ if((curCallback->type == type) && ((0U == curCallback->skipMode) ||
+ (0U == ((uint32_t) mode & curCallback->skipMode))))
+ {
+ /* Update elements for local callback parameter values */
+ curParams.base = curCallback->callbackParams->base;
+ curParams.context = curCallback->callbackParams->context;
+ curParams.mode = mode;
+
+ retVal = curCallback->callback(&curParams);
+
+ /* Update callback pointer with value of executed callback.
+ * Such update is required to execute further callbacks in
+ * backward order after exit from low power mode or to undo
+ * configuration after callback returned fail: from last executed
+ * to first registered.
+ */
+ lastExecutedCallback = curCallback;
+ }
+ curCallback = curCallback->nextItm;
+ }
+ }
+ else
+ {
+ /* Execute registered callbacks with order from lastCallback to
+ * the first registered callback. Such a flow is required if previous
+ * callback function returned CY_SYSPM_FAIL or previous callback mode was
+ * CY_SYSPM_BEFORE_TRANSITION. Such an order is required to undo configurations in
+ * correct backward order.
+ */
+ curCallback = callbackListLast;
+
+ /* Skip last executed callback that returned CY_SYSPM_FAIL, as this
+ * callback already knows that it failed
+ */
+ if (mode == CY_SYSPM_CHECK_FAIL)
+ {
+ curCallback = lastExecutedCallback;
+ if (curCallback != NULL)
+ {
+ curCallback = curCallback->prevItm;
+ }
+ }
+
+ /* Execute all registered callback functions with required type and mode */
+ while ((curCallback != NULL) && (retVal != CY_SYSPM_FAIL))
+ {
+ if ((curCallback->type == type) && ((curCallback->skipMode == 0UL) ||
+ (((uint32_t) mode & curCallback->skipMode) == 0UL)))
+ {
+ /* Update elements for local callback parameter values */
+ curParams.base = curCallback->callbackParams->base;
+ curParams.context = curCallback->callbackParams->context;
+ curParams.mode = mode;
+
+ retVal = curCallback->callback(&curParams);
+ }
+ curCallback = curCallback->prevItm;
+ }
+ }
+ return (retVal);
+}
+
+/** \cond INTERNAL */
+/*******************************************************************************
+* Function Name: Cy_SysPm_IoFreeze
+****************************************************************************//**
+*
+* This function saves the output states and configuration of I/O cells.
+*
+* I/O-cell configuration can be changed while I/O-cells are frozen. The new
+* configuration becomes effective only after the pins are unfrozen.
+*
+* Cy_SysPm_Hibernate() calls this function to freeze the I/O cells while
+* entering hibernate.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Freeze
+*
+*******************************************************************************/
+void Cy_SysPm_IoFreeze(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Check the FREEZE state to avoid a recurrent I/O-cells freeze attempt,
+ * because the second call to this function will cause an accidental switch
+ * to Hibernate mode (the system will enter Hibernate mode immediately
+ * after writing to the hibernate bit because both UNLOCK and FREEZE were set
+ * correctly in the previous call to this function).
+ */
+ if(0U == _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS->PWR_HIBERNATE))
+ {
+ /* Clear the unlock field for correct freeze of the I/O cells */
+ SRSS->PWR_HIBERNATE = _CLR_SET_FLD32U((SRSS->PWR_HIBERNATE), SRSS_PWR_HIBERNATE_UNLOCK, 0U);
+
+ /* Disable overriding by the peripherals the next pin-freeze command */
+ SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_SET_HIBERNATE;
+
+ /* The second write causes freeze of I/O cells to save the I/O-cell state */
+ regValue = SRSS->PWR_HIBERNATE;
+ SRSS->PWR_HIBERNATE = regValue;
+ }
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+/** \endcond */
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IoUnfreeze
+****************************************************************************//**
+*
+* This function unfreezes the I/O cells which were automatically frozen when the
+* Hibernate is entered with the call to \ref Cy_SysPm_Hibernate().
+*
+* I/O-cells remain frozen after a wakeup from hibernate mode until the
+* firmware unfreezes them, by calling this function.
+*
+* If the firmware must retain the data value on the port, then the
+* value must be read and re-written to the data register before calling this
+* function. Furthermore, the drive mode must be re-programmed before the pins are
+* unfrozen. If this is not done, the pin will change to the default state
+* the moment the freeze is removed.
+*
+* Note that I/O cell configuration can be changed while frozen. The new
+* configuration becomes effective only after the pins are unfrozen.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_IoUnfreeze
+*
+*******************************************************************************/
+void Cy_SysPm_IoUnfreeze(void)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O:
+ * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0,
+ */
+ SRSS->PWR_HIBERNATE = (SRSS->PWR_HIBERNATE & CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS) | CY_SYSPM_PWR_HIBERNATE_UNLOCK;
+
+ /* Lock the hibernate mode:
+ * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0
+ */
+ SRSS->PWR_HIBERNATE &= CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS;
+
+ /* Read register to make sure it is settled */
+ (void) SRSS->PWR_HIBERNATE;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SetVoltageBitForFlash
+****************************************************************************//**
+*
+* The internal function that changes the Vcc setting for the flash.
+*
+* Sets the bit for the flash macro register. This bit should be set when the
+* voltage for the core regulators is less than 0.99 V.
+*
+*******************************************************************************/
+static void SetVoltageBitForFlash(void)
+{
+ FLASHC_FM_CTL->ANA_CTL0 |= _VAL2FLD(FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, 1U);
+}
+
+
+/*******************************************************************************
+* Function Name: ClearVoltageBitForFlash
+****************************************************************************//**
+*
+* This is the internal function that changes the Vcc setting for the flash.
+*
+* Clears the bit for the flash macro register. This bit should
+* be cleared if the output voltage for the core regulators is higher than 0.99 V.
+*
+*******************************************************************************/
+static void ClearVoltageBitForFlash(void)
+{
+ FLASHC_FM_CTL->ANA_CTL0 &= ((uint32_t) (~_VAL2FLD(FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, 1U)));
+}
+
+#ifdef CY_IP_MXUDB
+
+ /*******************************************************************************
+ * Function Name: SaveRegisters
+ ****************************************************************************//**
+ *
+ * The internal function saves non-retained registers before entering Deep Sleep.
+ * Cypress ID #280370.
+ *
+ * \param regs
+ * The structure where the registers are saved before Deep Sleep.
+ *
+ *******************************************************************************/
+ static void SaveRegisters(cy_stc_syspm_backup_regs_t *regs)
+ {
+ /* Save the registers before deep sleep */
+ regs->CY_UDB_UDBIF_BANK_CTL_REG = UDB->UDBIF.BANK_CTL;
+
+ regs->CY_UDB_BCTL_MDCLK_EN_REG = UDB->BCTL.MDCLK_EN;
+ regs->CY_UDB_BCTL_MBCLK_EN_REG = UDB->BCTL.MBCLK_EN;
+ regs->CY_UDB_BCTL_BOTSEL_L_REG = UDB->BCTL.BOTSEL_L;
+ regs->CY_UDB_BCTL_BOTSEL_U_REG = UDB->BCTL.BOTSEL_U;
+ regs->CY_UDB_BCTL_QCLK_EN0_REG = UDB->BCTL.QCLK_EN[0U];
+ regs->CY_UDB_BCTL_QCLK_EN1_REG = UDB->BCTL.QCLK_EN[1U];
+ regs->CY_UDB_BCTL_QCLK_EN2_REG = UDB->BCTL.QCLK_EN[2U];
+ }
+
+
+ /*******************************************************************************
+ * Function Name: RestoreRegisters
+ ****************************************************************************//**
+ *
+ * The internal function restores the non-retained registers after
+ * leaving the Deep Sleep power mode. Cypress ID #280370.
+ *
+ * \param regs
+ * The structure with data stored into the required non-retained registers
+ * after Deep Sleep.
+ *
+ *******************************************************************************/
+ static void RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs)
+ {
+ /* Restore the registers after deep sleep */
+ UDB->BCTL.MDCLK_EN = regs->CY_UDB_BCTL_MDCLK_EN_REG;
+ UDB->BCTL.MBCLK_EN = regs->CY_UDB_BCTL_MBCLK_EN_REG;
+ UDB->BCTL.BOTSEL_L = regs->CY_UDB_BCTL_BOTSEL_L_REG;
+ UDB->BCTL.BOTSEL_U = regs->CY_UDB_BCTL_BOTSEL_U_REG;
+ UDB->BCTL.QCLK_EN[0U] = regs->CY_UDB_BCTL_QCLK_EN0_REG;
+ UDB->BCTL.QCLK_EN[1U] = regs->CY_UDB_BCTL_QCLK_EN1_REG;
+ UDB->BCTL.QCLK_EN[2U] = regs->CY_UDB_BCTL_QCLK_EN2_REG;
+
+ UDB->UDBIF.BANK_CTL = regs->CY_UDB_UDBIF_BANK_CTL_REG;
+ }
+#endif /* CY_IP_MXUDB */
+
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
+
+ /*******************************************************************************
+ * Function Name: Cy_EnterDeepSleep
+ ****************************************************************************//**
+ *
+ * The internal function that prepares the system for Deep Sleep and
+ * restores the system after a wakeup from Deep Sleep.
+ *
+ * \param waitFor Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+ *
+ *******************************************************************************/
+ #if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+ #else
+ CY_SECTION(".cy_ramfunc") CY_NOINLINE
+ #endif
+ static void Cy_EnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
+ {
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while(0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, SYSPM_IPC_STC->ACQUIRE))
+ {
+ /* Wait until the IPC structure is released by another core */
+ }
+
+ /* Set the flag that current core entered Deep Sleep */
+ SYSPM_IPC_STC->DATA |= CUR_CORE_DP_MASK;
+
+ /* Change the slow and fast clock dividers only under condition that
+ * the other core is already in Deep Sleep. Cypress ID #284516
+ */
+ if (0U != (SYSPM_IPC_STC->DATA & OTHER_CORE_DP_MASK))
+ {
+ /* Get the divider values of the slow and high clocks and store them into
+ * the IPC data register
+ */
+ SYSPM_IPC_STC->DATA =
+ (SYSPM_IPC_STC->DATA & ((uint32_t) ~(SYSPM_FAST_CLK_DIV_Msk | SYSPM_SLOW_CLK_DIV_Msk))) |
+ (((uint32_t)(_FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL) << SYSPM_SLOW_CLK_DIV_Pos)) |
+ ((uint32_t)(_FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL) << SYSPM_FAST_CLK_DIV_Pos)));
+
+ /* Increase the clock divider for the slow and fast clocks to SYSPM_CLK_DIVIDER */
+ CPUSS->CM0_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER);
+
+ CPUSS->CM4_CLOCK_CTL =
+ _CLR_SET_FLD32U(CPUSS->CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER);
+
+ /* Read the divider value to make sure it is set */
+ (void) CPUSS->CM0_CLOCK_CTL;
+ (void) CPUSS->CM4_CLOCK_CTL;
+ }
+
+ /* Release the IPC */
+ SYSPM_IPC_STC->RELEASE = 0U;
+
+ /* Read this register to make sure it is settled */
+ (void) SYSPM_IPC_STC->RELEASE;
+
+ #if(0u != CY_CPU_CORTEX_M0P)
+
+ /* The CPU enters the Deep Sleep mode upon execution of WFI/WFE */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+ }
+ #else
+
+ /* Repeat the WFI/WFE instructions if a wake up was not intended.
+ * Cypress ID #272909
+ */
+ do
+ {
+ /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+
+ /* Call the WFE instructions twice to clear the Event register
+ * of the CM4 core. Cypress ID #279077
+ */
+ if(wasEventSent)
+ {
+ __WFE();
+ }
+
+ wasEventSent = true;
+ }
+ } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, CPUSS->CM4_PWR_CTL) == CY_SYSPM_CM4_PWR_RETAINED);
+
+ #endif /* (0u != CY_CPU_CORTEX_M0P) */
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time */
+ while(0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, SYSPM_IPC_STC->ACQUIRE))
+ {
+ /* Wait until the IPC structure is released by another core */
+ }
+
+ /* Read and change the slow and fast clock dividers only under condition
+ * that the other core is already in Deep Sleep. Cypress ID #284516
+ */
+ if(0U != (SYSPM_IPC_STC->DATA & OTHER_CORE_DP_MASK))
+ {
+ /* Restore the clock dividers for the slow and fast clocks */
+ CPUSS->CM0_CLOCK_CTL =
+ (_CLR_SET_FLD32U(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV,
+ (_FLD2VAL(SYSPM_SLOW_CLK_DIV, SYSPM_IPC_STC->DATA))));
+
+ CPUSS->CM4_CLOCK_CTL =
+ (_CLR_SET_FLD32U(CPUSS->CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV,
+ (_FLD2VAL(SYSPM_FAST_CLK_DIV, SYSPM_IPC_STC->DATA))));
+ }
+
+ /* Indicate that the current core is out of Deep Sleep */
+ SYSPM_IPC_STC->DATA &= ((uint32_t) ~CUR_CORE_DP_MASK);
+
+ /* Release the IPC */
+ SYSPM_IPC_STC->RELEASE = 0U;
+ }
+ #if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+ #endif
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+
+
+/*******************************************************************************
+* Function Name: EnterDeepSleep
+****************************************************************************//**
+*
+* The internal function that prepares the system for Deep Sleep,
+* sets the CPU core to the Deep Sleep, and restores the system after a
+* wakeup from Deep Sleep.
+*
+* \param waitFor
+* Selects wait for action. See \ref cy_en_syspm_waitfor_t.
+*
+*******************************************************************************/
+#if defined (__ICCARM__)
+ #pragma diag_suppress=Ta023
+ __ramfunc
+#else
+ CY_SECTION(".cy_ramfunc") CY_NOINLINE
+#endif
+static void EnterDeepSleep(cy_en_syspm_waitfor_t waitFor)
+{
+#if(0u != CY_CPU_CORTEX_M0P)
+
+ /* The CPU enters the Deep Sleep mode upon execution of WFI/WFE */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+ }
+#else
+
+ /* Repeat the WFI/WFE instructions if a wake up was not intended.
+ * Cypress ID #272909
+ */
+ do
+ {
+ /* The CPU enters Deep Sleep mode upon execution of WFI/WFE */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ if(waitFor != CY_SYSPM_WAIT_FOR_EVENT)
+ {
+ __WFI();
+ }
+ else
+ {
+ __WFE();
+
+ /* Call the WFE instructions twice to clear the Event register
+ * of the CM4 core. Cypress ID #279077
+ */
+ if(wasEventSent)
+ {
+ __WFE();
+ }
+
+ wasEventSent = true;
+ }
+ } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, CPUSS->CM4_PWR_CTL) == CY_SYSPM_CM4_PWR_RETAINED);
+
+#endif /* (0u != CY_CPU_CORTEX_M0P) */
+
+ /* Acquire the IPC to prevent changing of the shared resources at the same time.
+ * Shared resources is the BIST_DATA[0] register.
+ */
+ while(0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, SYSPM_IPC_STC->ACQUIRE))
+ {
+ /* Wait until the IPC structure is released by another core */
+ }
+
+ /* Set 10 uS delay only under condition that the DELAY_DONE_FLAG is
+ * cleared. Cypress ID #288510
+ */
+ if(DELAY_DONE_FLAG->BIST_DATA[0] == NEED_DELAY)
+ {
+ /* Configure the counter to be sourced by IMO */
+ TST_DDFT_SLOW_CTL_REG = TST_DDFT_SLOW_CTL_MASK;
+ CLK_OUTPUT_SLOW_REG = CLK_OUTPUT_SLOW_MASK;
+ TST_DDFT_FAST_CTL_REG = TST_DDFT_FAST_CTL_MASK;
+
+ /* Load the down-counter to count the 10 uS */
+ CLK_CAL_CNT1_REG = IMO_10US_DELAY;
+
+ while(0U == (CLK_CAL_CNT1_REG & CLK_CAL_CNT1_DONE))
+ {
+ /* Wait until the counter stops counting */
+ }
+
+ /* Indicate that 10 uS delay was done */
+ DELAY_DONE_FLAG->BIST_DATA[0] = DELAY_DONE;
+ }
+
+ /* Release the IPC structure in do while loop just to sure that this code
+ * is not optimized
+ */
+ do
+ {
+ SYSPM_IPC_STC->RELEASE = 0U;
+ } while (0U != 0U);
+}
+#if defined (__ICCARM__)
+ #pragma diag_default=Ta023
+#endif
+
+
+/*******************************************************************************
+* Function Name: SetReadMarginTrimUlp
+****************************************************************************//**
+*
+* This is the internal function that updates the read-margin trim values for the
+* RAM and ROM. The trim update is done during transition of regulator voltage
+* from higher to a lower one.
+*
+*******************************************************************************/
+static void SetReadMarginTrimUlp(void)
+{
+ /* Update read-write margin value for the ULP mode. Cypress ID#297292 */
+ CPUSS->TRIM_RAM_CTL = (CPUSS->TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_RM_Msk);
+
+ CPUSS->TRIM_ROM_CTL = (CPUSS->TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_ROM_ULP & CPUSS_TRIM_ROM_CTL_RM_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: SetReadMarginTrimLp
+****************************************************************************//**
+*
+* The internal function which updates the read-margin trim values for the
+* RAM and ROM. The trim update is done during transition of regulator voltage
+* from lower to a higher one.
+*
+*******************************************************************************/
+static void SetReadMarginTrimLp(void)
+{
+ /* Update read-write margin value for the LP mode. Cypress ID#297292 */
+ CPUSS->TRIM_RAM_CTL = (CPUSS->TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_RM_Msk);
+
+ CPUSS->TRIM_ROM_CTL = (CPUSS->TRIM_ROM_CTL & ((uint32_t) ~CPUSS_TRIM_ROM_CTL_RM_Msk)) |
+ (CPUSS_TRIM_ROM_LP & CPUSS_TRIM_ROM_CTL_RM_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: SetWriteAssistTrimUlp
+****************************************************************************//**
+*
+* This is the internal function that updates the write assistant trim value for the
+* RAM. The trim update is done during transition of regulator voltage
+* from higher to a lower.
+*
+*******************************************************************************/
+static void SetWriteAssistTrimUlp(void)
+{
+ /* Update write assist value for the ULP mode. Cypress ID#297292 */
+ CPUSS->TRIM_RAM_CTL = (CPUSS->TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) |
+ (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_WA_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: SetWriteAssistTrimLp
+****************************************************************************//**
+*
+* This is the internal function that updates the write assistant trim value for the
+* RAM. The trim update is done during transition of regulator voltage
+* from lower to a higher one.
+*
+*******************************************************************************/
+static void SetWriteAssistTrimLp(void)
+{
+ /* Update write assist value for the LP mode. Cypress ID#297292 */
+ CPUSS->TRIM_RAM_CTL = (CPUSS->TRIM_RAM_CTL & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_WA_Msk)) |
+ (CPUSS_TRIM_RAM_LP & CPUSS_TRIM_RAM_CTL_WA_Msk);
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/syspm/cy_syspm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2261 @@
+/***************************************************************************//**
+* \file cy_syspm.h
+* \version 2.10
+*
+* Provides the function definitions for the power management API.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*
+*******************************************************************************/
+
+/**
+* \defgroup group_syspm System Power Management (SysPm)
+* \{
+*
+* Use the System Power Management (SysPm) driver to enter low-power modes and
+* reduce system power consumption in power sensitive designs. For multi-core
+* devices, this library allows you to individually enter low-power modes for
+* each core.
+*
+* This document contains the following topics:
+*
+* * \ref group_syspm_power_modes
+* * \ref group_syspm_device_power_modes
+* - \ref group_syspm_switching_into_lpactive
+* - \ref group_syspm_switching_from_lpactive
+* - \ref group_syspm_switching_into_sleep_deepsleep
+* - \ref group_syspm_wakingup_from_sleep_deepsleep
+* - \ref group_syspm_switching_into_hibernate
+* - \ref group_syspm_wakingup_from_hibernate
+* * \ref group_syspm_managing_core_regulators
+* - \ref group_syspm_ulp_limitations
+* - \ref group_syspm_lp_limitations
+* * \ref group_syspm_managing_pmic
+* * \ref group_syspm_managing_backup_domain
+* * \ref group_syspm_cb
+* - \ref group_syspm_cb_example
+* - \ref group_syspm_cb_config_consideration
+* - \ref group_syspm_cb_parameters
+* - \ref group_syspm_cb_structures
+* - \ref group_syspm_cb_function_implementation
+* - \ref group_syspm_cb_flow
+* - \ref group_syspm_cb_uregistering
+* * \ref group_syspm_definitions
+*
+* \section group_syspm_section_configuration Configuration Considerations
+* \subsection group_syspm_power_modes Power Modes
+* PSoC 6 MCUs support the following power modes (in the order of high-to-low
+* power consumption): Active, Low-Power (LPActive), Deep Sleep, and Hibernate.
+* The core(s) can also be in Arm-defined power modes - Active, Sleep,
+* and Deep Sleep.
+*
+* \subsection group_syspm_device_power_modes Device Power Modes
+* * <b>Active</b> - In this mode the code is executed, and all logic and
+* memories are powered. Firmware may disable clocks for specific peripherals
+* and power down specific analog power domains.
+*
+* * <b>LPActive</b> - Low-Power mode is like Active mode, but with clock
+* restrictions and limited/slower peripherals to achieve a lower system current.
+* Refer to \ref group_syspm_switching_into_lpactive in Configuration
+* considerations.
+*
+* * <b>Deep Sleep</b> - is a lower power mode where high-frequency clocks are
+* disabled. Deep-Sleep-capable peripherals are available. A normal wakeup from
+* Deep Sleep returns to either LPActive, Active, or Sleep, depending on the
+* previous state and programmed behavior for the configured wakeup interrupt.
+* Likewise, a debug wakeup from Deep Sleep returns to Sleep, depending on which
+* mode was used to enter the Deep Sleep power mode.
+*
+* * <b>Hibernate</b> - is an even lower power mode that is entered from
+* firmware, just like Deep Sleep. However, on a wakeup the core and all
+* peripherals go through a full reset. The I/O's state is frozen so that the
+* output driver state is held. Note that in this mode, the core(s) and all
+* peripherals lose their states, so the system and firmware reboot on a wakeup
+* event. Backup memory (if present) can be used to store system states for use
+* on the next reboot.
+*
+* \subsubsection group_syspm_switching_into_lpactive Switching Device into LPActive
+* Before switching into the LPActive power mode, ensure that the device meets
+* the current load limitation. Decrease the clock frequencies, and slow or
+* disable peripherals. Refer to the \ref group_syspm_managing_core_regulators
+* Section. <br>
+* * The IMO is set to the Clk_HF
+*
+* * Turn off unused peripherals, or decrease their operating frequencies to
+* achieve total current consumption less than or equal to 20 mA.
+*
+* * Call the Cy_SysPm_EnterLowPowerMode() function that will put references
+* such as POR and BOD into Low-Power mode.
+*
+* * If the core is sourced by the LDO Core Voltage Regulator, then the
+* 0.9 V (nominal) mode must be set. Refer \ref group_syspm_functions_ldo API
+* in \ref group_syspm_functions_core_regulators.
+*
+* * If the core is sourced by the Buck Core Voltage Regulator, then it is
+* recommended, but not required, to set CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V.
+* Decide whether your application can meet the requirements for the
+* CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V.
+* See \ref group_syspm_managing_core_regulators.
+*
+* \subsubsection group_syspm_switching_from_lpactive Switching Device from LPActive
+* To switch a device from LPActive to Active mode, just
+* call Cy_SysPm_ExitLowPowerMode().
+*
+* \subsubsection group_syspm_switching_into_sleep_deepsleep Switching Device or Core to Sleep or Deep Sleep
+* For multi-core devices, the Cy_SysPm_Sleep() and Cy_SysPm_DeepSleep()
+* functions switch only the core that calls the function into the Sleep or
+* the Deep Sleep power mode. To set the whole device in the Sleep or Deep Sleep
+* power mode, ensure that each core calls the Cy_SysPm_Sleep() or
+* Cy_SysPm_DeepSleep() function.
+*
+* There are situations when the device does not switch into the Deep Sleep
+* power mode immediately after the second core calls Cy_SysPm_DeepSleep().
+* The device will switch into Deep Sleep mode automatically a little bit later,
+* after the low-power circuits are ready to switch into Deep Sleep. Refer to
+* the Cy_SysPm_DeepSleep() description for more details.
+*
+* All pending interrupts should be cleared before the device is put into a
+* Sleep or Deep Sleep mode, even if they are masked.
+*
+* For single-core devices, SysPm functions that return the status of the
+* unsupported core always return CY_SYSPM_STATUS_<CORE>_DEEPSLEEP.
+*
+* \subsubsection group_syspm_wakingup_from_sleep_deepsleep Waking Up from Sleep or Deep Sleep
+* For Arm-based devices, an interrupt is required for the core to wake up.
+* For multi-core devices, one core can wake up the other core by sending the
+* event instruction. Use the CMSIS function __SEV() to sent event from one core
+* to another.
+*
+* \subsubsection group_syspm_switching_into_hibernate Switching Device to Hibernate
+* If you call Cy_SysPm_Hibernate() from either core, the device will be switched
+* into the Hibernate power mode directly, as there is no
+* handshake between cores.
+*
+* \subsubsection group_syspm_wakingup_from_hibernate Waking Up from Hibernate
+*
+* The system can wake up from Hibernate mode by configuring:
+*
+* * Wakeup pin
+*
+* * LP Comparator
+*
+* * RTC alarm
+*
+* * WDT interrupt
+*
+* Wakeup is supported from device specific pin(s) with programmable polarity.
+* Additionally, unregulated peripherals can wake the device under some
+* conditions. For example, a low-power comparator can wake the device by
+* comparing two external voltages but may not support comparison to an
+* internally-generated voltage. The Backup domain remains functional, and if
+* present it can schedule an alarm to wake the device from Hibernate using RTC.
+* Alternatively, the Watchdog Timer (WDT) can be configured to wake-up the
+* device by WDT interrupt.
+* Refer to \ref Cy_SysPm_SetHibernateWakeupSource() for more details.
+*
+* \subsection group_syspm_managing_core_regulators Managing Core Voltage Regulators
+* The SysPm driver provides functionality to manage the power modes of the
+* low-dropout (LDO) and Buck Core Voltage Regulators.
+* For both core regulators, two voltages are possible:
+*
+* * <b>0.9 V (nominal)</b> - core is sourced by 0.9 V (nominal). This core regulator
+* power mode is called Ultra Low-Power (ULP). In this mode, the device
+* functionality and performance is limited. You must decrease the operating
+* frequency and current consumption to meet the
+* \ref group_syspm_ulp_limitations, shown below.
+* * <b>1.1 V (nominal)</b> - core is sourced by 1.1 V (nominal). This core regulator
+* power mode is called low-power mode (LP). In this mode, you must meet the
+* \ref group_syspm_lp_limitations, shown below.
+*
+* \subsubsection group_syspm_ulp_limitations ULP Limitations
+* When the core voltage is <b>0.9 V (nominal)</b> the next limitations must be
+* meet: <br>
+* - the maximum operating frequency for all Clk_HF paths must not exceed
+* <b>50 MHz</b>, whereas the peripheral and slow clock must not exceed <b>25 MHz</b>
+* (refer to \ref group_sysclk driver documentation).
+* - the total current consumption must be less than or equal to <b>20 mA</b><br>
+*
+* \subsubsection group_syspm_lp_limitations LP Limitations
+* When the core voltage is <b>1.1V (nominal)</b> the next limitations must be meet:
+* - the maximum operating frequency for all Clk_HF paths must not exceed
+* <b>150 MHz</b>, whereas the peripheral and slow clock must not exceed <b>100 MHz</b>
+* (refer to \ref group_sysclk driver documentation). <br>
+* - the total current consumption must be less than or equal to <b>250 mA</b>
+*
+* \subsection group_syspm_managing_pmic Managing PMIC
+*
+* The SysPm driver also provides an API to configure the external power
+* management integrated circuit (PMIC) that supplies Vddd.
+* Use the API to enable the PMIC output that is routed to pmic_wakeup_out pin,
+* and configure the polarity of the PMIC input (pmic_wakeup_in) that is used to
+* wake up the PMIC.
+*
+* The PMIC is automatically enabled when:
+*
+* * the PMIC is locked by a call to Cy_SysPm_PmicLock()
+*
+* * the configured polarity of the PMIC input and the polarity driven to
+* pmic_wakeup_in pin matches.
+*
+* Because a call to Cy_SysPm_PmicLock() automatically enables the PMIC, the PMIC
+* can remain disabled only when it is unlocked. See Cy_SysPm_PmicUnlock()
+* for more details.
+*
+* Use Cy_SysPm_PmicIsLocked() to read the current PMIC lock status.
+*
+* To enable the PMIC, use these functions in this order:<br>
+* \code{.c}
+* 1 Cy_SysPm_PmicUnlock();
+* 2 Cy_SysPm_PmicEnable();
+* 3 Cy_SysPm_PmicLock();
+* \endcode
+*
+* To disable the PMIC block, unlock the PMIC. Then call Cy_SysPm_PmicDisable()
+* with the inverted value of the current active state of the pmic_wakeup_in pin.
+* For example, assume the current state of the pmic_wakeup_in pin is active low.
+* To disable the PMIC, call these functions in this order:<br>
+* \code{.c}
+* 1 Cy_SysPm_PmicUnlock();
+* 2 Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_HIGH);
+* \endcode
+* Note that you do not call Cy_SysPm_PmicLock(), because that automatically
+* enables the PMIC.
+*
+* While disabled, the PMIC block is automatically enabled when the
+* pmic_wakeup_in pin state is changed into high state.
+*
+* To disable the PMIC output, call these functions in this order:
+* Cy_SysPm_PmicUnlock();
+* Cy_SysPm_PmicDisableOutput();
+*
+* Do not call Cy_SysPm_PmicLock() (which automatically enables the PMIC output).
+*
+* When disabled, the PMIC output is enabled when the PMIC is locked, or by
+* calling Cy_SysPm_PmicEnableOutput().
+*
+* \subsection group_syspm_managing_backup_domain Managing the Backup Domain
+* The SysPm driver provide functions to:
+*
+* * Configure supercapacitor charge
+*
+* * Select power supply (Vbackup or Vddd) for the Vddbackup
+*
+* * Measure Vddbackup using the ADC
+*
+* Refer to the \ref group_syspm_functions_backup functions for more details.
+*
+* \subsection group_syspm_cb SysPm Callbacks
+* The SysPm driver handles the low power callbacks declared in the application.
+*
+* If there are no callbacks registered, the device just executes the power mode
+* transition. However, it is often the case that your firmware must prepare for
+* low power mode. For example, you may need to disable a peripheral, or ensure
+* that a message is not being transmitted or received.
+*
+* To enable this, the SysPm driver implements a callback mechanism. When a lower
+* power mode transition is about to take place (either entering or exiting
+* \ref group_syspm_device_power_modes), the registered callbacks are called.
+*
+* The SysPm driver organizes all the callbacks into a linked list. While
+* entering a low-power mode, SysPm goes through that linked list from first to
+* last, executing the callbacks one after another. While exiting low-power mode,
+* SysPm goes through that linked list again, but in the opposite direction from
+* last to first.
+*
+* For example, the picture below shows three callback structures organized into
+* a linked list: myDeepSleep1, mySleep1, myDeepSleep2 (represented with the
+* \ref cy_stc_syspm_callback_t configuration structure). Each structure
+* contains, among other fields, the address of the callback function. The code
+* snippets below set this up so that myDeepSleep1 is called first when entering
+* the low-power mode. This also means that myDeepSleep1 will be the last one to
+* execute when exiting the low-power mode.
+*
+* The callback structures after registration:
+* \image html syspm_2_10_after_registration.png
+*
+* Your application must register each callback, so that SysPm can execute it.
+* Upon registration, the linked list is built by the SysPm driver. Notice
+* the &mySleep1 address in the myDeepSleep1
+* \ref cy_stc_syspm_callback_t structure. This is filled in by the SysPm driver
+* when you register mySleep1. The order in which the callbacks are registered in
+* the application defines the order of their execution by the SysPm driver. You
+* may have up to 32 callback functions registered.
+* Call \ref Cy_SysPm_RegisterCallback() to register each callback function.
+*
+* A callback function is typically associated with a particular driver that
+* handles the peripheral. So the callback mechanism enables a peripheral to
+* prepare for a low-power mode (for instance, shutting down the analog part);
+* or to perform tasks while exiting a low-power mode (like enabling the analog
+* part again).
+*
+* With the callback mechanism you can prevent switching into a low-power mode if
+* a peripheral is not ready. For example, driver X is in the process of
+* receiving a message. In the callback function implementation simply return
+* CY_SYSPM_FAIL in a response to CY_SYSPM_CHECK_READY.
+*
+* If success is returned while executing a callback, the SysPm driver calls the
+* next callback and so on to the end of the list. If at some point a callback
+* returns CY_SYSPM_FAIL in response to the CY_SYSPM_CHECK_READY step, all the
+* callbacks that have already executed are executed in reverse order, with the
+* CY_SYSPM_CHECK_FAIL step. This allows each callback to know that entering the
+* low-power mode has failed. The callback can then undo whatever it did to
+* prepare for low power mode. For example, if the driver X callback shut down
+* the analog part, it can re-enable the analog part.
+*
+* Let's switch to an example explaining the implementation, setup, and
+* registration of three callbacks (myDeepSleep1, mySleep1, myDeepSleep2) in the
+* application. The \ref group_syspm_cb_config_consideration are provided after
+* the \ref group_syspm_cb_example.
+*
+* \subsection group_syspm_cb_example SysPm Callbacks Example
+*
+* The following code snippets demonstrate how use the SysPm callbacks mechanism.
+* We will build the prototype for an application that registers
+* three callback functions: <br>
+* 1. mySleep1 - handles Sleep <br>
+* 2. myDeepSleep1 - handles Deep Sleep and is associated with peripheral
+* HW1_address (see <a href="..\..\pdl_user_guide.pdf">PDL Design</a>
+* section to learn about the base hardware
+* address) <br>
+* 3. myDeepSleep2 - handles entering and exiting Deep Sleep and is
+* associated with peripheral HW2_address <br>
+*
+* We set things up so that the mySleep1 and myDeepSleep1 callbacks do nothing
+* while entering the low power mode (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION -
+* see \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration).
+* Skipping the actions while entering low power might be useful if you need
+* to save the time while switching low-power modes. This is because the callback
+* function with skipped mode is not even called.
+*
+* Let's first declare the callback functions. Each gets the pointer to the
+* \ref cy_stc_syspm_callback_params_t structure as the argument.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Func_Declaration
+*
+* Now we setup the \ref cy_stc_syspm_callback_params_t structures that we will
+* pass to callback functions. Note that for the myDeepSleep1 and myDeepSleep2
+* callbacks we also pass the pointers to the peripherals related to that
+* callback (see <a href="..\..\pdl_user_guide.pdf">PDL Design</a> section to
+* learn about the base hardware address).
+* The configuration considerations related to this structure are described
+* in \ref group_syspm_cb_parameters in \ref group_syspm_cb_config_consideration.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Params_Declaration
+*
+* Now we setup the actual callback configuration structures. Each of these
+* contains, among the other fields, the address of the
+* \ref cy_stc_syspm_callback_params_t we just set up. We will use the callback
+* configuration structures later in the code to register the callbacks in the
+* SysPm driver. Again, we set things up so that the mySleep1 and myDeepSleep1
+* callbacks do nothing while entering the low power mode
+* (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION) - see
+* \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Structure_Declaration
+*
+* Note that in each case the last two fields are NULL. These are fields used by
+* the SysPm driver to set up the linked list of callback functions.
+*
+* The callback structures are now defined and allocated in the user's
+* memory space:
+* \image html syspm_2_10_before_registration.png
+*
+* Now we implement the callback functions. See
+* \ref group_syspm_cb_function_implementation in
+* \ref group_syspm_cb_config_consideration for the instructions on how the
+* callback functions should be implemented.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Callback_Func_Implementation
+*
+* Finally, we register the callbacks so that the SysPm driver knows about them.
+* The order in which the callbacks will be called depends upon the order in
+* which the callbacks are registered. If there are no callbacks registered,
+* the device just executes the power mode transition.
+*
+* Callbacks that reconfigure global resources, such as clock frequencies, should
+* be registered last. They then modify global resources as the final step before
+* entering the low power mode, and restore those resources first, as the system
+* returns from low-power mode.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_RegisterCallback
+*
+* We are done configuring three callbacks. Now the SysPm driver will execute the
+* callbacks appropriately whenever there is a call to a power mode transition
+* function: \ref Cy_SysPm_Sleep(), \ref Cy_SysPm_DeepSleep(),
+* \ref Cy_SysPm_EnterLowPowerMode(), \ref Cy_SysPm_ExitLowPowerMode(), and
+* \ref Cy_SysPm_Hibernate().
+* \note On a wakeup from hibernate the device goes through a reset, so the
+* callbacks with CY_SYSPM_AFTER_TRANSITION are not executed. Refer to
+* \ref Cy_SysPm_Hibernate() for more details.
+*
+* Refer to \ref group_syspm_cb_uregistering in
+* \ref group_syspm_cb_config_consideration to learn what to do if you need to
+* remove the callback from the linked list. You might want to unregister the
+* callback for debug purposes.
+*
+* Refer to \ref group_syspm_cb_flow in \ref group_syspm_cb_config_consideration
+* to learn about how the SysPm is processing the callbacks.
+*
+* \subsection group_syspm_cb_config_consideration Callback Configuration Considerations
+*
+* \subsubsection group_syspm_cb_parameters Callback Function Parameters
+*
+* The <b>callbackParams</b> parameter of the callback function is a
+* \ref cy_stc_syspm_callback_params_t structure. The first field in this
+* structure (<b>mode</b>) is for internal use. In the example code we used a
+* dummy value CY_SYSPM_CHECK_READY to eliminate compilation errors associated
+* with the enumeration. The driver sets the <b>mode</b> field to the correct
+* value when calling the callback functions (the mode is referred to as step in
+* the \ref group_syspm_cb_function_implementation). The callback function reads
+* the value and acts based on the mode set by the SysPm driver. The <b>base</b>
+* and <b>context</b> fields are optional and can be NULL. Some drivers require a
+* base hardware address and a context. If your callback routine needs access to
+* the driver registers or context, provide those values (see
+* <a href="..\..\pdl_user_guide.pdf">PDL Design</a> section
+* to learn about Base Hardware Address). Be aware of MISRA warnings if these
+* parameters are NULL.
+*
+* \subsubsection group_syspm_cb_structures Callback Function Structure
+* For each callback, provide a \ref cy_stc_syspm_callback_t structure. Some
+* fields in this structure are maintained by the driver. Use NULL for
+* <b>prevItm</b> and <b>nextItm</b>. The driver uses these fields to build a
+* linked list of callback functions.
+*
+* \warning The Cy_SysPm_RegisterCallback() function stores a pointer to the
+* cy_stc_syspm_callback_t variable. Do not modify elements of the
+* cy_stc_syspm_callback_t structure after the callback is registered.
+* You are responsible for ensuring that the variable remains in scope.
+* Typically the structure is declared as a global or static variable, or as a
+* local variable in the main() function.
+*
+* \subsubsection group_syspm_cb_function_implementation Callback Function Implementation
+*
+* Every callback function should handle four possible steps (referred to as
+* "mode") defined in \ref cy_en_syspm_callback_mode_t : <br>
+* * CY_SYSPM_CHECK_READY - prepare for entering a low power mode<br>
+* * CY_SYSPM_BEFORE_TRANSITION - The actions to be done before entering
+* the low-power mode <br>
+* * CY_SYSPM_AFTER_TRANSITION - The actions to be done after exiting the
+* low-power mode <br>
+* * CY_SYSPM_CHECK_FAIL - roll back the actions done in the callbacks
+* executed previously with CY_SYSPM_CHECK_READY <br>
+*
+* A callback function can skip steps (see \ref group_syspm_skip_callback_modes).
+* In our example mySleep1 and myDeepSleep1 callbacks do nothing while entering
+* the low power mode (skip on CY_SYSPM_BEFORE_TRANSITION). If there is anything
+* preventing low power mode entry - return CY_SYSPM_FAIL in response to
+* CY_SYSPM_CHECK_READY in your callback implementation. Note that the callback
+* should return CY_SYSPM_FAIL only in response to CY_SYSPM_CHECK_READY. The
+* callback function should always return CY_SYSPM_PASS for other modes:
+* CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION
+* (see \ref group_syspm_cb_flow).
+*
+* \subsubsection group_syspm_cb_flow Callbacks Execution Flow
+*
+* This section explains what happens during a power transition, when callbacks
+* are implemented and set up correctly. The following discussion assumes: <br>
+* * All required callback functions are defined and implemented <br>
+* * All cy_stc_syspm_callback_t structures are filled with required values <br>
+* * All callbacks are successfully registered
+*
+* User calls one of the power mode transition functions: \ref Cy_SysPm_Sleep(),
+* \ref Cy_SysPm_DeepSleep(), \ref Cy_SysPm_EnterLowPowerMode(),
+* \ref Cy_SysPm_ExitLowPowerMode(), and \ref Cy_SysPm_Hibernate().
+* It calls each callback with the mode set to CY_SYSPM_CHECK_READY. This
+* triggers execution of the code for that step inside of each user callback.
+*
+* If that process is successful for all callbacks, then
+* \ref Cy_SysPm_ExecuteCallback() calls each callback with the mode set to
+* CY_SYSPM_BEFORE_TRANSITION. This triggers execution of the code for that step
+* inside each user callback. We then enter the low power mode.
+*
+* When exiting the low power mode, the SysPm driver executes
+* \ref Cy_SysPm_ExecuteCallback() again. This time it calls each callback in
+* reverse order, with the mode set to CY_SYSPM_AFTER_TRANSITION. This triggers
+* execution of the code for that step inside each user callback. When complete,
+* we are back to Active state.
+*
+* A callback can return CY_SYSPM_FAIL only while executing the
+* CY_SYSPM_CHECK_READY step. If that happens, then the remaining callbacks are
+* not executed. Any callbacks that have already executed are called again, in
+* reverse order, with CY_SYSPM_CHECK_FAIL. This allows the system to return to
+* the previous state. Then any of the functions (\ref Cy_SysPm_Sleep(),
+* \ref Cy_SysPm_DeepSleep(), \ref Cy_SysPm_EnterLowPowerMode(),
+* \ref Cy_SysPm_ExitLowPowerMode(), and \ref Cy_SysPm_Hibernate()) that
+* attempted to switch the device into a low power mode will
+* return CY_SYSPM_FAIL.
+*
+* Callbacks that reconfigure global resources, such as clock frequencies,
+* should be registered last. They then modify global resources as the final
+* step before entering the low power mode, and restore those resources first,
+* as the system returns from Low-power mode.
+*
+* \subsubsection group_syspm_cb_uregistering Callback Unregistering
+*
+* Unregistering the callback might be useful when you need dynamically manage
+* the callbacks.
+*
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_UnregisterCallback
+* The callback structures after mySleep1 callback is unregistered:
+* \image html syspm_2_10_unregistration.png
+*
+* \section group_syspm_definitions Definitions
+*
+* <table class="doxtable">
+* <tr>
+* <th>Term</th>
+* <th>Definition</th>
+* </tr>
+*
+* <tr>
+* <td>LDO</td>
+* <td>Low Dropout Linear Regulator (LDO). The functions that manage this
+* block are grouped as \ref group_syspm_functions_ldo under
+* \ref group_syspm_functions_core_regulators</td>
+* </tr>
+*
+* <tr>
+* <td>SIMO Buck</td>
+* <td>Single Inductor Multiple Output Buck Regulator, referred as
+* "Buck regulator" throughout the documentation. The functions that
+* manage this block are grouped as \ref group_syspm_functions_buck under
+* \ref group_syspm_functions_core_regulators</td>
+* </tr>
+*
+* <tr>
+* <td>PMIC</td>
+* <td>Power Management Integrated Circuit. The functions that manage this
+* block are grouped as \ref group_syspm_functions_pmic</td>
+* </tr>
+*
+* <tr>
+* <td>LPActive</td>
+* <td>Low-Power Active mode. The MCU power mode.
+* See the \ref group_syspm_switching_into_lpactive
+* section for details</td>
+* </tr>
+* </table>
+*
+* \section group_syspm_section_more_information More Information
+* For more information on the Power Management (SysPm) driver,
+* refer to the technical reference manual (TRM).
+*
+* \section group_syspm_MISRA MISRA-C Compliance
+* The SysPm driver does not have any specific deviations.
+*
+* \section group_syspm_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>2.10</td>
+* <td> <br>
+* * Changed names for all Backup, Buck-related functions, defines,
+* and enums <br>
+* * Changed next power mode function names: <br>
+* Cy_SysPm_EnterLpMode <br>
+* Cy_SysPm_ExitLpMode <br>
+* Cy_SysPm_SetHibWakeupSource <br>
+* Cy_SysPm_ClearHibWakeupSource <br>
+* Cy_SysPm_GetIoFreezeStatus <br>
+* * Changed following enumeration names: <br>
+* cy_en_syspm_hib_wakeup_source_t <br>
+* cy_en_syspm_simo_buck_voltage1_t <br>
+* cy_en_syspm_simo_buck_voltage2_t <br>
+* * Updated Power Modes documentation section <br>
+* * Added Low Power Callback Managements section <br>
+* * Documentation edits
+* </td>
+* <td>Improvements made based on usability feedback <br>
+* Documentation update and clarification
+* </td>
+* </tr>
+* <tr>
+* <td>2.0</td>
+* <td>Enhancement and defect fixes: <br>
+* * Added input parameter(s) validation to all public functions <br>
+* * Removed "_SysPm_" prefixes from the internal functions names <br>
+* * Changed the type of elements with limited set of values, from
+* uint32_t to enumeration
+* * Enhanced syspm callback mechanism
+* * Added functions to control: <br>
+* * Power supply for the Vddbackup <br>
+* * Supercapacitor charge <br>
+* * Vddbackup measurement by ADC <br>
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_syspm_macros Macros
+* \defgroup group_syspm_functions Functions
+* \{
+* \defgroup group_syspm_functions_power Power Modes
+* \defgroup group_syspm_functions_power_status Power Status
+* \defgroup group_syspm_functions_iofreeze I/Os Freeze
+* \defgroup group_syspm_functions_core_regulators Core Voltage Regulation
+* \{
+* \defgroup group_syspm_functions_ldo LDO
+* \defgroup group_syspm_functions_buck Buck
+* \}
+* \defgroup group_syspm_functions_pmic PMIC
+* \defgroup group_syspm_functions_backup Backup Domain
+* \defgroup group_syspm_functions_callback Low Power Callbacks
+* \}
+* \defgroup group_syspm_data_structures Data Structures
+* \defgroup group_syspm_data_enumerates Enumerated Types
+*/
+
+#if !defined (CY_SYSPM_H)
+#define CY_SYSPM_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Register Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_syspm_macros
+* \{
+*/
+
+/** Driver major version */
+#define CY_SYSPM_DRV_VERSION_MAJOR 2
+
+/** Driver minor version */
+#define CY_SYSPM_DRV_VERSION_MINOR 10
+
+/** syspm driver identifier */
+#define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U))
+
+
+/*******************************************************************************
+* Internal Defines
+*******************************************************************************/
+
+/** \cond INTERNAL */
+
+/* Internal redefine for sflash */
+#define CY_SYSPM_SFLASH SFLASH
+
+/** The internal define of the unlock value for the PMIC functions */
+#define CY_SYSPM_PMIC_UNLOCK_KEY (0x3AU)
+
+/** The internal define of the tries number in the Cy_SysPm_ExitLowPowerMode()
+* function
+*/
+#define CY_SYSPM_WAIT_DELAY_TRYES (100U)
+
+/* Macro to validate parameters in Cy_SysPm_SetHibernateWakeupSource() and for Cy_SysPm_ClearHibernateWakeupSource() function */
+#define CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource) (0UL == ((wakeupSource) & \
+ ((uint32_t) ~(CY_SYSPM_HIB_WAKEUP_SOURSE_MASK))))
+
+/* Macro to validate parameters in Cy_SysPm_PmicDisable() function */
+#define CY_SYSPM_IS_POLARITY_VALID(polarity) (((polarity) == CY_SYSPM_PMIC_POLARITY_LOW) || \
+ ((polarity) == CY_SYSPM_PMIC_POLARITY_HIGH))
+
+/* Macro to validate parameters in Cy_SysPm_BuckSetVoltage1() function */
+#define CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage) (((voltage) == CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V))
+
+/* Macro to validate parameters in Cy_SysPm_BuckSetVoltage2() function */
+#define CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage) (((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V) || \
+ ((voltage) == CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V))
+
+/* Macro to validate parameters in Cy_SysPm_BuckIsOutputEnabled() function */
+#define CY_SYSPM_IS_BUCK_OUTPUT_VALID(output) (((output) == CY_SYSPM_BUCK_VBUCK_1) || \
+ ((output) == CY_SYSPM_BUCK_VRF))
+
+/* Macro to validate parameters in Cy_SysPm_LdoSetVoltage() function */
+#define CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage) (((voltage) == CY_SYSPM_LDO_VOLTAGE_0_9V) || \
+ ((voltage) == CY_SYSPM_LDO_VOLTAGE_1_1V))
+
+/* Macro to validate parameters in Cy_SysPm_ExecuteCallback() function */
+#define CY_SYSPM_IS_CALLBACK_TYPE_VALID(type) (((type) == CY_SYSPM_SLEEP) || \
+ ((type) == CY_SYSPM_DEEPSLEEP) || \
+ ((type) == CY_SYSPM_HIBERNATE) || \
+ ((type) == CY_SYSPM_ENTER_LOWPOWER_MODE) || \
+ ((type) == CY_SYSPM_EXIT_LOWPOWER_MODE))
+
+/* Macro to validate parameters in Cy_SysPm_ExecuteCallback() function */
+#define CY_SYSPM_IS_CALLBACK_MODE_VALID(mode) (((mode) == CY_SYSPM_CHECK_READY) || \
+ ((mode) == CY_SYSPM_CHECK_FAIL) || \
+ ((mode) == CY_SYSPM_BEFORE_TRANSITION) || \
+ ((mode) == CY_SYSPM_AFTER_TRANSITION))
+
+/* Macro to validate parameters in Cy_SysPm_Sleep() and for Cy_SysPm_DeepSleep() function */
+#define CY_SYSPM_IS_WAIT_FOR_VALID(waitFor) (((waitFor) == CY_SYSPM_WAIT_FOR_INTERRUPT) || \
+ ((waitFor) == CY_SYSPM_WAIT_FOR_EVENT))
+
+/* Macro to validate parameters in Cy_SysPm_BackupSetSupply() function */
+#define CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl) (((vddBackControl) == CY_SYSPM_VDDBACKUP_DEFAULT) || \
+ ((vddBackControl) == CY_SYSPM_VDDBACKUP_VBACKUP))
+
+/* Macro to validate parameters in Cy_SysPm_BackupSuperCapCharge() function */
+#define CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key) (((key) == CY_SYSPM_SC_CHARGE_ENABLE) || \
+ ((key) == CY_SYSPM_SC_CHARGE_DISABLE))
+
+#if(0u != SRSS_BUCKCTL_PRESENT)
+
+ /** The definition for the delay of the Buck supply regulator
+ * stabilization after it was configured with enabled Buck output 1 */
+ #define CY_SYSPM_BUCK_CORE_SUPPLY_STABLE_US (900U)
+
+ /** The definition for the delay of the Buck supply regulator
+ * stabilization after it was configured with enabled Buck
+ * output 2 only
+ */
+ #define CY_SYSPM_BUCK_BLE_SUPPLY_STABLE_US (600U)
+
+ /** The definition for the delay of the Buck regulator after its output
+ * voltage is changed
+ */
+ #define BUCK_STABILIZATION_DELAY_US (200U)
+
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+
+/** The wait time for transition of the device from the Active into
+* the LPActive
+*/
+#define CY_SYSPM_ACTIVE_TO_LP_WAIT_US (1U)
+
+/** The wait delay time which occurs before the Active reference is settled.
+* This delay is used in transition of the device from Active into the LPActive
+* low-power mode
+*/
+#define CY_SYSPM_LP_TO_ACTIVE_WAIT_BEFORE_US (8U)
+
+/** The wait delay time which occurs after the Active reference is settled.
+* This delay is used in transition the device from Active into the LPActive
+* mode
+*/
+#define CY_SYSPM_LP_TO_ACTIVE_WAIT_AFTER_US (1U)
+
+/** The maximum callbacks number */
+#define CY_SYSPM_CALLBACKS_NUMBER_MAX (32U)
+
+/** The mask to unlock the Hibernate power mode */
+#define CY_SYSPM_PWR_HIBERNATE_UNLOCK ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos)
+
+/** The mask to set the Hibernate power mode */
+#define CY_SYSPM_PWR_SET_HIBERNATE ((uint32_t) CY_SYSPM_PWR_HIBERNATE_UNLOCK |\
+ SRSS_PWR_HIBERNATE_FREEZE_Msk |\
+ SRSS_PWR_HIBERNATE_HIBERNATE_Msk)
+
+/** The mask to retain the Hibernate power mode status */
+#define CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS ((uint32_t) SRSS_PWR_HIBERNATE_TOKEN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)
+
+/** The mask for the wakeup sources */
+#define CY_SYSPM_PWR_WAKEUP_HIB_MASK ((uint32_t) SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)
+
+/** The define to update the token to indicate the transition into Hibernate */
+#define CY_SYSPM_PWR_TOKEN_HIBERNATE ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos)
+
+/** The internal define of the first wakeup pin bit used in the
+* Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_PIN0_BIT (1UL)
+
+/** The internal define of the second wakeup pin bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_PIN1_BIT (2UL)
+
+/**
+* The internal define of the first LPComparator bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_LPCOMP0_BIT (4UL)
+
+/**
+* The internal define for the second LPComparator bit
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_LPCOMP1_BIT (8UL)
+
+/**
+* The internal define of the first LPComparator value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_LPCOMP0 ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP0_BIT << \
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)
+
+/**
+* The internal define of the second LPComparator value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_LPCOMP1 ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP1_BIT << \
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)
+
+/**
+* The internal define of the first wake-up pin value
+* used in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_PIN0 ((uint32_t) CY_SYSPM_WAKEUP_PIN0_BIT << \
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)
+
+/**
+* The internal define of the second wake-up pin value used
+* in the Cy_SysPm_SetHibernateWakeupSource() function
+*/
+#define CY_SYSPM_WAKEUP_PIN1 ((uint32_t) CY_SYSPM_WAKEUP_PIN1_BIT << \
+ SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)
+
+/** The internal define for the first LPComparator polarity configuration */
+#define CY_SYSPM_WAKEUP_LPCOMP0_POLARITY_HIGH ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP0_BIT << \
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos)
+
+/** The internal define for the second LPComparator polarity configuration */
+#define CY_SYSPM_WAKEUP_LPCOMP1_POLARITY_HIGH ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP1_BIT << \
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos)
+
+/** The internal define for the first wake-up pin polarity configuration */
+#define CY_SYSPM_WAKEUP_PIN0_POLARITY_HIGH ((uint32_t) CY_SYSPM_WAKEUP_PIN0_BIT << \
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos)
+
+/** The internal define for the second wake-up pin polarity configuration */
+#define CY_SYSPM_WAKEUP_PIN1_POLARITY_HIGH ((uint32_t) CY_SYSPM_WAKEUP_PIN1_BIT << \
+ SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos)
+
+/* Internal macro of all possible wakeup sources from hibernate power mode */
+#define CY_SYSPM_HIB_WAKEUP_SOURSE_MASK (CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_LPCOMP1_HIGH | \
+ CY_SYSPM_HIBERNATE_RTC_ALARM | CY_SYSPM_HIBERNATE_WDT | \
+ CY_SYSPM_HIBERNATE_PIN0_HIGH | CY_SYSPM_HIBERNATE_PIN1_HIGH)
+/** \endcond */
+
+/**
+* \defgroup group_syspm_return_status The Power Mode Status Defines
+* \{
+* The defines of the core(s) and device power mode status.
+*/
+#if(0u != CY_IP_M4CPUSS)
+
+ /** The CM4 is Active */
+ #define CY_SYSPM_STATUS_CM4_ACTIVE (0x01U)
+
+ /** The CM4 is in Sleep */
+ #define CY_SYSPM_STATUS_CM4_SLEEP (0x02U)
+
+ /** The CM4 is in Deep Sleep */
+ #define CY_SYSPM_STATUS_CM4_DEEPSLEEP (0x04U)
+
+ /** The CM4 is Low-Power mode */
+ #define CY_SYSPM_STATUS_CM4_LOWPOWER (0x80U)
+
+ /** The define of retained power mode of the CM4 */
+ #define CY_SYSPM_CM4_PWR_RETAINED (2UL)
+
+#endif /* (0u != CY_IP_M4CPUSS) */
+
+/** The CM0 is Active */
+#define CY_SYSPM_STATUS_CM0_ACTIVE ((uint32_t) ((uint32_t)0x01U << 8U))
+
+/** The CM0 is in Sleep */
+#define CY_SYSPM_STATUS_CM0_SLEEP ((uint32_t) ((uint32_t)0x02U << 8U))
+
+/** The CM0 is in Deep Sleep */
+#define CY_SYSPM_STATUS_CM0_DEEPSLEEP ((uint32_t) ((uint32_t)0x04U << 8U))
+
+/** The CM0 is in Low-Power mode */
+#define CY_SYSPM_STATUS_CM0_LOWPOWER ((uint32_t) ((uint32_t)0x80U << 8U))
+
+#if(0u != CY_IP_M4CPUSS)
+
+ /** The device is in the Low-Power mode define */
+ #define CY_SYSPM_STATUS_SYSTEM_LOWPOWER ((uint32_t) (CY_SYSPM_STATUS_CM0_LOWPOWER | \
+ (CY_SYSPM_STATUS_CM4_LOWPOWER)))
+#else
+ /** The device is in the Low-Power mode define */
+ #define CY_SYSPM_STATUS_SYSTEM_LOWPOWER CY_SYSPM_STATUS_CM0_LOWPOWER
+
+#endif /* (0u != CY_IP_M4CPUSS) */
+/** \} group_syspm_return_status */
+
+/** \} group_syspm_macros */
+
+/*******************************************************************************
+* Configuration Structures
+*******************************************************************************/
+
+/**
+* \addtogroup group_syspm_data_enumerates
+* \{
+*/
+
+/** The SysPm status definitions */
+typedef enum
+{
+ CY_SYSPM_SUCCESS = 0x00U, /**< Successful */
+ CY_SYSPM_BAD_PARAM = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */
+ CY_SYSPM_TIMEOUT = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< A time-out occurs */
+ CY_SYSPM_INVALID_STATE = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< The operation is not setup or is in an
+ improper state */
+ CY_SYSPM_FAIL = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0xFFU /**< An unknown failure */
+} cy_en_syspm_status_t;
+
+/**
+* This enumeration is used to initialize a wait action - an interrupt or
+* an event. Refer to the CMSIS for the WFE and WFI instruction explanations.
+*/
+typedef enum
+{
+ CY_SYSPM_WAIT_FOR_INTERRUPT, /**< Wait for an interrupt */
+ CY_SYSPM_WAIT_FOR_EVENT /**< Wait for an event */
+} cy_en_syspm_waitfor_t;
+
+/** This enumeration is used to configure sources for wakeup from the Hibernate
+* power mode
+*/
+typedef enum
+{
+ /** Configure a low level for the first LPComp */
+ CY_SYSPM_HIBERNATE_LPCOMP0_LOW =
+ ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP0_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos),
+
+ /** Configure a high level for the first LPComp */
+ CY_SYSPM_HIBERNATE_LPCOMP0_HIGH =
+ ((uint32_t) ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP0_BIT << SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos) |
+ ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP0_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)),
+
+ /** Configure a low level for the second LPComp */
+ CY_SYSPM_HIBERNATE_LPCOMP1_LOW = ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP1_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos),
+
+ /** Configure a high level for the second LPComp */
+ CY_SYSPM_HIBERNATE_LPCOMP1_HIGH =
+ ((uint32_t) ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP1_BIT << SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos) |
+ ((uint32_t) CY_SYSPM_WAKEUP_LPCOMP1_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)),
+
+ /** Configure the RTC alarm */
+ CY_SYSPM_HIBERNATE_RTC_ALARM = SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk,
+
+ /** Configure the WDT interrupt */
+ CY_SYSPM_HIBERNATE_WDT = SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk,
+
+ /** Configure a low level for the first wakeup-pin */
+ CY_SYSPM_HIBERNATE_PIN0_LOW = ((uint32_t) CY_SYSPM_WAKEUP_PIN0_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos),
+
+ /** Configure a high level for the first wakeup-pin */
+ CY_SYSPM_HIBERNATE_PIN0_HIGH =
+ ((uint32_t) ((uint32_t) CY_SYSPM_WAKEUP_PIN0_BIT << SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos) |
+ ((uint32_t) CY_SYSPM_WAKEUP_PIN0_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)),
+
+ /** Configure a low level for the second wakeup-pin */
+ CY_SYSPM_HIBERNATE_PIN1_LOW = ((uint32_t) CY_SYSPM_WAKEUP_PIN1_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos),
+
+ /** Configure a high level for the second wakeup-pin */
+ CY_SYSPM_HIBERNATE_PIN1_HIGH =
+ ((uint32_t) ((uint32_t) CY_SYSPM_WAKEUP_PIN1_BIT << SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos) |
+ ((uint32_t) CY_SYSPM_WAKEUP_PIN1_BIT << SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos)),
+} cy_en_syspm_hibernate_wakeup_source_t;
+
+/** The enumeration is used to select output voltage for the LDO */
+typedef enum
+{
+ CY_SYSPM_LDO_VOLTAGE_0_9V, /**< 0.9 V nominal LDO voltage */
+ CY_SYSPM_LDO_VOLTAGE_1_1V /**< 1.1 V nominal LDO voltage */
+} cy_en_syspm_ldo_voltage_t;
+
+#if(0u != SRSS_BUCKCTL_PRESENT)
+
+ /**
+ * The enumeration is used to select the output voltage for the Buck
+ * output 1, which can supply a core(s).
+ */
+ typedef enum
+ {
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V = 0x02U, /**< 0.9 V nominal Buck voltage */
+ CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V = 0x05U /**< 1.1 V nominal Buck voltage */
+ } cy_en_syspm_buck_voltage1_t;
+
+ /**
+ * The enumerations are used to select the Buck regulator outputs
+ */
+ typedef enum
+ {
+ CY_SYSPM_BUCK_VBUCK_1, /**< Buck output 1 Voltage (Vbuck1) */
+ CY_SYSPM_BUCK_VRF /**< Buck out 2 Voltage (Vbuckrf) */
+ } cy_en_syspm_buck_out_t;
+
+ #if(0u != SRSS_SIMOBUCK_PRESENT)
+
+ /**
+ * The enumeration is used to select the output voltage for the Buck
+ * output 2, which can source the BLE HW block.
+ */
+ typedef enum
+ {
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V = 0U, /**< 1.15 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V = 1U, /**< 1.20 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V = 2U, /**< 1.25 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V = 3U, /**< 1.3 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V = 4U, /**< 1.35 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V = 5U, /**< 1.4 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V = 6U, /**< 1.45 V nominal voltage */
+ CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V = 7U /**< 1.5 V nominal voltage */
+ } cy_en_syspm_buck_voltage2_t;
+
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+
+/**
+* This enumeration is used to set a polarity for the PMIC input. The PMIC is
+* automatically enabled when configured polarity of PMIC input and the polarity
+* driven to pmic_wakeup_in pin matches.
+*/
+typedef enum
+{
+ CY_SYSPM_PMIC_POLARITY_LOW = 0U, /**< Set active low state for the PMIC input */
+ CY_SYSPM_PMIC_POLARITY_HIGH = 1U /**< Set active high state for the PMIC input */
+} cy_en_syspm_pmic_wakeup_polarity_t;
+
+/**
+* This enumeration sets a switch to select Vbackup or Vddd to supply Vddbackup
+*/
+typedef enum
+{
+ CY_SYSPM_VDDBACKUP_DEFAULT = 0U, /**< Automatically selects Vddd or Vbackup to supply
+ Vddbackup */
+ CY_SYSPM_VDDBACKUP_VBACKUP = 2U /**< Set Vbackup to supply Vddbackup */
+} cy_en_syspm_vddbackup_control_t;
+
+/**
+* This enumeration configures supercapacitor charging.
+*/
+typedef enum
+{
+ CY_SYSPM_SC_CHARGE_ENABLE = 0x3CU, /**< Enables supercapacitor charging */
+ CY_SYSPM_SC_CHARGE_DISABLE = 0x00U /**< Disables supercapacitor charging */
+} cy_en_syspm_sc_charge_key_t;
+
+/**
+* This enumeration is used for selecting the low power mode on which the
+* appropriate registered callback handler will be executed. For example,
+* the registered callback of the type CY_SYSPM_SLEEP will be executed while
+* switching into the Sleep power mode.
+*/
+typedef enum
+{
+ CY_SYSPM_SLEEP, /**< The Sleep enum callback type */
+ CY_SYSPM_DEEPSLEEP, /**< The Deep Sleep enum callback type */
+ CY_SYSPM_HIBERNATE, /**< The Hibernate enum callback type */
+ CY_SYSPM_ENTER_LOWPOWER_MODE, /**< The enter into the LPActive mode enum callback type */
+ CY_SYSPM_EXIT_LOWPOWER_MODE, /**< The exit out of the LPActive mode enum callback type */
+} cy_en_syspm_callback_type_t;
+
+/** The callback mode enumeration. This enum defines the callback mode */
+typedef enum
+{
+ CY_SYSPM_CHECK_READY = 0x01U, /**< Callbacks with this mode are executed before entering into the
+ low-power mode. Callback function check if the device is ready
+ to enter the low-power mode */
+ CY_SYSPM_CHECK_FAIL = 0x02U, /**< Callbacks with this mode are executed after the previous callbacks
+ execution with CY_SYSPM_CHECK_READY return CY_SYSPM_FAIL. The callback
+ with the CY_SYSPM_CHECK_FAIL mode should roll back the actions done in
+ the callbacks executed previously with CY_SYSPM_CHECK_READY */
+ CY_SYSPM_BEFORE_TRANSITION = 0x04U, /**< The actions to be done before entering into the low-power mode */
+ CY_SYSPM_AFTER_TRANSITION = 0x08U, /**< The actions to be done after exiting the low-power mode */
+} cy_en_syspm_callback_mode_t;
+
+/** \} group_syspm_data_enumerates */
+
+/**
+* \addtogroup group_syspm_macros
+* \{
+*/
+/**
+* \defgroup group_syspm_skip_callback_modes The Defines to skip the callbacks modes
+* \{
+* The defines of the SysPm callbacks modes that can be skipped during execution.
+* For more information about callbacks modes refer
+* to \ref cy_en_syspm_callback_mode_t.
+*/
+#define CY_SYSPM_SKIP_CHECK_READY (0x01U) /**< The define to skip the check ready mode in the syspm callback */
+#define CY_SYSPM_SKIP_CHECK_FAIL (0x02U) /**< The define to skip the check fail mode in the syspm callback */
+#define CY_SYSPM_SKIP_BEFORE_TRANSITION (0x04U) /**< The define to skip the before transition mode in the syspm callback */
+#define CY_SYSPM_SKIP_AFTER_TRANSITION (0x08U) /**< The define to skip the after transition mode in the syspm callback */
+/** \} group_syspm_skip_callback_modes */
+/** \} group_syspm_macros */
+
+/**
+* \addtogroup group_syspm_data_structures
+* \{
+*/
+
+/** The structure with the syspm callback parameters */
+typedef struct
+{
+ cy_en_syspm_callback_mode_t mode; /**< The callback mode. You can skip assigning as this element is for
+ internal usage, see \ref cy_en_syspm_callback_mode_t. This element
+ should not be defined as it is updated every time before the
+ callback function is executed */
+ void *base; /**< The base address of a HW instance, matches name of the driver in
+ the API for the base address. Can be not defined if not required */
+ void *context; /**< The context for the handler function. This item can be
+ skipped if not required. Can be not defined if not required */
+
+} cy_stc_syspm_callback_params_t;
+
+/** The type for syspm callbacks */
+typedef cy_en_syspm_status_t (*Cy_SysPmCallback) (cy_stc_syspm_callback_params_t *callbackParams);
+
+/** The structure with the syspm callback configuration elements */
+typedef struct cy_stc_syspm_callback
+{
+ Cy_SysPmCallback callback; /**< The callback handler function */
+ cy_en_syspm_callback_type_t type; /**< The callback type, see \ref cy_en_syspm_callback_type_t */
+ uint32_t skipMode; /**< The mask of modes to be skipped during callback
+ execution, see \ref group_syspm_skip_callback_modes. The
+ corresponding callback mode won't execute if the
+ appropriate define is set. These values can be ORed.
+ If all modes are required to be executed this element
+ should be equal to zero. */
+
+ cy_stc_syspm_callback_params_t *callbackParams; /**< The address of a cy_stc_syspm_callback_params_t,
+ the callback is executed with these parameters */
+
+ struct cy_stc_syspm_callback *prevItm; /**< The previous list item. This element should not be
+ defined, or defined as NULL. It is for internal
+ usage to link this structure to the next registered structure.
+ It will be updated during callback registering. Do not
+ modify this element in run-time */
+
+ struct cy_stc_syspm_callback *nextItm; /**< The next list item. This element should not be
+ defined, or defined as NULL. It is for internal usage to
+ link this structure to the previous registered structure.
+ It will be updated during callback registering. Do not
+ modify this element in run-time */
+} cy_stc_syspm_callback_t;
+
+#ifdef CY_IP_MXUDB
+
+ /** \cond INTERNAL */
+
+ /** This internal structure stores non-retained registers in the Deep Sleep
+ * power mode.
+ */
+ typedef struct
+ {
+ /* The UDB interface control register */
+ uint32_t CY_UDB_UDBIF_BANK_CTL_REG;
+
+ /* The UDB bank control registers */
+ uint32_t CY_UDB_BCTL_MDCLK_EN_REG;
+ uint32_t CY_UDB_BCTL_MBCLK_EN_REG;
+ uint32_t CY_UDB_BCTL_BOTSEL_L_REG;
+ uint32_t CY_UDB_BCTL_BOTSEL_U_REG;
+ uint32_t CY_UDB_BCTL_QCLK_EN0_REG;
+ uint32_t CY_UDB_BCTL_QCLK_EN1_REG;
+ uint32_t CY_UDB_BCTL_QCLK_EN2_REG;
+ } cy_stc_syspm_backup_regs_t;
+ /** \endcond */
+
+#endif /* CY_IP_MXUDB */
+
+/** \} group_syspm_data_structures */
+
+
+/**
+* \addtogroup group_syspm_functions
+* \{
+*/
+
+/**
+* \addtogroup group_syspm_functions_power_status
+* \{
+*/
+#if(0u != CY_IP_M4CPUSS)
+
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void);
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void);
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void);
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsLowPower(void);
+
+#endif /* (0u != CY_IP_M4CPUSS) */
+
+__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void);
+__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void);
+__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void);
+__STATIC_INLINE bool Cy_SysPm_Cm0IsLowPower(void);
+__STATIC_INLINE bool Cy_SysPm_IsLowPower(void);
+uint32_t Cy_SysPm_ReadStatus(void);
+/** \} group_syspm_functions_power_status */
+
+/**
+* \addtogroup group_syspm_functions_power
+* \{
+*/
+cy_en_syspm_status_t Cy_SysPm_Sleep(cy_en_syspm_waitfor_t waitFor);
+cy_en_syspm_status_t Cy_SysPm_DeepSleep(cy_en_syspm_waitfor_t waitFor);
+cy_en_syspm_status_t Cy_SysPm_Hibernate(void);
+void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource);
+void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource);
+cy_en_syspm_status_t Cy_SysPm_EnterLowPowerMode(void);
+cy_en_syspm_status_t Cy_SysPm_ExitLowPowerMode(void);
+void Cy_SysPm_SleepOnExit(bool enable);
+/** \} group_syspm_functions_power */
+
+/**
+* \addtogroup group_syspm_functions_iofreeze
+* \{
+*/
+
+/** \cond INTERNAL */
+void Cy_SysPm_IoFreeze(void);
+/** \endcond */
+
+void Cy_SysPm_IoUnfreeze(void);
+__STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void);
+/** \} group_syspm_functions_iofreeze */
+
+/**
+* \addtogroup group_syspm_functions_ldo
+* \{
+*/
+void Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage);
+__STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void);
+__STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void);
+/** \} group_syspm_functions_ldo */
+
+/**
+* \addtogroup group_syspm_functions_pmic
+* \{
+*/
+__STATIC_INLINE void Cy_SysPm_PmicEnable(void);
+__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity);
+__STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void);
+__STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void);
+__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void);
+__STATIC_INLINE void Cy_SysPm_PmicLock(void);
+__STATIC_INLINE void Cy_SysPm_PmicUnlock(void);
+__STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void);
+__STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void);
+__STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void);
+/** \} group_syspm_functions_pmic */
+
+/**
+* \addtogroup group_syspm_functions_backup
+* \{
+*/
+__STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl);
+__STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void);
+__STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void);
+__STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void);
+__STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key);
+/** \} group_syspm_functions_backup */
+
+/**
+* \addtogroup group_syspm_functions_buck
+* \{
+*/
+#if(0u != SRSS_BUCKCTL_PRESENT)
+ __STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void);
+ __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void);
+
+ void Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage);
+ void Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage);
+ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output);
+
+ #if(0u != SRSS_SIMOBUCK_PRESENT)
+ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void);
+ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void);
+ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl);
+ __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void);
+ void Cy_SysPm_BuckEnableVoltage2(void);
+ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle);
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+/** \} group_syspm_functions_buck */
+
+/**
+* \addtogroup group_syspm_functions_callback
+* \{
+*/
+bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t *handler);
+bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler);
+cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, cy_en_syspm_callback_mode_t mode);
+/** \} group_syspm_functions_callback */
+
+/**
+* \addtogroup group_syspm_functions_power_status
+* \{
+*/
+
+#if(0u != CY_IP_M4CPUSS)
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_Cm4IsActive
+ ****************************************************************************//**
+ *
+ * Checks whether CM4 is in Active mode.
+ *
+ * \return
+ * true - if CM4 is in Active mode; false - if the CM4 is not in Active mode.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm4IsActive
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void)
+ {
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_ACTIVE) != 0U);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_Cm4IsSleep
+ ****************************************************************************//**
+ *
+ * Checks whether the CM4 is in Sleep mode.
+ *
+ * \return
+ * true - if the CM4 is in Sleep mode;
+ * false - if the CM4 is not in Sleep mode.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm4IsSleep
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void)
+ {
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_SLEEP) != 0U);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_Cm4IsDeepSleep
+ ****************************************************************************//**
+ *
+ * Checks whether the CM4 is in the Deep Sleep mode.
+ *
+ * \return
+ * true - if CM4 is in Deep Sleep mode; false - if the CM4 is not in
+ * Deep Sleep mode.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm4IsDeepSleep
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void)
+ {
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_DEEPSLEEP) != 0U);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_Cm4IsLowPower
+ ****************************************************************************//**
+ *
+ * Checks whether the CM4 is in Low-Power mode. Note that Low-Power mode is a
+ * status of the device.
+ *
+ * \return
+ * true - if the CM4 is in Low-Power mode;
+ * false - if the CM4 is not in Low-Power mode.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm4IsLowPower
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_Cm4IsLowPower(void)
+ {
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_LOWPOWER) != 0U);
+ }
+/** \} group_syspm_functions_power_status */
+#endif /* (0u != CY_IP_M4CPUSS) */
+
+/**
+* \addtogroup group_syspm_functions_power_status
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsActive
+****************************************************************************//**
+*
+* Checks whether the CM0+ is in Active mode.
+*
+* \return
+* true - if the CM0+ is in Active mode;
+* false - if the CM0+ is not in Active mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm0IsActive
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsSleep
+****************************************************************************//**
+*
+* Checks whether the CM0+ is in Sleep mode.
+*
+* \return
+* true - if the CM0+ is in Sleep mode;
+* false - if the CM0+ is not in Sleep mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm0IsSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsDeepSleep
+****************************************************************************//**
+*
+* Checks whether the CM0+ is in Deep Sleep mode.
+*
+* \return
+* true - if the CM0+ is in Deep Sleep mode;
+* false - if the CM0+ is not in Deep Sleep mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm0IsDeepSleep
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_Cm0IsLowPower
+****************************************************************************//**
+*
+* Checks whether the CM0+ is in Low-Power mode. Note that Low-Power mode is a
+* status of the device.
+*
+* \return
+* true - if the CM0+ is in Low-Power mode;
+* false - if the CM0+ is not in Low-Power mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_Cm0IsLowPower
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_Cm0IsLowPower(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_LOWPOWER) != 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IsLowPower
+****************************************************************************//**
+*
+* Checks whether the device is in Low-Power mode.
+*
+* \return
+* true - the system is in Low-Power mode;
+* false - the system is is not in Low-Power mode.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_IsLowPower
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_IsLowPower(void)
+{
+ return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LOWPOWER) != 0U);
+}
+
+/** \} group_syspm_functions_power_status */
+
+
+/**
+* \addtogroup group_syspm_functions_buck
+* \{
+*/
+#if(0u != SRSS_BUCKCTL_PRESENT)
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckIsEnabled
+ ****************************************************************************//**
+ *
+ * Get the current status of the Buck regulator.
+ *
+ * \return
+ * The current state of the Buck regulator. True if the Buck regulator
+ * is enabled; false if it is disabled.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void)
+ {
+ return((0u !=_FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_EN, SRSS->PWR_BUCK_CTL)) ? true : false);
+ }
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckGetVoltage1
+ ****************************************************************************//**
+ *
+ * Gets the current nominal output 1 voltage (Vccbuck1) of
+ * the Buck regulator.
+ *
+ * \note The actual device output 1 voltage (Vccbuck1) can be different from
+ * the nominal voltage because the actual voltage value depends on the
+ * conditions including the load current.
+ *
+ * \return
+ * The nominal output voltage 1 (Vccbuck1) of the Buck regulator.
+ * See \ref cy_en_syspm_buck_voltage1_t.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+ *
+ *******************************************************************************/
+ __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void)
+ {
+ uint32_t retVal;
+ retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, SRSS->PWR_BUCK_CTL);
+
+ return((cy_en_syspm_buck_voltage1_t) retVal);
+ }
+
+
+ #if(0u != SRSS_SIMOBUCK_PRESENT)
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckGetVoltage2
+ ****************************************************************************//**
+ *
+ * Gets the current output 2 nominal voltage (Vbuckrf) of the SIMO
+ * Buck regulator.
+ *
+ * \note The actual device output 2 voltage (Vbuckrf) can be different from the
+ * nominal voltage because the actual voltage value depends on the conditions
+ * including the load current.
+ *
+ * \return
+ * The nominal output voltage of the Buck SIMO regulator output 2
+ * voltage (Vbuckrf).
+ * See \ref cy_en_syspm_buck_voltage2_t.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckGetVoltage2
+ *
+ *******************************************************************************/
+ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void)
+ {
+ uint32_t retVal;
+ retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, SRSS->PWR_BUCK_CTL2);
+
+ return((cy_en_syspm_buck_voltage2_t) retVal);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckDisableVoltage2
+ ****************************************************************************//**
+ *
+ * Disables the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The
+ * output 2 voltage (Vbuckrf) of the Buck regulator is used to supply
+ * the BLE HW block.
+ *
+ * \note The function does not have effect if the Buck regulator is
+ * switched off.
+ *
+ * \note Ensures that the new voltage supply for the BLE HW block is settled
+ * and is stable before calling the Cy_SysPm_BuckDisableVoltage2() function.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckDisableVoltage2
+ *
+ *******************************************************************************/
+ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void)
+ {
+ /* Disable the Vbuck2 output */
+ SRSS->PWR_BUCK_CTL2 &= ((uint32_t) ~ (_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U)));
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckSetVoltage2HwControl
+ ****************************************************************************//**
+ *
+ * Sets the hardware control for the SIMO Buck output 2 (Vbuckrf).
+ *
+ * The hardware control for the Vbuckrf output. When this bit is set, the
+ * value in BUCK_OUT2_EN is ignored and the hardware signal is used instead. If the
+ * product has supporting hardware, it can directly control the enable signal
+ * for Vbuckrf.
+ *
+ * \param hwControl
+ * Enables/disables hardware control for the SIMO Buck output 2.
+ *
+ * Function does not have an effect if SIMO Buck regulator is disabled.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckSetVoltage2HwControl
+ *
+ *******************************************************************************/
+ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl)
+ {
+ if(Cy_SysPm_BuckIsEnabled())
+ {
+ if(hwControl)
+ {
+ SRSS->PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U);
+ }
+ else
+ {
+ SRSS->PWR_BUCK_CTL2 &= ((uint32_t)~(_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U)));
+ }
+ }
+ }
+
+
+ /*******************************************************************************
+ * Function Name: Cy_SysPm_BuckIsVoltage2HwControlled
+ ****************************************************************************//**
+ *
+ * Gets the hardware control for Vbuckrf.
+ *
+ * The hardware control for the Vbuckrf output. When this bit is set, the
+ * value in BUCK_OUT2_EN is ignored and the hardware signal is used instead.
+ * If the product has supporting hardware, it can directly control the enable
+ * signal for Vbuckrf.
+ *
+ * \return
+ * True if the HW control is set; false if the FW control is set for the
+ * Buck output 2.
+ *
+ * The function is applicable for devices with the SIMO Buck regulator.
+ * Refer to device datasheet about information if device contains
+ * SIMO Buck.
+ *
+ * \funcusage
+ * \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BuckIsVoltage2HwControlled
+ *
+ *******************************************************************************/
+ __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void)
+ {
+ return((0U != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS->PWR_BUCK_CTL2)) ? true : false);
+ }
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+/** \} group_syspm_functions_buck */
+
+/**
+* \addtogroup group_syspm_functions_ldo
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoGetVoltage
+****************************************************************************//**
+*
+* Gets the current output voltage value of the LDO.
+*
+* \note The actual device Vccd voltage can be different from the
+* nominal voltage because the actual voltage value depends on the conditions
+* including the load current.
+*
+* \return
+* The nominal output voltage of the LDO.
+* See \ref cy_en_syspm_ldo_voltage_t.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void)
+{
+ uint32_t curVoltage;
+
+ curVoltage = _FLD2VAL(SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, SRSS->PWR_TRIM_PWRSYS_CTL);
+
+ return((curVoltage == (CY_SYSPM_SFLASH->LDO_0P9V_TRIM)) ? CY_SYSPM_LDO_VOLTAGE_0_9V : CY_SYSPM_LDO_VOLTAGE_1_1V);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_LdoIsEnabled
+****************************************************************************//**
+*
+* Reads the current status of the LDO.
+*
+* \return
+* True means the LDO is enabled. False means it is disabled.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_VoltageRegulator
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void)
+{
+ return((0U != _FLD2VAL(SRSS_PWR_CTL_LINREG_DIS, SRSS->PWR_CTL)) ? false : true);
+}
+
+/** \} group_syspm_functions_ldo */
+
+
+/**
+* \addtogroup group_syspm_functions_iofreeze
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_IoIsFrozen
+****************************************************************************//**
+*
+* Checks whether IOs are frozen.
+*
+* \return Returns True if IOs are frozen. <br> False if IOs are unfrozen.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_IoUnfreeze
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void)
+{
+ return(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS->PWR_HIBERNATE));
+}
+
+/** \} group_syspm_functions_iofreeze */
+
+
+/**
+* \addtogroup group_syspm_functions_pmic
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicEnable
+****************************************************************************//**
+*
+* Enable the external PMIC that supplies Vddd (if present).
+*
+* For information about the PMIC input and output pins and their assignment in
+* the specific families devices, refer to the appropriate device TRM.
+*
+* The function is not effective when the PMIC is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicEnable(void)
+{
+ if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP->PMIC_CTL))
+ {
+ BACKUP->PMIC_CTL =
+ _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
+ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U) |
+ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicDisable
+****************************************************************************//**
+*
+* Disables the PMIC. This function does not affect the output pin. Configures
+* the PMIC input pin polarity. The PMIC input pin has programmable polarity to
+* enable the PMIC using different input polarities. The PMIC output pin is
+* automatically enabled when input polarity and configured polarity matches.
+* The function is not effective when the active level of PMIC input pin
+* is equal to configured PMIC polarity.
+*
+* The function is not effective when the PMIC is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* \param polarity
+* Configures the PMIC wakeup input pin to be active low or active
+* high. See \ref cy_en_syspm_pmic_wakeup_polarity_t.
+*
+* The PMIC will be enabled automatically by any of RTC alarm or PMIC wakeup
+* event regardless of the PMIC lock state.
+*
+* \warning
+* The PMIC is enabled automatically when you call Cy_SysPm_PmicLock().
+* To keep the PMIC disabled, the PMIC must remain unlocked.
+*
+* For information about the PMIC input and output pins and their assignment in
+* the specific families devices, refer to the appropriate device TRM.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicDisable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_POLARITY_VALID(polarity));
+
+ if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP->PMIC_CTL))
+ {
+ BACKUP->PMIC_CTL =
+ (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) |
+ _CLR_SET_FLD32U(BACKUP->PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, (uint32_t) polarity)) &
+ ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicAlwaysEnable
+****************************************************************************//**
+*
+* Enables the signal through the PMIC output pin. This is a Write once API,
+* ensure that the PMIC cannot be disabled or polarity changed until a next
+* device reset.
+*
+* For information about the PMIC input and output pins and their assignment in
+* the specific families devices, refer to the appropriate device TRM.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicAlwaysEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void)
+{
+ BACKUP->PMIC_CTL |= _VAL2FLD(BACKUP_PMIC_CTL_PMIC_ALWAYSEN, 1U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicEnableOutput
+****************************************************************************//**
+*
+* Enable the PMIC output.
+*
+* The function is not effective when the PMIC is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* For information about the PMIC output pin and it assignment in
+* the specific families devices, refer to the appropriate device TRM.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicEnableOutput
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void)
+{
+ if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP->PMIC_CTL))
+ {
+ BACKUP->PMIC_CTL |=
+ _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicDisableOutput
+****************************************************************************//**
+*
+* Disables the PMIC output.
+*
+* When PMIC output pin is disabled and is unlocked the pmic output pin can be
+* used for the another purpose.
+*
+* The function is not effective when the PMIC is locked. Call
+* Cy_SysPm_PmicUnlock() before enabling the PMIC.
+*
+* For information about the PMIC output pin and it assignment in
+* the specific families devices, refer to the appropriate device TRM.
+*
+* \warning
+* The PMIC output is enabled automatically when you call Cy_SysPm_PmicLock().
+* To keep PMIC output disabled, the PMIC must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicDisableOutput
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void)
+{
+ if(CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP->PMIC_CTL))
+ {
+ BACKUP->PMIC_CTL =
+ (BACKUP->PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) &
+ ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U));
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicLock
+****************************************************************************//**
+*
+* Locks the PMIC control register so that no changes can be made. The changes
+* are related to the PMIC enabling/disabling and PMIC output signal
+* enabling/disabling.
+*
+* \warning
+* The PMIC and/or the PMIC output are enabled automatically when
+* you call Cy_SysPm_PmicLock(). To keep the PMIC or PMIC output disabled,
+* the PMIC must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicLock(void)
+{
+ BACKUP->PMIC_CTL = _CLR_SET_FLD32U(BACKUP->PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0U);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicUnlock
+****************************************************************************//**
+*
+* Unlocks the PMIC control register so that changes can be made. The changes are
+* related to the PMIC enabling/disabling and PMIC output signal
+* enabling/disabling.
+*
+* \warning
+* The PMIC and/or the PMIC output are enabled automatically when
+* you call Cy_SysPm_PmicLock(). To keep the PMIC or PMIC output disabled,
+* the PMIC must remain unlocked.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicEnable
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_PmicUnlock(void)
+{
+ BACKUP->PMIC_CTL = _CLR_SET_FLD32U(BACKUP->PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsEnabled
+****************************************************************************//**
+*
+* The function returns the status of the PMIC.
+*
+* \return
+* True - The PMIC is enabled. <br>
+* False - The PMIC is disabled. <br>
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void)
+{
+ return(0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN, BACKUP->PMIC_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsOutputEnabled
+****************************************************************************//**
+*
+* The function returns the status of the PMIC output.
+*
+* \return
+* True - The PMIC output is enabled. <br>
+* False - The PMIC output is disabled. <br>
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicDisable
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void)
+{
+ return(0U != _FLD2VAL(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, BACKUP->PMIC_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_PmicIsLocked
+****************************************************************************//**
+*
+* Returns the PMIC lock status
+*
+* \return
+* True - The PMIC is locked. <br>
+* False - The PMIC is unlocked. <br>
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_PmicLock
+*
+*******************************************************************************/
+__STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void)
+{
+ return((_FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP->PMIC_CTL) == CY_SYSPM_PMIC_UNLOCK_KEY) ? false : true);
+}
+
+/** \} group_syspm_functions_pmic */
+
+
+/**
+* \addtogroup group_syspm_functions_backup
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupSetSupply
+****************************************************************************//**
+*
+* Sets the Backup Supply (Vddback) operation mode.
+*
+* \param
+* vddBackControl
+* Selects Backup Supply (Vddback) operation mode.
+* See \ref cy_en_syspm_vddbackup_control_t.
+*
+* Refer to device TRM for more details about Backup supply modes.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BackupSetSupply
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vddBackControl)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl));
+
+ BACKUP->CTL = _CLR_SET_FLD32U((BACKUP->CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupGetSupply
+****************************************************************************//**
+*
+* Returns the current Backup Supply (Vddback) operation mode.
+*
+* \return
+* The current Backup Supply (Vddback) operation mode,
+* see \ref cy_en_syspm_status_t.
+*
+* Refer to device TRM for more details about Backup supply modes.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BackupGetSupply
+*
+*******************************************************************************/
+__STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void)
+{
+ uint32_t retVal;
+ retVal = _FLD2VAL(BACKUP_CTL_VDDBAK_CTL, BACKUP->CTL);
+
+ return((cy_en_syspm_vddbackup_control_t) retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupEnableVoltageMeasurement
+****************************************************************************//**
+*
+* This function enables the Vbackup supply measurement by the ADC. The function
+* connects the Vbackup supply to the AMUXBUSA. Note that measured signal is
+* scaled by 40% to allow being measured by the ADC.
+*
+* Refer to device TRM for more details about Vbackup supply measurement.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BackupEnableVoltageMeasurement
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupEnableVoltageMeasurement(void)
+{
+ BACKUP->CTL |= BACKUP_CTL_VBACKUP_MEAS_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupDisableVoltageMeasurement
+****************************************************************************//**
+*
+* The function disables the Vbackup supply measurement by the ADC. The function
+* disconnects the Vbackup supply from the AMUXBUSA.
+*
+* Refer to device TRM for more details about Vbackup supply measurement.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BackupDisableVoltageMeasurement
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void)
+{
+ BACKUP->CTL &= ((uint32_t) ~BACKUP_CTL_VBACKUP_MEAS_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysPm_BackupSuperCapCharge
+****************************************************************************//**
+*
+* Configures the supercapacitor charger circuit.
+*
+* \param key
+* Passes the key to enable or disable the supercapacitor charger circuit.
+* See \ref cy_en_syspm_sc_charge_key_t.
+*
+* \warning
+* This function is used only for charging the supercapacitor.
+* Do not use this function to charge a battery. Refer to device TRM for more
+* details.
+*
+* \funcusage
+* \snippet syspm/syspm_2_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysPm_BackupSuperCapCharge
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key)
+{
+ CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key));
+
+ if(key == CY_SYSPM_SC_CHARGE_ENABLE)
+ {
+ BACKUP->CTL = _CLR_SET_FLD32U((BACKUP->CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE);
+ }
+ else
+ {
+ BACKUP->CTL &= ((uint32_t) ~BACKUP_CTL_EN_CHARGE_KEY_Msk);
+ }
+}
+
+/** \} group_syspm_functions_backup */
+/** \} group_syspm_functions*/
+
+/** \cond INTERNAL */
+
+/*******************************************************************************
+* Backward compatibility macro. The following code is DEPRECATED and must
+* not be used in new projects
+*******************************************************************************/
+#if(0u != SRSS_BUCKCTL_PRESENT)
+
+ /* BWC defines for Buck related functions */
+ #if(0u != SRSS_SIMOBUCK_PRESENT)
+ typedef cy_en_syspm_buck_voltage1_t cy_en_syspm_simo_buck_voltage1_t;
+ typedef cy_en_syspm_buck_voltage2_t cy_en_syspm_simo_buck_voltage2_t;
+
+ #define Cy_SysPm_SimoBuckGetVoltage2 Cy_SysPm_BuckGetVoltage2
+ #define Cy_SysPm_DisableVoltage2 Cy_SysPm_BuckDisableVoltage2
+ #define Cy_SysPm_EnableVoltage2 Cy_SysPm_BuckEnableVoltage2
+ #define Cy_SysPm_SimoBuckSetHwControl Cy_SysPm_BuckSetVoltage2HwControl
+ #define Cy_SysPm_SimoBuckGetHwControl Cy_SysPm_BuckIsVoltage2HwControlled
+ #define Cy_SysPm_SimoBuckSetVoltage2 Cy_SysPm_BuckSetVoltage2
+
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_15V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_2V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_25V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_3V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_35V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_4V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_45V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V
+ #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_5V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V
+ #endif /* (0u != SRSS_SIMOBUCK_PRESENT) */
+
+ #define CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V
+ #define CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V
+
+ #define Cy_SysPm_SwitchToSimoBuck() (Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V))
+ #define Cy_SysPm_SimoBuckGetVoltage1 Cy_SysPm_BuckGetVoltage1
+ #define Cy_SysPm_SimoBuckIsEnabled Cy_SysPm_BuckIsEnabled
+ #define Cy_SysPm_SimoBuckSetVoltage1 Cy_SysPm_BuckSetVoltage1
+ #define Cy_SysPm_SimoBuckOutputIsEnabled Cy_SysPm_BuckIsOutputEnabled
+#endif /* (0u != SRSS_BUCKCTL_PRESENT) */
+
+#define CY_SYSPM_LPCOMP0_LOW CY_SYSPM_HIBERNATE_LPCOMP0_LOW
+#define CY_SYSPM_LPCOMP0_HIGH CY_SYSPM_HIBERNATE_LPCOMP0_HIGH
+#define CY_SYSPM_LPCOMP1_LOW CY_SYSPM_HIBERNATE_LPCOMP1_LOW
+#define CY_SYSPM_LPCOMP1_HIGH CY_SYSPM_HIBERNATE_LPCOMP1_HIGH
+#define CY_SYSPM_HIBALARM CY_SYSPM_HIBERNATE_RTC_ALARM
+#define CY_SYSPM_HIBWDT CY_SYSPM_HIBERNATE_WDT
+#define CY_SYSPM_HIBPIN0_LOW CY_SYSPM_HIBERNATE_PIN0_LOW
+#define CY_SYSPM_HIBPIN0_HIGH CY_SYSPM_HIBERNATE_PIN0_HIGH
+#define CY_SYSPM_HIBPIN1_LOW CY_SYSPM_HIBERNATE_PIN1_LOW
+#define CY_SYSPM_HIBPIN1_HIGH CY_SYSPM_HIBERNATE_PIN1_HIGH
+
+#define CY_SYSPM_ENTER_LP_MODE CY_SYSPM_ENTER_LOWPOWER_MODE
+#define CY_SYSPM_EXIT_LP_MODE CY_SYSPM_EXIT_LOWPOWER_MODE
+
+/* BWC defines for functions related to low power transition*/
+#define Cy_SysPm_EnterLpMode Cy_SysPm_EnterLowPowerMode
+#define Cy_SysPm_ExitLpMode Cy_SysPm_ExitLowPowerMode
+
+typedef cy_en_syspm_hibernate_wakeup_source_t cy_en_syspm_hib_wakeup_source_t;
+
+/* BWC defines related to hibernation functions */
+#define Cy_SysPm_SetHibWakeupSource Cy_SysPm_SetHibernateWakeupSource
+#define Cy_SysPm_ClearHibWakeupSource Cy_SysPm_ClearHibernateWakeupSource
+#define Cy_SysPm_GetIoFreezeStatus Cy_SysPm_IoIsFrozen
+
+/* BWC defines for Backup related functions */
+#define Cy_SysPm_SetBackupSupply Cy_SysPm_BackupSetSupply
+#define Cy_SysPm_GetBackupSupply Cy_SysPm_BackupGetSupply
+#define Cy_SysPm_EnableBackupVMeasure Cy_SysPm_BackupEnableVoltageMeasurement
+#define Cy_SysPm_DisableBackupVMeasure Cy_SysPm_BackupDisableVoltageMeasurement
+
+/* BWC defines for PMIC related functions */
+#define Cy_SysPm_EnablePmic Cy_SysPm_PmicEnable
+#define Cy_SysPm_DisablePmic Cy_SysPm_PmicDisable
+#define Cy_SysPm_AlwaysEnablePmic Cy_SysPm_PmicAlwaysEnable
+#define Cy_SysPm_EnablePmicOutput Cy_SysPm_PmicEnableOutput
+#define Cy_SysPm_DisablePmicOutput Cy_SysPm_PmicDisableOutput
+#define Cy_SysPm_LockPmic Cy_SysPm_PmicLock
+#define Cy_SysPm_UnlockPmic Cy_SysPm_PmicUnlock
+#define Cy_SysPm_IsPmicEnabled Cy_SysPm_PmicIsEnabled
+#define Cy_SysPm_IsPmicOutputEnabled Cy_SysPm_PmicIsOutputEnabled
+#define Cy_SysPm_IsPmicLocked Cy_SysPm_PmicIsLocked
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CY_SYSPM_H */
+
+/** \} group_syspm */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/systick/cy_systick.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,244 @@
+/***************************************************************************//**
+* \file cy_systick.c
+* \version 1.0.1
+*
+* Provides the API definitions of the SisTick driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_systick.h"
+#include <stddef.h> /* for NULL */
+
+
+static Cy_SysTick_Callback Cy_SysTick_Callbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+static void Cy_SysTick_ServiceCallbacks(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Init
+****************************************************************************//**
+*
+* Initializes the SysTick driver:
+* - Initializes the callback addresses with pointers to NULL
+* - Associates the SysTick system vector with the callback functions
+* - Sets the SysTick clock by calling \ref Cy_SysTick_SetClockSource()
+* - Sets the SysTick reload interval by calling \ref Cy_SysTick_SetReload()
+* - Clears the SysTick counter value by calling \ref Cy_SysTick_Clear()
+* - Enables the SysTick by calling \ref Cy_SysTick_Enable(). Note the \ref
+* Cy_SysTick_Enable() function also enables the SysTick interrupt by calling
+* \ref Cy_SysTick_EnableInterrupt().
+*
+* \param clockSource The SysTick clock source \ref cy_en_systick_clock_source_t
+* \param interval The SysTick reload value.
+*
+* \sideeffect Clears the SysTick count flag if it was set.
+*
+*******************************************************************************/
+void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval)
+{
+ uint32_t i;
+
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ Cy_SysTick_Callbacks[i] = NULL;
+ }
+
+ __ramVectors[CY_SYSTICK_IRQ_NUM] = &Cy_SysTick_ServiceCallbacks;
+ Cy_SysTick_SetClockSource(clockSource);
+
+ Cy_SysTick_SetReload(interval);
+ Cy_SysTick_Clear();
+ Cy_SysTick_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Enable
+****************************************************************************//**
+*
+* Enables the SysTick timer and its interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+void Cy_SysTick_Enable(void)
+{
+ Cy_SysTick_EnableInterrupt();
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Disable
+****************************************************************************//**
+*
+* Disables the SysTick timer and its interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+void Cy_SysTick_Disable(void)
+{
+ Cy_SysTick_DisableInterrupt();
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetClockSource
+****************************************************************************//**
+*
+* Sets the clock source for the SysTick counter.
+*
+* Clears the SysTick count flag if it was set. If the clock source is not ready
+* this function call will have no effect. After changing the clock source to the
+* low frequency clock, the counter and reload register values will remain
+* unchanged so the time to the interrupt will be significantly longer and vice
+* versa.
+*
+* Changing the SysTick clock source and/or its frequency will change
+* the interrupt interval and Cy_SysTick_SetReload() should be
+* called to compensate this change.
+*
+* \param clockSource \ref cy_en_systick_clock_source_t Clock source.
+*
+*******************************************************************************/
+void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource)
+{
+ if (clockSource == CY_SYSTICK_CLOCK_SOURCE_CLK_CPU)
+ {
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ }
+ else
+ {
+ CPUSS->SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource);
+ SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetClockSource
+****************************************************************************//**
+*
+* Gets the clock source for the SysTick counter.
+*
+* \returns \ref cy_en_systick_clock_source_t Clock source
+*
+*******************************************************************************/
+cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void)
+{
+ cy_en_systick_clock_source_t returnValue;
+
+ if ((SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) != 0u)
+ {
+ returnValue = CY_SYSTICK_CLOCK_SOURCE_CLK_CPU;
+ }
+ else
+ {
+ returnValue = (cy_en_systick_clock_source_t) ((uint32_t) _FLD2VAL(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, CPUSS->SYSTICK_CTL));
+ }
+
+ return(returnValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetCallback
+****************************************************************************//**
+*
+* Sets the callback function to the specified callback number.
+*
+* \param number The number of the callback function addresses to be set.
+* The valid range is from 0 to \ref CY_SYS_SYST_NUM_OF_CALLBACKS - 1.
+*
+* \param function The pointer to the function that will be associated with the
+* SysTick ISR for the specified number.
+*
+* \return Returns the address of the previous callback function.
+* The NULL is returned if the specified address in not set or incorrect
+* parameter is specified.
+
+* \sideeffect
+* The registered callback functions will be executed in the interrupt.
+*
+*******************************************************************************/
+Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function)
+{
+ Cy_SysTick_Callback retVal;
+
+ if (number < CY_SYS_SYST_NUM_OF_CALLBACKS)
+ {
+ retVal = Cy_SysTick_Callbacks[number];
+ Cy_SysTick_Callbacks[number] = function;
+ }
+ else
+ {
+ retVal = NULL;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetCallback
+****************************************************************************//**
+*
+* Gets the specified callback function address.
+*
+* \param number The number of the callback function address to get. The valid
+* range is from 0 to \ref CY_SYS_SYST_NUM_OF_CALLBACKS - 1.
+*
+* \return Returns the address of the specified callback function.
+* The NULL is returned if the specified address in not initialized or incorrect
+* parameter is specified.
+*
+*******************************************************************************/
+Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number)
+{
+ Cy_SysTick_Callback retVal;
+
+ if (number < CY_SYS_SYST_NUM_OF_CALLBACKS)
+ {
+ retVal = Cy_SysTick_Callbacks[number];
+ }
+ else
+ {
+ retVal = NULL;
+ }
+
+ return (retVal);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_ServiceCallbacks
+****************************************************************************//**
+*
+* The system Tick timer interrupt routine.
+*
+*******************************************************************************/
+static void Cy_SysTick_ServiceCallbacks(void)
+{
+ uint32_t i;
+
+ /* Verify that tick timer flag was set */
+ if (0u != Cy_SysTick_GetCountFlag())
+ {
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ if (Cy_SysTick_Callbacks[i] != NULL)
+ {
+ (void)(Cy_SysTick_Callbacks[i])();
+ }
+ }
+ }
+}
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/systick/cy_systick.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,284 @@
+/***************************************************************************//**
+* \file cy_systick.h
+* \version 1.0.1
+*
+* Provides the API declarations of the SysTick driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CY_SYSTICK_H_
+#define _CY_SYSTICK_H_
+
+/**
+* \defgroup group_arm_system_timer ARM System Timer (SysTick)
+* \{
+* Provides vendor-specific SysTick API.
+*
+* The SysTick timer is part of the CPU. The timer is a down counter with a 24-bit reload/tick value that is clocked by
+* the FastClk/SlowClk. The timer has the capability to generate an interrupt when the set number of ticks expires and
+* the counter is reloaded. This interrupt is available as part of the Nested Vectored Interrupt Controller (NVIC) for
+* service by the CPU and can be used for general-purpose timing control in user code.
+*
+* The timer is independent of the CPU (except for the clock), which is useful in applications requiring
+* precise timing that do not have a dedicated timer/counter available for the job.
+*
+* \section group_systick_configuration Configuration Considerations
+*
+* The \ref Cy_SysTick_Init() performs all required driver's initialization and enables the timer. The function accepts
+* two parameters: clock source \ref cy_en_systick_clock_source_t and the timer interval. You must ensure
+* the selected clock source for SysTick is enabled.
+* The callbacks can be registered/unregistered any time after \ref Cy_SysTick_Init() by calling
+* \ref Cy_SysTick_SetCallback().
+*
+* Changing the SysTick clock source and/or its frequency will change the interrupt interval and therefore
+* \ref Cy_SysTick_SetReload() should be called to compensate for this change.
+*
+* \section group_systick_more_information More Information
+*
+* Refer to the SysTick section of the ARM reference guide for complete details on the registers and their use.
+* See also the "CPU Subsystem (CPUSS)" chapter of the device technical reference manual (TRM).
+*
+* \section group_systick_MISRA MISRA-C Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>8.12</td>
+* <td>Required</td>
+* <td>When an array is declared with external linkage, its size shall be
+* stated explicitly or defined implicitly by initialization.</td>
+* <td>The warning is related to the __ramVectors symbol defined in the assembly startup code.
+* It's size is device-specific and unknown to the SysTick driver.</td>
+* </tr>
+* </table>
+*
+* \section group_systick_changelog Changelog
+*
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Fixed a warning issued when the compilation of C++ source code was
+* enabled.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_systick_macros Macros
+* \defgroup group_systick_functions Functions
+* \defgroup group_systick_data_structures Data Structures
+*/
+
+#include <stdint.h>
+#include "syslib/cy_syslib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \cond */
+extern cy_israddress __ramVectors[];
+typedef void (*Cy_SysTick_Callback)(void);
+/** \endcond */
+
+/**
+* \addtogroup group_systick_data_structures
+* \{
+*/
+/** SysTick clocks sources */
+typedef enum
+{
+ CY_SYSTICK_CLOCK_SOURCE_CLK_LF = 0u, /**< The low frequency clock clk_lf is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_IMO = 1u, /**< The internal main oscillator (IMO) clock clk_imo is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_ECO = 2u, /**< The external crystal oscillator (ECO) clock clk_eco is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_TIMER = 3u, /**< The SRSS clk_timer is selected. */
+ CY_SYSTICK_CLOCK_SOURCE_CLK_CPU = 4u, /**< The CPU clock is selected. */
+} cy_en_systick_clock_source_t;
+
+/** \} group_systick_data_structures */
+
+
+/**
+* \addtogroup group_systick_functions
+* \{
+*/
+
+void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval);
+void Cy_SysTick_Enable(void);
+void Cy_SysTick_Disable(void);
+Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function);
+Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number);
+void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource);
+cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void);
+__STATIC_INLINE void Cy_SysTick_EnableInterrupt(void);
+__STATIC_INLINE void Cy_SysTick_DisableInterrupt(void);
+__STATIC_INLINE void Cy_SysTick_SetReload(uint32_t value);
+__STATIC_INLINE uint32_t Cy_SysTick_GetReload(void);
+__STATIC_INLINE uint32_t Cy_SysTick_GetValue(void);
+__STATIC_INLINE uint32_t Cy_SysTick_GetCountFlag(void);
+__STATIC_INLINE void Cy_SysTick_Clear(void);
+
+/** \} group_systick_functions */
+
+
+/**
+* \addtogroup group_systick_macros
+* \{
+*/
+
+/** Driver major version */
+#define SYSTICK_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define SYSTICK_DRV_VERSION_MINOR 0
+
+/** Number of the callbacks assigned to the SysTick interrupt */
+#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u)
+
+/** \} group_systick_macros */
+
+
+/** \cond */
+/** Interrupt number in the vector table */
+#define CY_SYSTICK_IRQ_NUM (15u)
+/** \endcond */
+
+/**
+* \addtogroup group_systick_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_EnableInterrupt
+****************************************************************************//**
+*
+* Enables the SysTick interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_EnableInterrupt(void)
+{
+ SysTick->CTRL = SysTick->CTRL | SysTick_CTRL_TICKINT_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_DisableInterrupt
+****************************************************************************//**
+*
+* Disables the SysTick interrupt.
+*
+* \sideeffect Clears the SysTick count flag if it was set
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_DisableInterrupt(void)
+{
+ SysTick->CTRL = SysTick->CTRL & ~SysTick_CTRL_TICKINT_Msk;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_SetReload
+****************************************************************************//**
+*
+* Sets the value the counter is set to on a startup and after it reaches zero.
+* This function does not change or reset the current sysTick counter value, so
+* it should be cleared using the Cy_SysTick_Clear() API.
+*
+* \param value: The valid range is [0x0-0x00FFFFFF]. The counter reset value.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_SetReload(uint32_t value)
+{
+ SysTick->LOAD = (value & SysTick_LOAD_RELOAD_Msk);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetReload
+****************************************************************************//**
+*
+* Gets the value the counter is set to on a startup and after it reaches zero.
+*
+* \return The counter reset value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetReload(void)
+{
+ return (SysTick->LOAD);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetValue
+****************************************************************************//**
+*
+* Gets the current SysTick counter value.
+*
+* \return The current SysTick counter value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetValue(void)
+{
+ return (SysTick->VAL);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_Clear
+****************************************************************************//**
+*
+* Clears the SysTick counter for a well-defined startup.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_SysTick_Clear(void)
+{
+ SysTick->VAL = 0u;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysTick_GetCountFlag
+****************************************************************************//**
+*
+* Gets the values of the count flag. The count flag is set once the SysTick
+* counter reaches zero. The flag is cleared on read.
+*
+* \return Returns a non-zero value if a flag is set; otherwise a zero is
+* returned.
+*
+* \sideeffect Clears the SysTick count flag if it was set.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_SysTick_GetCountFlag(void)
+{
+ return (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk);
+}
+
+
+/** \} group_systick_functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CY_SYSTICK_H_ */
+
+/** \} group_systick */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,654 @@
+/***************************************************************************//**
+* \file cy_tcpwm.h
+* \version 1.0.1
+*
+* The header file of the TCPWM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_tcpwm Timer Counter PWM (TCPWM)
+* \{
+* \defgroup group_tcpwm_common Common
+* \defgroup group_tcpwm_counter Timer/Counter (TCPWM)
+* \defgroup group_tcpwm_pwm PWM (TCPWM)
+* \defgroup group_tcpwm_quaddec Quadrature Decoder (TCPWM)
+* \} */
+
+/**
+* \addtogroup group_tcpwm
+* \{
+*
+* The TCPWM driver is a multifunction driver that implements Timer Counter,
+* PWM, and Quadrature Decoder functionality using the TCPWM block.
+*
+* Each TCPWM block is a collection of counters that can all be triggered
+* simultaneously. For each function call, the base register address of
+* the TCPWM being used must be passed first, followed by the index of
+* the counter you want to touch next.
+* For some functions, you can manage multiple counters simultaneously. You
+* provide a bit field representing each counter, rather than the single counter
+* index).
+*
+* The TCPWM supports three operating modes:
+* * Timer/Counter
+* * PWM
+* * Quadrature Decoder
+*
+* \n
+* \b Timer/Counter
+*
+* Use this mode whenever a specific timing interval or measurement is
+* needed. Examples include:
+* * Creating a periodic interrupt for running other system tasks
+* * Measuring frequency of an input signal
+* * Measuring pulse width of an input signal
+* * Measuring time between two external events
+* * Counting events
+* * Triggering other system resources after x number events
+* * Capturing time stamps when events occur
+*
+* The Timer/Counter has the following features:
+* * 16- or 32-bit Timer/Counter
+* * Programmable Period Register
+* * Programmable Compare Register. Compare value can be swapped with a
+* buffered compare value on comparison event
+* * Capture with buffer register
+* * Count Up, Count Down, or Count Up and Down Counting modes
+* * Continuous or One Shot Run modes
+* * Interrupt and Output on Overflow, Underflow, Capture, or Compare
+* * Start, Reload, Stop, Capture, and Count Inputs
+*
+* \n
+* \b PWM
+*
+* Use this mode when an output square wave is needed with a specific
+* period and duty cycle, such as:
+* * Creating arbitrary square wave outputs
+* * Driving an LED (changing the brightness)
+* * Driving Motors (dead time assertion available)
+*
+* The PWM has the following features:
+* * 16- or 32-bit Counter
+* * Two Programmable Period registers that can be swapped
+* * Two Output Compare registers that can be swapped on overflow and/or
+* underflow
+* * Left Aligned, Right Aligned, Center Aligned, and Asymmetric Aligned modes
+* * Continuous or One Shot run modes
+* * Pseudo Random mode
+* * Two PWM outputs with Dead Time insertion, and programmable polarity
+* * Interrupt and Output on Overflow, Underflow, or Compare
+* * Start, Reload, Stop, Swap (Capture), and Count Inputs
+* * Multiple Components can be synchronized together for applications
+* such as three phase motor control
+*
+* \n
+* \b Quadrature \b Decoder
+*
+* A quadrature decoder is used to decode the output of a quadrature encoder.
+* A quadrature encoder senses the position, velocity, and direction of
+* an object (for example a rotating axle, or a spinning mouse ball).
+* A quadrature decoder can also be used for precision measurement of speed,
+* acceleration, and position of a motor's rotor, or with a rotary switch to
+* determine user input. \n
+*
+* The Quadrature Decoder has the following features:
+* * 16- or 32-bit Counter
+* * Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and
+* phiB (Start) inputs
+* * Index Input to determine absolute position
+* * A positive edge on phiA increments the counter when phiB is 0 and decrements
+* the counter when phiB is 1
+*
+* \section group_tcpwm_configuration Configuration Considerations
+*
+* For each mode, the TCPWM driver has a configuration structure, an Init
+* function, and an Enable function.
+*
+* Provide the configuration parameters in the appropriate structure (see
+* Counter \ref group_tcpwm_data_structures_counter, PWM
+* \ref group_tcpwm_data_structures_pwm, or QuadDec
+* \ref group_tcpwm_data_structures_quaddec).
+* Then call the appropriate Init function:
+* \ref Cy_TCPWM_Counter_Init, \ref Cy_TCPWM_PWM_Init, or
+* \ref Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a
+* parameter. To enable the counter, call the appropriate Enable function:
+* \ref Cy_TCPWM_Counter_Enable, \ref Cy_TCPWM_PWM_Enable, or
+* \ref Cy_TCPWM_QuadDec_Enable).
+*
+* Many functions work with an individual counter. You can also manage multiple
+* counters simultaneously for certain functions. These are listed in the
+* \ref group_tcpwm_functions_common
+* section of the TCPWM. You can enable, disable, or trigger (in various ways)
+* multiple counters simultaneously. For these functions you provide a bit field
+* representing each counter in the TCPWM you want to control. You can
+* represent the bit field as an ORed mask of each counter, like
+* ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter
+* number from 0 to 31.
+*
+* \note
+* * If none of the input terminals (start, reload(index)) are used, the
+* software event \ref Cy_TCPWM_TriggerStart or
+* \ref Cy_TCPWM_TriggerReloadOrIndex must be called to start the counting.
+* * If count input terminal is not used, the \ref CY_TCPWM_INPUT_LEVEL macro
+* should be set for the countInputMode parameter and the \ref CY_TCPWM_INPUT_1
+* macro should be set for the countInputMode parameter in the configuration
+* structure of the appropriate mode(Counter
+* \ref group_tcpwm_data_structures_counter, PWM
+* \ref group_tcpwm_data_structures_pwm, or QuadDec
+* \ref group_tcpwm_data_structures_quaddec).
+*
+* \section group_tcpwm_more_information More Information
+*
+* For more information on the TCPWM peripheral, refer to the technical
+* reference manual (TRM).
+*
+* \section group_tcpwm_MISRA MISRA-C Compliance
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>14.2</td>
+* <td>R</td>
+* <td>All non-null statements shall either: a) have at least one side-effect
+* however executed, or b) cause control flow to change.</td>
+* <td>The unused function parameters are cast to void. This statement
+* has no side-effect and is used to suppress a compiler warning.</td>
+* </tr>
+* </table>
+*
+* \section group_tcpwm_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>Added a deviation to the MISRA Compliance section.
+* Added function-level code snippets.</td>
+* <td>Documentation update and clarification</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*/
+
+/** \} group_tcpwm */
+
+/**
+* \addtogroup group_tcpwm_common
+* Common API for the Timer Counter PWM Block.
+* \{
+* \defgroup group_tcpwm_macros_common Macros
+* \defgroup group_tcpwm_functions_common Functions
+* \defgroup group_tcpwm_data_structures_common Data Structures
+* \defgroup group_tcpwm_enums Enumerated Types
+*/
+
+
+#if !defined(CY_TCPWM_H)
+#define CY_TCPWM_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "syslib/cy_syslib.h"
+#include "cy_device_headers.h"
+
+#ifndef CY_IP_MXTCPWM
+ #error "The TCPWM driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_macros_common
+* \{
+*/
+
+/** Driver major version */
+#define CY_TCPWM_DRV_VERSION_MAJOR 1
+
+/** Driver minor version */
+#define CY_TCPWM_DRV_VERSION_MINOR 0
+
+
+/******************************************************************************
+* API Constants
+******************************************************************************/
+
+/** TCPWM driver identifier */
+#define CY_TCPWM_ID (CY_PDL_DRV_ID(0x2DU))
+
+/** \defgroup group_tcpwm_input_selection TCPWM Input Selection
+* \{
+* Selects which input to use
+*/
+#define CY_TCPWM_INPUT_0 (0U) /**< Input is tied to logic 0 */
+#define CY_TCPWM_INPUT_1 (1U) /**< Input is tied to logic 1 */
+#define CY_TCPWM_INPUT_TRIG_0 (2U) /**< Input is connected to the trigger input 0 */
+#define CY_TCPWM_INPUT_TRIG_1 (3U) /**< Input is connected to the trigger input 1 */
+#define CY_TCPWM_INPUT_TRIG_2 (4U) /**< Input is connected to the trigger input 2 */
+#define CY_TCPWM_INPUT_TRIG_3 (5U) /**< Input is connected to the trigger input 3 */
+#define CY_TCPWM_INPUT_TRIG_4 (6U) /**< Input is connected to the trigger input 4 */
+#define CY_TCPWM_INPUT_TRIG_5 (7U) /**< Input is connected to the trigger input 5 */
+#define CY_TCPWM_INPUT_TRIG_6 (8U) /**< Input is connected to the trigger input 6 */
+#define CY_TCPWM_INPUT_TRIG_7 (9U) /**< Input is connected to the trigger input 7 */
+#define CY_TCPWM_INPUT_TRIG_8 (10U) /**< Input is connected to the trigger input 8 */
+#define CY_TCPWM_INPUT_TRIG_9 (11U) /**< Input is connected to the trigger input 9 */
+#define CY_TCPWM_INPUT_TRIG_10 (12U) /**< Input is connected to the trigger input 10 */
+#define CY_TCPWM_INPUT_TRIG_11 (13U) /**< Input is connected to the trigger input 11 */
+#define CY_TCPWM_INPUT_TRIG_12 (14U) /**< Input is connected to the trigger input 12 */
+#define CY_TCPWM_INPUT_TRIG_13 (15U) /**< Input is connected to the trigger input 13 */
+
+/** Input is defined by Creator, and Init() function does not need to configure input */
+#define CY_TCPWM_INPUT_CREATOR (0xFFFFFFFFU)
+/** \} group_tcpwm_input_selection */
+
+/**
+* \defgroup group_tcpwm_input_modes Input Modes
+* \{
+* Configures how TCPWM inputs behave
+*/
+/** A rising edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_RISINGEDGE (0U)
+/** A falling edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_FALLINGEDGE (1U)
+/** A rising edge or falling edge triggers the event (Capture, Start, Reload, etc..) */
+#define CY_TCPWM_INPUT_EITHEREDGE (2U)
+/** The event is triggered on each edge of the TCPWM clock if the input is high */
+#define CY_TCPWM_INPUT_LEVEL (3U)
+/** \} group_tcpwm_input_modes */
+
+/**
+* \defgroup group_tcpwm_interrupt_sources Interrupt Sources
+* \{
+* Interrupt Sources
+*/
+#define CY_TCPWM_INT_ON_TC (1U) /**< Interrupt on Terminal count(TC) */
+#define CY_TCPWM_INT_ON_CC (2U) /**< Interrupt on Compare/Capture(CC) */
+#define CY_TCPWM_INT_NONE (0U) /**< No Interrupt */
+#define CY_TCPWM_INT_ON_CC_OR_TC (3U) /**< Interrupt on TC or CC */
+/** \} group_tcpwm_interrupt_sources */
+
+
+/***************************************
+* Registers Constants
+***************************************/
+
+/**
+* \defgroup group_tcpwm_reg_const Default registers constants
+* \{
+* Default constants for CNT Registers
+*/
+#define CY_TCPWM_CNT_CTRL_DEFAULT (0x0U) /**< Default value for CTRL register */
+#define CY_TCPWM_CNT_COUNTER_DEFAULT (0x0U) /**< Default value for COUNTER register */
+#define CY_TCPWM_CNT_CC_DEFAULT (0xFFFFFFFFU) /**< Default value for CC register */
+#define CY_TCPWM_CNT_CC_BUFF_DEFAULT (0xFFFFFFFFU) /**< Default value for CC_BUFF register */
+#define CY_TCPWM_CNT_PERIOD_DEFAULT (0xFFFFFFFFU) /**< Default value for PERIOD register */
+#define CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT (0xFFFFFFFFU) /**< Default value for PERIOD_BUFF register */
+#define CY_TCPWM_CNT_TR_CTRL0_DEFAULT (0x10U) /**< Default value for TR_CTRL0 register */
+#define CY_TCPWM_CNT_TR_CTRL1_DEFAULT (0x3FFU) /**< Default value for TR_CTRL1 register */
+#define CY_TCPWM_CNT_TR_CTRL2_DEFAULT (0x3FU) /**< Default value for TR_CTRL2 register */
+#define CY_TCPWM_CNT_INTR_DEFAULT (0x3U) /**< Default value for INTR register */
+#define CY_TCPWM_CNT_INTR_SET_DEFAULT (0x0U) /**< Default value for INTR_SET register */
+#define CY_TCPWM_CNT_INTR_MASK_DEFAULT (0x0U) /**< Default value for INTR_MASK register */
+/** \} group_tcpwm_reg_const */
+
+/** Position of Up counting counter status */
+#define CY_TCPWM_CNT_STATUS_UP_POS (0x1U)
+/** Initial value for the counter in the Up counting mode */
+#define CY_TCPWM_CNT_UP_INIT_VAL (0x0U)
+/** Initial value for the counter in the Up/Down counting modes */
+#define CY_TCPWM_CNT_UP_DOWN_INIT_VAL (0x1U)
+/** \} group_tcpwm_macros_common */
+
+
+/*******************************************************************************
+ * Enumerations
+ ******************************************************************************/
+
+ /**
+* \addtogroup group_tcpwm_enums
+* \{
+*/
+
+/** TCPWM status definitions */
+typedef enum
+{
+ CY_TCPWM_SUCCESS = 0x00U, /**< Successful */
+ CY_TCPWM_BAD_PARAM = CY_TCPWM_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */
+} cy_en_tcpwm_status_t;
+/** \} group_tcpwm_enums */
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_common
+* \{
+*/
+
+__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source);
+__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source);
+__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Enable_Multiple
+****************************************************************************//**
+*
+* Enables the counter(s) in the TCPWM block. Multiple blocks can be started
+* simultaneously.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Enable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters)
+{
+ base->CTRL_SET = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Disable_Multiple
+****************************************************************************//**
+*
+* Disables the counter(s) in the TCPWM block. Multiple TCPWM can be disabled
+* simultaneously.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Disable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters)
+{
+ base->CTRL_CLR = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerStart
+****************************************************************************//**
+*
+* Triggers a software start on the selected TCPWMs.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Enable_Multiple
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters)
+{
+ base->CMD_START = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerReloadOrIndex
+****************************************************************************//**
+*
+* Triggers a software reload event (or index in QuadDec mode).
+*
+* \param base
+* The pointer to a TCPWM instance
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_TriggerReloadOrIndex
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters)
+{
+ base->CMD_RELOAD = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerStopOrKill
+****************************************************************************//**
+*
+* Triggers a stop in the Timer Counter mode, or a kill in the PWM mode.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_TriggerStopOrKill
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters)
+{
+ base->CMD_STOP = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_TriggerCaptureOrSwap
+****************************************************************************//**
+*
+* Triggers a Capture in the Timer Counter mode, and a Swap in the PWM mode.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param counters
+* A bit field representing each counter in the TCPWM block.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters)
+{
+ base->CMD_CAPTURE = counters;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptStatus
+****************************************************************************//**
+*
+* Returns which event triggered the interrupt.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+*. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_GetInterruptStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].INTR);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_ClearInterrupt
+****************************************************************************//**
+*
+* Clears Active Interrupt Source
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param source
+* source to clear. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source)
+{
+ base->CNT[cntNum].INTR = source;
+ (void)base->CNT[cntNum].INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_SetInterrupt
+****************************************************************************//**
+*
+* Triggers an interrupt via a software write.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param source
+* The source to set an interrupt. See \ref group_tcpwm_interrupt_sources.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_SetInterrupt
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source)
+{
+ base->CNT[cntNum].INTR_SET = source;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_SetInterruptMask
+****************************************************************************//**
+*
+* Sets an interrupt mask. A 1 means that when the event occurs, it will cause an
+* interrupt; a 0 means no interrupt will be triggered.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param mask
+*. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask)
+{
+ base->CNT[cntNum].INTR_MASK = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptMask
+****************************************************************************//**
+*
+* Returns the interrupt mask.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Interrupt Mask. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_SetInterruptMask
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].INTR_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_GetInterruptStatusMasked
+****************************************************************************//**
+*
+* Returns which masked interrupt triggered the interrupt.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Interrupt Mask. See \ref group_tcpwm_interrupt_sources
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_GetInterruptStatusMasked
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].INTR_MASKED);
+}
+
+/** \} group_tcpwm_functions_common */
+
+/** \} group_tcpwm_common */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TCPWM_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_counter.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,146 @@
+/***************************************************************************//**
+* \file cy_tcpwm_counter.c
+* \version 1.0.1
+*
+* \brief
+* The source file of the tcpwm driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_tcpwm_counter.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_Init
+****************************************************************************//**
+*
+* Initializes the counter in the TCPWM block for the Counter operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to configuration structure. See \ref cy_stc_tcpwm_counter_config_t.
+*
+* \return error / status code. See \ref cy_en_tcpwm_status_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Config
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Init
+*
+*******************************************************************************/
+cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum,
+ cy_stc_tcpwm_counter_config_t const *config)
+{
+ cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM;
+
+ if ((NULL != base) && (NULL != config))
+ {
+ base->CNT[cntNum].CTRL = (_VAL2FLD(TCPWM_CNT_CTRL_GENERIC, config->clockPrescaler) |
+ _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) |
+ _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->countDirection) |
+ _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->compareOrCapture) |
+ (config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0UL));
+
+ if (CY_TCPWM_COUNTER_COUNT_UP == config->countDirection)
+ {
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_INIT_VAL;
+ }
+ else if (CY_TCPWM_COUNTER_COUNT_DOWN == config->countDirection)
+ {
+ base->CNT[cntNum].COUNTER = config->period;
+ }
+ else
+ {
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL;
+ }
+
+ if (CY_TCPWM_COUNTER_MODE_COMPARE == config->compareOrCapture)
+ {
+ base->CNT[cntNum].CC = config->compare0;
+ base->CNT[cntNum].CC_BUFF = config->compare1;
+ }
+
+ base->CNT[cntNum].PERIOD = config->period;
+
+ if (CY_TCPWM_INPUT_CREATOR != config->countInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->captureInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->reloadInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->startInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput));
+ }
+
+ base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->captureInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->stopInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, config->countInputMode));
+
+ base->CNT[cntNum].INTR_MASK = config->interruptSources;
+
+ status = CY_TCPWM_SUCCESS;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_DeInit
+****************************************************************************//**
+*
+* De-initializes the counter in the TCPWM block, returns register values to
+* default.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to configuration structure. See \ref cy_stc_tcpwm_counter_config_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_DeInit
+*
+*******************************************************************************/
+void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config)
+{
+ base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT;
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT;
+ base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT;
+ base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT;
+ base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT;
+ base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT;
+ base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT;
+ base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT;
+ base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT;
+ base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT;
+
+ if (CY_TCPWM_INPUT_CREATOR != config->countInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT;
+ }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_counter.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,525 @@
+/***************************************************************************//**
+* \file cy_tcpwm_counter.h
+* \version 1.0.1
+*
+* \brief
+* The header file of the TCPWM Timer Counter driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_TCPWM_COUNTER_H)
+#define CY_TCPWM_COUNTER_H
+
+#include "cy_tcpwm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_counter
+* \{
+* Driver API for Timer/Counter.
+*/
+
+/**
+* \defgroup group_tcpwm_macros_counter Macros
+* \defgroup group_tcpwm_functions_counter Functions
+* \defgroup group_tcpwm_data_structures_counter Data Structures
+* \} */
+
+/**
+* \addtogroup group_tcpwm_data_structures_counter
+* \{
+*/
+
+/** Counter Timer configuration structure */
+typedef struct cy_stc_tcpwm_counter_config
+{
+ uint32_t period; /**< Sets the period of the counter */
+ /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_counter_clk_prescalers */
+ uint32_t clockPrescaler;
+ uint32_t runMode; /**< Sets the Counter Timer Run mode. See \ref group_tcpwm_counter_run_modes */
+ uint32_t countDirection; /**< Sets the counter direction. See \ref group_tcpwm_counter_direction */
+ /** The counter can either compare or capture a value. See \ref group_tcpwm_counter_compare_capture */
+ uint32_t compareOrCapture;
+ uint32_t compare0; /**< Sets the value for Compare0*/
+ uint32_t compare1; /**< Sets the value for Compare1*/
+ bool enableCompareSwap; /**< If enabled, the compare values are swapped each time the comparison is true */
+ /** Enabled an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */
+ uint32_t interruptSources;
+ uint32_t captureInputMode; /**< Configures how the capture input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the capture uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t captureInput;
+ uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the reload uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t reloadInput;
+ uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the start uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t startInput;
+ uint32_t stopInputMode; /**< Configures how the stop input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the stop uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t stopInput;
+ uint32_t countInputMode; /**< Configures how the count input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the count uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t countInput;
+}cy_stc_tcpwm_counter_config_t;
+/** \} group_tcpwm_data_structures_counter */
+
+/**
+* \addtogroup group_tcpwm_macros_counter
+* \{
+* \defgroup group_tcpwm_counter_run_modes Counter Run Modes
+* \{
+* Run modes for the counter timer.
+*/
+#define CY_TCPWM_COUNTER_ONESHOT (1U) /**< Counter runs once and then stops */
+#define CY_TCPWM_COUNTER_CONTINUOUS (0U) /**< Counter runs forever */
+/** \} group_tcpwm_counter_run_modes */
+
+/** \defgroup group_tcpwm_counter_direction Counter Direction
+* The counter directions.
+* \{
+*/
+#define CY_TCPWM_COUNTER_COUNT_UP (0U) /**< Counter counts up */
+#define CY_TCPWM_COUNTER_COUNT_DOWN (1U) /**< Counter counts down */
+/** Counter counts up and down terminal count only occurs on underflow. */
+#define CY_TCPWM_COUNTER_COUNT_UP_DOWN_1 (2U)
+/** Counter counts up and down terminal count occurs on both overflow and underflow. */
+#define CY_TCPWM_COUNTER_COUNT_UP_DOWN_2 (3U)
+/** \} group_tcpwm_counter_direction */
+
+/** \defgroup group_tcpwm_counter_clk_prescalers Counter CLK Prescalers
+* \{
+* The clock prescaler values.
+*/
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_1 (0U) /**< Divide by 1 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_2 (1U) /**< Divide by 2 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_4 (2U) /**< Divide by 4 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_8 (3U) /**< Divide by 8 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_16 (4U) /**< Divide by 16 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_32 (5U) /**< Divide by 32 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_64 (6U) /**< Divide by 64 */
+#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_128 (7U) /**< Divide by 128 */
+/** \} group_tcpwm_counter_clk_prescalers */
+
+/** \defgroup group_tcpwm_counter_compare_capture Counter Compare Capture
+* \{
+* A compare or capture mode.
+*/
+#define CY_TCPWM_COUNTER_MODE_CAPTURE (2U) /**< Timer/Counter is in Capture Mode */
+#define CY_TCPWM_COUNTER_MODE_COMPARE (0U) /**< Timer/Counter is in Compare Mode */
+/** \} group_tcpwm_counter_compare_capture */
+
+/** \defgroup group_tcpwm_counter_status Counter Status
+* \{
+* The counter status.
+*/
+#define CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING (0x1UL) /**< Timer/Counter is down counting */
+#define CY_TCPWM_COUNTER_STATUS_UP_COUNTING (0x2UL) /**< Timer/Counter is up counting */
+
+/** Timer/Counter is running */
+#define CY_TCPWM_COUNTER_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk)
+/** \} group_tcpwm_counter_status */
+/** \} group_tcpwm_macros_counter */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_counter
+* \{
+*/
+cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum,
+ cy_stc_tcpwm_counter_config_t const *config);
+void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config);
+__STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNum, uint32_t period);
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint32_t cntNum);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_Enable
+****************************************************************************//**
+*
+* Enables the counter in the TCPWM block for the Counter operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Init
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_SET = (1UL << cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_Disable
+****************************************************************************//**
+*
+* Disables the counter in the TCPWM block.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_DeInit
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_CLR = (1UL << cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetStatus
+****************************************************************************//**
+*
+* Returns the status of the Counter Timer.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The status. See \ref group_tcpwm_counter_status
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_GetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ uint32_t status = base->CNT[cntNum].STATUS;
+
+ /* Generates proper up counting status. Is not generated by HW */
+ status &= ~CY_TCPWM_COUNTER_STATUS_UP_COUNTING;
+ status |= ((~status & CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) <<
+ CY_TCPWM_CNT_STATUS_UP_POS);
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetCapture
+****************************************************************************//**
+*
+* Returns the capture value when the capture mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The capture value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetCaptureBuf
+****************************************************************************//**
+*
+* Returns the buffered capture value when the capture mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The buffered capture value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC_BUFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_SetCompare0
+****************************************************************************//**
+*
+* Sets the compare value for Compare0 when the compare mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare0
+* The Compare0 value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0)
+{
+ base->CNT[cntNum].CC = compare0;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetCompare0
+****************************************************************************//**
+*
+* Returns compare value 0.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 0.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_SetCompare1
+****************************************************************************//**
+*
+* Sets the compare value for Compare1 when the compare mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare1
+* The Compare1 value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1)
+{
+ base->CNT[cntNum].CC_BUFF = compare1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetCompare1
+****************************************************************************//**
+*
+* Returns compare value 1.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 1.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC_BUFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_EnableCompareSwap
+****************************************************************************//**
+*
+* Enables the comparison swap when the comparison value is true.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param enable
+* true = swap enabled, false = swap disabled
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_EnableCompareSwap
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable)
+{
+ if (enable)
+ {
+ base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+ else
+ {
+ base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_SetCounter
+****************************************************************************//**
+*
+* Sets the value of the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param count
+* The value to write into the counter.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count)
+{
+ base->CNT[cntNum].COUNTER = count;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetCounter
+****************************************************************************//**
+*
+* Returns the value in the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current counter value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_GetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].COUNTER);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_SetPeriod
+****************************************************************************//**
+*
+* Sets the value of the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param period
+* The value to write into a period.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetPeriod
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNum, uint32_t period)
+{
+ base->CNT[cntNum].PERIOD = period;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_Counter_GetPeriod
+****************************************************************************//**
+*
+* Returns the value in the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current period value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_counter_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_Counter_SetPeriod
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].PERIOD);
+}
+/** \} group_tcpwm_functions_counter */
+
+/** \} group_tcpwm_counter */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TCPWM_COUNTER_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_pwm.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,157 @@
+/***************************************************************************//**
+* \file cy_tcpwm_pwm.c
+* \version 1.0.1
+*
+* \brief
+* The source file of the tcpwm driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_tcpwm_pwm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_Init
+****************************************************************************//**
+*
+* Initializes the counter in the TCPWM block for the PWM operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t.
+*
+* \return error / status code. See \ref cy_en_tcpwm_status_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_Config
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_Init
+*
+*******************************************************************************/
+cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config)
+{
+ cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM;
+
+ if ((NULL != base) && (NULL != config))
+ {
+ base->CNT[cntNum].CTRL = ((config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0UL) |
+ (config->enablePeriodSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk : 0UL) |
+ _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) |
+ _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->pwmAlignment) |
+ _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->pwmMode) |
+ _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE,
+ (config->invertPWMOut | (config->invertPWMOutN << 1U))) |
+ (config->killMode << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS) |
+ _VAL2FLD(TCPWM_CNT_CTRL_GENERIC, ((CY_TCPWM_PWM_MODE_DEADTIME == config->pwmMode) ?
+ config->deadTimeClocks : config->clockPrescaler)));
+
+ if (CY_TCPWM_PWM_MODE_PSEUDORANDOM == config->pwmMode)
+ {
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_PR;
+ }
+ else
+ {
+ if (CY_TCPWM_PWM_LEFT_ALIGN == config->pwmAlignment)
+ {
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_INIT_VAL;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_LEFT;
+ }
+ else if (CY_TCPWM_PWM_RIGHT_ALIGN == config->pwmAlignment)
+ {
+ base->CNT[cntNum].COUNTER = config->period0;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_RIGHT;
+ }
+ else
+ {
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM;
+ }
+ }
+
+ base->CNT[cntNum].CC = config->compare0;
+ base->CNT[cntNum].CC_BUFF = config->compare1;
+ base->CNT[cntNum].PERIOD = config->period0;
+ base->CNT[cntNum].PERIOD_BUFF = config->period1;
+
+ if (CY_TCPWM_INPUT_CREATOR != config->countInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->swapInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->reloadInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->startInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->killInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput));
+ }
+
+ base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->swapInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->killInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, config->countInputMode));
+
+ base->CNT[cntNum].INTR_MASK = config->interruptSources;
+
+ status = CY_TCPWM_SUCCESS;
+ }
+
+ return(status);
+}
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_DeInit
+****************************************************************************//**
+*
+* De-initializes the counter in the TCPWM block, returns register values to
+* default.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_DeInit
+*
+*******************************************************************************/
+void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config)
+{
+ base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT;
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT;
+ base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT;
+ base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT;
+ base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT;
+ base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT;
+ base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT;
+ base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT;
+ base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT;
+ base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT;
+
+ if (CY_TCPWM_INPUT_CREATOR != config->countInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT;
+ }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_pwm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,619 @@
+/***************************************************************************//**
+* \file cy_tcpwm_pwm.h
+* \version 1.0.1
+*
+* \brief
+* The header file of the TCPWM PWM driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_TCPWM_PWM_H)
+#define CY_TCPWM_PWM_H
+
+#include "cy_tcpwm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_pwm
+* Driver API for PWM.
+* \{
+*/
+
+/**
+* \defgroup group_tcpwm_macros_pwm Macros
+* \defgroup group_tcpwm_functions_pwm Functions
+* \defgroup group_tcpwm_data_structures_pwm Data Structures
+* \} */
+
+/**
+* \addtogroup group_tcpwm_data_structures_pwm
+* \{
+*/
+
+/** PWM configuration structure */
+typedef struct cy_stc_tcpwm_pwm_config
+{
+ uint32_t pwmMode; /**< Sets the PWM mode. See \ref group_tcpwm_pwm_modes */
+ /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_pwm_clk_prescalers */
+ uint32_t clockPrescaler;
+ uint32_t pwmAlignment; /**< Sets the PWM alignment. See \ref group_tcpwm_pwm_alignment */
+ uint32_t deadTimeClocks; /**< The number of dead time-clocks if PWM with dead time is chosen */
+ uint32_t runMode; /**< Sets the PWM run mode. See \ref group_tcpwm_pwm_run_modes */
+ uint32_t period0; /**< Sets the period0 of the pwm */
+ uint32_t period1; /**< Sets the period1 of the pwm */
+ bool enablePeriodSwap; /**< Enables swapping of period 0 and period 1 on terminal count */
+ uint32_t compare0; /**< Sets the value for Compare0 */
+ uint32_t compare1; /**< Sets the value for Compare1 */
+ bool enableCompareSwap; /**< If enabled, the compare values are swapped on the terminal count */
+ /** Enables an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */
+ uint32_t interruptSources;
+ uint32_t invertPWMOut; /**< Inverts the PWM output */
+ uint32_t invertPWMOutN; /**< Inverts the PWM_n output */
+ uint32_t killMode; /**< Configures the PWM kill modes. See \ref group_tcpwm_pwm_kill_modes */
+ uint32_t swapInputMode; /**< Configures how the swap input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the swap uses. Inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t swapInput;
+ uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the reload uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t reloadInput;
+ uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the start uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t startInput;
+ uint32_t killInputMode; /**< Configures how the kill input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the kill uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t killInput;
+ uint32_t countInputMode; /**< Configures how the count input behaves. See \ref group_tcpwm_input_modes */
+ /** Selects which input the count uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t countInput;
+}cy_stc_tcpwm_pwm_config_t;
+/** \} group_tcpwm_data_structures_pwm */
+
+/**
+* \addtogroup group_tcpwm_macros_pwm
+* \{
+* \defgroup group_tcpwm_pwm_run_modes PWM run modes
+* \{
+* Run modes for the pwm timer.
+*/
+#define CY_TCPWM_PWM_ONESHOT (1U) /**< Counter runs once and then stops */
+#define CY_TCPWM_PWM_CONTINUOUS (0U) /**< Counter runs forever */
+/** \} group_tcpwm_pwm_run_modes */
+
+/** \defgroup group_tcpwm_pwm_modes PWM modes
+* \{
+* Sets the PWM modes.
+*/
+#define CY_TCPWM_PWM_MODE_PWM (4U) /**< Standard PWM Mode*/
+#define CY_TCPWM_PWM_MODE_DEADTIME (5U) /**< PWM with deadtime mode*/
+#define CY_TCPWM_PWM_MODE_PSEUDORANDOM (6U) /**< Pseudo Random PWM */
+/** \} group_tcpwm_pwm_modes */
+
+/** \defgroup group_tcpwm_pwm_alignment PWM Alignment
+* Sets the alignment of the PWM.
+* \{
+*/
+#define CY_TCPWM_PWM_LEFT_ALIGN (0U) /**< PWM is left aligned, meaning it starts high */
+#define CY_TCPWM_PWM_RIGHT_ALIGN (1U) /**< PWM is right aligned, meaning it starts low */
+/** PWM is centered aligned, terminal count only occurs on underflow */
+#define CY_TCPWM_PWM_CENTER_ALIGN (2U)
+/** PWM is asymmetrically aligned, terminal count occurs on overflow and underflow */
+#define CY_TCPWM_PWM_ASYMMETRIC_ALIGN (3U)
+/** \} group_tcpwm_pwm_alignment */
+
+/** \defgroup group_tcpwm_pwm_kill_modes PWM kill modes
+* Sets the kill mode for the PWM.
+* \{
+*/
+#define CY_TCPWM_PWM_STOP_ON_KILL (2U) /**< PWM stops counting on kill */
+#define CY_TCPWM_PWM_SYNCH_KILL (1U) /**< PWM output is killed after next TC*/
+#define CY_TCPWM_PWM_ASYNC_KILL (0U) /**< PWM output is killed instantly */
+/** \} group_tcpwm_pwm_kill_modes */
+
+/** \defgroup group_tcpwm_pwm_clk_prescalers PWM CLK Prescaler values
+* \{
+* Clock prescaler values.
+*/
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_1 (0U) /**< Divide by 1 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_2 (1U) /**< Divide by 2 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_4 (2U) /**< Divide by 4 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_8 (3U) /**< Divide by 8 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_16 (4U) /**< Divide by 16 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_32 (5U) /**< Divide by 32 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_64 (6U) /**< Divide by 64 */
+#define CY_TCPWM_PWM_PRESCALER_DIVBY_128 (7U) /**< Divide by 128 */
+/** \} group_tcpwm_pwm_clk_prescalers */
+
+/** \defgroup group_tcpwm_pwm_output_invert PWM output invert
+* \{
+* Output invert modes.
+*/
+#define CY_TCPWM_PWM_INVERT_ENABLE (1U) /**< Invert the output mode */
+#define CY_TCPWM_PWM_INVERT_DISABLE (0U) /**< Do not invert the output mode */
+/** \} group_tcpwm_pwm_output_invert */
+
+/** \defgroup group_tcpwm_pwm_status PWM Status
+* \{
+* The counter status.
+*/
+#define CY_TCPWM_PWM_STATUS_DOWN_COUNTING (0x1UL) /**< PWM is down counting */
+#define CY_TCPWM_PWM_STATUS_UP_COUNTING (0x2UL) /**< PWM is up counting */
+#define CY_TCPWM_PWM_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk) /**< PWM counter is running */
+/** \} group_tcpwm_pwm_status */
+
+
+/***************************************
+* Registers Constants
+***************************************/
+
+/** \cond INTERNAL */
+#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS (2U)
+#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_MASK (0x3UL << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS)
+/** \endcond */
+
+/** \defgroup group_tcpwm_pwm_output_configuration PWM output signal configuration
+* \{
+* The configuration of PWM output signal for PWM alignment.
+*/
+#define CY_TCPWM_PWM_TR_CTRL2_SET (0UL) /**< Set define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_CLEAR (1UL) /**< Clear define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_INVERT (2UL) /**< Invert define for PWM output signal configuration */
+#define CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE (3UL) /**< No change define for PWM output signal configuration */
+
+/** The configuration of PWM output signal in Pseudo Random Mode */
+#define CY_TCPWM_PWM_MODE_PR (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE))
+
+/** The configuration of PWM output signal for Left alignment */
+#define CY_TCPWM_PWM_MODE_LEFT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE))
+
+/** The configuration of PWM output signal for Right alignment */
+#define CY_TCPWM_PWM_MODE_RIGHT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR))
+
+/** The configuration of PWM output signal for Center and Asymmetric alignment */
+#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \
+ _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR))
+/** \} group_tcpwm_pwm_output_configuration */
+/** \} group_tcpwm_macros_pwm */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_pwm
+* \{
+*/
+
+cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config);
+void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config);
+__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1);
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_Enable
+****************************************************************************//**
+*
+* Enables the counter in the TCPWM block for the PWM operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_Init
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_SET = (1UL << cntNum);
+}
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_Disable
+****************************************************************************//**
+*
+* Disables the counter in the TCPWM block.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_DeInit
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_CLR = (1UL << cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetStatus
+****************************************************************************//**
+*
+* Returns the status of the PWM.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The status. See \ref group_tcpwm_pwm_status
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_GetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ uint32_t status = base->CNT[cntNum].STATUS;
+
+ /* Generates proper up counting status, does not generated by HW */
+ status &= ~CY_TCPWM_PWM_STATUS_UP_COUNTING;
+ status |= ((~status & CY_TCPWM_PWM_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) <<
+ CY_TCPWM_CNT_STATUS_UP_POS);
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCompare0
+****************************************************************************//**
+*
+* Sets the compare value for Compare0 when the compare mode enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare0
+* The Compare0 value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0)
+{
+ base->CNT[cntNum].CC = compare0;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCompare0
+****************************************************************************//**
+*
+* Returns compare value 0.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 0.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetCompare0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCompare1
+****************************************************************************//**
+*
+* Sets the compare value for Compare1 when the compare mode is enabled.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param compare1
+* The Compare1 value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1)
+{
+ base->CNT[cntNum].CC_BUFF = compare1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCompare1
+****************************************************************************//**
+*
+* Returns compare value 1.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* Compare value 1.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetCompare1
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC_BUFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_EnableCompareSwap
+****************************************************************************//**
+*
+* Enables the comparison swap on OV and/or UN, depending on the PWM alignment.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param enable
+* true = swap enabled; false = swap disabled
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_EnableCompareSwap
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable)
+{
+ if (enable)
+ {
+ base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+ else
+ {
+ base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetCounter
+****************************************************************************//**
+*
+* Sets the value of the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param count
+* The value to write into the counter.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count)
+{
+ base->CNT[cntNum].COUNTER = count;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetCounter
+****************************************************************************//**
+*
+* Returns the value in the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current counter value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_GetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].COUNTER);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetPeriod0
+****************************************************************************//**
+*
+* Sets the value of the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param period0
+* The value to write into a period.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetPeriod0
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0)
+{
+ base->CNT[cntNum].PERIOD = period0;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetPeriod0
+****************************************************************************//**
+*
+* Returns the value in the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current period value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetPeriod0
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].PERIOD);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_SetPeriod1
+****************************************************************************//**
+*
+* Sets the value of the period register.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param period1
+* The value to write into a period1.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetPeriod1
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1)
+{
+ base->CNT[cntNum].PERIOD_BUFF = period1;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_GetPeriod1
+****************************************************************************//**
+*
+* Returns the value in the period register.
+*
+* \param base
+* The pointer to a COUNTER PWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current period value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_SetPeriod1
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].PERIOD_BUFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_PWM_EnablePeriodSwap
+****************************************************************************//**
+*
+* Enables a period swap on OV and/or UN, depending on the PWM alignment
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param enable
+* true = swap enabled; false = swap disabled
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_pwm_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_PWM_EnablePeriodSwap
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable)
+{
+ if (enable)
+ {
+ base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk;
+ }
+ else
+ {
+ base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk;
+ }
+}
+
+/** \} group_tcpwm_functions_pwm */
+
+/** \} group_tcpwm_pwm */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TCPWM_PWM_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_quaddec.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,121 @@
+/***************************************************************************//**
+* \file cy_tcpwm_quaddec.c
+* \version 1.0.1
+*
+* \brief
+* The source file of the tcpwm driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_tcpwm_quaddec.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_Init
+****************************************************************************//**
+*
+* Initializes the counter in the TCPWM block for the QuadDec operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t.
+*
+* \return error / status code. See \ref cy_en_tcpwm_status_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_Config
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_Init
+*
+*******************************************************************************/
+cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum,
+ cy_stc_tcpwm_quaddec_config_t const *config)
+{
+ cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM;
+
+ if ((NULL != base) && (NULL != config))
+ {
+ base->CNT[cntNum].CTRL = ( _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE, config->resolution) |
+ _VAL2FLD(TCPWM_CNT_CTRL_MODE, CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE));
+
+ if (CY_TCPWM_INPUT_CREATOR != config->phiAInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->phiBInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->indexInput) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput));
+ }
+
+ base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, CY_TCPWM_INPUT_LEVEL) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, CY_TCPWM_INPUT_LEVEL) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, CY_TCPWM_INPUT_LEVEL) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->indexInputMode) |
+ _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->stopInputMode));
+
+ base->CNT[cntNum].INTR_MASK = config->interruptSources;
+
+ status = CY_TCPWM_SUCCESS;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_DeInit
+****************************************************************************//**
+*
+* De-initializes the counter in the TCPWM block, returns register values to
+* default.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_DeInit
+*
+*******************************************************************************/
+void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config)
+{
+ base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT;
+ base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT;
+ base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT;
+ base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT;
+ base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT;
+ base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT;
+ base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT;
+ base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT;
+ base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT;
+ base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT;
+ base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT;
+
+ if (CY_TCPWM_INPUT_CREATOR != config->phiAInput)
+ {
+ base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT;
+ }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/tcpwm/cy_tcpwm_quaddec.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,302 @@
+/***************************************************************************//**
+* \file cy_tcpwm_quaddec.h
+* \version 1.0.1
+*
+* \brief
+* The header file of the TCPWM Quadrature Decoder driver.
+*
+********************************************************************************
+* \copyright
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#if !defined(CY_TCPWM_QUADDEC_H)
+#define CY_TCPWM_QUADDEC_H
+
+#include "cy_tcpwm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_tcpwm_quaddec
+* Driver API for Quadrature Decoder.
+* \{
+*/
+
+/**
+* \defgroup group_tcpwm_macros_quaddec Macros
+* \defgroup group_tcpwm_functions_quaddec Functions
+* \defgroup group_tcpwm_data_structures_quaddec Data Structures
+* \} */
+
+/**
+* \addtogroup group_tcpwm_data_structures_quaddec
+* \{
+*/
+
+/** Quadrature Decoder configuration structure */
+typedef struct cy_stc_tcpwm_quaddec_config
+{
+ /** Selects the quadrature encoding mode. See \ref group_tcpwm_quaddec_resolution */
+ uint32_t resolution;
+ /** Enables an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */
+ uint32_t interruptSources;
+ /** Configures how the index input behaves. See \ref group_tcpwm_input_modes */
+ uint32_t indexInputMode;
+ /** Selects which input the index uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t indexInput;
+ /** Configures how the stop input behaves. See \ref group_tcpwm_input_modes */
+ uint32_t stopInputMode;
+ /** Selects which input the stop uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */
+ uint32_t stopInput;
+ /** Selects which input the phiA uses. The inputs are device specific. See \ref group_tcpwm_input_selection */
+ uint32_t phiAInput;
+ /** Selects which input the phiB uses. The inputs are device specific. See \ref group_tcpwm_input_selection */
+ uint32_t phiBInput;
+
+}cy_stc_tcpwm_quaddec_config_t;
+/** \} group_tcpwm_data_structures_quaddec */
+
+/**
+* \addtogroup group_tcpwm_macros_quaddec
+* \{
+* \defgroup group_tcpwm_quaddec_resolution QuadDec Resolution
+* \{
+* The quadrature decoder resolution.
+*/
+#define CY_TCPWM_QUADDEC_X1 (0U) /**< X1 mode */
+#define CY_TCPWM_QUADDEC_X2 (1U) /**< X2 mode */
+#define CY_TCPWM_QUADDEC_X4 (2U) /**< X4 mode */
+/** \} group_tcpwm_quaddec_resolution */
+
+/** \defgroup group_tcpwm_quaddec_status QuadDec Status
+* \{
+* The counter status.
+*/
+#define CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING (0x1UL) /**< QuadDec is down counting */
+#define CY_TCPWM_QUADDEC_STATUS_UP_COUNTING (0x2UL) /**< QuadDec is up counting */
+/** QuadDec the counter is running */
+#define CY_TCPWM_QUADDEC_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk)
+/** \} group_tcpwm_quaddec_status */
+
+
+/***************************************
+* Registers Constants
+***************************************/
+/** \cond INTERNAL */
+#define CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE (0x3UL) /**< Quadrature encoding mode for CTRL register */
+/** \endcond */
+/** \} group_tcpwm_macros_quaddec */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_tcpwm_functions_quaddec
+* \{
+*/
+
+cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum,
+ cy_stc_tcpwm_quaddec_config_t const *config);
+void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config);
+__STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum);
+__STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count);
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uint32_t cntNum);
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_Enable
+****************************************************************************//**
+*
+* Enables the counter in the TCPWM block for the QuadDec operation.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_Init
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_SET = (1UL << cntNum);
+}
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_Disable
+****************************************************************************//**
+*
+* Disables the counter in the TCPWM block.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_DeInit
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum)
+{
+ base->CTRL_CLR = (1UL << cntNum);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_GetStatus
+****************************************************************************//**
+*
+* Returns the status of the QuadDec.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The status. See \ref group_tcpwm_quaddec_status
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_GetStatus
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum)
+{
+ uint32_t status = base->CNT[cntNum].STATUS;
+
+ /* Generates proper up counting status, does not generated by HW */
+ status &= ~CY_TCPWM_QUADDEC_STATUS_UP_COUNTING;
+ status |= ((~status & CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) <<
+ CY_TCPWM_CNT_STATUS_UP_POS);
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_GetCapture
+****************************************************************************//**
+*
+* Returns the capture value.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The capture value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_GetCaptureBuf
+****************************************************************************//**
+*
+* Returns the buffered capture value.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The buffered capture value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_Capture
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].CC_BUFF);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_SetCounter
+****************************************************************************//**
+*
+* Sets the value of the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \param count
+* The value to write into the counter.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_SetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count)
+{
+ base->CNT[cntNum].COUNTER = count;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TCPWM_QuadDec_GetCounter
+****************************************************************************//**
+*
+* Returns the value in the counter.
+*
+* \param base
+* The pointer to a TCPWM instance.
+*
+* \param cntNum
+* The Counter instance number in the selected TCPWM.
+*
+* \return
+* The current counter value.
+*
+* \funcusage
+* \snippet tcpwm/tcpwm_v1_0_quaddec_sut_01.cydsn/main_cm4.c snippet_Cy_TCPWM_QuadDec_GetCounter
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uint32_t cntNum)
+{
+ return(base->CNT[cntNum].COUNTER);
+}
+
+/** \} group_tcpwm_functions_quaddec */
+
+/** \} group_tcpwm_quaddec */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TCPWM_QUADDEC_H */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/trigmux/cy_trigmux.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,140 @@
+/***************************************************************************//**
+* \file cy_trigmux.c
+* \version 1.10
+*
+* \brief Trigger mux APIs.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "cy_trigmux.h"
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_Connect
+****************************************************************************//**
+*
+* This function connects an input trigger source and output trigger.
+*
+* \param inTrig
+* An input selection for the trigger mux.
+* - Bits 11:8 represent the trigger group selection.
+* - Bits 6:0 select the input trigger number in the trigger group.
+*
+* \param outTrig
+* The output of the trigger mux. This refers to the consumer of the trigger mux.
+* - Bits 11:8 represent the trigger group selection.
+* - Bits 6:0 select the output trigger number in the trigger group.
+*
+* \param invert
+* - true: The output trigger is inverted.
+* - false: The output trigger is not inverted.
+*
+* \param trigType
+* - TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock
+* and a two-cycle pulse is generated on this clock.
+* - TRIGGER_TYPE_LEVEL: The trigger is a simple level output.
+*
+* \return
+* A status
+* - 0: Successful connection made.
+* - 1: An invalid input selection corresponding to the output.
+* Generally when the trigger groups do not match.
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType)
+{
+ volatile uint32_t* trOutCtlAddr;
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM;
+
+ CY_ASSERT_L3(CY_LPCOMP_IS_TRIGTYPE_VALID(trigType));
+
+ /* inTrig and outTrig should be in the same group */
+ if ((inTrig & CY_TR_GROUP_MASK) == (outTrig & CY_TR_GROUP_MASK))
+ {
+ trOutCtlAddr = &(PERI->TR_GR[(outTrig & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT].TR_OUT_CTL[outTrig & CY_TR_MASK]);
+
+ *trOutCtlAddr = _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_SEL, inTrig) |
+ _BOOL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_INV, invert) |
+ _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_EDGE, trigType);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+
+ return retVal;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_TrigMux_SwTrigger
+****************************************************************************//**
+*
+* This function generates a software trigger on an input trigger line.
+* All output triggers connected to this input trigger will be triggered.
+* The function also verifies that there is no activated trigger before
+* generating another activation.
+*
+* \param trigLine
+* The input of the trigger mux.
+* - Bit 30 represents if the signal is an input/output. When this bit is set,
+* the trigger activation is for an output trigger from the trigger multiplexer.
+* When this bit is reset, the trigger activation is for an input trigger to
+* the trigger multiplexer.
+* - Bits 11:8 represent the trigger group selection.
+* - Bits 6:0 select the output trigger number in the trigger group.
+*
+* \param cycles
+* The number of cycles during which the trigger remains activated.
+* The valid range of cycles is 1-254.
+* These two additional special values can be passed to this parameter:
+* * CY_TRIGGER_INFINITE - The trigger will be active until the user
+* clears it;
+* * CY_TRIGGER_DEACTIVATE - The trigger will be deactivated forcibly.
+*
+* \return
+* A status
+* - 0: If there was not an already activated trigger.
+* - 1: If there was an already activated trigger.
+*
+*******************************************************************************/
+cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles)
+{
+ cy_en_trigmux_status_t retVal = CY_TRIGMUX_INVALID_STATE;
+
+ CY_ASSERT_L2(0U == (trigLine & (uint32_t)~CY_TR_PARAM_MASK));
+ CY_ASSERT_L2(CY_TR_CYCLES_MAX >= cycles);
+
+
+ if (CY_TRIGGER_DEACTIVATE != cycles)
+ {
+ if (PERI_TR_CMD_ACTIVATE_Msk != (PERI->TR_CMD & PERI_TR_CMD_ACTIVATE_Msk))
+ {
+ /* Activate the trigger if it is not in the active state. */
+ PERI->TR_CMD = _VAL2FLD(PERI_TR_CMD_TR_SEL, (trigLine & CY_TR_MASK)) |
+ _VAL2FLD(PERI_TR_CMD_GROUP_SEL, ((trigLine & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT)) |
+ _VAL2FLD(PERI_TR_CMD_COUNT, cycles) |
+ _VAL2FLD(PERI_TR_CMD_OUT_SEL, (trigLine & CY_TR_OUT_CTL_MASK) >> CY_TR_OUT_CTL_SHIFT) |
+ _VAL2FLD(PERI_TR_CMD_ACTIVATE, CY_TR_ACTIVATE_ENABLE);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+ }
+ else
+ {
+ if (PERI_TR_CMD_ACTIVATE_Msk == (PERI->TR_CMD & PERI_TR_CMD_ACTIVATE_Msk))
+ {
+ /* Forcibly deactivate the trigger. */
+ PERI->TR_CMD = _VAL2FLD(PERI_TR_CMD_TR_SEL, (trigLine & CY_TR_MASK)) |
+ _VAL2FLD(PERI_TR_CMD_GROUP_SEL, ((trigLine & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT)) |
+ _VAL2FLD(PERI_TR_CMD_OUT_SEL, (trigLine & CY_TR_OUT_CTL_MASK) >> CY_TR_OUT_CTL_SHIFT);
+
+ retVal = CY_TRIGMUX_SUCCESS;
+ }
+ }
+
+ return retVal;
+}
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/trigmux/cy_trigmux.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,227 @@
+/*******************************************************************************
+* \file cy_trigmux.h
+* \version 1.10
+*
+* This file provides constants and parameter values for the Trigger multiplexer driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+/**
+* \defgroup group_trigmux Trigger multiplexer (TrigMux)
+* \{
+* The trigger multiplexer provides access to the multiplexer that selects a set
+* of trigger output signals from different peripheral blocks to route them to the
+* specific trigger input of another peripheral block.
+*
+* The TrigMux driver is based on the trigger multiplexer's hardware block.
+* The Trigger multiplexer block consists of multiple trigger multiplexers.
+* These trigger multiplexers are grouped in trigger groups. All the trigger
+* multiplexers in the trigger group share similar input options. The trigger
+* multiplexer groups are either reduction multiplexers or distribution multiplexers.
+* Figure below illustrates a generic trigger multiplexer block implementation
+* with a reduction multiplexer layer of N trigger groups and a distribution multiplexer
+* layer of M trigger groups.
+* \image html trigmux_architecture.png
+* The reduction multiplexer groups have input options that are the trigger outputs
+* coming from the different peripheral blocks and the reduction multiplexer groups
+* route them to intermediate signals. The distribution multiplexer groups have input
+* options from these intermediate signals and route them back to multiple peripheral
+* blocks as their trigger inputs.
+*
+* The trigger architecture of the PSoC device is explained in the technical reference
+* manual (TRM). Refer to the TRM to better understand the trigger multiplexer routing
+* architecture available.
+*
+* \section group_trigmux_section_Configuration_Considerations Configuration Considerations
+*
+*
+* To route a trigger signal from one peripheral in the PSoC
+* to another, the user must configure a reduction multiplexer and a distribution
+* multiplexer. The Cy_TrigMux_connect() is used to configure a trigger multiplexer connection.
+* The user will need two calls of this API, one for the reduction multiplexer and another
+* for the distribution multiplexer, to achieve the trigger connection from a source
+* peripheral to a destination peripheral. The Cy_TrigMux_connect() function has two main
+* parameters, inTrig and outTrig that refer to the input and output trigger signals
+* connected using the multiplexer.
+*
+* These parameters are represented in the following format:
+* \image html trigmux_parameter_30.png
+* In addition, the Cy_TrigMux_connect() function also has an invert and trigger type parameter.
+* Refer to the API reference for a detailed description of this parameter.
+* All the constants associated with the different trigger signals in the system
+* (input and output) are defined as constants in the device configuration header file.
+* The constants for TrigMux in the device configuration header file are divided into four
+* types based on the signal being input/output and being part of a reduction/distribution
+* trigger multiplexer.
+*
+* The four types of the input/output parameters are:
+* 1) The parameters for the reduction multiplexer's inputs (input signals of TrigMux);
+* 2) The parameters for the reduction multiplexer's outputs (intermediate signals);
+* 3) The parameters for the distribution multiplexer's inputs (intermediate signals);
+* 4) The parameters for the distribution multiplexer's outputs (output signals of TrigMux).
+* Refer to the TRM for a more detailed description of this architecture and different options.
+*
+* The steps to connect one peripheral block to the other:
+*
+* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device
+* configuration header file that corresponds to the output of the first peripheral block.
+* For example, TRIG10_IN_CPUSS_DW0_TR_OUT4 input of the reduction multiplexers belongs
+* to Trigger Group 10.
+*
+* Step 2. Find the trigger group number in the Trigger Group Outputs section of the device
+* configuration header file that corresponds to the input of the second peripheral block.
+* For example, TRIG3_OUT_TCPWM1_TR_IN0 output of the distribution multiplexer belongs to
+* Trigger Group 3.
+*
+* Step 3. Find the same trigger group number in the Trigger Group Inputs section of the
+* device configuration header file that corresponds to the trigger group number found in
+* Step 1. Select the reduction multiplexer output that can be connected to the trigger group
+* found in Step 2. For example, TRIG3_IN_TR_GROUP10_OUTPUT5 means that Reduction Multiplexer
+* Output 5 of Trigger Group 10 can be connected to Trigger Group 3.
+*
+* Step 4. Find the same trigger group number in the Trigger Group Outputs section of the
+* device configuration header file that corresponds to the trigger group number found in Step 2.
+* Select the distribution multiplexer input that can be connected to the trigger group found
+* in Step 1. For example, TRIG10_OUT_TR_GROUP3_INPUT1 means that the Distribution Multiplexer
+* Input 1 of Trigger Group 3 can be connected to the output of the reduction multiplexer
+* in Trigger Group 10 found in Step 3.
+*
+* Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the
+* inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the
+* constants for the inTrig and outTrig parameters found in Steps 2 and Step 3.
+* For example,
+* Cy_TrigMux_Connect(TRIG10_IN_CPUSS_DW0_TR_OUT4, TRIG10_OUT_TR_GROUP3_INPUT1,
+* TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_LEVEL);
+* Cy_TrigMux_Connect(TRIG3_IN_TR_GROUP10_OUTPUT5, TRIG3_OUT_TCPWM1_TR_IN0,
+* TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_LEVEL);
+*
+* \section group_trigmux_more_information More Information
+* For more information on the TrigMux peripheral, refer to the technical reference manual (TRM).
+*
+* \section group_trigmux_MISRA MISRA-C Compliance
+* The TrigMux driver does not have any specific deviations.
+*
+* \section group_trigmux_Changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.10</td>
+* <td>The input/output bit in the trigLine parameter of the
+* Cy_TrigMux_SwTrigger() function is changed to 30.<br>
+* The invert parameter type is changed to bool.<br>
+* Added input parameter validation to the API functions.</td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_trigmux_macros Macros
+* \defgroup group_trigmux_functions Functions
+* \defgroup group_trigmux_enums Enumerated Types
+*/
+
+#if !defined(CY_TRIGMUX_H)
+#define CY_TRIGMUX_H
+
+#include "cy_device_headers.h"
+#include "syslib/cy_syslib.h"
+
+#ifndef CY_IP_MXPERI_TR
+ #error "The TRIGMUX driver is not supported on this device"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+* \addtogroup group_trigmux_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_TRIGMUX_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_TRIGMUX_DRV_VERSION_MINOR 10
+
+/**< TRIGMUX PDL ID */
+#define CY_TRIGMUX_ID CY_PDL_DRV_ID(0x33u) /**< The trigger multiplexer driver identifier */
+
+/**< TRIGMUX values for the cycles parameter in the Cy_TrigMux_SwTrigger() function */
+#define CY_TRIGGER_INFINITE (255u) /**< The trigger will be active until the user clears it or a hardware deactivates it. */
+#define CY_TRIGGER_DEACTIVATE (0u) /**< Use this parameter value to deactivate the trigger. */
+
+/** \cond */
+
+/******************************************************************************
+ * Macros
+ *****************************************************************************/
+
+#define CY_TR_MUX_TR_INV_ENABLE (0x01u)
+#define CY_TR_MUX_TR_INV_DISABLE (0x00u)
+#define CY_TR_ACTIVATE_DISABLE (0x00u)
+#define CY_TR_ACTIVATE_ENABLE (0x01u)
+#define CY_TR_GROUP_MASK (0x0F00u)
+#define CY_TR_MASK (0x007Fu)
+#define CY_TR_GROUP_SHIFT (0x08u)
+#define CY_TR_OUT_CTL_MASK (0x40000000uL)
+#define CY_TR_OUT_CTL_SHIFT (30u)
+#define CY_TR_PARAM_MASK (CY_TR_OUT_CTL_MASK | CY_TR_GROUP_MASK | CY_TR_MASK)
+#define CY_TR_CYCLES_MIN (0u)
+#define CY_TR_CYCLES_MAX (255u)
+
+#define CY_LPCOMP_IS_TRIGTYPE_VALID(trigType) (((trigType) == TRIGGER_TYPE_EDGE) || \
+ ((trigType) == TRIGGER_TYPE_LEVEL))
+
+/** \endcond */
+
+/** \} group_trigmux_macros */
+
+
+/**
+* \addtogroup group_trigmux_enums
+* \{
+*/
+
+/******************************************************************************
+ * Enumerations
+ *****************************************************************************/
+
+/** The TRIGMUX error codes. */
+typedef enum
+{
+ CY_TRIGMUX_SUCCESS = 0x00u, /**< Successful */
+ CY_TRIGMUX_BAD_PARAM = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
+ CY_TRIGMUX_INVALID_STATE = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x02u /**< Operation not setup or is in an improper state */
+} cy_en_trigmux_status_t;
+
+/** \} group_trigmux_enums */
+
+/**
+* \addtogroup group_trigmux_functions
+* \{
+*/
+
+cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType);
+cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles);
+
+/** \} group_trigmux_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_TRIGMUX_H */
+
+/** \} group_lpcomp */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/wdt/cy_wdt.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,203 @@
+/***************************************************************************//**
+* \file cy_wdt.c
+* \version 1.0.1
+*
+* This file provides the source code to the API for the WDT driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#include "cy_wdt.h"
+#include "syslib/cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+static bool Cy_WDT_Locked(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Init
+****************************************************************************//**
+*
+* Initializes the Watchdog timer to its default state.
+*
+* The given default setting of the WDT:
+* The WDT is unlocked and disabled.
+* The WDT match value is 4096.
+* None of ignore bits are set: the whole WDT counter bits are checked against
+* the match value.
+*
+*******************************************************************************/
+void Cy_WDT_Init(void)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* Unlock the WDT by two writes */
+ SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
+
+ SRSS->WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
+
+ Cy_WDT_Disable();
+
+ Cy_WDT_SetMatch(CY_SRSS_WDT_DEFAULT_MATCH_VALUE);
+
+ Cy_WDT_SetIgnoreBits(CY_SRSS_WDT_DEFAULT_IGNORE_BITS);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Lock
+****************************************************************************//**
+*
+* Locks out configuration changes to the Watchdog Timer register.
+*
+* After this function is called, the WDT configuration cannot be changed until
+* Cy_WDT_Unlock() is called.
+*
+*******************************************************************************/
+void Cy_WDT_Lock(void)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ SRSS->WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_LOCK, CY_SRSS_WDT_LOCK_BITS);
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Locked
+****************************************************************************//**
+* \internal
+* Reports the WDT lock state.
+*
+* \return true - if WDT is locked, and false - if WDT is unlocked.
+* \endinternal
+*******************************************************************************/
+static bool Cy_WDT_Locked(void)
+{
+ /* Prohibits writing to the WDT registers and LFCLK */
+ return (0u != _FLD2VAL(SRSS_WDT_CTL_WDT_LOCK, SRSS->WDT_CTL));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Unlock
+****************************************************************************//**
+*
+* Unlocks the Watchdog Timer configuration register.
+*
+*******************************************************************************/
+void Cy_WDT_Unlock(void)
+{
+ uint32_t interruptState;
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ /* The WDT lock is to be removed by two writes */
+ SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0);
+
+ SRSS->WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_SetMatch
+****************************************************************************//**
+*
+* Configures the WDT counter match comparison value. The Watchdog timer
+* should be unlocked before changing the match value. Call the Cy_WDT_Unlock()
+* function to unlock the WDT.
+*
+* \param match
+* The valid valid range is [0-65535]. The value to be used to match
+* against the counter.
+*
+*******************************************************************************/
+void Cy_WDT_SetMatch(uint32_t match)
+{
+ if (false == Cy_WDT_Locked())
+ {
+ SRSS->WDT_MATCH = _CLR_SET_FLD32U((SRSS->WDT_MATCH), SRSS_WDT_MATCH_MATCH, match);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_SetIgnoreBits
+****************************************************************************//**
+*
+* Configures the number of the most significant bits of the Watchdog timer that
+* are not checked against the match. Unlock the Watchdog timer before
+* ignoring the bits setting. Call the Cy_WDT_Unlock() API to unlock the WDT.
+*
+* \param bitsNum
+* The number of the most significant bits. The valid range is [0-15].
+* The bitsNum over 12 are considered as 12.
+*
+* \details The value of bitsNum controls the time-to-reset of the Watchdog timer
+* This happens after 3 successive matches.
+*
+* \warning This function changes the WDT interrupt period, therefore
+* the device can go into an infinite WDT reset loop. This may happen
+* if a WDT reset occurs faster that a device start-up.
+*
+*******************************************************************************/
+void Cy_WDT_SetIgnoreBits(uint32_t bitsNum)
+{
+ if (false == Cy_WDT_Locked())
+ {
+ SRSS->WDT_MATCH = _CLR_SET_FLD32U((SRSS->WDT_MATCH), SRSS_WDT_MATCH_IGNORE_BITS, bitsNum);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_ClearInterrupt
+****************************************************************************//**
+*
+* Clears the WDT match flag which is set every time the WDT counter reaches a
+* WDT match value. Two unserviced interrupts lead to a system reset
+* (i.e. at the third match).
+*
+*******************************************************************************/
+void Cy_WDT_ClearInterrupt(void)
+{
+ SRSS->SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1u);
+
+ /* Read the interrupt register to ensure that the initial clearing write has
+ * been flushed out to the hardware.
+ */
+ (void) SRSS->SRSS_INTR;
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_ClearWatchdog
+****************************************************************************//**
+*
+* Clears ("feeds") the watchdog, to prevent a XRES device reset.
+* This function simply call Cy_WDT_ClearInterrupt() function.
+*
+*******************************************************************************/
+void Cy_WDT_ClearWatchdog(void)
+{
+ Cy_WDT_ClearInterrupt();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/wdt/cy_wdt.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,367 @@
+/***************************************************************************//**
+* \file cy_wdt.h
+* \version 1.0.1
+*
+* This file provides constants and parameter values for the WDT driver.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*
+*******************************************************************************/
+
+/**
+* \defgroup group_wdt Watchdog Timer (WDT)
+* \{
+*
+* The Watchdog timer (WDT) has a 16-bit free-running up-counter. The WDT can
+* issue counter match interrupts, and a device reset if its interrupts are not
+* handled. Use the Watchdog timer for two main purposes.<br>
+* The <b> First use case </b> is recovering from a CPU or firmware failure.
+* A timeout period is set up in the Watchdog timer, and if a timeout occurs, the
+* device is reset (WRES). <br>
+* The <b>Second use case</b> is to generate periodic interrupts.
+* It is strongly recommended not to use the WDT for periodic interrupt
+* generation. However, if absolutely required, see information below.
+*
+* A "reset cause" register exists, and the firmware should check this register
+* at a start-up. An appropriate action can be taken if a WRES reset is detected.
+*
+* The user's firmware periodically resets the timeout period (clears or "feeds"
+* the watchdog) before a timeout occurs. If the firmware fails to do so, that is
+* considered to be a CPU crash or a firmware failure, and the reason for a
+* device reset.
+* The WDT can generate an interrupt instead of a device reset. The Interrupt
+* Service Routine (ISR) can handle the interrupt either as a periodic interrupt,
+* or as an early indication of a firmware failure and respond accordingly.
+* However, it is not recommended to use the WDT for periodic interrupt
+* generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate
+* periodic interrupts if such are presented in the device.
+*
+* <b> Functional Description </b> <br>
+* The WDT generates an interrupt when the count value in the counter equals the
+* configured match value.
+*
+* Note that the counter is not reset on a match. In such case the WDT
+* reset period is:
+* WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue);
+* When the counter reaches a match value, it generates an interrupt and then
+* keeps counting up until it overflows and rolls back to zero and reaches the
+* match value again, at which point another interrupt is generated.
+*
+* To use a WDT to generate a periodic interrupt, the match value should be
+* incremented in the ISR. As a result, the next WDT interrupt is generated when
+* the counter reaches a new match value.
+*
+* You can also reduce the entire WDT counter period by
+* specifying the number of most significant bits that are ignored in the WDT
+* counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with
+* parameter 3, the WDT counter becomes a 13-bit free-running up-counter.
+*
+* <b> Power Modes </b> <br>
+* WDT can operate in all possible low power modes.
+* Operation during Hibernate mode is possible because the logic and
+* high-voltage internal low oscillator (ILO) are supplied by the external
+* high-voltage supply (Vddd). The WDT can be configured to wake the device from
+* Hibernate mode.
+*
+* In Active or LPActive mode, an interrupt request from the WDT is sent to the
+* CPU via IRQ 22. In Sleep, LPSleep or Deep Sleep power mode, the CPU subsystem
+* is powered down, so the interrupt request from the WDT is sent directly to the
+* WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The
+* CPU then acknowledges the interrupt request and executes the ISR.
+*
+* <b> Clock Source </b> <br>
+* The WDT is clocked by the ILO. The WDT must be disabled before disabling
+* the ILO. According to the device datasheet, the ILO accuracy is +/-30% over
+* voltage and temperature. This means that the timeout period may vary by 30%
+* from the configured value. Appropriate margins should be added while
+* configuring WDT intervals to make sure that unwanted device resets do not
+* occur on some devices.
+*
+* Refer to the device datasheet for more information on the oscillator accuracy.
+*
+* <b> Register Locking </b> <br>
+* You can prevent accidental corruption of the WDT configuration by calling
+* the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*,
+* CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is
+* ignored.
+* Call the Cy_WDT_Unlock() function to allow WDT registers modification.
+*
+* <b> Clearing WDT </b> <br>
+* The ILO clock is asynchronous to the SysClk. Therefore it generally
+* takes three ILO cycles for WDT register changes to come into effect. It is
+* important to remember that a WDT should be cleared at least four cycles
+* (3 + 1 for sure) before a timeout occurs, especially when small
+* match values / low-toggle bit numbers are used.
+*
+* \warning It may happen that a WDT reset can be generated
+* faster than a device start-up. To prevent this, calculate the
+* start-up time and WDT reset time. The WDT reset time should be always smaller
+* than device start-up time.
+*
+* <b> Reset Detection </b> <br>
+* Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has
+* triggered a device reset.
+*
+* <b> Interrupt Configuration </b> <br>
+* The Global Signal Reference and Interrupt components can be used for ISR
+* configuration. If the WDT is configured to generate an interrupt, pending
+* interrupts must be cleared within the ISR (otherwise, the interrupt will be
+* generated continuously).
+* A pending interrupt to the WDT block must be cleared by calling the
+* Cy_WDT_ClearInterrupt() function. The call to the function will clear the
+* unhandled WDT interrupt counter.
+*
+* Use the WDT ISR as a timer to trigger certain actions
+* and to change a next WDT match value.
+*
+* Ensure that the interrupts from the WDT are passed to the CPU to avoid
+* unregistered interrupts. Unregistered WDT interrupts result in a continuous
+* device reset. To avoid this, call Cy_WDT_UnmaskInterrupt().
+* After that, call the WDT API functions for interrupt
+* handling/clearing.
+*
+* \section group_wdt_configuration Configuration Considerations
+*
+* To start the WDT, make sure that ILO is enabled.
+* After the ILO is enabled, ensure that the WDT is unlocked and disabled by
+* calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match
+* value by calling Cy_WDT_SetMatch() with the required match value. If needed,
+* set the ignore bits for reducing the WDT counter period by calling
+* Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set,
+* call Cy_WDT_Enable().
+*
+* \note Enable a WDT if the power supply can produce
+* sudden brownout events that may compromise the CPU functionality. This
+* ensures that the system can recover after a brownout.
+*
+* When the WDT is used to protect against system crashes, the
+* WDT interrupt should be cleared by a portion of the code that is not directly
+* associated with the WDT interrupt.
+* Otherwise, it is possible that the main firmware loop has crashed or is in an
+* endless loop, but the WDT interrupt vector continues to operate and service
+* the WDT. The user should:
+* * Feed the watchdog by clearing the interrupt bit regularly in the main body
+* of the firmware code.
+*
+* * Guarantee that the interrupt is cleared at least once every WDT period.
+*
+* * Use the WDT ISR only as a timer to trigger certain actions and to change the
+* next match value.
+*
+* \section group_wdt_section_more_information More Information
+*
+* For more information on the WDT peripheral, refer to the technical reference
+* manual (TRM).
+*
+* \section group_wdt_MISRA MISRA-C Compliance
+* The WDT driver does not have any specific deviations.
+*
+* \section group_wdt_changelog Changelog
+* <table class="doxtable">
+* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+* <tr>
+* <td>1.0.1</td>
+* <td>General documentation updates</td>
+* <td>Added info about periodic interrupt generation use case</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+* \defgroup group_wdt_macros Macros
+* \defgroup group_wdt_functions Functions
+*
+*/
+
+#if !defined(_WDT_H_)
+#define _WDT_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "cy_device_headers.h"
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Function Constants
+*******************************************************************************/
+
+/**
+* \addtogroup group_wdt_macros
+* \{
+*/
+
+/** The driver major version */
+#define CY_WDT_DRV_VERSION_MAJOR 1
+
+/** The driver minor version */
+#define CY_WDT_DRV_VERSION_MINOR 0
+
+/** The internal define for the first iteration of WDT unlocking */
+#define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u)
+
+/** The internal define for the second iteration of WDT unlocking */
+#define CY_SRSS_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u)
+
+/** The WDT default match value */
+#define CY_SRSS_WDT_DEFAULT_MATCH_VALUE ((uint32_t) 4096u)
+
+/** The default match value of the WDT ignore bits */
+#define CY_SRSS_WDT_DEFAULT_IGNORE_BITS (0u)
+
+/** The default match value of the WDT ignore bits */
+#define CY_SRSS_WDT_LOCK_BITS (3u)
+
+/** The WDT driver identifier */
+#define CY_WDT_ID CY_PDL_DRV_ID(0x34u)
+
+/** \} group_wdt_macros */
+
+
+/*******************************************************************************
+* Function Prototypes
+*******************************************************************************/
+
+/**
+* \addtogroup group_wdt_functions
+* @{
+*/
+/* WDT API */
+void Cy_WDT_Init(void);
+void Cy_WDT_Lock(void);
+void Cy_WDT_Unlock(void);
+void Cy_WDT_SetMatch(uint32_t match);
+void Cy_WDT_SetIgnoreBits(uint32_t bitsNum);
+void Cy_WDT_ClearInterrupt(void);
+void Cy_WDT_ClearWatchdog(void);
+
+__STATIC_INLINE void Cy_WDT_Enable(void);
+__STATIC_INLINE void Cy_WDT_Disable(void);
+__STATIC_INLINE uint32_t Cy_WDT_GetMatch(void);
+__STATIC_INLINE uint32_t Cy_WDT_GetCount(void);
+__STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void);
+__STATIC_INLINE void Cy_WDT_MaskInterrupt(void);
+__STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void);
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Enable
+****************************************************************************//**
+*
+* Enables the Watchdog timer.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_Enable(void)
+{
+ SRSS->WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1u);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_Disable
+****************************************************************************//**
+*
+* Disables the Watchdog timer. The Watchdog timer should be unlocked before being
+* disabled. Call the Cy_WDT_Unlock() API to unlock the WDT.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_Disable(void)
+{
+ SRSS->WDT_CTL &= ((uint32_t) ~(_VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1u)));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetMatch
+****************************************************************************//**
+*
+* Reads the WDT counter match comparison value.
+*
+* \return The counter match value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetMatch(void)
+{
+ return ((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_MATCH, SRSS->WDT_MATCH));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetCount
+****************************************************************************//**
+*
+* Reads the current WDT counter value.
+*
+* \return A live counter value.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetCount(void)
+{
+ return ((uint32_t) _FLD2VAL(SRSS_WDT_CNT_COUNTER, SRSS->WDT_CNT));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_GetIgnoreBits
+****************************************************************************//**
+*
+* Reads the number of the most significant bits of the Watchdog timer that are
+* not checked against the match.
+*
+* \return The number of the most significant bits.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void)
+{
+ return((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_IGNORE_BITS ,SRSS->WDT_MATCH));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_MaskInterrupt
+****************************************************************************//**
+*
+* After masking interrupts from the WDT, they are not passed to the CPU.
+* This function does not disable the WDT-reset generation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_MaskInterrupt(void)
+{
+ SRSS->SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1u));
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_WDT_UnmaskInterrupt
+****************************************************************************//**
+*
+* After unmasking interrupts from the WDT, they are passed to CPU.
+* This function does not impact the reset generation.
+*
+*******************************************************************************/
+__STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void)
+{
+ SRSS->SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1u);
+}
+/** \} group_wdt_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _WDT_H_ */
+
+/** \} group_wdt */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_backup.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,223 @@
+/***************************************************************************//**
+* \file cyip_backup.h
+*
+* \brief
+* BACKUP IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_BACKUP_H_
+#define _CYIP_BACKUP_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* BACKUP
+*******************************************************************************/
+
+#define BACKUP_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SRSS Backup Domain (BACKUP)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t RTC_RW; /*!< 0x00000008 RTC Read Write register */
+ __IOM uint32_t CAL_CTL; /*!< 0x0000000C Oscillator calibration for absolute frequency */
+ __IM uint32_t STATUS; /*!< 0x00000010 Status */
+ __IOM uint32_t RTC_TIME; /*!< 0x00000014 Calendar Seconds, Minutes, Hours, Day of Week */
+ __IOM uint32_t RTC_DATE; /*!< 0x00000018 Calendar Day of Month, Month, Year */
+ __IOM uint32_t ALM1_TIME; /*!< 0x0000001C Alarm 1 Seconds, Minute, Hours, Day of Week */
+ __IOM uint32_t ALM1_DATE; /*!< 0x00000020 Alarm 1 Day of Month, Month */
+ __IOM uint32_t ALM2_TIME; /*!< 0x00000024 Alarm 2 Seconds, Minute, Hours, Day of Week */
+ __IOM uint32_t ALM2_DATE; /*!< 0x00000028 Alarm 2 Day of Month, Month */
+ __IOM uint32_t INTR; /*!< 0x0000002C Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000030 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000034 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000038 Interrupt masked request register */
+ __IM uint32_t OSCCNT; /*!< 0x0000003C 32kHz oscillator counter */
+ __IM uint32_t TICKS; /*!< 0x00000040 128Hz tick counter */
+ __IOM uint32_t PMIC_CTL; /*!< 0x00000044 PMIC control register */
+ __IOM uint32_t RESET; /*!< 0x00000048 Backup reset register */
+ __IM uint32_t RESERVED1[1005];
+ __IOM uint32_t BREG[64]; /*!< 0x00001000 Backup register region */
+ __IM uint32_t RESERVED2[15232];
+ __IOM uint32_t TRIM; /*!< 0x0000FF00 Trim Register */
+} BACKUP_Type; /*!< Size = 65284 (0xFF04) */
+
+
+/* BACKUP.CTL */
+#define BACKUP_CTL_WCO_EN_Pos 3UL
+#define BACKUP_CTL_WCO_EN_Msk 0x8UL
+#define BACKUP_CTL_CLK_SEL_Pos 8UL
+#define BACKUP_CTL_CLK_SEL_Msk 0x300UL
+#define BACKUP_CTL_PRESCALER_Pos 12UL
+#define BACKUP_CTL_PRESCALER_Msk 0x3000UL
+#define BACKUP_CTL_WCO_BYPASS_Pos 16UL
+#define BACKUP_CTL_WCO_BYPASS_Msk 0x10000UL
+#define BACKUP_CTL_VDDBAK_CTL_Pos 17UL
+#define BACKUP_CTL_VDDBAK_CTL_Msk 0x60000UL
+#define BACKUP_CTL_VBACKUP_MEAS_Pos 19UL
+#define BACKUP_CTL_VBACKUP_MEAS_Msk 0x80000UL
+#define BACKUP_CTL_EN_CHARGE_KEY_Pos 24UL
+#define BACKUP_CTL_EN_CHARGE_KEY_Msk 0xFF000000UL
+/* BACKUP.RTC_RW */
+#define BACKUP_RTC_RW_READ_Pos 0UL
+#define BACKUP_RTC_RW_READ_Msk 0x1UL
+#define BACKUP_RTC_RW_WRITE_Pos 1UL
+#define BACKUP_RTC_RW_WRITE_Msk 0x2UL
+/* BACKUP.CAL_CTL */
+#define BACKUP_CAL_CTL_CALIB_VAL_Pos 0UL
+#define BACKUP_CAL_CTL_CALIB_VAL_Msk 0x3FUL
+#define BACKUP_CAL_CTL_CALIB_SIGN_Pos 6UL
+#define BACKUP_CAL_CTL_CALIB_SIGN_Msk 0x40UL
+#define BACKUP_CAL_CTL_CAL_OUT_Pos 31UL
+#define BACKUP_CAL_CTL_CAL_OUT_Msk 0x80000000UL
+/* BACKUP.STATUS */
+#define BACKUP_STATUS_RTC_BUSY_Pos 0UL
+#define BACKUP_STATUS_RTC_BUSY_Msk 0x1UL
+#define BACKUP_STATUS_WCO_OK_Pos 2UL
+#define BACKUP_STATUS_WCO_OK_Msk 0x4UL
+/* BACKUP.RTC_TIME */
+#define BACKUP_RTC_TIME_RTC_SEC_Pos 0UL
+#define BACKUP_RTC_TIME_RTC_SEC_Msk 0x7FUL
+#define BACKUP_RTC_TIME_RTC_MIN_Pos 8UL
+#define BACKUP_RTC_TIME_RTC_MIN_Msk 0x7F00UL
+#define BACKUP_RTC_TIME_RTC_HOUR_Pos 16UL
+#define BACKUP_RTC_TIME_RTC_HOUR_Msk 0x3F0000UL
+#define BACKUP_RTC_TIME_CTRL_12HR_Pos 22UL
+#define BACKUP_RTC_TIME_CTRL_12HR_Msk 0x400000UL
+#define BACKUP_RTC_TIME_RTC_DAY_Pos 24UL
+#define BACKUP_RTC_TIME_RTC_DAY_Msk 0x7000000UL
+/* BACKUP.RTC_DATE */
+#define BACKUP_RTC_DATE_RTC_DATE_Pos 0UL
+#define BACKUP_RTC_DATE_RTC_DATE_Msk 0x3FUL
+#define BACKUP_RTC_DATE_RTC_MON_Pos 8UL
+#define BACKUP_RTC_DATE_RTC_MON_Msk 0x1F00UL
+#define BACKUP_RTC_DATE_RTC_YEAR_Pos 16UL
+#define BACKUP_RTC_DATE_RTC_YEAR_Msk 0xFF0000UL
+/* BACKUP.ALM1_TIME */
+#define BACKUP_ALM1_TIME_ALM_SEC_Pos 0UL
+#define BACKUP_ALM1_TIME_ALM_SEC_Msk 0x7FUL
+#define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos 7UL
+#define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk 0x80UL
+#define BACKUP_ALM1_TIME_ALM_MIN_Pos 8UL
+#define BACKUP_ALM1_TIME_ALM_MIN_Msk 0x7F00UL
+#define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos 15UL
+#define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk 0x8000UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_Pos 16UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_Msk 0x3F0000UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos 23UL
+#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk 0x800000UL
+#define BACKUP_ALM1_TIME_ALM_DAY_Pos 24UL
+#define BACKUP_ALM1_TIME_ALM_DAY_Msk 0x7000000UL
+#define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos 31UL
+#define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk 0x80000000UL
+/* BACKUP.ALM1_DATE */
+#define BACKUP_ALM1_DATE_ALM_DATE_Pos 0UL
+#define BACKUP_ALM1_DATE_ALM_DATE_Msk 0x3FUL
+#define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos 7UL
+#define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk 0x80UL
+#define BACKUP_ALM1_DATE_ALM_MON_Pos 8UL
+#define BACKUP_ALM1_DATE_ALM_MON_Msk 0x1F00UL
+#define BACKUP_ALM1_DATE_ALM_MON_EN_Pos 15UL
+#define BACKUP_ALM1_DATE_ALM_MON_EN_Msk 0x8000UL
+#define BACKUP_ALM1_DATE_ALM_EN_Pos 31UL
+#define BACKUP_ALM1_DATE_ALM_EN_Msk 0x80000000UL
+/* BACKUP.ALM2_TIME */
+#define BACKUP_ALM2_TIME_ALM_SEC_Pos 0UL
+#define BACKUP_ALM2_TIME_ALM_SEC_Msk 0x7FUL
+#define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos 7UL
+#define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk 0x80UL
+#define BACKUP_ALM2_TIME_ALM_MIN_Pos 8UL
+#define BACKUP_ALM2_TIME_ALM_MIN_Msk 0x7F00UL
+#define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos 15UL
+#define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk 0x8000UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_Pos 16UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_Msk 0x3F0000UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos 23UL
+#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk 0x800000UL
+#define BACKUP_ALM2_TIME_ALM_DAY_Pos 24UL
+#define BACKUP_ALM2_TIME_ALM_DAY_Msk 0x7000000UL
+#define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos 31UL
+#define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk 0x80000000UL
+/* BACKUP.ALM2_DATE */
+#define BACKUP_ALM2_DATE_ALM_DATE_Pos 0UL
+#define BACKUP_ALM2_DATE_ALM_DATE_Msk 0x3FUL
+#define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos 7UL
+#define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk 0x80UL
+#define BACKUP_ALM2_DATE_ALM_MON_Pos 8UL
+#define BACKUP_ALM2_DATE_ALM_MON_Msk 0x1F00UL
+#define BACKUP_ALM2_DATE_ALM_MON_EN_Pos 15UL
+#define BACKUP_ALM2_DATE_ALM_MON_EN_Msk 0x8000UL
+#define BACKUP_ALM2_DATE_ALM_EN_Pos 31UL
+#define BACKUP_ALM2_DATE_ALM_EN_Msk 0x80000000UL
+/* BACKUP.INTR */
+#define BACKUP_INTR_ALARM1_Pos 0UL
+#define BACKUP_INTR_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_ALARM2_Pos 1UL
+#define BACKUP_INTR_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_CENTURY_Pos 2UL
+#define BACKUP_INTR_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_SET */
+#define BACKUP_INTR_SET_ALARM1_Pos 0UL
+#define BACKUP_INTR_SET_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_SET_ALARM2_Pos 1UL
+#define BACKUP_INTR_SET_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_SET_CENTURY_Pos 2UL
+#define BACKUP_INTR_SET_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_MASK */
+#define BACKUP_INTR_MASK_ALARM1_Pos 0UL
+#define BACKUP_INTR_MASK_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_MASK_ALARM2_Pos 1UL
+#define BACKUP_INTR_MASK_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_MASK_CENTURY_Pos 2UL
+#define BACKUP_INTR_MASK_CENTURY_Msk 0x4UL
+/* BACKUP.INTR_MASKED */
+#define BACKUP_INTR_MASKED_ALARM1_Pos 0UL
+#define BACKUP_INTR_MASKED_ALARM1_Msk 0x1UL
+#define BACKUP_INTR_MASKED_ALARM2_Pos 1UL
+#define BACKUP_INTR_MASKED_ALARM2_Msk 0x2UL
+#define BACKUP_INTR_MASKED_CENTURY_Pos 2UL
+#define BACKUP_INTR_MASKED_CENTURY_Msk 0x4UL
+/* BACKUP.OSCCNT */
+#define BACKUP_OSCCNT_CNT32KHZ_Pos 0UL
+#define BACKUP_OSCCNT_CNT32KHZ_Msk 0xFFUL
+/* BACKUP.TICKS */
+#define BACKUP_TICKS_CNT128HZ_Pos 0UL
+#define BACKUP_TICKS_CNT128HZ_Msk 0x3FUL
+/* BACKUP.PMIC_CTL */
+#define BACKUP_PMIC_CTL_UNLOCK_Pos 8UL
+#define BACKUP_PMIC_CTL_UNLOCK_Msk 0xFF00UL
+#define BACKUP_PMIC_CTL_POLARITY_Pos 16UL
+#define BACKUP_PMIC_CTL_POLARITY_Msk 0x10000UL
+#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos 29UL
+#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk 0x20000000UL
+#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos 30UL
+#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk 0x40000000UL
+#define BACKUP_PMIC_CTL_PMIC_EN_Pos 31UL
+#define BACKUP_PMIC_CTL_PMIC_EN_Msk 0x80000000UL
+/* BACKUP.RESET */
+#define BACKUP_RESET_RESET_Pos 31UL
+#define BACKUP_RESET_RESET_Msk 0x80000000UL
+/* BACKUP.BREG */
+#define BACKUP_BREG_BREG_Pos 0UL
+#define BACKUP_BREG_BREG_Msk 0xFFFFFFFFUL
+/* BACKUP.TRIM */
+#define BACKUP_TRIM_TRIM_Pos 0UL
+#define BACKUP_TRIM_TRIM_Msk 0x3FUL
+
+
+#endif /* _CYIP_BACKUP_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_ble.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2244 @@
+/***************************************************************************//**
+* \file cyip_ble.h
+*
+* \brief
+* BLE IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_BLE_H_
+#define _CYIP_BLE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* BLE
+*******************************************************************************/
+
+#define BLE_RCB_RCBLL_SECTION_SIZE 0x00000100UL
+#define BLE_RCB_SECTION_SIZE 0x00000200UL
+#define BLE_BLELL_SECTION_SIZE 0x0001E000UL
+#define BLE_BLESS_SECTION_SIZE 0x00001000UL
+#define BLE_SECTION_SIZE 0x00020000UL
+
+/**
+ * \brief Radio Control Bus (RCB) & Link Layer controller (BLE_RCB_RCBLL)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 RCB LL control register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t INTR; /*!< 0x00000010 Master interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 Master interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Master interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Master interrupt masked request register */
+ __IOM uint32_t RADIO_REG1_ADDR; /*!< 0x00000020 Address of Register#1 in Radio (MDON) */
+ __IOM uint32_t RADIO_REG2_ADDR; /*!< 0x00000024 Address of Register#2 in Radio (RSSI) */
+ __IOM uint32_t RADIO_REG3_ADDR; /*!< 0x00000028 Address of Register#3 in Radio (ACCL) */
+ __IOM uint32_t RADIO_REG4_ADDR; /*!< 0x0000002C Address of Register#4 in Radio (ACCH) */
+ __IOM uint32_t RADIO_REG5_ADDR; /*!< 0x00000030 Address of Register#5 in Radio (RSSI ENERGY) */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t CPU_WRITE_REG; /*!< 0x00000040 N/A */
+ __IOM uint32_t CPU_READ_REG; /*!< 0x00000044 N/A */
+ __IM uint32_t RESERVED2[46];
+} BLE_RCB_RCBLL_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Radio Control Bus (RCB) controller (BLE_RCB)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 RCB control register. */
+ __IM uint32_t STATUS; /*!< 0x00000004 RCB status register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t TX_CTRL; /*!< 0x00000010 Transmitter control register. */
+ __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000014 Transmitter FIFO control register. */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000018 Transmitter FIFO status register. */
+ __OM uint32_t TX_FIFO_WR; /*!< 0x0000001C Transmitter FIFO write register. */
+ __IOM uint32_t RX_CTRL; /*!< 0x00000020 Receiver control register. */
+ __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000024 Receiver FIFO control register. */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000028 Receiver FIFO status register. */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x0000002C Receiver FIFO read register. */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000030 Receiver FIFO read register. */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t INTR; /*!< 0x00000040 Master interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000044 Master interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000048 Master interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000004C Master interrupt masked request register */
+ __IM uint32_t RESERVED2[44];
+ BLE_RCB_RCBLL_Type RCBLL; /*!< 0x00000100 Radio Control Bus (RCB) & Link Layer controller */
+} BLE_RCB_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief Bluetooth Low Energy Link Layer (BLE_BLELL)
+ */
+typedef struct {
+ __OM uint32_t COMMAND_REGISTER; /*!< 0x00000000 Instruction Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t EVENT_INTR; /*!< 0x00000008 Event(Interrupt) status and Clear register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENT_ENABLE; /*!< 0x00000010 Event indications enable. */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ADV_PARAMS; /*!< 0x00000018 Advertising parameters register. */
+ __IOM uint32_t ADV_INTERVAL_TIMEOUT; /*!< 0x0000001C Advertising interval register. */
+ __IOM uint32_t ADV_INTR; /*!< 0x00000020 Advertising interrupt status and Clear register */
+ __IM uint32_t ADV_NEXT_INSTANT; /*!< 0x00000024 Advertising next instant. */
+ __IOM uint32_t SCAN_INTERVAL; /*!< 0x00000028 Scan Interval Register */
+ __IOM uint32_t SCAN_WINDOW; /*!< 0x0000002C Scan window Register */
+ __IOM uint32_t SCAN_PARAM; /*!< 0x00000030 Scanning parameters register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SCAN_INTR; /*!< 0x00000038 Scan interrupt status and Clear register */
+ __IM uint32_t SCAN_NEXT_INSTANT; /*!< 0x0000003C Advertising next instant. */
+ __IOM uint32_t INIT_INTERVAL; /*!< 0x00000040 Initiator Interval Register */
+ __IOM uint32_t INIT_WINDOW; /*!< 0x00000044 Initiator window Register */
+ __IOM uint32_t INIT_PARAM; /*!< 0x00000048 Initiator parameters register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t INIT_INTR; /*!< 0x00000050 Scan interrupt status and Clear register */
+ __IM uint32_t INIT_NEXT_INSTANT; /*!< 0x00000054 Initiator next instant. */
+ __IOM uint32_t DEVICE_RAND_ADDR_L; /*!< 0x00000058 Lower 16 bit random address of the device. */
+ __IOM uint32_t DEVICE_RAND_ADDR_M; /*!< 0x0000005C Middle 16 bit random address of the device. */
+ __IOM uint32_t DEVICE_RAND_ADDR_H; /*!< 0x00000060 Higher 16 bit random address of the device. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PEER_ADDR_L; /*!< 0x00000068 Lower 16 bit address of the peer device. */
+ __IOM uint32_t PEER_ADDR_M; /*!< 0x0000006C Middle 16 bit address of the peer device. */
+ __IOM uint32_t PEER_ADDR_H; /*!< 0x00000070 Higher 16 bit address of the peer device. */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t WL_ADDR_TYPE; /*!< 0x00000078 whitelist address type */
+ __IOM uint32_t WL_ENABLE; /*!< 0x0000007C whitelist valid entry bit */
+ __IOM uint32_t TRANSMIT_WINDOW_OFFSET; /*!< 0x00000080 Transmit window offset */
+ __IOM uint32_t TRANSMIT_WINDOW_SIZE; /*!< 0x00000084 Transmit window size */
+ __IOM uint32_t DATA_CHANNELS_L0; /*!< 0x00000088 Data channel map 0 (lower word) */
+ __IOM uint32_t DATA_CHANNELS_M0; /*!< 0x0000008C Data channel map 0 (middle word) */
+ __IOM uint32_t DATA_CHANNELS_H0; /*!< 0x00000090 Data channel map 0 (upper word) */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t DATA_CHANNELS_L1; /*!< 0x00000098 Data channel map 1 (lower word) */
+ __IOM uint32_t DATA_CHANNELS_M1; /*!< 0x0000009C Data channel map 1 (middle word) */
+ __IOM uint32_t DATA_CHANNELS_H1; /*!< 0x000000A0 Data channel map 1 (upper word) */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t CONN_INTR; /*!< 0x000000A8 Connection interrupt status and Clear register */
+ __IM uint32_t CONN_STATUS; /*!< 0x000000AC Connection channel status */
+ __IOM uint32_t CONN_INDEX; /*!< 0x000000B0 Connection Index register */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t WAKEUP_CONFIG; /*!< 0x000000B8 Wakeup configuration */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t WAKEUP_CONTROL; /*!< 0x000000C0 Wakeup control */
+ __IOM uint32_t CLOCK_CONFIG; /*!< 0x000000C4 Clock control */
+ __IM uint32_t TIM_COUNTER_L; /*!< 0x000000C8 Reference Clock */
+ __IOM uint32_t WAKEUP_CONFIG_EXTD; /*!< 0x000000CC Wakeup configuration extended */
+ __IM uint32_t RESERVED11[2];
+ __IOM uint32_t POC_REG__TIM_CONTROL; /*!< 0x000000D8 BLE Time Control */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t ADV_TX_DATA_FIFO; /*!< 0x000000E0 Advertising data transmit FIFO. Access ADVCH_TX_FIFO. */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t ADV_SCN_RSP_TX_FIFO; /*!< 0x000000E8 Advertising scan response data transmit FIFO. Access
+ ADVCH_TX_FIFO. */
+ __IM uint32_t RESERVED14[3];
+ __IM uint32_t INIT_SCN_ADV_RX_FIFO; /*!< 0x000000F8 advertising scan response data receive data FIFO. Access
+ ADVRX_FIFO. */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t CONN_INTERVAL; /*!< 0x00000100 Connection Interval */
+ __IOM uint32_t SUP_TIMEOUT; /*!< 0x00000104 Supervision timeout */
+ __IOM uint32_t SLAVE_LATENCY; /*!< 0x00000108 Slave Latency */
+ __IOM uint32_t CE_LENGTH; /*!< 0x0000010C Connection event length */
+ __IOM uint32_t PDU_ACCESS_ADDR_L_REGISTER; /*!< 0x00000110 Access address (lower) */
+ __IOM uint32_t PDU_ACCESS_ADDR_H_REGISTER; /*!< 0x00000114 Access address (upper) */
+ __IOM uint32_t CONN_CE_INSTANT; /*!< 0x00000118 Connection event instant */
+ __IOM uint32_t CE_CNFG_STS_REGISTER; /*!< 0x0000011C connection configuration & status register */
+ __IM uint32_t NEXT_CE_INSTANT; /*!< 0x00000120 Next connection event instant */
+ __IM uint32_t CONN_CE_COUNTER; /*!< 0x00000124 connection event counter */
+ __IOM uint32_t DATA_LIST_SENT_UPDATE__STATUS; /*!< 0x00000128 data list sent update and status */
+ __IOM uint32_t DATA_LIST_ACK_UPDATE__STATUS; /*!< 0x0000012C data list ack update and status */
+ __IOM uint32_t CE_CNFG_STS_REGISTER_EXT; /*!< 0x00000130 connection configuration & status register */
+ __IOM uint32_t CONN_EXT_INTR; /*!< 0x00000134 Connection extended interrupt status and Clear register */
+ __IOM uint32_t CONN_EXT_INTR_MASK; /*!< 0x00000138 Connection Extended Interrupt mask */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t DATA_MEM_DESCRIPTOR[5]; /*!< 0x00000140 Data buffer descriptor 0 to 4 */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t WINDOW_WIDEN_INTVL; /*!< 0x00000160 Window widen for interval */
+ __IOM uint32_t WINDOW_WIDEN_WINOFF; /*!< 0x00000164 Window widen for offset */
+ __IM uint32_t RESERVED18[2];
+ __IOM uint32_t LE_RF_TEST_MODE; /*!< 0x00000170 Direct Test Mode control */
+ __IM uint32_t DTM_RX_PKT_COUNT; /*!< 0x00000174 Direct Test Mode receive packet count */
+ __IOM uint32_t LE_RF_TEST_MODE_EXT; /*!< 0x00000178 Direct Test Mode control */
+ __IM uint32_t RESERVED19[3];
+ __IM uint32_t TXRX_HOP; /*!< 0x00000188 Channel Address register */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TX_RX_ON_DELAY; /*!< 0x00000190 Transmit/Receive data delay */
+ __IM uint32_t RESERVED21[5];
+ __IOM uint32_t ADV_ACCADDR_L; /*!< 0x000001A8 ADV packet access code low word */
+ __IOM uint32_t ADV_ACCADDR_H; /*!< 0x000001AC ADV packet access code high word */
+ __IOM uint32_t ADV_CH_TX_POWER_LVL_LS; /*!< 0x000001B0 Advertising channel transmit power setting */
+ __IOM uint32_t ADV_CH_TX_POWER_LVL_MS; /*!< 0x000001B4 Advertising channel transmit power setting extension */
+ __IOM uint32_t CONN_CH_TX_POWER_LVL_LS; /*!< 0x000001B8 Connection channel transmit power setting */
+ __IOM uint32_t CONN_CH_TX_POWER_LVL_MS; /*!< 0x000001BC Connection channel transmit power setting extension */
+ __IOM uint32_t DEV_PUB_ADDR_L; /*!< 0x000001C0 Device public address lower register */
+ __IOM uint32_t DEV_PUB_ADDR_M; /*!< 0x000001C4 Device public address middle register */
+ __IOM uint32_t DEV_PUB_ADDR_H; /*!< 0x000001C8 Device public address higher register */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t OFFSET_TO_FIRST_INSTANT; /*!< 0x000001D0 Offset to first instant */
+ __IOM uint32_t ADV_CONFIG; /*!< 0x000001D4 Advertiser configuration register */
+ __IOM uint32_t SCAN_CONFIG; /*!< 0x000001D8 Scan configuration register */
+ __IOM uint32_t INIT_CONFIG; /*!< 0x000001DC Initiator configuration register */
+ __IOM uint32_t CONN_CONFIG; /*!< 0x000001E0 Connection configuration register */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t CONN_PARAM1; /*!< 0x000001E8 Connection parameter 1 */
+ __IOM uint32_t CONN_PARAM2; /*!< 0x000001EC Connection parameter 2 */
+ __IOM uint32_t CONN_INTR_MASK; /*!< 0x000001F0 Connection Interrupt mask */
+ __IOM uint32_t SLAVE_TIMING_CONTROL; /*!< 0x000001F4 slave timing control */
+ __IOM uint32_t RECEIVE_TRIG_CTRL; /*!< 0x000001F8 Receive trigger control */
+ __IM uint32_t RESERVED24;
+ __IM uint32_t LL_DBG_1; /*!< 0x00000200 LL debug register 1 */
+ __IM uint32_t LL_DBG_2; /*!< 0x00000204 LL debug register 2 */
+ __IM uint32_t LL_DBG_3; /*!< 0x00000208 LL debug register 3 */
+ __IM uint32_t LL_DBG_4; /*!< 0x0000020C LL debug register 4 */
+ __IM uint32_t LL_DBG_5; /*!< 0x00000210 LL debug register 5 */
+ __IM uint32_t LL_DBG_6; /*!< 0x00000214 LL debug register 6 */
+ __IM uint32_t LL_DBG_7; /*!< 0x00000218 LL debug register 7 */
+ __IM uint32_t LL_DBG_8; /*!< 0x0000021C LL debug register 8 */
+ __IM uint32_t LL_DBG_9; /*!< 0x00000220 LL debug register 9 */
+ __IM uint32_t LL_DBG_10; /*!< 0x00000224 LL debug register 10 */
+ __IM uint32_t RESERVED25[2];
+ __IOM uint32_t PEER_ADDR_INIT_L; /*!< 0x00000230 Lower 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_ADDR_INIT_M; /*!< 0x00000234 Middle 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_ADDR_INIT_H; /*!< 0x00000238 Higher 16 bit address of the peer device for INIT. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_L; /*!< 0x0000023C Lower 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_M; /*!< 0x00000240 Middle 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t PEER_SEC_ADDR_ADV_H; /*!< 0x00000244 Higher 16 bits of the secondary address of the peer device for
+ ADV_DIR. */
+ __IOM uint32_t INIT_WINDOW_TIMER_CTRL; /*!< 0x00000248 Initiator Window NI timer control */
+ __IOM uint32_t CONN_CONFIG_EXT; /*!< 0x0000024C Connection extended configuration register */
+ __IM uint32_t RESERVED26[2];
+ __IOM uint32_t DPLL_CONFIG; /*!< 0x00000258 DPLL & CY Correlator configuration register */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t INIT_NI_VAL; /*!< 0x00000260 Initiator Window NI instant */
+ __IM uint32_t INIT_WINDOW_OFFSET; /*!< 0x00000264 Initiator Window offset captured at conn request */
+ __IM uint32_t INIT_WINDOW_NI_ANCHOR_PT; /*!< 0x00000268 Initiator Window NI anchor point captured at conn request */
+ __IM uint32_t RESERVED28[78];
+ __IOM uint32_t CONN_UPDATE_NEW_INTERVAL; /*!< 0x000003A4 Connection update new interval */
+ __IOM uint32_t CONN_UPDATE_NEW_LATENCY; /*!< 0x000003A8 Connection update new latency */
+ __IOM uint32_t CONN_UPDATE_NEW_SUP_TO; /*!< 0x000003AC Connection update new supervision timeout */
+ __IOM uint32_t CONN_UPDATE_NEW_SL_INTERVAL; /*!< 0x000003B0 Connection update new Slave Latency X Conn interval Value */
+ __IM uint32_t RESERVED29[3];
+ __IOM uint32_t CONN_REQ_WORD0; /*!< 0x000003C0 Connection request address word 0 */
+ __IOM uint32_t CONN_REQ_WORD1; /*!< 0x000003C4 Connection request address word 1 */
+ __IOM uint32_t CONN_REQ_WORD2; /*!< 0x000003C8 Connection request address word 2 */
+ __IOM uint32_t CONN_REQ_WORD3; /*!< 0x000003CC Connection request address word 3 */
+ __IOM uint32_t CONN_REQ_WORD4; /*!< 0x000003D0 Connection request address word 4 */
+ __IOM uint32_t CONN_REQ_WORD5; /*!< 0x000003D4 Connection request address word 5 */
+ __IOM uint32_t CONN_REQ_WORD6; /*!< 0x000003D8 Connection request address word 6 */
+ __IOM uint32_t CONN_REQ_WORD7; /*!< 0x000003DC Connection request address word 7 */
+ __IOM uint32_t CONN_REQ_WORD8; /*!< 0x000003E0 Connection request address word 8 */
+ __IOM uint32_t CONN_REQ_WORD9; /*!< 0x000003E4 Connection request address word 9 */
+ __IOM uint32_t CONN_REQ_WORD10; /*!< 0x000003E8 Connection request address word 10 */
+ __IOM uint32_t CONN_REQ_WORD11; /*!< 0x000003EC Connection request address word 11 */
+ __IM uint32_t RESERVED30[389];
+ __IOM uint32_t PDU_RESP_TIMER; /*!< 0x00000A04 PDU response timer/Generic Timer (MMMS mode) */
+ __IM uint32_t NEXT_RESP_TIMER_EXP; /*!< 0x00000A08 Next response timeout instant */
+ __IM uint32_t NEXT_SUP_TO; /*!< 0x00000A0C Next supervision timeout instant */
+ __IOM uint32_t LLH_FEATURE_CONFIG; /*!< 0x00000A10 Feature enable */
+ __IOM uint32_t WIN_MIN_STEP_SIZE; /*!< 0x00000A14 Window minimum step size */
+ __IOM uint32_t SLV_WIN_ADJ; /*!< 0x00000A18 Slave window adjustment */
+ __IOM uint32_t SL_CONN_INTERVAL; /*!< 0x00000A1C Slave Latency X Conn Interval Value */
+ __IOM uint32_t LE_PING_TIMER_ADDR; /*!< 0x00000A20 LE Ping connection timer address */
+ __IOM uint32_t LE_PING_TIMER_OFFSET; /*!< 0x00000A24 LE Ping connection timer offset */
+ __IM uint32_t LE_PING_TIMER_NEXT_EXP; /*!< 0x00000A28 LE Ping timer next expiry instant */
+ __IM uint32_t LE_PING_TIMER_WRAP_COUNT; /*!< 0x00000A2C LE Ping Timer wrap count */
+ __IM uint32_t RESERVED31[244];
+ __IOM uint32_t TX_EN_EXT_DELAY; /*!< 0x00000E00 Transmit enable extension delay */
+ __IOM uint32_t TX_RX_SYNTH_DELAY; /*!< 0x00000E04 Transmit/Receive enable delay */
+ __IOM uint32_t EXT_PA_LNA_DLY_CNFG; /*!< 0x00000E08 External TX PA and RX LNA delay configuration */
+ __IM uint32_t RESERVED32;
+ __IOM uint32_t LL_CONFIG; /*!< 0x00000E10 Link Layer additional configuration */
+ __IM uint32_t RESERVED33[59];
+ __IOM uint32_t LL_CONTROL; /*!< 0x00000F00 LL Backward compatibility */
+ __IOM uint32_t DEV_PA_ADDR_L; /*!< 0x00000F04 Device Resolvable/Non-Resolvable Private address lower register */
+ __IOM uint32_t DEV_PA_ADDR_M; /*!< 0x00000F08 Device Resolvable/Non-Resolvable Private address middle
+ register */
+ __IOM uint32_t DEV_PA_ADDR_H; /*!< 0x00000F0C Device Resolvable/Non-Resolvable Private address higher
+ register */
+ __IOM uint32_t RSLV_LIST_ENABLE[16]; /*!< 0x00000F10 Resolving list entry control bit */
+ __IM uint32_t RESERVED34[20];
+ __IOM uint32_t WL_CONNECTION_STATUS; /*!< 0x00000FA0 whitelist valid entry bit */
+ __IM uint32_t RESERVED35[535];
+ __IOM uint32_t CONN_RXMEM_BASE_ADDR_DLE; /*!< 0x00001800 DLE Connection RX memory base address */
+ __IM uint32_t RESERVED36[1023];
+ __IOM uint32_t CONN_TXMEM_BASE_ADDR_DLE; /*!< 0x00002800 DLE Connection TX memory base address */
+ __IM uint32_t RESERVED37[16383];
+ __IOM uint32_t CONN_1_PARAM_MEM_BASE_ADDR; /*!< 0x00012800 Connection Parameter memory base address for connection 1 */
+ __IM uint32_t RESERVED38[31];
+ __IOM uint32_t CONN_2_PARAM_MEM_BASE_ADDR; /*!< 0x00012880 Connection Parameter memory base address for connection 2 */
+ __IM uint32_t RESERVED39[31];
+ __IOM uint32_t CONN_3_PARAM_MEM_BASE_ADDR; /*!< 0x00012900 Connection Parameter memory base address for connection 3 */
+ __IM uint32_t RESERVED40[31];
+ __IOM uint32_t CONN_4_PARAM_MEM_BASE_ADDR; /*!< 0x00012980 Connection Parameter memory base address for connection 4 */
+ __IM uint32_t RESERVED41[1439];
+ __IOM uint32_t NI_TIMER; /*!< 0x00014000 Next Instant Timer */
+ __IOM uint32_t US_OFFSET; /*!< 0x00014004 Micro-second Offset */
+ __IOM uint32_t NEXT_CONN; /*!< 0x00014008 Next Connection */
+ __IOM uint32_t NI_ABORT; /*!< 0x0001400C Abort next scheduled connection */
+ __IM uint32_t RESERVED42[4];
+ __IM uint32_t CONN_NI_STATUS; /*!< 0x00014020 Connection NI Status */
+ __IM uint32_t NEXT_SUP_TO_STATUS; /*!< 0x00014024 Next Supervision timeout Status */
+ __IM uint32_t MMMS_CONN_STATUS; /*!< 0x00014028 Connection Status */
+ __IM uint32_t BT_SLOT_CAPT_STATUS; /*!< 0x0001402C BT Slot Captured Status */
+ __IM uint32_t US_CAPT_STATUS; /*!< 0x00014030 Micro-second Capture Status */
+ __IM uint32_t US_OFFSET_STATUS; /*!< 0x00014034 Micro-second Offset Status */
+ __IM uint32_t ACCU_WINDOW_WIDEN_STATUS; /*!< 0x00014038 Accumulated Window Widen Status */
+ __IM uint32_t EARLY_INTR_STATUS; /*!< 0x0001403C Status when early interrupt is raised */
+ __IOM uint32_t MMMS_CONFIG; /*!< 0x00014040 Multi-Master Multi-Slave Config */
+ __IM uint32_t US_COUNTER; /*!< 0x00014044 Running US of the current BT Slot */
+ __IOM uint32_t US_CAPT_PREV; /*!< 0x00014048 Previous captured US of the BT Slot */
+ __IM uint32_t EARLY_INTR_NI; /*!< 0x0001404C NI at early interrupt */
+ __IM uint32_t RESERVED43[12];
+ __IM uint32_t MMMS_MASTER_CREATE_BT_CAPT; /*!< 0x00014080 BT slot capture for master connection creation */
+ __IM uint32_t MMMS_SLAVE_CREATE_BT_CAPT; /*!< 0x00014084 BT slot capture for slave connection creation */
+ __IM uint32_t MMMS_SLAVE_CREATE_US_CAPT; /*!< 0x00014088 Micro second capture for slave connection creation */
+ __IM uint32_t RESERVED44[29];
+ __IOM uint32_t MMMS_DATA_MEM_DESCRIPTOR[16]; /*!< 0x00014100 Data buffer descriptor 0 to 15 */
+ __IM uint32_t RESERVED45[48];
+ __IOM uint32_t CONN_1_DATA_LIST_SENT; /*!< 0x00014200 data list sent update and status for connection 1 */
+ __IOM uint32_t CONN_1_DATA_LIST_ACK; /*!< 0x00014204 data list ack update and status for connection 1 */
+ __IOM uint32_t CONN_1_CE_DATA_LIST_CFG; /*!< 0x00014208 Connection specific pause resume for connection 1 */
+ __IM uint32_t RESERVED46;
+ __IOM uint32_t CONN_2_DATA_LIST_SENT; /*!< 0x00014210 data list sent update and status for connection 2 */
+ __IOM uint32_t CONN_2_DATA_LIST_ACK; /*!< 0x00014214 data list ack update and status for connection 2 */
+ __IOM uint32_t CONN_2_CE_DATA_LIST_CFG; /*!< 0x00014218 Connection specific pause resume for connection 2 */
+ __IM uint32_t RESERVED47;
+ __IOM uint32_t CONN_3_DATA_LIST_SENT; /*!< 0x00014220 data list sent update and status for connection 3 */
+ __IOM uint32_t CONN_3_DATA_LIST_ACK; /*!< 0x00014224 data list ack update and status for connection 3 */
+ __IOM uint32_t CONN_3_CE_DATA_LIST_CFG; /*!< 0x00014228 Connection specific pause resume for connection 3 */
+ __IM uint32_t RESERVED48;
+ __IOM uint32_t CONN_4_DATA_LIST_SENT; /*!< 0x00014230 data list sent update and status for connection 4 */
+ __IOM uint32_t CONN_4_DATA_LIST_ACK; /*!< 0x00014234 data list ack update and status for connection 4 */
+ __IOM uint32_t CONN_4_CE_DATA_LIST_CFG; /*!< 0x00014238 Connection specific pause resume for connection 4 */
+ __IM uint32_t RESERVED49[113];
+ __IOM uint32_t MMMS_ADVCH_NI_ENABLE; /*!< 0x00014400 Enable bits for ADV_NI, SCAN_NI and INIT_NI */
+ __IOM uint32_t MMMS_ADVCH_NI_VALID; /*!< 0x00014404 Next instant valid for ADV, SCAN, INIT */
+ __IOM uint32_t MMMS_ADVCH_NI_ABORT; /*!< 0x00014408 Abort the next instant of ADV, SCAN, INIT */
+ __IM uint32_t RESERVED50;
+ __IOM uint32_t CONN_PARAM_NEXT_SUP_TO; /*!< 0x00014410 Register to configure the supervision timeout for next
+ scheduled connection */
+ __IOM uint32_t CONN_PARAM_ACC_WIN_WIDEN; /*!< 0x00014414 Register to configure Accumulated window widening for next
+ scheduled connection */
+ __IM uint32_t RESERVED51[2];
+ __IOM uint32_t HW_LOAD_OFFSET; /*!< 0x00014420 Register to configure offset from connection anchor point at
+ which connection parameter memory should be read */
+ __IM uint32_t ADV_RAND; /*!< 0x00014424 Random number generated by Hardware for ADV NI calculation */
+ __IM uint32_t MMMS_RX_PKT_CNTR; /*!< 0x00014428 Packet Counter of packets in RX FIFO in MMMS mode */
+ __IM uint32_t RESERVED52;
+ __IM uint32_t CONN_RX_PKT_CNTR[8]; /*!< 0x00014430 Packet Counter for Individual connection index */
+ __IM uint32_t RESERVED53[236];
+ __IOM uint32_t WHITELIST_BASE_ADDR; /*!< 0x00014800 Whitelist base address */
+ __IM uint32_t RESERVED54[47];
+ __IOM uint32_t RSLV_LIST_PEER_IDNTT_BASE_ADDR; /*!< 0x000148C0 Resolving list base address for storing Peer Identity address */
+ __IM uint32_t RESERVED55[47];
+ __IOM uint32_t RSLV_LIST_PEER_RPA_BASE_ADDR; /*!< 0x00014980 Resolving list base address for storing resolved Peer RPA
+ address */
+ __IM uint32_t RESERVED56[47];
+ __IOM uint32_t RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR; /*!< 0x00014A40 Resolving list base address for storing Resolved received INITA
+ RPA */
+ __IM uint32_t RESERVED57[47];
+ __IOM uint32_t RSLV_LIST_TX_INIT_RPA_BASE_ADDR; /*!< 0x00014B00 Resolving list base address for storing generated TX INITA RPA */
+ __IM uint32_t RESERVED58[9535];
+} BLE_BLELL_Type; /*!< Size = 122880 (0x1E000) */
+
+/**
+ * \brief Bluetooth Low Energy Subsystem Miscellaneous (BLE_BLESS)
+ */
+typedef struct {
+ __IM uint32_t RESERVED[24];
+ __IOM uint32_t DDFT_CONFIG; /*!< 0x00000060 BLESS DDFT configuration register */
+ __IOM uint32_t XTAL_CLK_DIV_CONFIG; /*!< 0x00000064 Crystal clock divider configuration register */
+ __IOM uint32_t INTR_STAT; /*!< 0x00000068 Link Layer interrupt status register */
+ __IOM uint32_t INTR_MASK; /*!< 0x0000006C Link Layer interrupt mask register */
+ __IOM uint32_t LL_CLK_EN; /*!< 0x00000070 Link Layer primary clock enable */
+ __IOM uint32_t LF_CLK_CTRL; /*!< 0x00000074 BLESS LF clock control and BLESS revision ID indicator */
+ __IOM uint32_t EXT_PA_LNA_CTRL; /*!< 0x00000078 External TX PA and RX LNA control */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t LL_PKT_RSSI_CH_ENERGY; /*!< 0x00000080 Link Layer Last Received packet RSSI/Channel energy and channel
+ number */
+ __IM uint32_t BT_CLOCK_CAPT; /*!< 0x00000084 BT clock captured on an LL DSM exit */
+ __IM uint32_t RESERVED2[6];
+ __IOM uint32_t MT_CFG; /*!< 0x000000A0 MT Configuration Register */
+ __IOM uint32_t MT_DELAY_CFG; /*!< 0x000000A4 MT Delay configuration for state transitions */
+ __IOM uint32_t MT_DELAY_CFG2; /*!< 0x000000A8 MT Delay configuration for state transitions */
+ __IOM uint32_t MT_DELAY_CFG3; /*!< 0x000000AC MT Delay configuration for state transitions */
+ __IOM uint32_t MT_VIO_CTRL; /*!< 0x000000B0 MT Configuration Register to control VIO switches */
+ __IM uint32_t MT_STATUS; /*!< 0x000000B4 MT Status Register */
+ __IM uint32_t PWR_CTRL_SM_ST; /*!< 0x000000B8 Link Layer Power Control FSM Status Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t HVLDO_CTRL; /*!< 0x000000C0 HVLDO Configuration register */
+ __IOM uint32_t MISC_EN_CTRL; /*!< 0x000000C4 Radio Buck and Active regulator enable control */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t EFUSE_CONFIG; /*!< 0x000000D0 EFUSE mode configuration register */
+ __IOM uint32_t EFUSE_TIM_CTRL1; /*!< 0x000000D4 EFUSE timing control register (common for Program and Read
+ modes) */
+ __IOM uint32_t EFUSE_TIM_CTRL2; /*!< 0x000000D8 EFUSE timing control Register (for Read) */
+ __IOM uint32_t EFUSE_TIM_CTRL3; /*!< 0x000000DC EFUSE timing control Register (for Program) */
+ __IM uint32_t EFUSE_RDATA_L; /*!< 0x000000E0 EFUSE Lower read data */
+ __IM uint32_t EFUSE_RDATA_H; /*!< 0x000000E4 EFUSE higher read data */
+ __IOM uint32_t EFUSE_WDATA_L; /*!< 0x000000E8 EFUSE lower write word */
+ __IOM uint32_t EFUSE_WDATA_H; /*!< 0x000000EC EFUSE higher write word */
+ __IOM uint32_t DIV_BY_625_CFG; /*!< 0x000000F0 Divide by 625 for FW Use */
+ __IM uint32_t DIV_BY_625_STS; /*!< 0x000000F4 Output of divide by 625 divider */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t PACKET_COUNTER0; /*!< 0x00000100 Packet counter 0 */
+ __IOM uint32_t PACKET_COUNTER2; /*!< 0x00000104 Packet counter 2 */
+ __IOM uint32_t IV_MASTER0; /*!< 0x00000108 Master Initialization Vector 0 */
+ __IOM uint32_t IV_SLAVE0; /*!< 0x0000010C Slave Initialization Vector 0 */
+ __OM uint32_t ENC_KEY[4]; /*!< 0x00000110 Encryption Key register 0-3 */
+ __IOM uint32_t MIC_IN0; /*!< 0x00000120 MIC input register */
+ __IM uint32_t MIC_OUT0; /*!< 0x00000124 MIC output register */
+ __IOM uint32_t ENC_PARAMS; /*!< 0x00000128 Encryption Parameter register */
+ __IOM uint32_t ENC_CONFIG; /*!< 0x0000012C Encryption Configuration */
+ __IOM uint32_t ENC_INTR_EN; /*!< 0x00000130 Encryption Interrupt enable */
+ __IOM uint32_t ENC_INTR; /*!< 0x00000134 Encryption Interrupt status and clear register */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t B1_DATA_REG[4]; /*!< 0x00000140 Programmable B1 Data register (0-3) */
+ __IOM uint32_t ENC_MEM_BASE_ADDR; /*!< 0x00000150 Encryption memory base address */
+ __IM uint32_t RESERVED7[875];
+ __IOM uint32_t TRIM_LDO_0; /*!< 0x00000F00 LDO Trim register 0 */
+ __IOM uint32_t TRIM_LDO_1; /*!< 0x00000F04 LDO Trim register 1 */
+ __IOM uint32_t TRIM_LDO_2; /*!< 0x00000F08 LDO Trim register 2 */
+ __IOM uint32_t TRIM_LDO_3; /*!< 0x00000F0C LDO Trim register 3 */
+ __IOM uint32_t TRIM_MXD[4]; /*!< 0x00000F10 MXD die Trim registers */
+ __IM uint32_t RESERVED8[4];
+ __IOM uint32_t TRIM_LDO_4; /*!< 0x00000F30 LDO Trim register 4 */
+ __IOM uint32_t TRIM_LDO_5; /*!< 0x00000F34 LDO Trim register 5 */
+ __IM uint32_t RESERVED9[50];
+} BLE_BLESS_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Bluetooth Low Energy Subsystem (BLE)
+ */
+typedef struct {
+ BLE_RCB_Type RCB; /*!< 0x00000000 Radio Control Bus (RCB) controller */
+ __IM uint32_t RESERVED[896];
+ BLE_BLELL_Type BLELL; /*!< 0x00001000 Bluetooth Low Energy Link Layer */
+ BLE_BLESS_Type BLESS; /*!< 0x0001F000 Bluetooth Low Energy Subsystem Miscellaneous */
+} BLE_Type; /*!< Size = 131072 (0x20000) */
+
+
+/* BLE_RCB_RCBLL.CTRL */
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Pos 0UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk 0x1UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Pos 1UL
+#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Msk 0x2UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Pos 2UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Msk 0x4UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Pos 3UL
+#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Msk 0x8UL
+#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Pos 4UL
+#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Msk 0x10UL
+#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Pos 5UL
+#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Msk 0x20UL
+/* BLE_RCB_RCBLL.INTR */
+#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_SET */
+#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_MASK */
+#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.INTR_MASKED */
+#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Pos 0UL
+#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Msk 0x1UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Pos 2UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Msk 0x4UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Pos 3UL
+#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Msk 0x8UL
+/* BLE_RCB_RCBLL.RADIO_REG1_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG2_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG3_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG4_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.RADIO_REG5_ADDR */
+#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Msk 0xFFFFUL
+/* BLE_RCB_RCBLL.CPU_WRITE_REG */
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Msk 0xFFFFUL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Pos 16UL
+#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Msk 0xFFFF0000UL
+/* BLE_RCB_RCBLL.CPU_READ_REG */
+#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Pos 0UL
+#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Msk 0xFFFFUL
+#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Pos 16UL
+#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Msk 0xFFFF0000UL
+
+
+/* BLE_RCB.CTRL */
+#define BLE_RCB_CTRL_TX_CLK_EDGE_Pos 1UL
+#define BLE_RCB_CTRL_TX_CLK_EDGE_Msk 0x2UL
+#define BLE_RCB_CTRL_RX_CLK_EDGE_Pos 2UL
+#define BLE_RCB_CTRL_RX_CLK_EDGE_Msk 0x4UL
+#define BLE_RCB_CTRL_RX_CLK_SRC_Pos 3UL
+#define BLE_RCB_CTRL_RX_CLK_SRC_Msk 0x8UL
+#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Pos 4UL
+#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Msk 0x10UL
+#define BLE_RCB_CTRL_SSEL_POLARITY_Pos 5UL
+#define BLE_RCB_CTRL_SSEL_POLARITY_Msk 0x20UL
+#define BLE_RCB_CTRL_LEAD_Pos 8UL
+#define BLE_RCB_CTRL_LEAD_Msk 0x300UL
+#define BLE_RCB_CTRL_LAG_Pos 10UL
+#define BLE_RCB_CTRL_LAG_Msk 0xC00UL
+#define BLE_RCB_CTRL_DIV_ENABLED_Pos 12UL
+#define BLE_RCB_CTRL_DIV_ENABLED_Msk 0x1000UL
+#define BLE_RCB_CTRL_DIV_Pos 13UL
+#define BLE_RCB_CTRL_DIV_Msk 0x7E000UL
+#define BLE_RCB_CTRL_ADDR_WIDTH_Pos 19UL
+#define BLE_RCB_CTRL_ADDR_WIDTH_Msk 0x780000UL
+#define BLE_RCB_CTRL_DATA_WIDTH_Pos 23UL
+#define BLE_RCB_CTRL_DATA_WIDTH_Msk 0x800000UL
+#define BLE_RCB_CTRL_ENABLED_Pos 31UL
+#define BLE_RCB_CTRL_ENABLED_Msk 0x80000000UL
+/* BLE_RCB.STATUS */
+#define BLE_RCB_STATUS_BUS_BUSY_Pos 0UL
+#define BLE_RCB_STATUS_BUS_BUSY_Msk 0x1UL
+/* BLE_RCB.TX_CTRL */
+#define BLE_RCB_TX_CTRL_MSB_FIRST_Pos 0UL
+#define BLE_RCB_TX_CTRL_MSB_FIRST_Msk 0x1UL
+#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Pos 1UL
+#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Msk 0x2UL
+#define BLE_RCB_TX_CTRL_TX_ENTRIES_Pos 2UL
+#define BLE_RCB_TX_CTRL_TX_ENTRIES_Msk 0x7CUL
+/* BLE_RCB.TX_FIFO_CTRL */
+#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Pos 0UL
+#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Msk 0x1FUL
+#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Pos 16UL
+#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+/* BLE_RCB.TX_FIFO_STATUS */
+#define BLE_RCB_TX_FIFO_STATUS_USED_Pos 0UL
+#define BLE_RCB_TX_FIFO_STATUS_USED_Msk 0x1FUL
+#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Msk 0xF0000UL
+#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Msk 0xF000000UL
+/* BLE_RCB.TX_FIFO_WR */
+#define BLE_RCB_TX_FIFO_WR_DATA_Pos 0UL
+#define BLE_RCB_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.RX_CTRL */
+#define BLE_RCB_RX_CTRL_MSB_FIRST_Pos 0UL
+#define BLE_RCB_RX_CTRL_MSB_FIRST_Msk 0x1UL
+/* BLE_RCB.RX_FIFO_CTRL */
+#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFUL
+#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Pos 16UL
+#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+/* BLE_RCB.RX_FIFO_STATUS */
+#define BLE_RCB_RX_FIFO_STATUS_USED_Pos 0UL
+#define BLE_RCB_RX_FIFO_STATUS_USED_Msk 0x1FUL
+#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Msk 0xF0000UL
+#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Msk 0xF000000UL
+/* BLE_RCB.RX_FIFO_RD */
+#define BLE_RCB_RX_FIFO_RD_DATA_Pos 0UL
+#define BLE_RCB_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.RX_FIFO_RD_SILENT */
+#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* BLE_RCB.INTR */
+#define BLE_RCB_INTR_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_SET */
+#define BLE_RCB_INTR_SET_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_SET_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_MASK */
+#define BLE_RCB_INTR_MASK_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_MASK_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+/* BLE_RCB.INTR_MASKED */
+#define BLE_RCB_INTR_MASKED_RCB_DONE_Pos 0UL
+#define BLE_RCB_INTR_MASKED_RCB_DONE_Msk 0x1UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Pos 8UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Msk 0x100UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Pos 9UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Msk 0x200UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Pos 10UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Msk 0x400UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Pos 11UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Msk 0x800UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Pos 12UL
+#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Msk 0x1000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Pos 16UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Msk 0x10000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Pos 17UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Pos 18UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Msk 0x40000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Pos 19UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Msk 0x80000UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Pos 20UL
+#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Msk 0x100000UL
+
+
+/* BLE_BLELL.COMMAND_REGISTER */
+#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Pos 0UL
+#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Msk 0xFFUL
+/* BLE_BLELL.EVENT_INTR */
+#define BLE_BLELL_EVENT_INTR_ADV_INTR_Pos 0UL
+#define BLE_BLELL_EVENT_INTR_ADV_INTR_Msk 0x1UL
+#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Pos 1UL
+#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Msk 0x2UL
+#define BLE_BLELL_EVENT_INTR_INIT_INTR_Pos 2UL
+#define BLE_BLELL_EVENT_INTR_INIT_INTR_Msk 0x4UL
+#define BLE_BLELL_EVENT_INTR_CONN_INTR_Pos 3UL
+#define BLE_BLELL_EVENT_INTR_CONN_INTR_Msk 0x8UL
+#define BLE_BLELL_EVENT_INTR_SM_INTR_Pos 4UL
+#define BLE_BLELL_EVENT_INTR_SM_INTR_Msk 0x10UL
+#define BLE_BLELL_EVENT_INTR_DSM_INTR_Pos 5UL
+#define BLE_BLELL_EVENT_INTR_DSM_INTR_Msk 0x20UL
+#define BLE_BLELL_EVENT_INTR_ENC_INTR_Pos 6UL
+#define BLE_BLELL_EVENT_INTR_ENC_INTR_Msk 0x40UL
+#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Pos 7UL
+#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Msk 0x80UL
+/* BLE_BLELL.EVENT_ENABLE */
+#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Pos 0UL
+#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Msk 0x1UL
+#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Pos 1UL
+#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Msk 0x2UL
+#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Pos 2UL
+#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Msk 0x4UL
+#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Pos 3UL
+#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Msk 0x8UL
+#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Pos 4UL
+#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Msk 0x10UL
+#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Pos 5UL
+#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Msk 0x20UL
+#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Pos 6UL
+#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Msk 0x40UL
+#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Pos 7UL
+#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Msk 0x80UL
+/* BLE_BLELL.ADV_PARAMS */
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Pos 0UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Pos 1UL
+#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Msk 0x6UL
+#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Msk 0x18UL
+#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Pos 5UL
+#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Msk 0xE0UL
+#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Pos 8UL
+#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Msk 0x100UL
+#define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Pos 9UL
+#define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Msk 0x200UL
+#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Pos 10UL
+#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Msk 0x400UL
+#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Pos 11UL
+#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Msk 0x800UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Pos 12UL
+#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Msk 0x1000UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Pos 13UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Msk 0x2000UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 14UL
+#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x4000UL
+#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Pos 15UL
+#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Msk 0x8000UL
+/* BLE_BLELL.ADV_INTERVAL_TIMEOUT */
+#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Pos 0UL
+#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Msk 0x7FFFUL
+/* BLE_BLELL.ADV_INTR */
+#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Pos 0UL
+#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Msk 0x1UL
+#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Pos 1UL
+#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Msk 0x2UL
+#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Pos 2UL
+#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Msk 0x4UL
+#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Pos 3UL
+#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Msk 0x8UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Pos 4UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Msk 0x10UL
+#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Pos 5UL
+#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Msk 0x20UL
+#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Pos 6UL
+#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Msk 0x40UL
+#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Pos 7UL
+#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Msk 0x80UL
+#define BLE_BLELL_ADV_INTR_ADV_ON_Pos 8UL
+#define BLE_BLELL_ADV_INTR_ADV_ON_Msk 0x100UL
+#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Pos 9UL
+#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Msk 0x200UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Pos 10UL
+#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Msk 0x400UL
+#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 11UL
+#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x800UL
+#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 12UL
+#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x1000UL
+/* BLE_BLELL.ADV_NEXT_INSTANT */
+#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Pos 0UL
+#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_INTERVAL */
+#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Pos 0UL
+#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_WINDOW */
+#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Pos 0UL
+#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Msk 0xFFFFUL
+/* BLE_BLELL.SCAN_PARAM */
+#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Pos 0UL
+#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Pos 1UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Msk 0x6UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Msk 0x18UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Pos 5UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Msk 0x20UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Pos 6UL
+#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Msk 0x40UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Pos 7UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Msk 0x80UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Pos 8UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Msk 0x100UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 9UL
+#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x200UL
+/* BLE_BLELL.SCAN_INTR */
+#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Pos 0UL
+#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Msk 0x1UL
+#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Pos 1UL
+#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Msk 0x2UL
+#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Pos 2UL
+#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Msk 0x4UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Pos 3UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Msk 0x8UL
+#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Pos 4UL
+#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Msk 0x10UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Pos 5UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Msk 0x20UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Pos 6UL
+#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Msk 0x40UL
+#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Pos 7UL
+#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
+#define BLE_BLELL_SCAN_INTR_SCAN_ON_Pos 8UL
+#define BLE_BLELL_SCAN_INTR_SCAN_ON_Msk 0x100UL
+#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
+#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
+#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 10UL
+#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x400UL
+/* BLE_BLELL.SCAN_NEXT_INSTANT */
+#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Pos 0UL
+#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_INTERVAL */
+#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Pos 0UL
+#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW */
+#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_PARAM */
+#define BLE_BLELL_INIT_PARAM_TX_ADDR_Pos 0UL
+#define BLE_BLELL_INIT_PARAM_TX_ADDR_Msk 0x1UL
+#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Pos 1UL
+#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Msk 0x2UL
+#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Pos 3UL
+#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Msk 0x8UL
+#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Pos 4UL
+#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Msk 0x10UL
+/* BLE_BLELL.INIT_INTR */
+#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Pos 0UL
+#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Msk 0x1UL
+#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Pos 1UL
+#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Msk 0x2UL
+#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Pos 2UL
+#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Msk 0x4UL
+#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Pos 4UL
+#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Msk 0x10UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Pos 5UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Msk 0x20UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Pos 6UL
+#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Msk 0x40UL
+#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Pos 7UL
+#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
+#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 8UL
+#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x100UL
+#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
+#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
+/* BLE_BLELL.INIT_NEXT_INSTANT */
+#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Pos 0UL
+#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_L */
+#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_M */
+#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEVICE_RAND_ADDR_H */
+#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_L */
+#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_M */
+#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_H */
+#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.WL_ADDR_TYPE */
+#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Pos 0UL
+#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Msk 0xFFFFUL
+/* BLE_BLELL.WL_ENABLE */
+#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Pos 0UL
+#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Msk 0xFFFFUL
+/* BLE_BLELL.TRANSMIT_WINDOW_OFFSET */
+#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Pos 0UL
+#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.TRANSMIT_WINDOW_SIZE */
+#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Pos 0UL
+#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Msk 0xFFUL
+/* BLE_BLELL.DATA_CHANNELS_L0 */
+#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_M0 */
+#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_H0 */
+#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Msk 0x1FUL
+/* BLE_BLELL.DATA_CHANNELS_L1 */
+#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_M1 */
+#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_CHANNELS_H1 */
+#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Pos 0UL
+#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Msk 0x1FUL
+/* BLE_BLELL.CONN_INTR */
+#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Pos 0UL
+#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Msk 0x1UL
+#define BLE_BLELL_CONN_INTR_CONN_ESTB_Pos 1UL
+#define BLE_BLELL_CONN_INTR_CONN_ESTB_Msk 0x2UL
+#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Pos 2UL
+#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Msk 0x4UL
+#define BLE_BLELL_CONN_INTR_START_CE_Pos 3UL
+#define BLE_BLELL_CONN_INTR_START_CE_Msk 0x8UL
+#define BLE_BLELL_CONN_INTR_CLOSE_CE_Pos 4UL
+#define BLE_BLELL_CONN_INTR_CLOSE_CE_Msk 0x10UL
+#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Pos 5UL
+#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Msk 0x20UL
+#define BLE_BLELL_CONN_INTR_CE_RX_Pos 6UL
+#define BLE_BLELL_CONN_INTR_CE_RX_Msk 0x40UL
+#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Pos 7UL
+#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Msk 0x80UL
+#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Pos 8UL
+#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Msk 0x700UL
+#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Pos 11UL
+#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Msk 0x3800UL
+#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Pos 14UL
+#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
+#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Pos 15UL
+#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
+/* BLE_BLELL.CONN_STATUS */
+#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Pos 12UL
+#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Msk 0xF000UL
+/* BLE_BLELL.CONN_INDEX */
+#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Msk 0xFFFFUL
+/* BLE_BLELL.WAKEUP_CONFIG */
+#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Msk 0xFFUL
+#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Pos 10UL
+#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Msk 0xFC00UL
+/* BLE_BLELL.WAKEUP_CONTROL */
+#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CLOCK_CONFIG */
+#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Pos 0UL
+#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Msk 0x1UL
+#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Pos 1UL
+#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Msk 0x2UL
+#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Pos 2UL
+#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Msk 0x4UL
+#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Pos 3UL
+#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Msk 0x8UL
+#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Pos 4UL
+#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Msk 0x10UL
+#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Pos 5UL
+#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Msk 0x20UL
+#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Pos 6UL
+#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Msk 0x40UL
+#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Pos 7UL
+#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Msk 0x80UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Pos 8UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Msk 0x100UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Pos 9UL
+#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Msk 0x200UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Pos 10UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Msk 0x400UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Pos 12UL
+#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Msk 0x1000UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Pos 13UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Msk 0x2000UL
+#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Pos 14UL
+#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Msk 0x4000UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Pos 15UL
+#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Msk 0x8000UL
+/* BLE_BLELL.TIM_COUNTER_L */
+#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Pos 0UL
+#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Msk 0xFFFFUL
+/* BLE_BLELL.WAKEUP_CONFIG_EXTD */
+#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Pos 0UL
+#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Msk 0x1FUL
+/* BLE_BLELL.POC_REG__TIM_CONTROL */
+#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Pos 3UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Msk 0xF8UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Pos 8UL
+#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Msk 0xF00UL
+/* BLE_BLELL.ADV_TX_DATA_FIFO */
+#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Pos 0UL
+#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_SCN_RSP_TX_FIFO */
+#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Pos 0UL
+#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_SCN_ADV_RX_FIFO */
+#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Pos 0UL
+#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_INTERVAL */
+#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Pos 0UL
+#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.SUP_TIMEOUT */
+#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Pos 0UL
+#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Msk 0xFFFFUL
+/* BLE_BLELL.SLAVE_LATENCY */
+#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Pos 0UL
+#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Msk 0xFFFFUL
+/* BLE_BLELL.CE_LENGTH */
+#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Pos 0UL
+#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Msk 0xFFFFUL
+/* BLE_BLELL.PDU_ACCESS_ADDR_L_REGISTER */
+#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Pos 0UL
+#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Msk 0xFFFFUL
+/* BLE_BLELL.PDU_ACCESS_ADDR_H_REGISTER */
+#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Pos 0UL
+#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CE_INSTANT */
+#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Pos 0UL
+#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CE_CNFG_STS_REGISTER */
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Pos 0UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Msk 0xFUL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Pos 4UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Msk 0x10UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Pos 5UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Msk 0x20UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Pos 6UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Msk 0x40UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Pos 7UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Msk 0x80UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Pos 8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Msk 0x100UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Pos 10UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Msk 0x400UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Pos 12UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Msk 0xF000UL
+/* BLE_BLELL.NEXT_CE_INSTANT */
+#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CE_COUNTER */
+#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Pos 0UL
+#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Msk 0xFFFFUL
+/* BLE_BLELL.DATA_LIST_SENT_UPDATE__STATUS */
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Pos 0UL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Msk 0xFUL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Pos 7UL
+#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
+/* BLE_BLELL.DATA_LIST_ACK_UPDATE__STATUS */
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Pos 0UL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Msk 0xFUL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Pos 7UL
+#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
+/* BLE_BLELL.CE_CNFG_STS_REGISTER_EXT */
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Pos 0UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Msk 0x1UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Pos 1UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Msk 0x2UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Pos 2UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Msk 0x4UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Pos 3UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Msk 0x8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Pos 8UL
+#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
+/* BLE_BLELL.CONN_EXT_INTR */
+#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Pos 0UL
+#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Msk 0x1UL
+#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Pos 1UL
+#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Msk 0x2UL
+#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Pos 2UL
+#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Msk 0x4UL
+/* BLE_BLELL.CONN_EXT_INTR_MASK */
+#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Pos 0UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Msk 0x1UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Pos 1UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Msk 0x2UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Pos 2UL
+#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Msk 0x4UL
+/* BLE_BLELL.DATA_MEM_DESCRIPTOR */
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Pos 0UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Msk 0x3UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Pos 2UL
+#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Msk 0x3FCUL
+/* BLE_BLELL.WINDOW_WIDEN_INTVL */
+#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Pos 0UL
+#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Msk 0xFFFUL
+/* BLE_BLELL.WINDOW_WIDEN_WINOFF */
+#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Pos 0UL
+#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Msk 0xFFFUL
+/* BLE_BLELL.LE_RF_TEST_MODE */
+#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Pos 0UL
+#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Msk 0x3FUL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Pos 6UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Msk 0x40UL
+#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Pos 7UL
+#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Msk 0x380UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Pos 13UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Msk 0x2000UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Pos 15UL
+#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Msk 0x8000UL
+/* BLE_BLELL.DTM_RX_PKT_COUNT */
+#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Pos 0UL
+#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Msk 0xFFFFUL
+/* BLE_BLELL.LE_RF_TEST_MODE_EXT */
+#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Pos 0UL
+#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Msk 0xFFUL
+/* BLE_BLELL.TXRX_HOP */
+#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Pos 0UL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Msk 0x7FUL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Pos 8UL
+#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Msk 0x7F00UL
+/* BLE_BLELL.TX_RX_ON_DELAY */
+#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Pos 0UL
+#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Msk 0xFFUL
+#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Pos 8UL
+#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.ADV_ACCADDR_L */
+#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Pos 0UL
+#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_ACCADDR_H */
+#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Pos 0UL
+#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CH_TX_POWER_LVL_LS */
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Pos 0UL
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CH_TX_POWER_LVL_MS */
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Pos 0UL
+#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
+/* BLE_BLELL.CONN_CH_TX_POWER_LVL_LS */
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Pos 0UL
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_CH_TX_POWER_LVL_MS */
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Pos 0UL
+#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
+/* BLE_BLELL.DEV_PUB_ADDR_L */
+#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PUB_ADDR_M */
+#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PUB_ADDR_H */
+#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.OFFSET_TO_FIRST_INSTANT */
+#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Pos 0UL
+#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Msk 0xFFFFUL
+/* BLE_BLELL.ADV_CONFIG */
+#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Pos 0UL
+#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Pos 1UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Msk 0x2UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Pos 2UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Msk 0x4UL
+#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Pos 3UL
+#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Msk 0x8UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Pos 4UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Msk 0x10UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Pos 5UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Msk 0x20UL
+#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Pos 6UL
+#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Msk 0x40UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Pos 7UL
+#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Msk 0x80UL
+#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Pos 8UL
+#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Msk 0x100UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Pos 9UL
+#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Msk 0x200UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Pos 10UL
+#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Msk 0x400UL
+#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Pos 11UL
+#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Msk 0xF800UL
+/* BLE_BLELL.SCAN_CONFIG */
+#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Pos 0UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Pos 1UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Msk 0x2UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Pos 2UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Msk 0x4UL
+#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Pos 3UL
+#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Msk 0x8UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Pos 4UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Msk 0x10UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Pos 5UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Msk 0x20UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Pos 6UL
+#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Msk 0x40UL
+#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
+#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 8UL
+#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x100UL
+#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Pos 11UL
+#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Msk 0x800UL
+#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Pos 13UL
+#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Msk 0xE000UL
+/* BLE_BLELL.INIT_CONFIG */
+#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Pos 0UL
+#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Msk 0x1UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Pos 1UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Msk 0x2UL
+#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Pos 2UL
+#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Msk 0x4UL
+#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Pos 4UL
+#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Msk 0x10UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Pos 5UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Msk 0x20UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Pos 6UL
+#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Msk 0x40UL
+#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
+#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Pos 13UL
+#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Msk 0xE000UL
+/* BLE_BLELL.CONN_CONFIG */
+#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Pos 0UL
+#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Msk 0xFUL
+#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Pos 4UL
+#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Msk 0xF0UL
+#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Pos 8UL
+#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Msk 0x100UL
+#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Pos 11UL
+#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Msk 0x800UL
+#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Pos 12UL
+#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Msk 0x1000UL
+#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Pos 13UL
+#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Msk 0x2000UL
+#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Pos 14UL
+#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Msk 0x4000UL
+#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Pos 15UL
+#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Msk 0x8000UL
+/* BLE_BLELL.CONN_PARAM1 */
+#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Msk 0x7UL
+#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Pos 3UL
+#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Msk 0xF8UL
+#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Pos 8UL
+#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Msk 0xFF00UL
+/* BLE_BLELL.CONN_PARAM2 */
+#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Pos 0UL
+#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_INTR_MASK */
+#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Pos 0UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Msk 0x1UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Pos 1UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Msk 0x2UL
+#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Pos 2UL
+#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Msk 0x4UL
+#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Pos 3UL
+#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Msk 0x8UL
+#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Pos 4UL
+#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Msk 0x10UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Pos 5UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Msk 0x20UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Pos 6UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Msk 0x40UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Pos 7UL
+#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Msk 0x80UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Pos 8UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Msk 0x100UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Pos 9UL
+#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Msk 0x200UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Pos 13UL
+#define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Msk 0x2000UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Pos 14UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Pos 15UL
+#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
+/* BLE_BLELL.SLAVE_TIMING_CONTROL */
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Pos 0UL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Msk 0xFFUL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Pos 8UL
+#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Msk 0xFF00UL
+/* BLE_BLELL.RECEIVE_TRIG_CTRL */
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Pos 0UL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Msk 0x3FUL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Pos 8UL
+#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Msk 0xFF00UL
+/* BLE_BLELL.LL_DBG_1 */
+#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_2 */
+#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_3 */
+#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Pos 0UL
+#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Msk 0x3FFUL
+/* BLE_BLELL.LL_DBG_4 */
+#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Pos 0UL
+#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Msk 0xFUL
+#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Pos 4UL
+#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Msk 0x30UL
+#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Pos 6UL
+#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Msk 0x7C0UL
+/* BLE_BLELL.LL_DBG_5 */
+#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Pos 0UL
+#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Msk 0x1FUL
+#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Pos 5UL
+#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Msk 0x3E0UL
+/* BLE_BLELL.LL_DBG_6 */
+#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Msk 0xFUL
+#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Pos 4UL
+#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Msk 0xF0UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Pos 8UL
+#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Msk 0x3F00UL
+/* BLE_BLELL.LL_DBG_7 */
+#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Pos 0UL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Msk 0x7FUL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Pos 7UL
+#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Msk 0x3F80UL
+/* BLE_BLELL.LL_DBG_8 */
+#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Pos 0UL
+#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Msk 0x7FUL
+#define BLE_BLELL_LL_DBG_8_WLF_PTR_Pos 7UL
+#define BLE_BLELL_LL_DBG_8_WLF_PTR_Msk 0x3F80UL
+/* BLE_BLELL.LL_DBG_9 */
+#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Msk 0xFFFFUL
+/* BLE_BLELL.LL_DBG_10 */
+#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Pos 0UL
+#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Msk 0x3FUL
+/* BLE_BLELL.PEER_ADDR_INIT_L */
+#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_INIT_M */
+#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_ADDR_INIT_H */
+#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_L */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_M */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.PEER_SEC_ADDR_ADV_H */
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Pos 0UL
+#define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_TIMER_CTRL */
+#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Msk 0x1UL
+/* BLE_BLELL.CONN_CONFIG_EXT */
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Pos 0UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Msk 0x1UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Pos 1UL
+#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Msk 0x2UL
+#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Pos 2UL
+#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Msk 0x7CUL
+#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Pos 8UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Msk 0x3F00UL
+#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Pos 14UL
+#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Msk 0x4000UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Pos 15UL
+#define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Msk 0x8000UL
+/* BLE_BLELL.DPLL_CONFIG */
+#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Pos 0UL
+#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_NI_VAL */
+#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Pos 0UL
+#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_OFFSET */
+#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Msk 0xFFFFUL
+/* BLE_BLELL.INIT_WINDOW_NI_ANCHOR_PT */
+#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Pos 0UL
+#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_INTERVAL */
+#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_LATENCY */
+#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_SUP_TO */
+#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_UPDATE_NEW_SL_INTERVAL */
+#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD0 */
+#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD1 */
+#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD2 */
+#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Msk 0xFFUL
+#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Pos 8UL
+#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Msk 0xFF00UL
+/* BLE_BLELL.CONN_REQ_WORD3 */
+#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD4 */
+#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD5 */
+#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD6 */
+#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD7 */
+#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD8 */
+#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD9 */
+#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_REQ_WORD10 */
+#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Msk 0x1FUL
+/* BLE_BLELL.CONN_REQ_WORD11 */
+#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Pos 0UL
+#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Msk 0x1FUL
+#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Pos 5UL
+#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Msk 0xE0UL
+/* BLE_BLELL.PDU_RESP_TIMER */
+#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Pos 0UL
+#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_RESP_TIMER_EXP */
+#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_SUP_TO */
+#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Pos 0UL
+#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Msk 0xFFFFUL
+/* BLE_BLELL.LLH_FEATURE_CONFIG */
+#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Pos 0UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Msk 0x1UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Pos 1UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Msk 0x2UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Pos 2UL
+#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Msk 0x4UL
+/* BLE_BLELL.WIN_MIN_STEP_SIZE */
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Pos 0UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Msk 0xFUL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Pos 4UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Msk 0xF0UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Pos 8UL
+#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Msk 0xFF00UL
+/* BLE_BLELL.SLV_WIN_ADJ */
+#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Pos 0UL
+#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Msk 0x7FFUL
+/* BLE_BLELL.SL_CONN_INTERVAL */
+#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
+#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_ADDR */
+#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_OFFSET */
+#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_NEXT_EXP */
+#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Msk 0xFFFFUL
+/* BLE_BLELL.LE_PING_TIMER_WRAP_COUNT */
+#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Pos 0UL
+#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Msk 0xFFFFUL
+/* BLE_BLELL.TX_EN_EXT_DELAY */
+#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Pos 0UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Msk 0xFUL
+#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Pos 4UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Msk 0xF0UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Pos 8UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Msk 0xF00UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Pos 12UL
+#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Msk 0xF000UL
+/* BLE_BLELL.TX_RX_SYNTH_DELAY */
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Pos 0UL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Msk 0xFFUL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Pos 8UL
+#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.EXT_PA_LNA_DLY_CNFG */
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Pos 0UL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Msk 0xFFUL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Pos 8UL
+#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Msk 0xFF00UL
+/* BLE_BLELL.LL_CONFIG */
+#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Pos 0UL
+#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Msk 0x1UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Pos 1UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Msk 0x2UL
+#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Pos 2UL
+#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Msk 0x4UL
+#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Pos 3UL
+#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Msk 0x8UL
+#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Pos 5UL
+#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Msk 0x20UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Pos 6UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Msk 0x40UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Pos 7UL
+#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Msk 0x80UL
+#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Pos 8UL
+#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Msk 0x100UL
+#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Pos 9UL
+#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Msk 0x200UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Pos 10UL
+#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Msk 0x400UL
+#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Pos 11UL
+#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Msk 0x800UL
+#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Pos 12UL
+#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Msk 0x1000UL
+#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Pos 13UL
+#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Msk 0x2000UL
+#define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Pos 14UL
+#define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Msk 0x4000UL
+/* BLE_BLELL.LL_CONTROL */
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Pos 0UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Msk 0x1UL
+#define BLE_BLELL_LL_CONTROL_DLE_Pos 1UL
+#define BLE_BLELL_LL_CONTROL_DLE_Msk 0x2UL
+#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Pos 2UL
+#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Msk 0x4UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Pos 3UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Msk 0x8UL
+#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Pos 4UL
+#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Msk 0x10UL
+#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 5UL
+#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x20UL
+#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 6UL
+#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x40UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 7UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x80UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 8UL
+#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x100UL
+#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 9UL
+#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x200UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Pos 10UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Msk 0x400UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Pos 11UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Msk 0x800UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Pos 12UL
+#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Msk 0x1000UL
+#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Pos 13UL
+#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Msk 0x2000UL
+#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Pos 14UL
+#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Msk 0x4000UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Pos 15UL
+#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Msk 0x8000UL
+/* BLE_BLELL.DEV_PA_ADDR_L */
+#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PA_ADDR_M */
+#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Msk 0xFFFFUL
+/* BLE_BLELL.DEV_PA_ADDR_H */
+#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Pos 0UL
+#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_ENABLE */
+#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Msk 0x1UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Pos 1UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Msk 0x2UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Pos 2UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Msk 0x4UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Pos 3UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Msk 0x8UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Pos 4UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Msk 0x10UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Pos 5UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Msk 0x20UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Pos 6UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Msk 0x40UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Pos 7UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Msk 0x80UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Pos 8UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Msk 0x100UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Pos 9UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Msk 0x200UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Pos 10UL
+#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Msk 0x400UL
+/* BLE_BLELL.WL_CONNECTION_STATUS */
+#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Pos 0UL
+#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_RXMEM_BASE_ADDR_DLE */
+#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Pos 0UL
+#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
+/* BLE_BLELL.CONN_TXMEM_BASE_ADDR_DLE */
+#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Pos 0UL
+#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
+/* BLE_BLELL.CONN_1_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_2_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_3_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_4_PARAM_MEM_BASE_ADDR */
+#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Pos 0UL
+#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Msk 0xFFFFUL
+/* BLE_BLELL.NI_TIMER */
+#define BLE_BLELL_NI_TIMER_NI_TIMER_Pos 0UL
+#define BLE_BLELL_NI_TIMER_NI_TIMER_Msk 0xFFFFUL
+/* BLE_BLELL.US_OFFSET */
+#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Pos 0UL
+#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Msk 0x3FFUL
+/* BLE_BLELL.NEXT_CONN */
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Msk 0x1FUL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Pos 5UL
+#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Msk 0x20UL
+#define BLE_BLELL_NEXT_CONN_NI_VALID_Pos 6UL
+#define BLE_BLELL_NEXT_CONN_NI_VALID_Msk 0x40UL
+/* BLE_BLELL.NI_ABORT */
+#define BLE_BLELL_NI_ABORT_NI_ABORT_Pos 0UL
+#define BLE_BLELL_NI_ABORT_NI_ABORT_Msk 0x1UL
+#define BLE_BLELL_NI_ABORT_ABORT_ACK_Pos 1UL
+#define BLE_BLELL_NI_ABORT_ABORT_ACK_Msk 0x2UL
+/* BLE_BLELL.CONN_NI_STATUS */
+#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Pos 0UL
+#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Msk 0xFFFFUL
+/* BLE_BLELL.NEXT_SUP_TO_STATUS */
+#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Pos 0UL
+#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_CONN_STATUS */
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Pos 0UL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Msk 0x1FUL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Pos 5UL
+#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Msk 0x20UL
+#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Pos 6UL
+#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Msk 0x40UL
+#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Pos 7UL
+#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Msk 0x80UL
+#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Pos 8UL
+#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
+#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Pos 14UL
+#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Msk 0x4000UL
+#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Pos 15UL
+#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Msk 0x8000UL
+/* BLE_BLELL.BT_SLOT_CAPT_STATUS */
+#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Pos 0UL
+#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Msk 0xFFFFUL
+/* BLE_BLELL.US_CAPT_STATUS */
+#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Pos 0UL
+#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Msk 0x3FFUL
+/* BLE_BLELL.US_OFFSET_STATUS */
+#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Pos 0UL
+#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Msk 0xFFFFUL
+/* BLE_BLELL.ACCU_WINDOW_WIDEN_STATUS */
+#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Msk 0xFFFFUL
+/* BLE_BLELL.EARLY_INTR_STATUS */
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Pos 0UL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Msk 0x1FUL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Pos 5UL
+#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Msk 0x20UL
+#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Pos 6UL
+#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Msk 0xFFC0UL
+/* BLE_BLELL.MMMS_CONFIG */
+#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Pos 0UL
+#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Msk 0x1UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Pos 1UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Msk 0x2UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Pos 2UL
+#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Msk 0x4UL
+#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Pos 3UL
+#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Msk 0x8UL
+#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Pos 4UL
+#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Msk 0x1F0UL
+#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Pos 9UL
+#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Msk 0x200UL
+#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Pos 10UL
+#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Msk 0x400UL
+/* BLE_BLELL.US_COUNTER */
+#define BLE_BLELL_US_COUNTER_US_COUNTER_Pos 0UL
+#define BLE_BLELL_US_COUNTER_US_COUNTER_Msk 0x3FFUL
+/* BLE_BLELL.US_CAPT_PREV */
+#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Pos 0UL
+#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Msk 0x3FFUL
+/* BLE_BLELL.EARLY_INTR_NI */
+#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Pos 0UL
+#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_MASTER_CREATE_BT_CAPT */
+#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Pos 0UL
+#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_SLAVE_CREATE_BT_CAPT */
+#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Pos 0UL
+#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Msk 0x3FFUL
+/* BLE_BLELL.MMMS_SLAVE_CREATE_US_CAPT */
+#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Pos 0UL
+#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Msk 0xFFFFUL
+/* BLE_BLELL.MMMS_DATA_MEM_DESCRIPTOR */
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Pos 0UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Msk 0x3UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Pos 2UL
+#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Msk 0x3FCUL
+/* BLE_BLELL.CONN_1_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_1_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_1_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_2_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_2_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_2_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_3_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_3_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_3_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.CONN_4_DATA_LIST_SENT */
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
+#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
+/* BLE_BLELL.CONN_4_DATA_LIST_ACK */
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
+/* BLE_BLELL.CONN_4_CE_DATA_LIST_CFG */
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
+#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
+/* BLE_BLELL.MMMS_ADVCH_NI_ENABLE */
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Msk 0x2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Pos 2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Msk 0x4UL
+/* BLE_BLELL.MMMS_ADVCH_NI_VALID */
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Msk 0x2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Pos 2UL
+#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Msk 0x4UL
+/* BLE_BLELL.MMMS_ADVCH_NI_ABORT */
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Pos 0UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Msk 0x1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Pos 1UL
+#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Msk 0x2UL
+/* BLE_BLELL.CONN_PARAM_NEXT_SUP_TO */
+#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Pos 0UL
+#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Msk 0xFFFFUL
+/* BLE_BLELL.CONN_PARAM_ACC_WIN_WIDEN */
+#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Pos 0UL
+#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Msk 0x3FFUL
+/* BLE_BLELL.HW_LOAD_OFFSET */
+#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Pos 0UL
+#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Msk 0x1FUL
+/* BLE_BLELL.ADV_RAND */
+#define BLE_BLELL_ADV_RAND_ADV_RAND_Pos 0UL
+#define BLE_BLELL_ADV_RAND_ADV_RAND_Msk 0xFUL
+/* BLE_BLELL.MMMS_RX_PKT_CNTR */
+#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Pos 0UL
+#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Msk 0x3FUL
+/* BLE_BLELL.CONN_RX_PKT_CNTR */
+#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Pos 0UL
+#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Msk 0x3FUL
+/* BLE_BLELL.WHITELIST_BASE_ADDR */
+#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_PEER_IDNTT_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_PEER_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
+/* BLE_BLELL.RSLV_LIST_TX_INIT_RPA_BASE_ADDR */
+#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Pos 0UL
+#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
+
+
+/* BLE_BLESS.DDFT_CONFIG */
+#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Pos 0UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Msk 0x1UL
+#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Pos 1UL
+#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Msk 0x2UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Pos 8UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Msk 0x1F00UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Pos 16UL
+#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Msk 0x1F0000UL
+/* BLE_BLESS.XTAL_CLK_DIV_CONFIG */
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Pos 0UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk 0x3UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos 2UL
+#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Msk 0xCUL
+/* BLE_BLESS.INTR_STAT */
+#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Pos 0UL
+#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Msk 0x1UL
+#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Pos 1UL
+#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Msk 0x2UL
+#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Pos 2UL
+#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Msk 0x4UL
+#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Pos 3UL
+#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk 0x8UL
+#define BLE_BLESS_INTR_STAT_RCB_INTR_Pos 4UL
+#define BLE_BLESS_INTR_STAT_RCB_INTR_Msk 0x10UL
+#define BLE_BLESS_INTR_STAT_LL_INTR_Pos 5UL
+#define BLE_BLESS_INTR_STAT_LL_INTR_Msk 0x20UL
+#define BLE_BLESS_INTR_STAT_GPIO_INTR_Pos 6UL
+#define BLE_BLESS_INTR_STAT_GPIO_INTR_Msk 0x40UL
+#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Pos 7UL
+#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Msk 0x80UL
+#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Pos 8UL
+#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Msk 0x100UL
+#define BLE_BLESS_INTR_STAT_ENC_INTR_Pos 9UL
+#define BLE_BLESS_INTR_STAT_ENC_INTR_Msk 0x200UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Pos 10UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Msk 0x400UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Pos 11UL
+#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Msk 0x800UL
+/* BLE_BLESS.INTR_MASK */
+#define BLE_BLESS_INTR_MASK_DSM_EXIT_Pos 0UL
+#define BLE_BLESS_INTR_MASK_DSM_EXIT_Msk 0x1UL
+#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Pos 1UL
+#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Msk 0x2UL
+#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Pos 2UL
+#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Msk 0x4UL
+#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Pos 3UL
+#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Msk 0x8UL
+#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Pos 4UL
+#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Msk 0x10UL
+#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Pos 5UL
+#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Msk 0x20UL
+#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Pos 6UL
+#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Msk 0x40UL
+#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Pos 7UL
+#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Msk 0x80UL
+#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Pos 8UL
+#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Msk 0x100UL
+#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Pos 9UL
+#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Msk 0x200UL
+#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Pos 10UL
+#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Msk 0x400UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Pos 11UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Msk 0x800UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Pos 12UL
+#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Msk 0x1000UL
+/* BLE_BLESS.LL_CLK_EN */
+#define BLE_BLESS_LL_CLK_EN_CLK_EN_Pos 0UL
+#define BLE_BLESS_LL_CLK_EN_CLK_EN_Msk 0x1UL
+#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Pos 1UL
+#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Msk 0x2UL
+#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Pos 2UL
+#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Msk 0x4UL
+#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Pos 3UL
+#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk 0x8UL
+#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Pos 4UL
+#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk 0x10UL
+#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Pos 5UL
+#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Msk 0x20UL
+/* BLE_BLESS.LF_CLK_CTRL */
+#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Pos 0UL
+#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Msk 0x1UL
+#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Pos 1UL
+#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Msk 0x2UL
+#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Pos 29UL
+#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Msk 0xE0000000UL
+/* BLE_BLESS.EXT_PA_LNA_CTRL */
+#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Pos 1UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Msk 0x2UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Pos 2UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Msk 0x4UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Pos 3UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Msk 0x8UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Pos 4UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Msk 0x10UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Pos 5UL
+#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Msk 0x20UL
+/* BLE_BLESS.LL_PKT_RSSI_CH_ENERGY */
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Pos 0UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Msk 0xFFFFUL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Pos 16UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Msk 0x3F0000UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Pos 22UL
+#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Msk 0x400000UL
+/* BLE_BLESS.BT_CLOCK_CAPT */
+#define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Pos 0UL
+#define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Msk 0xFFFFUL
+/* BLE_BLESS.MT_CFG */
+#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Pos 0UL
+#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk 0x1UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Pos 1UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Msk 0x2UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Pos 2UL
+#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Msk 0x4UL
+#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Pos 3UL
+#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk 0x8UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Pos 4UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk 0x10UL
+#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Pos 5UL
+#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk 0x20UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Pos 6UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Msk 0x40UL
+#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Pos 7UL
+#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Msk 0x80UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Pos 8UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Msk 0x100UL
+#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Pos 9UL
+#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Msk 0x200UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Pos 10UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Msk 0x400UL
+#define BLE_BLESS_MT_CFG_RET_SWITCH_Pos 11UL
+#define BLE_BLESS_MT_CFG_RET_SWITCH_Msk 0x800UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Pos 12UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Msk 0x1000UL
+#define BLE_BLESS_MT_CFG_ISOLATE_N_Pos 13UL
+#define BLE_BLESS_MT_CFG_ISOLATE_N_Msk 0x2000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Pos 14UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Msk 0x4000UL
+#define BLE_BLESS_MT_CFG_LL_CLK_EN_Pos 15UL
+#define BLE_BLESS_MT_CFG_LL_CLK_EN_Msk 0x8000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Pos 16UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk 0x10000UL
+#define BLE_BLESS_MT_CFG_HVLDO_EN_Pos 17UL
+#define BLE_BLESS_MT_CFG_HVLDO_EN_Msk 0x20000UL
+#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Pos 18UL
+#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk 0x40000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Pos 19UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Msk 0x80000UL
+#define BLE_BLESS_MT_CFG_RESET_N_Pos 20UL
+#define BLE_BLESS_MT_CFG_RESET_N_Msk 0x100000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Pos 21UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Msk 0x200000UL
+#define BLE_BLESS_MT_CFG_XTAL_EN_Pos 22UL
+#define BLE_BLESS_MT_CFG_XTAL_EN_Msk 0x400000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Pos 23UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Msk 0x800000UL
+#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Pos 24UL
+#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Msk 0x1000000UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Pos 25UL
+#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Msk 0x2000000UL
+#define BLE_BLESS_MT_CFG_RET_LDO_OL_Pos 26UL
+#define BLE_BLESS_MT_CFG_RET_LDO_OL_Msk 0x4000000UL
+#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Pos 27UL
+#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Msk 0x8000000UL
+/* BLE_BLESS.MT_DELAY_CFG */
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Msk 0xFF0000UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos 24UL
+#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Msk 0xFF000000UL
+/* BLE_BLESS.MT_DELAY_CFG2 */
+#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Msk 0xFF0000UL
+#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos 24UL
+#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Msk 0xFF000000UL
+/* BLE_BLESS.MT_DELAY_CFG3 */
+#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos 0UL
+#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Msk 0xFFUL
+#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos 8UL
+#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Msk 0xFF00UL
+#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos 16UL
+#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Msk 0xFF0000UL
+/* BLE_BLESS.MT_VIO_CTRL */
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Pos 0UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk 0x1UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Pos 1UL
+#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk 0x2UL
+/* BLE_BLESS.MT_STATUS */
+#define BLE_BLESS_MT_STATUS_BLESS_STATE_Pos 0UL
+#define BLE_BLESS_MT_STATUS_BLESS_STATE_Msk 0x1UL
+#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Pos 1UL
+#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Msk 0x1EUL
+#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Pos 5UL
+#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Msk 0xE0UL
+#define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Pos 8UL
+#define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Msk 0x100UL
+/* BLE_BLESS.PWR_CTRL_SM_ST */
+#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Pos 0UL
+#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Msk 0xFUL
+/* BLE_BLESS.HVLDO_CTRL */
+#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Pos 0UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Msk 0x1UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Pos 1UL
+#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Msk 0x1EUL
+#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Pos 6UL
+#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Msk 0x40UL
+#define BLE_BLESS_HVLDO_CTRL_STATUS_Pos 31UL
+#define BLE_BLESS_HVLDO_CTRL_STATUS_Msk 0x80000000UL
+/* BLE_BLESS.MISC_EN_CTRL */
+#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Pos 0UL
+#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk 0x1UL
+#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Pos 1UL
+#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk 0x2UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Pos 2UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Msk 0x4UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Pos 3UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Msk 0x8UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Pos 4UL
+#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Msk 0x10UL
+/* BLE_BLESS.EFUSE_CONFIG */
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Pos 0UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Msk 0x1UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Pos 1UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Msk 0x2UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Pos 2UL
+#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Msk 0x4UL
+/* BLE_BLESS.EFUSE_TIM_CTRL1 */
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Msk 0xFFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Msk 0xFF00UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Pos 16UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Msk 0xF0000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Pos 20UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Msk 0xF00000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Pos 24UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Msk 0xF000000UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Pos 28UL
+#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Msk 0xF0000000UL
+/* BLE_BLESS.EFUSE_TIM_CTRL2 */
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Msk 0xFFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Msk 0xF00UL
+/* BLE_BLESS.EFUSE_TIM_CTRL3 */
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Pos 0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Msk 0xFUL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Pos 4UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Msk 0xF0UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Pos 8UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Msk 0xFF00UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Pos 16UL
+#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Msk 0xFF0000UL
+/* BLE_BLESS.EFUSE_RDATA_L */
+#define BLE_BLESS_EFUSE_RDATA_L_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_RDATA_L_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_RDATA_H */
+#define BLE_BLESS_EFUSE_RDATA_H_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_RDATA_H_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_WDATA_L */
+#define BLE_BLESS_EFUSE_WDATA_L_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_WDATA_L_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.EFUSE_WDATA_H */
+#define BLE_BLESS_EFUSE_WDATA_H_DATA_Pos 0UL
+#define BLE_BLESS_EFUSE_WDATA_H_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.DIV_BY_625_CFG */
+#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Pos 1UL
+#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Msk 0x2UL
+#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Pos 8UL
+#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Msk 0xFFFF00UL
+/* BLE_BLESS.DIV_BY_625_STS */
+#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Pos 0UL
+#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Msk 0x3FUL
+#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Pos 8UL
+#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Msk 0x3FF00UL
+/* BLE_BLESS.PACKET_COUNTER0 */
+#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Pos 0UL
+#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.PACKET_COUNTER2 */
+#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Pos 0UL
+#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Msk 0xFFUL
+/* BLE_BLESS.IV_MASTER0 */
+#define BLE_BLESS_IV_MASTER0_IV_MASTER_Pos 0UL
+#define BLE_BLESS_IV_MASTER0_IV_MASTER_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.IV_SLAVE0 */
+#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Pos 0UL
+#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_KEY */
+#define BLE_BLESS_ENC_KEY_ENC_KEY_Pos 0UL
+#define BLE_BLESS_ENC_KEY_ENC_KEY_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.MIC_IN0 */
+#define BLE_BLESS_MIC_IN0_MIC_IN_Pos 0UL
+#define BLE_BLESS_MIC_IN0_MIC_IN_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.MIC_OUT0 */
+#define BLE_BLESS_MIC_OUT0_MIC_OUT_Pos 0UL
+#define BLE_BLESS_MIC_OUT0_MIC_OUT_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_PARAMS */
+#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Pos 0UL
+#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Msk 0x3UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Pos 2UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Msk 0x7CUL
+#define BLE_BLESS_ENC_PARAMS_DIRECTION_Pos 7UL
+#define BLE_BLESS_ENC_PARAMS_DIRECTION_Msk 0x80UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Pos 8UL
+#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Msk 0x700UL
+#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Pos 11UL
+#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Msk 0x800UL
+/* BLE_BLESS.ENC_CONFIG */
+#define BLE_BLESS_ENC_CONFIG_START_PROC_Pos 0UL
+#define BLE_BLESS_ENC_CONFIG_START_PROC_Msk 0x1UL
+#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Pos 1UL
+#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Msk 0x2UL
+#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Pos 2UL
+#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Msk 0x4UL
+#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Pos 8UL
+#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Msk 0xFF00UL
+#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Pos 16UL
+#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Msk 0xFF0000UL
+#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Pos 24UL
+#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Msk 0x1000000UL
+/* BLE_BLESS.ENC_INTR_EN */
+#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Pos 0UL
+#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Msk 0x1UL
+#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Pos 1UL
+#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Msk 0x2UL
+#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Pos 2UL
+#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Msk 0x4UL
+/* BLE_BLESS.ENC_INTR */
+#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Pos 0UL
+#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Msk 0x1UL
+#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Pos 1UL
+#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Msk 0x2UL
+#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Pos 2UL
+#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Msk 0x4UL
+#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Pos 3UL
+#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Msk 0x8UL
+/* BLE_BLESS.B1_DATA_REG */
+#define BLE_BLESS_B1_DATA_REG_B1_DATA_Pos 0UL
+#define BLE_BLESS_B1_DATA_REG_B1_DATA_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.ENC_MEM_BASE_ADDR */
+#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Pos 0UL
+#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Msk 0xFFFFFFFFUL
+/* BLE_BLESS.TRIM_LDO_0 */
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Msk 0xFUL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Pos 4UL
+#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Msk 0xF0UL
+/* BLE_BLESS.TRIM_LDO_1 */
+#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Msk 0xFUL
+#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Pos 4UL
+#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Msk 0xF0UL
+/* BLE_BLESS.TRIM_LDO_2 */
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Msk 0x1FUL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Pos 5UL
+#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Msk 0x60UL
+/* BLE_BLESS.TRIM_LDO_3 */
+#define BLE_BLESS_TRIM_LDO_3_LVDET_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_3_LVDET_Msk 0x1FUL
+#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Pos 5UL
+#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Msk 0x60UL
+/* BLE_BLESS.TRIM_MXD */
+#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Pos 0UL
+#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Msk 0xFFUL
+/* BLE_BLESS.TRIM_LDO_4 */
+#define BLE_BLESS_TRIM_LDO_4_T_LDO_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_4_T_LDO_Msk 0xFFUL
+/* BLE_BLESS.TRIM_LDO_5 */
+#define BLE_BLESS_TRIM_LDO_5_RESERVED_Pos 0UL
+#define BLE_BLESS_TRIM_LDO_5_RESERVED_Msk 0xFFUL
+
+
+#endif /* _CYIP_BLE_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_cpuss.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,330 @@
+/***************************************************************************//**
+* \file cyip_cpuss.h
+*
+* \brief
+* CPUSS IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_CPUSS_H_
+#define _CYIP_CPUSS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CPUSS
+*******************************************************************************/
+
+#define CPUSS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief CPU subsystem (CPUSS) (CPUSS)
+ */
+typedef struct {
+ __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */
+ __IM uint32_t RESERVED;
+ __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */
+ __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */
+ __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */
+ __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */
+ __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */
+ __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */
+ __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */
+ __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */
+ __IM uint32_t RESERVED3[16];
+ __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */
+ __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */
+ __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */
+ __IM uint32_t RESERVED6[23];
+ __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */
+ __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */
+ __IM uint32_t RESERVED8[3];
+ __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */
+ __IM uint32_t RESERVED9[3];
+ __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */
+ __IM uint32_t RESERVED10[3];
+ __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */
+ __IM uint32_t RESERVED11[3];
+ __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */
+ __IM uint32_t RESERVED13[7];
+ __IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */
+ __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */
+ __IM uint32_t RESERVED14[4];
+ __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */
+ __IM uint32_t RESERVED15[5];
+ __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */
+ __IM uint32_t RESERVED16[3];
+ __IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */
+ __IM uint32_t RESERVED18[27];
+ __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */
+ __IM uint32_t RESERVED19[3];
+ __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */
+ __IM uint32_t RESERVED20[23];
+ __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */
+ __IM uint32_t RESERVED21[55];
+ __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */
+ __IM uint32_t RESERVED22[63];
+ __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */
+ __IM uint32_t RESERVED23[7];
+ __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */
+ __IM uint32_t RESERVED24[31];
+ __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */
+ __IM uint32_t RESERVED25[14999];
+ __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */
+ __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */
+} CPUSS_Type; /*!< Size = 61448 (0xF008) */
+
+
+/* CPUSS.CM0_CTL */
+#define CPUSS_CM0_CTL_SLV_STALL_Pos 0UL
+#define CPUSS_CM0_CTL_SLV_STALL_Msk 0x1UL
+#define CPUSS_CM0_CTL_ENABLED_Pos 1UL
+#define CPUSS_CM0_CTL_ENABLED_Msk 0x2UL
+#define CPUSS_CM0_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM0_STATUS */
+#define CPUSS_CM0_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_CM0_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_CM0_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_CM0_STATUS_SLEEPDEEP_Msk 0x2UL
+/* CPUSS.CM0_CLOCK_CTL */
+#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL
+#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL
+#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL
+#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL0 */
+#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL1 */
+#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL2 */
+#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL3 */
+#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL4 */
+#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL5 */
+#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL6 */
+#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM0_INT_CTL7 */
+#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Msk 0xFFUL
+#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Pos 8UL
+#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Msk 0xFF00UL
+#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Pos 16UL
+#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Msk 0xFF0000UL
+#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Pos 24UL
+#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Msk 0xFF000000UL
+/* CPUSS.CM4_PWR_CTL */
+#define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.CM4_PWR_DELAY_CTL */
+#define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.CM4_STATUS */
+#define CPUSS_CM4_STATUS_SLEEPING_Pos 0UL
+#define CPUSS_CM4_STATUS_SLEEPING_Msk 0x1UL
+#define CPUSS_CM4_STATUS_SLEEPDEEP_Pos 1UL
+#define CPUSS_CM4_STATUS_SLEEPDEEP_Msk 0x2UL
+#define CPUSS_CM4_STATUS_PWR_DONE_Pos 4UL
+#define CPUSS_CM4_STATUS_PWR_DONE_Msk 0x10UL
+/* CPUSS.CM4_CLOCK_CTL */
+#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL
+#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL
+/* CPUSS.CM4_NMI_CTL */
+#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Pos 0UL
+#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Msk 0xFFUL
+/* CPUSS.RAM0_CTL0 */
+#define CPUSS_RAM0_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM0_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM0_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM0_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM0_PWR_MACRO_CTL */
+#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM1_CTL0 */
+#define CPUSS_RAM1_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM1_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM1_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM1_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM1_PWR_CTL */
+#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM2_CTL0 */
+#define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL
+#define CPUSS_RAM2_CTL0_SLOW_WS_Msk 0x3UL
+#define CPUSS_RAM2_CTL0_FAST_WS_Pos 8UL
+#define CPUSS_RAM2_CTL0_FAST_WS_Msk 0x300UL
+/* CPUSS.RAM2_PWR_CTL */
+#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.RAM_PWR_DELAY_CTL */
+#define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.ROM_CTL */
+#define CPUSS_ROM_CTL_SLOW_WS_Pos 0UL
+#define CPUSS_ROM_CTL_SLOW_WS_Msk 0x3UL
+#define CPUSS_ROM_CTL_FAST_WS_Pos 8UL
+#define CPUSS_ROM_CTL_FAST_WS_Msk 0x300UL
+/* CPUSS.UDB_PWR_CTL */
+#define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos 0UL
+#define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL
+#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL
+#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* CPUSS.UDB_PWR_DELAY_CTL */
+#define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos 0UL
+#define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL
+/* CPUSS.DP_STATUS */
+#define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL
+#define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL
+#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL
+#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL
+#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL
+#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL
+/* CPUSS.BUFF_CTL */
+#define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL
+#define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL
+/* CPUSS.DDFT_CTL */
+#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Pos 0UL
+#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Msk 0x1FUL
+#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Pos 8UL
+#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Msk 0x1F00UL
+/* CPUSS.SYSTICK_CTL */
+#define CPUSS_SYSTICK_CTL_TENMS_Pos 0UL
+#define CPUSS_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL
+#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL
+#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL
+#define CPUSS_SYSTICK_CTL_SKEW_Pos 30UL
+#define CPUSS_SYSTICK_CTL_SKEW_Msk 0x40000000UL
+#define CPUSS_SYSTICK_CTL_NOREF_Pos 31UL
+#define CPUSS_SYSTICK_CTL_NOREF_Msk 0x80000000UL
+/* CPUSS.CM0_VECTOR_TABLE_BASE */
+#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL
+#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL
+/* CPUSS.CM4_VECTOR_TABLE_BASE */
+#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL
+#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL
+/* CPUSS.CM0_PC0_HANDLER */
+#define CPUSS_CM0_PC0_HANDLER_ADDR_Pos 0UL
+#define CPUSS_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL
+/* CPUSS.IDENTITY */
+#define CPUSS_IDENTITY_P_Pos 0UL
+#define CPUSS_IDENTITY_P_Msk 0x1UL
+#define CPUSS_IDENTITY_NS_Pos 1UL
+#define CPUSS_IDENTITY_NS_Msk 0x2UL
+#define CPUSS_IDENTITY_PC_Pos 4UL
+#define CPUSS_IDENTITY_PC_Msk 0xF0UL
+#define CPUSS_IDENTITY_MS_Pos 8UL
+#define CPUSS_IDENTITY_MS_Msk 0xF00UL
+/* CPUSS.PROTECTION */
+#define CPUSS_PROTECTION_STATE_Pos 0UL
+#define CPUSS_PROTECTION_STATE_Msk 0x7UL
+/* CPUSS.CM0_NMI_CTL */
+#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos 0UL
+#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk 0xFFUL
+/* CPUSS.MBIST_STAT */
+#define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL
+#define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL
+#define CPUSS_MBIST_STAT_SFP_FAIL_Pos 1UL
+#define CPUSS_MBIST_STAT_SFP_FAIL_Msk 0x2UL
+/* CPUSS.TRIM_ROM_CTL */
+#define CPUSS_TRIM_ROM_CTL_RM_Pos 0UL
+#define CPUSS_TRIM_ROM_CTL_RM_Msk 0xFUL
+#define CPUSS_TRIM_ROM_CTL_RME_Pos 4UL
+#define CPUSS_TRIM_ROM_CTL_RME_Msk 0x10UL
+/* CPUSS.TRIM_RAM_CTL */
+#define CPUSS_TRIM_RAM_CTL_RM_Pos 0UL
+#define CPUSS_TRIM_RAM_CTL_RM_Msk 0xFUL
+#define CPUSS_TRIM_RAM_CTL_RME_Pos 4UL
+#define CPUSS_TRIM_RAM_CTL_RME_Msk 0x10UL
+#define CPUSS_TRIM_RAM_CTL_WPULSE_Pos 5UL
+#define CPUSS_TRIM_RAM_CTL_WPULSE_Msk 0xE0UL
+#define CPUSS_TRIM_RAM_CTL_RA_Pos 8UL
+#define CPUSS_TRIM_RAM_CTL_RA_Msk 0x300UL
+#define CPUSS_TRIM_RAM_CTL_WA_Pos 12UL
+#define CPUSS_TRIM_RAM_CTL_WA_Msk 0x7000UL
+
+
+#endif /* _CYIP_CPUSS_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_crypto.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,29 @@ +/***************************************************************************//** +* \file cyip_crypto.h +* +* \brief +* CRYPTO IP definitions +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _CYIP_CRYPTO_H_ +#define _CYIP_CRYPTO_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* CRYPTO +******************************************************************************** +* Crypto functionality is supported by Crypto library +*******************************************************************************/ + +typedef uint32_t CRYPTO_Type; + +#endif /* _CYIP_CRYPTO_H_ */ + + +/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_csd.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,475 @@
+/***************************************************************************//**
+* \file cyip_csd.h
+*
+* \brief
+* CSD IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_CSD_H_
+#define _CYIP_CSD_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CSD
+*******************************************************************************/
+
+#define CSD_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief Capsense Controller (CSD)
+ */
+typedef struct {
+ __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */
+ __IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */
+ __IM uint32_t RESERVED[30];
+ __IM uint32_t STATUS; /*!< 0x00000080 Status Register */
+ __IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */
+ __IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */
+ __IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */
+ __IM uint32_t RESERVED1[16];
+ __IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */
+ __IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */
+ __IM uint32_t RESERVED2[2];
+ __IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */
+ __IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */
+ __IM uint32_t RESERVED4[32];
+ __IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */
+ __IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */
+ __IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */
+ __IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */
+ __IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */
+ __IM uint32_t RESERVED7[30];
+ __IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */
+ __IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */
+ __IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */
+ __IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */
+ __IM uint32_t RESERVED9[2];
+ __IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */
+ __IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */
+ __IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */
+ __IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */
+ __IM uint32_t RESERVED11[2];
+ __IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */
+ __IM uint32_t RESERVED13[11];
+ __IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */
+ __IM uint32_t RESERVED14[3];
+ __IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */
+ __IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */
+ __IM uint32_t RESERVED15[2];
+ __IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */
+ __IM uint32_t RESERVED16[7];
+ __IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */
+ __IM uint32_t RESERVED17[47];
+ __IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */
+ __IM uint32_t RESERVED18[63];
+ __IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */
+} CSD_Type; /*!< Size = 1284 (0x504) */
+
+
+/* CSD.CONFIG */
+#define CSD_CONFIG_IREF_SEL_Pos 0UL
+#define CSD_CONFIG_IREF_SEL_Msk 0x1UL
+#define CSD_CONFIG_FILTER_DELAY_Pos 4UL
+#define CSD_CONFIG_FILTER_DELAY_Msk 0x1F0UL
+#define CSD_CONFIG_SHIELD_DELAY_Pos 10UL
+#define CSD_CONFIG_SHIELD_DELAY_Msk 0xC00UL
+#define CSD_CONFIG_SENSE_EN_Pos 12UL
+#define CSD_CONFIG_SENSE_EN_Msk 0x1000UL
+#define CSD_CONFIG_FULL_WAVE_Pos 17UL
+#define CSD_CONFIG_FULL_WAVE_Msk 0x20000UL
+#define CSD_CONFIG_MUTUAL_CAP_Pos 18UL
+#define CSD_CONFIG_MUTUAL_CAP_Msk 0x40000UL
+#define CSD_CONFIG_CSX_DUAL_CNT_Pos 19UL
+#define CSD_CONFIG_CSX_DUAL_CNT_Msk 0x80000UL
+#define CSD_CONFIG_DSI_COUNT_SEL_Pos 24UL
+#define CSD_CONFIG_DSI_COUNT_SEL_Msk 0x1000000UL
+#define CSD_CONFIG_DSI_SAMPLE_EN_Pos 25UL
+#define CSD_CONFIG_DSI_SAMPLE_EN_Msk 0x2000000UL
+#define CSD_CONFIG_SAMPLE_SYNC_Pos 26UL
+#define CSD_CONFIG_SAMPLE_SYNC_Msk 0x4000000UL
+#define CSD_CONFIG_DSI_SENSE_EN_Pos 27UL
+#define CSD_CONFIG_DSI_SENSE_EN_Msk 0x8000000UL
+#define CSD_CONFIG_LP_MODE_Pos 30UL
+#define CSD_CONFIG_LP_MODE_Msk 0x40000000UL
+#define CSD_CONFIG_ENABLE_Pos 31UL
+#define CSD_CONFIG_ENABLE_Msk 0x80000000UL
+/* CSD.SPARE */
+#define CSD_SPARE_SPARE_Pos 0UL
+#define CSD_SPARE_SPARE_Msk 0xFUL
+/* CSD.STATUS */
+#define CSD_STATUS_CSD_SENSE_Pos 1UL
+#define CSD_STATUS_CSD_SENSE_Msk 0x2UL
+#define CSD_STATUS_HSCMP_OUT_Pos 2UL
+#define CSD_STATUS_HSCMP_OUT_Msk 0x4UL
+#define CSD_STATUS_CSDCMP_OUT_Pos 3UL
+#define CSD_STATUS_CSDCMP_OUT_Msk 0x8UL
+/* CSD.STAT_SEQ */
+#define CSD_STAT_SEQ_SEQ_STATE_Pos 0UL
+#define CSD_STAT_SEQ_SEQ_STATE_Msk 0x7UL
+#define CSD_STAT_SEQ_ADC_STATE_Pos 16UL
+#define CSD_STAT_SEQ_ADC_STATE_Msk 0x70000UL
+/* CSD.STAT_CNTS */
+#define CSD_STAT_CNTS_NUM_CONV_Pos 0UL
+#define CSD_STAT_CNTS_NUM_CONV_Msk 0xFFFFUL
+/* CSD.STAT_HCNT */
+#define CSD_STAT_HCNT_CNT_Pos 0UL
+#define CSD_STAT_HCNT_CNT_Msk 0xFFFFUL
+/* CSD.RESULT_VAL1 */
+#define CSD_RESULT_VAL1_VALUE_Pos 0UL
+#define CSD_RESULT_VAL1_VALUE_Msk 0xFFFFUL
+#define CSD_RESULT_VAL1_BAD_CONVS_Pos 16UL
+#define CSD_RESULT_VAL1_BAD_CONVS_Msk 0xFF0000UL
+/* CSD.RESULT_VAL2 */
+#define CSD_RESULT_VAL2_VALUE_Pos 0UL
+#define CSD_RESULT_VAL2_VALUE_Msk 0xFFFFUL
+/* CSD.ADC_RES */
+#define CSD_ADC_RES_VIN_CNT_Pos 0UL
+#define CSD_ADC_RES_VIN_CNT_Msk 0xFFFFUL
+#define CSD_ADC_RES_HSCMP_POL_Pos 16UL
+#define CSD_ADC_RES_HSCMP_POL_Msk 0x10000UL
+#define CSD_ADC_RES_ADC_OVERFLOW_Pos 30UL
+#define CSD_ADC_RES_ADC_OVERFLOW_Msk 0x40000000UL
+#define CSD_ADC_RES_ADC_ABORT_Pos 31UL
+#define CSD_ADC_RES_ADC_ABORT_Msk 0x80000000UL
+/* CSD.INTR */
+#define CSD_INTR_SAMPLE_Pos 1UL
+#define CSD_INTR_SAMPLE_Msk 0x2UL
+#define CSD_INTR_INIT_Pos 2UL
+#define CSD_INTR_INIT_Msk 0x4UL
+#define CSD_INTR_ADC_RES_Pos 8UL
+#define CSD_INTR_ADC_RES_Msk 0x100UL
+/* CSD.INTR_SET */
+#define CSD_INTR_SET_SAMPLE_Pos 1UL
+#define CSD_INTR_SET_SAMPLE_Msk 0x2UL
+#define CSD_INTR_SET_INIT_Pos 2UL
+#define CSD_INTR_SET_INIT_Msk 0x4UL
+#define CSD_INTR_SET_ADC_RES_Pos 8UL
+#define CSD_INTR_SET_ADC_RES_Msk 0x100UL
+/* CSD.INTR_MASK */
+#define CSD_INTR_MASK_SAMPLE_Pos 1UL
+#define CSD_INTR_MASK_SAMPLE_Msk 0x2UL
+#define CSD_INTR_MASK_INIT_Pos 2UL
+#define CSD_INTR_MASK_INIT_Msk 0x4UL
+#define CSD_INTR_MASK_ADC_RES_Pos 8UL
+#define CSD_INTR_MASK_ADC_RES_Msk 0x100UL
+/* CSD.INTR_MASKED */
+#define CSD_INTR_MASKED_SAMPLE_Pos 1UL
+#define CSD_INTR_MASKED_SAMPLE_Msk 0x2UL
+#define CSD_INTR_MASKED_INIT_Pos 2UL
+#define CSD_INTR_MASKED_INIT_Msk 0x4UL
+#define CSD_INTR_MASKED_ADC_RES_Pos 8UL
+#define CSD_INTR_MASKED_ADC_RES_Msk 0x100UL
+/* CSD.HSCMP */
+#define CSD_HSCMP_HSCMP_EN_Pos 0UL
+#define CSD_HSCMP_HSCMP_EN_Msk 0x1UL
+#define CSD_HSCMP_HSCMP_INVERT_Pos 4UL
+#define CSD_HSCMP_HSCMP_INVERT_Msk 0x10UL
+#define CSD_HSCMP_AZ_EN_Pos 31UL
+#define CSD_HSCMP_AZ_EN_Msk 0x80000000UL
+/* CSD.AMBUF */
+#define CSD_AMBUF_PWR_MODE_Pos 0UL
+#define CSD_AMBUF_PWR_MODE_Msk 0x3UL
+/* CSD.REFGEN */
+#define CSD_REFGEN_REFGEN_EN_Pos 0UL
+#define CSD_REFGEN_REFGEN_EN_Msk 0x1UL
+#define CSD_REFGEN_BYPASS_Pos 4UL
+#define CSD_REFGEN_BYPASS_Msk 0x10UL
+#define CSD_REFGEN_VDDA_EN_Pos 5UL
+#define CSD_REFGEN_VDDA_EN_Msk 0x20UL
+#define CSD_REFGEN_RES_EN_Pos 6UL
+#define CSD_REFGEN_RES_EN_Msk 0x40UL
+#define CSD_REFGEN_GAIN_Pos 8UL
+#define CSD_REFGEN_GAIN_Msk 0x1F00UL
+#define CSD_REFGEN_VREFLO_SEL_Pos 16UL
+#define CSD_REFGEN_VREFLO_SEL_Msk 0x1F0000UL
+#define CSD_REFGEN_VREFLO_INT_Pos 23UL
+#define CSD_REFGEN_VREFLO_INT_Msk 0x800000UL
+/* CSD.CSDCMP */
+#define CSD_CSDCMP_CSDCMP_EN_Pos 0UL
+#define CSD_CSDCMP_CSDCMP_EN_Msk 0x1UL
+#define CSD_CSDCMP_POLARITY_SEL_Pos 4UL
+#define CSD_CSDCMP_POLARITY_SEL_Msk 0x30UL
+#define CSD_CSDCMP_CMP_PHASE_Pos 8UL
+#define CSD_CSDCMP_CMP_PHASE_Msk 0x300UL
+#define CSD_CSDCMP_CMP_MODE_Pos 28UL
+#define CSD_CSDCMP_CMP_MODE_Msk 0x10000000UL
+#define CSD_CSDCMP_FEEDBACK_MODE_Pos 29UL
+#define CSD_CSDCMP_FEEDBACK_MODE_Msk 0x20000000UL
+#define CSD_CSDCMP_AZ_EN_Pos 31UL
+#define CSD_CSDCMP_AZ_EN_Msk 0x80000000UL
+/* CSD.SW_RES */
+#define CSD_SW_RES_RES_HCAV_Pos 0UL
+#define CSD_SW_RES_RES_HCAV_Msk 0x3UL
+#define CSD_SW_RES_RES_HCAG_Pos 2UL
+#define CSD_SW_RES_RES_HCAG_Msk 0xCUL
+#define CSD_SW_RES_RES_HCBV_Pos 4UL
+#define CSD_SW_RES_RES_HCBV_Msk 0x30UL
+#define CSD_SW_RES_RES_HCBG_Pos 6UL
+#define CSD_SW_RES_RES_HCBG_Msk 0xC0UL
+#define CSD_SW_RES_RES_F1PM_Pos 16UL
+#define CSD_SW_RES_RES_F1PM_Msk 0x30000UL
+#define CSD_SW_RES_RES_F2PT_Pos 18UL
+#define CSD_SW_RES_RES_F2PT_Msk 0xC0000UL
+/* CSD.SENSE_PERIOD */
+#define CSD_SENSE_PERIOD_SENSE_DIV_Pos 0UL
+#define CSD_SENSE_PERIOD_SENSE_DIV_Msk 0xFFFUL
+#define CSD_SENSE_PERIOD_LFSR_SIZE_Pos 16UL
+#define CSD_SENSE_PERIOD_LFSR_SIZE_Msk 0x70000UL
+#define CSD_SENSE_PERIOD_LFSR_SCALE_Pos 20UL
+#define CSD_SENSE_PERIOD_LFSR_SCALE_Msk 0xF00000UL
+#define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos 24UL
+#define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk 0x1000000UL
+#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos 25UL
+#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk 0x2000000UL
+#define CSD_SENSE_PERIOD_LFSR_BITS_Pos 26UL
+#define CSD_SENSE_PERIOD_LFSR_BITS_Msk 0xC000000UL
+/* CSD.SENSE_DUTY */
+#define CSD_SENSE_DUTY_SENSE_WIDTH_Pos 0UL
+#define CSD_SENSE_DUTY_SENSE_WIDTH_Msk 0xFFFUL
+#define CSD_SENSE_DUTY_SENSE_POL_Pos 16UL
+#define CSD_SENSE_DUTY_SENSE_POL_Msk 0x10000UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos 18UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk 0x40000UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos 19UL
+#define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk 0x80000UL
+/* CSD.SW_HS_P_SEL */
+#define CSD_SW_HS_P_SEL_SW_HMPM_Pos 0UL
+#define CSD_SW_HS_P_SEL_SW_HMPM_Msk 0x1UL
+#define CSD_SW_HS_P_SEL_SW_HMPT_Pos 4UL
+#define CSD_SW_HS_P_SEL_SW_HMPT_Msk 0x10UL
+#define CSD_SW_HS_P_SEL_SW_HMPS_Pos 8UL
+#define CSD_SW_HS_P_SEL_SW_HMPS_Msk 0x100UL
+#define CSD_SW_HS_P_SEL_SW_HMMA_Pos 12UL
+#define CSD_SW_HS_P_SEL_SW_HMMA_Msk 0x1000UL
+#define CSD_SW_HS_P_SEL_SW_HMMB_Pos 16UL
+#define CSD_SW_HS_P_SEL_SW_HMMB_Msk 0x10000UL
+#define CSD_SW_HS_P_SEL_SW_HMCA_Pos 20UL
+#define CSD_SW_HS_P_SEL_SW_HMCA_Msk 0x100000UL
+#define CSD_SW_HS_P_SEL_SW_HMCB_Pos 24UL
+#define CSD_SW_HS_P_SEL_SW_HMCB_Msk 0x1000000UL
+#define CSD_SW_HS_P_SEL_SW_HMRH_Pos 28UL
+#define CSD_SW_HS_P_SEL_SW_HMRH_Msk 0x10000000UL
+/* CSD.SW_HS_N_SEL */
+#define CSD_SW_HS_N_SEL_SW_HCCC_Pos 16UL
+#define CSD_SW_HS_N_SEL_SW_HCCC_Msk 0x10000UL
+#define CSD_SW_HS_N_SEL_SW_HCCD_Pos 20UL
+#define CSD_SW_HS_N_SEL_SW_HCCD_Msk 0x100000UL
+#define CSD_SW_HS_N_SEL_SW_HCRH_Pos 24UL
+#define CSD_SW_HS_N_SEL_SW_HCRH_Msk 0x7000000UL
+#define CSD_SW_HS_N_SEL_SW_HCRL_Pos 28UL
+#define CSD_SW_HS_N_SEL_SW_HCRL_Msk 0x70000000UL
+/* CSD.SW_SHIELD_SEL */
+#define CSD_SW_SHIELD_SEL_SW_HCAV_Pos 0UL
+#define CSD_SW_SHIELD_SEL_SW_HCAV_Msk 0x7UL
+#define CSD_SW_SHIELD_SEL_SW_HCAG_Pos 4UL
+#define CSD_SW_SHIELD_SEL_SW_HCAG_Msk 0x70UL
+#define CSD_SW_SHIELD_SEL_SW_HCBV_Pos 8UL
+#define CSD_SW_SHIELD_SEL_SW_HCBV_Msk 0x700UL
+#define CSD_SW_SHIELD_SEL_SW_HCBG_Pos 12UL
+#define CSD_SW_SHIELD_SEL_SW_HCBG_Msk 0x7000UL
+#define CSD_SW_SHIELD_SEL_SW_HCCV_Pos 16UL
+#define CSD_SW_SHIELD_SEL_SW_HCCV_Msk 0x10000UL
+#define CSD_SW_SHIELD_SEL_SW_HCCG_Pos 20UL
+#define CSD_SW_SHIELD_SEL_SW_HCCG_Msk 0x100000UL
+/* CSD.SW_AMUXBUF_SEL */
+#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos 4UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk 0x10UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos 8UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk 0x100UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos 12UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk 0x1000UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos 16UL
+#define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk 0x70000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos 20UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk 0x100000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos 24UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk 0x1000000UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos 28UL
+#define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk 0x10000000UL
+/* CSD.SW_BYP_SEL */
+#define CSD_SW_BYP_SEL_SW_BYA_Pos 12UL
+#define CSD_SW_BYP_SEL_SW_BYA_Msk 0x1000UL
+#define CSD_SW_BYP_SEL_SW_BYB_Pos 16UL
+#define CSD_SW_BYP_SEL_SW_BYB_Msk 0x10000UL
+#define CSD_SW_BYP_SEL_SW_CBCC_Pos 20UL
+#define CSD_SW_BYP_SEL_SW_CBCC_Msk 0x100000UL
+/* CSD.SW_CMP_P_SEL */
+#define CSD_SW_CMP_P_SEL_SW_SFPM_Pos 0UL
+#define CSD_SW_CMP_P_SEL_SW_SFPM_Msk 0x7UL
+#define CSD_SW_CMP_P_SEL_SW_SFPT_Pos 4UL
+#define CSD_SW_CMP_P_SEL_SW_SFPT_Msk 0x70UL
+#define CSD_SW_CMP_P_SEL_SW_SFPS_Pos 8UL
+#define CSD_SW_CMP_P_SEL_SW_SFPS_Msk 0x700UL
+#define CSD_SW_CMP_P_SEL_SW_SFMA_Pos 12UL
+#define CSD_SW_CMP_P_SEL_SW_SFMA_Msk 0x1000UL
+#define CSD_SW_CMP_P_SEL_SW_SFMB_Pos 16UL
+#define CSD_SW_CMP_P_SEL_SW_SFMB_Msk 0x10000UL
+#define CSD_SW_CMP_P_SEL_SW_SFCA_Pos 20UL
+#define CSD_SW_CMP_P_SEL_SW_SFCA_Msk 0x100000UL
+#define CSD_SW_CMP_P_SEL_SW_SFCB_Pos 24UL
+#define CSD_SW_CMP_P_SEL_SW_SFCB_Msk 0x1000000UL
+/* CSD.SW_CMP_N_SEL */
+#define CSD_SW_CMP_N_SEL_SW_SCRH_Pos 24UL
+#define CSD_SW_CMP_N_SEL_SW_SCRH_Msk 0x7000000UL
+#define CSD_SW_CMP_N_SEL_SW_SCRL_Pos 28UL
+#define CSD_SW_CMP_N_SEL_SW_SCRL_Msk 0x70000000UL
+/* CSD.SW_REFGEN_SEL */
+#define CSD_SW_REFGEN_SEL_SW_IAIB_Pos 0UL
+#define CSD_SW_REFGEN_SEL_SW_IAIB_Msk 0x1UL
+#define CSD_SW_REFGEN_SEL_SW_IBCB_Pos 4UL
+#define CSD_SW_REFGEN_SEL_SW_IBCB_Msk 0x10UL
+#define CSD_SW_REFGEN_SEL_SW_SGMB_Pos 16UL
+#define CSD_SW_REFGEN_SEL_SW_SGMB_Msk 0x10000UL
+#define CSD_SW_REFGEN_SEL_SW_SGRP_Pos 20UL
+#define CSD_SW_REFGEN_SEL_SW_SGRP_Msk 0x100000UL
+#define CSD_SW_REFGEN_SEL_SW_SGRE_Pos 24UL
+#define CSD_SW_REFGEN_SEL_SW_SGRE_Msk 0x1000000UL
+#define CSD_SW_REFGEN_SEL_SW_SGR_Pos 28UL
+#define CSD_SW_REFGEN_SEL_SW_SGR_Msk 0x10000000UL
+/* CSD.SW_FW_MOD_SEL */
+#define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos 0UL
+#define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk 0x1UL
+#define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos 8UL
+#define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk 0x700UL
+#define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos 16UL
+#define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk 0x70000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos 20UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk 0x100000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos 24UL
+#define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk 0x1000000UL
+#define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos 28UL
+#define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk 0x10000000UL
+/* CSD.SW_FW_TANK_SEL */
+#define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos 4UL
+#define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk 0x10UL
+#define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos 8UL
+#define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk 0x700UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos 12UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk 0x7000UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos 16UL
+#define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk 0x70000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos 20UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk 0x100000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos 24UL
+#define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk 0x1000000UL
+#define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos 28UL
+#define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk 0x10000000UL
+/* CSD.SW_DSI_SEL */
+#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos 0UL
+#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk 0xFUL
+#define CSD_SW_DSI_SEL_DSI_CMOD_Pos 4UL
+#define CSD_SW_DSI_SEL_DSI_CMOD_Msk 0xF0UL
+/* CSD.IO_SEL */
+#define CSD_IO_SEL_CSD_TX_OUT_Pos 0UL
+#define CSD_IO_SEL_CSD_TX_OUT_Msk 0xFUL
+#define CSD_IO_SEL_CSD_TX_OUT_EN_Pos 4UL
+#define CSD_IO_SEL_CSD_TX_OUT_EN_Msk 0xF0UL
+#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos 12UL
+#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk 0xF000UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_Pos 16UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_Msk 0xF0000UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos 20UL
+#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk 0xF00000UL
+#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos 24UL
+#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk 0xF000000UL
+/* CSD.SEQ_TIME */
+#define CSD_SEQ_TIME_AZ_TIME_Pos 0UL
+#define CSD_SEQ_TIME_AZ_TIME_Msk 0xFFUL
+/* CSD.SEQ_INIT_CNT */
+#define CSD_SEQ_INIT_CNT_CONV_CNT_Pos 0UL
+#define CSD_SEQ_INIT_CNT_CONV_CNT_Msk 0xFFFFUL
+/* CSD.SEQ_NORM_CNT */
+#define CSD_SEQ_NORM_CNT_CONV_CNT_Pos 0UL
+#define CSD_SEQ_NORM_CNT_CONV_CNT_Msk 0xFFFFUL
+/* CSD.ADC_CTL */
+#define CSD_ADC_CTL_ADC_TIME_Pos 0UL
+#define CSD_ADC_CTL_ADC_TIME_Msk 0xFFUL
+#define CSD_ADC_CTL_ADC_MODE_Pos 16UL
+#define CSD_ADC_CTL_ADC_MODE_Msk 0x30000UL
+/* CSD.SEQ_START */
+#define CSD_SEQ_START_START_Pos 0UL
+#define CSD_SEQ_START_START_Msk 0x1UL
+#define CSD_SEQ_START_SEQ_MODE_Pos 1UL
+#define CSD_SEQ_START_SEQ_MODE_Msk 0x2UL
+#define CSD_SEQ_START_ABORT_Pos 3UL
+#define CSD_SEQ_START_ABORT_Msk 0x8UL
+#define CSD_SEQ_START_DSI_START_EN_Pos 4UL
+#define CSD_SEQ_START_DSI_START_EN_Msk 0x10UL
+#define CSD_SEQ_START_AZ0_SKIP_Pos 8UL
+#define CSD_SEQ_START_AZ0_SKIP_Msk 0x100UL
+#define CSD_SEQ_START_AZ1_SKIP_Pos 9UL
+#define CSD_SEQ_START_AZ1_SKIP_Msk 0x200UL
+/* CSD.IDACA */
+#define CSD_IDACA_VAL_Pos 0UL
+#define CSD_IDACA_VAL_Msk 0x7FUL
+#define CSD_IDACA_POL_DYN_Pos 7UL
+#define CSD_IDACA_POL_DYN_Msk 0x80UL
+#define CSD_IDACA_POLARITY_Pos 8UL
+#define CSD_IDACA_POLARITY_Msk 0x300UL
+#define CSD_IDACA_BAL_MODE_Pos 10UL
+#define CSD_IDACA_BAL_MODE_Msk 0xC00UL
+#define CSD_IDACA_LEG1_MODE_Pos 16UL
+#define CSD_IDACA_LEG1_MODE_Msk 0x30000UL
+#define CSD_IDACA_LEG2_MODE_Pos 18UL
+#define CSD_IDACA_LEG2_MODE_Msk 0xC0000UL
+#define CSD_IDACA_DSI_CTRL_EN_Pos 21UL
+#define CSD_IDACA_DSI_CTRL_EN_Msk 0x200000UL
+#define CSD_IDACA_RANGE_Pos 22UL
+#define CSD_IDACA_RANGE_Msk 0xC00000UL
+#define CSD_IDACA_LEG1_EN_Pos 24UL
+#define CSD_IDACA_LEG1_EN_Msk 0x1000000UL
+#define CSD_IDACA_LEG2_EN_Pos 25UL
+#define CSD_IDACA_LEG2_EN_Msk 0x2000000UL
+/* CSD.IDACB */
+#define CSD_IDACB_VAL_Pos 0UL
+#define CSD_IDACB_VAL_Msk 0x7FUL
+#define CSD_IDACB_POL_DYN_Pos 7UL
+#define CSD_IDACB_POL_DYN_Msk 0x80UL
+#define CSD_IDACB_POLARITY_Pos 8UL
+#define CSD_IDACB_POLARITY_Msk 0x300UL
+#define CSD_IDACB_BAL_MODE_Pos 10UL
+#define CSD_IDACB_BAL_MODE_Msk 0xC00UL
+#define CSD_IDACB_LEG1_MODE_Pos 16UL
+#define CSD_IDACB_LEG1_MODE_Msk 0x30000UL
+#define CSD_IDACB_LEG2_MODE_Pos 18UL
+#define CSD_IDACB_LEG2_MODE_Msk 0xC0000UL
+#define CSD_IDACB_DSI_CTRL_EN_Pos 21UL
+#define CSD_IDACB_DSI_CTRL_EN_Msk 0x200000UL
+#define CSD_IDACB_RANGE_Pos 22UL
+#define CSD_IDACB_RANGE_Msk 0xC00000UL
+#define CSD_IDACB_LEG1_EN_Pos 24UL
+#define CSD_IDACB_LEG1_EN_Msk 0x1000000UL
+#define CSD_IDACB_LEG2_EN_Pos 25UL
+#define CSD_IDACB_LEG2_EN_Msk 0x2000000UL
+#define CSD_IDACB_LEG3_EN_Pos 26UL
+#define CSD_IDACB_LEG3_EN_Msk 0x4000000UL
+
+
+#endif /* _CYIP_CSD_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_ctbm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,285 @@
+/***************************************************************************//**
+* \file cyip_ctbm.h
+*
+* \brief
+* CTBM IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_CTBM_H_
+#define _CYIP_CTBM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CTBM
+*******************************************************************************/
+
+#define CTBM_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Continuous Time Block Mini (CTBM)
+ */
+typedef struct {
+ __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */
+ __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */
+ __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */
+ __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
+ __IM uint32_t RESERVED1[20];
+ __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */
+ __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */
+ __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */
+ __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */
+ __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */
+ __IM uint32_t RESERVED3[6];
+ __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */
+ __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */
+ __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */
+ __IM uint32_t RESERVED4[909];
+ __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */
+ __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */
+ __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */
+ __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */
+ __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */
+ __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */
+} CTBM_Type; /*!< Size = 3864 (0xF18) */
+
+
+/* CTBM.CTB_CTRL */
+#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define CTBM_CTB_CTRL_ENABLED_Pos 31UL
+#define CTBM_CTB_CTRL_ENABLED_Msk 0x80000000UL
+/* CTBM.OA_RES0_CTRL */
+#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL
+#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL
+#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL
+#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL
+#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL
+#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL
+#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL
+#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL
+#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL
+#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL
+#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL
+#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL
+#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL
+#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL
+#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL
+#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL
+#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL
+#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL
+/* CTBM.OA_RES1_CTRL */
+#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL
+#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL
+#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL
+#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL
+#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL
+#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL
+#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL
+#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL
+#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL
+#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL
+#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL
+#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL
+#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL
+#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL
+#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL
+#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL
+#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL
+#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL
+/* CTBM.COMP_STAT */
+#define CTBM_COMP_STAT_OA0_COMP_Pos 0UL
+#define CTBM_COMP_STAT_OA0_COMP_Msk 0x1UL
+#define CTBM_COMP_STAT_OA1_COMP_Pos 16UL
+#define CTBM_COMP_STAT_OA1_COMP_Msk 0x10000UL
+/* CTBM.INTR */
+#define CTBM_INTR_COMP0_Pos 0UL
+#define CTBM_INTR_COMP0_Msk 0x1UL
+#define CTBM_INTR_COMP1_Pos 1UL
+#define CTBM_INTR_COMP1_Msk 0x2UL
+/* CTBM.INTR_SET */
+#define CTBM_INTR_SET_COMP0_SET_Pos 0UL
+#define CTBM_INTR_SET_COMP0_SET_Msk 0x1UL
+#define CTBM_INTR_SET_COMP1_SET_Pos 1UL
+#define CTBM_INTR_SET_COMP1_SET_Msk 0x2UL
+/* CTBM.INTR_MASK */
+#define CTBM_INTR_MASK_COMP0_MASK_Pos 0UL
+#define CTBM_INTR_MASK_COMP0_MASK_Msk 0x1UL
+#define CTBM_INTR_MASK_COMP1_MASK_Pos 1UL
+#define CTBM_INTR_MASK_COMP1_MASK_Msk 0x2UL
+/* CTBM.INTR_MASKED */
+#define CTBM_INTR_MASKED_COMP0_MASKED_Pos 0UL
+#define CTBM_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
+#define CTBM_INTR_MASKED_COMP1_MASKED_Pos 1UL
+#define CTBM_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
+/* CTBM.OA0_SW */
+#define CTBM_OA0_SW_OA0P_A00_Pos 0UL
+#define CTBM_OA0_SW_OA0P_A00_Msk 0x1UL
+#define CTBM_OA0_SW_OA0P_A20_Pos 2UL
+#define CTBM_OA0_SW_OA0P_A20_Msk 0x4UL
+#define CTBM_OA0_SW_OA0P_A30_Pos 3UL
+#define CTBM_OA0_SW_OA0P_A30_Msk 0x8UL
+#define CTBM_OA0_SW_OA0M_A11_Pos 8UL
+#define CTBM_OA0_SW_OA0M_A11_Msk 0x100UL
+#define CTBM_OA0_SW_OA0M_A81_Pos 14UL
+#define CTBM_OA0_SW_OA0M_A81_Msk 0x4000UL
+#define CTBM_OA0_SW_OA0O_D51_Pos 18UL
+#define CTBM_OA0_SW_OA0O_D51_Msk 0x40000UL
+#define CTBM_OA0_SW_OA0O_D81_Pos 21UL
+#define CTBM_OA0_SW_OA0O_D81_Msk 0x200000UL
+/* CTBM.OA0_SW_CLEAR */
+#define CTBM_OA0_SW_CLEAR_OA0P_A00_Pos 0UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A20_Pos 2UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A30_Pos 3UL
+#define CTBM_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A11_Pos 8UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A81_Pos 14UL
+#define CTBM_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D51_Pos 18UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D81_Pos 21UL
+#define CTBM_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL
+/* CTBM.OA1_SW */
+#define CTBM_OA1_SW_OA1P_A03_Pos 0UL
+#define CTBM_OA1_SW_OA1P_A03_Msk 0x1UL
+#define CTBM_OA1_SW_OA1P_A13_Pos 1UL
+#define CTBM_OA1_SW_OA1P_A13_Msk 0x2UL
+#define CTBM_OA1_SW_OA1P_A43_Pos 4UL
+#define CTBM_OA1_SW_OA1P_A43_Msk 0x10UL
+#define CTBM_OA1_SW_OA1P_A73_Pos 7UL
+#define CTBM_OA1_SW_OA1P_A73_Msk 0x80UL
+#define CTBM_OA1_SW_OA1M_A22_Pos 8UL
+#define CTBM_OA1_SW_OA1M_A22_Msk 0x100UL
+#define CTBM_OA1_SW_OA1M_A82_Pos 14UL
+#define CTBM_OA1_SW_OA1M_A82_Msk 0x4000UL
+#define CTBM_OA1_SW_OA1O_D52_Pos 18UL
+#define CTBM_OA1_SW_OA1O_D52_Msk 0x40000UL
+#define CTBM_OA1_SW_OA1O_D62_Pos 19UL
+#define CTBM_OA1_SW_OA1O_D62_Msk 0x80000UL
+#define CTBM_OA1_SW_OA1O_D82_Pos 21UL
+#define CTBM_OA1_SW_OA1O_D82_Msk 0x200000UL
+/* CTBM.OA1_SW_CLEAR */
+#define CTBM_OA1_SW_CLEAR_OA1P_A03_Pos 0UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A13_Pos 1UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A43_Pos 4UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A73_Pos 7UL
+#define CTBM_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A22_Pos 8UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A82_Pos 14UL
+#define CTBM_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D52_Pos 18UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D62_Pos 19UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D82_Pos 21UL
+#define CTBM_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL
+/* CTBM.CTD_SW */
+#define CTBM_CTD_SW_CTDD_CRD_Pos 1UL
+#define CTBM_CTD_SW_CTDD_CRD_Msk 0x2UL
+#define CTBM_CTD_SW_CTDS_CRS_Pos 4UL
+#define CTBM_CTD_SW_CTDS_CRS_Msk 0x10UL
+#define CTBM_CTD_SW_CTDS_COR_Pos 5UL
+#define CTBM_CTD_SW_CTDS_COR_Msk 0x20UL
+#define CTBM_CTD_SW_CTDO_C6H_Pos 8UL
+#define CTBM_CTD_SW_CTDO_C6H_Msk 0x100UL
+#define CTBM_CTD_SW_CTDO_COS_Pos 9UL
+#define CTBM_CTD_SW_CTDO_COS_Msk 0x200UL
+#define CTBM_CTD_SW_CTDH_COB_Pos 10UL
+#define CTBM_CTD_SW_CTDH_COB_Msk 0x400UL
+#define CTBM_CTD_SW_CTDH_CHD_Pos 12UL
+#define CTBM_CTD_SW_CTDH_CHD_Msk 0x1000UL
+#define CTBM_CTD_SW_CTDH_CA0_Pos 13UL
+#define CTBM_CTD_SW_CTDH_CA0_Msk 0x2000UL
+#define CTBM_CTD_SW_CTDH_CIS_Pos 14UL
+#define CTBM_CTD_SW_CTDH_CIS_Msk 0x4000UL
+#define CTBM_CTD_SW_CTDH_ILR_Pos 15UL
+#define CTBM_CTD_SW_CTDH_ILR_Msk 0x8000UL
+/* CTBM.CTD_SW_CLEAR */
+#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL
+#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL
+#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL
+#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL
+#define CTBM_CTD_SW_CLEAR_CTDS_COR_Pos 5UL
+#define CTBM_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL
+#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL
+#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL
+#define CTBM_CTD_SW_CLEAR_CTDO_COS_Pos 9UL
+#define CTBM_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL
+#define CTBM_CTD_SW_CLEAR_CTDH_COB_Pos 10UL
+#define CTBM_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL
+#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL
+#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL
+#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL
+/* CTBM.CTB_SW_DS_CTRL */
+#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL
+#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL
+#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL
+#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL
+#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL
+#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL
+/* CTBM.CTB_SW_SQ_CTRL */
+#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL
+#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL
+#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL
+#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL
+/* CTBM.CTB_SW_STATUS */
+#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL
+#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL
+#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL
+#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL
+#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL
+#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL
+#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL
+#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL
+/* CTBM.OA0_OFFSET_TRIM */
+#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA0_SLOPE_OFFSET_TRIM */
+#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA0_COMP_TRIM */
+#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL
+#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL
+/* CTBM.OA1_OFFSET_TRIM */
+#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA1_SLOPE_OFFSET_TRIM */
+#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL
+#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL
+/* CTBM.OA1_COMP_TRIM */
+#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL
+#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL
+
+
+#endif /* _CYIP_CTBM_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_ctdac.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,103 @@
+/***************************************************************************//**
+* \file cyip_ctdac.h
+*
+* \brief
+* CTDAC IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_CTDAC_H_
+#define _CYIP_CTDAC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* CTDAC
+*******************************************************************************/
+
+#define CTDAC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Continuous Time DAC (CTDAC)
+ */
+typedef struct {
+ __IOM uint32_t CTDAC_CTRL; /*!< 0x00000000 Global CTDAC control */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
+ __IM uint32_t RESERVED1[32];
+ __IOM uint32_t CTDAC_SW; /*!< 0x000000B0 CTDAC switch control */
+ __IOM uint32_t CTDAC_SW_CLEAR; /*!< 0x000000B4 CTDAC switch control clear */
+ __IM uint32_t RESERVED2[18];
+ __IOM uint32_t CTDAC_VAL; /*!< 0x00000100 DAC Value */
+ __IOM uint32_t CTDAC_VAL_NXT; /*!< 0x00000104 Next DAC value (double buffering) */
+} CTDAC_Type; /*!< Size = 264 (0x108) */
+
+
+/* CTDAC.CTDAC_CTRL */
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos 0UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk 0x3FUL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Pos 8UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk 0x100UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Pos 9UL
+#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk 0x200UL
+#define CTDAC_CTDAC_CTRL_OUT_EN_Pos 22UL
+#define CTDAC_CTDAC_CTRL_OUT_EN_Msk 0x400000UL
+#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Pos 23UL
+#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk 0x800000UL
+#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos 24UL
+#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk 0x3000000UL
+#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Pos 27UL
+#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk 0x8000000UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Pos 28UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk 0x10000000UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Pos 29UL
+#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk 0x20000000UL
+#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define CTDAC_CTDAC_CTRL_ENABLED_Pos 31UL
+#define CTDAC_CTDAC_CTRL_ENABLED_Msk 0x80000000UL
+/* CTDAC.INTR */
+#define CTDAC_INTR_VDAC_EMPTY_Pos 0UL
+#define CTDAC_INTR_VDAC_EMPTY_Msk 0x1UL
+/* CTDAC.INTR_SET */
+#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Pos 0UL
+#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk 0x1UL
+/* CTDAC.INTR_MASK */
+#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos 0UL
+#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk 0x1UL
+/* CTDAC.INTR_MASKED */
+#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos 0UL
+#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk 0x1UL
+/* CTDAC.CTDAC_SW */
+#define CTDAC_CTDAC_SW_CTDD_CVD_Pos 0UL
+#define CTDAC_CTDAC_SW_CTDD_CVD_Msk 0x1UL
+#define CTDAC_CTDAC_SW_CTDO_CO6_Pos 8UL
+#define CTDAC_CTDAC_SW_CTDO_CO6_Msk 0x100UL
+/* CTDAC.CTDAC_SW_CLEAR */
+#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Pos 0UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk 0x1UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Pos 8UL
+#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk 0x100UL
+/* CTDAC.CTDAC_VAL */
+#define CTDAC_CTDAC_VAL_VALUE_Pos 0UL
+#define CTDAC_CTDAC_VAL_VALUE_Msk 0xFFFUL
+/* CTDAC.CTDAC_VAL_NXT */
+#define CTDAC_CTDAC_VAL_NXT_VALUE_Pos 0UL
+#define CTDAC_CTDAC_VAL_NXT_VALUE_Msk 0xFFFUL
+
+
+#endif /* _CYIP_CTDAC_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_dw.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,169 @@
+/***************************************************************************//**
+* \file cyip_dw.h
+*
+* \brief
+* DW IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_DW_H_
+#define _CYIP_DW_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* DW
+*******************************************************************************/
+
+#define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL
+#define DW_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief DW channel structure (DW_CH_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */
+ __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */
+ __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */
+ __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
+ __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */
+} DW_CH_STRUCT_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief Datawire Controller (DW)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IM uint32_t PENDING; /*!< 0x00000008 Pending channels */
+ __IM uint32_t RESERVED;
+ __IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */
+ __IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */
+ __IM uint32_t RESERVED1[2];
+ __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
+ __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
+ __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
+ __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
+ __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
+ __IM uint32_t RESERVED3;
+ __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */
+ __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */
+ __IM uint32_t RESERVED4[494];
+ DW_CH_STRUCT_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */
+} DW_Type; /*!< Size = 3072 (0xC00) */
+
+
+/* DW_CH_STRUCT.CH_CTL */
+#define DW_CH_STRUCT_CH_CTL_P_Pos 0UL
+#define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL
+#define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL
+#define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL
+#define DW_CH_STRUCT_CH_CTL_B_Pos 2UL
+#define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL
+#define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL
+#define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL
+#define DW_CH_STRUCT_CH_CTL_PRIO_Pos 16UL
+#define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x30000UL
+#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 18UL
+#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x40000UL
+#define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL
+#define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL
+/* DW_CH_STRUCT.CH_STATUS */
+#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL
+#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL
+/* DW_CH_STRUCT.CH_IDX */
+#define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL
+#define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL
+#define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL
+#define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL
+/* DW_CH_STRUCT.CH_CURR_PTR */
+#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL
+#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW_CH_STRUCT.INTR */
+#define DW_CH_STRUCT_INTR_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_SET */
+#define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASK */
+#define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL
+/* DW_CH_STRUCT.INTR_MASKED */
+#define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL
+#define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL
+
+
+/* DW.CTL */
+#define DW_CTL_ENABLED_Pos 31UL
+#define DW_CTL_ENABLED_Msk 0x80000000UL
+/* DW.STATUS */
+#define DW_STATUS_P_Pos 0UL
+#define DW_STATUS_P_Msk 0x1UL
+#define DW_STATUS_NS_Pos 1UL
+#define DW_STATUS_NS_Msk 0x2UL
+#define DW_STATUS_B_Pos 2UL
+#define DW_STATUS_B_Msk 0x4UL
+#define DW_STATUS_PC_Pos 4UL
+#define DW_STATUS_PC_Msk 0xF0UL
+#define DW_STATUS_CH_IDX_Pos 8UL
+#define DW_STATUS_CH_IDX_Msk 0x1F00UL
+#define DW_STATUS_PRIO_Pos 16UL
+#define DW_STATUS_PRIO_Msk 0x30000UL
+#define DW_STATUS_PREEMPTABLE_Pos 18UL
+#define DW_STATUS_PREEMPTABLE_Msk 0x40000UL
+#define DW_STATUS_STATE_Pos 20UL
+#define DW_STATUS_STATE_Msk 0x700000UL
+#define DW_STATUS_ACTIVE_Pos 31UL
+#define DW_STATUS_ACTIVE_Msk 0x80000000UL
+/* DW.PENDING */
+#define DW_PENDING_CH_PENDING_Pos 0UL
+#define DW_PENDING_CH_PENDING_Msk 0xFFFFFFFFUL
+/* DW.STATUS_INTR */
+#define DW_STATUS_INTR_CH_Pos 0UL
+#define DW_STATUS_INTR_CH_Msk 0xFFFFFFFFUL
+/* DW.STATUS_INTR_MASKED */
+#define DW_STATUS_INTR_MASKED_CH_Pos 0UL
+#define DW_STATUS_INTR_MASKED_CH_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_CTL */
+#define DW_ACT_DESCR_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_SRC */
+#define DW_ACT_DESCR_SRC_DATA_Pos 0UL
+#define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_DST */
+#define DW_ACT_DESCR_DST_DATA_Pos 0UL
+#define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_X_CTL */
+#define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_Y_CTL */
+#define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL
+#define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
+/* DW.ACT_DESCR_NEXT_PTR */
+#define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
+#define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
+/* DW.ACT_SRC */
+#define DW_ACT_SRC_SRC_ADDR_Pos 0UL
+#define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
+/* DW.ACT_DST */
+#define DW_ACT_DST_DST_ADDR_Pos 0UL
+#define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_DW_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_efuse.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,316 @@
+/***************************************************************************//**
+* \file cyip_efuse.h
+*
+* \brief
+* EFUSE IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_H_
+#define _CYIP_EFUSE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* EFUSE
+*******************************************************************************/
+
+#define EFUSE_SECTION_SIZE 0x00000080UL
+
+/**
+ * \brief EFUSE MXS40 registers (EFUSE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CMD; /*!< 0x00000010 Command */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t SEQ_DEFAULT; /*!< 0x00000020 Sequencer Default value */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t SEQ_READ_CTL_0; /*!< 0x00000040 Sequencer read control 0 */
+ __IOM uint32_t SEQ_READ_CTL_1; /*!< 0x00000044 Sequencer read control 1 */
+ __IOM uint32_t SEQ_READ_CTL_2; /*!< 0x00000048 Sequencer read control 2 */
+ __IOM uint32_t SEQ_READ_CTL_3; /*!< 0x0000004C Sequencer read control 3 */
+ __IOM uint32_t SEQ_READ_CTL_4; /*!< 0x00000050 Sequencer read control 4 */
+ __IOM uint32_t SEQ_READ_CTL_5; /*!< 0x00000054 Sequencer read control 5 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t SEQ_PROGRAM_CTL_0; /*!< 0x00000060 Sequencer program control 0 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_1; /*!< 0x00000064 Sequencer program control 1 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_2; /*!< 0x00000068 Sequencer program control 2 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_3; /*!< 0x0000006C Sequencer program control 3 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_4; /*!< 0x00000070 Sequencer program control 4 */
+ __IOM uint32_t SEQ_PROGRAM_CTL_5; /*!< 0x00000074 Sequencer program control 5 */
+} EFUSE_Type; /*!< Size = 120 (0x78) */
+
+
+/* EFUSE.CTL */
+#define EFUSE_CTL_ENABLED_Pos 31UL
+#define EFUSE_CTL_ENABLED_Msk 0x80000000UL
+/* EFUSE.CMD */
+#define EFUSE_CMD_BIT_DATA_Pos 0UL
+#define EFUSE_CMD_BIT_DATA_Msk 0x1UL
+#define EFUSE_CMD_BIT_ADDR_Pos 4UL
+#define EFUSE_CMD_BIT_ADDR_Msk 0x70UL
+#define EFUSE_CMD_BYTE_ADDR_Pos 8UL
+#define EFUSE_CMD_BYTE_ADDR_Msk 0x1F00UL
+#define EFUSE_CMD_MACRO_ADDR_Pos 16UL
+#define EFUSE_CMD_MACRO_ADDR_Msk 0xF0000UL
+#define EFUSE_CMD_START_Pos 31UL
+#define EFUSE_CMD_START_Msk 0x80000000UL
+/* EFUSE.SEQ_DEFAULT */
+#define EFUSE_SEQ_DEFAULT_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_DEFAULT_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_DEFAULT_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_DEFAULT_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_DEFAULT_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_DEFAULT_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_DEFAULT_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_DEFAULT_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_DEFAULT_STROBE_G_Msk 0x400000UL
+/* EFUSE.SEQ_READ_CTL_0 */
+#define EFUSE_SEQ_READ_CTL_0_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_0_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_0_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_0_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_1 */
+#define EFUSE_SEQ_READ_CTL_1_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_1_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_1_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_1_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_2 */
+#define EFUSE_SEQ_READ_CTL_2_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_2_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_2_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_2_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_3 */
+#define EFUSE_SEQ_READ_CTL_3_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_3_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_3_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_3_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_4 */
+#define EFUSE_SEQ_READ_CTL_4_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_4_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_4_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_4_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_READ_CTL_5 */
+#define EFUSE_SEQ_READ_CTL_5_CYCLES_Pos 0UL
+#define EFUSE_SEQ_READ_CTL_5_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_READ_CTL_5_DONE_Pos 31UL
+#define EFUSE_SEQ_READ_CTL_5_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_0 */
+#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_1 */
+#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_2 */
+#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_3 */
+#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_4 */
+#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Msk 0x80000000UL
+/* EFUSE.SEQ_PROGRAM_CTL_5 */
+#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Pos 0UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Msk 0x3FFUL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Pos 16UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Msk 0x10000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Pos 17UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Msk 0x20000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Pos 18UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Msk 0x40000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Pos 19UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Msk 0x80000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Pos 20UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Msk 0x100000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Pos 21UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Msk 0x200000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Pos 22UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Msk 0x400000UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Pos 31UL
+#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_EFUSE_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_efuse_data.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,103 @@
+/***************************************************************************//**
+* \file cyip_efuse_data.h
+*
+* \brief
+* EFUSE_DATA IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_EFUSE_DATA_H_
+#define _CYIP_EFUSE_DATA_H_
+
+#include "cyip_headers.h"
+
+/**
+ * \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_dead_access_restrict0_t;
+
+/**
+ * \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t SMIF_XIP_ALLOWED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_dead_access_restrict1_t;
+
+/**
+ * \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT0)
+ */
+typedef struct {
+ uint8_t CM0_DISABLE;
+ uint8_t CM4_DISABLE;
+ uint8_t SYS_DISABLE;
+ uint8_t SYS_AP_MPU_ENABLE;
+ uint8_t SFLASH_ALLOWED[2];
+ uint8_t MMIO_ALLOWED[2];
+} cy_stc_secure_access_restrict0_t;
+
+/**
+ * \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT1)
+ */
+typedef struct {
+ uint8_t FLASH_ALLOWED[3];
+ uint8_t SRAM_ALLOWED[3];
+ uint8_t SMIF_XIP_ALLOWED;
+ uint8_t DIRECT_EXECUTE_DISABLE;
+} cy_stc_secure_access_restrict1_t;
+
+/**
+ * \brief NORMAL, SECURE_WITH_DEBUG, and SECURE fuse bits (LIFECYCLE_STAGE)
+ */
+typedef struct {
+ uint8_t NORMAL;
+ uint8_t SECURE_WITH_DEBUG;
+ uint8_t SECURE;
+ uint8_t RMA;
+ uint8_t RESERVED[4];
+} cy_stc_lifecycle_stage_t;
+
+/**
+ * \brief Customer data (CUSTOMER_DATA)
+ */
+typedef struct {
+ uint8_t CUSTOMER_USE[8];
+} cy_stc_customer_data_t;
+
+
+/**
+ * \brief eFUSE memory (EFUSE_DATA)
+ */
+typedef struct {
+ uint8_t RESERVED[312];
+ cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0;
+ cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1;
+ cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0;
+ cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1;
+ cy_stc_lifecycle_stage_t LIFECYCLE_STAGE;
+ uint8_t RESERVED1[160];
+ cy_stc_customer_data_t CUSTOMER_DATA[64];
+} cy_stc_efuse_data_t;
+
+
+#endif /* _CYIP_EFUSE_DATA_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_fault.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,111 @@
+/***************************************************************************//**
+* \file cyip_fault.h
+*
+* \brief
+* FAULT IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_FAULT_H_
+#define _CYIP_FAULT_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FAULT
+*******************************************************************************/
+
+#define FAULT_STRUCT_SECTION_SIZE 0x00000100UL
+#define FAULT_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Fault structure (FAULT_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Fault control */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */
+ __IM uint32_t DATA[4]; /*!< 0x00000010 Fault data */
+ __IM uint32_t RESERVED1[8];
+ __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */
+ __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */
+ __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */
+ __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */
+ __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */
+ __IM uint32_t RESERVED3[25];
+ __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */
+ __IM uint32_t RESERVED4[12];
+} FAULT_STRUCT_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Fault structures (FAULT)
+ */
+typedef struct {
+ FAULT_STRUCT_Type STRUCT[4]; /*!< 0x00000000 Fault structure */
+} FAULT_Type; /*!< Size = 1024 (0x400) */
+
+
+/* FAULT_STRUCT.CTL */
+#define FAULT_STRUCT_CTL_TR_EN_Pos 0UL
+#define FAULT_STRUCT_CTL_TR_EN_Msk 0x1UL
+#define FAULT_STRUCT_CTL_OUT_EN_Pos 1UL
+#define FAULT_STRUCT_CTL_OUT_EN_Msk 0x2UL
+#define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos 2UL
+#define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk 0x4UL
+/* FAULT_STRUCT.STATUS */
+#define FAULT_STRUCT_STATUS_IDX_Pos 0UL
+#define FAULT_STRUCT_STATUS_IDX_Msk 0x7FUL
+#define FAULT_STRUCT_STATUS_VALID_Pos 31UL
+#define FAULT_STRUCT_STATUS_VALID_Msk 0x80000000UL
+/* FAULT_STRUCT.DATA */
+#define FAULT_STRUCT_DATA_DATA_Pos 0UL
+#define FAULT_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING0 */
+#define FAULT_STRUCT_PENDING0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING1 */
+#define FAULT_STRUCT_PENDING1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.PENDING2 */
+#define FAULT_STRUCT_PENDING2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK0 */
+#define FAULT_STRUCT_MASK0_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK0_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK1 */
+#define FAULT_STRUCT_MASK1_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK1_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.MASK2 */
+#define FAULT_STRUCT_MASK2_SOURCE_Pos 0UL
+#define FAULT_STRUCT_MASK2_SOURCE_Msk 0xFFFFFFFFUL
+/* FAULT_STRUCT.INTR */
+#define FAULT_STRUCT_INTR_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_SET */
+#define FAULT_STRUCT_INTR_SET_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_SET_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASK */
+#define FAULT_STRUCT_INTR_MASK_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_MASK_FAULT_Msk 0x1UL
+/* FAULT_STRUCT.INTR_MASKED */
+#define FAULT_STRUCT_INTR_MASKED_FAULT_Pos 0UL
+#define FAULT_STRUCT_INTR_MASKED_FAULT_Msk 0x1UL
+
+
+#endif /* _CYIP_FAULT_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_flashc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,592 @@
+/***************************************************************************//**
+* \file cyip_flashc.h
+*
+* \brief
+* FLASHC IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_FLASHC_H_
+#define _CYIP_FLASHC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* FLASHC
+*******************************************************************************/
+
+#define FLASHC_FM_CTL_SECTION_SIZE 0x00001000UL
+#define FLASHC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Flash Macro Registers (FLASHC_FM_CTL)
+ */
+typedef struct {
+ __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */
+ __IM uint32_t GEOMETRY; /*!< 0x0000000C Regular flash geometry */
+ __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000010 Supervisory flash geometry */
+ __IOM uint32_t TIMER_CTL; /*!< 0x00000014 Timer control */
+ __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */
+ __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */
+ __IM uint32_t GEOMETRY_GEN; /*!< 0x00000020 N/A, DNU */
+ __IOM uint32_t TEST_CTL; /*!< 0x00000024 Test mode control */
+ __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wiat State control */
+ __IM uint32_t MONITOR_STATUS; /*!< 0x0000002C Monitor Status */
+ __IOM uint32_t SCRATCH_CTL; /*!< 0x00000030 Scratch Control */
+ __IOM uint32_t HV_CTL; /*!< 0x00000034 High voltage control */
+ __OM uint32_t ACLK_CTL; /*!< 0x00000038 Aclk control */
+ __IOM uint32_t INTR; /*!< 0x0000003C Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000040 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000044 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000048 Interrupt masked */
+ __OM uint32_t FM_HV_DATA_ALL; /*!< 0x0000004C Flash macro high Voltage page latches data (for all page
+ latches) */
+ __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */
+ __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */
+ __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext */
+ __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim, bdac. */
+ __OM uint32_t BOOKMARK; /*!< 0x00000060 Bookmark register - keeps the current FW HV seq */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */
+ __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Controll normal sectors 2,3 */
+ __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Controll normal sectors 4,5 */
+ __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Controll normal sectors 6,7 */
+ __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Controll special sectors 0,1 */
+ __IM uint32_t RESERVED1[27];
+ __IM uint32_t TM_CMPR[32]; /*!< 0x00000100 Do Not Use */
+ __IM uint32_t RESERVED2[416];
+ __IOM uint32_t FM_HV_DATA[256]; /*!< 0x00000800 Flash macro high Voltage page latches data */
+ __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */
+} FLASHC_FM_CTL_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Flash controller (FLASHC)
+ */
+typedef struct {
+ __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */
+ __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
+ __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t BIST_CTL; /*!< 0x00000100 BIST control */
+ __IOM uint32_t BIST_CMD; /*!< 0x00000104 BIST command */
+ __IOM uint32_t BIST_ADDR_START; /*!< 0x00000108 BIST address start register */
+ __IOM uint32_t BIST_DATA[8]; /*!< 0x0000010C BIST data register(s) */
+ __IM uint32_t BIST_DATA_ACT[8]; /*!< 0x0000012C BIST data actual register(s) */
+ __IM uint32_t BIST_DATA_EXP[8]; /*!< 0x0000014C BIST data expected register(s) */
+ __IM uint32_t BIST_ADDR; /*!< 0x0000016C BIST address register */
+ __IOM uint32_t BIST_STATUS; /*!< 0x00000170 BIST status register */
+ __IM uint32_t RESERVED1[163];
+ __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
+ __IOM uint32_t CM0_CA_CMD; /*!< 0x0000040C CM0+ cache command */
+ __IM uint32_t RESERVED2[12];
+ __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
+ __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
+ __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */
+ __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */
+ __IOM uint32_t CM4_CA_CMD; /*!< 0x0000048C CM4 cache command */
+ __IM uint32_t RESERVED4[12];
+ __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */
+ __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */
+ __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t CRYPTO_BUFF_CMD; /*!< 0x00000508 Cryptography buffer command */
+ __IM uint32_t RESERVED7[29];
+ __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t DW0_BUFF_CMD; /*!< 0x00000588 Datawire 0 buffer command */
+ __IM uint32_t RESERVED9[29];
+ __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t DW1_BUFF_CMD; /*!< 0x00000608 Datawire 1 buffer command */
+ __IM uint32_t RESERVED11[29];
+ __IOM uint32_t DAP_BUFF_CTL; /*!< 0x00000680 Debug access port buffer control */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t DAP_BUFF_CMD; /*!< 0x00000688 Debug access port buffer command */
+ __IM uint32_t RESERVED13[29];
+ __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t EXT_MS0_BUFF_CMD; /*!< 0x00000708 External master 0 buffer command */
+ __IM uint32_t RESERVED15[29];
+ __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t EXT_MS1_BUFF_CMD; /*!< 0x00000788 External master 1 buffer command */
+ __IM uint32_t RESERVED17[14877];
+ FLASHC_FM_CTL_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */
+} FLASHC_Type; /*!< Size = 65536 (0x10000) */
+
+
+/* FLASHC_FM_CTL.FM_CTL */
+#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Pos 0UL
+#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Msk 0xFUL
+#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Pos 8UL
+#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Msk 0x300UL
+#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Pos 16UL
+#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL
+#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Pos 24UL
+#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_FM_CTL_WR_EN_Pos 25UL
+#define FLASHC_FM_CTL_FM_CTL_WR_EN_Msk 0x2000000UL
+/* FLASHC_FM_CTL.STATUS */
+#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Pos 0UL
+#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Msk 0x1UL
+#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos 1UL
+#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
+#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos 2UL
+#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk 0x4UL
+#define FLASHC_FM_CTL_STATUS_TURBO_N_Pos 3UL
+#define FLASHC_FM_CTL_STATUS_TURBO_N_Msk 0x8UL
+#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos 4UL
+#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk 0x10UL
+#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos 5UL
+#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk 0x20UL
+/* FLASHC_FM_CTL.FM_ADDR */
+#define FLASHC_FM_CTL_FM_ADDR_RA_Pos 0UL
+#define FLASHC_FM_CTL_FM_ADDR_RA_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_FM_ADDR_BA_Pos 16UL
+#define FLASHC_FM_CTL_FM_ADDR_BA_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_FM_ADDR_AXA_Pos 24UL
+#define FLASHC_FM_CTL_FM_ADDR_AXA_Msk 0x1000000UL
+/* FLASHC_FM_CTL.GEOMETRY */
+#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos 0UL
+#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk 0xFUL
+#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos 4UL
+#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0UL
+#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos 8UL
+#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk 0xFFFF00UL
+#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos 24UL
+#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 0UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xFUL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 4UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 8UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFF00UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 24UL
+#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF000000UL
+/* FLASHC_FM_CTL.TIMER_CTL */
+#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos 0UL
+#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk 0xFFFFUL
+#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos 16UL
+#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk 0x10000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Pos 24UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos 25UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk 0x2000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
+#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos 29UL
+#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk 0x20000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos 30UL
+#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk 0x40000000UL
+#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos 31UL
+#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk 0x80000000UL
+/* FLASHC_FM_CTL.ANA_CTL0 */
+#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Pos 8UL
+#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Msk 0x700UL
+#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Pos 24UL
+#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Msk 0x1000000UL
+#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 27UL
+#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x8000000UL
+/* FLASHC_FM_CTL.ANA_CTL1 */
+#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Pos 0UL
+#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Msk 0xFFUL
+#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Pos 16UL
+#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Msk 0xF0000UL
+#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Pos 24UL
+#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Msk 0xF000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Pos 28UL
+#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Msk 0x10000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Pos 29UL
+#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Msk 0x20000000UL
+#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Pos 30UL
+#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Msk 0x40000000UL
+/* FLASHC_FM_CTL.GEOMETRY_GEN */
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Pos 1UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Msk 0x2UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Pos 2UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Msk 0x4UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Pos 3UL
+#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Msk 0x8UL
+/* FLASHC_FM_CTL.TEST_CTL */
+#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Pos 0UL
+#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Msk 0x1FUL
+#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Pos 8UL
+#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Msk 0x100UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Pos 9UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Msk 0x200UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Pos 10UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Msk 0x400UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Pos 11UL
+#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Msk 0x800UL
+#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Pos 16UL
+#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Msk 0x10000UL
+#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Pos 17UL
+#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Msk 0x20000UL
+#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Pos 18UL
+#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Msk 0x40000UL
+#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Pos 31UL
+#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Msk 0x80000000UL
+/* FLASHC_FM_CTL.WAIT_CTL */
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
+#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
+/* FLASHC_FM_CTL.MONITOR_STATUS */
+#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Pos 1UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Msk 0x2UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Pos 2UL
+#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Msk 0x4UL
+/* FLASHC_FM_CTL.SCRATCH_CTL */
+#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Pos 0UL
+#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.HV_CTL */
+#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Pos 0UL
+#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
+/* FLASHC_FM_CTL.ACLK_CTL */
+#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos 0UL
+#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR */
+#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_SET */
+#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASK */
+#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.INTR_MASKED */
+#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
+#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
+/* FLASHC_FM_CTL.FM_HV_DATA_ALL */
+#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.CAL_CTL0 */
+#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Msk 0xF0000UL
+/* FLASHC_FM_CTL.CAL_CTL1 */
+#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Msk 0xF0000UL
+/* FLASHC_FM_CTL.CAL_CTL2 */
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Msk 0xE0UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 8UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x1F00UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Pos 13UL
+#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Msk 0xE000UL
+#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Msk 0x10000UL
+#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Pos 17UL
+#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Msk 0x20000UL
+#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Pos 18UL
+#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Pos 19UL
+#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.CAL_CTL3 */
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos 0UL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
+#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Pos 5UL
+#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Msk 0x1E0UL
+#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Pos 9UL
+#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Msk 0x600UL
+#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Pos 11UL
+#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Msk 0x7800UL
+#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos 15UL
+#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk 0x8000UL
+#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos 16UL
+#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x30000UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Pos 18UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Msk 0x40000UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Pos 19UL
+#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Msk 0x80000UL
+/* FLASHC_FM_CTL.BOOKMARK */
+#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos 0UL
+#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.RED_CTL01 */
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL23 */
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk 0x1000000UL
+/* FLASHC_FM_CTL.RED_CTL45 */
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Msk 0x1UL
+#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Pos 1UL
+#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Msk 0x2UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Pos 2UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Msk 0x4UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Pos 3UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Msk 0x8UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Pos 4UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Msk 0x10UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Pos 5UL
+#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Msk 0x20UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Pos 6UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Msk 0x40UL
+#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Pos 7UL
+#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Msk 0x80UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Msk 0xFF0000UL
+/* FLASHC_FM_CTL.RED_CTL67 */
+#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Msk 0x1UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Pos 1UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Msk 0x2UL
+#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Pos 2UL
+#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Msk 0x4UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Pos 3UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Msk 0x8UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Pos 4UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Msk 0x10UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Pos 5UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Msk 0x20UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Pos 6UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Msk 0x40UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Pos 7UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Msk 0x80UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Msk 0xFF0000UL
+/* FLASHC_FM_CTL.RED_CTL_SM01 */
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Pos 8UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Pos 24UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Pos 30UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Msk 0x40000000UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Pos 31UL
+#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Msk 0x80000000UL
+/* FLASHC_FM_CTL.TM_CMPR */
+#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Pos 0UL
+#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Msk 0x1UL
+/* FLASHC_FM_CTL.FM_HV_DATA */
+#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Msk 0xFFFFFFFFUL
+/* FLASHC_FM_CTL.FM_MEM_DATA */
+#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos 0UL
+#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL
+
+
+/* FLASHC.FLASH_CTL */
+#define FLASHC_FLASH_CTL_MAIN_WS_Pos 0UL
+#define FLASHC_FLASH_CTL_MAIN_WS_Msk 0xFUL
+#define FLASHC_FLASH_CTL_REMAP_Pos 8UL
+#define FLASHC_FLASH_CTL_REMAP_Msk 0x100UL
+/* FLASHC.FLASH_PWR_CTL */
+#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
+#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
+/* FLASHC.FLASH_CMD */
+#define FLASHC_FLASH_CMD_INV_Pos 0UL
+#define FLASHC_FLASH_CMD_INV_Msk 0x1UL
+/* FLASHC.BIST_CTL */
+#define FLASHC_BIST_CTL_OPCODE_Pos 0UL
+#define FLASHC_BIST_CTL_OPCODE_Msk 0x3UL
+#define FLASHC_BIST_CTL_UP_Pos 2UL
+#define FLASHC_BIST_CTL_UP_Msk 0x4UL
+#define FLASHC_BIST_CTL_ROW_FIRST_Pos 3UL
+#define FLASHC_BIST_CTL_ROW_FIRST_Msk 0x8UL
+#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Pos 4UL
+#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Msk 0x10UL
+#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Pos 5UL
+#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Msk 0x20UL
+#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Pos 6UL
+#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Msk 0x40UL
+#define FLASHC_BIST_CTL_STOP_ON_ERROR_Pos 7UL
+#define FLASHC_BIST_CTL_STOP_ON_ERROR_Msk 0x80UL
+/* FLASHC.BIST_CMD */
+#define FLASHC_BIST_CMD_START_Pos 0UL
+#define FLASHC_BIST_CMD_START_Msk 0x1UL
+/* FLASHC.BIST_ADDR_START */
+#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Pos 0UL
+#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Msk 0xFFFFUL
+#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Pos 16UL
+#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Msk 0xFFFF0000UL
+/* FLASHC.BIST_DATA */
+#define FLASHC_BIST_DATA_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_DATA_ACT */
+#define FLASHC_BIST_DATA_ACT_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_ACT_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_DATA_EXP */
+#define FLASHC_BIST_DATA_EXP_DATA_Pos 0UL
+#define FLASHC_BIST_DATA_EXP_DATA_Msk 0xFFFFFFFFUL
+/* FLASHC.BIST_ADDR */
+#define FLASHC_BIST_ADDR_COL_ADDR_Pos 0UL
+#define FLASHC_BIST_ADDR_COL_ADDR_Msk 0xFFFFUL
+#define FLASHC_BIST_ADDR_ROW_ADDR_Pos 16UL
+#define FLASHC_BIST_ADDR_ROW_ADDR_Msk 0xFFFF0000UL
+/* FLASHC.BIST_STATUS */
+#define FLASHC_BIST_STATUS_FAIL_Pos 0UL
+#define FLASHC_BIST_STATUS_FAIL_Msk 0x1UL
+/* FLASHC.CM0_CA_CTL0 */
+#define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CM0_CA_CTL0_ENABLED_Pos 31UL
+#define FLASHC_CM0_CA_CTL0_ENABLED_Msk 0x80000000UL
+/* FLASHC.CM0_CA_CTL1 */
+#define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM0_CA_CTL2 */
+#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM0_CA_CMD */
+#define FLASHC_CM0_CA_CMD_INV_Pos 0UL
+#define FLASHC_CM0_CA_CMD_INV_Msk 0x1UL
+/* FLASHC.CM0_CA_STATUS0 */
+#define FLASHC_CM0_CA_STATUS0_VALID16_Pos 0UL
+#define FLASHC_CM0_CA_STATUS0_VALID16_Msk 0xFFFFUL
+/* FLASHC.CM0_CA_STATUS1 */
+#define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM0_CA_STATUS2 */
+#define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CM4_CA_CTL0 */
+#define FLASHC_CM4_CA_CTL0_WAY_Pos 16UL
+#define FLASHC_CM4_CA_CTL0_WAY_Msk 0x30000UL
+#define FLASHC_CM4_CA_CTL0_SET_ADDR_Pos 24UL
+#define FLASHC_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL
+#define FLASHC_CM4_CA_CTL0_PREF_EN_Pos 30UL
+#define FLASHC_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CM4_CA_CTL0_ENABLED_Pos 31UL
+#define FLASHC_CM4_CA_CTL0_ENABLED_Msk 0x80000000UL
+/* FLASHC.CM4_CA_CTL1 */
+#define FLASHC_CM4_CA_CTL1_PWR_MODE_Pos 0UL
+#define FLASHC_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL
+#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL
+#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
+/* FLASHC.CM4_CA_CTL2 */
+#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL
+#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
+/* FLASHC.CM4_CA_CMD */
+#define FLASHC_CM4_CA_CMD_INV_Pos 0UL
+#define FLASHC_CM4_CA_CMD_INV_Msk 0x1UL
+/* FLASHC.CM4_CA_STATUS0 */
+#define FLASHC_CM4_CA_STATUS0_VALID16_Pos 0UL
+#define FLASHC_CM4_CA_STATUS0_VALID16_Msk 0xFFFFUL
+/* FLASHC.CM4_CA_STATUS1 */
+#define FLASHC_CM4_CA_STATUS1_TAG_Pos 0UL
+#define FLASHC_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
+/* FLASHC.CM4_CA_STATUS2 */
+#define FLASHC_CM4_CA_STATUS2_LRU_Pos 0UL
+#define FLASHC_CM4_CA_STATUS2_LRU_Msk 0x3FUL
+/* FLASHC.CRYPTO_BUFF_CTL */
+#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.CRYPTO_BUFF_CMD */
+#define FLASHC_CRYPTO_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_CRYPTO_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DW0_BUFF_CTL */
+#define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DW0_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DW0_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DW0_BUFF_CMD */
+#define FLASHC_DW0_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DW0_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DW1_BUFF_CTL */
+#define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DW1_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DW1_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DW1_BUFF_CMD */
+#define FLASHC_DW1_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DW1_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.DAP_BUFF_CTL */
+#define FLASHC_DAP_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_DAP_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_DAP_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_DAP_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.DAP_BUFF_CMD */
+#define FLASHC_DAP_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_DAP_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.EXT_MS0_BUFF_CTL */
+#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.EXT_MS0_BUFF_CMD */
+#define FLASHC_EXT_MS0_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_EXT_MS0_BUFF_CMD_INV_Msk 0x1UL
+/* FLASHC.EXT_MS1_BUFF_CTL */
+#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL
+#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
+#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Pos 31UL
+#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Msk 0x80000000UL
+/* FLASHC.EXT_MS1_BUFF_CMD */
+#define FLASHC_EXT_MS1_BUFF_CMD_INV_Pos 0UL
+#define FLASHC_EXT_MS1_BUFF_CMD_INV_Msk 0x1UL
+
+
+#endif /* _CYIP_FLASHC_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_gpio.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,466 @@
+/***************************************************************************//**
+* \file cyip_gpio.h
+*
+* \brief
+* GPIO IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_GPIO_H_
+#define _CYIP_GPIO_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* GPIO
+*******************************************************************************/
+
+#define GPIO_PRT_SECTION_SIZE 0x00000080UL
+#define GPIO_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief GPIO port registers (GPIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t OUT; /*!< 0x00000000 Port output data register */
+ __IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data set register */
+ __IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data clear register */
+ __IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */
+ __IM uint32_t IN; /*!< 0x00000010 Port input state register */
+ __IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */
+ __IOM uint32_t INTR_CFG; /*!< 0x00000024 Port interrupt configuration register */
+ __IOM uint32_t CFG; /*!< 0x00000028 Port configuration register */
+ __IOM uint32_t CFG_IN; /*!< 0x0000002C Port input buffer configuration register */
+ __IOM uint32_t CFG_OUT; /*!< 0x00000030 Port output buffer configuration register */
+ __IOM uint32_t CFG_SIO; /*!< 0x00000034 Port SIO configuration register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CFG_IN_GPIO5V; /*!< 0x0000003C Port GPIO5V input buffer configuration register */
+ __IM uint32_t RESERVED1[16];
+} GPIO_PRT_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief GPIO port control/configuration (GPIO)
+ */
+typedef struct {
+ GPIO_PRT_Type PRT[128]; /*!< 0x00000000 GPIO port registers */
+ __IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
+ __IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
+ __IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
+ __IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
+ __IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
+ __IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
+ __IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
+ __IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
+ __IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
+} GPIO_Type; /*!< Size = 16420 (0x4024) */
+
+
+/* GPIO_PRT.OUT */
+#define GPIO_PRT_OUT_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_CLR */
+#define GPIO_PRT_OUT_CLR_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_CLR_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_CLR_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_CLR_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_CLR_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_CLR_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_CLR_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_CLR_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_CLR_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_CLR_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_CLR_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_CLR_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_CLR_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_CLR_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_CLR_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_CLR_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_SET */
+#define GPIO_PRT_OUT_SET_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_SET_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_SET_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_SET_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_SET_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_SET_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_SET_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_SET_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_SET_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_SET_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_SET_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_SET_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_SET_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_SET_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_SET_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_SET_OUT7_Msk 0x80UL
+/* GPIO_PRT.OUT_INV */
+#define GPIO_PRT_OUT_INV_OUT0_Pos 0UL
+#define GPIO_PRT_OUT_INV_OUT0_Msk 0x1UL
+#define GPIO_PRT_OUT_INV_OUT1_Pos 1UL
+#define GPIO_PRT_OUT_INV_OUT1_Msk 0x2UL
+#define GPIO_PRT_OUT_INV_OUT2_Pos 2UL
+#define GPIO_PRT_OUT_INV_OUT2_Msk 0x4UL
+#define GPIO_PRT_OUT_INV_OUT3_Pos 3UL
+#define GPIO_PRT_OUT_INV_OUT3_Msk 0x8UL
+#define GPIO_PRT_OUT_INV_OUT4_Pos 4UL
+#define GPIO_PRT_OUT_INV_OUT4_Msk 0x10UL
+#define GPIO_PRT_OUT_INV_OUT5_Pos 5UL
+#define GPIO_PRT_OUT_INV_OUT5_Msk 0x20UL
+#define GPIO_PRT_OUT_INV_OUT6_Pos 6UL
+#define GPIO_PRT_OUT_INV_OUT6_Msk 0x40UL
+#define GPIO_PRT_OUT_INV_OUT7_Pos 7UL
+#define GPIO_PRT_OUT_INV_OUT7_Msk 0x80UL
+/* GPIO_PRT.IN */
+#define GPIO_PRT_IN_IN0_Pos 0UL
+#define GPIO_PRT_IN_IN0_Msk 0x1UL
+#define GPIO_PRT_IN_IN1_Pos 1UL
+#define GPIO_PRT_IN_IN1_Msk 0x2UL
+#define GPIO_PRT_IN_IN2_Pos 2UL
+#define GPIO_PRT_IN_IN2_Msk 0x4UL
+#define GPIO_PRT_IN_IN3_Pos 3UL
+#define GPIO_PRT_IN_IN3_Msk 0x8UL
+#define GPIO_PRT_IN_IN4_Pos 4UL
+#define GPIO_PRT_IN_IN4_Msk 0x10UL
+#define GPIO_PRT_IN_IN5_Pos 5UL
+#define GPIO_PRT_IN_IN5_Msk 0x20UL
+#define GPIO_PRT_IN_IN6_Pos 6UL
+#define GPIO_PRT_IN_IN6_Msk 0x40UL
+#define GPIO_PRT_IN_IN7_Pos 7UL
+#define GPIO_PRT_IN_IN7_Msk 0x80UL
+#define GPIO_PRT_IN_FLT_IN_Pos 8UL
+#define GPIO_PRT_IN_FLT_IN_Msk 0x100UL
+/* GPIO_PRT.INTR */
+#define GPIO_PRT_INTR_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_FLT_EDGE_Msk 0x100UL
+#define GPIO_PRT_INTR_IN_IN0_Pos 16UL
+#define GPIO_PRT_INTR_IN_IN0_Msk 0x10000UL
+#define GPIO_PRT_INTR_IN_IN1_Pos 17UL
+#define GPIO_PRT_INTR_IN_IN1_Msk 0x20000UL
+#define GPIO_PRT_INTR_IN_IN2_Pos 18UL
+#define GPIO_PRT_INTR_IN_IN2_Msk 0x40000UL
+#define GPIO_PRT_INTR_IN_IN3_Pos 19UL
+#define GPIO_PRT_INTR_IN_IN3_Msk 0x80000UL
+#define GPIO_PRT_INTR_IN_IN4_Pos 20UL
+#define GPIO_PRT_INTR_IN_IN4_Msk 0x100000UL
+#define GPIO_PRT_INTR_IN_IN5_Pos 21UL
+#define GPIO_PRT_INTR_IN_IN5_Msk 0x200000UL
+#define GPIO_PRT_INTR_IN_IN6_Pos 22UL
+#define GPIO_PRT_INTR_IN_IN6_Msk 0x400000UL
+#define GPIO_PRT_INTR_IN_IN7_Pos 23UL
+#define GPIO_PRT_INTR_IN_IN7_Msk 0x800000UL
+#define GPIO_PRT_INTR_FLT_IN_IN_Pos 24UL
+#define GPIO_PRT_INTR_FLT_IN_IN_Msk 0x1000000UL
+/* GPIO_PRT.INTR_MASK */
+#define GPIO_PRT_INTR_MASK_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_MASK_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_MASK_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_MASK_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_MASK_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_MASK_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_MASK_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_MASK_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_MASK_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_MASK_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_MASK_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_MASK_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_MASK_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_MASK_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_MASK_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_MASK_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_MASKED */
+#define GPIO_PRT_INTR_MASKED_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_MASKED_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_MASKED_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_MASKED_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_MASKED_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_MASKED_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_MASKED_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_MASKED_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_MASKED_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_MASKED_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_MASKED_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_MASKED_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_MASKED_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_MASKED_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_MASKED_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_MASKED_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_SET */
+#define GPIO_PRT_INTR_SET_EDGE0_Pos 0UL
+#define GPIO_PRT_INTR_SET_EDGE0_Msk 0x1UL
+#define GPIO_PRT_INTR_SET_EDGE1_Pos 1UL
+#define GPIO_PRT_INTR_SET_EDGE1_Msk 0x2UL
+#define GPIO_PRT_INTR_SET_EDGE2_Pos 2UL
+#define GPIO_PRT_INTR_SET_EDGE2_Msk 0x4UL
+#define GPIO_PRT_INTR_SET_EDGE3_Pos 3UL
+#define GPIO_PRT_INTR_SET_EDGE3_Msk 0x8UL
+#define GPIO_PRT_INTR_SET_EDGE4_Pos 4UL
+#define GPIO_PRT_INTR_SET_EDGE4_Msk 0x10UL
+#define GPIO_PRT_INTR_SET_EDGE5_Pos 5UL
+#define GPIO_PRT_INTR_SET_EDGE5_Msk 0x20UL
+#define GPIO_PRT_INTR_SET_EDGE6_Pos 6UL
+#define GPIO_PRT_INTR_SET_EDGE6_Msk 0x40UL
+#define GPIO_PRT_INTR_SET_EDGE7_Pos 7UL
+#define GPIO_PRT_INTR_SET_EDGE7_Msk 0x80UL
+#define GPIO_PRT_INTR_SET_FLT_EDGE_Pos 8UL
+#define GPIO_PRT_INTR_SET_FLT_EDGE_Msk 0x100UL
+/* GPIO_PRT.INTR_CFG */
+#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos 0UL
+#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk 0x3UL
+#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos 2UL
+#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk 0xCUL
+#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos 4UL
+#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk 0x30UL
+#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos 6UL
+#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
+#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos 8UL
+#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk 0x300UL
+#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos 10UL
+#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
+#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos 12UL
+#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
+#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos 14UL
+#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
+#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
+#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
+#define GPIO_PRT_INTR_CFG_FLT_SEL_Pos 18UL
+#define GPIO_PRT_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
+/* GPIO_PRT.CFG */
+#define GPIO_PRT_CFG_DRIVE_MODE0_Pos 0UL
+#define GPIO_PRT_CFG_DRIVE_MODE0_Msk 0x7UL
+#define GPIO_PRT_CFG_IN_EN0_Pos 3UL
+#define GPIO_PRT_CFG_IN_EN0_Msk 0x8UL
+#define GPIO_PRT_CFG_DRIVE_MODE1_Pos 4UL
+#define GPIO_PRT_CFG_DRIVE_MODE1_Msk 0x70UL
+#define GPIO_PRT_CFG_IN_EN1_Pos 7UL
+#define GPIO_PRT_CFG_IN_EN1_Msk 0x80UL
+#define GPIO_PRT_CFG_DRIVE_MODE2_Pos 8UL
+#define GPIO_PRT_CFG_DRIVE_MODE2_Msk 0x700UL
+#define GPIO_PRT_CFG_IN_EN2_Pos 11UL
+#define GPIO_PRT_CFG_IN_EN2_Msk 0x800UL
+#define GPIO_PRT_CFG_DRIVE_MODE3_Pos 12UL
+#define GPIO_PRT_CFG_DRIVE_MODE3_Msk 0x7000UL
+#define GPIO_PRT_CFG_IN_EN3_Pos 15UL
+#define GPIO_PRT_CFG_IN_EN3_Msk 0x8000UL
+#define GPIO_PRT_CFG_DRIVE_MODE4_Pos 16UL
+#define GPIO_PRT_CFG_DRIVE_MODE4_Msk 0x70000UL
+#define GPIO_PRT_CFG_IN_EN4_Pos 19UL
+#define GPIO_PRT_CFG_IN_EN4_Msk 0x80000UL
+#define GPIO_PRT_CFG_DRIVE_MODE5_Pos 20UL
+#define GPIO_PRT_CFG_DRIVE_MODE5_Msk 0x700000UL
+#define GPIO_PRT_CFG_IN_EN5_Pos 23UL
+#define GPIO_PRT_CFG_IN_EN5_Msk 0x800000UL
+#define GPIO_PRT_CFG_DRIVE_MODE6_Pos 24UL
+#define GPIO_PRT_CFG_DRIVE_MODE6_Msk 0x7000000UL
+#define GPIO_PRT_CFG_IN_EN6_Pos 27UL
+#define GPIO_PRT_CFG_IN_EN6_Msk 0x8000000UL
+#define GPIO_PRT_CFG_DRIVE_MODE7_Pos 28UL
+#define GPIO_PRT_CFG_DRIVE_MODE7_Msk 0x70000000UL
+#define GPIO_PRT_CFG_IN_EN7_Pos 31UL
+#define GPIO_PRT_CFG_IN_EN7_Msk 0x80000000UL
+/* GPIO_PRT.CFG_IN */
+#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos 0UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos 1UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos 2UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos 3UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos 4UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos 5UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos 6UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos 7UL
+#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
+/* GPIO_PRT.CFG_OUT */
+#define GPIO_PRT_CFG_OUT_SLOW0_Pos 0UL
+#define GPIO_PRT_CFG_OUT_SLOW0_Msk 0x1UL
+#define GPIO_PRT_CFG_OUT_SLOW1_Pos 1UL
+#define GPIO_PRT_CFG_OUT_SLOW1_Msk 0x2UL
+#define GPIO_PRT_CFG_OUT_SLOW2_Pos 2UL
+#define GPIO_PRT_CFG_OUT_SLOW2_Msk 0x4UL
+#define GPIO_PRT_CFG_OUT_SLOW3_Pos 3UL
+#define GPIO_PRT_CFG_OUT_SLOW3_Msk 0x8UL
+#define GPIO_PRT_CFG_OUT_SLOW4_Pos 4UL
+#define GPIO_PRT_CFG_OUT_SLOW4_Msk 0x10UL
+#define GPIO_PRT_CFG_OUT_SLOW5_Pos 5UL
+#define GPIO_PRT_CFG_OUT_SLOW5_Msk 0x20UL
+#define GPIO_PRT_CFG_OUT_SLOW6_Pos 6UL
+#define GPIO_PRT_CFG_OUT_SLOW6_Msk 0x40UL
+#define GPIO_PRT_CFG_OUT_SLOW7_Pos 7UL
+#define GPIO_PRT_CFG_OUT_SLOW7_Msk 0x80UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos 16UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos 18UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos 20UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos 22UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos 24UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos 26UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos 28UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos 30UL
+#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
+/* GPIO_PRT.CFG_SIO */
+#define GPIO_PRT_CFG_SIO_VREG_EN01_Pos 0UL
+#define GPIO_PRT_CFG_SIO_VREG_EN01_Msk 0x1UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos 1UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk 0x2UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos 2UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos 3UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk 0x18UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos 5UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk 0xE0UL
+#define GPIO_PRT_CFG_SIO_VREG_EN23_Pos 8UL
+#define GPIO_PRT_CFG_SIO_VREG_EN23_Msk 0x100UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos 9UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk 0x200UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos 10UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos 11UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk 0x1800UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos 13UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk 0xE000UL
+#define GPIO_PRT_CFG_SIO_VREG_EN45_Pos 16UL
+#define GPIO_PRT_CFG_SIO_VREG_EN45_Msk 0x10000UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos 17UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos 18UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos 19UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk 0x180000UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos 21UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
+#define GPIO_PRT_CFG_SIO_VREG_EN67_Pos 24UL
+#define GPIO_PRT_CFG_SIO_VREG_EN67_Msk 0x1000000UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos 25UL
+#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos 26UL
+#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos 27UL
+#define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos 29UL
+#define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
+/* GPIO_PRT.CFG_IN_GPIO5V */
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Pos 0UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Msk 0x1UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Pos 1UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Msk 0x2UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Pos 2UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Msk 0x4UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Pos 3UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Msk 0x8UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Pos 4UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Msk 0x10UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Pos 5UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Msk 0x20UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Pos 6UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Msk 0x40UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Pos 7UL
+#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Msk 0x80UL
+
+
+/* GPIO.INTR_CAUSE0 */
+#define GPIO_INTR_CAUSE0_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE1 */
+#define GPIO_INTR_CAUSE1_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE2 */
+#define GPIO_INTR_CAUSE2_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.INTR_CAUSE3 */
+#define GPIO_INTR_CAUSE3_PORT_INT_Pos 0UL
+#define GPIO_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
+/* GPIO.VDD_ACTIVE */
+#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR */
+#define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASK */
+#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_MASKED */
+#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
+/* GPIO.VDD_INTR_SET */
+#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
+#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
+#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
+#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
+#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
+#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_GPIO_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_headers.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,30 @@ +/***************************************************************************//** +* \file cyip_headers.h +* +* \brief +* Common header file to be included by all IP definition headers +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _CYIP_HEADERS_H_ +#define _CYIP_HEADERS_H_ + +#include <stdint.h> + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) +#include "core_cm0plus.h" +#else +#include "core_cm4.h" +#endif + +#endif /* _CYIP_HEADERS_H_ */ + + +/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_hsiom.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,86 @@
+/***************************************************************************//**
+* \file cyip_hsiom.h
+*
+* \brief
+* HSIOM IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_HSIOM_H_
+#define _CYIP_HSIOM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* HSIOM
+*******************************************************************************/
+
+#define HSIOM_PRT_SECTION_SIZE 0x00000010UL
+#define HSIOM_SECTION_SIZE 0x00004000UL
+
+/**
+ * \brief HSIOM port registers (HSIOM_PRT)
+ */
+typedef struct {
+ __IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
+ __IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
+ __IM uint32_t RESERVED[2];
+} HSIOM_PRT_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * \brief High Speed IO Matrix (HSIOM) (HSIOM)
+ */
+typedef struct {
+ HSIOM_PRT_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
+ __IM uint32_t RESERVED[1536];
+ __IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
+} HSIOM_Type; /*!< Size = 8448 (0x2100) */
+
+
+/* HSIOM_PRT.PORT_SEL0 */
+#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL
+#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL
+#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL
+#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL
+#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL
+#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
+/* HSIOM_PRT.PORT_SEL1 */
+#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL
+#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL
+#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL
+#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
+#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL
+#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
+#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL
+#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
+
+
+/* HSIOM.AMUX_SPLIT_CTL */
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
+#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
+
+
+#endif /* _CYIP_HSIOM_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_i2s.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,278 @@
+/***************************************************************************//**
+* \file cyip_i2s.h
+*
+* \brief
+* I2S IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_I2S_H_
+#define _CYIP_I2S_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* I2S
+*******************************************************************************/
+
+#define I2S_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief I2S registers (I2S)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t CMD; /*!< 0x00000020 Command */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
+ __IM uint32_t RESERVED3[15];
+ __IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */
+ __IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */
+ __IM uint32_t RESERVED4[6];
+ __IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */
+ __IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */
+ __IM uint32_t RESERVED5[86];
+ __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */
+ __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */
+ __IM uint32_t RESERVED6[61];
+ __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
+ __IM uint32_t RESERVED7[764];
+ __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
+} I2S_Type; /*!< Size = 3856 (0xF10) */
+
+
+/* I2S.CTL */
+#define I2S_CTL_TX_ENABLED_Pos 30UL
+#define I2S_CTL_TX_ENABLED_Msk 0x40000000UL
+#define I2S_CTL_RX_ENABLED_Pos 31UL
+#define I2S_CTL_RX_ENABLED_Msk 0x80000000UL
+/* I2S.CLOCK_CTL */
+#define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL
+#define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL
+#define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL
+#define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL
+/* I2S.CMD */
+#define I2S_CMD_TX_START_Pos 0UL
+#define I2S_CMD_TX_START_Msk 0x1UL
+#define I2S_CMD_TX_PAUSE_Pos 8UL
+#define I2S_CMD_TX_PAUSE_Msk 0x100UL
+#define I2S_CMD_RX_START_Pos 16UL
+#define I2S_CMD_RX_START_Msk 0x10000UL
+/* I2S.TR_CTL */
+#define I2S_TR_CTL_TX_REQ_EN_Pos 0UL
+#define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL
+#define I2S_TR_CTL_RX_REQ_EN_Pos 16UL
+#define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL
+/* I2S.TX_CTL */
+#define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL
+#define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL
+#define I2S_TX_CTL_CH_NR_Pos 4UL
+#define I2S_TX_CTL_CH_NR_Msk 0x70UL
+#define I2S_TX_CTL_MS_Pos 7UL
+#define I2S_TX_CTL_MS_Msk 0x80UL
+#define I2S_TX_CTL_I2S_MODE_Pos 8UL
+#define I2S_TX_CTL_I2S_MODE_Msk 0x300UL
+#define I2S_TX_CTL_WS_PULSE_Pos 10UL
+#define I2S_TX_CTL_WS_PULSE_Msk 0x400UL
+#define I2S_TX_CTL_OVHDATA_Pos 12UL
+#define I2S_TX_CTL_OVHDATA_Msk 0x1000UL
+#define I2S_TX_CTL_WD_EN_Pos 13UL
+#define I2S_TX_CTL_WD_EN_Msk 0x2000UL
+#define I2S_TX_CTL_CH_LEN_Pos 16UL
+#define I2S_TX_CTL_CH_LEN_Msk 0x70000UL
+#define I2S_TX_CTL_WORD_LEN_Pos 20UL
+#define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL
+#define I2S_TX_CTL_SCKO_POL_Pos 24UL
+#define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL
+#define I2S_TX_CTL_SCKI_POL_Pos 25UL
+#define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL
+/* I2S.TX_WATCHDOG */
+#define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL
+#define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
+/* I2S.RX_CTL */
+#define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL
+#define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL
+#define I2S_RX_CTL_CH_NR_Pos 4UL
+#define I2S_RX_CTL_CH_NR_Msk 0x70UL
+#define I2S_RX_CTL_MS_Pos 7UL
+#define I2S_RX_CTL_MS_Msk 0x80UL
+#define I2S_RX_CTL_I2S_MODE_Pos 8UL
+#define I2S_RX_CTL_I2S_MODE_Msk 0x300UL
+#define I2S_RX_CTL_WS_PULSE_Pos 10UL
+#define I2S_RX_CTL_WS_PULSE_Msk 0x400UL
+#define I2S_RX_CTL_WD_EN_Pos 13UL
+#define I2S_RX_CTL_WD_EN_Msk 0x2000UL
+#define I2S_RX_CTL_CH_LEN_Pos 16UL
+#define I2S_RX_CTL_CH_LEN_Msk 0x70000UL
+#define I2S_RX_CTL_WORD_LEN_Pos 20UL
+#define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL
+#define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL
+#define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL
+#define I2S_RX_CTL_SCKO_POL_Pos 24UL
+#define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL
+#define I2S_RX_CTL_SCKI_POL_Pos 25UL
+#define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL
+/* I2S.RX_WATCHDOG */
+#define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL
+#define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
+/* I2S.TX_FIFO_CTL */
+#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL
+#define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL
+#define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* I2S.TX_FIFO_STATUS */
+#define I2S_TX_FIFO_STATUS_USED_Pos 0UL
+#define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* I2S.TX_FIFO_WR */
+#define I2S_TX_FIFO_WR_DATA_Pos 0UL
+#define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
+/* I2S.RX_FIFO_CTL */
+#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL
+#define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL
+#define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* I2S.RX_FIFO_STATUS */
+#define I2S_RX_FIFO_STATUS_USED_Pos 0UL
+#define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* I2S.RX_FIFO_RD */
+#define I2S_RX_FIFO_RD_DATA_Pos 0UL
+#define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* I2S.RX_FIFO_RD_SILENT */
+#define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* I2S.INTR */
+#define I2S_INTR_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_TX_EMPTY_Pos 4UL
+#define I2S_INTR_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_TX_WD_Pos 8UL
+#define I2S_INTR_TX_WD_Msk 0x100UL
+#define I2S_INTR_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_RX_FULL_Pos 19UL
+#define I2S_INTR_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_RX_WD_Pos 24UL
+#define I2S_INTR_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_SET */
+#define I2S_INTR_SET_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_SET_TX_EMPTY_Pos 4UL
+#define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_SET_TX_WD_Pos 8UL
+#define I2S_INTR_SET_TX_WD_Msk 0x100UL
+#define I2S_INTR_SET_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_SET_RX_FULL_Pos 19UL
+#define I2S_INTR_SET_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_SET_RX_WD_Pos 24UL
+#define I2S_INTR_SET_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_MASK */
+#define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_MASK_TX_EMPTY_Pos 4UL
+#define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_MASK_TX_WD_Pos 8UL
+#define I2S_INTR_MASK_TX_WD_Msk 0x100UL
+#define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_MASK_RX_FULL_Pos 19UL
+#define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_MASK_RX_WD_Pos 24UL
+#define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL
+/* I2S.INTR_MASKED */
+#define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL
+#define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL
+#define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL
+#define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL
+#define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL
+#define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL
+#define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL
+#define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL
+#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL
+#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL
+#define I2S_INTR_MASKED_TX_WD_Pos 8UL
+#define I2S_INTR_MASKED_TX_WD_Msk 0x100UL
+#define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL
+#define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
+#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
+#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
+#define I2S_INTR_MASKED_RX_FULL_Pos 19UL
+#define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL
+#define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL
+#define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
+#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
+#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
+#define I2S_INTR_MASKED_RX_WD_Pos 24UL
+#define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL
+
+
+#endif /* _CYIP_I2S_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_ipc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,121 @@
+/***************************************************************************//**
+* \file cyip_ipc.h
+*
+* \brief
+* IPC IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_IPC_H_
+#define _CYIP_IPC_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* IPC
+*******************************************************************************/
+
+#define IPC_STRUCT_SECTION_SIZE 0x00000020UL
+#define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL
+#define IPC_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief IPC structure (IPC_STRUCT)
+ */
+typedef struct {
+ __IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */
+ __OM uint32_t RELEASE; /*!< 0x00000004 IPC release */
+ __OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */
+ __IOM uint32_t DATA; /*!< 0x0000000C IPC data */
+ __IM uint32_t LOCK_STATUS; /*!< 0x00000010 IPC lock status */
+ __IM uint32_t RESERVED[3];
+} IPC_STRUCT_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC interrupt structure (IPC_INTR_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t INTR; /*!< 0x00000000 Interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */
+ __IM uint32_t RESERVED[4];
+} IPC_INTR_STRUCT_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief IPC (IPC)
+ */
+typedef struct {
+ IPC_STRUCT_Type STRUCT[16]; /*!< 0x00000000 IPC structure */
+ __IM uint32_t RESERVED[896];
+ IPC_INTR_STRUCT_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
+} IPC_Type; /*!< Size = 4608 (0x1200) */
+
+
+/* IPC_STRUCT.ACQUIRE */
+#define IPC_STRUCT_ACQUIRE_P_Pos 0UL
+#define IPC_STRUCT_ACQUIRE_P_Msk 0x1UL
+#define IPC_STRUCT_ACQUIRE_NS_Pos 1UL
+#define IPC_STRUCT_ACQUIRE_NS_Msk 0x2UL
+#define IPC_STRUCT_ACQUIRE_PC_Pos 4UL
+#define IPC_STRUCT_ACQUIRE_PC_Msk 0xF0UL
+#define IPC_STRUCT_ACQUIRE_MS_Pos 8UL
+#define IPC_STRUCT_ACQUIRE_MS_Msk 0xF00UL
+#define IPC_STRUCT_ACQUIRE_SUCCESS_Pos 31UL
+#define IPC_STRUCT_ACQUIRE_SUCCESS_Msk 0x80000000UL
+/* IPC_STRUCT.RELEASE */
+#define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos 0UL
+#define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
+/* IPC_STRUCT.NOTIFY */
+#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos 0UL
+#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
+/* IPC_STRUCT.DATA */
+#define IPC_STRUCT_DATA_DATA_Pos 0UL
+#define IPC_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
+/* IPC_STRUCT.LOCK_STATUS */
+#define IPC_STRUCT_LOCK_STATUS_P_Pos 0UL
+#define IPC_STRUCT_LOCK_STATUS_P_Msk 0x1UL
+#define IPC_STRUCT_LOCK_STATUS_NS_Pos 1UL
+#define IPC_STRUCT_LOCK_STATUS_NS_Msk 0x2UL
+#define IPC_STRUCT_LOCK_STATUS_PC_Pos 4UL
+#define IPC_STRUCT_LOCK_STATUS_PC_Msk 0xF0UL
+#define IPC_STRUCT_LOCK_STATUS_MS_Pos 8UL
+#define IPC_STRUCT_LOCK_STATUS_MS_Msk 0xF00UL
+#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos 31UL
+#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
+
+
+/* IPC_INTR_STRUCT.INTR */
+#define IPC_INTR_STRUCT_INTR_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_SET */
+#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASK */
+#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
+/* IPC_INTR_STRUCT.INTR_MASKED */
+#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos 0UL
+#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk 0xFFFFUL
+#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos 16UL
+#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
+
+
+#endif /* _CYIP_IPC_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_lcd.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,90 @@
+/***************************************************************************//**
+* \file cyip_lcd.h
+*
+* \brief
+* LCD IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_LCD_H_
+#define _CYIP_LCD_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* LCD
+*******************************************************************************/
+
+#define LCD_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief LCD Controller Block (LCD)
+ */
+typedef struct {
+ __IM uint32_t ID; /*!< 0x00000000 ID & Revision */
+ __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */
+ __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */
+} LCD_Type; /*!< Size = 1056 (0x420) */
+
+
+/* LCD.ID */
+#define LCD_ID_ID_Pos 0UL
+#define LCD_ID_ID_Msk 0xFFFFUL
+#define LCD_ID_REVISION_Pos 16UL
+#define LCD_ID_REVISION_Msk 0xFFFF0000UL
+/* LCD.DIVIDER */
+#define LCD_DIVIDER_SUBFR_DIV_Pos 0UL
+#define LCD_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL
+#define LCD_DIVIDER_DEAD_DIV_Pos 16UL
+#define LCD_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL
+/* LCD.CONTROL */
+#define LCD_CONTROL_LS_EN_Pos 0UL
+#define LCD_CONTROL_LS_EN_Msk 0x1UL
+#define LCD_CONTROL_HS_EN_Pos 1UL
+#define LCD_CONTROL_HS_EN_Msk 0x2UL
+#define LCD_CONTROL_LCD_MODE_Pos 2UL
+#define LCD_CONTROL_LCD_MODE_Msk 0x4UL
+#define LCD_CONTROL_TYPE_Pos 3UL
+#define LCD_CONTROL_TYPE_Msk 0x8UL
+#define LCD_CONTROL_OP_MODE_Pos 4UL
+#define LCD_CONTROL_OP_MODE_Msk 0x10UL
+#define LCD_CONTROL_BIAS_Pos 5UL
+#define LCD_CONTROL_BIAS_Msk 0x60UL
+#define LCD_CONTROL_COM_NUM_Pos 8UL
+#define LCD_CONTROL_COM_NUM_Msk 0xF00UL
+#define LCD_CONTROL_LS_EN_STAT_Pos 31UL
+#define LCD_CONTROL_LS_EN_STAT_Msk 0x80000000UL
+/* LCD.DATA0 */
+#define LCD_DATA0_DATA_Pos 0UL
+#define LCD_DATA0_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA1 */
+#define LCD_DATA1_DATA_Pos 0UL
+#define LCD_DATA1_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA2 */
+#define LCD_DATA2_DATA_Pos 0UL
+#define LCD_DATA2_DATA_Msk 0xFFFFFFFFUL
+/* LCD.DATA3 */
+#define LCD_DATA3_DATA_Pos 0UL
+#define LCD_DATA3_DATA_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_LCD_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_lpcomp.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,169 @@
+/***************************************************************************//**
+* \file cyip_lpcomp.h
+*
+* \brief
+* LPCOMP IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_LPCOMP_H_
+#define _CYIP_LPCOMP_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* LPCOMP
+*******************************************************************************/
+
+#define LPCOMP_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Low Power Comparators (LPCOMP)
+ */
+typedef struct {
+ __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */
+ __IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */
+ __IM uint32_t RESERVED1[8];
+ __IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */
+ __IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */
+ __IM uint32_t RESERVED4[3];
+ __IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */
+ __IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */
+} LPCOMP_Type; /*!< Size = 152 (0x98) */
+
+
+/* LPCOMP.CONFIG */
+#define LPCOMP_CONFIG_LPREF_EN_Pos 30UL
+#define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL
+#define LPCOMP_CONFIG_ENABLED_Pos 31UL
+#define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL
+/* LPCOMP.STATUS */
+#define LPCOMP_STATUS_OUT0_Pos 0UL
+#define LPCOMP_STATUS_OUT0_Msk 0x1UL
+#define LPCOMP_STATUS_OUT1_Pos 16UL
+#define LPCOMP_STATUS_OUT1_Msk 0x10000UL
+/* LPCOMP.INTR */
+#define LPCOMP_INTR_COMP0_Pos 0UL
+#define LPCOMP_INTR_COMP0_Msk 0x1UL
+#define LPCOMP_INTR_COMP1_Pos 1UL
+#define LPCOMP_INTR_COMP1_Msk 0x2UL
+/* LPCOMP.INTR_SET */
+#define LPCOMP_INTR_SET_COMP0_Pos 0UL
+#define LPCOMP_INTR_SET_COMP0_Msk 0x1UL
+#define LPCOMP_INTR_SET_COMP1_Pos 1UL
+#define LPCOMP_INTR_SET_COMP1_Msk 0x2UL
+/* LPCOMP.INTR_MASK */
+#define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL
+#define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL
+#define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL
+#define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL
+/* LPCOMP.INTR_MASKED */
+#define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL
+#define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
+#define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL
+#define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
+/* LPCOMP.CMP0_CTRL */
+#define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL
+#define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL
+#define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL
+#define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL
+#define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL
+#define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL
+#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL
+#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL
+#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL
+#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL
+/* LPCOMP.CMP0_SW */
+#define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL
+#define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL
+#define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL
+#define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL
+#define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL
+#define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL
+#define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL
+#define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL
+#define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL
+#define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL
+#define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL
+#define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL
+#define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL
+#define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL
+/* LPCOMP.CMP0_SW_CLEAR */
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL
+#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL
+/* LPCOMP.CMP1_CTRL */
+#define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL
+#define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL
+#define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL
+#define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL
+#define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL
+#define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL
+#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL
+#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL
+#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL
+#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL
+/* LPCOMP.CMP1_SW */
+#define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL
+#define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL
+#define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL
+#define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL
+#define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL
+#define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL
+#define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL
+#define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL
+#define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL
+#define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL
+#define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL
+#define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL
+#define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL
+#define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL
+/* LPCOMP.CMP1_SW_CLEAR */
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL
+#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL
+
+
+#endif /* _CYIP_LPCOMP_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_pass.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,128 @@
+/***************************************************************************//**
+* \file cyip_pass.h
+*
+* \brief
+* PASS IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_PASS_H_
+#define _CYIP_PASS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PASS
+*******************************************************************************/
+
+#define PASS_AREF_SECTION_SIZE 0x00000100UL
+#define PASS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief AREF configuration (PASS_AREF)
+ */
+typedef struct {
+ __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */
+ __IM uint32_t RESERVED[63];
+} PASS_AREF_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief PASS top-level MMIO (DSABv2, INTR) (PASS)
+ */
+typedef struct {
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */
+ __IM uint32_t RESERVED[895];
+ PASS_AREF_Type AREF; /*!< 0x00000E00 AREF configuration */
+ __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */
+ __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */
+ __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 IZTAT Trim bits */
+ __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */
+ __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */
+ __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */
+} PASS_Type; /*!< Size = 3872 (0xF20) */
+
+
+/* PASS_AREF.AREF_CTRL */
+#define PASS_AREF_AREF_CTRL_AREF_MODE_Pos 0UL
+#define PASS_AREF_AREF_CTRL_AREF_MODE_Msk 0x1UL
+#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL
+#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL
+#define PASS_AREF_AREF_CTRL_AREF_RMB_Pos 4UL
+#define PASS_AREF_AREF_CTRL_AREF_RMB_Msk 0x70UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL
+#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL
+#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos 16UL
+#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL
+#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL
+#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL
+#define PASS_AREF_AREF_CTRL_VREF_SEL_Pos 20UL
+#define PASS_AREF_AREF_CTRL_VREF_SEL_Msk 0x300000UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL
+#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
+#define PASS_AREF_AREF_CTRL_ENABLED_Pos 31UL
+#define PASS_AREF_AREF_CTRL_ENABLED_Msk 0x80000000UL
+
+
+/* PASS.INTR_CAUSE */
+#define PASS_INTR_CAUSE_CTB0_INT_Pos 0UL
+#define PASS_INTR_CAUSE_CTB0_INT_Msk 0x1UL
+#define PASS_INTR_CAUSE_CTB1_INT_Pos 1UL
+#define PASS_INTR_CAUSE_CTB1_INT_Msk 0x2UL
+#define PASS_INTR_CAUSE_CTB2_INT_Pos 2UL
+#define PASS_INTR_CAUSE_CTB2_INT_Msk 0x4UL
+#define PASS_INTR_CAUSE_CTB3_INT_Pos 3UL
+#define PASS_INTR_CAUSE_CTB3_INT_Msk 0x8UL
+#define PASS_INTR_CAUSE_CTDAC0_INT_Pos 4UL
+#define PASS_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL
+#define PASS_INTR_CAUSE_CTDAC1_INT_Pos 5UL
+#define PASS_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL
+#define PASS_INTR_CAUSE_CTDAC2_INT_Pos 6UL
+#define PASS_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL
+#define PASS_INTR_CAUSE_CTDAC3_INT_Pos 7UL
+#define PASS_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL
+/* PASS.VREF_TRIM0 */
+#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL
+#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM1 */
+#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL
+#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM2 */
+#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL
+#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL
+/* PASS.VREF_TRIM3 */
+#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL
+#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL
+/* PASS.IZTAT_TRIM0 */
+#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL
+#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL
+/* PASS.IZTAT_TRIM1 */
+#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL
+#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL
+/* PASS.IPTAT_TRIM0 */
+#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL
+#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL
+#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL
+#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL
+/* PASS.ICTAT_TRIM0 */
+#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL
+#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL
+
+
+#endif /* _CYIP_PASS_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_pdm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,159 @@
+/***************************************************************************//**
+* \file cyip_pdm.h
+*
+* \brief
+* PDM IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_PDM_H_
+#define _CYIP_PDM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PDM
+*******************************************************************************/
+
+#define PDM_SECTION_SIZE 0x00001000UL
+
+/**
+ * \brief PDM registers (PDM)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
+ __IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */
+ __IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CMD; /*!< 0x00000020 Command */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
+ __IM uint32_t RESERVED3[175];
+ __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
+ __IM uint32_t RESERVED4[764];
+ __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
+} PDM_Type; /*!< Size = 3856 (0xF10) */
+
+
+/* PDM.CTL */
+#define PDM_CTL_PGA_R_Pos 0UL
+#define PDM_CTL_PGA_R_Msk 0xFUL
+#define PDM_CTL_PGA_L_Pos 8UL
+#define PDM_CTL_PGA_L_Msk 0xF00UL
+#define PDM_CTL_SOFT_MUTE_Pos 16UL
+#define PDM_CTL_SOFT_MUTE_Msk 0x10000UL
+#define PDM_CTL_STEP_SEL_Pos 17UL
+#define PDM_CTL_STEP_SEL_Msk 0x20000UL
+#define PDM_CTL_ENABLED_Pos 31UL
+#define PDM_CTL_ENABLED_Msk 0x80000000UL
+/* PDM.CLOCK_CTL */
+#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos 0UL
+#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk 0x3UL
+#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos 4UL
+#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk 0x30UL
+#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos 8UL
+#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk 0xF00UL
+#define PDM_CLOCK_CTL_SINC_RATE_Pos 16UL
+#define PDM_CLOCK_CTL_SINC_RATE_Msk 0x7F0000UL
+/* PDM.MODE_CTL */
+#define PDM_MODE_CTL_PCM_CH_SET_Pos 0UL
+#define PDM_MODE_CTL_PCM_CH_SET_Msk 0x3UL
+#define PDM_MODE_CTL_SWAP_LR_Pos 2UL
+#define PDM_MODE_CTL_SWAP_LR_Msk 0x4UL
+#define PDM_MODE_CTL_S_CYCLES_Pos 8UL
+#define PDM_MODE_CTL_S_CYCLES_Msk 0x700UL
+#define PDM_MODE_CTL_CKO_DELAY_Pos 16UL
+#define PDM_MODE_CTL_CKO_DELAY_Msk 0x70000UL
+#define PDM_MODE_CTL_HPF_GAIN_Pos 24UL
+#define PDM_MODE_CTL_HPF_GAIN_Msk 0xF000000UL
+#define PDM_MODE_CTL_HPF_EN_N_Pos 28UL
+#define PDM_MODE_CTL_HPF_EN_N_Msk 0x10000000UL
+/* PDM.DATA_CTL */
+#define PDM_DATA_CTL_WORD_LEN_Pos 0UL
+#define PDM_DATA_CTL_WORD_LEN_Msk 0x3UL
+#define PDM_DATA_CTL_BIT_EXTENSION_Pos 8UL
+#define PDM_DATA_CTL_BIT_EXTENSION_Msk 0x100UL
+/* PDM.CMD */
+#define PDM_CMD_STREAM_EN_Pos 0UL
+#define PDM_CMD_STREAM_EN_Msk 0x1UL
+/* PDM.TR_CTL */
+#define PDM_TR_CTL_RX_REQ_EN_Pos 16UL
+#define PDM_TR_CTL_RX_REQ_EN_Msk 0x10000UL
+/* PDM.RX_FIFO_CTL */
+#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
+#define PDM_RX_FIFO_CTL_CLEAR_Pos 16UL
+#define PDM_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
+#define PDM_RX_FIFO_CTL_FREEZE_Pos 17UL
+#define PDM_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
+/* PDM.RX_FIFO_STATUS */
+#define PDM_RX_FIFO_STATUS_USED_Pos 0UL
+#define PDM_RX_FIFO_STATUS_USED_Msk 0xFFUL
+#define PDM_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define PDM_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define PDM_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define PDM_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* PDM.RX_FIFO_RD */
+#define PDM_RX_FIFO_RD_DATA_Pos 0UL
+#define PDM_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
+/* PDM.RX_FIFO_RD_SILENT */
+#define PDM_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define PDM_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
+/* PDM.INTR */
+#define PDM_INTR_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_SET */
+#define PDM_INTR_SET_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_SET_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_SET_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_SET_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_SET_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_MASK */
+#define PDM_INTR_MASK_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_MASK_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_MASK_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
+/* PDM.INTR_MASKED */
+#define PDM_INTR_MASKED_RX_TRIGGER_Pos 16UL
+#define PDM_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
+#define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
+#define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
+#define PDM_INTR_MASKED_RX_OVERFLOW_Pos 21UL
+#define PDM_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
+#define PDM_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
+#define PDM_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
+
+
+#endif /* _CYIP_PDM_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_peri.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,480 @@
+/***************************************************************************//**
+* \file cyip_peri.h
+*
+* \brief
+* PERI IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_PERI_H_
+#define _CYIP_PERI_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PERI
+*******************************************************************************/
+
+#define PERI_GR_SECTION_SIZE 0x00000040UL
+#define PERI_TR_GR_SECTION_SIZE 0x00000200UL
+#define PERI_PPU_PR_SECTION_SIZE 0x00000040UL
+#define PERI_PPU_GR_SECTION_SIZE 0x00000040UL
+#define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL
+#define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL
+#define PERI_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Peripheral group structure (PERI_GR)
+ */
+typedef struct {
+ __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */
+ __IM uint32_t RESERVED[7];
+ __IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */
+ __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Trigger group (PERI_TR_GR)
+ */
+typedef struct {
+ __IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */
+} PERI_TR_GR_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief PPU structure with programmable address (PERI_PPU_PR)
+ */
+typedef struct {
+ __IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_PPU_PR_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_PPU_GR_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_PPU_SL_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG)
+ */
+typedef struct {
+ __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PERI_GR_PPU_RG_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Peripheral interconnect (PERI)
+ */
+typedef struct {
+ PERI_GR_Type GR[16]; /*!< 0x00000000 Peripheral group structure */
+ __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */
+ __IM uint32_t RESERVED[255];
+ __IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */
+ __IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */
+ __IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */
+ __IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */
+ __IM uint32_t RESERVED2[128];
+ __IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */
+ __IM uint32_t RESERVED3[1023];
+ PERI_TR_GR_Type TR_GR[16]; /*!< 0x00002000 Trigger group */
+ PERI_PPU_PR_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */
+ __IM uint32_t RESERVED4[512];
+ PERI_PPU_GR_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral
+ group */
+} PERI_Type; /*!< Size = 21504 (0x5400) */
+
+
+/* PERI_GR.CLOCK_CTL */
+#define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL
+#define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI_GR.SL_CTL */
+#define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL
+#define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL
+#define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL
+#define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL
+#define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL
+#define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL
+#define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL
+#define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL
+#define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL
+#define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL
+#define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL
+#define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL
+#define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL
+#define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL
+#define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL
+#define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL
+#define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL
+#define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL
+#define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL
+#define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL
+#define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL
+#define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL
+#define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL
+#define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL
+#define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL
+#define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL
+#define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL
+#define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL
+#define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL
+#define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL
+#define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL
+#define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL
+/* PERI_GR.TIMEOUT_CTL */
+#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos 0UL
+#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
+
+
+/* PERI_TR_GR.TR_OUT_CTL */
+#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos 0UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk 0xFFUL
+#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos 8UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk 0x100UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos 9UL
+#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk 0x200UL
+
+
+/* PERI_PPU_PR.ADDR0 */
+#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_PR_ADDR0_ADDR24_Pos 8UL
+#define PERI_PPU_PR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_PR.ATT0 */
+#define PERI_PPU_PR_ATT0_UR_Pos 0UL
+#define PERI_PPU_PR_ATT0_UR_Msk 0x1UL
+#define PERI_PPU_PR_ATT0_UW_Pos 1UL
+#define PERI_PPU_PR_ATT0_UW_Msk 0x2UL
+#define PERI_PPU_PR_ATT0_UX_Pos 2UL
+#define PERI_PPU_PR_ATT0_UX_Msk 0x4UL
+#define PERI_PPU_PR_ATT0_PR_Pos 3UL
+#define PERI_PPU_PR_ATT0_PR_Msk 0x8UL
+#define PERI_PPU_PR_ATT0_PW_Pos 4UL
+#define PERI_PPU_PR_ATT0_PW_Msk 0x10UL
+#define PERI_PPU_PR_ATT0_PX_Pos 5UL
+#define PERI_PPU_PR_ATT0_PX_Msk 0x20UL
+#define PERI_PPU_PR_ATT0_NS_Pos 6UL
+#define PERI_PPU_PR_ATT0_NS_Msk 0x40UL
+#define PERI_PPU_PR_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_PPU_PR_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_PR_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_PPU_PR_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_PR_ATT0_PC_MATCH_Pos 30UL
+#define PERI_PPU_PR_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_PR_ATT0_ENABLED_Pos 31UL
+#define PERI_PPU_PR_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_PPU_PR.ADDR1 */
+#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_PR_ADDR1_ADDR24_Pos 8UL
+#define PERI_PPU_PR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_PR.ATT1 */
+#define PERI_PPU_PR_ATT1_UR_Pos 0UL
+#define PERI_PPU_PR_ATT1_UR_Msk 0x1UL
+#define PERI_PPU_PR_ATT1_UW_Pos 1UL
+#define PERI_PPU_PR_ATT1_UW_Msk 0x2UL
+#define PERI_PPU_PR_ATT1_UX_Pos 2UL
+#define PERI_PPU_PR_ATT1_UX_Msk 0x4UL
+#define PERI_PPU_PR_ATT1_PR_Pos 3UL
+#define PERI_PPU_PR_ATT1_PR_Msk 0x8UL
+#define PERI_PPU_PR_ATT1_PW_Pos 4UL
+#define PERI_PPU_PR_ATT1_PW_Msk 0x10UL
+#define PERI_PPU_PR_ATT1_PX_Pos 5UL
+#define PERI_PPU_PR_ATT1_PX_Msk 0x20UL
+#define PERI_PPU_PR_ATT1_NS_Pos 6UL
+#define PERI_PPU_PR_ATT1_NS_Msk 0x40UL
+#define PERI_PPU_PR_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_PPU_PR_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_PR_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_PPU_PR_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_PR_ATT1_PC_MATCH_Pos 30UL
+#define PERI_PPU_PR_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_PR_ATT1_ENABLED_Pos 31UL
+#define PERI_PPU_PR_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_PPU_GR.ADDR0 */
+#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_GR_ADDR0_ADDR24_Pos 8UL
+#define PERI_PPU_GR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_GR.ATT0 */
+#define PERI_PPU_GR_ATT0_UR_Pos 0UL
+#define PERI_PPU_GR_ATT0_UR_Msk 0x1UL
+#define PERI_PPU_GR_ATT0_UW_Pos 1UL
+#define PERI_PPU_GR_ATT0_UW_Msk 0x2UL
+#define PERI_PPU_GR_ATT0_UX_Pos 2UL
+#define PERI_PPU_GR_ATT0_UX_Msk 0x4UL
+#define PERI_PPU_GR_ATT0_PR_Pos 3UL
+#define PERI_PPU_GR_ATT0_PR_Msk 0x8UL
+#define PERI_PPU_GR_ATT0_PW_Pos 4UL
+#define PERI_PPU_GR_ATT0_PW_Msk 0x10UL
+#define PERI_PPU_GR_ATT0_PX_Pos 5UL
+#define PERI_PPU_GR_ATT0_PX_Msk 0x20UL
+#define PERI_PPU_GR_ATT0_NS_Pos 6UL
+#define PERI_PPU_GR_ATT0_NS_Msk 0x40UL
+#define PERI_PPU_GR_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_PPU_GR_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_GR_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_PPU_GR_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_GR_ATT0_PC_MATCH_Pos 30UL
+#define PERI_PPU_GR_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_GR_ATT0_ENABLED_Pos 31UL
+#define PERI_PPU_GR_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_PPU_GR.ADDR1 */
+#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_PPU_GR_ADDR1_ADDR24_Pos 8UL
+#define PERI_PPU_GR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_PPU_GR.ATT1 */
+#define PERI_PPU_GR_ATT1_UR_Pos 0UL
+#define PERI_PPU_GR_ATT1_UR_Msk 0x1UL
+#define PERI_PPU_GR_ATT1_UW_Pos 1UL
+#define PERI_PPU_GR_ATT1_UW_Msk 0x2UL
+#define PERI_PPU_GR_ATT1_UX_Pos 2UL
+#define PERI_PPU_GR_ATT1_UX_Msk 0x4UL
+#define PERI_PPU_GR_ATT1_PR_Pos 3UL
+#define PERI_PPU_GR_ATT1_PR_Msk 0x8UL
+#define PERI_PPU_GR_ATT1_PW_Pos 4UL
+#define PERI_PPU_GR_ATT1_PW_Msk 0x10UL
+#define PERI_PPU_GR_ATT1_PX_Pos 5UL
+#define PERI_PPU_GR_ATT1_PX_Msk 0x20UL
+#define PERI_PPU_GR_ATT1_NS_Pos 6UL
+#define PERI_PPU_GR_ATT1_NS_Msk 0x40UL
+#define PERI_PPU_GR_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_PPU_GR_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_PPU_GR_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_PPU_GR_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_PPU_GR_ATT1_PC_MATCH_Pos 30UL
+#define PERI_PPU_GR_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_PPU_GR_ATT1_ENABLED_Pos 31UL
+#define PERI_PPU_GR_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_GR_PPU_SL.ADDR0 */
+#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos 8UL
+#define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_SL.ATT0 */
+#define PERI_GR_PPU_SL_ATT0_UR_Pos 0UL
+#define PERI_GR_PPU_SL_ATT0_UR_Msk 0x1UL
+#define PERI_GR_PPU_SL_ATT0_UW_Pos 1UL
+#define PERI_GR_PPU_SL_ATT0_UW_Msk 0x2UL
+#define PERI_GR_PPU_SL_ATT0_UX_Pos 2UL
+#define PERI_GR_PPU_SL_ATT0_UX_Msk 0x4UL
+#define PERI_GR_PPU_SL_ATT0_PR_Pos 3UL
+#define PERI_GR_PPU_SL_ATT0_PR_Msk 0x8UL
+#define PERI_GR_PPU_SL_ATT0_PW_Pos 4UL
+#define PERI_GR_PPU_SL_ATT0_PW_Msk 0x10UL
+#define PERI_GR_PPU_SL_ATT0_PX_Pos 5UL
+#define PERI_GR_PPU_SL_ATT0_PX_Msk 0x20UL
+#define PERI_GR_PPU_SL_ATT0_NS_Pos 6UL
+#define PERI_GR_PPU_SL_ATT0_NS_Msk 0x40UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_SL_ATT0_ENABLED_Pos 31UL
+#define PERI_GR_PPU_SL_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_GR_PPU_SL.ADDR1 */
+#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos 8UL
+#define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_SL.ATT1 */
+#define PERI_GR_PPU_SL_ATT1_UR_Pos 0UL
+#define PERI_GR_PPU_SL_ATT1_UR_Msk 0x1UL
+#define PERI_GR_PPU_SL_ATT1_UW_Pos 1UL
+#define PERI_GR_PPU_SL_ATT1_UW_Msk 0x2UL
+#define PERI_GR_PPU_SL_ATT1_UX_Pos 2UL
+#define PERI_GR_PPU_SL_ATT1_UX_Msk 0x4UL
+#define PERI_GR_PPU_SL_ATT1_PR_Pos 3UL
+#define PERI_GR_PPU_SL_ATT1_PR_Msk 0x8UL
+#define PERI_GR_PPU_SL_ATT1_PW_Pos 4UL
+#define PERI_GR_PPU_SL_ATT1_PW_Msk 0x10UL
+#define PERI_GR_PPU_SL_ATT1_PX_Pos 5UL
+#define PERI_GR_PPU_SL_ATT1_PX_Msk 0x20UL
+#define PERI_GR_PPU_SL_ATT1_NS_Pos 6UL
+#define PERI_GR_PPU_SL_ATT1_NS_Msk 0x40UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_SL_ATT1_ENABLED_Pos 31UL
+#define PERI_GR_PPU_SL_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI_GR_PPU_RG.ADDR0 */
+#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos 8UL
+#define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_RG.ATT0 */
+#define PERI_GR_PPU_RG_ATT0_UR_Pos 0UL
+#define PERI_GR_PPU_RG_ATT0_UR_Msk 0x1UL
+#define PERI_GR_PPU_RG_ATT0_UW_Pos 1UL
+#define PERI_GR_PPU_RG_ATT0_UW_Msk 0x2UL
+#define PERI_GR_PPU_RG_ATT0_UX_Pos 2UL
+#define PERI_GR_PPU_RG_ATT0_UX_Msk 0x4UL
+#define PERI_GR_PPU_RG_ATT0_PR_Pos 3UL
+#define PERI_GR_PPU_RG_ATT0_PR_Msk 0x8UL
+#define PERI_GR_PPU_RG_ATT0_PW_Pos 4UL
+#define PERI_GR_PPU_RG_ATT0_PW_Msk 0x10UL
+#define PERI_GR_PPU_RG_ATT0_PX_Pos 5UL
+#define PERI_GR_PPU_RG_ATT0_PX_Msk 0x20UL
+#define PERI_GR_PPU_RG_ATT0_NS_Pos 6UL
+#define PERI_GR_PPU_RG_ATT0_NS_Msk 0x40UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_RG_ATT0_ENABLED_Pos 31UL
+#define PERI_GR_PPU_RG_ATT0_ENABLED_Msk 0x80000000UL
+/* PERI_GR_PPU_RG.ADDR1 */
+#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos 8UL
+#define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PERI_GR_PPU_RG.ATT1 */
+#define PERI_GR_PPU_RG_ATT1_UR_Pos 0UL
+#define PERI_GR_PPU_RG_ATT1_UR_Msk 0x1UL
+#define PERI_GR_PPU_RG_ATT1_UW_Pos 1UL
+#define PERI_GR_PPU_RG_ATT1_UW_Msk 0x2UL
+#define PERI_GR_PPU_RG_ATT1_UX_Pos 2UL
+#define PERI_GR_PPU_RG_ATT1_UX_Msk 0x4UL
+#define PERI_GR_PPU_RG_ATT1_PR_Pos 3UL
+#define PERI_GR_PPU_RG_ATT1_PR_Msk 0x8UL
+#define PERI_GR_PPU_RG_ATT1_PW_Pos 4UL
+#define PERI_GR_PPU_RG_ATT1_PW_Msk 0x10UL
+#define PERI_GR_PPU_RG_ATT1_PX_Pos 5UL
+#define PERI_GR_PPU_RG_ATT1_PX_Msk 0x20UL
+#define PERI_GR_PPU_RG_ATT1_NS_Pos 6UL
+#define PERI_GR_PPU_RG_ATT1_NS_Msk 0x40UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos 8UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk 0x100UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos 24UL
+#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos 30UL
+#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PERI_GR_PPU_RG_ATT1_ENABLED_Pos 31UL
+#define PERI_GR_PPU_RG_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PERI.DIV_CMD */
+#define PERI_DIV_CMD_DIV_SEL_Pos 0UL
+#define PERI_DIV_CMD_DIV_SEL_Msk 0x3FUL
+#define PERI_DIV_CMD_TYPE_SEL_Pos 6UL
+#define PERI_DIV_CMD_TYPE_SEL_Msk 0xC0UL
+#define PERI_DIV_CMD_PA_DIV_SEL_Pos 8UL
+#define PERI_DIV_CMD_PA_DIV_SEL_Msk 0x3F00UL
+#define PERI_DIV_CMD_PA_TYPE_SEL_Pos 14UL
+#define PERI_DIV_CMD_PA_TYPE_SEL_Msk 0xC000UL
+#define PERI_DIV_CMD_DISABLE_Pos 30UL
+#define PERI_DIV_CMD_DISABLE_Msk 0x40000000UL
+#define PERI_DIV_CMD_ENABLE_Pos 31UL
+#define PERI_DIV_CMD_ENABLE_Msk 0x80000000UL
+/* PERI.DIV_8_CTL */
+#define PERI_DIV_8_CTL_EN_Pos 0UL
+#define PERI_DIV_8_CTL_EN_Msk 0x1UL
+#define PERI_DIV_8_CTL_INT8_DIV_Pos 8UL
+#define PERI_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
+/* PERI.DIV_16_CTL */
+#define PERI_DIV_16_CTL_EN_Pos 0UL
+#define PERI_DIV_16_CTL_EN_Msk 0x1UL
+#define PERI_DIV_16_CTL_INT16_DIV_Pos 8UL
+#define PERI_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_16_5_CTL */
+#define PERI_DIV_16_5_CTL_EN_Pos 0UL
+#define PERI_DIV_16_5_CTL_EN_Msk 0x1UL
+#define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_DIV_16_5_CTL_INT16_DIV_Pos 8UL
+#define PERI_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
+/* PERI.DIV_24_5_CTL */
+#define PERI_DIV_24_5_CTL_EN_Pos 0UL
+#define PERI_DIV_24_5_CTL_EN_Msk 0x1UL
+#define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
+#define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
+#define PERI_DIV_24_5_CTL_INT24_DIV_Pos 8UL
+#define PERI_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
+/* PERI.CLOCK_CTL */
+#define PERI_CLOCK_CTL_DIV_SEL_Pos 0UL
+#define PERI_CLOCK_CTL_DIV_SEL_Msk 0x3FUL
+#define PERI_CLOCK_CTL_TYPE_SEL_Pos 6UL
+#define PERI_CLOCK_CTL_TYPE_SEL_Msk 0xC0UL
+/* PERI.TR_CMD */
+#define PERI_TR_CMD_TR_SEL_Pos 0UL
+#define PERI_TR_CMD_TR_SEL_Msk 0xFFUL
+#define PERI_TR_CMD_GROUP_SEL_Pos 8UL
+#define PERI_TR_CMD_GROUP_SEL_Msk 0xF00UL
+#define PERI_TR_CMD_COUNT_Pos 16UL
+#define PERI_TR_CMD_COUNT_Msk 0xFF0000UL
+#define PERI_TR_CMD_OUT_SEL_Pos 30UL
+#define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL
+#define PERI_TR_CMD_ACTIVATE_Pos 31UL
+#define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL
+
+
+#endif /* _CYIP_PERI_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_profile.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,103 @@
+/***************************************************************************//**
+* \file cyip_profile.h
+*
+* \brief
+* PROFILE IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_PROFILE_H_
+#define _CYIP_PROFILE_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PROFILE
+*******************************************************************************/
+
+#define PROFILE_CNT_STRUCT_SECTION_SIZE 0x00000010UL
+#define PROFILE_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Profile counter structure (PROFILE_CNT_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Profile counter configuration */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CNT; /*!< 0x00000008 Profile counter value */
+ __IM uint32_t RESERVED1;
+} PROFILE_CNT_STRUCT_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * \brief Energy Profiler IP (PROFILE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Profile control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Profile status */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CMD; /*!< 0x00000010 Profile command */
+ __IM uint32_t RESERVED1[491];
+ __IOM uint32_t INTR; /*!< 0x000007C0 Profile interrupt */
+ __IOM uint32_t INTR_SET; /*!< 0x000007C4 Profile interrupt set */
+ __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Profile interrupt mask */
+ __IM uint32_t INTR_MASKED; /*!< 0x000007CC Profile interrupt masked */
+ __IM uint32_t RESERVED2[12];
+ PROFILE_CNT_STRUCT_Type CNT_STRUCT[16]; /*!< 0x00000800 Profile counter structure */
+} PROFILE_Type; /*!< Size = 2304 (0x900) */
+
+
+/* PROFILE_CNT_STRUCT.CTL */
+#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Pos 0UL
+#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Msk 0x1UL
+#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Pos 4UL
+#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Msk 0x70UL
+#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Pos 16UL
+#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Msk 0x7F0000UL
+#define PROFILE_CNT_STRUCT_CTL_ENABLED_Pos 31UL
+#define PROFILE_CNT_STRUCT_CTL_ENABLED_Msk 0x80000000UL
+/* PROFILE_CNT_STRUCT.CNT */
+#define PROFILE_CNT_STRUCT_CNT_CNT_Pos 0UL
+#define PROFILE_CNT_STRUCT_CNT_CNT_Msk 0xFFFFFFFFUL
+
+
+/* PROFILE.CTL */
+#define PROFILE_CTL_WIN_MODE_Pos 0UL
+#define PROFILE_CTL_WIN_MODE_Msk 0x1UL
+#define PROFILE_CTL_ENABLED_Pos 31UL
+#define PROFILE_CTL_ENABLED_Msk 0x80000000UL
+/* PROFILE.STATUS */
+#define PROFILE_STATUS_WIN_ACTIVE_Pos 0UL
+#define PROFILE_STATUS_WIN_ACTIVE_Msk 0x1UL
+/* PROFILE.CMD */
+#define PROFILE_CMD_START_TR_Pos 0UL
+#define PROFILE_CMD_START_TR_Msk 0x1UL
+#define PROFILE_CMD_STOP_TR_Pos 1UL
+#define PROFILE_CMD_STOP_TR_Msk 0x2UL
+#define PROFILE_CMD_CLR_ALL_CNT_Pos 8UL
+#define PROFILE_CMD_CLR_ALL_CNT_Msk 0x100UL
+/* PROFILE.INTR */
+#define PROFILE_INTR_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_SET */
+#define PROFILE_INTR_SET_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_SET_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_MASK */
+#define PROFILE_INTR_MASK_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_MASK_CNT_OVFLW_Msk 0xFFFFFFFFUL
+/* PROFILE.INTR_MASKED */
+#define PROFILE_INTR_MASKED_CNT_OVFLW_Pos 0UL
+#define PROFILE_INTR_MASKED_CNT_OVFLW_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_PROFILE_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_prot.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,372 @@
+/***************************************************************************//**
+* \file cyip_prot.h
+*
+* \brief
+* PROT IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_PROT_H_
+#define _CYIP_PROT_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* PROT
+*******************************************************************************/
+
+#define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL
+#define PROT_SMPU_SECTION_SIZE 0x00004000UL
+#define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL
+#define PROT_MPU_SECTION_SIZE 0x00000400UL
+#define PROT_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
+ __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
+ __IM uint32_t RESERVED[6];
+ __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
+ __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
+ __IM uint32_t RESERVED1[6];
+} PROT_SMPU_SMPU_STRUCT_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief SMPU (PROT_SMPU)
+ */
+typedef struct {
+ __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */
+ __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */
+ __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */
+ __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */
+ __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */
+ __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */
+ __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */
+ __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */
+ __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */
+ __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */
+ __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */
+ __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */
+ __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */
+ __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */
+ __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */
+ __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */
+ __IM uint32_t RESERVED[2032];
+ PROT_SMPU_SMPU_STRUCT_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
+ __IM uint32_t RESERVED1[1536];
+} PROT_SMPU_Type; /*!< Size = 16384 (0x4000) */
+
+/**
+ * \brief MPU structure (PROT_MPU_MPU_STRUCT)
+ */
+typedef struct {
+ __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */
+ __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */
+ __IM uint32_t RESERVED[6];
+} PROT_MPU_MPU_STRUCT_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief MPU (PROT_MPU)
+ */
+typedef struct {
+ __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */
+ __IM uint32_t RESERVED[127];
+ PROT_MPU_MPU_STRUCT_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
+} PROT_MPU_Type; /*!< Size = 1024 (0x400) */
+
+/**
+ * \brief Protection (PROT)
+ */
+typedef struct {
+ PROT_SMPU_Type SMPU; /*!< 0x00000000 SMPU */
+ PROT_MPU_Type CYMPU[16]; /*!< 0x00004000 MPU */
+} PROT_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT0 */
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk 0x80000000UL
+/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_SMPU_SMPU_STRUCT.ATT1 */
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos 0UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk 0x1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos 1UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk 0x2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos 2UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk 0x4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos 3UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk 0x8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos 4UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk 0x10UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos 5UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk 0x20UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos 6UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk 0x40UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos 8UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk 0x100UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos 9UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos 24UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos 30UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk 0x40000000UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos 31UL
+#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_SMPU.MS0_CTL */
+#define PROT_SMPU_MS0_CTL_P_Pos 0UL
+#define PROT_SMPU_MS0_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS0_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS0_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS0_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS0_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS1_CTL */
+#define PROT_SMPU_MS1_CTL_P_Pos 0UL
+#define PROT_SMPU_MS1_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS1_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS1_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS1_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS1_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS2_CTL */
+#define PROT_SMPU_MS2_CTL_P_Pos 0UL
+#define PROT_SMPU_MS2_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS2_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS2_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS2_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS2_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS3_CTL */
+#define PROT_SMPU_MS3_CTL_P_Pos 0UL
+#define PROT_SMPU_MS3_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS3_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS3_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS3_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS3_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS4_CTL */
+#define PROT_SMPU_MS4_CTL_P_Pos 0UL
+#define PROT_SMPU_MS4_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS4_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS4_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS4_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS4_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS5_CTL */
+#define PROT_SMPU_MS5_CTL_P_Pos 0UL
+#define PROT_SMPU_MS5_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS5_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS5_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS5_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS5_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS6_CTL */
+#define PROT_SMPU_MS6_CTL_P_Pos 0UL
+#define PROT_SMPU_MS6_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS6_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS6_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS6_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS6_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS7_CTL */
+#define PROT_SMPU_MS7_CTL_P_Pos 0UL
+#define PROT_SMPU_MS7_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS7_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS7_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS7_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS7_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS8_CTL */
+#define PROT_SMPU_MS8_CTL_P_Pos 0UL
+#define PROT_SMPU_MS8_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS8_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS8_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS8_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS8_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS9_CTL */
+#define PROT_SMPU_MS9_CTL_P_Pos 0UL
+#define PROT_SMPU_MS9_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS9_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS9_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS9_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS9_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS10_CTL */
+#define PROT_SMPU_MS10_CTL_P_Pos 0UL
+#define PROT_SMPU_MS10_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS10_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS10_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS10_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS10_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS11_CTL */
+#define PROT_SMPU_MS11_CTL_P_Pos 0UL
+#define PROT_SMPU_MS11_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS11_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS11_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS11_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS11_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS12_CTL */
+#define PROT_SMPU_MS12_CTL_P_Pos 0UL
+#define PROT_SMPU_MS12_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS12_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS12_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS12_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS12_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS13_CTL */
+#define PROT_SMPU_MS13_CTL_P_Pos 0UL
+#define PROT_SMPU_MS13_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS13_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS13_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS13_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS13_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS14_CTL */
+#define PROT_SMPU_MS14_CTL_P_Pos 0UL
+#define PROT_SMPU_MS14_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS14_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS14_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS14_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS14_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+/* PROT_SMPU.MS15_CTL */
+#define PROT_SMPU_MS15_CTL_P_Pos 0UL
+#define PROT_SMPU_MS15_CTL_P_Msk 0x1UL
+#define PROT_SMPU_MS15_CTL_NS_Pos 1UL
+#define PROT_SMPU_MS15_CTL_NS_Msk 0x2UL
+#define PROT_SMPU_MS15_CTL_PRIO_Pos 8UL
+#define PROT_SMPU_MS15_CTL_PRIO_Msk 0x300UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos 16UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk 0x10000UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
+#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
+
+
+/* PROT_MPU_MPU_STRUCT.ADDR */
+#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
+#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos 8UL
+#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk 0xFFFFFF00UL
+/* PROT_MPU_MPU_STRUCT.ATT */
+#define PROT_MPU_MPU_STRUCT_ATT_UR_Pos 0UL
+#define PROT_MPU_MPU_STRUCT_ATT_UR_Msk 0x1UL
+#define PROT_MPU_MPU_STRUCT_ATT_UW_Pos 1UL
+#define PROT_MPU_MPU_STRUCT_ATT_UW_Msk 0x2UL
+#define PROT_MPU_MPU_STRUCT_ATT_UX_Pos 2UL
+#define PROT_MPU_MPU_STRUCT_ATT_UX_Msk 0x4UL
+#define PROT_MPU_MPU_STRUCT_ATT_PR_Pos 3UL
+#define PROT_MPU_MPU_STRUCT_ATT_PR_Msk 0x8UL
+#define PROT_MPU_MPU_STRUCT_ATT_PW_Pos 4UL
+#define PROT_MPU_MPU_STRUCT_ATT_PW_Msk 0x10UL
+#define PROT_MPU_MPU_STRUCT_ATT_PX_Pos 5UL
+#define PROT_MPU_MPU_STRUCT_ATT_PX_Msk 0x20UL
+#define PROT_MPU_MPU_STRUCT_ATT_NS_Pos 6UL
+#define PROT_MPU_MPU_STRUCT_ATT_NS_Msk 0x40UL
+#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos 24UL
+#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk 0x1F000000UL
+#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos 31UL
+#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk 0x80000000UL
+
+
+/* PROT_MPU.MS_CTL */
+#define PROT_MPU_MS_CTL_PC_Pos 0UL
+#define PROT_MPU_MS_CTL_PC_Msk 0xFUL
+#define PROT_MPU_MS_CTL_PC_SAVED_Pos 16UL
+#define PROT_MPU_MS_CTL_PC_SAVED_Msk 0xF0000UL
+
+
+#endif /* _CYIP_PROT_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_sar.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,625 @@
+/***************************************************************************//**
+* \file cyip_sar.h
+*
+* \brief
+* SAR IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SAR_H_
+#define _CYIP_SAR_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SAR
+*******************************************************************************/
+
+#define SAR_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief SAR ADC with Sequencer (SAR)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */
+ __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */
+ __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */
+ __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */
+ __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */
+ __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */
+ __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */
+ __IM uint32_t RESERVED1[22];
+ __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */
+ __IM uint32_t RESERVED2[16];
+ __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */
+ __IM uint32_t RESERVED3[16];
+ __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */
+ __IM uint32_t RESERVED4[16];
+ __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */
+ __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */
+ __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */
+ __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */
+ __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */
+ __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */
+ __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */
+ __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */
+ __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */
+ __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */
+ __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */
+ __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */
+ __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */
+ __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */
+ __IM uint32_t RESERVED5[15];
+ __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */
+ __IM uint32_t RESERVED6[3];
+ __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */
+ __IM uint32_t RESERVED7[3];
+ __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */
+ __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */
+ __IM uint32_t RESERVED8[22];
+ __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */
+ __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */
+ __IM uint32_t RESERVED9[14];
+ __IOM uint32_t MUX_SWITCH_DS_CTRL; /*!< 0x00000340 SARMUX switch DSI control */
+ __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */
+ __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */
+ __IM uint32_t RESERVED10[749];
+ __IOM uint32_t ANA_TRIM0; /*!< 0x00000F00 Analog trim register. */
+ __IOM uint32_t ANA_TRIM1; /*!< 0x00000F04 Analog trim register. */
+} SAR_Type; /*!< Size = 3848 (0xF08) */
+
+
+/* SAR.CTRL */
+#define SAR_CTRL_PWR_CTRL_VREF_Pos 0UL
+#define SAR_CTRL_PWR_CTRL_VREF_Msk 0x7UL
+#define SAR_CTRL_VREF_SEL_Pos 4UL
+#define SAR_CTRL_VREF_SEL_Msk 0x70UL
+#define SAR_CTRL_VREF_BYP_CAP_EN_Pos 7UL
+#define SAR_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL
+#define SAR_CTRL_NEG_SEL_Pos 9UL
+#define SAR_CTRL_NEG_SEL_Msk 0xE00UL
+#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL
+#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL
+#define SAR_CTRL_COMP_DLY_Pos 14UL
+#define SAR_CTRL_COMP_DLY_Msk 0xC000UL
+#define SAR_CTRL_SPARE_Pos 16UL
+#define SAR_CTRL_SPARE_Msk 0xF0000UL
+#define SAR_CTRL_BOOSTPUMP_EN_Pos 20UL
+#define SAR_CTRL_BOOSTPUMP_EN_Msk 0x100000UL
+#define SAR_CTRL_REFBUF_EN_Pos 21UL
+#define SAR_CTRL_REFBUF_EN_Msk 0x200000UL
+#define SAR_CTRL_COMP_PWR_Pos 24UL
+#define SAR_CTRL_COMP_PWR_Msk 0x7000000UL
+#define SAR_CTRL_DEEPSLEEP_ON_Pos 27UL
+#define SAR_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL
+#define SAR_CTRL_DSI_SYNC_CONFIG_Pos 28UL
+#define SAR_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL
+#define SAR_CTRL_DSI_MODE_Pos 29UL
+#define SAR_CTRL_DSI_MODE_Msk 0x20000000UL
+#define SAR_CTRL_SWITCH_DISABLE_Pos 30UL
+#define SAR_CTRL_SWITCH_DISABLE_Msk 0x40000000UL
+#define SAR_CTRL_ENABLED_Pos 31UL
+#define SAR_CTRL_ENABLED_Msk 0x80000000UL
+/* SAR.SAMPLE_CTRL */
+#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL
+#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL
+#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL
+#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL
+#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL
+#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL
+#define SAR_SAMPLE_CTRL_AVG_CNT_Pos 4UL
+#define SAR_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL
+#define SAR_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL
+#define SAR_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL
+#define SAR_SAMPLE_CTRL_AVG_MODE_Pos 8UL
+#define SAR_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL
+#define SAR_SAMPLE_CTRL_CONTINUOUS_Pos 16UL
+#define SAR_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL
+#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL
+#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL
+#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL
+#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL
+#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL
+#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL
+#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_Pos 24UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL
+#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL
+#define SAR_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL
+#define SAR_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL
+#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL
+#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL
+#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL
+#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL
+/* SAR.SAMPLE_TIME01 */
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL
+#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL
+/* SAR.SAMPLE_TIME23 */
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL
+#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL
+/* SAR.RANGE_THRES */
+#define SAR_RANGE_THRES_RANGE_LOW_Pos 0UL
+#define SAR_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL
+#define SAR_RANGE_THRES_RANGE_HIGH_Pos 16UL
+#define SAR_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL
+/* SAR.RANGE_COND */
+#define SAR_RANGE_COND_RANGE_COND_Pos 30UL
+#define SAR_RANGE_COND_RANGE_COND_Msk 0xC0000000UL
+/* SAR.CHAN_EN */
+#define SAR_CHAN_EN_CHAN_EN_Pos 0UL
+#define SAR_CHAN_EN_CHAN_EN_Msk 0xFFFFUL
+/* SAR.START_CTRL */
+#define SAR_START_CTRL_FW_TRIGGER_Pos 0UL
+#define SAR_START_CTRL_FW_TRIGGER_Msk 0x1UL
+/* SAR.CHAN_CONFIG */
+#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL
+#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL
+#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL
+#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL
+#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL
+#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL
+#define SAR_CHAN_CONFIG_AVG_EN_Pos 10UL
+#define SAR_CHAN_CONFIG_AVG_EN_Msk 0x400UL
+#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL
+#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL
+#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL
+#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL
+#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL
+#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL
+#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL
+#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL
+#define SAR_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL
+#define SAR_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL
+/* SAR.CHAN_WORK */
+#define SAR_CHAN_WORK_WORK_Pos 0UL
+#define SAR_CHAN_WORK_WORK_Msk 0xFFFFUL
+#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL
+#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL
+#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL
+#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL
+/* SAR.CHAN_RESULT */
+#define SAR_CHAN_RESULT_RESULT_Pos 0UL
+#define SAR_CHAN_RESULT_RESULT_Msk 0xFFFFUL
+#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL
+#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL
+#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL
+#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL
+#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL
+#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL
+/* SAR.CHAN_WORK_UPDATED */
+#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL
+#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL
+/* SAR.CHAN_RESULT_UPDATED */
+#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL
+#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL
+/* SAR.CHAN_WORK_NEWVALUE */
+#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL
+#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL
+/* SAR.CHAN_RESULT_NEWVALUE */
+#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL
+#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL
+/* SAR.INTR */
+#define SAR_INTR_EOS_INTR_Pos 0UL
+#define SAR_INTR_EOS_INTR_Msk 0x1UL
+#define SAR_INTR_OVERFLOW_INTR_Pos 1UL
+#define SAR_INTR_OVERFLOW_INTR_Msk 0x2UL
+#define SAR_INTR_FW_COLLISION_INTR_Pos 2UL
+#define SAR_INTR_FW_COLLISION_INTR_Msk 0x4UL
+#define SAR_INTR_DSI_COLLISION_INTR_Pos 3UL
+#define SAR_INTR_DSI_COLLISION_INTR_Msk 0x8UL
+#define SAR_INTR_INJ_EOC_INTR_Pos 4UL
+#define SAR_INTR_INJ_EOC_INTR_Msk 0x10UL
+#define SAR_INTR_INJ_SATURATE_INTR_Pos 5UL
+#define SAR_INTR_INJ_SATURATE_INTR_Msk 0x20UL
+#define SAR_INTR_INJ_RANGE_INTR_Pos 6UL
+#define SAR_INTR_INJ_RANGE_INTR_Msk 0x40UL
+#define SAR_INTR_INJ_COLLISION_INTR_Pos 7UL
+#define SAR_INTR_INJ_COLLISION_INTR_Msk 0x80UL
+/* SAR.INTR_SET */
+#define SAR_INTR_SET_EOS_SET_Pos 0UL
+#define SAR_INTR_SET_EOS_SET_Msk 0x1UL
+#define SAR_INTR_SET_OVERFLOW_SET_Pos 1UL
+#define SAR_INTR_SET_OVERFLOW_SET_Msk 0x2UL
+#define SAR_INTR_SET_FW_COLLISION_SET_Pos 2UL
+#define SAR_INTR_SET_FW_COLLISION_SET_Msk 0x4UL
+#define SAR_INTR_SET_DSI_COLLISION_SET_Pos 3UL
+#define SAR_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL
+#define SAR_INTR_SET_INJ_EOC_SET_Pos 4UL
+#define SAR_INTR_SET_INJ_EOC_SET_Msk 0x10UL
+#define SAR_INTR_SET_INJ_SATURATE_SET_Pos 5UL
+#define SAR_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL
+#define SAR_INTR_SET_INJ_RANGE_SET_Pos 6UL
+#define SAR_INTR_SET_INJ_RANGE_SET_Msk 0x40UL
+#define SAR_INTR_SET_INJ_COLLISION_SET_Pos 7UL
+#define SAR_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL
+/* SAR.INTR_MASK */
+#define SAR_INTR_MASK_EOS_MASK_Pos 0UL
+#define SAR_INTR_MASK_EOS_MASK_Msk 0x1UL
+#define SAR_INTR_MASK_OVERFLOW_MASK_Pos 1UL
+#define SAR_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL
+#define SAR_INTR_MASK_FW_COLLISION_MASK_Pos 2UL
+#define SAR_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL
+#define SAR_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL
+#define SAR_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL
+#define SAR_INTR_MASK_INJ_EOC_MASK_Pos 4UL
+#define SAR_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL
+#define SAR_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL
+#define SAR_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL
+#define SAR_INTR_MASK_INJ_RANGE_MASK_Pos 6UL
+#define SAR_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL
+#define SAR_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL
+#define SAR_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL
+/* SAR.INTR_MASKED */
+#define SAR_INTR_MASKED_EOS_MASKED_Pos 0UL
+#define SAR_INTR_MASKED_EOS_MASKED_Msk 0x1UL
+#define SAR_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL
+#define SAR_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL
+#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL
+#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL
+#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL
+#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL
+#define SAR_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL
+#define SAR_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL
+#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL
+#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL
+#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL
+#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL
+#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL
+#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL
+/* SAR.SATURATE_INTR */
+#define SAR_SATURATE_INTR_SATURATE_INTR_Pos 0UL
+#define SAR_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_SET */
+#define SAR_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL
+#define SAR_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_MASK */
+#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL
+#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL
+/* SAR.SATURATE_INTR_MASKED */
+#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL
+#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL
+/* SAR.RANGE_INTR */
+#define SAR_RANGE_INTR_RANGE_INTR_Pos 0UL
+#define SAR_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_SET */
+#define SAR_RANGE_INTR_SET_RANGE_SET_Pos 0UL
+#define SAR_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_MASK */
+#define SAR_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL
+#define SAR_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL
+/* SAR.RANGE_INTR_MASKED */
+#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL
+#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL
+/* SAR.INTR_CAUSE */
+#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL
+#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL
+#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL
+#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL
+#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL
+#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL
+#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL
+#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL
+#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL
+#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL
+#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL
+#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL
+#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL
+#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL
+#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL
+#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL
+#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL
+#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL
+#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL
+#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL
+/* SAR.INJ_CHAN_CONFIG */
+#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL
+#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL
+#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL
+#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL
+#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL
+#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL
+#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL
+#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL
+#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL
+#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL
+#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL
+#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL
+/* SAR.INJ_RESULT */
+#define SAR_INJ_RESULT_INJ_RESULT_Pos 0UL
+#define SAR_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL
+#define SAR_INJ_RESULT_INJ_NEWVALUE_Pos 27UL
+#define SAR_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL
+#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL
+#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL
+#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL
+#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL
+#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL
+#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL
+#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL
+#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL
+/* SAR.STATUS */
+#define SAR_STATUS_CUR_CHAN_Pos 0UL
+#define SAR_STATUS_CUR_CHAN_Msk 0x1FUL
+#define SAR_STATUS_SW_VREF_NEG_Pos 30UL
+#define SAR_STATUS_SW_VREF_NEG_Msk 0x40000000UL
+#define SAR_STATUS_BUSY_Pos 31UL
+#define SAR_STATUS_BUSY_Msk 0x80000000UL
+/* SAR.AVG_STAT */
+#define SAR_AVG_STAT_CUR_AVG_ACCU_Pos 0UL
+#define SAR_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL
+#define SAR_AVG_STAT_INTRLV_BUSY_Pos 23UL
+#define SAR_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL
+#define SAR_AVG_STAT_CUR_AVG_CNT_Pos 24UL
+#define SAR_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL
+/* SAR.MUX_SWITCH0 */
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL
+#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL
+#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL
+#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL
+#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
+/* SAR.MUX_SWITCH_CLEAR0 */
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL
+#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
+/* SAR.MUX_SWITCH_DS_CTRL */
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Pos 0UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Msk 0x1UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Pos 1UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Msk 0x2UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Pos 2UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Msk 0x4UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Pos 3UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Msk 0x8UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Pos 4UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Msk 0x10UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Pos 5UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Msk 0x20UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Pos 6UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Msk 0x40UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Pos 7UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Msk 0x80UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Pos 16UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Msk 0x10000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Pos 17UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Msk 0x20000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Pos 18UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Msk 0x40000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Pos 19UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Msk 0x80000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Pos 22UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Msk 0x400000UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Pos 23UL
+#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Msk 0x800000UL
+/* SAR.MUX_SWITCH_SQ_CTRL */
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL
+#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL
+/* SAR.MUX_SWITCH_STATUS */
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL
+#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
+/* SAR.ANA_TRIM0 */
+#define SAR_ANA_TRIM0_CAP_TRIM_Pos 0UL
+#define SAR_ANA_TRIM0_CAP_TRIM_Msk 0x1FUL
+#define SAR_ANA_TRIM0_TRIMUNIT_Pos 5UL
+#define SAR_ANA_TRIM0_TRIMUNIT_Msk 0x20UL
+/* SAR.ANA_TRIM1 */
+#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Pos 0UL
+#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Msk 0x3FUL
+
+
+#endif /* _CYIP_SAR_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_scb.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,755 @@
+/***************************************************************************//**
+* \file cyip_scb.h
+*
+* \brief
+* SCB IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SCB_H_
+#define _CYIP_SCB_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SCB
+*******************************************************************************/
+
+#define SCB_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Serial Communications Block (SPI/UART/I2C) (CySCB)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Generic control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Generic status */
+ __IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */
+ __IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */
+ __IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */
+ __IM uint32_t RESERVED1[6];
+ __IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */
+ __IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */
+ __IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */
+ __IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */
+ __IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */
+ __IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */
+ __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */
+ __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */
+ __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */
+ __IM uint32_t RESERVED3[35];
+ __IOM uint32_t DDFT_CTRL; /*!< 0x00000100 Digital DfT control */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */
+ __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */
+ __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */
+ __IM uint32_t RESERVED5[13];
+ __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */
+ __IM uint32_t RESERVED6[47];
+ __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */
+ __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */
+ __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */
+ __IM uint32_t RESERVED8[11];
+ __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */
+ __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */
+ __IM uint32_t RESERVED9[46];
+ __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */
+ __IM uint32_t RESERVED10[128];
+ __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */
+ __IM uint32_t RESERVED11[31];
+ __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */
+ __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */
+ __IM uint32_t RESERVED13[12];
+ __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */
+ __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */
+ __IM uint32_t RESERVED15[12];
+ __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */
+ __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */
+ __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */
+ __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */
+ __IM uint32_t RESERVED16[12];
+ __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */
+ __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */
+ __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */
+ __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */
+ __IM uint32_t RESERVED17[12];
+ __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */
+ __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */
+ __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */
+ __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */
+ __IM uint32_t RESERVED18[12];
+ __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */
+ __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */
+ __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */
+ __IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */
+} CySCB_Type; /*!< Size = 4048 (0xFD0) */
+
+
+/* SCB.CTRL */
+#define SCB_CTRL_OVS_Pos 0UL
+#define SCB_CTRL_OVS_Msk 0xFUL
+#define SCB_CTRL_EC_AM_MODE_Pos 8UL
+#define SCB_CTRL_EC_AM_MODE_Msk 0x100UL
+#define SCB_CTRL_EC_OP_MODE_Pos 9UL
+#define SCB_CTRL_EC_OP_MODE_Msk 0x200UL
+#define SCB_CTRL_EZ_MODE_Pos 10UL
+#define SCB_CTRL_EZ_MODE_Msk 0x400UL
+#define SCB_CTRL_BYTE_MODE_Pos 11UL
+#define SCB_CTRL_BYTE_MODE_Msk 0x800UL
+#define SCB_CTRL_CMD_RESP_MODE_Pos 12UL
+#define SCB_CTRL_CMD_RESP_MODE_Msk 0x1000UL
+#define SCB_CTRL_ADDR_ACCEPT_Pos 16UL
+#define SCB_CTRL_ADDR_ACCEPT_Msk 0x10000UL
+#define SCB_CTRL_BLOCK_Pos 17UL
+#define SCB_CTRL_BLOCK_Msk 0x20000UL
+#define SCB_CTRL_MODE_Pos 24UL
+#define SCB_CTRL_MODE_Msk 0x3000000UL
+#define SCB_CTRL_ENABLED_Pos 31UL
+#define SCB_CTRL_ENABLED_Msk 0x80000000UL
+/* SCB.STATUS */
+#define SCB_STATUS_EC_BUSY_Pos 0UL
+#define SCB_STATUS_EC_BUSY_Msk 0x1UL
+/* SCB.CMD_RESP_CTRL */
+#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 0UL
+#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 0x1FFUL
+#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 16UL
+#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 0x1FF0000UL
+/* SCB.CMD_RESP_STATUS */
+#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 0UL
+#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 0x1FFUL
+#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 16UL
+#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 0x1FF0000UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 30UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 0x40000000UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 31UL
+#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 0x80000000UL
+/* SCB.SPI_CTRL */
+#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos 0UL
+#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk 0x1UL
+#define SCB_SPI_CTRL_SELECT_PRECEDE_Pos 1UL
+#define SCB_SPI_CTRL_SELECT_PRECEDE_Msk 0x2UL
+#define SCB_SPI_CTRL_CPHA_Pos 2UL
+#define SCB_SPI_CTRL_CPHA_Msk 0x4UL
+#define SCB_SPI_CTRL_CPOL_Pos 3UL
+#define SCB_SPI_CTRL_CPOL_Msk 0x8UL
+#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos 4UL
+#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk 0x10UL
+#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos 5UL
+#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk 0x20UL
+#define SCB_SPI_CTRL_SSEL_POLARITY0_Pos 8UL
+#define SCB_SPI_CTRL_SSEL_POLARITY0_Msk 0x100UL
+#define SCB_SPI_CTRL_SSEL_POLARITY1_Pos 9UL
+#define SCB_SPI_CTRL_SSEL_POLARITY1_Msk 0x200UL
+#define SCB_SPI_CTRL_SSEL_POLARITY2_Pos 10UL
+#define SCB_SPI_CTRL_SSEL_POLARITY2_Msk 0x400UL
+#define SCB_SPI_CTRL_SSEL_POLARITY3_Pos 11UL
+#define SCB_SPI_CTRL_SSEL_POLARITY3_Msk 0x800UL
+#define SCB_SPI_CTRL_LOOPBACK_Pos 16UL
+#define SCB_SPI_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_SPI_CTRL_MODE_Pos 24UL
+#define SCB_SPI_CTRL_MODE_Msk 0x3000000UL
+#define SCB_SPI_CTRL_SSEL_Pos 26UL
+#define SCB_SPI_CTRL_SSEL_Msk 0xC000000UL
+#define SCB_SPI_CTRL_MASTER_MODE_Pos 31UL
+#define SCB_SPI_CTRL_MASTER_MODE_Msk 0x80000000UL
+/* SCB.SPI_STATUS */
+#define SCB_SPI_STATUS_BUS_BUSY_Pos 0UL
+#define SCB_SPI_STATUS_BUS_BUSY_Msk 0x1UL
+#define SCB_SPI_STATUS_SPI_EC_BUSY_Pos 1UL
+#define SCB_SPI_STATUS_SPI_EC_BUSY_Msk 0x2UL
+#define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos 8UL
+#define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
+#define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos 16UL
+#define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
+/* SCB.UART_CTRL */
+#define SCB_UART_CTRL_LOOPBACK_Pos 16UL
+#define SCB_UART_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_UART_CTRL_MODE_Pos 24UL
+#define SCB_UART_CTRL_MODE_Msk 0x3000000UL
+/* SCB.UART_TX_CTRL */
+#define SCB_UART_TX_CTRL_STOP_BITS_Pos 0UL
+#define SCB_UART_TX_CTRL_STOP_BITS_Msk 0x7UL
+#define SCB_UART_TX_CTRL_PARITY_Pos 4UL
+#define SCB_UART_TX_CTRL_PARITY_Msk 0x10UL
+#define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos 5UL
+#define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk 0x20UL
+#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos 8UL
+#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk 0x100UL
+/* SCB.UART_RX_CTRL */
+#define SCB_UART_RX_CTRL_STOP_BITS_Pos 0UL
+#define SCB_UART_RX_CTRL_STOP_BITS_Msk 0x7UL
+#define SCB_UART_RX_CTRL_PARITY_Pos 4UL
+#define SCB_UART_RX_CTRL_PARITY_Msk 0x10UL
+#define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos 5UL
+#define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk 0x20UL
+#define SCB_UART_RX_CTRL_POLARITY_Pos 6UL
+#define SCB_UART_RX_CTRL_POLARITY_Msk 0x40UL
+#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL
+#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL
+#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 9UL
+#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 0x200UL
+#define SCB_UART_RX_CTRL_MP_MODE_Pos 10UL
+#define SCB_UART_RX_CTRL_MP_MODE_Msk 0x400UL
+#define SCB_UART_RX_CTRL_LIN_MODE_Pos 12UL
+#define SCB_UART_RX_CTRL_LIN_MODE_Msk 0x1000UL
+#define SCB_UART_RX_CTRL_SKIP_START_Pos 13UL
+#define SCB_UART_RX_CTRL_SKIP_START_Msk 0x2000UL
+#define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos 16UL
+#define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk 0xF0000UL
+/* SCB.UART_RX_STATUS */
+#define SCB_UART_RX_STATUS_BR_COUNTER_Pos 0UL
+#define SCB_UART_RX_STATUS_BR_COUNTER_Msk 0xFFFUL
+/* SCB.UART_FLOW_CTRL */
+#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos 16UL
+#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk 0x10000UL
+#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos 24UL
+#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk 0x1000000UL
+#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos 25UL
+#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk 0x2000000UL
+/* SCB.I2C_CTRL */
+#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos 0UL
+#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk 0xFUL
+#define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos 4UL
+#define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk 0xF0UL
+#define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos 8UL
+#define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk 0x100UL
+#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 9UL
+#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 0x200UL
+#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos 11UL
+#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk 0x800UL
+#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos 12UL
+#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk 0x1000UL
+#define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos 13UL
+#define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk 0x2000UL
+#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 14UL
+#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 0x4000UL
+#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 15UL
+#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 0x8000UL
+#define SCB_I2C_CTRL_LOOPBACK_Pos 16UL
+#define SCB_I2C_CTRL_LOOPBACK_Msk 0x10000UL
+#define SCB_I2C_CTRL_SLAVE_MODE_Pos 30UL
+#define SCB_I2C_CTRL_SLAVE_MODE_Msk 0x40000000UL
+#define SCB_I2C_CTRL_MASTER_MODE_Pos 31UL
+#define SCB_I2C_CTRL_MASTER_MODE_Msk 0x80000000UL
+/* SCB.I2C_STATUS */
+#define SCB_I2C_STATUS_BUS_BUSY_Pos 0UL
+#define SCB_I2C_STATUS_BUS_BUSY_Msk 0x1UL
+#define SCB_I2C_STATUS_I2C_EC_BUSY_Pos 1UL
+#define SCB_I2C_STATUS_I2C_EC_BUSY_Msk 0x2UL
+#define SCB_I2C_STATUS_S_READ_Pos 4UL
+#define SCB_I2C_STATUS_S_READ_Msk 0x10UL
+#define SCB_I2C_STATUS_M_READ_Pos 5UL
+#define SCB_I2C_STATUS_M_READ_Msk 0x20UL
+#define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos 8UL
+#define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
+#define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos 16UL
+#define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
+/* SCB.I2C_M_CMD */
+#define SCB_I2C_M_CMD_M_START_Pos 0UL
+#define SCB_I2C_M_CMD_M_START_Msk 0x1UL
+#define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos 1UL
+#define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk 0x2UL
+#define SCB_I2C_M_CMD_M_ACK_Pos 2UL
+#define SCB_I2C_M_CMD_M_ACK_Msk 0x4UL
+#define SCB_I2C_M_CMD_M_NACK_Pos 3UL
+#define SCB_I2C_M_CMD_M_NACK_Msk 0x8UL
+#define SCB_I2C_M_CMD_M_STOP_Pos 4UL
+#define SCB_I2C_M_CMD_M_STOP_Msk 0x10UL
+/* SCB.I2C_S_CMD */
+#define SCB_I2C_S_CMD_S_ACK_Pos 0UL
+#define SCB_I2C_S_CMD_S_ACK_Msk 0x1UL
+#define SCB_I2C_S_CMD_S_NACK_Pos 1UL
+#define SCB_I2C_S_CMD_S_NACK_Msk 0x2UL
+/* SCB.I2C_CFG */
+#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos 0UL
+#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk 0x3UL
+#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos 4UL
+#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk 0x10UL
+#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos 8UL
+#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk 0x300UL
+#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos 12UL
+#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk 0x1000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 16UL
+#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 0x30000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 18UL
+#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 0xC0000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 20UL
+#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL
+#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL
+#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL
+/* SCB.DDFT_CTRL */
+#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Pos 0UL
+#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Msk 0x1UL
+#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Pos 4UL
+#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Msk 0x10UL
+#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Pos 16UL
+#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Msk 0x70000UL
+#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Pos 20UL
+#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Msk 0x700000UL
+/* SCB.TX_CTRL */
+#define SCB_TX_CTRL_DATA_WIDTH_Pos 0UL
+#define SCB_TX_CTRL_DATA_WIDTH_Msk 0xFUL
+#define SCB_TX_CTRL_MSB_FIRST_Pos 8UL
+#define SCB_TX_CTRL_MSB_FIRST_Msk 0x100UL
+#define SCB_TX_CTRL_OPEN_DRAIN_Pos 16UL
+#define SCB_TX_CTRL_OPEN_DRAIN_Msk 0x10000UL
+/* SCB.TX_FIFO_CTRL */
+#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_TX_FIFO_CTRL_CLEAR_Pos 16UL
+#define SCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+#define SCB_TX_FIFO_CTRL_FREEZE_Pos 17UL
+#define SCB_TX_FIFO_CTRL_FREEZE_Msk 0x20000UL
+/* SCB.TX_FIFO_STATUS */
+#define SCB_TX_FIFO_STATUS_USED_Pos 0UL
+#define SCB_TX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define SCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define SCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define SCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define SCB_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define SCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define SCB_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* SCB.TX_FIFO_WR */
+#define SCB_TX_FIFO_WR_DATA_Pos 0UL
+#define SCB_TX_FIFO_WR_DATA_Msk 0xFFFFUL
+/* SCB.RX_CTRL */
+#define SCB_RX_CTRL_DATA_WIDTH_Pos 0UL
+#define SCB_RX_CTRL_DATA_WIDTH_Msk 0xFUL
+#define SCB_RX_CTRL_MSB_FIRST_Pos 8UL
+#define SCB_RX_CTRL_MSB_FIRST_Msk 0x100UL
+#define SCB_RX_CTRL_MEDIAN_Pos 9UL
+#define SCB_RX_CTRL_MEDIAN_Msk 0x200UL
+/* SCB.RX_FIFO_CTRL */
+#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
+#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
+#define SCB_RX_FIFO_CTRL_CLEAR_Pos 16UL
+#define SCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL
+#define SCB_RX_FIFO_CTRL_FREEZE_Pos 17UL
+#define SCB_RX_FIFO_CTRL_FREEZE_Msk 0x20000UL
+/* SCB.RX_FIFO_STATUS */
+#define SCB_RX_FIFO_STATUS_USED_Pos 0UL
+#define SCB_RX_FIFO_STATUS_USED_Msk 0x1FFUL
+#define SCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL
+#define SCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
+#define SCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL
+#define SCB_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
+#define SCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL
+#define SCB_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
+/* SCB.RX_MATCH */
+#define SCB_RX_MATCH_ADDR_Pos 0UL
+#define SCB_RX_MATCH_ADDR_Msk 0xFFUL
+#define SCB_RX_MATCH_MASK_Pos 16UL
+#define SCB_RX_MATCH_MASK_Msk 0xFF0000UL
+/* SCB.RX_FIFO_RD */
+#define SCB_RX_FIFO_RD_DATA_Pos 0UL
+#define SCB_RX_FIFO_RD_DATA_Msk 0xFFFFUL
+/* SCB.RX_FIFO_RD_SILENT */
+#define SCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL
+#define SCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFUL
+/* SCB.EZ_DATA */
+#define SCB_EZ_DATA_EZ_DATA_Pos 0UL
+#define SCB_EZ_DATA_EZ_DATA_Msk 0xFFUL
+/* SCB.INTR_CAUSE */
+#define SCB_INTR_CAUSE_M_Pos 0UL
+#define SCB_INTR_CAUSE_M_Msk 0x1UL
+#define SCB_INTR_CAUSE_S_Pos 1UL
+#define SCB_INTR_CAUSE_S_Msk 0x2UL
+#define SCB_INTR_CAUSE_TX_Pos 2UL
+#define SCB_INTR_CAUSE_TX_Msk 0x4UL
+#define SCB_INTR_CAUSE_RX_Pos 3UL
+#define SCB_INTR_CAUSE_RX_Msk 0x8UL
+#define SCB_INTR_CAUSE_I2C_EC_Pos 4UL
+#define SCB_INTR_CAUSE_I2C_EC_Msk 0x10UL
+#define SCB_INTR_CAUSE_SPI_EC_Pos 5UL
+#define SCB_INTR_CAUSE_SPI_EC_Msk 0x20UL
+/* SCB.INTR_I2C_EC */
+#define SCB_INTR_I2C_EC_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_I2C_EC_MASK */
+#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_I2C_EC_MASKED */
+#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos 0UL
+#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos 1UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC */
+#define SCB_INTR_SPI_EC_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC_MASK */
+#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_SPI_EC_MASKED */
+#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos 0UL
+#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk 0x1UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos 1UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk 0x2UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 3UL
+#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
+/* SCB.INTR_M */
+#define SCB_INTR_M_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_SET */
+#define SCB_INTR_M_SET_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_SET_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_SET_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_SET_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_SET_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_SET_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_SET_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_SET_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_SET_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_SET_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_MASK */
+#define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_MASK_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_MASK_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_MASK_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_MASK_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_MASK_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_MASK_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_MASK_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_MASK_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_M_MASKED */
+#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_M_MASKED_I2C_NACK_Pos 1UL
+#define SCB_INTR_M_MASKED_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_M_MASKED_I2C_ACK_Pos 2UL
+#define SCB_INTR_M_MASKED_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_M_MASKED_I2C_STOP_Pos 4UL
+#define SCB_INTR_M_MASKED_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_M_MASKED_SPI_DONE_Pos 9UL
+#define SCB_INTR_M_MASKED_SPI_DONE_Msk 0x200UL
+/* SCB.INTR_S */
+#define SCB_INTR_S_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_I2C_START_Pos 5UL
+#define SCB_INTR_S_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_SET */
+#define SCB_INTR_S_SET_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_SET_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_SET_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_SET_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_SET_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_SET_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_SET_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_SET_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_SET_I2C_START_Pos 5UL
+#define SCB_INTR_S_SET_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_SET_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_SET_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_SET_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_SET_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_MASK */
+#define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_MASK_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_MASK_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_MASK_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_MASK_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_MASK_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_MASK_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_MASK_I2C_START_Pos 5UL
+#define SCB_INTR_S_MASK_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_MASK_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_MASK_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_S_MASKED */
+#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos 0UL
+#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk 0x1UL
+#define SCB_INTR_S_MASKED_I2C_NACK_Pos 1UL
+#define SCB_INTR_S_MASKED_I2C_NACK_Msk 0x2UL
+#define SCB_INTR_S_MASKED_I2C_ACK_Pos 2UL
+#define SCB_INTR_S_MASKED_I2C_ACK_Msk 0x4UL
+#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3UL
+#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk 0x8UL
+#define SCB_INTR_S_MASKED_I2C_STOP_Pos 4UL
+#define SCB_INTR_S_MASKED_I2C_STOP_Msk 0x10UL
+#define SCB_INTR_S_MASKED_I2C_START_Pos 5UL
+#define SCB_INTR_S_MASKED_I2C_START_Msk 0x20UL
+#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 6UL
+#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 0x40UL
+#define SCB_INTR_S_MASKED_I2C_GENERAL_Pos 7UL
+#define SCB_INTR_S_MASKED_I2C_GENERAL_Msk 0x80UL
+#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos 8UL
+#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk 0x100UL
+#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 9UL
+#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 0x200UL
+#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos 10UL
+#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk 0x400UL
+#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos 11UL
+#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk 0x800UL
+/* SCB.INTR_TX */
+#define SCB_INTR_TX_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_EMPTY_Pos 4UL
+#define SCB_INTR_TX_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_SET */
+#define SCB_INTR_TX_SET_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_SET_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_SET_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_SET_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_SET_EMPTY_Pos 4UL
+#define SCB_INTR_TX_SET_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_SET_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_SET_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_SET_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_SET_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_SET_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_SET_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_SET_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_SET_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_SET_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_SET_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_SET_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_SET_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_MASK */
+#define SCB_INTR_TX_MASK_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_MASK_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_MASK_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_MASK_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_MASK_EMPTY_Pos 4UL
+#define SCB_INTR_TX_MASK_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_MASK_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_MASK_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_MASK_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_MASK_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_MASK_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_MASK_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_MASK_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_MASK_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_MASK_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_MASK_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_TX_MASKED */
+#define SCB_INTR_TX_MASKED_TRIGGER_Pos 0UL
+#define SCB_INTR_TX_MASKED_TRIGGER_Msk 0x1UL
+#define SCB_INTR_TX_MASKED_NOT_FULL_Pos 1UL
+#define SCB_INTR_TX_MASKED_NOT_FULL_Msk 0x2UL
+#define SCB_INTR_TX_MASKED_EMPTY_Pos 4UL
+#define SCB_INTR_TX_MASKED_EMPTY_Msk 0x10UL
+#define SCB_INTR_TX_MASKED_OVERFLOW_Pos 5UL
+#define SCB_INTR_TX_MASKED_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_TX_MASKED_UNDERFLOW_Pos 6UL
+#define SCB_INTR_TX_MASKED_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL
+#define SCB_INTR_TX_MASKED_BLOCKED_Msk 0x80UL
+#define SCB_INTR_TX_MASKED_UART_NACK_Pos 8UL
+#define SCB_INTR_TX_MASKED_UART_NACK_Msk 0x100UL
+#define SCB_INTR_TX_MASKED_UART_DONE_Pos 9UL
+#define SCB_INTR_TX_MASKED_UART_DONE_Msk 0x200UL
+#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos 10UL
+#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk 0x400UL
+/* SCB.INTR_RX */
+#define SCB_INTR_RX_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_FULL_Pos 3UL
+#define SCB_INTR_RX_FULL_Msk 0x8UL
+#define SCB_INTR_RX_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_SET */
+#define SCB_INTR_RX_SET_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_SET_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_SET_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_SET_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_SET_FULL_Pos 3UL
+#define SCB_INTR_RX_SET_FULL_Msk 0x8UL
+#define SCB_INTR_RX_SET_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_SET_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_SET_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_SET_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_SET_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_SET_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_SET_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_SET_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_SET_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_SET_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_SET_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_SET_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_SET_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_SET_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_MASK */
+#define SCB_INTR_RX_MASK_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_MASK_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_MASK_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_MASK_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_MASK_FULL_Pos 3UL
+#define SCB_INTR_RX_MASK_FULL_Msk 0x8UL
+#define SCB_INTR_RX_MASK_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_MASK_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_MASK_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_MASK_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_MASK_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_MASK_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_MASK_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_MASK_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_MASK_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_MASK_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_MASK_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_MASK_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_MASK_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_MASK_BREAK_DETECT_Msk 0x800UL
+/* SCB.INTR_RX_MASKED */
+#define SCB_INTR_RX_MASKED_TRIGGER_Pos 0UL
+#define SCB_INTR_RX_MASKED_TRIGGER_Msk 0x1UL
+#define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos 2UL
+#define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk 0x4UL
+#define SCB_INTR_RX_MASKED_FULL_Pos 3UL
+#define SCB_INTR_RX_MASKED_FULL_Msk 0x8UL
+#define SCB_INTR_RX_MASKED_OVERFLOW_Pos 5UL
+#define SCB_INTR_RX_MASKED_OVERFLOW_Msk 0x20UL
+#define SCB_INTR_RX_MASKED_UNDERFLOW_Pos 6UL
+#define SCB_INTR_RX_MASKED_UNDERFLOW_Msk 0x40UL
+#define SCB_INTR_RX_MASKED_BLOCKED_Pos 7UL
+#define SCB_INTR_RX_MASKED_BLOCKED_Msk 0x80UL
+#define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos 8UL
+#define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk 0x100UL
+#define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos 9UL
+#define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk 0x200UL
+#define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos 10UL
+#define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk 0x400UL
+#define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos 11UL
+#define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk 0x800UL
+
+
+#endif /* _CYIP_SCB_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_sflash.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,457 @@
+/***************************************************************************//**
+* \file cyip_sflash.h
+*
+* \brief
+* SFLASH IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SFLASH_H_
+#define _CYIP_SFLASH_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SFLASH
+*******************************************************************************/
+
+#define SFLASH_SECTION_SIZE 0x00008000UL
+
+/**
+ * \brief FLASH Supervisory Region (SFLASH)
+ */
+typedef struct {
+ __IM uint8_t RESERVED;
+ __IOM uint8_t SI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */
+ __IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */
+ __IM uint16_t RESERVED2[761];
+ __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */
+ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */
+ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */
+ __IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */
+ __IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */
+ __IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */
+ __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */
+ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */
+ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */
+ __IM uint8_t RESERVED3[61];
+ __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */
+ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */
+ __IM uint32_t RESERVED4[8];
+ __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */
+ __IM uint32_t RESERVED5[52];
+ __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */
+ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */
+ __IM uint16_t RESERVED6[95];
+ __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */
+ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */
+ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */
+ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */
+ __IM uint32_t RESERVED7[302];
+ __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */
+ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */
+ __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */
+ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */
+ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */
+ __IM uint32_t RESERVED8[122];
+ __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */
+ __IM uint16_t RESERVED9;
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p3 & 0p8 voltage levels for accuracy */
+ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */
+ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */
+ __IM uint16_t RESERVED10;
+ __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */
+ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */
+ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */
+ __IM uint32_t RESERVED11[502];
+ __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */
+ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */
+ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */
+ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */
+ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */
+ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */
+ __IM uint32_t RESERVED12[48];
+ __IOM uint8_t FLASH_BOOT_CODE[8488]; /*!< 0x000020D8 Flash Boot - Code and Data */
+ __IM uint32_t RESERVED13[1536];
+ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */
+ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */
+ __IM uint32_t RESERVED14[768];
+ __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset
+ 0x00 */
+ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */
+ __IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for
+ FACTORY_HASH */
+ __IOM uint32_t TOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x0000780C Address of trims stored in SFLASH */
+ __IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */
+ __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */
+ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007818 Address of SYSCALL_TABLE entry in SFLASH */
+ __IOM uint32_t TOC1_BOOT_PROTECTION_ADDR; /*!< 0x0000781C Address of boot protection object */
+ __IM uint32_t RESERVED15[119];
+ __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
+ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting
+ from offset 0x00 */
+ __IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */
+ __IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be
+ verified for FACTORY_HASH */
+ __IOM uint32_t RTOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x00007A0C Redundant Address of trims stored in SFLASH */
+ __IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */
+ __IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH
+ patch also */
+ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007A18 Redundant Address of SYSCALL_TABLE entry in SFLASH */
+ __IM uint32_t RESERVED16[120];
+ __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
+ bytes are 0 */
+ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset
+ 0x00 */
+ __IOM uint32_t TOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */
+ __IOM uint32_t TOC2_KEY_BLOCK_ADDR; /*!< 0x00007C08 Address of Key Storage FLASH blocks */
+ __IOM uint32_t TOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C0C Null terminated table of pointers representing the SMIF
+ configuration structure */
+ __IOM uint32_t TOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C10 Address of First User Application Object */
+ __IOM uint32_t TOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C14 Format of First User Application Object. 0 - Basic, 1 - Cypress
+ standard & 2 - Simplified */
+ __IOM uint32_t TOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C18 Address of Second User Application Object */
+ __IOM uint32_t TOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C1C Format of Second User Application Object. 0 - Basic, 1 -
+ Cypress standard & 2 - Simplified */
+ __IOM uint32_t TOC2_SHASH_OBJECTS; /*!< 0x00007C20 Number of additional objects(in addition to objects covered by
+ FACORY_CAMC) starting from offset 0x24 to be verified for
+ SECURE_HASH(SHASH) */
+ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is
+ signature specific key. It is the public key in case of RSA */
+ __IM uint32_t RESERVED17[116];
+ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */
+ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
+ __IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting
+ from offset 0x00 */
+ __IOM uint32_t RTOC2_MAGIC_NUMBER; /*!< 0x00007E04 Redundant Magic number(0x01211220) */
+ __IOM uint32_t RTOC2_KEY_BLOCK_ADDR; /*!< 0x00007E08 Redundant Address of Key Storage FLASH blocks */
+ __IOM uint32_t RTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007E0C Redundant Null terminated table of pointers representing the
+ SMIF configuration structure */
+ __IOM uint32_t RTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007E10 Redundant Address of First User Application Object */
+ __IOM uint32_t RTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007E14 Redundant Format of First User Application Object. 0 - Basic, 1
+ - Cypress standard & 2 - Simplified */
+ __IOM uint32_t RTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007E18 Redundant Address of Second User Application Object */
+ __IOM uint32_t RTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007E1C Redundant Format of Second User Application Object. 0 - Basic,
+ 1 - Cypress standard & 2 - Simplified */
+ __IOM uint32_t RTOC2_SHASH_OBJECTS; /*!< 0x00007E20 Redundant Number of additional objects(in addition to objects
+ covered by FACORY_CAMC) starting from offset 0x24 to be verified
+ for SECURE_HASH(SHASH) */
+ __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The
+ object is signature specific key. It is the public key in case
+ of RSA */
+ __IM uint32_t RESERVED18[116];
+ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */
+ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
+ bytes are 0 */
+} SFLASH_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* SFLASH.SI_REVISION_ID */
+#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL
+#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL
+/* SFLASH.SILICON_ID */
+#define SFLASH_SILICON_ID_ID_Pos 0UL
+#define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL
+/* SFLASH.FAMILY_ID */
+#define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL
+#define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL
+/* SFLASH.DIE_LOT */
+#define SFLASH_DIE_LOT_LOT_Pos 0UL
+#define SFLASH_DIE_LOT_LOT_Msk 0xFFUL
+/* SFLASH.DIE_WAFER */
+#define SFLASH_DIE_WAFER_WAFER_Pos 0UL
+#define SFLASH_DIE_WAFER_WAFER_Msk 0xFFUL
+/* SFLASH.DIE_X */
+#define SFLASH_DIE_X_X_Pos 0UL
+#define SFLASH_DIE_X_X_Msk 0xFFUL
+/* SFLASH.DIE_Y */
+#define SFLASH_DIE_Y_Y_Pos 0UL
+#define SFLASH_DIE_Y_Y_Msk 0xFFUL
+/* SFLASH.DIE_SORT */
+#define SFLASH_DIE_SORT_S1_PASS_Pos 0UL
+#define SFLASH_DIE_SORT_S1_PASS_Msk 0x1UL
+#define SFLASH_DIE_SORT_S2_PASS_Pos 1UL
+#define SFLASH_DIE_SORT_S2_PASS_Msk 0x2UL
+#define SFLASH_DIE_SORT_S3_PASS_Pos 2UL
+#define SFLASH_DIE_SORT_S3_PASS_Msk 0x4UL
+#define SFLASH_DIE_SORT_CRI_PASS_Pos 3UL
+#define SFLASH_DIE_SORT_CRI_PASS_Msk 0x8UL
+#define SFLASH_DIE_SORT_CHI_PASS_Pos 4UL
+#define SFLASH_DIE_SORT_CHI_PASS_Msk 0x10UL
+#define SFLASH_DIE_SORT_ENG_PASS_Pos 5UL
+#define SFLASH_DIE_SORT_ENG_PASS_Msk 0x20UL
+/* SFLASH.DIE_MINOR */
+#define SFLASH_DIE_MINOR_MINOR_Pos 0UL
+#define SFLASH_DIE_MINOR_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_DAY */
+#define SFLASH_DIE_DAY_MINOR_Pos 0UL
+#define SFLASH_DIE_DAY_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_MONTH */
+#define SFLASH_DIE_MONTH_MINOR_Pos 0UL
+#define SFLASH_DIE_MONTH_MINOR_Msk 0xFFUL
+/* SFLASH.DIE_YEAR */
+#define SFLASH_DIE_YEAR_MINOR_Pos 0UL
+#define SFLASH_DIE_YEAR_MINOR_Msk 0xFFUL
+/* SFLASH.SAR_TEMP_MULTIPLIER */
+#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Pos 0UL
+#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Msk 0xFFFFUL
+/* SFLASH.SAR_TEMP_OFFSET */
+#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Pos 0UL
+#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Msk 0xFFFFUL
+/* SFLASH.CSP_PANEL_ID */
+#define SFLASH_CSP_PANEL_ID_DATA32_Pos 0UL
+#define SFLASH_CSP_PANEL_ID_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.LDO_0P9V_TRIM */
+#define SFLASH_LDO_0P9V_TRIM_DATA8_Pos 0UL
+#define SFLASH_LDO_0P9V_TRIM_DATA8_Msk 0xFFUL
+/* SFLASH.LDO_1P1V_TRIM */
+#define SFLASH_LDO_1P1V_TRIM_DATA8_Pos 0UL
+#define SFLASH_LDO_1P1V_TRIM_DATA8_Msk 0xFFUL
+/* SFLASH.BLE_DEVICE_ADDRESS */
+#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos 0UL
+#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW1 */
+#define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW2 */
+#define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.USER_FREE_ROW3 */
+#define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL
+#define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.DEVICE_UID */
+#define SFLASH_DEVICE_UID_DATA8_Pos 0UL
+#define SFLASH_DEVICE_UID_DATA8_Msk 0xFFUL
+/* SFLASH.MASTER_KEY */
+#define SFLASH_MASTER_KEY_DATA8_Pos 0UL
+#define SFLASH_MASTER_KEY_DATA8_Msk 0xFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR */
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR */
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR */
+#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos 0UL
+#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_MPU_STRUCT */
+#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos 0UL
+#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.STANDARD_PPU_STRUCT */
+#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos 0UL
+#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.PILO_FREQ_STEP */
+#define SFLASH_PILO_FREQ_STEP_STEP_Pos 0UL
+#define SFLASH_PILO_FREQ_STEP_STEP_Msk 0xFFFFUL
+/* SFLASH.CSDV2_CSD0_ADC_VREF0 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Msk 0xFFFFUL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Pos 16UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Msk 0xFFFF0000UL
+/* SFLASH.CSDV2_CSD0_ADC_VREF1 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Msk 0xFFFFUL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Pos 16UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Msk 0xFFFF0000UL
+/* SFLASH.CSDV2_CSD0_ADC_VREF2 */
+#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Pos 0UL
+#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Msk 0xFFFFUL
+/* SFLASH.PWR_TRIM_WAKE_CTL */
+#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
+#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
+/* SFLASH.RADIO_LDO_TRIMS */
+#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos 0UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk 0xFUL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos 4UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk 0x30UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos 6UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk 0xC0UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos 8UL
+#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk 0x300UL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_ULP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_ULP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_ROM_CTL_LP */
+#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.CPUSS_TRIM_RAM_CTL_LP */
+#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Pos 0UL
+#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_OBJECT_SIZE */
+#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_APP_ID */
+#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL
+#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL
+#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL
+#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL
+#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL
+#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL
+/* SFLASH.FLASH_BOOT_ATTRIBUTE */
+#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_N_CORES */
+#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_VT_OFFSET */
+#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_CORE_CPUID */
+#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.FLASH_BOOT_CODE */
+#define SFLASH_FLASH_BOOT_CODE_DATA32_Pos 0UL
+#define SFLASH_FLASH_BOOT_CODE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.PUBLIC_KEY */
+#define SFLASH_PUBLIC_KEY_DATA_Pos 0UL
+#define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL
+/* SFLASH.BOOT_PROT_SETTINGS */
+#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Pos 0UL
+#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_OBJECT_SIZE */
+#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_MAGIC_NUMBER */
+#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_FHASH_OBJECTS */
+#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_SFLASH_GENERAL_TRIM_ADDR */
+#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_UNIQUE_ID_ADDR */
+#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_FB_OBJECT_ADDR */
+#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_SYSCALL_TABLE_ADDR */
+#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_BOOT_PROTECTION_ADDR */
+#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC1_CRC_ADDR */
+#define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_OBJECT_SIZE */
+#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_MAGIC_NUMBER */
+#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_FHASH_OBJECTS */
+#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_SFLASH_GENERAL_TRIM_ADDR */
+#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_UNIQUE_ID_ADDR */
+#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_FB_OBJECT_ADDR */
+#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR */
+#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC1_CRC_ADDR */
+#define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_OBJECT_SIZE */
+#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_MAGIC_NUMBER */
+#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_KEY_BLOCK_ADDR */
+#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */
+#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FIRST_USER_APP_ADDR */
+#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FIRST_USER_APP_FORMAT */
+#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SECOND_USER_APP_ADDR */
+#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SECOND_USER_APP_FORMAT */
+#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SHASH_OBJECTS */
+#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_SIGNATURE_VERIF_KEY */
+#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
+#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_FLAGS */
+#define SFLASH_TOC2_FLAGS_DATA32_Pos 0UL
+#define SFLASH_TOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.TOC2_CRC_ADDR */
+#define SFLASH_TOC2_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_TOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_OBJECT_SIZE */
+#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Pos 0UL
+#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_MAGIC_NUMBER */
+#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Pos 0UL
+#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_KEY_BLOCK_ADDR */
+#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SMIF_CFG_STRUCT_ADDR */
+#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FIRST_USER_APP_ADDR */
+#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FIRST_USER_APP_FORMAT */
+#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SECOND_USER_APP_ADDR */
+#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SECOND_USER_APP_FORMAT */
+#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SHASH_OBJECTS */
+#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_SIGNATURE_VERIF_KEY */
+#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
+#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_FLAGS */
+#define SFLASH_RTOC2_FLAGS_DATA32_Pos 0UL
+#define SFLASH_RTOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
+/* SFLASH.RTOC2_CRC_ADDR */
+#define SFLASH_RTOC2_CRC_ADDR_DATA32_Pos 0UL
+#define SFLASH_RTOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_SFLASH_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_smartio.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,107 @@
+/***************************************************************************//**
+* \file cyip_smartio.h
+*
+* \brief
+* SMARTIO IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SMARTIO_H_
+#define _CYIP_SMARTIO_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL
+#define SMARTIO_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Programmable IO port registers (SMARTIO_PRT)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control register */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
+ __IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
+ __IM uint32_t RESERVED2[24];
+ __IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
+ __IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t DATA; /*!< 0x000000F0 Data register */
+ __IM uint32_t RESERVED4[3];
+} SMARTIO_PRT_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief Programmable IO configuration (SMARTIO)
+ */
+typedef struct {
+ SMARTIO_PRT_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
+} SMARTIO_Type; /*!< Size = 32768 (0x8000) */
+
+
+/* SMARTIO_PRT.CTL */
+#define SMARTIO_PRT_CTL_BYPASS_Pos 0UL
+#define SMARTIO_PRT_CTL_BYPASS_Msk 0xFFUL
+#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos 8UL
+#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk 0x1F00UL
+#define SMARTIO_PRT_CTL_HLD_OVR_Pos 24UL
+#define SMARTIO_PRT_CTL_HLD_OVR_Msk 0x1000000UL
+#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos 25UL
+#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk 0x2000000UL
+#define SMARTIO_PRT_CTL_ENABLED_Pos 31UL
+#define SMARTIO_PRT_CTL_ENABLED_Msk 0x80000000UL
+/* SMARTIO_PRT.SYNC_CTL */
+#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos 0UL
+#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
+#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
+#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
+/* SMARTIO_PRT.LUT_SEL */
+#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
+/* SMARTIO_PRT.LUT_CTL */
+#define SMARTIO_PRT_LUT_CTL_LUT_Pos 0UL
+#define SMARTIO_PRT_LUT_CTL_LUT_Msk 0xFFUL
+#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos 8UL
+#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk 0x300UL
+/* SMARTIO_PRT.DU_SEL */
+#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos 0UL
+#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk 0xFUL
+#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos 8UL
+#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
+#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos 16UL
+#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos 24UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos 28UL
+#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
+/* SMARTIO_PRT.DU_CTL */
+#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos 0UL
+#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk 0x7UL
+#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos 8UL
+#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk 0xF00UL
+/* SMARTIO_PRT.DATA */
+#define SMARTIO_PRT_DATA_DATA_Pos 0UL
+#define SMARTIO_PRT_DATA_DATA_Msk 0xFFUL
+
+
+#endif /* _CYIP_SMARTIO_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_smif.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,376 @@
+/***************************************************************************//**
+* \file cyip_smif.h
+*
+* \brief
+* SMIF IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SMIF_H_
+#define _CYIP_SMIF_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SMIF
+*******************************************************************************/
+
+#define SMIF_DEVICE_SECTION_SIZE 0x00000080UL
+#define SMIF_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Device (only used in XIP mode) (SMIF_DEVICE)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */
+ __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */
+ __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */
+ __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */
+ __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */
+ __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */
+ __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */
+ __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */
+ __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */
+ __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */
+ __IM uint32_t RESERVED4[3];
+} SMIF_DEVICE_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Serial Memory Interface (SMIF)
+ */
+typedef struct {
+ __IOM uint32_t CTL; /*!< 0x00000000 Control */
+ __IM uint32_t STATUS; /*!< 0x00000004 Status */
+ __IM uint32_t RESERVED[15];
+ __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */
+ __IM uint32_t RESERVED2[11];
+ __IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */
+ __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */
+ __IM uint32_t RESERVED3[2];
+ __OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */
+ __OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */
+ __OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */
+ __IM uint32_t RESERVED4[9];
+ __IOM uint32_t RX_DATA_FIFO_CTL; /*!< 0x000000C0 Receiver data FIFO control */
+ __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C4 Receiver data FIFO status */
+ __IM uint32_t RESERVED5[2];
+ __IM uint32_t RX_DATA_FIFO_RD1; /*!< 0x000000D0 Receiver data FIFO read */
+ __IM uint32_t RX_DATA_FIFO_RD2; /*!< 0x000000D4 Receiver data FIFO read */
+ __IM uint32_t RX_DATA_FIFO_RD4; /*!< 0x000000D8 Receiver data FIFO read */
+ __IM uint32_t RESERVED6;
+ __IM uint32_t RX_DATA_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data FIFO silent read */
+ __IM uint32_t RESERVED7[7];
+ __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */
+ __IM uint32_t RESERVED9[29];
+ __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */
+ __IM uint32_t RESERVED11[29];
+ __IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */
+ __IM uint32_t RESERVED12[7];
+ __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */
+ __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */
+ __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */
+ __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */
+ __IM uint32_t RESERVED13[4];
+ __OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */
+ __OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */
+ __OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */
+ __OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */
+ __IM uint32_t RESERVED14[4];
+ __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */
+ __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */
+ __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */
+ __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */
+ __IM uint32_t RESERVED15[340];
+ __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */
+ __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */
+ __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */
+ __IM uint32_t RESERVED16[12];
+ SMIF_DEVICE_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */
+} SMIF_Type; /*!< Size = 2560 (0xA00) */
+
+
+/* SMIF_DEVICE.CTL */
+#define SMIF_DEVICE_CTL_WR_EN_Pos 0UL
+#define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL
+#define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 8UL
+#define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x100UL
+#define SMIF_DEVICE_CTL_DATA_SEL_Pos 16UL
+#define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x30000UL
+#define SMIF_DEVICE_CTL_ENABLED_Pos 31UL
+#define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF_DEVICE.ADDR */
+#define SMIF_DEVICE_ADDR_ADDR_Pos 8UL
+#define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL
+/* SMIF_DEVICE.MASK */
+#define SMIF_DEVICE_MASK_MASK_Pos 8UL
+#define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL
+/* SMIF_DEVICE.ADDR_CTL */
+#define SMIF_DEVICE_ADDR_CTL_SIZE2_Pos 0UL
+#define SMIF_DEVICE_ADDR_CTL_SIZE2_Msk 0x3UL
+#define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL
+#define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL
+/* SMIF_DEVICE.RD_CMD_CTL */
+#define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_ADDR_CTL */
+#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.RD_MODE_CTL */
+#define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_DUMMY_CTL */
+#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL
+#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL
+#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.RD_DATA_CTL */
+#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.WR_CMD_CTL */
+#define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_ADDR_CTL */
+#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL
+/* SMIF_DEVICE.WR_MODE_CTL */
+#define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL
+#define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL
+#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL
+#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_DUMMY_CTL */
+#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL
+#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL
+#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Pos 31UL
+#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk 0x80000000UL
+/* SMIF_DEVICE.WR_DATA_CTL */
+#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL
+#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL
+
+
+/* SMIF.CTL */
+#define SMIF_CTL_XIP_MODE_Pos 0UL
+#define SMIF_CTL_XIP_MODE_Msk 0x1UL
+#define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL
+#define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x3000UL
+#define SMIF_CTL_DESELECT_DELAY_Pos 16UL
+#define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL
+#define SMIF_CTL_BLOCK_Pos 24UL
+#define SMIF_CTL_BLOCK_Msk 0x1000000UL
+#define SMIF_CTL_ENABLED_Pos 31UL
+#define SMIF_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.STATUS */
+#define SMIF_STATUS_BUSY_Pos 31UL
+#define SMIF_STATUS_BUSY_Msk 0x80000000UL
+/* SMIF.TX_CMD_FIFO_STATUS */
+#define SMIF_TX_CMD_FIFO_STATUS_USED3_Pos 0UL
+#define SMIF_TX_CMD_FIFO_STATUS_USED3_Msk 0x7UL
+/* SMIF.TX_CMD_FIFO_WR */
+#define SMIF_TX_CMD_FIFO_WR_DATA20_Pos 0UL
+#define SMIF_TX_CMD_FIFO_WR_DATA20_Msk 0xFFFFFUL
+/* SMIF.TX_DATA_FIFO_CTL */
+#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
+/* SMIF.TX_DATA_FIFO_STATUS */
+#define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL
+#define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
+/* SMIF.TX_DATA_FIFO_WR1 */
+#define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk 0xFFUL
+/* SMIF.TX_DATA_FIFO_WR2 */
+#define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk 0xFFUL
+#define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos 8UL
+#define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk 0xFF00UL
+/* SMIF.TX_DATA_FIFO_WR4 */
+#define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos 0UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk 0xFFUL
+#define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos 8UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk 0xFF00UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos 16UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk 0xFF0000UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos 24UL
+#define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk 0xFF000000UL
+/* SMIF.RX_DATA_FIFO_CTL */
+#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
+#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
+/* SMIF.RX_DATA_FIFO_STATUS */
+#define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos 0UL
+#define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
+/* SMIF.RX_DATA_FIFO_RD1 */
+#define SMIF_RX_DATA_FIFO_RD1_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD1_DATA0_Msk 0xFFUL
+/* SMIF.RX_DATA_FIFO_RD2 */
+#define SMIF_RX_DATA_FIFO_RD2_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD2_DATA0_Msk 0xFFUL
+#define SMIF_RX_DATA_FIFO_RD2_DATA1_Pos 8UL
+#define SMIF_RX_DATA_FIFO_RD2_DATA1_Msk 0xFF00UL
+/* SMIF.RX_DATA_FIFO_RD4 */
+#define SMIF_RX_DATA_FIFO_RD4_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA0_Msk 0xFFUL
+#define SMIF_RX_DATA_FIFO_RD4_DATA1_Pos 8UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA1_Msk 0xFF00UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA2_Pos 16UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA2_Msk 0xFF0000UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA3_Pos 24UL
+#define SMIF_RX_DATA_FIFO_RD4_DATA3_Msk 0xFF000000UL
+/* SMIF.RX_DATA_FIFO_RD1_SILENT */
+#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Pos 0UL
+#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL
+/* SMIF.SLOW_CA_CTL */
+#define SMIF_SLOW_CA_CTL_WAY_Pos 16UL
+#define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL
+#define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL
+#define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL
+#define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL
+#define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL
+#define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL
+#define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.SLOW_CA_CMD */
+#define SMIF_SLOW_CA_CMD_INV_Pos 0UL
+#define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL
+/* SMIF.FAST_CA_CTL */
+#define SMIF_FAST_CA_CTL_WAY_Pos 16UL
+#define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL
+#define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL
+#define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL
+#define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL
+#define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL
+#define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL
+#define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL
+/* SMIF.FAST_CA_CMD */
+#define SMIF_FAST_CA_CMD_INV_Pos 0UL
+#define SMIF_FAST_CA_CMD_INV_Msk 0x1UL
+/* SMIF.CRYPTO_CMD */
+#define SMIF_CRYPTO_CMD_START_Pos 0UL
+#define SMIF_CRYPTO_CMD_START_Msk 0x1UL
+/* SMIF.CRYPTO_INPUT0 */
+#define SMIF_CRYPTO_INPUT0_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT0_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT1 */
+#define SMIF_CRYPTO_INPUT1_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT2 */
+#define SMIF_CRYPTO_INPUT2_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_INPUT3 */
+#define SMIF_CRYPTO_INPUT3_INPUT_Pos 0UL
+#define SMIF_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY0 */
+#define SMIF_CRYPTO_KEY0_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY1 */
+#define SMIF_CRYPTO_KEY1_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY2 */
+#define SMIF_CRYPTO_KEY2_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_KEY3 */
+#define SMIF_CRYPTO_KEY3_KEY_Pos 0UL
+#define SMIF_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT0 */
+#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT1 */
+#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT2 */
+#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.CRYPTO_OUTPUT3 */
+#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL
+#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL
+/* SMIF.INTR */
+#define SMIF_INTR_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_SET */
+#define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_MASK */
+#define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+/* SMIF.INTR_MASKED */
+#define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL
+#define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL
+#define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL
+#define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL
+#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL
+#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL
+#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL
+#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
+#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL
+#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
+#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
+#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
+
+
+#endif /* _CYIP_SMIF_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_srss.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,599 @@
+/***************************************************************************//**
+* \file cyip_srss.h
+*
+* \brief
+* SRSS IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_SRSS_H_
+#define _CYIP_SRSS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* SRSS
+*******************************************************************************/
+
+#define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL
+#define SRSS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Multi-Counter Watchdog Timer (MCWDT_STRUCT)
+ */
+typedef struct {
+ __IM uint32_t RESERVED;
+ __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */
+ __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */
+ __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */
+ __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */
+ __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */
+ __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */
+ __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */
+ __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */
+ __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */
+ __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */
+ __IM uint32_t RESERVED1[5];
+} MCWDT_STRUCT_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief SRSS Core Registers (SRSS)
+ */
+typedef struct {
+ __IOM uint32_t PWR_CTL; /*!< 0x00000000 Power Mode Control */
+ __IOM uint32_t PWR_HIBERNATE; /*!< 0x00000004 HIBERNATE Mode Register */
+ __IOM uint32_t PWR_LVD_CTL; /*!< 0x00000008 Low Voltage Detector (LVD) Configuration Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00000014 Buck Control Register */
+ __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00000018 Buck Control Register 2 */
+ __IM uint32_t PWR_LVD_STATUS; /*!< 0x0000001C Low Voltage Detector (LVD) Status Register */
+ __IM uint32_t RESERVED1[24];
+ __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000080 HIBERNATE Data Register */
+ __IM uint32_t RESERVED2[48];
+ __IOM uint32_t WDT_CTL; /*!< 0x00000180 Watchdog Counter Control Register */
+ __IOM uint32_t WDT_CNT; /*!< 0x00000184 Watchdog Counter Count Register */
+ __IOM uint32_t WDT_MATCH; /*!< 0x00000188 Watchdog Counter Match Register */
+ __IM uint32_t RESERVED3[29];
+ MCWDT_STRUCT_Type MCWDT_STRUCT[4]; /*!< 0x00000200 Multi-Counter Watchdog Timer */
+ __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000300 Clock DSI Select Register */
+ __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00000340 Clock Path Select Register */
+ __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00000380 Clock Root Select Register */
+ __IM uint32_t RESERVED4[80];
+ __IOM uint32_t CLK_SELECT; /*!< 0x00000500 Clock selection register */
+ __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00000504 Timer Clock Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x0000050C ILO Configuration */
+ __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00000510 IMO Configuration */
+ __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000514 Fast Clock Output Select Register */
+ __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000518 Slow Clock Output Select Register */
+ __IOM uint32_t CLK_CAL_CNT1; /*!< 0x0000051C Clock Calibration Counter 1 */
+ __IM uint32_t CLK_CAL_CNT2; /*!< 0x00000520 Clock Calibration Counter 2 */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000052C ECO Configuration Register */
+ __IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */
+ __IM uint32_t RESERVED7[2];
+ __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */
+ __IM uint32_t RESERVED8[16];
+ __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */
+ __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */
+ __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */
+ __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */
+ __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */
+ __IM uint32_t RESERVED9[27];
+ __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */
+ __IM uint32_t RESERVED11[33];
+ __IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */
+ __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */
+ __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */
+ __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */
+ __IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */
+ __IM uint32_t RESERVED12[59];
+ __IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */
+ __IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */
+ __IM uint32_t RESERVED13[7614];
+ __IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */
+ __IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */
+ __IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */
+ __IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */
+ __IM uint32_t RESERVED14[8];
+ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */
+ __IM uint32_t RESERVED15[8183];
+ __IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */
+ __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */
+ __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */
+ __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x0000FF24 PILO Trim Register */
+ __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x0000FF28 PILO Trim Register 2 */
+ __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000FF2C PILO Trim Register 3 */
+} SRSS_Type; /*!< Size = 65328 (0xFF30) */
+
+
+/* MCWDT_STRUCT.MCWDT_CNTLOW */
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL
+/* MCWDT_STRUCT.MCWDT_CNTHIGH */
+#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL
+/* MCWDT_STRUCT.MCWDT_MATCH */
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL
+/* MCWDT_STRUCT.MCWDT_CONFIG */
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL
+#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL
+/* MCWDT_STRUCT.MCWDT_CTL */
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL
+#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL
+/* MCWDT_STRUCT.MCWDT_INTR */
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_SET */
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_MASK */
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_INTR_MASKED */
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL
+#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL
+/* MCWDT_STRUCT.MCWDT_LOCK */
+#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL
+#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL
+
+
+/* SRSS.PWR_CTL */
+#define SRSS_PWR_CTL_POWER_MODE_Pos 0UL
+#define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL
+#define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL
+#define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL
+#define SRSS_PWR_CTL_LPM_READY_Pos 5UL
+#define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL
+#define SRSS_PWR_CTL_IREF_LPMODE_Pos 18UL
+#define SRSS_PWR_CTL_IREF_LPMODE_Msk 0x40000UL
+#define SRSS_PWR_CTL_VREFBUF_OK_Pos 19UL
+#define SRSS_PWR_CTL_VREFBUF_OK_Msk 0x80000UL
+#define SRSS_PWR_CTL_DPSLP_REG_DIS_Pos 20UL
+#define SRSS_PWR_CTL_DPSLP_REG_DIS_Msk 0x100000UL
+#define SRSS_PWR_CTL_RET_REG_DIS_Pos 21UL
+#define SRSS_PWR_CTL_RET_REG_DIS_Msk 0x200000UL
+#define SRSS_PWR_CTL_NWELL_REG_DIS_Pos 22UL
+#define SRSS_PWR_CTL_NWELL_REG_DIS_Msk 0x400000UL
+#define SRSS_PWR_CTL_LINREG_DIS_Pos 23UL
+#define SRSS_PWR_CTL_LINREG_DIS_Msk 0x800000UL
+#define SRSS_PWR_CTL_LINREG_LPMODE_Pos 24UL
+#define SRSS_PWR_CTL_LINREG_LPMODE_Msk 0x1000000UL
+#define SRSS_PWR_CTL_PORBOD_LPMODE_Pos 25UL
+#define SRSS_PWR_CTL_PORBOD_LPMODE_Msk 0x2000000UL
+#define SRSS_PWR_CTL_BGREF_LPMODE_Pos 26UL
+#define SRSS_PWR_CTL_BGREF_LPMODE_Msk 0x4000000UL
+#define SRSS_PWR_CTL_PLL_LS_BYPASS_Pos 27UL
+#define SRSS_PWR_CTL_PLL_LS_BYPASS_Msk 0x8000000UL
+#define SRSS_PWR_CTL_VREFBUF_LPMODE_Pos 28UL
+#define SRSS_PWR_CTL_VREFBUF_LPMODE_Msk 0x10000000UL
+#define SRSS_PWR_CTL_VREFBUF_DIS_Pos 29UL
+#define SRSS_PWR_CTL_VREFBUF_DIS_Msk 0x20000000UL
+#define SRSS_PWR_CTL_ACT_REF_DIS_Pos 30UL
+#define SRSS_PWR_CTL_ACT_REF_DIS_Msk 0x40000000UL
+#define SRSS_PWR_CTL_ACT_REF_OK_Pos 31UL
+#define SRSS_PWR_CTL_ACT_REF_OK_Msk 0x80000000UL
+/* SRSS.PWR_HIBERNATE */
+#define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL
+#define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL
+#define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL
+#define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL
+#define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL
+#define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL
+#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL
+#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL
+#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL
+#define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL
+/* SRSS.PWR_LVD_CTL */
+#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL
+#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL
+#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL
+/* SRSS.PWR_BUCK_CTL */
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL
+#define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL
+#define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL
+#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL
+/* SRSS.PWR_BUCK_CTL2 */
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL
+#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL
+/* SRSS.PWR_LVD_STATUS */
+#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL
+#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL
+/* SRSS.PWR_HIB_DATA */
+#define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL
+#define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL
+/* SRSS.WDT_CTL */
+#define SRSS_WDT_CTL_WDT_EN_Pos 0UL
+#define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL
+#define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL
+#define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL
+/* SRSS.WDT_CNT */
+#define SRSS_WDT_CNT_COUNTER_Pos 0UL
+#define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFUL
+/* SRSS.WDT_MATCH */
+#define SRSS_WDT_MATCH_MATCH_Pos 0UL
+#define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFUL
+#define SRSS_WDT_MATCH_IGNORE_BITS_Pos 16UL
+#define SRSS_WDT_MATCH_IGNORE_BITS_Msk 0xF0000UL
+/* SRSS.CLK_DSI_SELECT */
+#define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL
+#define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL
+/* SRSS.CLK_PATH_SELECT */
+#define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL
+#define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL
+/* SRSS.CLK_ROOT_SELECT */
+#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL
+#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL
+#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL
+#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL
+#define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL
+#define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_SELECT */
+#define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL
+#define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x3UL
+#define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL
+#define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL
+#define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL
+#define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL
+#define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL
+#define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL
+/* SRSS.CLK_TIMER_CTL */
+#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL
+#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL
+#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL
+#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL
+#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL
+#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL
+#define SRSS_CLK_TIMER_CTL_ENABLE_Pos 31UL
+#define SRSS_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_ILO_CONFIG */
+#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL
+#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL
+#define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_IMO_CONFIG */
+#define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_OUTPUT_FAST */
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL
+#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL
+#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL
+#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL
+/* SRSS.CLK_OUTPUT_SLOW */
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL
+#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL
+/* SRSS.CLK_CAL_CNT1 */
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL
+#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL
+/* SRSS.CLK_CAL_CNT2 */
+#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL
+#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL
+/* SRSS.CLK_ECO_CONFIG */
+#define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL
+#define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL
+#define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL
+#define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL
+/* SRSS.CLK_ECO_STATUS */
+#define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL
+#define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL
+#define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL
+#define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL
+/* SRSS.CLK_PILO_CONFIG */
+#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL
+#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL
+#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL
+#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL
+#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL
+#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL
+#define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL
+#define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL
+/* SRSS.CLK_FLL_CONFIG */
+#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL
+#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL
+#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL
+#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL
+#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_FLL_CONFIG2 */
+#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL
+#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL
+#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0x1FF0000UL
+/* SRSS.CLK_FLL_CONFIG3 */
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL
+#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL
+#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL
+#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL
+#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL
+#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL
+/* SRSS.CLK_FLL_CONFIG4 */
+#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL
+#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL
+#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_FLL_STATUS */
+#define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL
+#define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL
+#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
+#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
+#define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL
+#define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL
+/* SRSS.CLK_PLL_CONFIG */
+#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL
+#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL
+#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL
+#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL
+#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL
+#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL
+#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL
+#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL
+#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL
+#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL
+#define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL
+#define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL
+/* SRSS.CLK_PLL_STATUS */
+#define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL
+#define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL
+#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
+#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
+/* SRSS.SRSS_INTR */
+#define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_SET */
+#define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_MASK */
+#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_MASKED */
+#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL
+#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL
+#define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL
+#define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL
+#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL
+#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL
+/* SRSS.SRSS_INTR_CFG */
+#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Pos 0UL
+#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Msk 0x3UL
+/* SRSS.RES_CAUSE */
+#define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL
+#define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL
+#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL
+#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL
+#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL
+#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL
+#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Pos 3UL
+#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Msk 0x8UL
+#define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL
+#define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL
+#define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL
+#define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL
+#define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL
+#define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL
+#define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL
+#define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL
+#define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL
+#define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL
+/* SRSS.RES_CAUSE2 */
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos 0UL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk 0xFFFFUL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos 16UL
+#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk 0xFFFF0000UL
+/* SRSS.PWR_TRIM_REF_CTL */
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Pos 0UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Msk 0xFUL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Pos 4UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Msk 0xF0UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Pos 8UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Msk 0x1F00UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Pos 14UL
+#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Msk 0x4000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Pos 16UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Msk 0xF0000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Pos 20UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Msk 0x1F00000UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Pos 28UL
+#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Msk 0xF0000000UL
+/* SRSS.PWR_TRIM_BODOVP_CTL */
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Pos 0UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Msk 0x7UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Pos 4UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Msk 0x70UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Pos 7UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Msk 0x380UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Pos 10UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Msk 0x1C00UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Pos 14UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Msk 0x1C000UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Pos 17UL
+#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Msk 0xE0000UL
+/* SRSS.CLK_TRIM_CCO_CTL */
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Msk 0x3FUL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Pos 24UL
+#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Msk 0x3F000000UL
+#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Pos 31UL
+#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Msk 0x80000000UL
+/* SRSS.CLK_TRIM_CCO_CTL2 */
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Pos 0UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Msk 0x1FUL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Pos 5UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Msk 0x3E0UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Pos 10UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Msk 0x7C00UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Pos 15UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Msk 0xF8000UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Pos 20UL
+#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Msk 0x1F00000UL
+/* SRSS.PWR_TRIM_WAKE_CTL */
+#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
+#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
+/* SRSS.PWR_TRIM_LVD_CTL */
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Pos 0UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Msk 0x7UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Pos 4UL
+#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Msk 0x70UL
+/* SRSS.CLK_TRIM_ILO_CTL */
+#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL
+/* SRSS.PWR_TRIM_PWRSYS_CTL */
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL
+#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL
+/* SRSS.CLK_TRIM_ECO_CTL */
+#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos 0UL
+#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk 0x7UL
+#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Pos 4UL
+#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk 0xF0UL
+#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Pos 8UL
+#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk 0x300UL
+#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Pos 10UL
+#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk 0xC00UL
+#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Pos 12UL
+#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk 0x3000UL
+#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL
+#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL
+/* SRSS.CLK_TRIM_PILO_CTL */
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL
+#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL
+/* SRSS.CLK_TRIM_PILO_CTL2 */
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL
+#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL
+/* SRSS.CLK_TRIM_PILO_CTL3 */
+#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL
+#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL
+
+
+#endif /* _CYIP_SRSS_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_tcpwm.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,189 @@
+/***************************************************************************//**
+* \file cyip_tcpwm.h
+*
+* \brief
+* TCPWM IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_TCPWM_H_
+#define _CYIP_TCPWM_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* TCPWM
+*******************************************************************************/
+
+#define TCPWM_CNT_SECTION_SIZE 0x00000040UL
+#define TCPWM_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief Timer/Counter/PWM Counter Module (TCPWM_CNT)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */
+ __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */
+ __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */
+ __IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */
+ __IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */
+ __IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */
+ __IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */
+ __IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */
+ __IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */
+ __IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */
+ __IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */
+ __IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */
+} TCPWM_CNT_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief Timer/Counter/PWM (TCPWM)
+ */
+typedef struct {
+ __IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */
+ __IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */
+ __IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */
+ __IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */
+ __IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */
+ __IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */
+ __IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */
+ __IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */
+ __IM uint32_t RESERVED[56];
+ TCPWM_CNT_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */
+} TCPWM_Type; /*!< Size = 2304 (0x900) */
+
+
+/* TCPWM_CNT.CTRL */
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos 0UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk 0x1UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 1UL
+#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x2UL
+#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos 2UL
+#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk 0x4UL
+#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos 3UL
+#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x8UL
+#define TCPWM_CNT_CTRL_GENERIC_Pos 8UL
+#define TCPWM_CNT_CTRL_GENERIC_Msk 0xFF00UL
+#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos 16UL
+#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL
+#define TCPWM_CNT_CTRL_ONE_SHOT_Pos 18UL
+#define TCPWM_CNT_CTRL_ONE_SHOT_Msk 0x40000UL
+#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos 20UL
+#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk 0x300000UL
+#define TCPWM_CNT_CTRL_MODE_Pos 24UL
+#define TCPWM_CNT_CTRL_MODE_Msk 0x7000000UL
+/* TCPWM_CNT.STATUS */
+#define TCPWM_CNT_STATUS_DOWN_Pos 0UL
+#define TCPWM_CNT_STATUS_DOWN_Msk 0x1UL
+#define TCPWM_CNT_STATUS_GENERIC_Pos 8UL
+#define TCPWM_CNT_STATUS_GENERIC_Msk 0xFF00UL
+#define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
+#define TCPWM_CNT_STATUS_RUNNING_Msk 0x80000000UL
+/* TCPWM_CNT.COUNTER */
+#define TCPWM_CNT_COUNTER_COUNTER_Pos 0UL
+#define TCPWM_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.CC */
+#define TCPWM_CNT_CC_CC_Pos 0UL
+#define TCPWM_CNT_CC_CC_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.CC_BUFF */
+#define TCPWM_CNT_CC_BUFF_CC_Pos 0UL
+#define TCPWM_CNT_CC_BUFF_CC_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.PERIOD */
+#define TCPWM_CNT_PERIOD_PERIOD_Pos 0UL
+#define TCPWM_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.PERIOD_BUFF */
+#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos 0UL
+#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL
+/* TCPWM_CNT.TR_CTRL0 */
+#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos 0UL
+#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk 0xFUL
+#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos 4UL
+#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk 0xF0UL
+#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos 8UL
+#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk 0xF00UL
+#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos 12UL
+#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk 0xF000UL
+#define TCPWM_CNT_TR_CTRL0_START_SEL_Pos 16UL
+#define TCPWM_CNT_TR_CTRL0_START_SEL_Msk 0xF0000UL
+/* TCPWM_CNT.TR_CTRL1 */
+#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos 0UL
+#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk 0x3UL
+#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos 2UL
+#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk 0xCUL
+#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos 4UL
+#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk 0x30UL
+#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos 6UL
+#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk 0xC0UL
+#define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos 8UL
+#define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk 0x300UL
+/* TCPWM_CNT.TR_CTRL2 */
+#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos 0UL
+#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk 0x3UL
+#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos 2UL
+#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk 0xCUL
+#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos 4UL
+#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk 0x30UL
+/* TCPWM_CNT.INTR */
+#define TCPWM_CNT_INTR_TC_Pos 0UL
+#define TCPWM_CNT_INTR_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_SET */
+#define TCPWM_CNT_INTR_SET_TC_Pos 0UL
+#define TCPWM_CNT_INTR_SET_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_SET_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_SET_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_MASK */
+#define TCPWM_CNT_INTR_MASK_TC_Pos 0UL
+#define TCPWM_CNT_INTR_MASK_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk 0x2UL
+/* TCPWM_CNT.INTR_MASKED */
+#define TCPWM_CNT_INTR_MASKED_TC_Pos 0UL
+#define TCPWM_CNT_INTR_MASKED_TC_Msk 0x1UL
+#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos 1UL
+#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk 0x2UL
+
+
+/* TCPWM.CTRL */
+#define TCPWM_CTRL_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CTRL_CLR */
+#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CTRL_SET */
+#define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos 0UL
+#define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_CAPTURE */
+#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos 0UL
+#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_RELOAD */
+#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos 0UL
+#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_STOP */
+#define TCPWM_CMD_STOP_COUNTER_STOP_Pos 0UL
+#define TCPWM_CMD_STOP_COUNTER_STOP_Msk 0xFFFFFFFFUL
+/* TCPWM.CMD_START */
+#define TCPWM_CMD_START_COUNTER_START_Pos 0UL
+#define TCPWM_CMD_START_COUNTER_START_Msk 0xFFFFFFFFUL
+/* TCPWM.INTR_CAUSE */
+#define TCPWM_INTR_CAUSE_COUNTER_INT_Pos 0UL
+#define TCPWM_INTR_CAUSE_COUNTER_INT_Msk 0xFFFFFFFFUL
+
+
+#endif /* _CYIP_TCPWM_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_udb.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2024 @@
+/***************************************************************************//**
+* \file cyip_udb.h
+*
+* \brief
+* UDB IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_UDB_H_
+#define _CYIP_UDB_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* UDB
+*******************************************************************************/
+
+#define UDB_WRKONE_SECTION_SIZE 0x00000800UL
+#define UDB_WRKMULT_SECTION_SIZE 0x00001000UL
+#define UDB_UDBPAIR_UDBSNG_SECTION_SIZE 0x00000080UL
+#define UDB_UDBPAIR_ROUTE_SECTION_SIZE 0x00000100UL
+#define UDB_UDBPAIR_SECTION_SIZE 0x00000200UL
+#define UDB_DSI_SECTION_SIZE 0x00000080UL
+#define UDB_PA_SECTION_SIZE 0x00000040UL
+#define UDB_BCTL_SECTION_SIZE 0x00000080UL
+#define UDB_UDBIF_SECTION_SIZE 0x00000020UL
+#define UDB_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief UDB Working Registers (2 registers from one UDB at a time) (UDB_WRKONE)
+ */
+typedef struct {
+ __IOM uint32_t A[64]; /*!< 0x00000000 Accumulator Registers {A1,A0} */
+ __IOM uint32_t D[64]; /*!< 0x00000100 Data Registers {D1,D0} */
+ __IOM uint32_t F[64]; /*!< 0x00000200 FIFOs {F1,F0} */
+ __IOM uint32_t CTL_ST[64]; /*!< 0x00000300 Status and Control Registers {CTL,ST} */
+ __IOM uint32_t ACTL_MSK[64]; /*!< 0x00000400 Mask and Auxiliary Control Registers {ACTL,MSK} */
+ __IM uint32_t MC[64]; /*!< 0x00000500 PLD Macrocell Read Registers {00,MC} */
+ __IM uint32_t RESERVED[128];
+} UDB_WRKONE_Type; /*!< Size = 2048 (0x800) */
+
+/**
+ * \brief UDB Working Registers (1 register from multiple UDBs at a time) (UDB_WRKMULT)
+ */
+typedef struct {
+ __IOM uint32_t A0[64]; /*!< 0x00000000 Accumulator 0 */
+ __IOM uint32_t A1[64]; /*!< 0x00000100 Accumulator 1 */
+ __IOM uint32_t D0[64]; /*!< 0x00000200 Data 0 */
+ __IOM uint32_t D1[64]; /*!< 0x00000300 Data 1 */
+ __IOM uint32_t F0[64]; /*!< 0x00000400 FIFO 0 */
+ __IOM uint32_t F1[64]; /*!< 0x00000500 FIFO 1 */
+ __IM uint32_t ST[64]; /*!< 0x00000600 Status Register */
+ __IOM uint32_t CTL[64]; /*!< 0x00000700 Control Register */
+ __IOM uint32_t MSK[64]; /*!< 0x00000800 Interrupt Mask */
+ __IOM uint32_t ACTL[64]; /*!< 0x00000900 Auxiliary Control */
+ __IM uint32_t MC[64]; /*!< 0x00000A00 PLD Macrocell reading */
+ __IM uint32_t RESERVED[320];
+} UDB_WRKMULT_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief Single UDB Configuration (UDB_UDBPAIR_UDBSNG)
+ */
+typedef struct {
+ __IOM uint32_t PLD_IT[12]; /*!< 0x00000000 PLD Input Terms */
+ __IOM uint32_t PLD_ORT0; /*!< 0x00000030 PLD OR Terms */
+ __IOM uint32_t PLD_ORT1; /*!< 0x00000034 PLD OR Terms */
+ __IOM uint32_t PLD_CFG0; /*!< 0x00000038 PLD configuration for Carry Enable, Constant, and XOR feedback */
+ __IOM uint32_t PLD_CFG1; /*!< 0x0000003C PLD configuration for Set / Reset selection, and Bypass control */
+ __IOM uint32_t DPATH_CFG0; /*!< 0x00000040 Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD,
+ D0_LD, D1_LD) */
+ __IOM uint32_t DPATH_CFG1; /*!< 0x00000044 Datapath input and output selections (SCI_MUX, SI_MUX, OUT0
+ thru OUT5) */
+ __IOM uint32_t DPATH_CFG2; /*!< 0x00000048 Datapath output synchronization, ALU mask, compare 0 and 1
+ masks */
+ __IOM uint32_t DPATH_CFG3; /*!< 0x0000004C Datapath mask enables, shift in, carry in, compare, chaining,
+ MSB configs; FIFO, shift and parallel input control */
+ __IOM uint32_t DPATH_CFG4; /*!< 0x00000050 Datapath FIFO and register access configuration control */
+ __IOM uint32_t SC_CFG0; /*!< 0x00000054 SC Mode 0 and 1 control registers; status register input mode;
+ general SC configuration */
+ __IOM uint32_t SC_CFG1; /*!< 0x00000058 SC counter control */
+ __IOM uint32_t RC_CFG0; /*!< 0x0000005C PLD0, PLD1, Datatpath, and SC clock and reset control */
+ __IOM uint32_t RC_CFG1; /*!< 0x00000060 PLD0, PLD1, Datatpath, and SC clock selection, general reset
+ control */
+ __IOM uint32_t DPATH_OPC[4]; /*!< 0x00000064 Datapath opcode configuration */
+ __IM uint32_t RESERVED[3];
+} UDB_UDBPAIR_UDBSNG_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Routing Configuration for one UDB Pair (UDB_UDBPAIR_ROUTE)
+ */
+typedef struct {
+ __IOM uint32_t TOP_V_BOT; /*!< 0x00000000 Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing */
+ __IOM uint32_t LVO1_V_2; /*!< 0x00000004 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals */
+ __IOM uint32_t RVO1_V_2; /*!< 0x00000008 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain
+ horizontals */
+ __IOM uint32_t TUI_CFG0; /*!< 0x0000000C Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG1; /*!< 0x00000010 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG2; /*!< 0x00000014 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG3; /*!< 0x00000018 Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG4; /*!< 0x0000001C Top UDB Input (TUI) selection */
+ __IOM uint32_t TUI_CFG5; /*!< 0x00000020 Top UDB Input (TUI) selection */
+ __IOM uint32_t BUI_CFG0; /*!< 0x00000024 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG1; /*!< 0x00000028 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG2; /*!< 0x0000002C Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG3; /*!< 0x00000030 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG4; /*!< 0x00000034 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t BUI_CFG5; /*!< 0x00000038 Bottom UDB Input (BUI) selection */
+ __IOM uint32_t RVO_CFG0; /*!< 0x0000003C Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG1; /*!< 0x00000040 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG2; /*!< 0x00000044 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG3; /*!< 0x00000048 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t LVO_CFG0; /*!< 0x0000004C Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t LVO_CFG1; /*!< 0x00000050 Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t RHO_CFG0; /*!< 0x00000054 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG1; /*!< 0x00000058 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG2; /*!< 0x0000005C Right Horizontal Out (RHO) selection */
+ __IOM uint32_t LHO_CFG0; /*!< 0x00000060 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG1; /*!< 0x00000064 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG2; /*!< 0x00000068 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG3; /*!< 0x0000006C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG4; /*!< 0x00000070 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG5; /*!< 0x00000074 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG6; /*!< 0x00000078 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG7; /*!< 0x0000007C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG8; /*!< 0x00000080 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG9; /*!< 0x00000084 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG10; /*!< 0x00000088 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG11; /*!< 0x0000008C Left Horizontal Out (LHO) selection */
+ __IM uint32_t RESERVED[28];
+} UDB_UDBPAIR_ROUTE_Type; /*!< Size = 256 (0x100) */
+
+/**
+ * \brief UDB Pair Configuration (up to 32 Pairs) (UDB_UDBPAIR)
+ */
+typedef struct {
+ UDB_UDBPAIR_UDBSNG_Type UDBSNG[2]; /*!< 0x00000000 Single UDB Configuration */
+ UDB_UDBPAIR_ROUTE_Type ROUTE; /*!< 0x00000100 Routing Configuration for one UDB Pair */
+} UDB_UDBPAIR_Type; /*!< Size = 512 (0x200) */
+
+/**
+ * \brief DSI Configuration (up to 32 DSI) (UDB_DSI)
+ */
+typedef struct {
+ __IOM uint32_t LVO1_V_2; /*!< 0x00000000 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals */
+ __IOM uint32_t RVO1_V_2; /*!< 0x00000004 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain
+ horizontals */
+ __IOM uint32_t DOP_CFG0; /*!< 0x00000008 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG1; /*!< 0x0000000C DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG2; /*!< 0x00000010 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOP_CFG3; /*!< 0x00000014 DSI Out Pair (DOP) selection */
+ __IOM uint32_t DOT_CFG0; /*!< 0x00000018 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG1; /*!< 0x0000001C DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG2; /*!< 0x00000020 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t DOT_CFG3; /*!< 0x00000024 DSI Out Triplet (DOT) selection */
+ __IOM uint32_t RVO_CFG0; /*!< 0x00000028 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG1; /*!< 0x0000002C Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG2; /*!< 0x00000030 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t RVO_CFG3; /*!< 0x00000034 Right Vertical Ouput (RVO) selection */
+ __IOM uint32_t LVO_CFG0; /*!< 0x00000038 Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t LVO_CFG1; /*!< 0x0000003C Left Vertical Ouput (LVO) selection */
+ __IOM uint32_t RHO_CFG0; /*!< 0x00000040 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG1; /*!< 0x00000044 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t RHO_CFG2; /*!< 0x00000048 Right Horizontal Out (RHO) selection */
+ __IOM uint32_t LHO_CFG0; /*!< 0x0000004C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG1; /*!< 0x00000050 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG2; /*!< 0x00000054 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG3; /*!< 0x00000058 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG4; /*!< 0x0000005C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG5; /*!< 0x00000060 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG6; /*!< 0x00000064 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG7; /*!< 0x00000068 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG8; /*!< 0x0000006C Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG9; /*!< 0x00000070 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG10; /*!< 0x00000074 Left Horizontal Out (LHO) selection */
+ __IOM uint32_t LHO_CFG11; /*!< 0x00000078 Left Horizontal Out (LHO) selection */
+ __IM uint32_t RESERVED;
+} UDB_DSI_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief Port Adapter Configuration (up to 32 PA) (UDB_PA)
+ */
+typedef struct {
+ __IOM uint32_t CFG0; /*!< 0x00000000 PA Data In Clock Control Register */
+ __IOM uint32_t CFG1; /*!< 0x00000004 PA Data Out Clock Control Register */
+ __IOM uint32_t CFG2; /*!< 0x00000008 PA Clock Select Register */
+ __IOM uint32_t CFG3; /*!< 0x0000000C PA Reset Select Register */
+ __IOM uint32_t CFG4; /*!< 0x00000010 PA Reset Enable Register */
+ __IOM uint32_t CFG5; /*!< 0x00000014 PA Reset Pin Select Register */
+ __IOM uint32_t CFG6; /*!< 0x00000018 PA Input Data Sync Control Register - Low */
+ __IOM uint32_t CFG7; /*!< 0x0000001C PA Input Data Sync Control Register - High */
+ __IOM uint32_t CFG8; /*!< 0x00000020 PA Output Data Sync Control Register - Low */
+ __IOM uint32_t CFG9; /*!< 0x00000024 PA Output Data Sync Control Register - High */
+ __IOM uint32_t CFG10; /*!< 0x00000028 PA Output Data Select Register - Low */
+ __IOM uint32_t CFG11; /*!< 0x0000002C PA Output Data Select Register - High */
+ __IOM uint32_t CFG12; /*!< 0x00000030 PA OE Select Register - Low */
+ __IOM uint32_t CFG13; /*!< 0x00000034 PA OE Select Register - High */
+ __IOM uint32_t CFG14; /*!< 0x00000038 PA OE Sync Register */
+ __IM uint32_t RESERVED;
+} UDB_PA_Type; /*!< Size = 64 (0x40) */
+
+/**
+ * \brief UDB Array Bank Control (UDB_BCTL)
+ */
+typedef struct {
+ __IOM uint32_t MDCLK_EN; /*!< 0x00000000 Master Digital Clock Enable Register */
+ __IOM uint32_t MBCLK_EN; /*!< 0x00000004 Master clk_peri_app Enable Register */
+ __IOM uint32_t BOTSEL_L; /*!< 0x00000008 Lower Nibble Bottom Digital Clock Select Register */
+ __IOM uint32_t BOTSEL_U; /*!< 0x0000000C Upper Nibble Bottom Digital Clock Select Register */
+ __IOM uint32_t QCLK_EN[16]; /*!< 0x00000010 Quadrant Digital Clock Enable Registers */
+ __IM uint32_t RESERVED[12];
+} UDB_BCTL_Type; /*!< Size = 128 (0x80) */
+
+/**
+ * \brief UDB Subsystem Interface Configuration (UDB_UDBIF)
+ */
+typedef struct {
+ __IOM uint32_t BANK_CTL; /*!< 0x00000000 Bank Control */
+ __IOM uint32_t INT_CLK_CTL; /*!< 0x00000004 Interrupt Clock Control */
+ __IOM uint32_t INT_CFG; /*!< 0x00000008 Interrupt Configuration */
+ __IOM uint32_t TR_CLK_CTL; /*!< 0x0000000C Trigger Clock Control */
+ __IOM uint32_t TR_CFG; /*!< 0x00000010 Trigger Configuration */
+ __IOM uint32_t PRIVATE; /*!< 0x00000014 Internal use only */
+ __IM uint32_t RESERVED[2];
+} UDB_UDBIF_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * \brief Programmable Digital Subsystem (UDB)
+ */
+typedef struct {
+ UDB_WRKONE_Type WRKONE; /*!< 0x00000000 UDB Working Registers (2 registers from one UDB at a time) */
+ __IM uint32_t RESERVED[512];
+ UDB_WRKMULT_Type WRKMULT; /*!< 0x00001000 UDB Working Registers (1 register from multiple UDBs at a time) */
+ UDB_UDBPAIR_Type UDBPAIR[32]; /*!< 0x00002000 UDB Pair Configuration (up to 32 Pairs) */
+ UDB_DSI_Type DSI[32]; /*!< 0x00006000 DSI Configuration (up to 32 DSI) */
+ UDB_PA_Type PA[32]; /*!< 0x00007000 Port Adapter Configuration (up to 32 PA) */
+ UDB_BCTL_Type BCTL; /*!< 0x00007800 UDB Array Bank Control */
+ __IM uint32_t RESERVED1[32];
+ UDB_UDBIF_Type UDBIF; /*!< 0x00007900 UDB Subsystem Interface Configuration */
+} UDB_Type; /*!< Size = 31008 (0x7920) */
+
+
+/* UDB_WRKONE.A */
+#define UDB_WRKONE_A_A0_Pos 0UL
+#define UDB_WRKONE_A_A0_Msk 0xFFUL
+#define UDB_WRKONE_A_A1_Pos 8UL
+#define UDB_WRKONE_A_A1_Msk 0xFF00UL
+/* UDB_WRKONE.D */
+#define UDB_WRKONE_D_D0_Pos 0UL
+#define UDB_WRKONE_D_D0_Msk 0xFFUL
+#define UDB_WRKONE_D_D1_Pos 8UL
+#define UDB_WRKONE_D_D1_Msk 0xFF00UL
+/* UDB_WRKONE.F */
+#define UDB_WRKONE_F_F0_Pos 0UL
+#define UDB_WRKONE_F_F0_Msk 0xFFUL
+#define UDB_WRKONE_F_F1_Pos 8UL
+#define UDB_WRKONE_F_F1_Msk 0xFF00UL
+/* UDB_WRKONE.CTL_ST */
+#define UDB_WRKONE_CTL_ST_ST_Pos 0UL
+#define UDB_WRKONE_CTL_ST_ST_Msk 0xFFUL
+#define UDB_WRKONE_CTL_ST_CTL_Pos 8UL
+#define UDB_WRKONE_CTL_ST_CTL_Msk 0xFF00UL
+/* UDB_WRKONE.ACTL_MSK */
+#define UDB_WRKONE_ACTL_MSK_MSK_Pos 0UL
+#define UDB_WRKONE_ACTL_MSK_MSK_Msk 0x7FUL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Pos 8UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Msk 0x100UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Pos 9UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Msk 0x200UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Pos 10UL
+#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Msk 0x400UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Pos 11UL
+#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Msk 0x800UL
+#define UDB_WRKONE_ACTL_MSK_INT_EN_Pos 12UL
+#define UDB_WRKONE_ACTL_MSK_INT_EN_Msk 0x1000UL
+#define UDB_WRKONE_ACTL_MSK_CNT_START_Pos 13UL
+#define UDB_WRKONE_ACTL_MSK_CNT_START_Msk 0x2000UL
+/* UDB_WRKONE.MC */
+#define UDB_WRKONE_MC_PLD0_MC_Pos 0UL
+#define UDB_WRKONE_MC_PLD0_MC_Msk 0xFUL
+#define UDB_WRKONE_MC_PLD1_MC_Pos 4UL
+#define UDB_WRKONE_MC_PLD1_MC_Msk 0xF0UL
+
+
+/* UDB_WRKMULT.A0 */
+#define UDB_WRKMULT_A0_A0_0_Pos 0UL
+#define UDB_WRKMULT_A0_A0_0_Msk 0xFFUL
+#define UDB_WRKMULT_A0_A0_1_Pos 8UL
+#define UDB_WRKMULT_A0_A0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_A0_A0_2_Pos 16UL
+#define UDB_WRKMULT_A0_A0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_A0_A0_3_Pos 24UL
+#define UDB_WRKMULT_A0_A0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.A1 */
+#define UDB_WRKMULT_A1_A1_0_Pos 0UL
+#define UDB_WRKMULT_A1_A1_0_Msk 0xFFUL
+#define UDB_WRKMULT_A1_A1_1_Pos 8UL
+#define UDB_WRKMULT_A1_A1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_A1_A1_2_Pos 16UL
+#define UDB_WRKMULT_A1_A1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_A1_A1_3_Pos 24UL
+#define UDB_WRKMULT_A1_A1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.D0 */
+#define UDB_WRKMULT_D0_D0_0_Pos 0UL
+#define UDB_WRKMULT_D0_D0_0_Msk 0xFFUL
+#define UDB_WRKMULT_D0_D0_1_Pos 8UL
+#define UDB_WRKMULT_D0_D0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_D0_D0_2_Pos 16UL
+#define UDB_WRKMULT_D0_D0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_D0_D0_3_Pos 24UL
+#define UDB_WRKMULT_D0_D0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.D1 */
+#define UDB_WRKMULT_D1_D1_0_Pos 0UL
+#define UDB_WRKMULT_D1_D1_0_Msk 0xFFUL
+#define UDB_WRKMULT_D1_D1_1_Pos 8UL
+#define UDB_WRKMULT_D1_D1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_D1_D1_2_Pos 16UL
+#define UDB_WRKMULT_D1_D1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_D1_D1_3_Pos 24UL
+#define UDB_WRKMULT_D1_D1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.F0 */
+#define UDB_WRKMULT_F0_F0_0_Pos 0UL
+#define UDB_WRKMULT_F0_F0_0_Msk 0xFFUL
+#define UDB_WRKMULT_F0_F0_1_Pos 8UL
+#define UDB_WRKMULT_F0_F0_1_Msk 0xFF00UL
+#define UDB_WRKMULT_F0_F0_2_Pos 16UL
+#define UDB_WRKMULT_F0_F0_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_F0_F0_3_Pos 24UL
+#define UDB_WRKMULT_F0_F0_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.F1 */
+#define UDB_WRKMULT_F1_F1_0_Pos 0UL
+#define UDB_WRKMULT_F1_F1_0_Msk 0xFFUL
+#define UDB_WRKMULT_F1_F1_1_Pos 8UL
+#define UDB_WRKMULT_F1_F1_1_Msk 0xFF00UL
+#define UDB_WRKMULT_F1_F1_2_Pos 16UL
+#define UDB_WRKMULT_F1_F1_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_F1_F1_3_Pos 24UL
+#define UDB_WRKMULT_F1_F1_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.ST */
+#define UDB_WRKMULT_ST_ST_0_Pos 0UL
+#define UDB_WRKMULT_ST_ST_0_Msk 0xFFUL
+#define UDB_WRKMULT_ST_ST_1_Pos 8UL
+#define UDB_WRKMULT_ST_ST_1_Msk 0xFF00UL
+#define UDB_WRKMULT_ST_ST_2_Pos 16UL
+#define UDB_WRKMULT_ST_ST_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_ST_ST_3_Pos 24UL
+#define UDB_WRKMULT_ST_ST_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.CTL */
+#define UDB_WRKMULT_CTL_CTL_0_Pos 0UL
+#define UDB_WRKMULT_CTL_CTL_0_Msk 0xFFUL
+#define UDB_WRKMULT_CTL_CTL_1_Pos 8UL
+#define UDB_WRKMULT_CTL_CTL_1_Msk 0xFF00UL
+#define UDB_WRKMULT_CTL_CTL_2_Pos 16UL
+#define UDB_WRKMULT_CTL_CTL_2_Msk 0xFF0000UL
+#define UDB_WRKMULT_CTL_CTL_3_Pos 24UL
+#define UDB_WRKMULT_CTL_CTL_3_Msk 0xFF000000UL
+/* UDB_WRKMULT.MSK */
+#define UDB_WRKMULT_MSK_MSK_0_Pos 0UL
+#define UDB_WRKMULT_MSK_MSK_0_Msk 0x7FUL
+#define UDB_WRKMULT_MSK_MSK_1_Pos 8UL
+#define UDB_WRKMULT_MSK_MSK_1_Msk 0x7F00UL
+#define UDB_WRKMULT_MSK_MSK_2_Pos 16UL
+#define UDB_WRKMULT_MSK_MSK_2_Msk 0x7F0000UL
+#define UDB_WRKMULT_MSK_MSK_3_Pos 24UL
+#define UDB_WRKMULT_MSK_MSK_3_Msk 0x7F000000UL
+/* UDB_WRKMULT.ACTL */
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Pos 0UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Msk 0x1UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Pos 1UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Msk 0x2UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Pos 2UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Msk 0x4UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Pos 3UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Msk 0x8UL
+#define UDB_WRKMULT_ACTL_INT_EN_0_Pos 4UL
+#define UDB_WRKMULT_ACTL_INT_EN_0_Msk 0x10UL
+#define UDB_WRKMULT_ACTL_CNT_START_0_Pos 5UL
+#define UDB_WRKMULT_ACTL_CNT_START_0_Msk 0x20UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Pos 8UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Msk 0x100UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Pos 9UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Msk 0x200UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Pos 10UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Msk 0x400UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Pos 11UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Msk 0x800UL
+#define UDB_WRKMULT_ACTL_INT_EN_1_Pos 12UL
+#define UDB_WRKMULT_ACTL_INT_EN_1_Msk 0x1000UL
+#define UDB_WRKMULT_ACTL_CNT_START_1_Pos 13UL
+#define UDB_WRKMULT_ACTL_CNT_START_1_Msk 0x2000UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Pos 16UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Msk 0x10000UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Pos 17UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Msk 0x20000UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Pos 18UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Msk 0x40000UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Pos 19UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Msk 0x80000UL
+#define UDB_WRKMULT_ACTL_INT_EN_2_Pos 20UL
+#define UDB_WRKMULT_ACTL_INT_EN_2_Msk 0x100000UL
+#define UDB_WRKMULT_ACTL_CNT_START_2_Pos 21UL
+#define UDB_WRKMULT_ACTL_CNT_START_2_Msk 0x200000UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Pos 24UL
+#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Msk 0x1000000UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Pos 25UL
+#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Msk 0x2000000UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Pos 26UL
+#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Msk 0x4000000UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Pos 27UL
+#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Msk 0x8000000UL
+#define UDB_WRKMULT_ACTL_INT_EN_3_Pos 28UL
+#define UDB_WRKMULT_ACTL_INT_EN_3_Msk 0x10000000UL
+#define UDB_WRKMULT_ACTL_CNT_START_3_Pos 29UL
+#define UDB_WRKMULT_ACTL_CNT_START_3_Msk 0x20000000UL
+/* UDB_WRKMULT.MC */
+#define UDB_WRKMULT_MC_PLD0_MC_0_Pos 0UL
+#define UDB_WRKMULT_MC_PLD0_MC_0_Msk 0xFUL
+#define UDB_WRKMULT_MC_PLD1_MC_0_Pos 4UL
+#define UDB_WRKMULT_MC_PLD1_MC_0_Msk 0xF0UL
+#define UDB_WRKMULT_MC_PLD0_MC_1_Pos 8UL
+#define UDB_WRKMULT_MC_PLD0_MC_1_Msk 0xF00UL
+#define UDB_WRKMULT_MC_PLD1_MC_1_Pos 12UL
+#define UDB_WRKMULT_MC_PLD1_MC_1_Msk 0xF000UL
+#define UDB_WRKMULT_MC_PLD0_MC_2_Pos 16UL
+#define UDB_WRKMULT_MC_PLD0_MC_2_Msk 0xF0000UL
+#define UDB_WRKMULT_MC_PLD1_MC_2_Pos 20UL
+#define UDB_WRKMULT_MC_PLD1_MC_2_Msk 0xF00000UL
+#define UDB_WRKMULT_MC_PLD0_MC_3_Pos 24UL
+#define UDB_WRKMULT_MC_PLD0_MC_3_Msk 0xF000000UL
+#define UDB_WRKMULT_MC_PLD1_MC_3_Pos 28UL
+#define UDB_WRKMULT_MC_PLD1_MC_3_Msk 0xF0000000UL
+
+
+/* UDB_UDBPAIR_UDBSNG.PLD_IT */
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_ORT0 */
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_ORT1 */
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Msk 0xC0000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Msk 0x300000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Msk 0xC00000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Msk 0x30000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Msk 0xC0000000UL
+/* UDB_UDBPAIR_UDBSNG.PLD_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Msk 0x400UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Msk 0x40000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Msk 0x7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Msk 0x70UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Msk 0x700UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Pos 11UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Msk 0x800UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Pos 15UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Msk 0x8000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Msk 0x70000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Msk 0x700000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Msk 0x7000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Msk 0x70000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Msk 0x7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Msk 0x70UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Msk 0xF00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Msk 0xF000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Msk 0xF0000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Msk 0xF00000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Msk 0xF000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Msk 0xF0000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG2 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Msk 0x3FUL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Msk 0xFF00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Msk 0xFF0000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Msk 0xFF000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG3 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Msk 0x3000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Msk 0xC000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Msk 0x700000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_CFG4 */
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Msk 0x100UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Pos 9UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Msk 0x200UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Msk 0x1000UL
+/* UDB_UDBPAIR_UDBSNG.SC_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Msk 0xFFUL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Msk 0xFF00UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Msk 0xFF0000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Msk 0x10000000UL
+/* UDB_UDBPAIR_UDBSNG.SC_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Msk 0x40UL
+/* UDB_UDBPAIR_UDBSNG.RC_CFG0 */
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Msk 0x3UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Msk 0xCUL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Msk 0x10UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Pos 5UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Msk 0x20UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Msk 0x40UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Pos 7UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Msk 0x80UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Msk 0x2000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Pos 14UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Msk 0x4000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Msk 0xC0000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Msk 0x100000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Pos 21UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Msk 0x200000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Msk 0x20000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Msk 0x40000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Pos 31UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Msk 0x80000000UL
+/* UDB_UDBPAIR_UDBSNG.RC_CFG1 */
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Msk 0xFUL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Msk 0x30000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Msk 0x400000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Pos 23UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Msk 0x800000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Msk 0x1000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Pos 25UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Msk 0x2000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Msk 0x4000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Pos 27UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Msk 0x8000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Msk 0x30000000UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Pos 30UL
+#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Msk 0x40000000UL
+/* UDB_UDBPAIR_UDBSNG.DPATH_OPC */
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Pos 0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Msk 0x1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Pos 1UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Msk 0x2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Pos 2UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Msk 0x4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Pos 3UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Msk 0x8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Pos 4UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Msk 0x30UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Pos 6UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Msk 0xC0UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Pos 8UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Msk 0x300UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Pos 10UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Msk 0xC00UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Pos 12UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Msk 0x1000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Pos 13UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Msk 0xE000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Pos 16UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Msk 0x10000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Pos 17UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Msk 0x20000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Pos 18UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Msk 0x40000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Pos 19UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Msk 0x80000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Pos 20UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Msk 0x300000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Pos 22UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Msk 0xC00000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Pos 24UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Msk 0x3000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Pos 26UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Msk 0xC000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Pos 28UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Msk 0x10000000UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Pos 29UL
+#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Msk 0xE0000000UL
+
+
+/* UDB_UDBPAIR_ROUTE.TOP_V_BOT */
+#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.LVO1_V_2 */
+#define UDB_UDBPAIR_ROUTE_LVO1_V_2_LVO1_V_2_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO1_V_2_LVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RVO1_V_2 */
+#define UDB_UDBPAIR_ROUTE_RVO1_V_2_RVO1_V_2_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO1_V_2_RVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG0 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG1 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG2 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG3 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG4 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.TUI_CFG5 */
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Msk 0xF0UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG0 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG1 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG2 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG3 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG4 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.BUI_CFG5 */
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Msk 0xF0UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.RVO_CFG3 */
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Msk 0x1FUL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Msk 0x1F00UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Msk 0x1F0000UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Msk 0x1F000000UL
+/* UDB_UDBPAIR_ROUTE.LVO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LVO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.RHO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG0 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG1 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG2 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG3 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG4 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG5 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG6 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG7 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG8 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG9 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG10 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Msk 0xF0000000UL
+/* UDB_UDBPAIR_ROUTE.LHO_CFG11 */
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Pos 0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Msk 0xFUL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Pos 4UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Msk 0xF0UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Pos 8UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Msk 0xF00UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Pos 12UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Msk 0xF000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Pos 16UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Msk 0xF0000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Pos 20UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Msk 0xF00000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Pos 24UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Msk 0xF000000UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Pos 28UL
+#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Msk 0xF0000000UL
+
+
+/* UDB_DSI.LVO1_V_2 */
+#define UDB_DSI_LVO1_V_2_LVO1_V_2_Pos 0UL
+#define UDB_DSI_LVO1_V_2_LVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RVO1_V_2 */
+#define UDB_DSI_RVO1_V_2_RVO1_V_2_Pos 0UL
+#define UDB_DSI_RVO1_V_2_RVO1_V_2_Msk 0xFFFFFFFFUL
+/* UDB_DSI.DOP_CFG0 */
+#define UDB_DSI_DOP_CFG0_DOP0SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG0_DOP0SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG0_DOP1SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG0_DOP1SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG0_DOP2SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG0_DOP2SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG0_DOP3SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG0_DOP3SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG1 */
+#define UDB_DSI_DOP_CFG1_DOP4SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG1_DOP4SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG1_DOP5SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG1_DOP5SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG1_DOP6SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG1_DOP6SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG1_DOP7SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG1_DOP7SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG2 */
+#define UDB_DSI_DOP_CFG2_DOP8SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG2_DOP8SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG2_DOP9SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG2_DOP9SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG2_DOP10SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG2_DOP10SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG2_DOP11SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG2_DOP11SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOP_CFG3 */
+#define UDB_DSI_DOP_CFG3_DOP12SEL_Pos 0UL
+#define UDB_DSI_DOP_CFG3_DOP12SEL_Msk 0x1FUL
+#define UDB_DSI_DOP_CFG3_DOP13SEL_Pos 8UL
+#define UDB_DSI_DOP_CFG3_DOP13SEL_Msk 0x1F00UL
+#define UDB_DSI_DOP_CFG3_DOP14SEL_Pos 16UL
+#define UDB_DSI_DOP_CFG3_DOP14SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOP_CFG3_DOP15SEL_Pos 24UL
+#define UDB_DSI_DOP_CFG3_DOP15SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG0 */
+#define UDB_DSI_DOT_CFG0_DOT0SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG0_DOT0SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG0_DOT1SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG0_DOT1SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG0_DOT2SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG0_DOT2SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG0_DOT3SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG0_DOT3SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG1 */
+#define UDB_DSI_DOT_CFG1_DOT4SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG1_DOT4SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG1_DOT5SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG1_DOT5SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG1_DOT6SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG1_DOT6SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG1_DOT7SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG1_DOT7SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG2 */
+#define UDB_DSI_DOT_CFG2_DOT8SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG2_DOT8SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG2_DOT9SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG2_DOT9SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG2_DOT10SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG2_DOT10SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG2_DOT11SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG2_DOT11SEL_Msk 0x1F000000UL
+/* UDB_DSI.DOT_CFG3 */
+#define UDB_DSI_DOT_CFG3_DOT12SEL_Pos 0UL
+#define UDB_DSI_DOT_CFG3_DOT12SEL_Msk 0x1FUL
+#define UDB_DSI_DOT_CFG3_DOT13SEL_Pos 8UL
+#define UDB_DSI_DOT_CFG3_DOT13SEL_Msk 0x1F00UL
+#define UDB_DSI_DOT_CFG3_DOT14SEL_Pos 16UL
+#define UDB_DSI_DOT_CFG3_DOT14SEL_Msk 0x1F0000UL
+#define UDB_DSI_DOT_CFG3_DOT15SEL_Pos 24UL
+#define UDB_DSI_DOT_CFG3_DOT15SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG0 */
+#define UDB_DSI_RVO_CFG0_RVO0SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG0_RVO0SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG0_RVO1SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG0_RVO1SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG0_RVO2SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG0_RVO2SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG0_RVO3SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG0_RVO3SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG1 */
+#define UDB_DSI_RVO_CFG1_RVO4SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG1_RVO4SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG1_RVO5SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG1_RVO5SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG1_RVO6SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG1_RVO6SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG1_RVO7SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG1_RVO7SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG2 */
+#define UDB_DSI_RVO_CFG2_RVO8SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG2_RVO8SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG2_RVO9SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG2_RVO9SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG2_RVO10SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG2_RVO10SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG2_RVO11SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG2_RVO11SEL_Msk 0x1F000000UL
+/* UDB_DSI.RVO_CFG3 */
+#define UDB_DSI_RVO_CFG3_RVO12SEL_Pos 0UL
+#define UDB_DSI_RVO_CFG3_RVO12SEL_Msk 0x1FUL
+#define UDB_DSI_RVO_CFG3_RVO13SEL_Pos 8UL
+#define UDB_DSI_RVO_CFG3_RVO13SEL_Msk 0x1F00UL
+#define UDB_DSI_RVO_CFG3_RVO14SEL_Pos 16UL
+#define UDB_DSI_RVO_CFG3_RVO14SEL_Msk 0x1F0000UL
+#define UDB_DSI_RVO_CFG3_RVO15SEL_Pos 24UL
+#define UDB_DSI_RVO_CFG3_RVO15SEL_Msk 0x1F000000UL
+/* UDB_DSI.LVO_CFG0 */
+#define UDB_DSI_LVO_CFG0_LVO0SEL_Pos 0UL
+#define UDB_DSI_LVO_CFG0_LVO0SEL_Msk 0xFUL
+#define UDB_DSI_LVO_CFG0_LVO1SEL_Pos 4UL
+#define UDB_DSI_LVO_CFG0_LVO1SEL_Msk 0xF0UL
+#define UDB_DSI_LVO_CFG0_LVO2SEL_Pos 8UL
+#define UDB_DSI_LVO_CFG0_LVO2SEL_Msk 0xF00UL
+#define UDB_DSI_LVO_CFG0_LVO3SEL_Pos 12UL
+#define UDB_DSI_LVO_CFG0_LVO3SEL_Msk 0xF000UL
+#define UDB_DSI_LVO_CFG0_LVO4SEL_Pos 16UL
+#define UDB_DSI_LVO_CFG0_LVO4SEL_Msk 0xF0000UL
+#define UDB_DSI_LVO_CFG0_LVO5SEL_Pos 20UL
+#define UDB_DSI_LVO_CFG0_LVO5SEL_Msk 0xF00000UL
+#define UDB_DSI_LVO_CFG0_LVO6SEL_Pos 24UL
+#define UDB_DSI_LVO_CFG0_LVO6SEL_Msk 0xF000000UL
+#define UDB_DSI_LVO_CFG0_LVO7SEL_Pos 28UL
+#define UDB_DSI_LVO_CFG0_LVO7SEL_Msk 0xF0000000UL
+/* UDB_DSI.LVO_CFG1 */
+#define UDB_DSI_LVO_CFG1_LVO8SEL_Pos 0UL
+#define UDB_DSI_LVO_CFG1_LVO8SEL_Msk 0xFUL
+#define UDB_DSI_LVO_CFG1_LVO9SEL_Pos 4UL
+#define UDB_DSI_LVO_CFG1_LVO9SEL_Msk 0xF0UL
+#define UDB_DSI_LVO_CFG1_LVO10SEL_Pos 8UL
+#define UDB_DSI_LVO_CFG1_LVO10SEL_Msk 0xF00UL
+#define UDB_DSI_LVO_CFG1_LVO11SEL_Pos 12UL
+#define UDB_DSI_LVO_CFG1_LVO11SEL_Msk 0xF000UL
+#define UDB_DSI_LVO_CFG1_LVO12SEL_Pos 16UL
+#define UDB_DSI_LVO_CFG1_LVO12SEL_Msk 0xF0000UL
+#define UDB_DSI_LVO_CFG1_LVO13SEL_Pos 20UL
+#define UDB_DSI_LVO_CFG1_LVO13SEL_Msk 0xF00000UL
+#define UDB_DSI_LVO_CFG1_LVO14SEL_Pos 24UL
+#define UDB_DSI_LVO_CFG1_LVO14SEL_Msk 0xF000000UL
+#define UDB_DSI_LVO_CFG1_LVO15SEL_Pos 28UL
+#define UDB_DSI_LVO_CFG1_LVO15SEL_Msk 0xF0000000UL
+/* UDB_DSI.RHO_CFG0 */
+#define UDB_DSI_RHO_CFG0_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG0_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RHO_CFG1 */
+#define UDB_DSI_RHO_CFG1_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG1_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.RHO_CFG2 */
+#define UDB_DSI_RHO_CFG2_RHOSEL_Pos 0UL
+#define UDB_DSI_RHO_CFG2_RHOSEL_Msk 0xFFFFFFFFUL
+/* UDB_DSI.LHO_CFG0 */
+#define UDB_DSI_LHO_CFG0_LHO0SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG0_LHO0SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG0_LHO1SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG0_LHO1SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG0_LHO2SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG0_LHO2SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG0_LHO3SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG0_LHO3SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG0_LHO4SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG0_LHO4SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG0_LHO5SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG0_LHO5SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG0_LHO6SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG0_LHO6SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG0_LHO7SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG0_LHO7SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG1 */
+#define UDB_DSI_LHO_CFG1_LHO8SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG1_LHO8SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG1_LHO9SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG1_LHO9SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG1_LHO10SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG1_LHO10SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG1_LHO11SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG1_LHO11SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG1_LHO12SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG1_LHO12SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG1_LHO13SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG1_LHO13SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG1_LHO14SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG1_LHO14SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG1_LHO15SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG1_LHO15SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG2 */
+#define UDB_DSI_LHO_CFG2_LHO16SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG2_LHO16SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG2_LHO17SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG2_LHO17SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG2_LHO18SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG2_LHO18SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG2_LHO19SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG2_LHO19SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG2_LHO20SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG2_LHO20SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG2_LHO21SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG2_LHO21SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG2_LHO22SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG2_LHO22SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG2_LHO23SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG2_LHO23SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG3 */
+#define UDB_DSI_LHO_CFG3_LHO24SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG3_LHO24SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG3_LHO25SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG3_LHO25SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG3_LHO26SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG3_LHO26SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG3_LHO27SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG3_LHO27SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG3_LHO28SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG3_LHO28SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG3_LHO29SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG3_LHO29SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG3_LHO30SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG3_LHO30SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG3_LHO31SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG3_LHO31SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG4 */
+#define UDB_DSI_LHO_CFG4_LHO32SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG4_LHO32SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG4_LHO33SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG4_LHO33SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG4_LHO34SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG4_LHO34SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG4_LHO35SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG4_LHO35SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG4_LHO36SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG4_LHO36SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG4_LHO37SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG4_LHO37SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG4_LHO38SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG4_LHO38SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG4_LHO39SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG4_LHO39SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG5 */
+#define UDB_DSI_LHO_CFG5_LHO40SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG5_LHO40SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG5_LHO41SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG5_LHO41SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG5_LHO42SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG5_LHO42SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG5_LHO43SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG5_LHO43SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG5_LHO44SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG5_LHO44SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG5_LHO45SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG5_LHO45SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG5_LHO46SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG5_LHO46SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG5_LHO47SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG5_LHO47SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG6 */
+#define UDB_DSI_LHO_CFG6_LHO48SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG6_LHO48SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG6_LHO49SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG6_LHO49SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG6_LHO50SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG6_LHO50SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG6_LHO51SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG6_LHO51SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG6_LHO52SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG6_LHO52SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG6_LHO53SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG6_LHO53SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG6_LHO54SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG6_LHO54SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG6_LHO55SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG6_LHO55SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG7 */
+#define UDB_DSI_LHO_CFG7_LHO56SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG7_LHO56SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG7_LHO57SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG7_LHO57SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG7_LHO58SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG7_LHO58SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG7_LHO59SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG7_LHO59SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG7_LHO60SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG7_LHO60SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG7_LHO61SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG7_LHO61SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG7_LHO62SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG7_LHO62SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG7_LHO63SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG7_LHO63SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG8 */
+#define UDB_DSI_LHO_CFG8_LHO64SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG8_LHO64SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG8_LHO65SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG8_LHO65SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG8_LHO66SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG8_LHO66SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG8_LHO67SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG8_LHO67SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG8_LHO68SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG8_LHO68SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG8_LHO69SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG8_LHO69SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG8_LHO70SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG8_LHO70SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG8_LHO71SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG8_LHO71SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG9 */
+#define UDB_DSI_LHO_CFG9_LHO72SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG9_LHO72SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG9_LHO73SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG9_LHO73SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG9_LHO74SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG9_LHO74SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG9_LHO75SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG9_LHO75SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG9_LHO76SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG9_LHO76SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG9_LHO77SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG9_LHO77SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG9_LHO78SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG9_LHO78SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG9_LHO79SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG9_LHO79SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG10 */
+#define UDB_DSI_LHO_CFG10_LHO80SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG10_LHO80SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG10_LHO81SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG10_LHO81SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG10_LHO82SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG10_LHO82SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG10_LHO83SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG10_LHO83SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG10_LHO84SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG10_LHO84SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG10_LHO85SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG10_LHO85SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG10_LHO86SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG10_LHO86SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG10_LHO87SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG10_LHO87SEL_Msk 0xF0000000UL
+/* UDB_DSI.LHO_CFG11 */
+#define UDB_DSI_LHO_CFG11_LHO88SEL_Pos 0UL
+#define UDB_DSI_LHO_CFG11_LHO88SEL_Msk 0xFUL
+#define UDB_DSI_LHO_CFG11_LHO89SEL_Pos 4UL
+#define UDB_DSI_LHO_CFG11_LHO89SEL_Msk 0xF0UL
+#define UDB_DSI_LHO_CFG11_LHO90SEL_Pos 8UL
+#define UDB_DSI_LHO_CFG11_LHO90SEL_Msk 0xF00UL
+#define UDB_DSI_LHO_CFG11_LHO91SEL_Pos 12UL
+#define UDB_DSI_LHO_CFG11_LHO91SEL_Msk 0xF000UL
+#define UDB_DSI_LHO_CFG11_LHO92SEL_Pos 16UL
+#define UDB_DSI_LHO_CFG11_LHO92SEL_Msk 0xF0000UL
+#define UDB_DSI_LHO_CFG11_LHO93SEL_Pos 20UL
+#define UDB_DSI_LHO_CFG11_LHO93SEL_Msk 0xF00000UL
+#define UDB_DSI_LHO_CFG11_LHO94SEL_Pos 24UL
+#define UDB_DSI_LHO_CFG11_LHO94SEL_Msk 0xF000000UL
+#define UDB_DSI_LHO_CFG11_LHO95SEL_Pos 28UL
+#define UDB_DSI_LHO_CFG11_LHO95SEL_Msk 0xF0000000UL
+
+
+/* UDB_PA.CFG0 */
+#define UDB_PA_CFG0_CLKIN_EN_SEL_Pos 0UL
+#define UDB_PA_CFG0_CLKIN_EN_SEL_Msk 0x3UL
+#define UDB_PA_CFG0_CLKIN_EN_MODE_Pos 2UL
+#define UDB_PA_CFG0_CLKIN_EN_MODE_Msk 0xCUL
+#define UDB_PA_CFG0_CLKIN_EN_INV_Pos 4UL
+#define UDB_PA_CFG0_CLKIN_EN_INV_Msk 0x10UL
+#define UDB_PA_CFG0_CLKIN_INV_Pos 5UL
+#define UDB_PA_CFG0_CLKIN_INV_Msk 0x20UL
+/* UDB_PA.CFG1 */
+#define UDB_PA_CFG1_CLKOUT_EN_SEL_Pos 0UL
+#define UDB_PA_CFG1_CLKOUT_EN_SEL_Msk 0x3UL
+#define UDB_PA_CFG1_CLKOUT_EN_MODE_Pos 2UL
+#define UDB_PA_CFG1_CLKOUT_EN_MODE_Msk 0xCUL
+#define UDB_PA_CFG1_CLKOUT_EN_INV_Pos 4UL
+#define UDB_PA_CFG1_CLKOUT_EN_INV_Msk 0x10UL
+#define UDB_PA_CFG1_CLKOUT_INV_Pos 5UL
+#define UDB_PA_CFG1_CLKOUT_INV_Msk 0x20UL
+/* UDB_PA.CFG2 */
+#define UDB_PA_CFG2_CLKIN_SEL_Pos 0UL
+#define UDB_PA_CFG2_CLKIN_SEL_Msk 0xFUL
+#define UDB_PA_CFG2_CLKOUT_SEL_Pos 4UL
+#define UDB_PA_CFG2_CLKOUT_SEL_Msk 0xF0UL
+/* UDB_PA.CFG3 */
+#define UDB_PA_CFG3_RES_IN_SEL_Pos 0UL
+#define UDB_PA_CFG3_RES_IN_SEL_Msk 0x3UL
+#define UDB_PA_CFG3_RES_IN_INV_Pos 2UL
+#define UDB_PA_CFG3_RES_IN_INV_Msk 0x4UL
+#define UDB_PA_CFG3_RES_OUT_SEL_Pos 4UL
+#define UDB_PA_CFG3_RES_OUT_SEL_Msk 0x30UL
+#define UDB_PA_CFG3_RES_OUT_INV_Pos 6UL
+#define UDB_PA_CFG3_RES_OUT_INV_Msk 0x40UL
+/* UDB_PA.CFG4 */
+#define UDB_PA_CFG4_RES_IN_EN_Pos 0UL
+#define UDB_PA_CFG4_RES_IN_EN_Msk 0x1UL
+#define UDB_PA_CFG4_RES_OUT_EN_Pos 1UL
+#define UDB_PA_CFG4_RES_OUT_EN_Msk 0x2UL
+#define UDB_PA_CFG4_RES_OE_EN_Pos 2UL
+#define UDB_PA_CFG4_RES_OE_EN_Msk 0x4UL
+/* UDB_PA.CFG5 */
+#define UDB_PA_CFG5_PIN_SEL_Pos 0UL
+#define UDB_PA_CFG5_PIN_SEL_Msk 0x7UL
+/* UDB_PA.CFG6 */
+#define UDB_PA_CFG6_IN_SYNC0_Pos 0UL
+#define UDB_PA_CFG6_IN_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG6_IN_SYNC1_Pos 2UL
+#define UDB_PA_CFG6_IN_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG6_IN_SYNC2_Pos 4UL
+#define UDB_PA_CFG6_IN_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG6_IN_SYNC3_Pos 6UL
+#define UDB_PA_CFG6_IN_SYNC3_Msk 0xC0UL
+/* UDB_PA.CFG7 */
+#define UDB_PA_CFG7_IN_SYNC4_Pos 0UL
+#define UDB_PA_CFG7_IN_SYNC4_Msk 0x3UL
+#define UDB_PA_CFG7_IN_SYNC5_Pos 2UL
+#define UDB_PA_CFG7_IN_SYNC5_Msk 0xCUL
+#define UDB_PA_CFG7_IN_SYNC6_Pos 4UL
+#define UDB_PA_CFG7_IN_SYNC6_Msk 0x30UL
+#define UDB_PA_CFG7_IN_SYNC7_Pos 6UL
+#define UDB_PA_CFG7_IN_SYNC7_Msk 0xC0UL
+/* UDB_PA.CFG8 */
+#define UDB_PA_CFG8_OUT_SYNC0_Pos 0UL
+#define UDB_PA_CFG8_OUT_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG8_OUT_SYNC1_Pos 2UL
+#define UDB_PA_CFG8_OUT_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG8_OUT_SYNC2_Pos 4UL
+#define UDB_PA_CFG8_OUT_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG8_OUT_SYNC3_Pos 6UL
+#define UDB_PA_CFG8_OUT_SYNC3_Msk 0xC0UL
+/* UDB_PA.CFG9 */
+#define UDB_PA_CFG9_OUT_SYNC4_Pos 0UL
+#define UDB_PA_CFG9_OUT_SYNC4_Msk 0x3UL
+#define UDB_PA_CFG9_OUT_SYNC5_Pos 2UL
+#define UDB_PA_CFG9_OUT_SYNC5_Msk 0xCUL
+#define UDB_PA_CFG9_OUT_SYNC6_Pos 4UL
+#define UDB_PA_CFG9_OUT_SYNC6_Msk 0x30UL
+#define UDB_PA_CFG9_OUT_SYNC7_Pos 6UL
+#define UDB_PA_CFG9_OUT_SYNC7_Msk 0xC0UL
+/* UDB_PA.CFG10 */
+#define UDB_PA_CFG10_DATA_SEL0_Pos 0UL
+#define UDB_PA_CFG10_DATA_SEL0_Msk 0x3UL
+#define UDB_PA_CFG10_DATA_SEL1_Pos 2UL
+#define UDB_PA_CFG10_DATA_SEL1_Msk 0xCUL
+#define UDB_PA_CFG10_DATA_SEL2_Pos 4UL
+#define UDB_PA_CFG10_DATA_SEL2_Msk 0x30UL
+#define UDB_PA_CFG10_DATA_SEL3_Pos 6UL
+#define UDB_PA_CFG10_DATA_SEL3_Msk 0xC0UL
+/* UDB_PA.CFG11 */
+#define UDB_PA_CFG11_DATA_SEL4_Pos 0UL
+#define UDB_PA_CFG11_DATA_SEL4_Msk 0x3UL
+#define UDB_PA_CFG11_DATA_SEL5_Pos 2UL
+#define UDB_PA_CFG11_DATA_SEL5_Msk 0xCUL
+#define UDB_PA_CFG11_DATA_SEL6_Pos 4UL
+#define UDB_PA_CFG11_DATA_SEL6_Msk 0x30UL
+#define UDB_PA_CFG11_DATA_SEL7_Pos 6UL
+#define UDB_PA_CFG11_DATA_SEL7_Msk 0xC0UL
+/* UDB_PA.CFG12 */
+#define UDB_PA_CFG12_OE_SEL0_Pos 0UL
+#define UDB_PA_CFG12_OE_SEL0_Msk 0x3UL
+#define UDB_PA_CFG12_OE_SEL1_Pos 2UL
+#define UDB_PA_CFG12_OE_SEL1_Msk 0xCUL
+#define UDB_PA_CFG12_OE_SEL2_Pos 4UL
+#define UDB_PA_CFG12_OE_SEL2_Msk 0x30UL
+#define UDB_PA_CFG12_OE_SEL3_Pos 6UL
+#define UDB_PA_CFG12_OE_SEL3_Msk 0xC0UL
+/* UDB_PA.CFG13 */
+#define UDB_PA_CFG13_OE_SEL4_Pos 0UL
+#define UDB_PA_CFG13_OE_SEL4_Msk 0x3UL
+#define UDB_PA_CFG13_OE_SEL5_Pos 2UL
+#define UDB_PA_CFG13_OE_SEL5_Msk 0xCUL
+#define UDB_PA_CFG13_OE_SEL6_Pos 4UL
+#define UDB_PA_CFG13_OE_SEL6_Msk 0x30UL
+#define UDB_PA_CFG13_OE_SEL7_Pos 6UL
+#define UDB_PA_CFG13_OE_SEL7_Msk 0xC0UL
+/* UDB_PA.CFG14 */
+#define UDB_PA_CFG14_OE_SYNC0_Pos 0UL
+#define UDB_PA_CFG14_OE_SYNC0_Msk 0x3UL
+#define UDB_PA_CFG14_OE_SYNC1_Pos 2UL
+#define UDB_PA_CFG14_OE_SYNC1_Msk 0xCUL
+#define UDB_PA_CFG14_OE_SYNC2_Pos 4UL
+#define UDB_PA_CFG14_OE_SYNC2_Msk 0x30UL
+#define UDB_PA_CFG14_OE_SYNC3_Pos 6UL
+#define UDB_PA_CFG14_OE_SYNC3_Msk 0xC0UL
+
+
+/* UDB_BCTL.MDCLK_EN */
+#define UDB_BCTL_MDCLK_EN_DCEN_Pos 0UL
+#define UDB_BCTL_MDCLK_EN_DCEN_Msk 0xFFUL
+/* UDB_BCTL.MBCLK_EN */
+#define UDB_BCTL_MBCLK_EN_BCEN_Pos 0UL
+#define UDB_BCTL_MBCLK_EN_BCEN_Msk 0x1UL
+/* UDB_BCTL.BOTSEL_L */
+#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Pos 0UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Msk 0x3UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Pos 2UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Msk 0xCUL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Pos 4UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Msk 0x30UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Pos 6UL
+#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Msk 0xC0UL
+/* UDB_BCTL.BOTSEL_U */
+#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Pos 0UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Msk 0x3UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Pos 2UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Msk 0xCUL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Pos 4UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Msk 0x30UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Pos 6UL
+#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Msk 0xC0UL
+/* UDB_BCTL.QCLK_EN */
+#define UDB_BCTL_QCLK_EN_DCEN_Q_Pos 0UL
+#define UDB_BCTL_QCLK_EN_DCEN_Q_Msk 0xFFUL
+#define UDB_BCTL_QCLK_EN_BCEN_Q_Pos 8UL
+#define UDB_BCTL_QCLK_EN_BCEN_Q_Msk 0x100UL
+#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Pos 11UL
+#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Msk 0x800UL
+
+
+/* UDB_UDBIF.BANK_CTL */
+#define UDB_UDBIF_BANK_CTL_DIS_COR_Pos 0UL
+#define UDB_UDBIF_BANK_CTL_DIS_COR_Msk 0x1UL
+#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Pos 1UL
+#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Msk 0x2UL
+#define UDB_UDBIF_BANK_CTL_BANK_EN_Pos 2UL
+#define UDB_UDBIF_BANK_CTL_BANK_EN_Msk 0x4UL
+#define UDB_UDBIF_BANK_CTL_READ_WAIT_Pos 8UL
+#define UDB_UDBIF_BANK_CTL_READ_WAIT_Msk 0x100UL
+/* UDB_UDBIF.INT_CLK_CTL */
+#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Pos 0UL
+#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Msk 0x1UL
+/* UDB_UDBIF.INT_CFG */
+#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Pos 0UL
+#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Msk 0xFFFFFFFFUL
+/* UDB_UDBIF.TR_CLK_CTL */
+#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Pos 0UL
+#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Msk 0x1UL
+/* UDB_UDBIF.TR_CFG */
+#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Pos 0UL
+#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Msk 0xFFFFFFFFUL
+/* UDB_UDBIF.PRIVATE */
+#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Pos 0UL
+#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Msk 0x1UL
+
+
+#endif /* _CYIP_UDB_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/ip/cyip_usbfs.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1768 @@
+/***************************************************************************//**
+* \file cyip_usbfs.h
+*
+* \brief
+* USBFS IP definitions
+*
+* \note
+* Generator version: 1.2.0.117
+* Database revision: rev#1034984
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+
+#ifndef _CYIP_USBFS_H_
+#define _CYIP_USBFS_H_
+
+#include "cyip_headers.h"
+
+/*******************************************************************************
+* USBFS
+*******************************************************************************/
+
+#define USBFS_USBDEV_SECTION_SIZE 0x00002000UL
+#define USBFS_USBLPM_SECTION_SIZE 0x00001000UL
+#define USBFS_USBHOST_SECTION_SIZE 0x00002000UL
+#define USBFS_SECTION_SIZE 0x00010000UL
+
+/**
+ * \brief USB Device (USBFS_USBDEV)
+ */
+typedef struct {
+ __IOM uint32_t EP0_DR[8]; /*!< 0x00000000 Control End point EP0 Data Register */
+ __IOM uint32_t CR0; /*!< 0x00000020 USB control 0 Register */
+ __IOM uint32_t CR1; /*!< 0x00000024 USB control 1 Register */
+ __IOM uint32_t SIE_EP_INT_EN; /*!< 0x00000028 USB SIE Data Endpoints Interrupt Enable Register */
+ __IOM uint32_t SIE_EP_INT_SR; /*!< 0x0000002C USB SIE Data Endpoint Interrupt Status */
+ __IOM uint32_t SIE_EP1_CNT0; /*!< 0x00000030 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP1_CNT1; /*!< 0x00000034 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP1_CR0; /*!< 0x00000038 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t USBIO_CR0; /*!< 0x00000040 USBIO Control 0 Register */
+ __IOM uint32_t USBIO_CR2; /*!< 0x00000044 USBIO control 2 Register */
+ __IOM uint32_t USBIO_CR1; /*!< 0x00000048 USBIO control 1 Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t DYN_RECONFIG; /*!< 0x00000050 USB Dynamic reconfiguration register */
+ __IM uint32_t RESERVED2[3];
+ __IM uint32_t SOF0; /*!< 0x00000060 Start Of Frame Register */
+ __IM uint32_t SOF1; /*!< 0x00000064 Start Of Frame Register */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t SIE_EP2_CNT0; /*!< 0x00000070 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP2_CNT1; /*!< 0x00000074 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP2_CR0; /*!< 0x00000078 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t OSCLK_DR0; /*!< 0x00000080 Oscillator lock data register 0 */
+ __IM uint32_t OSCLK_DR1; /*!< 0x00000084 Oscillator lock data register 1 */
+ __IM uint32_t RESERVED5[6];
+ __IOM uint32_t EP0_CR; /*!< 0x000000A0 Endpoint0 control Register */
+ __IOM uint32_t EP0_CNT; /*!< 0x000000A4 Endpoint0 count Register */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t SIE_EP3_CNT0; /*!< 0x000000B0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP3_CNT1; /*!< 0x000000B4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP3_CR0; /*!< 0x000000B8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED7[13];
+ __IOM uint32_t SIE_EP4_CNT0; /*!< 0x000000F0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP4_CNT1; /*!< 0x000000F4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP4_CR0; /*!< 0x000000F8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED8[13];
+ __IOM uint32_t SIE_EP5_CNT0; /*!< 0x00000130 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP5_CNT1; /*!< 0x00000134 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP5_CR0; /*!< 0x00000138 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED9[13];
+ __IOM uint32_t SIE_EP6_CNT0; /*!< 0x00000170 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP6_CNT1; /*!< 0x00000174 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP6_CR0; /*!< 0x00000178 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED10[13];
+ __IOM uint32_t SIE_EP7_CNT0; /*!< 0x000001B0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP7_CNT1; /*!< 0x000001B4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP7_CR0; /*!< 0x000001B8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED11[13];
+ __IOM uint32_t SIE_EP8_CNT0; /*!< 0x000001F0 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP8_CNT1; /*!< 0x000001F4 Non-control endpoint count register */
+ __IOM uint32_t SIE_EP8_CR0; /*!< 0x000001F8 Non-control endpoint's control Register */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t ARB_EP1_CFG; /*!< 0x00000200 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */
+ __IM uint32_t RESERVED14[3];
+ __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t EP_ACTIVE; /*!< 0x00000238 Endpoint Active Indication Register *1 */
+ __IOM uint32_t EP_TYPE; /*!< 0x0000023C Endpoint Type (IN/OUT) Indication *1 */
+ __IOM uint32_t ARB_EP2_CFG; /*!< 0x00000240 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */
+ __IM uint32_t RESERVED17[3];
+ __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */
+ __IOM uint32_t USB_CLK_EN; /*!< 0x00000274 USB Block Clock Enable Register */
+ __IOM uint32_t ARB_INT_EN; /*!< 0x00000278 Arbiter Interrupt Enable *1 */
+ __IM uint32_t ARB_INT_SR; /*!< 0x0000027C Arbiter Interrupt Status *1 */
+ __IOM uint32_t ARB_EP3_CFG; /*!< 0x00000280 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */
+ __IM uint32_t RESERVED19[3];
+ __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */
+ __IOM uint32_t CWA_MSB; /*!< 0x000002B4 Endpoint Read Address value *1 */
+ __IM uint32_t RESERVED20[2];
+ __IOM uint32_t ARB_EP4_CFG; /*!< 0x000002C0 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */
+ __IM uint32_t RESERVED22[3];
+ __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */
+ __IOM uint32_t DMA_THRES_MSB; /*!< 0x000002F4 DMA Burst / Threshold Configuration */
+ __IM uint32_t RESERVED23[2];
+ __IOM uint32_t ARB_EP5_CFG; /*!< 0x00000300 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */
+ __IM uint32_t RESERVED25[3];
+ __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */
+ __IM uint32_t RESERVED26[3];
+ __IOM uint32_t ARB_EP6_CFG; /*!< 0x00000340 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */
+ __IM uint32_t RESERVED28[7];
+ __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED29;
+ __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */
+ __IM uint32_t RESERVED30[7];
+ __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */
+ __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */
+ __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */
+ __IM uint32_t RESERVED31;
+ __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1 */
+ __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1 */
+ __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */
+ __IM uint32_t RESERVED32[7];
+ __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */
+ __IM uint32_t RESERVED33[280];
+ __IM uint32_t SOF16; /*!< 0x00001060 Start Of Frame Register */
+ __IM uint32_t RESERVED34[7];
+ __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */
+ __IM uint32_t RESERVED35[99];
+ __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value */
+ __IM uint32_t RESERVED36;
+ __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value */
+ __IM uint32_t RESERVED37;
+ __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */
+ __IM uint32_t RESERVED38[11];
+ __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value */
+ __IM uint32_t RESERVED39;
+ __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value */
+ __IM uint32_t RESERVED40;
+ __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */
+ __IM uint32_t RESERVED41[11];
+ __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value */
+ __IM uint32_t RESERVED42;
+ __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value */
+ __IM uint32_t RESERVED43;
+ __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */
+ __IM uint32_t RESERVED44[3];
+ __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */
+ __IM uint32_t RESERVED45[7];
+ __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value */
+ __IM uint32_t RESERVED46;
+ __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value */
+ __IM uint32_t RESERVED47;
+ __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */
+ __IM uint32_t RESERVED48[3];
+ __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */
+ __IM uint32_t RESERVED49[7];
+ __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value */
+ __IM uint32_t RESERVED50;
+ __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value */
+ __IM uint32_t RESERVED51;
+ __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */
+ __IM uint32_t RESERVED52[11];
+ __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value */
+ __IM uint32_t RESERVED53;
+ __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value */
+ __IM uint32_t RESERVED54;
+ __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */
+ __IM uint32_t RESERVED55[11];
+ __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value */
+ __IM uint32_t RESERVED56;
+ __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value */
+ __IM uint32_t RESERVED57;
+ __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */
+ __IM uint32_t RESERVED58[11];
+ __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value */
+ __IM uint32_t RESERVED59;
+ __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value */
+ __IM uint32_t RESERVED60;
+ __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */
+ __IM uint32_t RESERVED61[775];
+} USBFS_USBDEV_Type; /*!< Size = 8192 (0x2000) */
+
+/**
+ * \brief USB Device LPM and PHY Test (USBFS_USBLPM)
+ */
+typedef struct {
+ __IOM uint32_t POWER_CTL; /*!< 0x00000000 Power Control Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t USBIO_CTL; /*!< 0x00000008 USB IO Control Register */
+ __IOM uint32_t FLOW_CTL; /*!< 0x0000000C Flow Control Register */
+ __IOM uint32_t LPM_CTL; /*!< 0x00000010 LPM Control Register */
+ __IM uint32_t LPM_STAT; /*!< 0x00000014 LPM Status register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t INTR_SIE; /*!< 0x00000020 USB SOF, BUS RESET and EP0 Interrupt Status */
+ __IOM uint32_t INTR_SIE_SET; /*!< 0x00000024 USB SOF, BUS RESET and EP0 Interrupt Set */
+ __IOM uint32_t INTR_SIE_MASK; /*!< 0x00000028 USB SOF, BUS RESET and EP0 Interrupt Mask */
+ __IM uint32_t INTR_SIE_MASKED; /*!< 0x0000002C USB SOF, BUS RESET and EP0 Interrupt Masked */
+ __IOM uint32_t INTR_LVL_SEL; /*!< 0x00000030 Select interrupt level for each interrupt source */
+ __IM uint32_t INTR_CAUSE_HI; /*!< 0x00000034 High priority interrupt Cause register */
+ __IM uint32_t INTR_CAUSE_MED; /*!< 0x00000038 Medium priority interrupt Cause register */
+ __IM uint32_t INTR_CAUSE_LO; /*!< 0x0000003C Low priority interrupt Cause register */
+ __IM uint32_t RESERVED2[12];
+ __IOM uint32_t DFT_CTL; /*!< 0x00000070 DFT control */
+ __IM uint32_t RESERVED3[995];
+} USBFS_USBLPM_Type; /*!< Size = 4096 (0x1000) */
+
+/**
+ * \brief USB Host Controller (USBFS_USBHOST)
+ */
+typedef struct {
+ __IOM uint32_t HOST_CTL0; /*!< 0x00000000 Host Control 0 Register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t HOST_CTL1; /*!< 0x00000010 Host Control 1 Register. */
+ __IM uint32_t RESERVED1[59];
+ __IOM uint32_t HOST_CTL2; /*!< 0x00000100 Host Control 2 Register. */
+ __IOM uint32_t HOST_ERR; /*!< 0x00000104 Host Error Status Register. */
+ __IOM uint32_t HOST_STATUS; /*!< 0x00000108 Host Status Register. */
+ __IOM uint32_t HOST_FCOMP; /*!< 0x0000010C Host SOF Interrupt Frame Compare Register */
+ __IOM uint32_t HOST_RTIMER; /*!< 0x00000110 Host Retry Timer Setup Register */
+ __IOM uint32_t HOST_ADDR; /*!< 0x00000114 Host Address Register */
+ __IOM uint32_t HOST_EOF; /*!< 0x00000118 Host EOF Setup Register */
+ __IOM uint32_t HOST_FRAME; /*!< 0x0000011C Host Frame Setup Register */
+ __IOM uint32_t HOST_TOKEN; /*!< 0x00000120 Host Token Endpoint Register */
+ __IM uint32_t RESERVED2[183];
+ __IOM uint32_t HOST_EP1_CTL; /*!< 0x00000400 Host Endpoint 1 Control Register */
+ __IM uint32_t HOST_EP1_STATUS; /*!< 0x00000404 Host Endpoint 1 Status Register */
+ __IOM uint32_t HOST_EP1_RW1_DR; /*!< 0x00000408 Host Endpoint 1 Data 1-Byte Register */
+ __IOM uint32_t HOST_EP1_RW2_DR; /*!< 0x0000040C Host Endpoint 1 Data 2-Byte Register */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t HOST_EP2_CTL; /*!< 0x00000500 Host Endpoint 2 Control Register */
+ __IM uint32_t HOST_EP2_STATUS; /*!< 0x00000504 Host Endpoint 2 Status Register */
+ __IOM uint32_t HOST_EP2_RW1_DR; /*!< 0x00000508 Host Endpoint 2 Data 1-Byte Register */
+ __IOM uint32_t HOST_EP2_RW2_DR; /*!< 0x0000050C Host Endpoint 2 Data 2-Byte Register */
+ __IM uint32_t RESERVED4[188];
+ __IOM uint32_t HOST_LVL1_SEL; /*!< 0x00000800 Host Interrupt Level 1 Selection Register */
+ __IOM uint32_t HOST_LVL2_SEL; /*!< 0x00000804 Host Interrupt Level 2 Selection Register */
+ __IM uint32_t RESERVED5[62];
+ __IM uint32_t INTR_USBHOST_CAUSE_HI; /*!< 0x00000900 Interrupt USB Host Cause High Register */
+ __IM uint32_t INTR_USBHOST_CAUSE_MED; /*!< 0x00000904 Interrupt USB Host Cause Medium Register */
+ __IM uint32_t INTR_USBHOST_CAUSE_LO; /*!< 0x00000908 Interrupt USB Host Cause Low Register */
+ __IM uint32_t RESERVED6[5];
+ __IM uint32_t INTR_HOST_EP_CAUSE_HI; /*!< 0x00000920 Interrupt USB Host Endpoint Cause High Register */
+ __IM uint32_t INTR_HOST_EP_CAUSE_MED; /*!< 0x00000924 Interrupt USB Host Endpoint Cause Medium Register */
+ __IM uint32_t INTR_HOST_EP_CAUSE_LO; /*!< 0x00000928 Interrupt USB Host Endpoint Cause Low Register */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t INTR_USBHOST; /*!< 0x00000940 Interrupt USB Host Register */
+ __IOM uint32_t INTR_USBHOST_SET; /*!< 0x00000944 Interrupt USB Host Set Register */
+ __IOM uint32_t INTR_USBHOST_MASK; /*!< 0x00000948 Interrupt USB Host Mask Register */
+ __IM uint32_t INTR_USBHOST_MASKED; /*!< 0x0000094C Interrupt USB Host Masked Register */
+ __IM uint32_t RESERVED8[44];
+ __IOM uint32_t INTR_HOST_EP; /*!< 0x00000A00 Interrupt USB Host Endpoint Register */
+ __IOM uint32_t INTR_HOST_EP_SET; /*!< 0x00000A04 Interrupt USB Host Endpoint Set Register */
+ __IOM uint32_t INTR_HOST_EP_MASK; /*!< 0x00000A08 Interrupt USB Host Endpoint Mask Register */
+ __IM uint32_t INTR_HOST_EP_MASKED; /*!< 0x00000A0C Interrupt USB Host Endpoint Masked Register */
+ __IM uint32_t RESERVED9[60];
+ __IOM uint32_t HOST_DMA_ENBL; /*!< 0x00000B00 Host DMA Enable Register */
+ __IM uint32_t RESERVED10[7];
+ __IOM uint32_t HOST_EP1_BLK; /*!< 0x00000B20 Host Endpoint 1 Block Register */
+ __IM uint32_t RESERVED11[3];
+ __IOM uint32_t HOST_EP2_BLK; /*!< 0x00000B30 Host Endpoint 2 Block Register */
+ __IM uint32_t RESERVED12[1331];
+} USBFS_USBHOST_Type; /*!< Size = 8192 (0x2000) */
+
+/**
+ * \brief USB Host and Device Controller (USBFS)
+ */
+typedef struct {
+ USBFS_USBDEV_Type USBDEV; /*!< 0x00000000 USB Device */
+ USBFS_USBLPM_Type USBLPM; /*!< 0x00002000 USB Device LPM and PHY Test */
+ __IM uint32_t RESERVED[1024];
+ USBFS_USBHOST_Type USBHOST; /*!< 0x00004000 USB Host Controller */
+} USBFS_Type; /*!< Size = 24576 (0x6000) */
+
+
+/* USBFS_USBDEV.EP0_DR */
+#define USBFS_USBDEV_EP0_DR_DATA_BYTE_Pos 0UL
+#define USBFS_USBDEV_EP0_DR_DATA_BYTE_Msk 0xFFUL
+/* USBFS_USBDEV.CR0 */
+#define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Pos 0UL
+#define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Msk 0x7FUL
+#define USBFS_USBDEV_CR0_USB_ENABLE_Pos 7UL
+#define USBFS_USBDEV_CR0_USB_ENABLE_Msk 0x80UL
+/* USBFS_USBDEV.CR1 */
+#define USBFS_USBDEV_CR1_REG_ENABLE_Pos 0UL
+#define USBFS_USBDEV_CR1_REG_ENABLE_Msk 0x1UL
+#define USBFS_USBDEV_CR1_ENABLE_LOCK_Pos 1UL
+#define USBFS_USBDEV_CR1_ENABLE_LOCK_Msk 0x2UL
+#define USBFS_USBDEV_CR1_BUS_ACTIVITY_Pos 2UL
+#define USBFS_USBDEV_CR1_BUS_ACTIVITY_Msk 0x4UL
+#define USBFS_USBDEV_CR1_RESERVED_3_Pos 3UL
+#define USBFS_USBDEV_CR1_RESERVED_3_Msk 0x8UL
+/* USBFS_USBDEV.SIE_EP_INT_EN */
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Pos 0UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Msk 0x1UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Pos 1UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Msk 0x2UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Pos 2UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Msk 0x4UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Pos 3UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Msk 0x8UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Pos 7UL
+#define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP_INT_SR */
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Pos 0UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Msk 0x1UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Pos 1UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Msk 0x2UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Pos 2UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Msk 0x4UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Pos 3UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Msk 0x8UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Pos 4UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Pos 5UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Pos 6UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Pos 7UL
+#define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP1_CNT0 */
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP1_CNT1 */
+#define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP1_CR0 */
+#define USBFS_USBDEV_SIE_EP1_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP1_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP1_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR0 */
+#define USBFS_USBDEV_USBIO_CR0_RD_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR0_RD_Msk 0x1UL
+#define USBFS_USBDEV_USBIO_CR0_TD_Pos 5UL
+#define USBFS_USBDEV_USBIO_CR0_TD_Msk 0x20UL
+#define USBFS_USBDEV_USBIO_CR0_TSE0_Pos 6UL
+#define USBFS_USBDEV_USBIO_CR0_TSE0_Msk 0x40UL
+#define USBFS_USBDEV_USBIO_CR0_TEN_Pos 7UL
+#define USBFS_USBDEV_USBIO_CR0_TEN_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR2 */
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Msk 0x3FUL
+#define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Pos 6UL
+#define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Msk 0x40UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Pos 7UL
+#define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Msk 0x80UL
+/* USBFS_USBDEV.USBIO_CR1 */
+#define USBFS_USBDEV_USBIO_CR1_DMO_Pos 0UL
+#define USBFS_USBDEV_USBIO_CR1_DMO_Msk 0x1UL
+#define USBFS_USBDEV_USBIO_CR1_DPO_Pos 1UL
+#define USBFS_USBDEV_USBIO_CR1_DPO_Msk 0x2UL
+#define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Pos 2UL
+#define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Msk 0x4UL
+#define USBFS_USBDEV_USBIO_CR1_IOMODE_Pos 5UL
+#define USBFS_USBDEV_USBIO_CR1_IOMODE_Msk 0x20UL
+/* USBFS_USBDEV.DYN_RECONFIG */
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Pos 0UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Msk 0x1UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Pos 1UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Msk 0xEUL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Pos 4UL
+#define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Msk 0x10UL
+/* USBFS_USBDEV.SOF0 */
+#define USBFS_USBDEV_SOF0_FRAME_NUMBER_Pos 0UL
+#define USBFS_USBDEV_SOF0_FRAME_NUMBER_Msk 0xFFUL
+/* USBFS_USBDEV.SOF1 */
+#define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Pos 0UL
+#define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Msk 0x7UL
+/* USBFS_USBDEV.SIE_EP2_CNT0 */
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP2_CNT1 */
+#define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP2_CR0 */
+#define USBFS_USBDEV_SIE_EP2_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP2_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP2_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP2_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.OSCLK_DR0 */
+#define USBFS_USBDEV_OSCLK_DR0_ADDER_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR0_ADDER_Msk 0xFFUL
+/* USBFS_USBDEV.OSCLK_DR1 */
+#define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Msk 0x7FUL
+/* USBFS_USBDEV.EP0_CR */
+#define USBFS_USBDEV_EP0_CR_MODE_Pos 0UL
+#define USBFS_USBDEV_EP0_CR_MODE_Msk 0xFUL
+#define USBFS_USBDEV_EP0_CR_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_EP0_CR_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_EP0_CR_OUT_RCVD_Pos 5UL
+#define USBFS_USBDEV_EP0_CR_OUT_RCVD_Msk 0x20UL
+#define USBFS_USBDEV_EP0_CR_IN_RCVD_Pos 6UL
+#define USBFS_USBDEV_EP0_CR_IN_RCVD_Msk 0x40UL
+#define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Pos 7UL
+#define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Msk 0x80UL
+/* USBFS_USBDEV.EP0_CNT */
+#define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Pos 0UL
+#define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Msk 0xFUL
+#define USBFS_USBDEV_EP0_CNT_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_EP0_CNT_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP3_CNT0 */
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP3_CNT1 */
+#define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP3_CR0 */
+#define USBFS_USBDEV_SIE_EP3_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP3_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP3_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP3_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP4_CNT0 */
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP4_CNT1 */
+#define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP4_CR0 */
+#define USBFS_USBDEV_SIE_EP4_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP4_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP4_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP4_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP5_CNT0 */
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP5_CNT1 */
+#define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP5_CR0 */
+#define USBFS_USBDEV_SIE_EP5_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP5_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP5_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP5_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP6_CNT0 */
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP6_CNT1 */
+#define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP6_CR0 */
+#define USBFS_USBDEV_SIE_EP6_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP6_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP6_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP6_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP7_CNT0 */
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP7_CNT1 */
+#define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP7_CR0 */
+#define USBFS_USBDEV_SIE_EP7_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP7_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP7_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP7_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP8_CNT0 */
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Msk 0x7UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Pos 6UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Pos 7UL
+#define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Msk 0x80UL
+/* USBFS_USBDEV.SIE_EP8_CNT1 */
+#define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Msk 0xFFUL
+/* USBFS_USBDEV.SIE_EP8_CR0 */
+#define USBFS_USBDEV_SIE_EP8_CR0_MODE_Pos 0UL
+#define USBFS_USBDEV_SIE_EP8_CR0_MODE_Msk 0xFUL
+#define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Pos 4UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Msk 0x10UL
+#define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Pos 5UL
+#define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Msk 0x20UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Pos 6UL
+#define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Msk 0x40UL
+#define USBFS_USBDEV_SIE_EP8_CR0_STALL_Pos 7UL
+#define USBFS_USBDEV_SIE_EP8_CR0_STALL_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP1_CFG */
+#define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP1_INT_EN */
+#define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP1_SR */
+#define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW1_WA */
+#define USBFS_USBDEV_ARB_RW1_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW1_WA_MSB */
+#define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW1_RA */
+#define USBFS_USBDEV_ARB_RW1_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW1_RA_MSB */
+#define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW1_DR */
+#define USBFS_USBDEV_ARB_RW1_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.BUF_SIZE */
+#define USBFS_USBDEV_BUF_SIZE_IN_BUF_Pos 0UL
+#define USBFS_USBDEV_BUF_SIZE_IN_BUF_Msk 0xFUL
+#define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Pos 4UL
+#define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Msk 0xF0UL
+/* USBFS_USBDEV.EP_ACTIVE */
+#define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Pos 0UL
+#define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Msk 0x1UL
+#define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Pos 1UL
+#define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Msk 0x2UL
+#define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Pos 2UL
+#define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Msk 0x4UL
+#define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Pos 3UL
+#define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Msk 0x8UL
+#define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Pos 4UL
+#define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Msk 0x10UL
+#define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Pos 5UL
+#define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Msk 0x20UL
+#define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Pos 6UL
+#define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Msk 0x40UL
+#define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Pos 7UL
+#define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Msk 0x80UL
+/* USBFS_USBDEV.EP_TYPE */
+#define USBFS_USBDEV_EP_TYPE_EP1_TYP_Pos 0UL
+#define USBFS_USBDEV_EP_TYPE_EP1_TYP_Msk 0x1UL
+#define USBFS_USBDEV_EP_TYPE_EP2_TYP_Pos 1UL
+#define USBFS_USBDEV_EP_TYPE_EP2_TYP_Msk 0x2UL
+#define USBFS_USBDEV_EP_TYPE_EP3_TYP_Pos 2UL
+#define USBFS_USBDEV_EP_TYPE_EP3_TYP_Msk 0x4UL
+#define USBFS_USBDEV_EP_TYPE_EP4_TYP_Pos 3UL
+#define USBFS_USBDEV_EP_TYPE_EP4_TYP_Msk 0x8UL
+#define USBFS_USBDEV_EP_TYPE_EP5_TYP_Pos 4UL
+#define USBFS_USBDEV_EP_TYPE_EP5_TYP_Msk 0x10UL
+#define USBFS_USBDEV_EP_TYPE_EP6_TYP_Pos 5UL
+#define USBFS_USBDEV_EP_TYPE_EP6_TYP_Msk 0x20UL
+#define USBFS_USBDEV_EP_TYPE_EP7_TYP_Pos 6UL
+#define USBFS_USBDEV_EP_TYPE_EP7_TYP_Msk 0x40UL
+#define USBFS_USBDEV_EP_TYPE_EP8_TYP_Pos 7UL
+#define USBFS_USBDEV_EP_TYPE_EP8_TYP_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP2_CFG */
+#define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP2_INT_EN */
+#define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP2_SR */
+#define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW2_WA */
+#define USBFS_USBDEV_ARB_RW2_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW2_WA_MSB */
+#define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW2_RA */
+#define USBFS_USBDEV_ARB_RW2_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW2_RA_MSB */
+#define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW2_DR */
+#define USBFS_USBDEV_ARB_RW2_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_CFG */
+#define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Pos 4UL
+#define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk 0x10UL
+#define USBFS_USBDEV_ARB_CFG_DMA_CFG_Pos 5UL
+#define USBFS_USBDEV_ARB_CFG_DMA_CFG_Msk 0x60UL
+#define USBFS_USBDEV_ARB_CFG_CFG_CMP_Pos 7UL
+#define USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk 0x80UL
+/* USBFS_USBDEV.USB_CLK_EN */
+#define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Pos 0UL
+#define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk 0x1UL
+/* USBFS_USBDEV.ARB_INT_EN */
+#define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Msk 0x20UL
+#define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Pos 6UL
+#define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Msk 0x40UL
+#define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Pos 7UL
+#define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Msk 0x80UL
+/* USBFS_USBDEV.ARB_INT_SR */
+#define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Pos 0UL
+#define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Msk 0x1UL
+#define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Pos 1UL
+#define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Msk 0x2UL
+#define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Pos 2UL
+#define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Msk 0x4UL
+#define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Pos 3UL
+#define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Msk 0x8UL
+#define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Pos 4UL
+#define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Msk 0x10UL
+#define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Pos 5UL
+#define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Msk 0x20UL
+#define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Pos 6UL
+#define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Msk 0x40UL
+#define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Pos 7UL
+#define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Msk 0x80UL
+/* USBFS_USBDEV.ARB_EP3_CFG */
+#define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP3_INT_EN */
+#define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP3_SR */
+#define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW3_WA */
+#define USBFS_USBDEV_ARB_RW3_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW3_WA_MSB */
+#define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW3_RA */
+#define USBFS_USBDEV_ARB_RW3_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW3_RA_MSB */
+#define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW3_DR */
+#define USBFS_USBDEV_ARB_RW3_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.CWA */
+#define USBFS_USBDEV_CWA_CWA_Pos 0UL
+#define USBFS_USBDEV_CWA_CWA_Msk 0xFFUL
+/* USBFS_USBDEV.CWA_MSB */
+#define USBFS_USBDEV_CWA_MSB_CWA_MSB_Pos 0UL
+#define USBFS_USBDEV_CWA_MSB_CWA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_EP4_CFG */
+#define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP4_INT_EN */
+#define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP4_SR */
+#define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW4_WA */
+#define USBFS_USBDEV_ARB_RW4_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW4_WA_MSB */
+#define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW4_RA */
+#define USBFS_USBDEV_ARB_RW4_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW4_RA_MSB */
+#define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW4_DR */
+#define USBFS_USBDEV_ARB_RW4_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.DMA_THRES */
+#define USBFS_USBDEV_DMA_THRES_DMA_THS_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES_DMA_THS_Msk 0xFFUL
+/* USBFS_USBDEV.DMA_THRES_MSB */
+#define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_EP5_CFG */
+#define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP5_INT_EN */
+#define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP5_SR */
+#define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW5_WA */
+#define USBFS_USBDEV_ARB_RW5_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW5_WA_MSB */
+#define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW5_RA */
+#define USBFS_USBDEV_ARB_RW5_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW5_RA_MSB */
+#define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW5_DR */
+#define USBFS_USBDEV_ARB_RW5_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.BUS_RST_CNT */
+#define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Pos 0UL
+#define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Msk 0xFUL
+/* USBFS_USBDEV.ARB_EP6_CFG */
+#define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP6_INT_EN */
+#define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP6_SR */
+#define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW6_WA */
+#define USBFS_USBDEV_ARB_RW6_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW6_WA_MSB */
+#define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW6_RA */
+#define USBFS_USBDEV_ARB_RW6_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW6_RA_MSB */
+#define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW6_DR */
+#define USBFS_USBDEV_ARB_RW6_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_EP7_CFG */
+#define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP7_INT_EN */
+#define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP7_SR */
+#define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW7_WA */
+#define USBFS_USBDEV_ARB_RW7_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW7_WA_MSB */
+#define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW7_RA */
+#define USBFS_USBDEV_ARB_RW7_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW7_RA_MSB */
+#define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW7_DR */
+#define USBFS_USBDEV_ARB_RW7_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_EP8_CFG */
+#define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Msk 0x8UL
+/* USBFS_USBDEV.ARB_EP8_INT_EN */
+#define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Pos 4UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Msk 0x10UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_EP8_SR */
+#define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Pos 0UL
+#define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Msk 0x1UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Pos 1UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Msk 0x2UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Pos 2UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Msk 0x4UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Pos 3UL
+#define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Msk 0x8UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Pos 5UL
+#define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Msk 0x20UL
+/* USBFS_USBDEV.ARB_RW8_WA */
+#define USBFS_USBDEV_ARB_RW8_WA_WA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA_WA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW8_WA_MSB */
+#define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW8_RA */
+#define USBFS_USBDEV_ARB_RW8_RA_RA_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA_RA_Msk 0xFFUL
+/* USBFS_USBDEV.ARB_RW8_RA_MSB */
+#define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Msk 0x1UL
+/* USBFS_USBDEV.ARB_RW8_DR */
+#define USBFS_USBDEV_ARB_RW8_DR_DR_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_DR_DR_Msk 0xFFUL
+/* USBFS_USBDEV.MEM_DATA */
+#define USBFS_USBDEV_MEM_DATA_DR_Pos 0UL
+#define USBFS_USBDEV_MEM_DATA_DR_Msk 0xFFUL
+/* USBFS_USBDEV.SOF16 */
+#define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Pos 0UL
+#define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Msk 0x7FFUL
+/* USBFS_USBDEV.OSCLK_DR16 */
+#define USBFS_USBDEV_OSCLK_DR16_ADDER16_Pos 0UL
+#define USBFS_USBDEV_OSCLK_DR16_ADDER16_Msk 0x7FFFUL
+/* USBFS_USBDEV.ARB_RW1_WA16 */
+#define USBFS_USBDEV_ARB_RW1_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW1_RA16 */
+#define USBFS_USBDEV_ARB_RW1_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW1_DR16 */
+#define USBFS_USBDEV_ARB_RW1_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW1_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW2_WA16 */
+#define USBFS_USBDEV_ARB_RW2_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW2_RA16 */
+#define USBFS_USBDEV_ARB_RW2_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW2_DR16 */
+#define USBFS_USBDEV_ARB_RW2_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW2_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW3_WA16 */
+#define USBFS_USBDEV_ARB_RW3_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW3_RA16 */
+#define USBFS_USBDEV_ARB_RW3_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW3_DR16 */
+#define USBFS_USBDEV_ARB_RW3_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW3_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.CWA16 */
+#define USBFS_USBDEV_CWA16_CWA16_Pos 0UL
+#define USBFS_USBDEV_CWA16_CWA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_WA16 */
+#define USBFS_USBDEV_ARB_RW4_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_RA16 */
+#define USBFS_USBDEV_ARB_RW4_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW4_DR16 */
+#define USBFS_USBDEV_ARB_RW4_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW4_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.DMA_THRES16 */
+#define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Pos 0UL
+#define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_WA16 */
+#define USBFS_USBDEV_ARB_RW5_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_RA16 */
+#define USBFS_USBDEV_ARB_RW5_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW5_DR16 */
+#define USBFS_USBDEV_ARB_RW5_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW5_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW6_WA16 */
+#define USBFS_USBDEV_ARB_RW6_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW6_RA16 */
+#define USBFS_USBDEV_ARB_RW6_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW6_DR16 */
+#define USBFS_USBDEV_ARB_RW6_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW6_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW7_WA16 */
+#define USBFS_USBDEV_ARB_RW7_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW7_RA16 */
+#define USBFS_USBDEV_ARB_RW7_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW7_DR16 */
+#define USBFS_USBDEV_ARB_RW7_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW7_DR16_DR16_Msk 0xFFFFUL
+/* USBFS_USBDEV.ARB_RW8_WA16 */
+#define USBFS_USBDEV_ARB_RW8_WA16_WA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_WA16_WA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW8_RA16 */
+#define USBFS_USBDEV_ARB_RW8_RA16_RA16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_RA16_RA16_Msk 0x1FFUL
+/* USBFS_USBDEV.ARB_RW8_DR16 */
+#define USBFS_USBDEV_ARB_RW8_DR16_DR16_Pos 0UL
+#define USBFS_USBDEV_ARB_RW8_DR16_DR16_Msk 0xFFFFUL
+
+
+/* USBFS_USBLPM.POWER_CTL */
+#define USBFS_USBLPM_POWER_CTL_SUSPEND_Pos 2UL
+#define USBFS_USBLPM_POWER_CTL_SUSPEND_Msk 0x4UL
+#define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Pos 16UL
+#define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Msk 0x10000UL
+#define USBFS_USBLPM_POWER_CTL_DP_BIG_Pos 17UL
+#define USBFS_USBLPM_POWER_CTL_DP_BIG_Msk 0x20000UL
+#define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Pos 18UL
+#define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Msk 0x40000UL
+#define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Pos 19UL
+#define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Msk 0x80000UL
+#define USBFS_USBLPM_POWER_CTL_DM_BIG_Pos 20UL
+#define USBFS_USBLPM_POWER_CTL_DM_BIG_Msk 0x100000UL
+#define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Pos 21UL
+#define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Msk 0x200000UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Pos 28UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Msk 0x10000000UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Pos 29UL
+#define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Msk 0x20000000UL
+/* USBFS_USBLPM.USBIO_CTL */
+#define USBFS_USBLPM_USBIO_CTL_DM_P_Pos 0UL
+#define USBFS_USBLPM_USBIO_CTL_DM_P_Msk 0x7UL
+#define USBFS_USBLPM_USBIO_CTL_DM_M_Pos 3UL
+#define USBFS_USBLPM_USBIO_CTL_DM_M_Msk 0x38UL
+/* USBFS_USBLPM.FLOW_CTL */
+#define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Pos 0UL
+#define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Msk 0x1UL
+#define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Pos 1UL
+#define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Msk 0x2UL
+#define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Pos 2UL
+#define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Msk 0x4UL
+#define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Pos 3UL
+#define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Msk 0x8UL
+#define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Pos 4UL
+#define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Msk 0x10UL
+#define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Pos 5UL
+#define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Msk 0x20UL
+#define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Pos 6UL
+#define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Msk 0x40UL
+#define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Pos 7UL
+#define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Msk 0x80UL
+/* USBFS_USBLPM.LPM_CTL */
+#define USBFS_USBLPM_LPM_CTL_LPM_EN_Pos 0UL
+#define USBFS_USBLPM_LPM_CTL_LPM_EN_Msk 0x1UL
+#define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Pos 1UL
+#define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Msk 0x2UL
+#define USBFS_USBLPM_LPM_CTL_NYET_EN_Pos 2UL
+#define USBFS_USBLPM_LPM_CTL_NYET_EN_Msk 0x4UL
+#define USBFS_USBLPM_LPM_CTL_SUB_RESP_Pos 4UL
+#define USBFS_USBLPM_LPM_CTL_SUB_RESP_Msk 0x10UL
+/* USBFS_USBLPM.LPM_STAT */
+#define USBFS_USBLPM_LPM_STAT_LPM_BESL_Pos 0UL
+#define USBFS_USBLPM_LPM_STAT_LPM_BESL_Msk 0xFUL
+#define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Pos 4UL
+#define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE */
+#define USBFS_USBLPM_INTR_SIE_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_SET */
+#define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_MASK */
+#define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Msk 0x10UL
+/* USBFS_USBLPM.INTR_SIE_MASKED */
+#define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Pos 0UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Msk 0x1UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Pos 1UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Msk 0x2UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Pos 2UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Msk 0x4UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Pos 3UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Msk 0x8UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Pos 4UL
+#define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Msk 0x10UL
+/* USBFS_USBLPM.INTR_LVL_SEL */
+#define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Pos 0UL
+#define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Msk 0x3UL
+#define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Pos 2UL
+#define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Msk 0xCUL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Pos 4UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Msk 0x30UL
+#define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Pos 6UL
+#define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Msk 0xC0UL
+#define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Pos 8UL
+#define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Msk 0x300UL
+#define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Pos 14UL
+#define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Msk 0xC000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Pos 16UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Msk 0x30000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Pos 18UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Msk 0xC0000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Pos 20UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Msk 0x300000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Pos 22UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Msk 0xC00000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Pos 24UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Msk 0x3000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Pos 26UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Msk 0xC000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Pos 28UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Msk 0x30000000UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Pos 30UL
+#define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Msk 0xC0000000UL
+/* USBFS_USBLPM.INTR_CAUSE_HI */
+#define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.INTR_CAUSE_MED */
+#define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.INTR_CAUSE_LO */
+#define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Pos 0UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Msk 0x1UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Pos 1UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Msk 0x2UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Pos 2UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Msk 0x4UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Pos 3UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Msk 0x8UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Pos 4UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Msk 0x10UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Pos 7UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Msk 0x80UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Pos 8UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Msk 0x100UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Pos 9UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Msk 0x200UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Pos 10UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Msk 0x400UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Pos 11UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Msk 0x800UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Pos 12UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Msk 0x1000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Pos 13UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Msk 0x2000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Pos 14UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Msk 0x4000UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Pos 15UL
+#define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Msk 0x8000UL
+/* USBFS_USBLPM.DFT_CTL */
+#define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Pos 0UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Msk 0x7UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Pos 3UL
+#define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Msk 0x18UL
+
+
+/* USBFS_USBHOST.HOST_CTL0 */
+#define USBFS_USBHOST_HOST_CTL0_HOST_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL0_HOST_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL0_ENABLE_Pos 31UL
+#define USBFS_USBHOST_HOST_CTL0_ENABLE_Msk 0x80000000UL
+/* USBFS_USBHOST.HOST_CTL1 */
+#define USBFS_USBHOST_HOST_CTL1_CLKSEL_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL1_CLKSEL_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL1_USTP_Pos 1UL
+#define USBFS_USBHOST_HOST_CTL1_USTP_Msk 0x2UL
+#define USBFS_USBHOST_HOST_CTL1_RST_Pos 7UL
+#define USBFS_USBHOST_HOST_CTL1_RST_Msk 0x80UL
+/* USBFS_USBHOST.HOST_CTL2 */
+#define USBFS_USBHOST_HOST_CTL2_RETRY_Pos 0UL
+#define USBFS_USBHOST_HOST_CTL2_RETRY_Msk 0x1UL
+#define USBFS_USBHOST_HOST_CTL2_CANCEL_Pos 1UL
+#define USBFS_USBHOST_HOST_CTL2_CANCEL_Msk 0x2UL
+#define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Pos 2UL
+#define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Msk 0x4UL
+#define USBFS_USBHOST_HOST_CTL2_ALIVE_Pos 3UL
+#define USBFS_USBHOST_HOST_CTL2_ALIVE_Msk 0x8UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Pos 4UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Msk 0x10UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Pos 5UL
+#define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Msk 0x20UL
+#define USBFS_USBHOST_HOST_CTL2_TTEST_Pos 6UL
+#define USBFS_USBHOST_HOST_CTL2_TTEST_Msk 0xC0UL
+/* USBFS_USBHOST.HOST_ERR */
+#define USBFS_USBHOST_HOST_ERR_HS_Pos 0UL
+#define USBFS_USBHOST_HOST_ERR_HS_Msk 0x3UL
+#define USBFS_USBHOST_HOST_ERR_STUFF_Pos 2UL
+#define USBFS_USBHOST_HOST_ERR_STUFF_Msk 0x4UL
+#define USBFS_USBHOST_HOST_ERR_TGERR_Pos 3UL
+#define USBFS_USBHOST_HOST_ERR_TGERR_Msk 0x8UL
+#define USBFS_USBHOST_HOST_ERR_CRC_Pos 4UL
+#define USBFS_USBHOST_HOST_ERR_CRC_Msk 0x10UL
+#define USBFS_USBHOST_HOST_ERR_TOUT_Pos 5UL
+#define USBFS_USBHOST_HOST_ERR_TOUT_Msk 0x20UL
+#define USBFS_USBHOST_HOST_ERR_RERR_Pos 6UL
+#define USBFS_USBHOST_HOST_ERR_RERR_Msk 0x40UL
+#define USBFS_USBHOST_HOST_ERR_LSTSOF_Pos 7UL
+#define USBFS_USBHOST_HOST_ERR_LSTSOF_Msk 0x80UL
+/* USBFS_USBHOST.HOST_STATUS */
+#define USBFS_USBHOST_HOST_STATUS_CSTAT_Pos 0UL
+#define USBFS_USBHOST_HOST_STATUS_CSTAT_Msk 0x1UL
+#define USBFS_USBHOST_HOST_STATUS_TMODE_Pos 1UL
+#define USBFS_USBHOST_HOST_STATUS_TMODE_Msk 0x2UL
+#define USBFS_USBHOST_HOST_STATUS_SUSP_Pos 2UL
+#define USBFS_USBHOST_HOST_STATUS_SUSP_Msk 0x4UL
+#define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Pos 3UL
+#define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Msk 0x8UL
+#define USBFS_USBHOST_HOST_STATUS_URST_Pos 4UL
+#define USBFS_USBHOST_HOST_STATUS_URST_Msk 0x10UL
+#define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Pos 5UL
+#define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Msk 0x20UL
+#define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Pos 6UL
+#define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Msk 0x40UL
+#define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Pos 7UL
+#define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Msk 0x80UL
+#define USBFS_USBHOST_HOST_STATUS_HOST_ST_Pos 8UL
+#define USBFS_USBHOST_HOST_STATUS_HOST_ST_Msk 0x100UL
+/* USBFS_USBHOST.HOST_FCOMP */
+#define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Pos 0UL
+#define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_RTIMER */
+#define USBFS_USBHOST_HOST_RTIMER_RTIMER_Pos 0UL
+#define USBFS_USBHOST_HOST_RTIMER_RTIMER_Msk 0x3FFFFUL
+/* USBFS_USBHOST.HOST_ADDR */
+#define USBFS_USBHOST_HOST_ADDR_ADDRESS_Pos 0UL
+#define USBFS_USBHOST_HOST_ADDR_ADDRESS_Msk 0x7FUL
+/* USBFS_USBHOST.HOST_EOF */
+#define USBFS_USBHOST_HOST_EOF_EOF_Pos 0UL
+#define USBFS_USBHOST_HOST_EOF_EOF_Msk 0x3FFFUL
+/* USBFS_USBHOST.HOST_FRAME */
+#define USBFS_USBHOST_HOST_FRAME_FRAME_Pos 0UL
+#define USBFS_USBHOST_HOST_FRAME_FRAME_Msk 0x7FFUL
+/* USBFS_USBHOST.HOST_TOKEN */
+#define USBFS_USBHOST_HOST_TOKEN_ENDPT_Pos 0UL
+#define USBFS_USBHOST_HOST_TOKEN_ENDPT_Msk 0xFUL
+#define USBFS_USBHOST_HOST_TOKEN_TKNEN_Pos 4UL
+#define USBFS_USBHOST_HOST_TOKEN_TKNEN_Msk 0x70UL
+#define USBFS_USBHOST_HOST_TOKEN_TGGL_Pos 8UL
+#define USBFS_USBHOST_HOST_TOKEN_TGGL_Msk 0x100UL
+/* USBFS_USBHOST.HOST_EP1_CTL */
+#define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Msk 0x1FFUL
+#define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Pos 10UL
+#define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Msk 0x400UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Pos 11UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Msk 0x800UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DIR_Pos 12UL
+#define USBFS_USBHOST_HOST_EP1_CTL_DIR_Msk 0x1000UL
+#define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Pos 15UL
+#define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Msk 0x8000UL
+/* USBFS_USBHOST.HOST_EP1_STATUS */
+#define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Msk 0x1FFUL
+#define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Pos 16UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Msk 0x10000UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Pos 17UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Msk 0x20000UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Pos 18UL
+#define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Msk 0x40000UL
+/* USBFS_USBHOST.HOST_EP1_RW1_DR */
+#define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_EP1_RW2_DR */
+#define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Pos 0UL
+#define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Msk 0xFFFFUL
+/* USBFS_USBHOST.HOST_EP2_CTL */
+#define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Msk 0x7FUL
+#define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Pos 10UL
+#define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Msk 0x400UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Pos 11UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Msk 0x800UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DIR_Pos 12UL
+#define USBFS_USBHOST_HOST_EP2_CTL_DIR_Msk 0x1000UL
+#define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Pos 15UL
+#define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Msk 0x8000UL
+/* USBFS_USBHOST.HOST_EP2_STATUS */
+#define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Msk 0x7FUL
+#define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Pos 16UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Msk 0x10000UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Pos 17UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Msk 0x20000UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Pos 18UL
+#define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Msk 0x40000UL
+/* USBFS_USBHOST.HOST_EP2_RW1_DR */
+#define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Msk 0xFFUL
+/* USBFS_USBHOST.HOST_EP2_RW2_DR */
+#define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Pos 0UL
+#define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Msk 0xFFFFUL
+/* USBFS_USBHOST.HOST_LVL1_SEL */
+#define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Pos 0UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Msk 0x3UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Pos 2UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Msk 0xCUL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Pos 4UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Msk 0x30UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Pos 6UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Msk 0xC0UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Pos 8UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Msk 0x300UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Pos 10UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Msk 0xC00UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Pos 12UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Msk 0x3000UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Pos 14UL
+#define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Msk 0xC000UL
+/* USBFS_USBHOST.HOST_LVL2_SEL */
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Pos 4UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Msk 0x30UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Pos 6UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Msk 0xC0UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Pos 8UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Msk 0x300UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Pos 10UL
+#define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Msk 0xC00UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_HI */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_MED */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_CAUSE_LO */
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Msk 0x80UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_HI */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_MED */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_CAUSE_LO */
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Msk 0x20UL
+/* USBFS_USBHOST.INTR_USBHOST */
+#define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_DIRQ_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_DIRQ_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_URIRQ_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_URIRQ_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_TCAN_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_TCAN_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_SET */
+#define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_MASK */
+#define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Msk 0x80UL
+/* USBFS_USBHOST.INTR_USBHOST_MASKED */
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Pos 0UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Msk 0x1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Pos 1UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Msk 0x2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Pos 2UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Msk 0x4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Pos 3UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Msk 0x8UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Pos 4UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Msk 0x10UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Pos 5UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Msk 0x20UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Pos 6UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Msk 0x40UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Pos 7UL
+#define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Msk 0x80UL
+/* USBFS_USBHOST.INTR_HOST_EP */
+#define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_SET */
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_MASK */
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Msk 0x20UL
+/* USBFS_USBHOST.INTR_HOST_EP_MASKED */
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Pos 2UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Msk 0x4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Pos 3UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Msk 0x8UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Pos 4UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Msk 0x10UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Pos 5UL
+#define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Msk 0x20UL
+/* USBFS_USBHOST.HOST_DMA_ENBL */
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Pos 2UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Msk 0x4UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Pos 3UL
+#define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Msk 0x8UL
+/* USBFS_USBHOST.HOST_EP1_BLK */
+#define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Pos 16UL
+#define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Msk 0xFFFF0000UL
+/* USBFS_USBHOST.HOST_EP2_BLK */
+#define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Pos 16UL
+#define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Msk 0xFFFF0000UL
+
+
+#endif /* _CYIP_USBFS_H_ */
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/flash_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "flash_api.h"
+#include "drivers/peripheral/flash/cy_flash.h"
+
+#if DEVICE_FLASH
+
+int32_t flash_init(flash_t *obj)
+{
+ (void)(obj);
+ return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+ (void)(obj);
+ return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ (void)(obj);
+ int32_t status = 0;
+ if (Cy_Flash_EraseRow(address) != CY_FLASH_DRV_SUCCESS) {
+ status = -1;
+ }
+
+ return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+ (void)(obj);
+ int32_t status = 0;
+ if (Cy_Flash_ProgramRow(address, (const uint32_t *)data) != CY_FLASH_DRV_SUCCESS) {
+ status = -1;
+ }
+
+ return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ (void)(obj);
+ if ((address >= CY_FLASH_BASE) && (address < CY_FLASH_BASE + CY_FLASH_SIZE)) {
+ return CY_FLASH_SIZEOF_ROW;
+ }
+
+ return MBED_FLASH_INVALID_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ (void)(obj);
+ return CY_FLASH_SIZEOF_ROW;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ (void)(obj);
+ return CY_FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+ (void)(obj);
+ return CY_FLASH_SIZE;
+}
+
+#endif // DEVICE_FLASH
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,99 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "device.h"
+#include "mbed_assert.h"
+#include "gpio_object.h"
+#include "psoc6_utils.h"
+#include "mbed_error.h"
+#include "rtx_lib.h"
+
+static inline void gpio_set_dir_mode(gpio_t *obj)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->port);
+ MBED_ASSERT(obj->pin != NC);
+
+ uint32_t pin = CY_PIN(obj->pin);
+ uint32_t cymode = gpio_get_cy_drive_mode(obj->dir, obj->mode);
+
+ Cy_GPIO_SetDrivemode(obj->port, pin, cymode);
+
+ if (obj->dir == PIN_INPUT) {
+ // Force output to enable pulls.
+ switch (cymode) {
+ case CY_GPIO_DM_PULLUP:
+ Cy_GPIO_Write(obj->port, pin, 1);
+ break;
+ case CY_GPIO_DM_PULLDOWN:
+ Cy_GPIO_Write(obj->port, pin, 0);
+ break;
+ }
+ }
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ MBED_ASSERT(obj);
+ obj->pin = pin;
+ obj->dir = PIN_INPUT;
+ obj->mode = PullNone;
+
+ if (pin == NC) {
+ return;
+ }
+
+ MBED_ASSERT(CY_PIN(obj->pin) < 8); // PSoC6 architecture supports 8 pins per port.
+
+ /*
+ * Perform i/o reservation only if this is called outside of critical section/interrupt context.
+ * This is a workaround for mbed_die() implementation, which configures LED1 inside critical section.
+ * Normally user is advised to perform all of the i/o configuration at the program beginning,
+ * or elsewhere in the running thread context. when we detect that we are in the wrong context here,
+ * we assume it's explicitly called from mbed_die() or other fault handling, so eventual forcing
+ * of the pin mode is deliberate and should not cause more problems.
+ */
+ if (!(IsIrqMode() || IsIrqMasked())) {
+ if (cy_reserve_io_pin(pin)) {
+ error("GPIO pin reservation conflict.");
+ }
+ }
+ obj->port = Cy_GPIO_PortToAddr(CY_PORT(obj->pin));
+
+ const uint32_t outputVal = 0;
+
+ Cy_GPIO_Pin_FastInit(obj->port, CY_PIN(obj->pin), CY_GPIO_DM_HIGHZ, outputVal, HSIOM_SEL_GPIO);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->pin != NC);
+
+ obj->mode = mode;
+ gpio_set_dir_mode(obj);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->pin != NC);
+
+ obj->dir = direction;
+ gpio_set_dir_mode(obj);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/gpio_irq_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,282 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "device.h"
+#include "mbed_assert.h"
+#include "gpio_object.h"
+#include "gpio_irq_api.h"
+#include "psoc6_utils.h"
+#include "cy_sysint.h"
+
+
+#define NUM_GPIO_PORTS IOSS_GPIO_GPIO_PORT_NR
+#define NUM_GPIO_PORT_PINS 8
+#define GPIO_DEFAULT_IRQ_PRIORITY 5
+
+static gpio_irq_t *irq_objects[NUM_GPIO_PORTS][NUM_GPIO_PORT_PINS] = {NULL};
+
+typedef struct irq_port_info_s {
+ IRQn_Type irqn;
+ uint32_t pin_mask;
+} irq_port_info_t;
+
+static irq_port_info_t irq_port_usage[NUM_GPIO_PORTS] = {{0, 0},};
+
+static void gpio_irq_dispatcher(uint32_t port_id)
+{
+ uint32_t pin;
+ gpio_irq_event event;
+ GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(port_id);
+
+ for (pin = 0; pin < NUM_GPIO_PORT_PINS; ++pin) {
+ if (Cy_GPIO_GetInterruptStatusMasked(port, pin)) {
+ gpio_irq_t *obj = irq_objects[port_id][pin];
+ MBED_ASSERT(obj);
+ Cy_GPIO_ClearInterrupt(port, pin);
+ event = (obj->mode == IRQ_FALL)? IRQ_FALL : IRQ_RISE;
+ obj->handler(obj->id_arg, event);
+ }
+ }
+}
+
+static void gpio_irq_dispatcher_port0(void)
+{
+ gpio_irq_dispatcher(0);
+}
+
+static void gpio_irq_dispatcher_port1(void)
+{
+ gpio_irq_dispatcher(1);
+}
+
+static void gpio_irq_dispatcher_port2(void)
+{
+ gpio_irq_dispatcher(2);
+}
+
+static void gpio_irq_dispatcher_port3(void)
+{
+ gpio_irq_dispatcher(3);
+}
+
+static void gpio_irq_dispatcher_port4(void)
+{
+ gpio_irq_dispatcher(4);
+}
+
+static void gpio_irq_dispatcher_port5(void)
+{
+ gpio_irq_dispatcher(5);
+}
+
+static void gpio_irq_dispatcher_port6(void)
+{
+ gpio_irq_dispatcher(6);
+}
+
+static void gpio_irq_dispatcher_port7(void)
+{
+ gpio_irq_dispatcher(7);
+}
+
+static void gpio_irq_dispatcher_port8(void)
+{
+ gpio_irq_dispatcher(8);
+}
+
+static void gpio_irq_dispatcher_port9(void)
+{
+ gpio_irq_dispatcher(9);
+}
+
+static void gpio_irq_dispatcher_port10(void)
+{
+ gpio_irq_dispatcher(10);
+}
+
+static void gpio_irq_dispatcher_port11(void)
+{
+ gpio_irq_dispatcher(11);
+}
+
+static void gpio_irq_dispatcher_port12(void)
+{
+ gpio_irq_dispatcher(12);
+}
+
+static void gpio_irq_dispatcher_port13(void)
+{
+ gpio_irq_dispatcher(13);
+}
+
+static void gpio_irq_dispatcher_port14(void)
+{
+ gpio_irq_dispatcher(14);
+}
+
+static void (*irq_dispatcher_table[])(void) = {
+ gpio_irq_dispatcher_port0,
+ gpio_irq_dispatcher_port1,
+ gpio_irq_dispatcher_port2,
+ gpio_irq_dispatcher_port3,
+ gpio_irq_dispatcher_port4,
+ gpio_irq_dispatcher_port5,
+ gpio_irq_dispatcher_port6,
+ gpio_irq_dispatcher_port7,
+ gpio_irq_dispatcher_port8,
+ gpio_irq_dispatcher_port9,
+ gpio_irq_dispatcher_port10,
+ gpio_irq_dispatcher_port11,
+ gpio_irq_dispatcher_port12,
+ gpio_irq_dispatcher_port13,
+ gpio_irq_dispatcher_port14
+};
+
+
+static IRQn_Type gpio_irq_allocate_channel(gpio_irq_t *obj)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ obj->cm0p_irq_src = ioss_interrupts_gpio_0_IRQn + obj->port_id;
+ return cy_m0_nvic_allocate_channel(CY_GPIO_IRQN_ID + obj->port_id);
+#else
+ return (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + obj->port_id);
+#endif // M0
+}
+
+static void gpio_irq_release_channel(IRQn_Type channel, uint32_t port_id)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_m0_nvic_release_channel(channel, CY_GPIO_IRQN_ID + port_id);
+#endif //M0
+}
+
+static int gpio_irq_setup_channel(gpio_irq_t *obj)
+{
+ cy_stc_sysint_t irq_config;
+
+ if (irq_port_usage[obj->port_id].pin_mask == 0) {
+ IRQn_Type irqn = gpio_irq_allocate_channel(obj);
+ if (irqn < 0) {
+ return (-1);
+ }
+ irq_port_usage[obj->port_id].irqn = irqn;
+ // Configure NVIC
+ irq_config.intrPriority = GPIO_DEFAULT_IRQ_PRIORITY;
+ irq_config.intrSrc = irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ irq_config.cm0pSrc = obj->cm0p_irq_src;
+#endif
+ if (Cy_SysInt_Init(&irq_config, irq_dispatcher_table[obj->port_id]) != CY_SYSINT_SUCCESS) {
+ return(-1);
+ }
+
+ irq_port_usage[obj->port_id].pin_mask |= (1 << obj->pin);
+ NVIC_EnableIRQ(irqn);
+ }
+
+ return 0;
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ if (pin != NC) {
+ obj->port_id = CY_PORT(pin);
+ obj->port = Cy_GPIO_PortToAddr(obj->port_id);
+ obj->pin = CY_PIN(pin);
+ if (obj->pin > NUM_GPIO_PORT_PINS) {
+ MBED_ASSERT("Invalid pin ID!");
+ return (-1);
+ }
+ obj->handler = handler;
+ obj->id_arg = id;
+ return gpio_irq_setup_channel(obj);
+ } else {
+ return (-1);
+ }
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ gpio_irq_disable(obj);
+ // TODO: Need atomicity for the following operations.
+ NVIC_DisableIRQ(irq_port_usage[obj->port_id].irqn);
+ irq_port_usage[obj->port_id].pin_mask &= ~(1 << obj->pin);
+ if (irq_port_usage[obj->port_id].pin_mask == 0) {
+ gpio_irq_release_channel(irq_port_usage[obj->port_id].irqn, obj->port_id);
+ return;
+ }
+ NVIC_EnableIRQ(irq_port_usage[obj->port_id].irqn);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ if (enable) {
+ if (event == IRQ_RISE) {
+ if (obj->mode == IRQ_FALL) {
+ obj->mode += IRQ_RISE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_BOTH);
+ } else {
+ obj->mode = IRQ_RISE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_RISING);
+ }
+ } else if (event == IRQ_FALL) {
+ if (obj->mode == IRQ_RISE) {
+ obj->mode += IRQ_FALL;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_BOTH);
+ } else {
+ obj->mode = IRQ_FALL;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_FALLING);
+ }
+ } else {
+ obj->mode = IRQ_NONE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE);
+ }
+ } else if (obj->mode != IRQ_NONE) {
+ if (event == IRQ_RISE) {
+ if (obj->mode == IRQ_RISE) {
+ obj->mode = IRQ_NONE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE);
+ } else {
+ obj->mode = IRQ_FALL;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_FALLING);
+ }
+ } else if (event == IRQ_FALL) {
+ if (obj->mode == IRQ_FALL) {
+ obj->mode = IRQ_NONE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE);
+ } else {
+ obj->mode = IRQ_RISE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_RISING);
+ }
+ } else {
+ obj->mode = IRQ_NONE;
+ Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE);
+ }
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ Cy_GPIO_SetInterruptMask(obj->port, obj->pin, 1);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ Cy_GPIO_SetInterruptMask(obj->port, obj->pin, 0);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,85 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_GPIO_OBJECTS_H
+#define MBED_GPIO_OBJECTS_H
+
+#include "mbed_assert.h"
+#include "PinNamesTypes.h"
+#include "PinNames.h"
+
+#include "drivers/peripheral/gpio/cy_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_s {
+ GPIO_PRT_Type *port;
+ PinName pin;
+ PinDirection dir;
+ PinMode mode;
+};
+
+typedef struct gpio_s gpio_t;
+
+/** Set the output value
+ *
+ * @param obj The GPIO object
+ * @param value The value to be set
+ */
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != NC);
+
+ Cy_GPIO_Write(obj->port, CY_PIN(obj->pin), value);
+}
+
+/** Read the input value
+ *
+ * @param obj The GPIO object
+ * @return An integer value 1 or 0
+ */
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != NC);
+
+ return Cy_GPIO_Read(obj->port, CY_PIN(obj->pin));
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->pin != NC;
+}
+
+/** Get the pin name from the port's pin number
+ *
+ * @param port The port name
+ * @param pin_n The pin number within the specified port
+ * @return The pin name for the port's pin number
+ */
+inline PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName)((port << 8) + pin_n);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_GPIO_OBJECTS_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/i2c_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,548 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "pinmap.h"
+#include "i2c_api.h"
+#include "psoc6_utils.h"
+
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+#include "drivers/peripheral/gpio/cy_gpio.h"
+#include "drivers/peripheral/scb/cy_scb_i2c.h"
+#include "drivers/peripheral/sysint/cy_sysint.h"
+
+#define I2C_DEFAULT_SPEED 100000
+#define NUM_I2C_PORTS 8
+#define I2C_DEFAULT_IRQ_PRIORITY 3
+#define I2C_NUM_DIVIDERS 3
+#define MIN_I2C_CLOCK_FREQUENCY CY_SCB_I2C_SLAVE_STD_CLK_MIN
+// Default timeout in milliseconds.
+#define I2C_DEFAULT_TIMEOUT 1000
+
+#define PENDING_NONE 0
+#define PENDING_RX 1
+#define PENDING_TX 2
+#define PENDING_TX_RX 3
+
+typedef enum {
+ I2C_DIVIDER_LOW = 0,
+ I2C_DIVIDER_MID,
+ I2C_DIVIDER_HIGH,
+ I2C_INVALID_DIVIDER = 0xff
+} I2cDividerType;
+
+
+typedef struct {
+ uint32_t div_num;
+ cy_en_divider_types_t div_type;
+ uint32_t clk_frequency;
+} I2cDividerInfo;
+
+
+static const cy_stc_scb_i2c_config_t default_i2c_config = {
+ .i2cMode = CY_SCB_I2C_MASTER,
+ .useRxFifo = true,
+ .useTxFifo = true,
+ .slaveAddress = 0,
+ .slaveAddressMask = 0,
+ .acceptAddrInFifo = false,
+ .ackGeneralAddr = false,
+ .enableWakeFromSleep = false
+};
+
+
+static I2cDividerInfo i2c_dividers[I2C_NUM_DIVIDERS] = {
+ { I2C_INVALID_DIVIDER, 0, CY_SCB_I2C_SLAVE_STD_CLK_MIN }, // Low divider uses lowest possible frequency.
+ { I2C_INVALID_DIVIDER, 0, CY_SCB_I2C_SLAVE_FST_CLK_MIN },
+ { I2C_INVALID_DIVIDER, 0, CY_SCB_I2C_SLAVE_FSTP_CLK_MIN }
+};
+
+typedef struct i2c_s i2c_obj_t;
+
+#if DEVICE_I2C_ASYNCH
+#define OBJ_P(in) (&(in->i2c))
+#else
+#define OBJ_P(in) (in)
+#endif
+
+
+#if DEVICE_I2C_ASYNCH
+
+static IRQn_Type i2c_irq_allocate_channel(i2c_obj_t *obj)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ obj->cm0p_irq_src = scb_0_interrupt_IRQn + obj->i2c_id;
+ return cy_m0_nvic_allocate_channel(CY_SERIAL_IRQN_ID + obj->i2c_id);
+#else
+ return (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + obj->i2c_id);
+#endif // M0
+}
+
+static void i2c_irq_release_channel(IRQn_Type channel, uint32_t i2c_id)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_m0_nvic_release_channel(channel, CY_SERIAL_IRQN_ID + i2c_id);
+#endif //M0
+}
+
+static int i2c_irq_setup_channel(i2c_obj_t *obj)
+{
+ cy_stc_sysint_t irq_config;
+
+ if (obj->irqn == unconnected_IRQn) {
+ IRQn_Type irqn = i2c_irq_allocate_channel(obj);
+ if (irqn < 0) {
+ return (-1);
+ }
+ // Configure NVIC
+ irq_config.intrPriority = I2C_DEFAULT_IRQ_PRIORITY;
+ irq_config.intrSrc = irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ irq_config.cm0pSrc = obj->cm0p_irq_src;
+#endif
+ if (Cy_SysInt_Init(&irq_config, (cy_israddress)(obj->handler)) != CY_SYSINT_SUCCESS) {
+ return(-1);
+ }
+
+ obj->irqn = irqn;
+ NVIC_EnableIRQ(irqn);
+ }
+ return 0;
+}
+
+#endif // DEVICE_I2C_ASYNCH
+
+static int allocate_divider(I2cDividerType divider)
+{
+ I2cDividerInfo *p_div = &i2c_dividers[divider];
+
+ if (p_div->div_num == CY_INVALID_DIVIDER) {
+ p_div->div_num = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
+ if (p_div->div_num != CY_INVALID_DIVIDER) {
+ p_div->div_type = CY_SYSCLK_DIV_8_BIT;
+ } else {
+ p_div->div_num = cy_clk_allocate_divider(CY_SYSCLK_DIV_16_BIT);
+ if (p_div->div_num != CY_INVALID_DIVIDER) {
+ p_div->div_type = CY_SYSCLK_DIV_16_BIT;
+ }
+ }
+ }
+
+ if (p_div->div_num != CY_INVALID_DIVIDER) {
+ // Set up proper frequency;
+ uint32_t div_value = CY_CLK_PERICLK_FREQ_HZ / p_div->clk_frequency;
+ p_div->clk_frequency = CY_CLK_PERICLK_FREQ_HZ / div_value;
+ if (Cy_SysClk_PeriphSetDivider(p_div->div_type, p_div->div_num, div_value) == CY_SYSCLK_SUCCESS) {
+ Cy_SysClk_PeriphEnableDivider(p_div->div_type, p_div->div_num);
+ } else {
+ p_div->div_num = CY_INVALID_DIVIDER;
+ }
+ }
+
+ return (p_div->div_num == CY_INVALID_DIVIDER)? -1 : 0;
+}
+
+/*
+ * Select one of the 3 dividers used depending on the required frequency.
+ */
+static I2cDividerType select_divider(uint32_t frequency)
+{
+ if (frequency <= (MIN_I2C_CLOCK_FREQUENCY / CY_SCB_I2C_DUTY_CYCLE_MAX)) {
+ // Required speed lower than min supported.
+ return I2C_INVALID_DIVIDER;
+ } else if (frequency <= CY_SCB_I2C_STD_DATA_RATE) {
+ return I2C_DIVIDER_LOW;
+ } else if (frequency <= CY_SCB_I2C_FST_DATA_RATE) {
+ return I2C_DIVIDER_MID;
+ } else if (frequency <= CY_SCB_I2C_FSTP_DATA_RATE) {
+ return I2C_DIVIDER_HIGH;
+ } else {
+ // Required speed too high;
+ return I2C_INVALID_DIVIDER;
+ }
+}
+
+/*
+ * Initializes i2c clock for the required speed
+ */
+static cy_en_sysclk_status_t i2c_init_clock(i2c_obj_t *obj, uint32_t speed)
+{
+ I2cDividerInfo *p_div = NULL;
+ cy_en_sysclk_status_t status = CY_SYSCLK_INVALID_STATE;
+ I2cDividerType divider = select_divider(speed);
+
+ if (divider == I2C_INVALID_DIVIDER) {
+ error("i2c: required speed/frequency is out of valid range.");
+ return CY_SYSCLK_BAD_PARAM;
+ }
+
+ if (allocate_divider(divider) < 0) {
+ error("i2c: cannot allocate clock divider.");
+ return CY_SYSCLK_INVALID_STATE;
+ }
+
+ obj->divider = divider;
+ p_div = &i2c_dividers[divider];
+
+ status = Cy_SysClk_PeriphAssignDivider(obj->clock, p_div->div_type, p_div->div_num);
+ if (status != CY_SYSCLK_SUCCESS) {
+ error("i2c: cannot assign clock divider.");
+ return status;
+ }
+
+ /* Set desired speed/frequency */
+ obj->actual_speed = Cy_SCB_I2C_SetDataRate(obj->base, speed, p_div->clk_frequency);
+ return (obj->actual_speed != 0)? CY_SYSCLK_SUCCESS : CY_SYSCLK_BAD_PARAM;
+}
+
+/*
+ * Initializes i/o pins for i2c sda/scl.
+ */
+static void i2c_init_pins(i2c_obj_t *obj)
+{
+ int sda_function = pinmap_function(obj->pin_sda, PinMap_I2C_SDA);
+ int scl_function = pinmap_function(obj->pin_scl, PinMap_I2C_SCL);
+ pin_function(obj->pin_sda, sda_function);
+ pin_function(obj->pin_scl, scl_function);
+}
+
+
+/*
+ * Initializes and enables I2C/SCB.
+ */
+static void i2c_init_peripheral(i2c_obj_t *obj)
+{
+ cy_stc_scb_i2c_config_t i2c_config = default_i2c_config;
+ I2cDividerInfo *p_div = &i2c_dividers[obj->divider];
+
+ Cy_SCB_I2C_Init(obj->base, &i2c_config, &obj->context);
+ Cy_SCB_I2C_SetDataRate(obj->base,obj->actual_speed, p_div->clk_frequency);
+ Cy_SCB_I2C_Enable(obj->base);
+}
+
+/*
+ * Coverts PDL status into Mbed status.
+ */
+static int i2c_convert_status(cy_en_scb_i2c_status_t status)
+{
+ switch (status) {
+ case CY_SCB_I2C_MASTER_NOT_READY:
+ case CY_SCB_I2C_MASTER_MANUAL_ARB_LOST:
+ case CY_SCB_I2C_MASTER_MANUAL_BUS_ERR:
+ case CY_SCB_I2C_MASTER_MANUAL_ABORT_START:
+ return I2C_ERROR_BUS_BUSY;
+
+ case CY_SCB_I2C_MASTER_MANUAL_TIMEOUT:
+ case CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK:
+ case CY_SCB_I2C_MASTER_MANUAL_NAK:
+ return I2C_ERROR_NO_SLAVE;
+
+ case CY_SCB_I2C_SUCCESS:
+ case CY_SCB_I2C_BAD_PARAM:
+ default:
+ return 0;
+ }
+}
+
+/*
+ * Callback function to handle into and out of deep sleep state transitions.
+ */
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+static cy_en_syspm_status_t i2c_pm_callback(cy_stc_syspm_callback_params_t *callback_params)
+{
+ cy_stc_syspm_callback_params_t params = *callback_params;
+ i2c_obj_t *obj = (i2c_obj_t *)params.context;
+ params.context = &obj->context;
+
+ return Cy_SCB_I2C_DeepSleepCallback(¶ms);
+}
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+
+
+void i2c_init(i2c_t *obj_in, PinName sda, PinName scl)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ uint32_t i2c = pinmap_peripheral(sda, PinMap_I2C_SDA);
+ i2c = pinmap_merge(i2c, pinmap_peripheral(scl, PinMap_I2C_SCL));
+ if (i2c != (uint32_t)NC) {
+ if (cy_reserve_io_pin(sda) || cy_reserve_io_pin(scl)) {
+ error("I2C pin reservation conflict.");
+ }
+ obj->base = (CySCB_Type*)i2c;
+ obj->i2c_id = ((I2CName)i2c - I2C_0) / (I2C_1 - I2C_0);
+ obj->pin_sda = sda;
+ obj->pin_scl = scl;
+ obj->clock = CY_PIN_CLOCK(pinmap_function(scl, PinMap_I2C_SCL));
+ obj->divider = I2C_INVALID_DIVIDER;
+ obj->mode = CY_SCB_I2C_MASTER;
+ obj->timeout = I2C_DEFAULT_TIMEOUT;
+#if DEVICE_I2C_ASYNCH
+ obj->pending = PENDING_NONE;
+ obj->events = 0;
+#endif // DEVICE_I2C_ASYNCH
+ i2c_init_clock(obj, I2C_DEFAULT_SPEED);
+ i2c_init_pins(obj);
+ i2c_init_peripheral(obj);
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ obj->pm_callback_handler.callback = i2c_pm_callback;
+ obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP;
+ obj->pm_callback_handler.skipMode = 0;
+ obj->pm_callback_handler.callbackParams = &obj->pm_callback_params;
+ obj->pm_callback_params.base = obj->base;
+ obj->pm_callback_params.context = obj;
+ if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) {
+ error("PM callback registration failed!");
+ }
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ } else {
+ error("I2C pinout mismatch. Requested pins Rx and Tx can't be used for the same I2C communication.");
+ }
+}
+
+void i2c_frequency(i2c_t *obj_in, int hz)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ Cy_SCB_I2C_Disable(obj->base, &obj->context);
+ i2c_init_clock(obj, hz);
+ Cy_SCB_I2C_Enable(obj->base);
+}
+
+int i2c_start(i2c_t *obj_in)
+{
+ // Unsupported, start condition is sent automatically.
+ return 0;
+}
+
+int i2c_stop(i2c_t *obj_in)
+{
+ // Unsupported, stop condition is sent automatically.
+ return 0;
+}
+
+int i2c_read(i2c_t *obj_in, int address, char *data, int length, int stop)
+{
+ cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS;
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ cy_en_scb_i2c_command_t ack = CY_SCB_I2C_ACK;
+ int byte_count = 0;
+ address >>= 1;
+
+ // Start transaction, send address.
+ if (obj->context.state == CY_SCB_I2C_IDLE) {
+ status = Cy_SCB_I2C_MasterSendStart(obj->base, address, CY_SCB_I2C_READ_XFER, obj->timeout, &obj->context);
+ }
+ if (status == CY_SCB_I2C_SUCCESS) {
+ while (length > 0) {
+ if (length == 1) {
+ ack = CY_SCB_I2C_NAK;
+ }
+ status = Cy_SCB_I2C_MasterReadByte(obj->base, ack, (uint8_t *)data, obj->timeout, &obj->context);
+ if (status != CY_SCB_I2C_SUCCESS) {
+ break;
+ }
+ ++byte_count;
+ --length;
+ ++data;
+ }
+ // SCB in I2C mode is very time sensitive. In practice we have to request STOP after
+ // each block, otherwise it may break the transmission.
+ Cy_SCB_I2C_MasterSendStop(obj->base, obj->timeout, &obj->context);
+ }
+
+ if (status != CY_SCB_I2C_SUCCESS) {
+ Cy_SCB_I2C_MasterSendStop(obj->base, obj->timeout, &obj->context);
+ byte_count = i2c_convert_status(status);
+ }
+
+ return byte_count;
+}
+
+int i2c_write(i2c_t *obj_in, int address, const char *data, int length, int stop)
+{
+ cy_en_scb_i2c_status_t status = CY_SCB_I2C_SUCCESS;
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ int byte_count = 0;
+ address >>= 1;
+
+ // Start transaction, send address.
+ if (obj->context.state == CY_SCB_I2C_IDLE) {
+ status = Cy_SCB_I2C_MasterSendStart(obj->base, address, CY_SCB_I2C_WRITE_XFER, obj->timeout, &obj->context);
+ }
+ if (status == CY_SCB_I2C_SUCCESS) {
+ while (length > 0) {
+ status = Cy_SCB_I2C_MasterWriteByte(obj->base, *data, obj->timeout, &obj->context);
+ if (status != CY_SCB_I2C_SUCCESS) {
+ break;;
+ }
+ ++byte_count;
+ --length;
+ ++data;
+ }
+ // SCB in I2C mode is very time sensitive. In practice we have to request STOP after
+ // each block, otherwise it may break the transmission.
+ Cy_SCB_I2C_MasterSendStop(obj->base, obj->timeout, &obj->context);
+ }
+
+ if (status != CY_SCB_I2C_SUCCESS) {
+ Cy_SCB_I2C_MasterSendStop(obj->base, obj->timeout, &obj->context);
+ byte_count = i2c_convert_status(status);
+ }
+
+ return byte_count;
+}
+
+void i2c_reset(i2c_t *obj_in)
+{
+ i2c_stop(obj_in);
+}
+
+int i2c_byte_read(i2c_t *obj_in, int last)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ uint8_t tmp_byte = 0;
+ cy_en_scb_i2c_command_t ack = last? CY_SCB_I2C_NAK : CY_SCB_I2C_ACK;
+ cy_en_scb_i2c_status_t status = Cy_SCB_I2C_MasterReadByte(obj->base, ack, &tmp_byte, obj->timeout, &obj->context);
+
+ if (status == CY_SCB_I2C_SUCCESS) {
+ return tmp_byte;
+ } else {
+ return 0;
+ }
+}
+
+int i2c_byte_write(i2c_t *obj_in, int data)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ cy_en_scb_i2c_status_t status = Cy_SCB_I2C_MasterWriteByte(obj->base, (uint8_t)data, obj->timeout, &obj->context);
+ switch (status) {
+ case CY_SCB_I2C_MASTER_MANUAL_TIMEOUT:
+ return 2;
+ case CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK:
+ case CY_SCB_I2C_MASTER_MANUAL_NAK:
+ return 0;
+ case CY_SCB_I2C_SUCCESS:
+ return 1;
+ default:
+ // Error has occurred.
+ return (-1);
+ }
+}
+
+#if DEVICE_I2C_ASYNCH
+
+void i2c_transfer_asynch(i2c_t *obj_in,
+ const void *tx,
+ size_t tx_length,
+ void *rx, size_t rx_length,
+ uint32_t address,
+ uint32_t stop,
+ uint32_t handler,
+ uint32_t event,
+ DMAUsage hint)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+
+ (void)hint; // At the moment we do not support DMA transfers, so this parameter gets ignored.
+
+ if (obj->pending != PENDING_NONE) {
+ return;
+ }
+
+ obj->rx_config.slaveAddress = address >> 1;
+ obj->tx_config.slaveAddress = address >> 1;
+ obj->events = event;
+ obj->handler = handler;
+ if (i2c_irq_setup_channel(obj) < 0) {
+ return;
+ }
+
+ obj->rx_config.buffer = rx;
+ obj->rx_config.bufferSize = rx_length;
+ obj->rx_config.xferPending = !stop;
+
+ obj->tx_config.buffer = (void*)tx;
+ obj->tx_config.bufferSize = tx_length;
+ obj->tx_config.xferPending = rx_length || !stop;
+
+ if (tx_length) {
+ // Write first, then read, or write only.
+ if (rx_length > 0) {
+ obj->pending = PENDING_TX_RX;
+ } else {
+ obj->pending = PENDING_TX;
+ }
+ Cy_SCB_I2C_MasterWrite(obj->base, &obj->tx_config, &obj->context);
+ } else if (rx_length) {
+ // Read transaction;
+ obj->pending = PENDING_RX;
+ Cy_SCB_I2C_MasterRead(obj->base, &obj->rx_config, &obj->context);
+ }
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj_in)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ uint32_t event = 0;
+ // Process actual interrupt.
+ Cy_SCB_I2C_Interrupt(obj->base, &obj->context);
+ if (obj->context.state == CY_SCB_I2C_MASTER_CMPLT) {
+ if (obj->context.masterStatus & CY_SCB_I2C_MASTER_ERR) {
+ if (obj->context.masterStatus & CY_SCB_I2C_MASTER_ADDR_NAK) {
+ event = I2C_EVENT_ERROR_NO_SLAVE;
+ } else if (obj->context.masterStatus & CY_SCB_I2C_MASTER_DATA_NAK) {
+ event = I2C_EVENT_TRANSFER_EARLY_NACK;
+ } else {
+ event = I2C_EVENT_ERROR;
+ }
+ } else {
+ // Check if a read phase is pending after write.
+ if (obj->pending == PENDING_TX_RX) {
+ obj->pending = PENDING_RX;
+ Cy_SCB_I2C_MasterRead(obj->base, &obj->rx_config, &obj->context);
+ } else {
+ event = I2C_EVENT_TRANSFER_COMPLETE;
+ }
+ }
+ }
+ if (event) {
+ obj->pending = PENDING_NONE;
+ }
+ return event & obj->events;
+}
+
+uint8_t i2c_active(i2c_t *obj_in)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ return (obj->pending != PENDING_NONE);
+}
+
+void i2c_abort_asynch(i2c_t *obj_in)
+{
+ i2c_obj_t *obj = OBJ_P(obj_in);
+ if (obj->pending != PENDING_NONE) {
+ if (obj->pending == PENDING_RX) {
+ Cy_SCB_I2C_MasterAbortRead(obj->base, &obj->context);
+ } else {
+ Cy_SCB_I2C_MasterAbortWrite(obj->base, &obj->context);
+ }
+ }
+}
+
+#endif // DEVICE_ASYNCH
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/ipcpipe_transport.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,191 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ipcpipe_transport.h"
+#include "cy_ipc_config.h"
+#include "ipc/cy_ipc_pipe.h"
+//#include "syspm/cy_syspm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static IpcPipeBuffer ipcpipe_buffer[2];
+
+volatile uint32_t ipcpipe_current_buffer = 0;
+volatile uint32_t ipcpipe_transfer_buffer = 0;
+
+static uint32_t num_registered_clients = 0;
+
+IpcPipeTxCompleteHandler *ipcpipe_xfer_complete_cb[CY_IPC_USRPIPE_CLIENT_CNT] = {NULL};
+
+
+/** Buffer release callback function
+ * Just releases currently transmitted buffer upon tx completion.
+ * Used in the case the currently transmitted buffer was not the last one
+ * in the queue, i.e. event doesn't complete the whole transmission.
+ */
+void ipcpipe_buffer_release(void)
+{
+ IPCPIPE_ASSERT(ipcpipe_buffer[ipcpipe_transfer_buffer].busy_flag == 1);
+ ipcpipe_buffer[ipcpipe_transfer_buffer].busy_flag = 0;
+}
+
+/** Buffer release callback function
+ * Releases currently transmitted buffer upon tx completion
+ * and calls associated tx complete event handler.
+ */
+void ipcpipe_buffer_release_callback(void)
+{
+ uint32_t client_id = ipcpipe_buffer[ipcpipe_transfer_buffer].message.client_id;
+ IpcPipeTxCompleteHandler *handler = ipcpipe_xfer_complete_cb[client_id];
+
+ IPCPIPE_ASSERT(client_id < CY_IPC_USRPIPE_CLIENT_CNT);
+ IPCPIPE_ASSERT(ipcpipe_buffer[ipcpipe_transfer_buffer].busy_flag == 1);
+ ipcpipe_buffer[ipcpipe_transfer_buffer].busy_flag = 0;
+
+ /* call back transfer complete function */
+ if (handler) {
+ (*handler)();
+ }
+}
+
+/** Locks a buffer making it available for transmission.
+ *
+ * @param current_buffer index of the buffer to be locked
+ */
+void ipcpipe_transfer_lock_buffer(uint32_t current_buffer)
+{
+ IPCPIPE_ASSERT(current_buffer < 2);
+ IPCPIPE_ASSERT(ipcpipe_buffer[current_buffer].busy_flag == 0);
+ /* make sure previous transfer has ended */
+ while (ipcpipe_buffer[ipcpipe_transfer_buffer].busy_flag) {
+ /* busy wait */
+ }
+
+ ipcpipe_buffer[current_buffer].busy_flag = 1;
+ ipcpipe_transfer_buffer = current_buffer;
+}
+
+/** Find index of the next available buffer
+ * This is a blocking call, it blocks until the buffer becomes available
+ * if there is no free buffer at the moment.
+ *
+ * @return index of the buffer
+ */
+uint32_t ipcpipe_buffer_aquire(void)
+{
+ uint32_t buffer_index;
+ /* check that we have a buffer available */
+ while (ipcpipe_buffer[ipcpipe_current_buffer].busy_flag) {
+ /* just wait here */
+ }
+
+ buffer_index = ipcpipe_current_buffer;
+ ipcpipe_current_buffer = ipcpipe_current_buffer ? 0 : 1;
+ return buffer_index;
+}
+
+/** Write header and data over IPC pipe.
+ */
+void ipcpipe_write_data(uint32_t client_id, uint8_t *header, uint32_t header_length, uint8_t *data, uint32_t data_length)
+{
+ uint32_t sent_idx = 0;
+ cy_en_ipc_pipe_status_t status;
+ int avail = 0;
+
+ IPCPIPE_ASSERT(client_id < CY_IPC_USRPIPE_CLIENT_CNT);
+
+ while ((sent_idx < data_length) || (header_length > 0)) {
+ uint32_t buffer_id = ipcpipe_buffer_aquire();
+ IpcPipeBuffer *buffer = &ipcpipe_buffer[buffer_id];
+ uint32_t data_idx = 0;
+
+ /* copy over the header */
+ buffer->message.header_length = header_length;
+ while (header_length > 0) {
+ buffer->message.header[data_idx++] = *header++;
+ --header_length;
+ }
+ /* copy over the data */
+ data_idx = 0;
+ while ((sent_idx < data_length) && (data_idx < IPCPIPE_MAX_DATA_LENGTH)) {
+ buffer->message.data[data_idx++] = data[sent_idx++];
+ }
+ buffer->message.data_length = data_idx;
+ buffer->message.client_id = client_id;
+ /* put into the pipe */
+ ipcpipe_transfer_lock_buffer(buffer_id);
+ do {
+ avail = ipcpipe_buffer[ipcpipe_current_buffer].busy_flag == 0;
+
+ status = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_USRPIPE_DEST, /* destination EP */
+ CY_IPC_EP_USRPIPE_ADDR, /* source EP */
+ &buffer->message,
+ avail? ipcpipe_buffer_release : ipcpipe_buffer_release_callback);
+ if (status == CY_IPC_PIPE_ERROR_SEND_BUSY) {
+ /* busy wait */
+ }
+ } while (status != CY_IPC_PIPE_SUCCESS);
+ }
+
+ /* execute transfer complete callback as appropriate */
+ if (avail && ipcpipe_xfer_complete_cb[client_id]) {
+ (*ipcpipe_xfer_complete_cb[client_id])();
+ }
+}
+
+void ipcpipe_transport_start(uint32_t client_id, IpcPipeRxHandler *rx_handler, IpcPipeTxCompleteHandler *tx_handler)
+{
+ IPCPIPE_ASSERT(client_id < CY_IPC_USRPIPE_CLIENT_CNT);
+
+ /* register/initialize required callbacks */
+ Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_USRPIPE_ADDR, rx_handler, client_id);
+ Cy_IPC_Pipe_RegisterCallbackRel(CY_IPC_EP_USRPIPE_ADDR, ipcpipe_buffer_release);
+ ipcpipe_xfer_complete_cb[client_id] = tx_handler;
+ if (++num_registered_clients == 1) {
+ ipcpipe_transport_enable();
+ }
+}
+
+void ipcpipe_transport_stop(uint32_t client_id)
+{
+ Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_USRPIPE_ADDR, NULL, client_id);
+ Cy_IPC_Pipe_RegisterCallbackRel(CY_IPC_EP_USRPIPE_ADDR, NULL);
+ ipcpipe_xfer_complete_cb[client_id] = NULL;
+ if (--num_registered_clients == 0) {
+ ipcpipe_transport_disable();
+ }
+}
+
+void ipcpipe_transport_enable(void)
+{
+ Cy_IPC_Pipe_EndpointResume(CY_IPC_EP_USRPIPE_ADDR);
+}
+
+
+void ipcpipe_transport_disable(void)
+{
+ Cy_IPC_Pipe_EndpointPause(CY_IPC_EP_USRPIPE_ADDR);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/ipcpipe_transport.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,109 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IPCPIPE_TRANSPORT_H
+#define IPCPIPE_TRANSPORT_H
+
+#include <stdint.h>
+
+#if defined(__MBED__)
+#define IPCPIPE_ASSERT MBED_ASSERT
+#include "mbed_assert.h"
+#else
+#include "project.h"
+#define IPCPIPE_ASSERT CY_ASSERT
+#endif
+
+
+#define IPCPIPE_MAX_DATA_LENGTH 256
+#define IPCPIPE_MAX_HEADER_LENGTH 4
+
+/* Client IDs */
+#define IPCPIPE_CLIENT_H4 0
+
+/** IPC Pipe message data structure
+ */
+typedef struct {
+ uint32_t client_id; ///< ID of the client using this API
+ uint32_t header_length; ///< length of the message header in bytes
+ uint32_t data_length; ///< length of the message data field
+ uint8_t header[IPCPIPE_MAX_HEADER_LENGTH]; ///< message header
+ uint8_t data[IPCPIPE_MAX_DATA_LENGTH]; ///< message data
+} IpcPipeMessage;
+
+
+/** IPC Pipe message buffer
+ * Used to transfer a message to other MCU
+ */
+typedef struct {
+ volatile uint8_t busy_flag; ///< indicates whether the transfer is in progress
+ IpcPipeMessage message; ///< the message itself
+} IpcPipeBuffer;
+
+/** Type of rx (buffer received) event handler function
+ */
+typedef void (IpcPipeRxHandler)(uint32_t *message_ptr);
+
+/** Type of tx complete (buffer sent out) event handler function
+ */
+typedef void (IpcPipeTxCompleteHandler)(void);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send a data block over IPC pipe
+ *
+ * @param client_id ID of the client using this service
+ * @param header pointer to the message header to be sent
+ * @param header_length length of the header
+ * @param data pointer to the message data to be sent
+ * @param data_length length of the data
+ */
+void ipcpipe_write_data(uint32_t client_id, uint8_t* header, uint32_t header_length, uint8_t *data, uint32_t data_length);
+
+/** Initialize and start IPC pipe transport service
+ *
+ * @param client_id ID of the client using this service
+ * @param rx_handler receive event handler
+ * @param tx_handler transmit complete event handler
+ */
+void ipcpipe_transport_start(uint32_t client_id, IpcPipeRxHandler *rx_handler, IpcPipeTxCompleteHandler *tx_handler);
+
+/** Stop IPC pipe transport service
+ *
+ * @param client_id ID of the client using this service
+ */
+void ipcpipe_transport_stop(uint32_t client_id);
+
+
+/** Enable IPC pipe transport service
+ */
+void ipcpipe_transport_enable(void);
+
+/** Disable IPC pipe transport service
+ */
+void ipcpipe_transport_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* IPCPIPE_H4_TRANSPORT_H */
+
+/* [] END OF FILE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,162 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+#include "device.h"
+#include "mbed_error.h"
+#include "lp_ticker_api.h"
+#include "device/drivers/peripheral/mcwdt/cy_mcwdt.h"
+#include "device/drivers/peripheral/sysint/cy_sysint.h"
+#include "psoc6_utils.h"
+
+#if DEVICE_LPTICKER
+
+/*
+ * Low Power Timer API on PSoC6 uses MCWD0 timer0 to implement functionality.
+ */
+
+#if defined(TARGET_MCU_PSOC6_M0)
+#define LPT_MCWDT_UNIT MCWDT_STRUCT0
+#define LPT_INTERRUPT_PRIORITY 3
+#define LPT_INTERRUPT_SOURCE srss_interrupt_mcwdt_0_IRQn
+#else
+#define LPT_MCWDT_UNIT MCWDT_STRUCT1
+#define LPT_INTERRUPT_PRIORITY 6
+#define LPT_INTERRUPT_SOURCE srss_interrupt_mcwdt_1_IRQn
+#endif
+#define LPT_MCWDT_DELAY_WAIT 0 // Recommended value is 93, but then we fail function execution time test.
+
+static const ticker_info_t lp_ticker_info = {
+ .frequency = CY_CLK_WCO_FREQ_HZ,
+ .bits = 16,
+};
+
+static bool lpt_init_done = false;
+// Timer h/w configuration.
+static cy_stc_mcwdt_config_t config = {
+ .c0Match = 0,
+ .c1Match = 0,
+ .c0Mode = CY_MCWDT_MODE_INT,
+ .c1Mode = CY_MCWDT_MODE_NONE,
+ .c2ToggleBit = 0,
+ .c2Mode = CY_MCWDT_MODE_NONE,
+ .c0ClearOnMatch = false,
+ .c1ClearOnMatch = false,
+ .c0c1Cascade = false,
+ .c1c2Cascade = false
+};
+
+// Interrupt configuration.
+static cy_stc_sysint_t lpt_sysint_config = {
+#if defined(TARGET_MCU_PSOC6_M0)
+ .intrSrc = (IRQn_Type)(-1),
+ .cm0pSrc = LPT_INTERRUPT_SOURCE,
+#else
+ .intrSrc = LPT_INTERRUPT_SOURCE,
+#endif
+ .intrPriority = LPT_INTERRUPT_PRIORITY
+};
+
+
+void lp_ticker_init(void)
+{
+ lp_ticker_disable_interrupt();
+ lp_ticker_clear_interrupt();
+
+ if (lpt_init_done) {
+ return;
+ }
+
+#ifdef TARGET_MCU_PSOC6_M0
+ // Allocate NVIC channel.
+ lpt_sysint_config.intrSrc = cy_m0_nvic_allocate_channel(CY_LP_TICKER_IRQN_ID);
+ if (lpt_sysint_config.intrSrc == (IRQn_Type)(-1)) {
+ // No free NVIC channel.
+ error("LP_TICKER NVIC channel allocation failed.");
+ return;
+ }
+#endif
+
+ Cy_MCWDT_Init(LPT_MCWDT_UNIT, &config);
+ Cy_SysInt_Init(&lpt_sysint_config, lp_ticker_irq_handler);
+ NVIC_EnableIRQ(lpt_sysint_config.intrSrc);
+ Cy_MCWDT_Enable(LPT_MCWDT_UNIT, CY_MCWDT_CTR0, LPT_MCWDT_DELAY_WAIT);
+ lpt_init_done = true;
+}
+
+void lp_ticker_free(void)
+{
+ NVIC_DisableIRQ(lpt_sysint_config.intrSrc);
+ Cy_MCWDT_Disable(LPT_MCWDT_UNIT, CY_MCWDT_CTR0, LPT_MCWDT_DELAY_WAIT);
+#ifdef TARGET_MCU_PSOC6_M0
+ cy_m0_nvic_release_channel(CY_LP_TICKER_IRQN_ID, lpt_sysint_config.intrSrc);
+ lpt_sysint_config.intrSrc = (IRQn_Type)(-1);
+#endif
+ lpt_init_done = 0;
+}
+
+uint32_t lp_ticker_read(void)
+{
+ return Cy_MCWDT_GetCount(LPT_MCWDT_UNIT, CY_MCWDT_COUNTER0);
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint16_t delay;
+ uint16_t current = Cy_MCWDT_GetCount(LPT_MCWDT_UNIT, CY_MCWDT_COUNTER0);
+ uint16_t new_ts = (uint16_t)timestamp;
+ delay = new_ts - current;
+ // Make sure the event is set for the future. Mbed internally will not schedule
+ // delays longer than 0x7000, so too large delay means it should occur already.
+ // MCWDT has internal delay of about 1.5 LF clock ticks, so this is the minimum
+ // that we can schedule.
+ if ((delay < 3) || (delay > (uint16_t)(-3))) {
+ // Cheating a bit here.
+ new_ts = current + 3;
+ }
+
+ // Cypress PDL manual says that valid match range is 1..65535.
+ if (new_ts == 0) {
+ new_ts = 1;
+ }
+
+ // Set up and enable match interrupt.
+ Cy_MCWDT_SetMatch(LPT_MCWDT_UNIT, CY_MCWDT_COUNTER0, new_ts, LPT_MCWDT_DELAY_WAIT);
+ Cy_MCWDT_SetInterruptMask(LPT_MCWDT_UNIT, CY_MCWDT_CTR0);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ Cy_MCWDT_SetInterruptMask(LPT_MCWDT_UNIT, 0);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ Cy_MCWDT_ClearInterrupt(LPT_MCWDT_UNIT, CY_MCWDT_CTR0);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(lpt_sysint_config.intrSrc);
+}
+
+const ticker_info_t* lp_ticker_get_info(void)
+{
+ return &lp_ticker_info;
+}
+
+#endif // DEVICE_LPTICKER
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,40 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2016 u-blox + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_MCU_PSOC6_M0) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x08000000 + 0x00010000) // Ram origin + length +#endif + +#elif defined(TARGET_MCU_PSOC6_M4) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x08010000 + 0x00037800) // Ram origin + length +#endif + +#else + +#error "Unknown board" + +#endif + +#endif // MBED_MBED_RTX_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,227 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "PortNames.h"
+
+#include "gpio_irq_api.h"
+#include "gpio_object.h"
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+#include "drivers/peripheral/syspm/cy_syspm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_INTERRUPTIN
+struct gpio_irq_s {
+ GPIO_PRT_Type* port;
+ uint32_t port_id;
+ uint32_t pin;
+ gpio_irq_event mode;
+ gpio_irq_handler handler;
+ uint32_t id_arg;
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_en_intr_t cm0p_irq_src;
+#endif
+};
+#endif // DEVICE_INTERRUPTIN
+
+struct port_s {
+ GPIO_PRT_Type *port;
+
+ uint32_t port_id;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
+// __IO uint32_t *reg_in;
+// __IO uint32_t *reg_out;
+};
+
+// struct analogin_s {
+// ADCName adc;
+// PinName pin;
+// uint32_t channel;
+// };
+
+#if DEVICE_SERIAL
+#include "cy_scb_uart.h"
+
+struct serial_s {
+ CySCB_Type *base;
+ uint32_t serial_id;
+ PinName pin_rx;
+ PinName pin_tx;
+ PinName pin_cts;
+ PinName pin_rts;
+ en_clk_dst_t clock;
+ cy_en_divider_types_t div_type;
+ uint8_t div_num;
+ uint8_t data_width;
+ cy_en_scb_uart_stop_bits_t stop_bits;
+ cy_en_scb_uart_parity_t parity;
+#if DEVICE_SERIAL_ASYNCH
+ uint32_t rx_events;
+ bool rx_pending;
+ uint32_t tx_events;
+ bool tx_pending;
+ cy_israddress async_handler;
+#endif // DEVICE_SERIAL_ASYNCH
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ cy_stc_syspm_callback_params_t pm_callback_params;
+ cy_stc_syspm_callback_t pm_callback_handler;
+#endif
+};
+#endif // DEVICE_SERIAL
+
+#if DEVICE_SPI
+#include "cy_scb_spi.h"
+
+struct spi_s {
+ CySCB_Type *base;
+ uint32_t spi_id;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+ en_clk_dst_t clock;
+ uint32_t div_num;
+ cy_en_divider_types_t div_type;
+ uint32_t clk_frequency;
+ cy_en_scb_spi_mode_t ms_mode;
+ cy_en_scb_spi_sclk_mode_t clk_mode;
+ uint8_t data_bits;
+ cy_stc_scb_spi_context_t context;
+#if DEVICE_SPI_ASYNCH
+ IRQn_Type irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_en_intr_t cm0p_irq_src;
+#endif
+ uint16_t pending;
+ uint16_t events;
+ uint32_t handler;
+ void *rx_buffer;
+ uint32_t rx_buffer_size;
+ void *tx_buffer;
+ uint32_t tx_buffer_size;
+#endif // DEVICE_SPI_ASYNCH
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ cy_stc_syspm_callback_params_t pm_callback_params;
+ cy_stc_syspm_callback_t pm_callback_handler;
+#endif
+};
+#endif // DEVICE_SPI
+
+#if DEVICE_I2C
+#include "cy_scb_i2c.h"
+
+struct i2c_s {
+ CySCB_Type *base;
+ uint32_t i2c_id;
+ PinName pin_sda;
+ PinName pin_scl;
+ en_clk_dst_t clock;
+ uint32_t divider;
+ uint32_t actual_speed;
+ cy_en_scb_i2c_mode_t mode;
+ uint32_t timeout;
+#if DEVICE_I2C_SLAVE
+ uint16_t ADDRESS;
+ uint16_t is_setAddress;
+#endif
+ cy_stc_scb_i2c_context_t context;
+#if DEVICE_I2C_ASYNCH
+ cy_stc_scb_i2c_master_xfer_config_t rx_config;
+ cy_stc_scb_i2c_master_xfer_config_t tx_config;
+ IRQn_Type irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_en_intr_t cm0p_irq_src;
+#endif
+ uint16_t pending;
+ uint16_t events;
+ uint32_t handler;
+#endif // DEVICE_I2C_ASYNCH
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ cy_stc_syspm_callback_params_t pm_callback_params;
+ cy_stc_syspm_callback_t pm_callback_handler;
+#endif
+};
+#endif // DEVICE_I2C
+
+#if DEVICE_PWMOUT
+#include "cy_tcpwm.h"
+
+struct pwmout_s {
+ TCPWM_Type *base;
+ PinName pin;
+ uint32_t counter_id;
+ uint32_t clock;
+ uint32_t period;
+ uint32_t pulse_width;
+ uint32_t prescaler;
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ cy_stc_syspm_callback_params_t pm_callback_params;
+ cy_stc_syspm_callback_t pm_callback_handler;
+#endif
+};
+#endif // DEVICE_PWMOUT
+
+#ifdef DEVICE_ANALOGIN
+#include "cy_sar.h"
+
+struct analogin_s {
+ SAR_Type *base;
+ PinName pin;
+ uint32_t channel_mask;
+ uint32_t clock;
+};
+#endif // DEVICE_ANALOGIN
+
+#ifdef DEVICE_ANALOGOUT
+#include "cy_ctdac.h"
+
+struct dac_s {
+ CTDAC_Type *base;
+ PinName pin;
+ uint32_t clock;
+};
+#endif // DEVICE_ANALOGOUT
+
+#ifdef DEVICE_FLASH
+struct flash_s {
+ /* nothing to be stored for now */
+ void *dummy;
+};
+#endif // DEVICE_FLASH
+
+#if DEVICE_TRNG
+struct trng_s {
+ /* nothing to be stored for now */
+ void *dummy;
+};
+#endif // DEVICE_TRNG
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,67 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "cy_gpio.h"
+#include "psoc6_utils.h"
+
+void pin_function(PinName pin, int function)
+{
+ if (pin != NC) {
+ GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CY_PORT(pin));
+ uint32_t mode = gpio_get_cy_drive_mode(CY_PIN_DIRECTION(function), CY_PIN_MODE(function));
+
+ Cy_GPIO_Pin_FastInit(port, CY_PIN(pin), mode, 1, CY_PIN_HSIOM(function));
+ // Force output to enable pulls.
+ switch (mode) {
+ case CY_GPIO_DM_PULLUP:
+ Cy_GPIO_Write(port, CY_PIN(pin), 1);
+ break;
+ case CY_GPIO_DM_PULLDOWN:
+ Cy_GPIO_Write(port, CY_PIN(pin), 0);
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+ if (pin != NC) {
+ uint32_t cymode = gpio_get_cy_drive_mode(PIN_INPUT, mode);
+ GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CY_PORT(pin));
+
+ Cy_GPIO_SetDrivemode(port, CY_PIN(pin), cymode);
+
+ // Force output to enable pulls.
+ switch (cymode) {
+ case CY_GPIO_DM_PULLUP:
+ Cy_GPIO_Write(port, CY_PIN(pin), 1);
+ break;
+ case CY_GPIO_DM_PULLDOWN:
+ Cy_GPIO_Write(port, CY_PIN(pin), 0);
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/port_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,117 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "device.h"
+#include "mbed_assert.h"
+#include "gpio_object.h"
+#include "port_api.h"
+#include "psoc6_utils.h"
+#include "mbed_error.h"
+
+static void port_init_pins(port_t *obj)
+{
+ uint32_t pin;
+ uint32_t cy_mode;
+
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->port);
+
+ cy_mode = gpio_get_cy_drive_mode(obj->direction, obj->mode);
+ for (pin = 0; pin < 8; ++pin) {
+ if (obj->mask & (1 << pin)) {
+ Cy_GPIO_Pin_FastInit(obj->port, pin, cy_mode, 0, HSIOM_SEL_GPIO);
+ }
+ }
+
+ // Force output to enable pulls.
+ if (obj->direction == PIN_INPUT) {
+ switch (cy_mode) {
+ case CY_GPIO_DM_PULLUP:
+ port_write(obj, 0xff);
+ break; // Force output to enable pulls.
+
+ case CY_GPIO_DM_PULLDOWN:
+ port_write(obj, 0);
+ break;
+ }
+ }
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ uint32_t pin;
+
+ MBED_ASSERT(obj);
+
+ for (pin = 0; pin < 8; ++pin) {
+ if (mask & (1 << pin)) {
+ if (cy_reserve_io_pin((PinName)((port << 8)+pin))) {
+ error("Port pin reservation conflict.");
+ }
+ }
+ }
+ obj->port_id = port;
+ obj->port = Cy_GPIO_PortToAddr(port);
+ obj->mask = mask & 0xff; // Only 8 bits exist on a port in PSoC.
+ obj->direction = dir;
+ obj->mode = PullDefault;
+ port_init_pins(obj);
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->port);
+
+ obj->mode = mode;
+ port_init_pins(obj);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->port);
+
+ obj->direction = dir;
+ port_init_pins(obj);
+}
+
+void port_write(port_t *obj, int value)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(obj->port);
+
+ if (obj->mask == 0xff) {
+ obj->port->OUT = value;
+ } else {
+ // In case some bits are used for different functionality we need to write
+ // each bit separately to not break things out, eg. pull up state on other bits.
+ uint32_t pin;
+ for (pin = 0; pin < 8; ++pin) {
+ if (obj->mask & (1 << pin)) {
+ Cy_GPIO_Write(obj->port, pin, value & 0x1);
+ value >>= 1;
+ }
+ }
+ }
+}
+
+int port_read(port_t *obj)
+{
+ return obj->port->IN & obj->mask;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,456 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "psoc6_utils.h"
+
+#if defined(__MBED__)
+
+#include "mbed_critical.h"
+#include "mbed_error.h"
+
+#else
+
+/** Adaptation layer to native Cypress environment */
+/* Notice, that since we use critical section here only for operations
+ * that do not involve function calls, we can get away with using
+ * a global static variable for interrupt status saving.
+ */
+
+#include "syslib/cy_syslib.h"
+
+#define error(arg) CY_ASSERT(0)
+#define MBED_ASSERT CY_ASSERT
+
+#define core_util_critical_section_enter() \
+ uint32_t _last_irq_status_ = Cy_SysLib_EnterCriticalSection()
+
+#define core_util_critical_section_exit() \
+ Cy_SysLib_ExitCriticalSection(_last_irq_status_)
+
+#endif /* defined(__MBED__) */
+
+
+#define CY_NUM_PSOC6_PORTS 14
+#define CY_NUM_DIVIDER_TYPES 4
+#define NUM_SCB 8
+#define NUM_TCPWM 32
+
+
+#if defined(TARGET_MCU_PSOC6_M0) || PSOC6_DYNSRM_DISABLE || !defined(__MBED__)
+
+/****************************************************************************/
+/* Dynamic Shared Resource Manager */
+/****************************************************************************/
+/*
+ * This part of the code is responsible for management of the hardware
+ * resource shared between both CPUs of the PSoC 6.
+ * It supports allocation, freeing and conflict detection, so that never
+ * both CPUs try to use a single resource.
+ * It also detects conflicts arising from allocation of hardware devices
+ * for different modes of operation and when user tries to assign multiple
+ * functions to the same chip pin.
+ * It supports two modes of operation:
+ * 1. DYNAMIC (default mode)
+ * Resource manager is run on M0 core and M4 core asks it to allocate
+ * or free resources using RPC over IPC mechanism.
+ * M0 core communicates with manager via local function calls.
+ * 2. STATIC (enabled with PSOC6_DYNSRM_DISABLE compilation flag)
+ * In this mode resources are split statically between both cores.
+ * Targets using this mode should add psoc6_static_srm.h file to
+ * each core folder with declarations of resources assigned to it.
+ * See example file for details.
+ */
+
+
+#if PSOC6_DYNSRM_DISABLE
+
+#define SRM_INIT_RESOURCE(_type_, _res_, _field_, ...) \
+do { \
+ struct _init_s_ { \
+ uint8_t idx; \
+ _type_ val; \
+ } init[] = {{0, 0}, __VA_ARGS__}; \
+ uint32_t i; \
+ for (i = 1; i < sizeof(init)/sizeof(struct _init_s_); ++i) \
+ _res_[init[i].idx]_field_ = init[i].val; \
+} while(0)
+
+#if defined(TARGET_MCU_PSOC6_M0)
+/*
+ * On M0 we start with all resources assigned to M4 and then clear reservations
+ * for those assigned to it (M0).
+ */
+#define SRM_PORT(port, pins) {(port), (uint8_t)~(pins)}
+#define SRM_DIVIDER(type, dividers) {(type), (uint16_t)~(dividers)}
+#define SRM_SCB(num) {(num), (0)}
+#define SRM_TCPWM(num) {(num), (0)}
+
+#define DEFAULT_PORT_RES 0xff
+#define DEFAULT_DIVIDER_RES 0xffff
+#define DEFAULT_SCM_RES 1
+#define DEFAULT_TCPWM_RES 1
+
+#else // defined(TARGET_MCU_PSOC6_M0)
+
+#define SRM_PORT(port, pins) {(port), (pins)}
+#define SRM_DIVIDER(type, dividers) {(type), (dividers)}
+#define SRM_SCB(num) {(num), (1)}
+#define SRM_TCPWM(num) {(num), (1)}
+
+#define DEFAULT_PORT_RES 0
+#define DEFAULT_DIVIDER_RES 0
+#define DEFAULT_DIVIDER8_RES 0
+#define DEFAULT_SCM_RES 0
+#define DEFAULT_TCPWM_RES 0
+#endif // defined(TARGET_MCU_PSOC6_M0)
+
+#include "psoc6_static_srm.h"
+
+#else // PSOC6_DYNSRM_DISABLE
+
+#define DEFAULT_PORT_RES 0
+#define DEFAULT_DIVIDER_RES 0
+#define DEFAULT_DIVIDER8_RES 0x3 // dividers 0 & 1 are reserved for us_ticker
+#define DEFAULT_SCM_RES 0
+#define DEFAULT_TCPWM_RES 0x3 // 32b counters 0 & 1 are reserved for us_ticker
+
+#endif // PSOC6_DYNSRM_DISABLE
+
+static uint8_t port_reservations[CY_NUM_PSOC6_PORTS] = {DEFAULT_PORT_RES};
+
+typedef struct {
+ const uint32_t max_index;
+ uint32_t current_index;
+ uint32_t reservations;
+} divider_alloc_t;
+
+static divider_alloc_t divider_allocations[CY_NUM_DIVIDER_TYPES] = {
+ { PERI_DIV_8_NR - 1, 2, DEFAULT_DIVIDER8_RES }, // CY_SYSCLK_DIV_8_BIT
+ { PERI_DIV_16_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_BIT
+ { PERI_DIV_16_5_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_5_BIT
+ { PERI_DIV_24_5_NR - 1, 0, DEFAULT_DIVIDER_RES } // CY_SYSCLK_DIV_24_5_BIT
+};
+
+static uint8_t scb_reservations[NUM_SCB] = {DEFAULT_SCM_RES};
+
+static uint8_t tcpwm_reservations[NUM_TCPWM] = {DEFAULT_TCPWM_RES};
+
+
+int cy_reserve_io_pin(PinName pin_name)
+{
+ uint32_t port = CY_PORT(pin_name);
+ uint32_t pin = CY_PIN(pin_name);
+ int result = (-1);
+
+ if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
+ core_util_critical_section_enter();
+ if (!(port_reservations[port] & (1 << pin))) {
+ port_reservations[port] |= (1 << pin);
+ result = 0;
+ }
+ core_util_critical_section_exit();
+ } else {
+ error("Trying to reserve non existing port/pin!");
+ }
+ return result;
+}
+
+
+void cy_free_io_pin(PinName pin_name)
+{
+ uint32_t port = CY_PORT(pin_name);
+ uint32_t pin = CY_PIN(pin_name);
+ int result = (-1);
+
+ if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
+ core_util_critical_section_enter();
+ if (port_reservations[port] & (1 << pin)) {
+ port_reservations[port] &= ~(1 << pin);
+ result = 0;
+ }
+ core_util_critical_section_exit();
+ }
+
+ if (result) {
+ error("Trying to free wrong port/pin.");
+ }
+}
+
+
+uint32_t cy_clk_reserve_divider(cy_en_divider_types_t div_type, uint32_t div_num)
+{
+ uint32_t divider = CY_INVALID_DIVIDER;
+ divider_alloc_t *p_alloc = ÷r_allocations[div_type];
+
+ MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
+ MBED_ASSERT(div_num <= p_alloc->max_index);
+
+ core_util_critical_section_enter();
+
+ if ((p_alloc->reservations & (1 << div_num)) == 0) {
+ p_alloc->reservations |= (1 << div_num);
+ divider = div_num;
+ p_alloc->current_index = ++div_num;
+ if (p_alloc->current_index > p_alloc->max_index) {
+ p_alloc->current_index = 0;
+ }
+ }
+
+ core_util_critical_section_exit();
+
+ return divider;
+}
+
+
+void cy_clk_free_divider(cy_en_divider_types_t div_type, uint32_t div_num)
+{
+ int result = (-1);
+ divider_alloc_t *p_alloc = ÷r_allocations[div_type];
+
+ MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
+ MBED_ASSERT(div_num <= p_alloc->max_index);
+
+ core_util_critical_section_enter();
+
+ if ((p_alloc->reservations & (1 << div_num)) != 0) {
+ p_alloc->reservations &= ~(1 << div_num);
+ result = 0;
+ }
+
+ core_util_critical_section_exit();
+
+ if (result) {
+ error("Trying to release wrong clock divider.");
+ }
+}
+
+
+uint32_t cy_clk_allocate_divider(cy_en_divider_types_t div_type)
+{
+ uint32_t divider = CY_INVALID_DIVIDER;
+ divider_alloc_t *p_alloc = ÷r_allocations[div_type];
+
+ MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
+
+ core_util_critical_section_enter();
+
+ MBED_ASSERT(p_alloc->current_index < p_alloc->max_index);
+
+
+ for ( uint32_t first_index = p_alloc->current_index;
+ CY_INVALID_DIVIDER == (divider = cy_clk_reserve_divider(div_type, p_alloc->current_index));
+ ++p_alloc->current_index) {
+ if (p_alloc->current_index > p_alloc->max_index) {
+ p_alloc->current_index = 0;
+ }
+ if (p_alloc->current_index == first_index) {
+ break;
+ }
+ }
+
+ core_util_critical_section_exit();
+
+ return divider;
+}
+
+
+int cy_reserve_scb(uint32_t scb_num)
+{
+ int result = (-1);
+
+ if (scb_num < NUM_SCB) {
+ core_util_critical_section_enter();
+ if (scb_reservations[scb_num] == 0) {
+ scb_reservations[scb_num] = 1;
+ }
+ core_util_critical_section_exit();
+ }
+ return result;
+}
+
+
+void cy_free_scb(uint32_t scb_num)
+{
+ int result = (-1);
+
+ if (scb_num < NUM_SCB) {
+ core_util_critical_section_enter();
+ if (scb_reservations[scb_num] == 1) {
+ scb_reservations[scb_num] = 0;
+ }
+ core_util_critical_section_exit();
+ }
+ if (result) {
+ error("Trying to release wrong SCB.");
+ }
+}
+
+
+int cy_reserve_tcpwm(uint32_t tcpwm_num)
+{
+ int result = (-1);
+
+ if (tcpwm_num < NUM_TCPWM) {
+ core_util_critical_section_enter();
+ if (tcpwm_reservations[tcpwm_num] == 0) {
+ tcpwm_reservations[tcpwm_num] = 1;
+ result = 0;
+ }
+ core_util_critical_section_exit();
+ }
+ return result;
+}
+
+
+void cy_free_tcpwm(uint32_t tcpwm_num)
+{
+ int result = (-1);
+
+ if (tcpwm_num < NUM_TCPWM) {
+ core_util_critical_section_enter();
+ if (tcpwm_reservations[tcpwm_num] == 1) {
+ tcpwm_reservations[tcpwm_num] = 0;
+ result = 0;
+ }
+ core_util_critical_section_exit();
+ }
+ if (result) {
+ error("Trying to release wrong TCPWM.");
+ }
+}
+
+
+/*
+ * NVIC channel dynamic allocation (multiplexing) is used only on M0.
+ * On M4 IRQs are statically pre-assigned to NVIC channels.
+ */
+
+#if defined(TARGET_MCU_PSOC6_M0)
+
+#define NUM_NVIC_CHANNELS ((uint32_t)(NvicMux31_IRQn - NvicMux0_IRQn) + 1)
+
+static uint32_t irq_channels[NUM_NVIC_CHANNELS] = {0};
+
+
+IRQn_Type cy_m0_nvic_allocate_channel(uint32_t channel_id)
+{
+ IRQn_Type alloc = (IRQn_Type)(-1);
+ uint32_t chn;
+ MBED_ASSERT(channel_id);
+
+ core_util_critical_section_enter();
+ for (chn = 0; chn < NUM_NVIC_CHANNELS; ++chn) {
+ if (irq_channels[chn] == 0) {
+ irq_channels[chn] = channel_id;
+ alloc = NvicMux0_IRQn + chn;
+ break;
+ irq_channels[chn] = channel_id;
+
+ }
+ }
+ core_util_critical_section_exit();
+ return alloc;
+}
+
+IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t channel_id)
+{
+ uint32_t chn = channel - NvicMux0_IRQn;
+
+ MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
+ MBED_ASSERT(channel_id);
+
+ core_util_critical_section_enter();
+ if (irq_channels[chn]) {
+ channel = (IRQn_Type)(-1);
+ } else {
+ irq_channels[chn] = channel_id;
+ }
+ core_util_critical_section_exit();
+ return channel;
+}
+
+void cy_m0_nvic_release_channel(IRQn_Type channel, uint32_t channel_id)
+{
+ uint32_t chn = channel - NvicMux0_IRQn;
+
+ MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
+ MBED_ASSERT(channel_id);
+
+ core_util_critical_section_enter();
+ if (irq_channels[chn] == channel_id) {
+ irq_channels[chn] = 0;
+ } else {
+ error("NVIC channel cross-check failed on release.");
+ }
+ core_util_critical_section_exit();
+}
+
+#define CY_BLE_SFLASH_DIE_X_MASK (0x3Fu)
+#define CY_BLE_SFLASH_DIE_X_BITS (6u)
+#define CY_BLE_SFLASH_DIE_Y_MASK (0x3Fu)
+#define CY_BLE_SFLASH_DIE_Y_BITS (6u)
+#define CY_BLE_SFLASH_DIE_XY_BITS (CY_BLE_SFLASH_DIE_X_BITS + CY_BLE_SFLASH_DIE_Y_BITS)
+#define CY_BLE_SFLASH_DIE_WAFER_MASK (0x1Fu)
+#define CY_BLE_SFLASH_DIE_WAFER_BITS (5u)
+#define CY_BLE_SFLASH_DIE_XYWAFER_BITS (CY_BLE_SFLASH_DIE_XY_BITS + CY_BLE_SFLASH_DIE_WAFER_BITS)
+#define CY_BLE_SFLASH_DIE_LOT_MASK (0x7Fu)
+#define CY_BLE_SFLASH_DIE_LOT_BITS (7u)
+
+static uint8_t cy_ble_deviceAddress[6] = {0x19u, 0x00u, 0x00u, 0x50u, 0xA0u, 0x00u};
+
+void cy_get_bd_mac_address(uint8_t *buffer)
+{
+ uint32_t bdAddrLoc;
+ bdAddrLoc = ((uint32_t)SFLASH->DIE_X & (uint32_t)CY_BLE_SFLASH_DIE_X_MASK) |
+ ((uint32_t)(((uint32_t)SFLASH->DIE_Y) & ((uint32_t)CY_BLE_SFLASH_DIE_Y_MASK)) <<
+ CY_BLE_SFLASH_DIE_X_BITS) |
+ ((uint32_t)(((uint32_t)SFLASH->DIE_WAFER) & ((uint32_t)CY_BLE_SFLASH_DIE_WAFER_MASK)) <<
+ CY_BLE_SFLASH_DIE_XY_BITS) |
+ ((uint32_t)(((uint32_t)SFLASH->DIE_LOT[0]) & ((uint32_t)CY_BLE_SFLASH_DIE_LOT_MASK)) <<
+ CY_BLE_SFLASH_DIE_XYWAFER_BITS);
+
+ cy_ble_deviceAddress[0] = (uint8_t)bdAddrLoc;
+ cy_ble_deviceAddress[1] = (uint8_t)(bdAddrLoc >> 8u);
+ cy_ble_deviceAddress[2] = (uint8_t)(bdAddrLoc >> 16u);
+
+ for (int i = 0; i < 6; ++i) {
+ buffer[i] = cy_ble_deviceAddress[i];
+ }
+}
+
+#endif // defined(TARGET_MCU_PSOC6_M0)
+
+#endif // defined(TARGET_MCU_PSOC6_M0) || PSOC6_DSRM_DISABLE || !defined(__MBED__)
+
+void cy_srm_initialize(void)
+{
+#if PSOC6_DYNSRM_DISABLE
+#ifdef M0_ASSIGNED_PORTS
+ SRM_INIT_RESOURCE(uint8_t, port_reservations,, M0_ASSIGNED_PORTS);
+#endif
+#ifdef M0_ASSIGNED_DIVIDERS
+ SRM_INIT_RESOURCE(uint32_t, divider_allocations, .reservations, M0_ASSIGNED_DIVIDERS);
+#endif
+#ifdef M0_ASSIGNED_SCBS
+ SRM_INIT_RESOURCE(uint8_t, scb_reservations,, M0_ASSIGNED_SCBS);
+#endif
+#ifdef M0_ASSIGNED_TCPWMS
+ SRM_INIT_RESOURCE(uint8_t, tcpwm_reservations,, M0_ASSIGNED_TCPWMS);
+#endif
+#endif // PSOC6_DYNSRM_DISABLE
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,223 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _PSOC6_UTILS_H_
+#define _PSOC6_UTILS_H_
+
+#if defined(__MBED__)
+
+#include <stdint.h>
+#include <device.h>
+#include "drivers/peripheral/gpio/cy_gpio.h"
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+
+#else
+
+#include "project.h"
+
+#endif
+
+#include "PinNamesTypes.h"
+#include "PinNames.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+#define CY_INVALID_DIVIDER 0xFF
+
+/** \brief Allocates clock divider to be used for a new clock signal.
+ *
+ * \param div_type cy_en_divider_types_t Divider type.
+ * \return uint32_t Divider number (id) or CY_CLK_INVALID_DIVIDER if unavailable.
+ *
+ */
+uint32_t cy_clk_allocate_divider(cy_en_divider_types_t div_type);
+
+/** \brief Reserves clock divider to be used for a new clock signal.
+ *
+ * \param div_type cy_en_divider_types_t Divider type.
+ * \param div_num Divider number to be reserved.
+ * \return uint32_t Divider number (id) or CY_CLK_INVALID_DIVIDER if unavailable.
+ *
+ */
+uint32_t cy_clk_reserve_divider(cy_en_divider_types_t div_type, uint32_t div_num);
+
+/** \brief Releases already reserved clock divider.
+ *
+ * \param div_type cy_en_divider_types_t Divider type.
+ * \param div_num Divider number to be released.
+ *
+ */
+void cy_clk_free_divider(cy_en_divider_types_t div_type, uint32_t div_num);
+
+#ifdef TARGET_MCU_PSOC6_M0
+
+#include "gpio_irq_api.h"
+
+/** \brief On PSoC6 M0 core interrupts are routed into NVIC via additional multiplexer.
+ * This function allocates free NVIC channel to be used by particular interrupt.
+ *
+ * \param allocation_id Unique identifier (for debug purposes).
+ * \return IRQ channel allocated or (-1) if no free channel is available.
+ *
+ */
+IRQn_Type cy_m0_nvic_allocate_channel(uint32_t allocation_id);
+
+/** \brief Reserves particular NVIC channel if it is available.
+ *
+ * \param channel IRQn_Type Channel to be reserved.
+ * \param allocation_id uint32_t Identifier.
+ * \return IRQ channel allocated or (-1) if no free channel is available.
+ *
+ */
+IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t allocation_id);
+
+/** \brief Releases NVIC channel.
+ *
+ * \param channel IRQn_Type Channel to be released.
+ * \param allocation_id uint32_t Id used during allocation (for cross check).
+ * \return void
+ *
+ */
+void cy_m0_nvic_release_channel(IRQn_Type channel, uint32_t allocation_id);
+
+#endif /* M0+ core */
+
+
+/** \brief Request allocation of SCB block.
+ *
+ * \param scb_num uint32_t Id of the SCB block.
+ * \return (0) when OK, (-1) when reservation conflict occurs.
+ *
+ */
+int cy_reserve_scb(uint32_t scb_num);
+
+/** \brief Releases SCB block.
+ *
+ * \param scb_num uint32_t Id of the SCB block.
+ * \return void
+ *
+ */
+void cy_free_scb(uint32_t scb_num);
+
+/** \brief Request allocation of TCPWM block.
+ *
+ * \param tcpwm_num uint32_t Id of the TCPWM block.
+ * \return (0) when OK, (-1) when reservation conflict occurs.
+ *
+ */
+int cy_reserve_tcpwm(uint32_t tcpwm_num);
+
+/** \brief Releases TCPWM block.
+ *
+ * \param tcpwm_num uint32_t Id of the TCPWM block.
+ * \return void
+ *
+ */
+void cy_free_tcpwm(uint32_t tcpwm_num);
+
+/** \brief Request allocation of i/o pin.
+ *
+ * \param pin PinName Id of the pin to allocate.
+ * \return (0) when OK, (-1) when reservation conflict occurs.
+ *
+ */
+int cy_reserve_io_pin(PinName pin);
+
+
+/** \brief Releases i/o pin.
+ *
+ * \param pin PinName Id of the pin.
+ * \return void
+ *
+ */
+void cy_free_io_pin(PinName pin);
+
+/** \brief Initializes shared resource manager.
+ *
+ * \param none.
+ * \return void
+ *
+ */
+void cy_srm_initialize(void);
+
+
+/** \brief Returns board-specific hardware MAC address.
+ *
+ * \param uint8_t *buffer Buffer where address will be returned.
+ * \return void.
+ *
+ */
+void cy_get_bd_mac_address(uint8_t* buffer);
+
+
+/** \brief Determines proper PSoC6 pin drive mode settings.
+ *
+ * \param dir PinDirection Pin direction, in or out.
+ * \param mode PinMode Mbed pin mode.
+ * \return PSoC6 pin drive mode.
+ *
+ */
+static inline uint32_t gpio_get_cy_drive_mode(PinDirection dir, PinMode mode)
+{
+ uint32_t cymode = 0;
+
+ switch (mode) {
+ case PullNone:
+ switch (dir) {
+ case PIN_INPUT:
+ cymode = CY_GPIO_DM_HIGHZ;
+ break;
+ case PIN_OUTPUT:
+ cymode = CY_GPIO_DM_STRONG;
+ break;
+ }
+ break;
+
+ case PushPull:
+ cymode = CY_GPIO_DM_STRONG;
+ break;
+
+ case PullUp:
+ cymode = CY_GPIO_DM_PULLUP;
+ break;
+ case PullDown:
+ cymode = CY_GPIO_DM_PULLDOWN;
+ break;
+ case OpenDrainDriveLow:
+ cymode = CY_GPIO_DM_OD_DRIVESLOW;
+ break;
+ case OpenDrainDriveHigh:
+ cymode = CY_GPIO_DM_OD_DRIVESHIGH;
+ break;
+ case AnalogMode:
+ cymode = CY_GPIO_DM_ANALOG;
+ break;
+ }
+
+ return cymode;
+}
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+
+#endif // _PSOC6_UTILS_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/pwmout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,321 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "pwmout_api.h"
+#include "cy_tcpwm.h"
+#include "cy_tcpwm_pwm.h"
+#include "psoc6_utils.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "platform/mbed_error.h"
+#include "cy_syspm.h"
+
+#define PWMOUT_BASE_CLOCK_HZ 1000000UL
+#define MAX_16_BIT_PERIOD 65536
+
+static uint32_t pwm_clock_divider = CY_INVALID_DIVIDER;
+
+static const cy_stc_tcpwm_pwm_config_t pwm_config = {
+ .pwmMode = CY_TCPWM_PWM_MODE_PWM,
+ .clockPrescaler = 0, // will be configured separately
+ .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
+ .runMode = CY_TCPWM_PWM_CONTINUOUS,
+ .period0 = 0, // will be configured separately
+ .enablePeriodSwap = 0,
+ .compare0 = 0, // will be configured separately
+ .compare1 = 0, // will be configured separately
+ .enableCompareSwap = 0,
+ .interruptSources = 0, //CY_TCPWM_INT_ON_CC,
+ .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
+ .invertPWMOutN = CY_TCPWM_PWM_INVERT_ENABLE,
+ .killMode = CY_TCPWM_PWM_ASYNC_KILL,
+ .countInputMode = CY_TCPWM_INPUT_LEVEL,
+ .countInput = CY_TCPWM_INPUT_1,
+ .swapInputMode = CY_TCPWM_INPUT_LEVEL,
+ .swapInput = CY_TCPWM_INPUT_1,
+ .reloadInputMode = CY_TCPWM_INPUT_LEVEL,
+ .reloadInput = CY_TCPWM_INPUT_0,
+ .startInputMode = CY_TCPWM_INPUT_LEVEL,
+ .startInput = CY_TCPWM_INPUT_0,
+ .killInputMode = CY_TCPWM_INPUT_LEVEL,
+ .killInput = CY_TCPWM_INPUT_0,
+};
+
+
+static void Cy_TCPWM_PWM_SetPrescaler(TCPWM_Type *base, uint32_t cntNum, uint32_t prescaler)
+{
+ base->CNT[cntNum].CTRL = _CLR_SET_FLD32U(base->CNT[cntNum].CTRL, TCPWM_CNT_CTRL_GENERIC, prescaler);
+}
+
+static void pwm_start_32b(pwmout_t *obj, uint32_t new_period, uint32_t new_width)
+{
+ obj->period = new_period;
+ obj->pulse_width = new_width;
+ Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->counter_id, obj->period - 1);
+ Cy_TCPWM_PWM_SetCompare0(obj->base, obj->counter_id, obj->pulse_width);
+ Cy_TCPWM_PWM_Enable(obj->base, obj->counter_id);
+ Cy_TCPWM_TriggerStart(obj->base, 1UL << obj->counter_id);
+}
+
+static void pwm_start_16b(pwmout_t *obj, uint32_t period, uint32_t width)
+{
+ uint32_t prescaler = 0;
+
+ obj->period = period;
+ obj->pulse_width = width;
+
+ // For 16-bit counters we need to configure prescaler appropriately.
+ while ((period > MAX_16_BIT_PERIOD) && (prescaler < CY_TCPWM_PWM_PRESCALER_DIVBY_128)) {
+ period /= 2;
+ prescaler += 1;
+ }
+ if (period > MAX_16_BIT_PERIOD) {
+ // We have reached the prescaler limit, set period to max value.
+ error("Can't configure required PWM period.");
+ period = MAX_16_BIT_PERIOD;
+ }
+
+ obj->prescaler = prescaler;
+ width >>= prescaler;
+
+ Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->counter_id, period - 1);
+ Cy_TCPWM_PWM_SetPrescaler(obj->base, obj->counter_id, prescaler);
+ Cy_TCPWM_PWM_SetCompare0(obj->base, obj->counter_id, width);
+ Cy_TCPWM_PWM_Enable(obj->base, obj->counter_id);
+ Cy_TCPWM_TriggerStart(obj->base, 1UL << obj->counter_id);
+}
+
+static void pwm_start(pwmout_t *obj, uint32_t new_period, uint32_t new_pulse_width)
+{
+ obj->period = new_period;
+ obj->pulse_width = new_pulse_width;
+ Cy_TCPWM_PWM_Disable(obj->base, obj->counter_id);
+ if (new_period > 0) {
+ if (obj->base == TCPWM0) {
+ pwm_start_32b(obj, new_period, new_pulse_width);
+ } else {
+ pwm_start_16b(obj, new_period, new_pulse_width);
+ }
+ }
+}
+
+
+/*
+ * Callback handler to restart the timer after deep sleep.
+ */
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+static cy_en_syspm_status_t pwm_pm_callback(cy_stc_syspm_callback_params_t *callback_params)
+{
+ pwmout_t *obj = (pwmout_t *)callback_params->context;
+
+ switch (callback_params->mode) {
+ case CY_SYSPM_BEFORE_TRANSITION:
+ /* Disable timer before transition */
+ Cy_TCPWM_PWM_Disable(obj->base, obj->counter_id);
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ /* Enable the timer to operate */
+ if (obj->period > 0) {
+ Cy_TCPWM_PWM_Enable(obj->base, obj->counter_id);
+ Cy_TCPWM_TriggerStart(obj->base, 1UL << obj->counter_id);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return CY_SYSPM_SUCCESS;
+}
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+ uint32_t pwm_cnt = 0;
+ uint32_t pwm_function = 0;
+ uint32_t abs_cnt_num = 0;
+
+ MBED_ASSERT(obj);
+ MBED_ASSERT(pin != (PinName)NC);
+ // Allocate and setup clock.
+ if (pwm_clock_divider == CY_INVALID_DIVIDER) {
+ pwm_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
+ if (pwm_clock_divider == CY_INVALID_DIVIDER) {
+ error("PWM clock divider allocation failed.");
+ return;
+ }
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
+ pwm_clock_divider,
+ (CY_CLK_PERICLK_FREQ_HZ / PWMOUT_BASE_CLOCK_HZ) - 1);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, pwm_clock_divider);
+ }
+
+ pwm_cnt = pinmap_peripheral(pin, PinMap_PWM_OUT);
+ if (pwm_cnt != (uint32_t)NC) {
+ if (cy_reserve_io_pin(pin)) {
+ error("PWMOUT pin reservation conflict.");
+ }
+ obj->base = (TCPWM_Type*)CY_PERIPHERAL_BASE(pwm_cnt);
+ obj->pin = pin;
+ if (obj->base == TCPWM0) {
+ obj->counter_id = ((PWMName)pwm_cnt - PWM_32b_0) / (PWM_32b_1 - PWM_32b_0);
+ abs_cnt_num = obj->counter_id;
+ } else {
+ // TCPWM1 is used.
+ obj->counter_id = ((PWMName)pwm_cnt - PWM_16b_0) / (PWM_16b_1 - PWM_16b_0);
+ abs_cnt_num = obj->counter_id + 8;
+ }
+ if (cy_reserve_tcpwm(abs_cnt_num)) {
+ error("PWMOUT Timer/Counter reservation conflict.");
+ }
+
+ // Configure clock.
+ pwm_function = pinmap_function(pin, PinMap_PWM_OUT);
+ obj->clock = CY_PIN_CLOCK(pwm_function);
+ Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, pwm_clock_divider);
+ Cy_TCPWM_PWM_Init(obj->base, obj->counter_id, &pwm_config);
+ pin_function(pin, pwm_function);
+ // These will be properly configured later on.
+ obj->period = 0;
+ obj->pulse_width = 0;
+ obj->prescaler = 0;
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ obj->pm_callback_handler.callback = pwm_pm_callback;
+ obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP;
+ obj->pm_callback_handler.skipMode = CY_SYSPM_SKIP_CHECK_READY | CY_SYSPM_SKIP_CHECK_FAIL;
+ obj->pm_callback_handler.callbackParams = &obj->pm_callback_params;
+ obj->pm_callback_params.base = obj->base;
+ obj->pm_callback_params.context = obj;
+ if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) {
+ error("PM callback registration failed!");
+ }
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+
+ } else {
+ error("PWM OUT pinout mismatch.");
+ }
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+ // TODO: Not implemented yet.
+}
+
+void pwmout_write(pwmout_t *obj, float percent)
+{
+ uint32_t pulse_width;
+ MBED_ASSERT(obj);
+
+ if (percent < 0.0) {
+ percent = 0.0;
+ } else if (percent > 1.0) {
+ percent = 1.0;
+ }
+ pulse_width = (uint32_t)(percent * obj->period + 0.5);
+ pwm_start(obj, obj->period, pulse_width);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+ MBED_ASSERT(obj);
+
+ return (float)(obj->pulse_width) / obj->period;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+ uint32_t period;
+ uint32_t pulse_width;
+
+ MBED_ASSERT(obj);
+
+ if (seconds < 0.0) {
+ seconds = 0.0;
+ }
+ period = (uint32_t)(seconds * 1000000 + 0.5);
+ pulse_width = (uint32_t)((uint64_t)period * obj->pulse_width / obj->period);
+ pwm_start(obj, period, pulse_width);
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+ uint32_t period;
+ uint32_t pulse_width;
+
+ MBED_ASSERT(obj);
+
+ if (ms < 0.0) {
+ ms = 0.0;
+ }
+ period = (uint32_t)(ms * 1000 + 0.5);
+ pulse_width = (uint32_t)((uint64_t)period * obj->pulse_width / obj->period);
+ pwm_start(obj, period, pulse_width);
+}
+
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+ uint32_t pulse_width;
+
+ MBED_ASSERT(obj);
+
+ if (us < 0) {
+ us = 0;
+ }
+ pulse_width = (uint32_t)((uint64_t)us * obj->pulse_width / obj->period);
+ pwm_start(obj, us, pulse_width);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+ uint32_t pulse_width;
+
+ MBED_ASSERT(obj);
+
+ if (seconds < 0.0) {
+ seconds = 0.0;
+ }
+ pulse_width = (uint32_t)(seconds * 1000000 + 0.5);
+ pwm_start(obj, obj->period, pulse_width);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+ uint32_t pulse_width;
+
+ MBED_ASSERT(obj);
+
+ if (ms < 0.0) {
+ ms = 0.0;
+ }
+ pulse_width = (uint32_t)(ms * 1000 + 0.5);
+ pwm_start(obj, obj->period, pulse_width);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+ MBED_ASSERT(obj);
+
+ if (us < 0) {
+ us = 0;
+ }
+ pwm_start(obj, obj->period, us);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Cypress/TARGET_PSOC6/rpc_api.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,87 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file contains declarations of all the functions executed on CM0+ core + * that need to be callable from CM4 core via internal RPC mechanism. + * + * Functions are declared using RPC_FUNCTION( _type_, _name_, _args_) macro, + * where it's arguments are also created using support macros: + * _type_ is a function type declared as either TYPE(<actual_type>) or VOID, + * _name_ is a function name declared using macro NAME(<function name>), + * function must use "C" type interfacing (ABI), + * _args_ function arguments declared using macro ARGS(<list of types>), + * where <list of types> is a list of type definitions (as in function + * prototype). + * + * Proper RPC interfacing between processors is automatically generated based + * on the content of this file. + */ + +/* Notice! This file explicitly avoids using re-include suppress schema. */ + +#include "psoc6_utils.h" +#include "rpc_defs.h" + +#undef __RPC_API_H_BODY_START__ +#define __RPC_API_H_BODY_START__ + +#if !PSOC6_DYNSRM_DISABLE + +RPC_FUNCTION(TYPE( uint32_t ), + NAME( cy_clk_allocate_divider ), + ARGS( cy_en_divider_types_t /* div_type */)) + +RPC_FUNCTION(TYPE( uint32_t ), + NAME( cy_clk_reserve_divider ), + ARGS( cy_en_divider_types_t /* div_type */, uint32_t /* div_num */)) + +RPC_FUNCTION(VOID, + NAME( cy_clk_free_divider ), + ARGS( cy_en_divider_types_t /* div_type */, uint32_t /* div_num */)) + +RPC_FUNCTION(TYPE( int ), + NAME( cy_reserve_scb ), + ARGS( uint32_t /* scb_num */)) + +RPC_FUNCTION(VOID, + NAME( cy_free_scb ), + ARGS( uint32_t /* scb_num */)) + +RPC_FUNCTION(TYPE( int ), + NAME( cy_reserve_tcpwm ), + ARGS( uint32_t /* tcpwm_num */)) + +RPC_FUNCTION(VOID, + NAME( cy_free_tcpwm ), + ARGS( uint32_t /* tcpwm_num */)) + +RPC_FUNCTION(TYPE( int ), + NAME( cy_reserve_io_pin ), + ARGS( PinName /* pin */)) + +RPC_FUNCTION(VOID, + NAME( cy_free_io_pin ), + ARGS( PinName /* pin */)) + +RPC_FUNCTION(VOID, + NAME( cy_get_bd_mac_address ), + ARGS( uint8_t* /* buffer */ )) + +#endif // !PSOC6_DYNSRM_DISABLE + +#undef __RPC_API_H_BODY_END__ +#define __RPC_API_H_BODY_END__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/rpc_defs.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,236 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef RPC_DEFS_H
+#define RPC_DEFS_H
+
+/*
+ * This file defines set of helper macros used in implementation of the RPC
+ * (Remote Procedure Call) mechanism to allow M4 core (caller) to call functions
+ * that will execute on M0 core (callee), mainly used for shared hardware resource
+ * management.
+ * The RPC mechanism is build around PSoC6 IPC messaging interface.
+ * When a function has to be called remotely, its ID as well as arguments
+ * are packed into the message buffer and send out to M0 core.
+ * M0 core receives the message, unpacks arguments from the buffer and calls
+ * the proper function depending on the ID provided in the message. Then it puts
+ * the function result back into the buffer and releases the message back to
+ * M4 core.
+ * Additional assumptions:
+ * - message buffers reside in the M4 core address space,
+ * - M0 core has read/write access at least to the message buffers and to other
+ * data referenced when function arguments are pointers.
+ *
+ * The helper macros are used to automatically generate proper function wrappers for
+ * required APIs.
+ * All remotely callable functions have to be declared in the rpc_api.h header using
+ * a set of macros (see description in the rpc_api.h for details).
+ * Wrapper generation will process in a few phases, controlled by the value of
+ * RPC_GEN macro. Each generation phase is invoked as follows:
+ *
+ * #define RPC_GEN <phase>
+ * #include "rpc_api.h"
+ * #undef RPC_GEN
+ *
+ * Macros declaring RPC APIs in the rpc_api.h will be expanded to various C code, depending
+ * on the generation phase. See description of the generation phases below.
+ */
+
+
+/* Macros, that simply return it's n-th argument */
+#define _GET_10TH_ARG(_1, _2, _3, _4, _5, _6, _7, _8, _9, N, ...) N
+#define _GET_9TH_ARG(_1, _2, _3, _4, _5, _6, _7, _8, N, ...) N
+#define _GET_8TH_ARG(_1, _2, _3, _4, _5, _6, _7, N, ...) N
+#define _GET_7TH_ARG(_1, _2, _3, _4, _5, _6, N, ...) N
+#define _GET_6TH_ARG(_1, _2, _3, _4, _5, N, ...) N
+#define _GET_5TH_ARG(_1, _2, _3, _4, N, ...) N
+#define _GET_4TH_ARG(_1, _2, _3, N, ...) N
+#define _GET_3TH_ARG(_1, _2, N, ...) N
+#define _GET_2ND_ARG(_1, N, ...) N
+#define _GET_1ST_ARG(N, ...) N
+
+/* Count how many args are in a variadic macro. We now use GCC/Clang's extension to
+ * handle the case where ... expands to nothing. We must add a placeholder arg before
+ * ##__VA_ARGS__ (its value is totally irrelevant, but it's necessary to preserve
+ * the shifting offset we want). In addition, we must add 0 as a valid value to be in
+ * the N position.
+ * Good for 0 to 9 arguments.
+ */
+#define COUNT_VARARGS(...) _GET_10TH_ARG(__VA_ARGS__, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
+
+
+/* Non-variadic macros generating (RPC) function call arguments (on a callee MCU).
+ * Macro arguments are argument types for the function to be called,
+ * actual argument values are taken from RPC message buffer.
+ * Variants for functions using 0 - 5 arguments.
+ */
+#define _RPC_CALL_0() ()
+#define _RPC_CALL_1(_t1) ((_t1)(message->args[0]))
+#define _RPC_CALL_2(_t1, _t2) ((_t1)(message->args[0]), (_t2)(message->args[1]))
+#define _RPC_CALL_3(_t1, _t2, _t3) ((_t1)(message->args[0]), (_t2)(message->args[1]), (_t3)(message->args[2]))
+#define _RPC_CALL_4(_t1, _t2, _t3, _t4) ((_t1)(message->args[0]), (_t2)(message->args[1]), (_t3)(message->args[2]), (_t4)(message->args[3]))
+#define _RPC_CALL_5(_t1, _t2, _t3, _t4, _t5) ((_t1)(message->args[0]), (_t2)(message->args[1]), (_t4)(message->args[3]), (_t5)(message->args[4]), (_t2)(message->args[1]))
+
+/* Non-variadic macros generating (RPC) function argument declaration (on a caller MCU).
+ * Macro arguments are argument types for the function to be called.
+ * Expands to predefined argument names (arg1, arg2 and so on).
+ * Variants for functions using 0 - 5 arguments.
+ */
+#define _RPC_DECL_ARGS_0()
+#define _RPC_DECL_ARGS_1(_t1) _t1 arg1
+#define _RPC_DECL_ARGS_2(_t1, _t2) _t1 arg1, _t2 arg2
+#define _RPC_DECL_ARGS_3(_t1, _t2, _t3) _t1 arg1, _t2 arg2, _t3 arg3
+#define _RPC_DECL_ARGS_4(_t1, _t2, _t3, _t4) _t1 arg1, _t2 arg2, _t3 arg3, _t4 arg4
+#define _RPC_DECL_ARGS_5(_t1, _t2, _t3, _t4, _t5) _t1 arg1, _t2 arg2, _t3 arg3, _t4 arg4, _t5 arg5
+
+/* Non-variadic macros generating (RPC) function arguments (on a caller MCU).
+ * Macro arguments are argument types for the function to be called.
+ * Expands to predefined argument names (arg1, arg2 and so on).
+ * Variants for functions using 0 - 5 arguments.
+ */
+#define _RPC_ARGS_0()
+#define _RPC_ARGS_1(_t1) , arg1
+#define _RPC_ARGS_2(_t1, _t2) , arg1, arg2
+#define _RPC_ARGS_3(_t1, _t2, _t3) , arg1, arg2, arg3
+#define _RPC_ARGS_4(_t1, _t2, _t3, _t4) , arg1, arg2, arg3, arg4
+#define _RPC_ARGS_5(_t1, _t2, _t3, _t4, _t5) , arg1, arg2, arg3, arg4, arg5
+
+
+/* Variadic macro generating (RPC) function argument declaration (on a caller MCU).
+ * Macro arguments are argument types for the function to be called;
+ * expands to the non-variadic variant for the proper number of arguments.
+ */
+#define RPC_DECL_ARGS(...) \
+ _GET_6TH_ARG(__VA_ARGS__, _RPC_DECL_ARGS_5, _RPC_DECL_ARGS_4, _RPC_DECL_ARGS_3, _RPC_DECL_ARGS_2, _RPC_DECL_ARGS_1, _RPC_DECL_ARGS_0)(__VA_ARGS__)
+
+
+/* Variadic macro generating (RPC) function arguments (on a caller MCU).
+ * Macro arguments are argument types for the function to be called;
+ * expands to the non-variadic variant for the proper number of arguments.
+ */
+#define RPC_LIST_ARGS(...) \
+ _GET_6TH_ARG(__VA_ARGS__, _RPC_ARGS_5, _RPC_ARGS_4, _RPC_ARGS_3, _RPC_ARGS_2, _RPC_ARGS_1, _RPC_ARGS_0)(__VA_ARGS__)
+
+/* Variadic macro generating (RPC) function call arguments (on a callee MCU).
+ * Macro arguments are argument types for the function to be called;
+ * expands to the non-variadic variant for the proper number of arguments.
+ */
+#define RPC_CALL_ARGS(...) \
+ _GET_6TH_ARG(__VA_ARGS__, _RPC_CALL_5, _RPC_CALL_4, _RPC_CALL_3, _RPC_CALL_2, _RPC_CALL_1, _RPC_CALL_0)(__VA_ARGS__)
+
+
+#define _RPC_VOID(arg)
+#define _RPC_NON_VOID(arg) arg
+#define NAME(_name_) _name_
+#define TYPE(_type_) _RPC_NON_VOID, _type_
+#define VOID _RPC_VOID, void
+#define ARGS(...) __VA_ARGS__
+#define RPC_FUNCTION(...) RPC_FUNCTION_(__VA_ARGS__)
+
+/*
+ * Wrapper generation phases.
+ * ========================================================================================
+ * Generation of the RPC wrappers consists of a few phases, both on caller and callee MCUs.
+ * Each phase is invoked through re-definition of RPC_GEN macro (holding current phase id)
+ * and then inclusion of the rpc_api.h header, which also includes this file. The phases
+ * (and their applicability) are in sequence:
+ *
+ * RPC_GEN_INTERFACE_IDS (caller, callee)
+ * This will generate a set of variable declarations with names RPC_ID_<api name>,
+ * where <api_name> is a name of the RPCed function. Variables will be initialized
+ * in the next phase with unique integer values to be use in RPC messages to identify
+ * function to be called.
+ *
+ * RPC_GEN_INTERFACE_IDS_INIT (caller, callee)
+ * This will generate initialization code for the ID variables (assigning unique identifiers).
+ * The assumption is that the generation is invoked inside a function containing
+ * a local variable caller rpc_counter and initialized to 0. Example:
+ *
+ * void ipcrpc_init2(void)
+ * {
+ * uint32_t rpc_counter = 0;
+ * #define RPC_GEN RPC_GEN_INTERFACE_IDS_INIT
+ * #include "rpc_api.h"
+ * #undef RPC_GEN
+ * }
+ *
+ * RPC_GEN_INTERFACE (caller only)
+ * This will generate a set of functions with the defined API that will internally call
+ * RPC pipe message sending variadic function ipcrpc_call(...).
+ *
+ * RPC_GEN_IMPLEMENTATION (callee only)
+ * This will generate a set of functions named RPC_<api_name> which internally will decode
+ * an RPC message and will then call appropriate API function.
+ *
+ * RPC_GEN_IMPL_INITIALIZATION (callee only)
+ * This will generate an initialization code on a target(calee) core that will register
+ * interface functions generated in the previous step as RPC message receivers.
+ * This phase has to be invoked within a function with the same assumptions as for
+ * RPC_GEN_INTERFACE_IDS_INIT
+ */
+
+#define RPC_GEN_INTERFACE_IDS 1
+#define RPC_GEN_INTERFACE_IDS_INIT 2
+#define RPC_GEN_INTERFACE 3
+#define RPC_GEN_IMPLEMENTATION 4
+#define RPC_GEN_INITIALIZATION 5
+
+
+#endif // RPC_DEFS_H
+
+#undef __RPC_DEFS_H_BODY_START__
+#define __RPC_DEFS_H_BODY_START__
+
+#if RPC_GEN == RPC_GEN_INTERFACE_IDS
+/* Generating interface IDs. */
+#undef RPC_FUNCTION_
+#define RPC_FUNCTION_(T, _type_, _name_, ...) static uint32_t RPC_ID_##_name_ = 0;
+
+#elif RPC_GEN == RPC_GEN_INTERFACE_IDS_INIT
+/* Initialization of interface IDs. */
+#undef RPC_FUNCTION_
+#define RPC_FUNCTION_(T, _type_, _name_, ...)\
+ RPC_ID_##_name_ = rpc_counter++;
+
+#elif RPC_GEN == RPC_GEN_INTERFACE
+/* Generating interface functions on caller core. */
+#undef RPC_FUNCTION_
+#define RPC_FUNCTION_(T, _type_, _name_, ... )\
+_type_ _name_(RPC_DECL_ARGS(__VA_ARGS__)) {\
+ T(return ) (_type_)ipcrpc_call(RPC_ID_##_name_, COUNT_VARARGS(__VA_ARGS__) RPC_LIST_ARGS(__VA_ARGS__));\
+}
+
+#elif RPC_GEN == RPC_GEN_IMPLEMENTATION
+/* Generating implementation interface on a target (calee) core. */
+#undef RPC_FUNCTION_
+#define RPC_FUNCTION_( T, _type_, _name_, ...)\
+void RPC_##_name_(uint32_t *msg_ptr) {\
+ IpcRpcMessage *message = (IpcRpcMessage *)msg_ptr;\
+ T(message->result = ) (_type_) _name_ RPC_CALL_ARGS(__VA_ARGS__);\
+}
+
+#elif RPC_GEN == RPC_GEN_INITIALIZATION
+/* This will generate an initialization code on target(calee) core. */
+#undef RPC_FUNCTION_
+#define RPC_FUNCTION_( T, _type_, _name_, ...)\
+ Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_RPCPIPE_ADDR, RPC_##_name_, rpc_counter++);
+
+#endif // RPC_GEN
+
+#undef __RPC_DEFS_H_BODY_END__
+#define __RPC_DEFS_H_BODY_END__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,159 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "rtc_api.h"
+#include "mbed_error.h"
+#include "mbed_mktime.h"
+#include "cy_rtc.h"
+
+
+#if DEVICE_RTC
+
+/*
+ * Since Mbed tests insist on supporting 1970 - 2106 years range
+ * and Cypress h/w supports only 2000 - 2099 years range,
+* two backup registers are used to flag century correction.
+ */
+#define BR_LAST_YEAR_READ 14
+#define BR_CENTURY_CORRECTION 15
+
+static int enabled = 0;
+
+static uint32_t rtc_read_convert_year(uint32_t short_year)
+{
+ uint32_t century = BACKUP->BREG[BR_CENTURY_CORRECTION];
+
+ if (BACKUP->BREG[BR_LAST_YEAR_READ] > short_year) {
+ BACKUP->BREG[BR_CENTURY_CORRECTION] = ++century;
+ }
+ BACKUP->BREG[BR_LAST_YEAR_READ] = short_year;
+
+ return century * 100 + short_year;
+}
+
+static uint32_t rtc_write_convert_year(uint32_t long_year)
+{
+ uint32_t short_year = long_year;
+ uint32_t century = short_year / 100;
+ short_year -= century * 100;
+ BACKUP->BREG[BR_CENTURY_CORRECTION] = century;
+ BACKUP->BREG[BR_LAST_YEAR_READ] = short_year;
+ return short_year;
+}
+
+void rtc_init(void)
+{
+ static cy_stc_rtc_config_t init_val = {
+ /* Time information */
+ .hrFormat = CY_RTC_24_HOURS,
+ .sec = 0,
+ .min = 0,
+ .hour = 0,
+ .dayOfWeek = CY_RTC_SATURDAY,
+ .date = 1,
+ .month = 1,
+ .year = 0 // 2000 - 30 == 1970
+ };
+ cy_stc_rtc_config_t cy_time;
+
+ if (!enabled) {
+ // Setup power management callback.
+ // Setup century interrupt.
+ // Verify RTC time consistency.
+ Cy_RTC_GetDateAndTime(&cy_time);
+ if ( CY_RTC_IS_SEC_VALID(cy_time.sec) &&
+ CY_RTC_IS_MIN_VALID(cy_time.min) &&
+ CY_RTC_IS_HOUR_VALID(cy_time.hour) &&
+ CY_RTC_IS_DOW_VALID(cy_time.dayOfWeek) &&
+ CY_RTC_IS_MONTH_VALID(cy_time.month) &&
+ CY_RTC_IS_YEAR_SHORT_VALID(cy_time.year) &&
+ (cy_time.hrFormat == CY_RTC_24_HOURS)) {
+ enabled = 1;
+ } else {
+ // reinitialize
+ init_val.year = rtc_write_convert_year(1970);
+ if (Cy_RTC_Init(&init_val) == CY_RTC_SUCCESS) {
+ enabled = 1;
+ }
+ }
+ }
+}
+
+void rtc_free(void)
+{
+ // Nothing to do
+}
+
+int rtc_isenabled(void)
+{
+ return enabled;
+}
+
+time_t rtc_read(void)
+{
+ cy_stc_rtc_config_t cy_time;
+ struct tm gmt;
+ time_t timestamp = 0;
+ uint32_t interrupt_state;
+
+ // Since RTC reading function is unreliable when the RTC is busy with previous update
+ // we have to make sure it's not before calling it.
+ while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) {}
+
+ interrupt_state = Cy_SysLib_EnterCriticalSection();
+ Cy_RTC_GetDateAndTime(&cy_time);
+ gmt.tm_sec = cy_time.sec;
+ gmt.tm_min = cy_time.min;
+ gmt.tm_hour = cy_time.hour;
+ gmt.tm_mday = cy_time.date;
+ gmt.tm_mon = cy_time.month - 1;
+ gmt.tm_year = rtc_read_convert_year(cy_time.year);
+ gmt.tm_isdst = 0;
+ Cy_SysLib_ExitCriticalSection(interrupt_state);
+
+ _rtc_maketime(&gmt, ×tamp, RTC_4_YEAR_LEAP_YEAR_SUPPORT);
+ return timestamp;
+}
+
+void rtc_write(time_t t)
+{
+ cy_en_rtc_status_t status;
+ struct tm gmt;
+
+ if ( _rtc_localtime(t, &gmt, RTC_4_YEAR_LEAP_YEAR_SUPPORT)) {
+ uint32_t year;
+ uint32_t interrupt_state;
+ // Make sure RTC is not busy and can be updated.
+ while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) {}
+
+ interrupt_state = Cy_SysLib_EnterCriticalSection();
+ year = rtc_write_convert_year(gmt.tm_year);
+ status = Cy_RTC_SetDateAndTimeDirect(gmt.tm_sec,
+ gmt.tm_min,
+ gmt.tm_hour,
+ gmt.tm_mday,
+ gmt.tm_mon + 1,
+ year);
+ Cy_SysLib_ExitCriticalSection(interrupt_state);
+ if (status != CY_RTC_SUCCESS) {
+ error("Error 0x%x while setting RTC time.", status);
+ }
+ }
+}
+
+#endif // DEVICE_RTC
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,820 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if DEVICE_SERIAL
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "pinmap.h"
+#include "serial_api.h"
+#include "psoc6_utils.h"
+
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+#include "drivers/peripheral/gpio/cy_gpio.h"
+#include "drivers/peripheral/scb/cy_scb_uart.h"
+#include "drivers/peripheral/sysint/cy_sysint.h"
+
+#define UART_OVERSAMPLE 12
+#define UART_DEFAULT_BAUDRATE 115200
+#define NUM_SERIAL_PORTS 8
+#define SERIAL_DEFAULT_IRQ_PRIORITY 3
+
+typedef struct serial_s serial_obj_t;
+#if DEVICE_SERIAL_ASYNCH
+#define OBJ_P(in) (&(in->serial))
+#else
+#define OBJ_P(in) (in)
+#endif
+
+/*
+ * NOTE: Cypress PDL high level API implementation of USART doe not
+ * align well with Mbed interface for interrupt-driven serial I/O.
+ * For this reason only low level PDL API is used here.
+ */
+
+
+static const cy_stc_scb_uart_config_t default_uart_config = {
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+
+ .oversample = UART_OVERSAMPLE,
+
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 20UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+
+ .rxFifoTriggerLevel = 0UL,
+ .rxFifoIntEnableMask = 0x0UL,
+
+ .txFifoTriggerLevel = 0UL,
+ .txFifoIntEnableMask = 0x0UL
+};
+
+int stdio_uart_inited = false;
+serial_t stdio_uart;
+
+typedef struct irq_info_s {
+ serial_obj_t *serial_obj;
+ uart_irq_handler handler;
+ uint32_t id_arg;
+ IRQn_Type irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_en_intr_t cm0p_irq_src;
+#endif
+} irq_info_t;
+
+static irq_info_t irq_info[NUM_SERIAL_PORTS] = {
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn},
+ {NULL, NULL, 0, unconnected_IRQn}
+};
+
+
+static void serial_irq_dispatcher(uint32_t serial_id)
+{
+ MBED_ASSERT(serial_id < NUM_SERIAL_PORTS);
+ irq_info_t *info = &irq_info[serial_id];
+ serial_obj_t *obj = info->serial_obj;
+ MBED_ASSERT(obj);
+
+#if DEVICE_SERIAL_ASYNCH
+ if (obj->async_handler) {
+ obj->async_handler();
+ return;
+ }
+#endif
+ if (Cy_SCB_GetRxInterruptStatusMasked(obj->base) & CY_SCB_RX_INTR_NOT_EMPTY) {
+ info->handler(info->id_arg, RxIrq);
+ Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY);
+ }
+
+ if (Cy_SCB_GetTxInterruptStatusMasked(obj->base) & (CY_SCB_TX_INTR_LEVEL | CY_SCB_UART_TX_DONE)) {
+ info->handler(info->id_arg, TxIrq);
+ }
+}
+
+static void serial_irq_dispatcher_uart0(void)
+{
+ serial_irq_dispatcher(0);
+}
+
+static void serial_irq_dispatcher_uart1(void)
+{
+ serial_irq_dispatcher(1);
+}
+
+static void serial_irq_dispatcher_uart2(void)
+{
+ serial_irq_dispatcher(2);
+}
+
+static void serial_irq_dispatcher_uart3(void)
+{
+ serial_irq_dispatcher(3);
+}
+
+static void serial_irq_dispatcher_uart4(void)
+{
+ serial_irq_dispatcher(4);
+}
+
+static void serial_irq_dispatcher_uart5(void)
+{
+ serial_irq_dispatcher(5);
+}
+
+void serial_irq_dispatcher_uart6(void)
+{
+ serial_irq_dispatcher(6);
+}
+
+static void serial_irq_dispatcher_uart7(void)
+{
+ serial_irq_dispatcher(7);
+}
+
+
+static void (*irq_dispatcher_table[])(void) = {
+ serial_irq_dispatcher_uart0,
+ serial_irq_dispatcher_uart1,
+ serial_irq_dispatcher_uart2,
+ serial_irq_dispatcher_uart3,
+ serial_irq_dispatcher_uart4,
+ serial_irq_dispatcher_uart5,
+ serial_irq_dispatcher_uart6,
+ serial_irq_dispatcher_uart7
+};
+
+
+static IRQn_Type serial_irq_allocate_channel(serial_obj_t *obj)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ irq_info[obj->serial_id].cm0p_irq_src = scb_0_interrupt_IRQn + obj->serial_id;
+ return cy_m0_nvic_allocate_channel(CY_SERIAL_IRQN_ID + obj->serial_id);
+#else
+ return (IRQn_Type)(scb_0_interrupt_IRQn + obj->serial_id);
+#endif // M0
+}
+
+static void serial_irq_release_channel(IRQn_Type channel, uint32_t serial_id)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_m0_nvic_release_channel(channel, CY_SERIAL_IRQN_ID + serial_id);
+#endif //M0
+}
+
+static int serial_irq_setup_channel(serial_obj_t *obj)
+{
+ cy_stc_sysint_t irq_config;
+ irq_info_t *info = &irq_info[obj->serial_id];
+
+ if (info->irqn == unconnected_IRQn) {
+ IRQn_Type irqn = serial_irq_allocate_channel(obj);
+ if (irqn < 0) {
+ return (-1);
+ }
+ // Configure NVIC
+ irq_config.intrPriority = SERIAL_DEFAULT_IRQ_PRIORITY;
+ irq_config.intrSrc = irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ irq_config.cm0pSrc = info->cm0p_irq_src;
+#endif
+ if (Cy_SysInt_Init(&irq_config, irq_dispatcher_table[obj->serial_id]) != CY_SYSINT_SUCCESS) {
+ return(-1);
+ }
+
+ info->irqn = irqn;
+ info->serial_obj = obj;
+ NVIC_EnableIRQ(irqn);
+ }
+ return 0;
+}
+
+/*
+ * Calculates fractional divider value.
+ */
+static uint32_t divider_value(uint32_t frequency, uint32_t frac_bits)
+{
+ /* UARTs use peripheral clock */
+ return ((CY_CLK_PERICLK_FREQ_HZ * (1 << frac_bits)) + (frequency / 2)) / frequency;
+}
+
+static cy_en_sysclk_status_t serial_init_clock(serial_obj_t *obj, uint32_t baudrate)
+{
+ cy_en_sysclk_status_t status = CY_SYSCLK_BAD_PARAM;
+
+ if (obj->div_num == CY_INVALID_DIVIDER) {
+ uint32_t divider_num = cy_clk_allocate_divider(CY_SYSCLK_DIV_16_5_BIT);
+
+ if (divider_num < PERI_DIV_16_5_NR) {
+ /* Assign fractional divider. */
+ status = Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_16_5_BIT, divider_num);
+ if (status == CY_SYSCLK_SUCCESS) {
+ obj->div_type = CY_SYSCLK_DIV_16_5_BIT;
+ obj->div_num = divider_num;
+ }
+ } else {
+ // Try 16-bit divider.
+ divider_num = cy_clk_allocate_divider(CY_SYSCLK_DIV_16_BIT);
+ if (divider_num < PERI_DIV_16_NR) {
+ /* Assign 16-bit divider. */
+ status = Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_16_BIT, divider_num);
+ if (status == CY_SYSCLK_SUCCESS) {
+ obj->div_type = CY_SYSCLK_DIV_16_BIT;
+ obj->div_num = divider_num;
+ }
+ } else {
+ error("Serial: cannot assign clock divider.");
+ }
+ }
+ } else {
+ status = CY_SYSCLK_SUCCESS;
+ }
+
+ if (status == CY_SYSCLK_SUCCESS) {
+ /* Set baud rate */
+ if (obj->div_type == CY_SYSCLK_DIV_16_5_BIT) {
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_5_BIT, obj->div_num);
+ uint32_t divider = divider_value(baudrate * UART_OVERSAMPLE, 5);
+ status = Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT,
+ obj->div_num,
+ (divider >> 5) - 1, // integral part
+ divider & 0x1F); // fractional part
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_5_BIT, obj->div_num);
+ } else if (obj->div_type == CY_SYSCLK_DIV_16_BIT) {
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, obj->div_num);
+ status = Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT,
+ obj->div_num,
+ divider_value(baudrate * UART_OVERSAMPLE, 0));
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, obj->div_num);
+ }
+ }
+ return status;
+}
+
+/*
+ * Initializes i/o pins for UART tx/rx.
+ */
+static void serial_init_pins(serial_obj_t *obj)
+{
+ int tx_function = pinmap_function(obj->pin_tx, PinMap_UART_TX);
+ int rx_function = pinmap_function(obj->pin_rx, PinMap_UART_RX);
+ if (cy_reserve_io_pin(obj->pin_tx) || cy_reserve_io_pin(obj->pin_rx)) {
+ error("Serial TX/RX pin reservation conflict.");
+ }
+ pin_function(obj->pin_tx, tx_function);
+ pin_function(obj->pin_rx, rx_function);
+}
+
+/*
+ * Initializes i/o pins for UART flow control.
+ */
+static void serial_init_flow_pins(serial_obj_t *obj)
+{
+ if (obj->pin_rts != NC) {
+ int rts_function = pinmap_function(obj->pin_rts, PinMap_UART_RTS);
+ if (cy_reserve_io_pin(obj->pin_rts)) {
+ error("Serial RTS pin reservation conflict.");
+ }
+ pin_function(obj->pin_rts, rts_function);
+ }
+
+ if (obj->pin_cts != NC) {
+ int cts_function = pinmap_function(obj->pin_cts, PinMap_UART_CTS);
+ if (cy_reserve_io_pin(obj->pin_cts)) {
+ error("Serial CTS pin reservation conflict.");
+ }
+ pin_function(obj->pin_cts, cts_function);
+ }
+}
+
+
+/*
+ * Initializes and enables UART/SCB.
+ */
+static void serial_init_peripheral(serial_obj_t *obj)
+{
+ cy_stc_scb_uart_config_t uart_config = default_uart_config;
+
+ uart_config.dataWidth = obj->data_width;
+ uart_config.parity = obj->parity;
+ uart_config.stopBits = obj->stop_bits;
+ uart_config.enableCts = (obj->pin_cts != NC);
+
+ Cy_SCB_UART_Init(obj->base, &uart_config, NULL);
+ Cy_SCB_UART_Enable(obj->base);
+}
+
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+static cy_en_syspm_status_t serial_pm_callback(cy_stc_syspm_callback_params_t *params)
+{
+ serial_obj_t *obj = (serial_obj_t *)params->context;
+ cy_en_syspm_status_t status = CY_SYSPM_FAIL;
+
+ switch (params->mode) {
+ case CY_SYSPM_CHECK_READY:
+ /* If all data elements are transmitted from the TX FIFO and
+ * shifter and the RX FIFO is empty: the UART is ready to enter
+ * Deep Sleep mode.
+ */
+ if (Cy_SCB_UART_IsTxComplete(obj->base)) {
+ if (0UL == Cy_SCB_UART_GetNumInRxFifo(obj->base)) {
+ /* Disable the UART. The transmitter stops driving the
+ * lines and the receiver stops receiving data until
+ * the UART is enabled.
+ * This happens when the device failed to enter Deep
+ * Sleep or it is awaken from Deep Sleep mode.
+ */
+ Cy_SCB_UART_Disable(obj->base, NULL);
+ status = CY_SYSPM_SUCCESS;
+ }
+ }
+ break;
+
+
+ case CY_SYSPM_CHECK_FAIL:
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(obj->base);
+ status = CY_SYSPM_SUCCESS;
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ status = CY_SYSPM_SUCCESS;
+ break;
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ /* Enable the UART to operate */
+ Cy_SCB_UART_Enable(obj->base);
+ status = CY_SYSPM_SUCCESS;
+ break;
+
+ default:
+ break;
+ }
+ return status;
+}
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+
+void serial_init(serial_t *obj_in, PinName tx, PinName rx)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ bool is_stdio = (tx == CY_STDIO_UART_TX) || (rx == CY_STDIO_UART_RX);
+
+ if (is_stdio && stdio_uart_inited) {
+ memcpy(obj_in, &stdio_uart, sizeof(serial_t));
+ return;
+ }
+ {
+ uint32_t uart = pinmap_peripheral(tx, PinMap_UART_TX);
+ uart = pinmap_merge(uart, pinmap_peripheral(rx, PinMap_UART_RX));
+ if (uart != (uint32_t)NC) {
+ obj->base = (CySCB_Type*)uart;
+ obj->serial_id = ((UARTName)uart - UART_0) / (UART_1 - UART_0);
+ obj->pin_tx = tx;
+ obj->pin_rx = rx;
+ obj->clock = CY_PIN_CLOCK(pinmap_function(tx, PinMap_UART_TX));
+ obj->div_num = CY_INVALID_DIVIDER;
+ obj->data_width = 8;
+ obj->stop_bits = CY_SCB_UART_STOP_BITS_1;
+ obj->parity = CY_SCB_UART_PARITY_NONE;
+ obj->pin_rts = NC;
+ obj->pin_cts = NC;
+
+ serial_init_clock(obj, UART_DEFAULT_BAUDRATE);
+ serial_init_peripheral(obj);
+ //Cy_GPIO_Write(Cy_GPIO_PortToAddr(CY_PORT(P13_6)), CY_PIN(P13_6), 1);
+ serial_init_pins(obj);
+ //Cy_GPIO_Write(Cy_GPIO_PortToAddr(CY_PORT(P13_6)), CY_PIN(P13_6), 0);
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ obj->pm_callback_handler.callback = serial_pm_callback;
+ obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP;
+ obj->pm_callback_handler.skipMode = 0;
+ obj->pm_callback_handler.callbackParams = &obj->pm_callback_params;
+ obj->pm_callback_params.base = obj->base;
+ obj->pm_callback_params.context = obj;
+ if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) {
+ error("PM callback registration failed!");
+ }
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ if (is_stdio) {
+ memcpy(&stdio_uart, obj_in, sizeof(serial_t));
+ stdio_uart_inited = true;
+ }
+ } else {
+ error("Serial pinout mismatch. Requested pins Rx and Tx can't be used for the same Serial communication.");
+ }
+ }
+}
+
+void serial_baud(serial_t *obj_in, int baudrate)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ Cy_SCB_UART_Disable(obj->base, NULL);
+ serial_init_clock(obj, baudrate);
+ Cy_SCB_UART_Enable(obj->base);
+}
+
+void serial_format(serial_t *obj_in, int data_bits, SerialParity parity, int stop_bits)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ if ((data_bits >= 5) && (data_bits <= 9)) {
+ obj->data_width = data_bits;
+ }
+
+ switch (parity) {
+ case ParityNone:
+ obj->parity = CY_SCB_UART_PARITY_NONE;
+ break;
+ case ParityOdd:
+ obj->parity = CY_SCB_UART_PARITY_ODD;
+ break;
+ case ParityEven:
+ obj->parity = CY_SCB_UART_PARITY_EVEN;
+ break;
+ case ParityForced1:
+ case ParityForced0:
+ MBED_ASSERT("Serial parity mode not supported!");
+ break;
+ }
+
+ switch (stop_bits) {
+ case 1:
+ obj->stop_bits = CY_SCB_UART_STOP_BITS_1;
+ break;
+ case 2:
+ obj->stop_bits = CY_SCB_UART_STOP_BITS_2;
+ break;
+ case 3:
+ obj->stop_bits = CY_SCB_UART_STOP_BITS_3;
+ break;
+ case 4:
+ obj->stop_bits = CY_SCB_UART_STOP_BITS_4;
+ break;
+ }
+
+ Cy_SCB_UART_Disable(obj->base, NULL);
+ serial_init_peripheral(obj);
+}
+
+void serial_putc(serial_t *obj_in, int c)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ while (!serial_writable(obj_in)) {
+ // empty
+ }
+ Cy_SCB_UART_Put(obj->base, c);
+}
+
+int serial_getc(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ while (!serial_readable(obj_in)) {
+ // empty
+ }
+ return Cy_SCB_UART_Get(obj->base);
+}
+
+int serial_readable(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ return Cy_SCB_GetNumInRxFifo(obj->base) != 0;
+}
+
+int serial_writable(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ return Cy_SCB_GetNumInTxFifo(obj->base) != Cy_SCB_GetFifoSize(obj->base);
+}
+
+void serial_clear(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ Cy_SCB_UART_Disable(obj->base, NULL);
+ Cy_SCB_ClearTxFifo(obj->base);
+ Cy_SCB_ClearRxFifo(obj->base);
+ serial_init_peripheral(obj);
+}
+
+void serial_break_set(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ /* Cypress SCB does not support transmitting break directly.
+ * We emulate functionality by switching TX pin to GPIO mode.
+ */
+ GPIO_PRT_Type *port_tx = Cy_GPIO_PortToAddr(CY_PORT(obj->pin_tx));
+ Cy_GPIO_Pin_FastInit(port_tx, CY_PIN(obj->pin_tx), CY_GPIO_DM_STRONG_IN_OFF, 0, HSIOM_SEL_GPIO);
+ Cy_GPIO_Write(port_tx, CY_PIN(obj->pin_tx), 0);
+}
+
+void serial_break_clear(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ /* Connect TX pin back to SCB, see a comment in serial_break_set() above */
+ GPIO_PRT_Type *port_tx = Cy_GPIO_PortToAddr(CY_PORT(obj->pin_tx));
+ int tx_function = pinmap_function(obj->pin_tx, PinMap_UART_TX);
+ Cy_GPIO_Pin_FastInit(port_tx, CY_PIN(obj->pin_tx), CY_GPIO_DM_STRONG_IN_OFF, 0, CY_PIN_HSIOM(tx_function));
+}
+
+void serial_set_flow_control(serial_t *obj_in, FlowControl type, PinName rxflow, PinName txflow)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ Cy_SCB_UART_Disable(obj->base, NULL);
+
+ switch (type) {
+ case FlowControlNone:
+ obj->pin_rts = NC;
+ obj->pin_cts = NC;
+ break;
+ case FlowControlRTS:
+ obj->pin_rts = rxflow;
+ obj->pin_cts = NC;
+ break;
+ case FlowControlCTS:
+ obj->pin_rts = NC;
+ obj->pin_cts = txflow;
+ break;
+ case FlowControlRTSCTS:
+ obj->pin_rts = rxflow;
+ obj->pin_cts = txflow;
+ break;
+ }
+
+ serial_init_peripheral(obj);
+ serial_init_flow_pins(obj);
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+void serial_irq_handler(serial_t *obj_in, uart_irq_handler handler, uint32_t id)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ irq_info_t *info = &irq_info[obj->serial_id];
+
+ if (info->irqn != unconnected_IRQn) {
+ NVIC_DisableIRQ(info->irqn);
+ }
+ info->handler = handler;
+ info->id_arg = id;
+ serial_irq_setup_channel(obj);
+}
+
+void serial_irq_set(serial_t *obj_in, SerialIrq irq, uint32_t enable)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ switch (irq) {
+ case RxIrq:
+ if (enable) {
+ Cy_SCB_SetRxInterruptMask(obj->base, CY_SCB_RX_INTR_NOT_EMPTY);
+ } else {
+ Cy_SCB_SetRxInterruptMask(obj->base, 0);
+ }
+ break;
+ case TxIrq:
+ if (enable) {
+ Cy_SCB_SetTxInterruptMask(obj->base, CY_SCB_TX_INTR_LEVEL | CY_SCB_UART_TX_DONE);
+ } else {
+ Cy_SCB_SetTxInterruptMask(obj->base, 0);
+ }
+ break;
+ }
+}
+
+static void serial_finish_tx_asynch(serial_obj_t *obj)
+{
+ Cy_SCB_SetTxInterruptMask(obj->base, 0);
+ obj->tx_pending = false;
+}
+
+static void serial_finish_rx_asynch(serial_obj_t *obj)
+{
+ Cy_SCB_SetRxInterruptMask(obj->base, 0);
+ obj->rx_pending = false;
+}
+
+int serial_tx_asynch(serial_t *obj_in, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+ const uint8_t *p_buf = tx;
+
+ (void)tx_width; // Obsolete argument
+ (void)hint; // At the moment we do not support DAM transfers, so this parameter gets ignored.
+
+ if (obj->tx_pending) {
+ return 0;
+ }
+
+ obj->async_handler = (cy_israddress)handler;
+ if (serial_irq_setup_channel(obj) < 0) {
+ return 0;
+ }
+
+ // Write as much as possible into the FIFO first.
+ while ((tx_length > 0) && Cy_SCB_UART_Put(obj->base, *p_buf)) {
+ ++p_buf;
+ --tx_length;
+ }
+
+ if (tx_length > 0) {
+ obj->tx_events = event;
+ obj_in->tx_buff.buffer = (void *)p_buf;
+ obj_in->tx_buff.length = tx_length;
+ obj_in->tx_buff.pos = 0;
+ obj->tx_pending = true;
+ // Enable interrupts to complete transmission.
+ Cy_SCB_SetRxInterruptMask(obj->base, CY_SCB_TX_INTR_LEVEL | CY_SCB_UART_TX_DONE);
+
+ } else {
+ // Enable interrupt to signal completing of the transmission.
+ Cy_SCB_SetRxInterruptMask(obj->base, CY_SCB_UART_TX_DONE);
+ }
+ return tx_length;
+}
+
+void serial_rx_asynch(serial_t *obj_in, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ (void)rx_width; // Obsolete argument
+ (void)hint; // At the moment we do not support DAM transfers, so this parameter gets ignored.
+
+ if (obj->rx_pending || (rx_length == 0)) {
+ return;
+ }
+
+ obj_in->char_match = char_match;
+ obj_in->char_found = false;
+ obj->rx_events = event;
+ obj_in->rx_buff.buffer = rx;
+ obj_in->rx_buff.length = rx_length;
+ obj_in->rx_buff.pos = 0;
+ obj->async_handler = (cy_israddress)handler;
+ if (serial_irq_setup_channel(obj) < 0) {
+ return;
+ }
+ obj->rx_pending = true;
+ // Enable interrupts to start receiving.
+ Cy_SCB_SetRxInterruptMask(obj->base, CY_SCB_UART_RX_INTR_MASK & ~CY_SCB_RX_INTR_UART_BREAK_DETECT);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+ return obj->serial.tx_pending;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+ return obj->serial.rx_pending;
+}
+
+int serial_irq_handler_asynch(serial_t *obj_in)
+{
+ uint32_t cur_events = 0;
+ uint32_t tx_status;
+ uint32_t rx_status;
+
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ rx_status = Cy_SCB_GetRxInterruptStatusMasked(obj->base);
+
+ tx_status = Cy_SCB_GetTxInterruptStatusMasked(obj->base);
+
+
+ if (tx_status & CY_SCB_TX_INTR_LEVEL) {
+ // FIFO has space available for more TX
+ uint8_t *ptr = obj_in->tx_buff.buffer;
+ ptr += obj_in->tx_buff.pos;
+ while ((obj_in->tx_buff.pos < obj_in->tx_buff.length) &&
+ Cy_SCB_UART_Put(obj->base, *ptr)) {
+ ++ptr;
+ ++(obj_in->tx_buff.pos);
+ }
+ if (obj_in->tx_buff.pos == obj_in->tx_buff.length) {
+ // No more bytes to follow; check to see if we need to signal completion.
+ if (obj->tx_events & SERIAL_EVENT_TX_COMPLETE) {
+ // Disable FIFO interrupt as there are no more bytes to follow.
+ Cy_SCB_SetRxInterruptMask(obj->base, CY_SCB_UART_TX_DONE);
+ } else {
+ // Nothing more to do, mark end of transmission.
+ serial_finish_tx_asynch(obj);
+ }
+ }
+ }
+
+ if (tx_status & CY_SCB_TX_INTR_UART_DONE) {
+ // Mark end of the transmission.
+ serial_finish_tx_asynch(obj);
+ cur_events |= SERIAL_EVENT_TX_COMPLETE & obj->tx_events;
+ }
+
+ Cy_SCB_ClearTxInterrupt(obj->base, tx_status);
+
+ if (rx_status & CY_SCB_RX_INTR_OVERFLOW) {
+ cur_events |= SERIAL_EVENT_RX_OVERRUN_ERROR & obj->rx_events;
+ }
+
+ if (rx_status & CY_SCB_RX_INTR_UART_FRAME_ERROR) {
+ cur_events |= SERIAL_EVENT_RX_FRAMING_ERROR & obj->rx_events;
+ }
+
+ if (rx_status & CY_SCB_RX_INTR_UART_PARITY_ERROR) {
+ cur_events |= SERIAL_EVENT_RX_PARITY_ERROR & obj->rx_events;
+ }
+
+ if (rx_status & CY_SCB_RX_INTR_LEVEL) {
+ uint8_t *ptr = obj_in->rx_buff.buffer;
+ ptr += obj_in->rx_buff.pos;
+ while (obj_in->rx_buff.pos < obj_in->rx_buff.length) {
+ uint32_t c = Cy_SCB_UART_Get(obj->base);
+ if (c == CY_SCB_UART_RX_NO_DATA) {
+ break;
+ }
+ *ptr++ = (uint8_t)c;
+ ++(obj_in->rx_buff.pos);
+ // Check for character match condition.
+ if (obj_in->char_match != SERIAL_RESERVED_CHAR_MATCH) {
+ if (c == obj_in->char_match) {
+ obj_in->char_found = true;
+ cur_events |= SERIAL_EVENT_RX_CHARACTER_MATCH & obj->rx_events;
+ // Clamp RX.
+ obj_in->rx_buff.length = obj_in->rx_buff.pos;
+ break;
+ }
+ }
+ }
+ }
+
+ if (obj_in->rx_buff.pos == obj_in->rx_buff.length) {
+ serial_finish_rx_asynch(obj);
+ }
+
+ Cy_SCB_ClearRxInterrupt(obj->base, rx_status);
+
+ return cur_events;
+}
+
+void serial_tx_abort_asynch(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ serial_finish_tx_asynch(obj);
+ Cy_SCB_UART_ClearTxFifo(obj->base);
+}
+
+void serial_rx_abort_asynch(serial_t *obj_in)
+{
+ serial_obj_t *obj = OBJ_P(obj_in);
+
+ serial_finish_rx_asynch(obj);
+ Cy_SCB_UART_ClearRxFifo(obj->base);
+}
+
+#endif // DEVICE_SERIAL_ASYNCH
+
+#endif // DEVICE_SERIAL
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/sleep_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,42 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "device.h"
+#include "cy_syspm.h"
+
+#ifdef DEVICE_SLEEP
+
+void hal_sleep(void)
+{
+ Cy_SysPm_Sleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
+}
+
+void hal_deepsleep(void)
+{
+#if DEVICE_LPTICKER
+ if(CY_SYSPM_SUCCESS == Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)) {
+ // Have to make sure PLL clock is restored before continuing.
+ // FLL clock is not used in basic configuration.
+ while(!Cy_SysClk_PllLocked(1)) {
+ // Just wait here.
+ }
+ }
+#endif
+}
+
+#endif // DEVICE_SLEEP
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/spi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,545 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "mbed_debug.h"
+#include "PeripheralPins.h"
+#include "pinmap.h"
+#include "spi_api.h"
+#include "psoc6_utils.h"
+
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+#include "drivers/peripheral/gpio/cy_gpio.h"
+#include "drivers/peripheral/scb/cy_scb_spi.h"
+#include "drivers/peripheral/sysint/cy_sysint.h"
+
+#define SPI_DEFAULT_SPEED 100000
+#define NUM_SPI_PORTS 8
+#define SPI_DEFAULT_IRQ_PRIORITY 3
+#define SPI_OVERSAMPLE 4 /* 4..16 */
+// Default timeout in milliseconds.
+#define SPI_DEFAULT_TIMEOUT 1000
+
+#define PENDING_NONE 0
+#define PENDING_RX 1
+#define PENDING_TX 2
+#define PENDING_TX_RX 3
+
+
+
+static const cy_stc_scb_spi_config_t default_spi_config = {
+ .spiMode = CY_SCB_SPI_MASTER,
+ .subMode = CY_SCB_SPI_MOTOROLA,
+ .sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
+ .oversample = SPI_OVERSAMPLE,
+ .rxDataWidth = 8,
+ .txDataWidth = 8,
+ .enableMsbFirst = true,
+ .enableFreeRunSclk = false,
+ .enableInputFilter = false,
+ .enableMisoLateSample = false,
+ .enableTransferSeperation = false,
+ .enableWakeFromSleep = false,
+ .ssPolarity = CY_SCB_SPI_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 0,
+ .rxFifoIntEnableMask = 0,
+ .txFifoTriggerLevel = 0,
+ .txFifoIntEnableMask = 0,
+ .masterSlaveIntEnableMask = 0
+};
+
+
+
+typedef struct spi_s spi_obj_t;
+
+#if DEVICE_SPI_ASYNCH
+#define OBJ_P(in) (&(in->spi))
+#else
+#define OBJ_P(in) (in)
+#endif
+
+
+#if DEVICE_SPI_ASYNCH
+
+static IRQn_Type spi_irq_allocate_channel(spi_obj_t *obj)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ obj->cm0p_irq_src = scb_0_interrupt_IRQn + obj->spi_id;
+ return cy_m0_nvic_allocate_channel(CY_SERIAL_IRQN_ID + obj->spi_id);
+#else
+ return (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + obj->spi_id);
+#endif // M0
+}
+
+static void spi_irq_release_channel(IRQn_Type channel, uint32_t spi_id)
+{
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_m0_nvic_release_channel(channel, CY_SERIAL_IRQN_ID + spi_id);
+#endif //M0
+}
+
+static int spi_irq_setup_channel(spi_obj_t *obj)
+{
+ cy_stc_sysint_t irq_config;
+
+ if (obj->irqn == unconnected_IRQn) {
+ IRQn_Type irqn = spi_irq_allocate_channel(obj);
+ if (irqn < 0) {
+ return (-1);
+ }
+ // Configure NVIC
+ irq_config.intrPriority = SPI_DEFAULT_IRQ_PRIORITY;
+ irq_config.intrSrc = irqn;
+#if defined (TARGET_MCU_PSOC6_M0)
+ irq_config.cm0pSrc = obj->cm0p_irq_src;
+#endif
+ if (Cy_SysInt_Init(&irq_config, (cy_israddress)(obj->handler)) != CY_SYSINT_SUCCESS) {
+ return(-1);
+ }
+
+ obj->irqn = irqn;
+ NVIC_EnableIRQ(irqn);
+ }
+ return 0;
+}
+
+#endif // DEVICE_SPI_ASYNCH
+
+static int allocate_divider(spi_obj_t *obj)
+{
+ if (obj->div_num == CY_INVALID_DIVIDER) {
+ obj->div_type = CY_SYSCLK_DIV_16_BIT;
+ obj->div_num = cy_clk_allocate_divider(CY_SYSCLK_DIV_16_BIT);
+ }
+ return (obj->div_num == CY_INVALID_DIVIDER)? -1 : 0;
+}
+
+
+/*
+ * Initializes spi clock for the required speed
+ */
+static cy_en_sysclk_status_t spi_init_clock(spi_obj_t *obj, uint32_t frequency)
+{
+ cy_en_sysclk_status_t status = CY_SYSCLK_INVALID_STATE;
+ uint32_t div_value;
+
+ if (obj->div_num == CY_INVALID_DIVIDER) {
+ if (allocate_divider(obj) < 0) {
+ error("spi: cannot allocate clock divider.");
+ return CY_SYSCLK_INVALID_STATE;
+ }
+ }
+
+ // Set up proper frequency; round up the divider so the frequency is not higher than specified.
+ div_value = (CY_CLK_PERICLK_FREQ_HZ + frequency *(SPI_OVERSAMPLE - 1)) / frequency / SPI_OVERSAMPLE;
+ obj->clk_frequency = CY_CLK_PERICLK_FREQ_HZ / div_value / SPI_OVERSAMPLE;
+ Cy_SysClk_PeriphDisableDivider(obj->div_type, obj->div_num);
+ if (Cy_SysClk_PeriphSetDivider(obj->div_type, obj->div_num, div_value) != CY_SYSCLK_SUCCESS) {
+ obj->div_num = CY_INVALID_DIVIDER;
+ }
+ Cy_SysClk_PeriphEnableDivider(obj->div_type, obj->div_num);
+
+ if (obj->div_num != CY_INVALID_DIVIDER) {
+ status = Cy_SysClk_PeriphAssignDivider(obj->clock, obj->div_type, obj->div_num);
+ if (status != CY_SYSCLK_SUCCESS) {
+ error("spi: cannot assign clock divider.");
+ return status;
+ }
+ }
+ return CY_SYSCLK_SUCCESS;
+}
+
+/*
+ * Initializes i/o pins for spi.
+ */
+static void spi_init_pins(spi_obj_t *obj)
+{
+ if (cy_reserve_io_pin(obj->pin_sclk) ||
+ cy_reserve_io_pin(obj->pin_mosi) ||
+ cy_reserve_io_pin(obj->pin_miso) ||
+ cy_reserve_io_pin(obj->pin_ssel)) {
+ error("SPI pin reservation conflict.");
+ }
+ pin_function(obj->pin_sclk, pinmap_function(obj->pin_sclk, PinMap_SPI_SCLK));
+ pin_function(obj->pin_mosi, pinmap_function(obj->pin_mosi, PinMap_SPI_MOSI));
+ pin_function(obj->pin_miso, pinmap_function(obj->pin_miso, PinMap_SPI_MISO));
+ pin_function(obj->pin_ssel, pinmap_function(obj->pin_ssel, PinMap_SPI_SSEL));
+ // Pin configuration in PinMap defaults to Master mode; revert for Slave.
+ if (obj->ms_mode == CY_SCB_SPI_SLAVE) {
+ pin_mode(obj->pin_sclk, PullNone);
+ pin_mode(obj->pin_mosi, PullNone);
+ pin_mode(obj->pin_miso, PushPull);
+ pin_mode(obj->pin_ssel, PullNone);
+ }
+}
+
+/*
+ * Initializes and enables SPI/SCB.
+ */
+static void spi_init_peripheral(spi_obj_t *obj)
+{
+ cy_stc_scb_spi_config_t spi_config = default_spi_config;
+ spi_config.spiMode = obj->ms_mode;
+ spi_config.sclkMode = obj->clk_mode;
+ spi_config.rxDataWidth = obj->data_bits;
+ spi_config.txDataWidth = obj->data_bits;
+ Cy_SCB_SPI_Init(obj->base, &spi_config, &obj->context);
+ Cy_SCB_SPI_Enable(obj->base);
+}
+
+
+/* Callback function to handle into and out of deep sleep state transitions.
+ *
+ */
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+static cy_en_syspm_status_t spi_pm_callback(cy_stc_syspm_callback_params_t *callback_params)
+{
+ cy_stc_syspm_callback_params_t params = *callback_params;
+ spi_obj_t *obj = (spi_obj_t *)params.context;
+ params.context = &obj->context;
+
+ return Cy_SCB_SPI_DeepSleepCallback(¶ms);
+}
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+
+
+void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ uint32_t spi = (uint32_t)NC;
+ en_clk_dst_t clock;
+
+ if (mosi != NC) {
+ spi = pinmap_merge(spi, pinmap_peripheral(mosi, PinMap_SPI_MOSI));
+ clock = CY_PIN_CLOCK(pinmap_function(mosi, PinMap_SPI_MOSI));
+ }
+ if (miso != NC) {
+ spi = pinmap_merge(spi, pinmap_peripheral(miso, PinMap_SPI_MISO));
+ clock = CY_PIN_CLOCK(pinmap_function(miso, PinMap_SPI_MISO));
+ }
+ if (sclk != NC) {
+ spi = pinmap_merge(spi, pinmap_peripheral(sclk, PinMap_SPI_SCLK));
+ clock = CY_PIN_CLOCK(pinmap_function(sclk, PinMap_SPI_SCLK));
+ }
+ if (ssel != NC) {
+ spi = pinmap_merge(spi, pinmap_peripheral(ssel, PinMap_SPI_SSEL));
+ clock = CY_PIN_CLOCK(pinmap_function(ssel, PinMap_SPI_SSEL));
+ }
+
+ if (spi != (uint32_t)NC) {
+ obj->base = (CySCB_Type*)spi;
+ obj->spi_id = ((SPIName)spi - SPI_0) / (SPI_1 - SPI_0);
+ obj->pin_mosi = mosi;
+ obj->pin_miso = miso;
+ obj->pin_sclk = sclk;
+ obj->pin_ssel = ssel;
+ obj->data_bits = 8;
+ obj->clock = clock;
+ obj->div_num = CY_INVALID_DIVIDER;
+ obj->ms_mode = CY_SCB_SPI_MASTER;
+#if DEVICE_SPI_ASYNCH
+ obj->pending = PENDING_NONE;
+ obj->events = 0;
+ obj->tx_buffer = NULL;
+ obj->tx_buffer_size = 0;
+ obj->rx_buffer = NULL;
+ obj->rx_buffer_size = 0;
+#endif // DEVICE_SPI_ASYNCH
+ spi_init_clock(obj, SPI_DEFAULT_SPEED);
+ spi_init_pins(obj);
+ spi_init_peripheral(obj);
+#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ obj->pm_callback_handler.callback = spi_pm_callback;
+ obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP;
+ obj->pm_callback_handler.skipMode = 0;
+ obj->pm_callback_handler.callbackParams = &obj->pm_callback_params;
+ obj->pm_callback_params.base = obj->base;
+ obj->pm_callback_params.context = obj;
+ if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) {
+ error("PM callback registration failed!");
+ }
+#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
+ } else {
+ error("Serial pinout mismatch. Requested pins Rx and Tx can't be used for the same Serial communication.");
+ }
+}
+
+void spi_format(spi_t *obj_in, int bits, int mode, int slave)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ cy_en_scb_spi_mode_t new_mode = slave? CY_SCB_SPI_SLAVE : CY_SCB_SPI_MASTER;
+ if ((bits < 4) || (bits > 16)) return;
+ Cy_SCB_SPI_Disable(obj->base, &obj->context);
+ obj->data_bits = bits;
+ obj->clk_mode = (cy_en_scb_spi_sclk_mode_t)(mode & 0x3);
+ if (obj->ms_mode != new_mode) {
+ obj->ms_mode = new_mode;
+ spi_init_pins(obj);
+ }
+ spi_init_peripheral(obj);
+}
+
+void spi_frequency(spi_t *obj_in, int hz)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ Cy_SCB_SPI_Disable(obj->base, &obj->context);
+ spi_init_clock(obj, hz);
+ Cy_SCB_SPI_Enable(obj->base);
+}
+
+int spi_master_write(spi_t *obj_in, int value)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+
+ if (obj->ms_mode == CY_SCB_SPI_MASTER) {
+ while (spi_busy(obj_in)) {
+ // wait for the device to become ready
+ }
+ Cy_SCB_SPI_Write(obj->base, value);
+ while (!Cy_SCB_SPI_IsTxComplete(obj->base)) {
+ // wait for the transmission to complete
+ }
+ return Cy_SCB_SPI_Read(obj->base);
+ } else {
+ return (int)CY_SCB_SPI_RX_NO_DATA;
+ }
+}
+
+int spi_master_block_write(spi_t *obj_in, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ int trans_length = 0;
+ int rx_count = 0;
+ int tx_count = 0;
+ uint8_t tx_byte = (uint8_t)write_fill;
+
+ if (obj->ms_mode != CY_SCB_SPI_MASTER) {
+ return 0;
+ }
+
+ // Make sure no leftovers from previous transactions.
+ Cy_SCB_SPI_ClearRxFifo(obj->base);
+ // Calculate transaction length,
+ trans_length = (tx_length > rx_length)? tx_length : rx_length;
+ // get first byte to transmit.
+ if (tx_count < tx_length) {
+ tx_byte = *tx_buffer++;
+ }
+ // Send required number of bytes.
+ while (tx_count < trans_length) {
+ if (Cy_SCB_SPI_Write(obj->base, tx_byte)) {
+ ++tx_count;
+ // Get next byte to transfer.
+ if (tx_count < tx_length) {
+ tx_byte = *tx_buffer++;
+ } else {
+ tx_byte = (uint8_t)write_fill;
+ }
+ }
+ // If we have bytes to receive check the rx fifo.
+ if (rx_count < rx_length) {
+ if (Cy_SCB_SPI_GetNumInRxFifo(obj->base) > 0) {
+ *rx_buffer++ = (char)Cy_SCB_SPI_Read(obj->base);
+ ++rx_count;
+ }
+ }
+ }
+ // Wait for tx fifo to empty while reading received bytes.
+ while (!Cy_SCB_SPI_IsTxComplete(obj->base)) {
+ if ((rx_count < rx_length) && (Cy_SCB_SPI_GetNumInRxFifo(obj->base) > 0)) {
+ *rx_buffer++ = (char)Cy_SCB_SPI_Read(obj->base);
+ ++rx_count;
+ }
+ }
+ // Read any ramaining bytes from the fifo.
+ while (rx_count < rx_length) {
+ *rx_buffer++ = (char)Cy_SCB_SPI_Read(obj->base);
+ }
+ // Clean up if we have read less bytes than available.
+ Cy_SCB_SPI_ClearRxFifo(obj->base);
+ return trans_length;
+}
+
+int spi_slave_receive(spi_t *obj_in)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ if (obj->ms_mode == CY_SCB_SPI_SLAVE) {
+ return Cy_SCB_SPI_GetNumInRxFifo(obj->base);
+ } else {
+ return 0;
+ }
+}
+
+int spi_slave_read(spi_t *obj_in)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+
+ if (obj->ms_mode == CY_SCB_SPI_SLAVE) {
+ while (Cy_SCB_SPI_GetNumInRxFifo(obj->base) == 0) {
+ // Wait for data.
+ }
+ return Cy_SCB_SPI_GetNumInRxFifo(obj->base);
+ } else {
+ return (int)CY_SCB_SPI_RX_NO_DATA;
+ }
+}
+
+void spi_slave_write(spi_t *obj_in, int value)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+
+ if (obj->ms_mode == CY_SCB_SPI_SLAVE) {
+ while ((Cy_SCB_SPI_GetTxFifoStatus(obj->base) & CY_SCB_SPI_TX_NOT_FULL) == 0) {
+ // Wait for a place available in a fifo.
+ }
+ Cy_SCB_SPI_Write(obj->base, value);
+ }
+}
+
+int spi_busy(spi_t *obj)
+{
+ return !Cy_SCB_SPI_IsTxComplete(OBJ_P(obj)->base);
+}
+
+uint8_t spi_get_module(spi_t *obj_in)
+{
+ return (uint8_t) OBJ_P(obj_in)->spi_id;
+}
+
+#if DEVICE_SPI_ASYNCH
+
+void spi_master_transfer(spi_t *obj_in,
+ const void *tx,
+ size_t tx_length,
+ void *rx,
+ size_t rx_length,
+ uint8_t bit_width,
+ uint32_t handler,
+ uint32_t event,
+ DMAUsage hint)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+
+ (void)hint; // At the moment we do not support DAM transfers, so this parameter gets ignored.
+
+ if (obj->pending != PENDING_NONE) {
+ return;
+ }
+
+ // Validate buffer parameters.
+ if (((obj->data_bits <= 8) && (bit_width != 8)) || ((obj->data_bits > 8) && (bit_width != 16))) {
+ error("spi: buffer configurations does not match device configuration");
+ return;
+ }
+
+ obj->events = event;
+ obj->handler = handler;
+ if (spi_irq_setup_channel(obj) < 0) {
+ return;
+ }
+
+ if (tx_length > rx_length) {
+ if (rx_length > 0) {
+ // I) write + read, II) write only
+ obj->pending = PENDING_TX_RX;
+ obj->rx_buffer = NULL;
+ obj->tx_buffer = (bit_width == 8)?
+ (void*)(((uint8_t*)tx) + rx_length) :
+ (void*)(((uint16_t*)tx) + rx_length);
+ obj->tx_buffer_size = tx_length - rx_length;
+ Cy_SCB_SPI_Transfer(obj->base, (void*)tx, rx, rx_length, &obj->context);
+ } else {
+ // I) write only.
+ obj->pending = PENDING_TX;
+ obj->rx_buffer = NULL;
+ obj->tx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, (void*)tx, NULL, tx_length, &obj->context);
+ }
+ } else if (rx_length > tx_length) {
+ if (tx_length > 0) {
+ // I) write + read, II) read only
+ obj->pending = PENDING_TX_RX;
+ obj->rx_buffer = (bit_width == 8)?
+ (void*)(((uint8_t*)rx) + tx_length) :
+ (void*)(((uint16_t*)rx) + tx_length);
+ obj->rx_buffer_size = rx_length - tx_length;
+ obj->tx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, (void*)tx, rx, tx_length, &obj->context);
+ } else {
+ // I) read only.
+ obj->pending = PENDING_RX;
+ obj->rx_buffer = NULL;
+ obj->tx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, NULL, rx, rx_length, &obj->context);
+ }
+ } else {
+ // Rx and Tx of the same size
+ // I) write + read.
+ obj->pending = PENDING_TX_RX;
+ obj->rx_buffer = NULL;
+ obj->tx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, (void*)tx, rx, tx_length, &obj->context);
+ }
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj_in)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ uint32_t event = 0;
+ void *buf;
+ // Process actual interrupt.
+ Cy_SCB_SPI_Interrupt(obj->base, &obj->context);
+ if (obj->context.status & CY_SCB_SPI_TRANSFER_OVERFLOW) {
+ event = SPI_EVENT_RX_OVERFLOW;
+ } else if (obj->context.status & (CY_SCB_SPI_SLAVE_TRANSFER_ERR | CY_SCB_SPI_TRANSFER_OVERFLOW)) {
+ event = SPI_EVENT_ERROR;
+ } else if (0 == (obj->context.status & CY_SCB_SPI_TRANSFER_ACTIVE)) {
+ // Check to see if the second transfer phase needs to be started.
+ MBED_ASSERT(!(obj->tx_buffer && obj->rx_buffer));
+ if (obj->tx_buffer) {
+ obj->pending = PENDING_TX;
+ buf = obj->tx_buffer;
+ obj->tx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, buf, NULL, obj->tx_buffer_size, &obj->context);
+ } else if (obj->rx_buffer) {
+ obj->pending = PENDING_RX;
+ buf = obj->rx_buffer;
+ obj->rx_buffer = NULL;
+ Cy_SCB_SPI_Transfer(obj->base, NULL, buf, obj->rx_buffer_size, &obj->context);
+ } else {
+ event = SPI_EVENT_COMPLETE;
+ obj->pending = PENDING_NONE;
+ }
+ }
+ return event & obj->events;
+}
+
+uint8_t spi_active(spi_t *obj_in)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ return (obj->pending != PENDING_NONE);
+}
+
+void spi_abort_asynch(spi_t *obj_in)
+{
+ spi_obj_t *obj = OBJ_P(obj_in);
+ Cy_SCB_SPI_AbortTransfer(obj->base, &obj->context);
+}
+
+#endif // DEVICE_ASYNCH
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,215 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (c) 2017-2018 Future Electronics
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+#include <limits.h>
+#include "device.h"
+#include "PeripheralNames.h"
+#include "us_ticker_api.h"
+#include "mbed_error.h"
+#include "psoc6_utils.h"
+
+#include "drivers/peripheral/sysint/cy_sysint.h"
+#include "drivers/peripheral/sysclk/cy_sysclk.h"
+#include "drivers/peripheral/tcpwm/cy_tcpwm_counter.h"
+#include "drivers/peripheral/syspm/cy_syspm.h"
+
+/** Each CPU core in PSoC6 needs its own usec timer.
+ ** Although each of TCPWM timers have two compare registers,
+ ** it has only one interrupt line, so we need to allocate
+ ** two TCPWM counters for the purpose of us_ticker
+ **/
+
+
+#if defined(TARGET_MCU_PSOC6_M0)
+
+#define TICKER_COUNTER_UNIT TCPWM0
+#define TICKER_COUNTER_NUM 0
+#define TICKER_COUNTER_INTERRUPT_SOURCE tcpwm_0_interrupts_0_IRQn
+#define TICKER_COUNTER_NVIC_IRQN CY_M0_CORE_IRQ_CHANNEL_US_TICKER
+#define TICKER_COUNTER_INTERRUPT_PRIORITY 3
+#define TICKER_CLOCK_DIVIDER_NUM 0
+
+#elif defined(TARGET_MCU_PSOC6_M4)
+
+#define TICKER_COUNTER_UNIT TCPWM0
+#define TICKER_COUNTER_NUM 1
+#define TICKER_COUNTER_INTERRUPT_SOURCE tcpwm_0_interrupts_1_IRQn
+#define TICKER_COUNTER_NVIC_IRQN TICKER_COUNTER_INTERRUPT_SOURCE
+#define TICKER_COUNTER_INTERRUPT_PRIORITY 6
+#define TICKER_CLOCK_DIVIDER_NUM 1
+
+#else
+#error "Unknown MCU type."
+#endif
+
+
+static const ticker_info_t us_ticker_info = {
+ .frequency = 1000000UL,
+ .bits = 32,
+};
+
+static const cy_stc_sysint_t us_ticker_sysint_cfg = {
+ .intrSrc = TICKER_COUNTER_NVIC_IRQN,
+#if defined(TARGET_MCU_PSOC6_M0)
+ .cm0pSrc = TICKER_COUNTER_INTERRUPT_SOURCE,
+#endif
+ .intrPriority = TICKER_COUNTER_INTERRUPT_PRIORITY
+};
+
+static int us_ticker_inited = 0;
+
+static const cy_stc_tcpwm_counter_config_t cy_counter_config = {
+ .period = 0xFFFFFFFFUL,
+ .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1,
+ .runMode = CY_TCPWM_COUNTER_CONTINUOUS,
+ .countDirection = CY_TCPWM_COUNTER_COUNT_UP,
+ .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE,
+ .enableCompareSwap = false,
+ .interruptSources = CY_TCPWM_INT_ON_CC,
+ .countInputMode = CY_TCPWM_INPUT_LEVEL,
+ .countInput = CY_TCPWM_INPUT_1
+};
+
+// PM callback to be executed when exiting deep sleep.
+static cy_en_syspm_status_t ticker_pm_callback(cy_stc_syspm_callback_params_t *callbackParams);
+
+static cy_stc_syspm_callback_params_t ticker_pm_callback_params = {
+ .base = TICKER_COUNTER_UNIT
+};
+
+static cy_stc_syspm_callback_t ticker_pm_callback_handler = {
+ .callback = ticker_pm_callback,
+ .type = CY_SYSPM_DEEPSLEEP,
+ .skipMode = CY_SYSPM_SKIP_CHECK_READY | CY_SYSPM_SKIP_CHECK_FAIL | CY_SYSPM_SKIP_BEFORE_TRANSITION,
+ .callbackParams = &ticker_pm_callback_params
+};
+
+
+/*
+ * Callback handler to restart the timer after deep sleep.
+ */
+static cy_en_syspm_status_t ticker_pm_callback(cy_stc_syspm_callback_params_t *params)
+{
+ if (params->mode == CY_SYSPM_AFTER_TRANSITION) {
+ Cy_TCPWM_Counter_Enable(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM);
+ Cy_TCPWM_TriggerStart(TICKER_COUNTER_UNIT, 1UL << TICKER_COUNTER_NUM);
+ }
+ return CY_SYSPM_SUCCESS;
+}
+
+/*
+ * Interrupt handler.
+ */
+static void local_irq_handler(void)
+{
+ us_ticker_clear_interrupt();
+ us_ticker_disable_interrupt();
+ us_ticker_irq_handler();
+}
+
+
+void us_ticker_init(void)
+{
+ us_ticker_disable_interrupt();
+ us_ticker_clear_interrupt();
+
+ if (us_ticker_inited)
+ return;
+
+ us_ticker_inited = 1;
+
+ // Configure the clock, us_ticker 1 MHz from PCLK 50 MHz
+ Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0 + TICKER_COUNTER_NUM, CY_SYSCLK_DIV_8_BIT, TICKER_CLOCK_DIVIDER_NUM);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, TICKER_CLOCK_DIVIDER_NUM, (CY_CLK_PERICLK_FREQ_HZ / 1000000UL) - 1);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, TICKER_CLOCK_DIVIDER_NUM);
+
+ /*
+ Configure the counter
+ */
+
+ Cy_TCPWM_Counter_Init(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM, &cy_counter_config);
+ Cy_TCPWM_Counter_Enable(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM);
+ if (!Cy_SysPm_RegisterCallback(&ticker_pm_callback_handler)) {
+ error("PM callback registration failed!");
+ }
+ Cy_TCPWM_TriggerStart(TICKER_COUNTER_UNIT, 1UL << TICKER_COUNTER_NUM);
+
+#if defined (TARGET_MCU_PSOC6_M0)
+ if (cy_m0_nvic_reserve_channel(TICKER_COUNTER_NVIC_IRQN, CY_US_TICKER_IRQN_ID) == (IRQn_Type)(-1)) {
+ error("Microsecond ticker NVIC channel reservation conflict.");
+ }
+#endif //
+
+ Cy_SysInt_Init(&us_ticker_sysint_cfg, local_irq_handler);
+}
+
+void us_ticker_free(void)
+{
+ us_ticker_disable_interrupt();
+ Cy_TCPWM_Counter_Disable(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM);
+ Cy_SysPm_UnregisterCallback(&ticker_pm_callback_handler);
+#if defined (TARGET_MCU_PSOC6_M0)
+ cy_m0_nvic_release_channel(TICKER_COUNTER_NVIC_IRQN, CY_US_TICKER_IRQN_ID);
+#endif //
+ us_ticker_inited = 0;
+}
+
+uint32_t us_ticker_read(void)
+{
+ if (!us_ticker_inited)
+ us_ticker_init();
+ return Cy_TCPWM_Counter_GetCounter(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t current_ts = Cy_TCPWM_Counter_GetCounter(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM);
+ uint32_t delta = timestamp - current_ts;
+
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ // Set new output compare value
+ if ((delta < 2) || (delta > (uint32_t)(-3))) {
+ timestamp = current_ts + 2;
+ }
+ Cy_TCPWM_Counter_SetCompare0(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM, timestamp);
+ // Enable int
+ NVIC_EnableIRQ(TICKER_COUNTER_NVIC_IRQN);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ NVIC_DisableIRQ(TICKER_COUNTER_NVIC_IRQN);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ Cy_TCPWM_ClearInterrupt(TICKER_COUNTER_UNIT, TICKER_COUNTER_NUM, CY_TCPWM_INT_ON_CC);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_EnableIRQ(TICKER_COUNTER_NVIC_IRQN);
+ NVIC_SetPendingIRQ(TICKER_COUNTER_NVIC_IRQN);
+}
+
+const ticker_info_t* us_ticker_get_info(void)
+{
+ return &us_ticker_info;
+}
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device/TOOLCHAIN_GCC_ARM/MK20D5.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device/TOOLCHAIN_GCC_ARM/MK20D5.ld Thu Nov 08 11:46:34 2018 +0000
@@ -46,13 +46,13 @@
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH_PROTECTION
.text :
@@ -101,13 +101,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -115,14 +115,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -158,3 +158,8 @@
{
NVIC_SetPendingIRQ(PIT_TICKER_IRQ);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld Thu Nov 08 11:46:34 2018 +0000
@@ -47,13 +47,13 @@
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
*(.text.SystemInit)
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH_PROTECTION
.text :
@@ -102,13 +102,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -116,14 +116,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -81,3 +81,8 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device/TOOLCHAIN_GCC_ARM/MKL05Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device/TOOLCHAIN_GCC_ARM/MKL05Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -43,7 +43,7 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.text :
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,14 +106,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_ARM/MKL25Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_ARM/MKL25Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -46,13 +46,13 @@
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH_PROTECTION
.text :
@@ -101,13 +101,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -115,14 +115,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -35,22 +35,22 @@
.interrupts :
{
__vector_table = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.vectortable)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.cfmprotect :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_cfmprotrom
/* The program code and other data goes into Flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -62,7 +62,7 @@
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
_etext = .; /* define a global symbols at end of code */
} > m_text
@@ -141,20 +141,20 @@
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT(___ROM_AT)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__sinit__ = .;
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
- . = ALIGN(4);
+ . = ALIGN(8);
_edata = .; /* define a global symbol at data end */
} > m_data
___data_size = _edata - _sdata;
/* Uninitialized data section */
- . = ALIGN(4);
+ . = ALIGN(8);
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
@@ -164,7 +164,7 @@
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__END_BSS = .;
PROVIDE ( __bss_end__ = __END_BSS );
} > m_data
@@ -184,13 +184,13 @@
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
- . = ALIGN(4);
+ . = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
__heap_addr = .;
. = . + __heap_size;
. = . + __stack_size;
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_data
.ARM.attributes 0 : { *(.ARM.attributes) }
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -91,13 +91,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -105,14 +105,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_IAR/MKL25Z4.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_IAR/MKL25Z4.icf Thu Nov 08 11:46:34 2018 +0000 @@ -11,9 +11,8 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0; define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; /*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x1000; +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/ define symbol __region_RAM2_start__ = 0x20000000;
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/MKL26Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_GCC_ARM/MKL26Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -46,13 +46,13 @@
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH_PROTECTION
.text :
@@ -101,13 +101,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -115,14 +115,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_GCC_ARM/MKL46Z4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device/TOOLCHAIN_GCC_ARM/MKL46Z4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -46,13 +46,13 @@
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH_PROTECTION
.text :
@@ -101,13 +101,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -115,14 +115,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -223,3 +223,8 @@
#endif
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,12 +17,37 @@
#define CRC16
#include "crc.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -34,13 +59,6 @@
gpio_init_in(&gpio, PTA4);
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
// Provide ethernet devices with a semi-unique MAC address from the UUID
void mbed_mac_address(char *mac)
{
@@ -55,7 +73,7 @@
// generate three CRC16's using different slices of the UUID
MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
- MAC[1] = crcSlow((const uint8_t *)UID, 12);
+ MAC[1] = crcSlow((const uint8_t *)UID, 12);
MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
// The network stack expects an array of 6 bytes
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld Thu Nov 08 11:46:34 2018 +0000
@@ -53,10 +53,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x6000;
#if !defined(MBED_APP_START)
@@ -88,22 +84,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -113,7 +109,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -191,12 +187,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -205,13 +201,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -223,13 +219,13 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data_2
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/trng_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/trng_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,6 +22,8 @@
* Reference: "K66 Sub-Family Reference Manual, Rev. 2", chapter 38
*/
+#if defined(DEVICE_TRNG)
+
#include <stdlib.h>
#include "cmsis.h"
#include "fsl_common.h"
@@ -48,13 +50,14 @@
*/
static void trng_get_byte(unsigned char *byte)
{
+ *byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
for( bit = 0; bit < 8; bit++ )
{
- while( ( RNG->SR & RNG_SR_OREG_LVL_MASK ) == 0 );
- *byte |= ( RNG->OR & 1 ) << bit;
+ while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 );
+ *byte |= (RNG->OR & 1) << bit;
}
}
@@ -62,7 +65,6 @@
{
(void)obj;
size_t i;
- int ret;
/* Set "Interrupt Mask", "High Assurance" and "Go",
* unset "Clear interrupt" and "Sleep" */
@@ -81,3 +83,5 @@
return 0;
}
+
+#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,8 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -106,6 +106,10 @@
SPI_2 = 2,
} SPIName;
+typedef enum {
+ QSPI_0 = 0
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -265,3 +265,29 @@
{NC , NC , 0}
};
+
+const PinMap PinMap_QSPI_DATA[] = {
+ {PTE0, QSPI_0, 5},
+ {PTE2, QSPI_0, 5},
+ {PTE3, QSPI_0, 5},
+ {PTE4, QSPI_0, 5},
+ {PTE6, QSPI_0, 5},
+ {PTE7, QSPI_0, 5},
+ {PTE8, QSPI_0, 5},
+ {PTE9, QSPI_0, 5},
+ {PTE10, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_QSPI_SCLK[] = {
+ {PTE1, QSPI_0, 5},
+ {PTE7, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_QSPI_SSEL[] = {
+ {PTE5, QSPI_0, 5},
+ {PTE11, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -172,6 +172,20 @@
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+ //SPI Pins configuration
+ SPI_MOSI = PTE2,
+ SPI_MISO = PTE4,
+ SPI_SCK = PTE1,
+ SPI_PERSISTENT_MEM_CS = PTE5,
+
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PTE2,
+ QSPI_FLASH1_IO1 = PTE4,
+ QSPI_FLASH1_IO2 = PTE3,
+ QSPI_FLASH1_IO3 = PTE0,
+ QSPI_FLASH1_SCK = PTE1,
+ QSPI_FLASH1_CSN = PTE5,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/device.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -18,22 +18,9 @@ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H - - - +#include "objects.h" - - - - +#define DEVICE_ID_LENGTH 24 -#define DEVICE_ID_LENGTH 24 - - - - - -#include "objects.h" - #endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,12 +14,37 @@
* limitations under the License.
*/
#include "gpio_api.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -31,16 +56,15 @@
gpio_init_in(&gpio, PTA4);
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
// Set the UART clock source
void serial_clock_init(void)
{
CLOCK_SetLpuartClock(2U);
}
+// Get the QSPI clock frequency
+uint32_t qspi_get_freq(void)
+{
+ return CLOCK_GetFreq(kCLOCK_McgPll0Clk);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/qspi_device.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_MBED_QSPI_DEVICE_H_
+#define _FSL_MBED_QSPI_DEVICE_H_
+
+#include "fsl_qspi.h"
+
+#define FLASH_SIZE 0x00400000U
+#define FLASH_PAGE_SIZE 256U
+
+qspi_flash_config_t single_config = {
+ .flashA1Size = FLASH_SIZE, /* 4MB */
+ .flashA2Size = 0,
+#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+ .flashB1Size = FLASH_SIZE,
+ .flashB2Size = 0,
+#endif
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+ .dataHoldTime = 0,
+#endif
+ .CSHoldTime = 0,
+ .CSSetupTime = 0,
+ .cloumnspace = 0,
+ .dataLearnValue = 0,
+ .endian = kQSPI_64LittleEndian,
+ .enableWordAddress = false
+};
+
+/* Pre-defined LUT definitions */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] =
+ {
+ /* Seq0 : Read */
+ /* CMD: 0x03 - Read, Single pad */
+ /* ADDR: 0x18 - 24bit address, Single pad */
+ /* READ: 0x80 - Read 128 bytes, Single pad */
+ /* JUMP_ON_CS: 0 */
+ [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x03, QSPI_ADDR, QSPI_PAD_1, 0x18),
+ [1] = QSPI_LUT_SEQ(QSPI_READ, QSPI_PAD_1, 0x80, QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0),
+
+ /* Seq1: Page Program */
+ /* CMD: 0x02 - Page Program, Single pad */
+ /* ADDR: 0x18 - 24bit address, Single pad */
+ /* WRITE: 0x80 - Write 128 bytes at one pass, Single pad */
+ [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+ [5] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+ /* Match MISRA rule */
+ [63] = 0
+ };
+
+#endif /* _FSL_MBED_QSPI_DEVICE_H_*/
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,13 +17,18 @@
#include "fsl_smc.h"
#include "fsl_rcm.h"
#include "fsl_pmc.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
//!< this contains the wakeup source
rcm_reset_source_t kinetisResetSource;
// called before main
-void mbed_sdk_init() {
+void mbed_sdk_init()
+{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
// check the power mode source
@@ -36,6 +41,26 @@
BOARD_BootClockRUN();
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -47,13 +72,6 @@
gpio_init_in(&gpio, PTA4);
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
// Set the UART clock source
void serial_clock_init(void)
{
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/MK82F25615.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/MK82F25615.h Thu Nov 08 11:46:34 2018 +0000
@@ -11013,7 +11013,14 @@
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
- __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
+ union { /* offset: 0x8 */
+ __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
+ struct {
+ __IO uint16_t IDATZ; /**< IP data transfer size, offset: 0x8 */
+ __IO uint8_t PAR_EN; /**< IP data transfer size, offset: 0xA */
+ __IO uint8_t SEQID; /**< IP data transfer size, offset: 0xB */
+ } IPCR_ACCESSBIT;
+ };
__IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */
__IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */
__IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/MK82FN256xxx15.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/MK82FN256xxx15.ld Thu Nov 08 11:46:34 2018 +0000
@@ -56,10 +56,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x6000;
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
@@ -84,29 +80,29 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.bootloader_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.BootloaderConfig)) /* Bootloader Configuration Area (BCA) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_bootloader_config
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -116,7 +112,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -194,12 +190,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -208,13 +204,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -227,7 +223,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -236,7 +232,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_qspi.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.qspi"
+#endif
+
+
/*******************************************************************************
* Definitations
******************************************************************************/
@@ -40,17 +50,11 @@
kQSPI_TxError /*!< Transfer error occured. */
};
-#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))
+#define QSPI_AHB_BUFFER_REG(base, index) (((volatile uint32_t *)&((base)->BUF0CR))[(index)])
/*******************************************************************************
* Prototypes
******************************************************************************/
-/*!
-* @brief Get the instance number for QSPI.
-*
-* @param base QSPI base pointer.
-*/
-uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*******************************************************************************
* Variables
@@ -70,7 +74,7 @@
uint32_t instance;
/* Find the instance index from base address mappings. */
- for (instance = 0; instance < FSL_FEATURE_SOC_QuadSPI_COUNT; instance++)
+ for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++)
{
if (s_qspiBases[instance] == base)
{
@@ -78,7 +82,7 @@
}
}
- assert(instance < FSL_FEATURE_SOC_QuadSPI_COUNT);
+ assert(instance < ARRAY_SIZE(s_qspiBases));
return instance;
}
@@ -102,12 +106,21 @@
/* Configure QSPI */
QSPI_Enable(base, false);
+#if !defined (FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Set qspi clock source */
base->SOCCR = config->clockSource;
/* Set the divider of QSPI clock */
base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
- base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
+
+ if (srcClock_Hz % config->baudRate) {
+ /* In case we cannot get the exact baudrate, get the closest lower value */
+ base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate);
+ } else {
+ base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
+ }
+
+#endif /* FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL */
/* Set AHB buffer size and buffer master */
for (i = 0; i < FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++)
@@ -127,8 +140,11 @@
/* Set watermark */
base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK;
base->RBCT |= QuadSPI_RBCT_WMRK(config->rxWatermark - 1);
+
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK;
base->TBCT |= QuadSPI_TBCT_WMRK(config->txWatermark - 1);
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
/* Enable QSPI module */
if (config->enableQspi)
@@ -178,9 +194,11 @@
base->SFB2AD = address;
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_SFACR) || (!FSL_FEATURE_QSPI_HAS_NO_SFACR)
/* Set Word Addressable feature */
val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace);
base->SFACR = val;
+#endif /* FSL_FEATURE_QSPI_HAS_NO_SFACR */
/* Config look up table */
base->LUTKEY = 0x5AF05AF0U;
@@ -192,9 +210,13 @@
base->LUTKEY = 0x5AF05AF0U;
base->LCKCR = 0x1U;
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
/* Config flash timing */
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) |
QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
+#else
+ val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
base->FLSHCR = val;
/* Set flash endianness */
@@ -207,7 +229,7 @@
void QSPI_SoftwareReset(QuadSPI_Type *base)
{
- volatile uint32_t i = 0;
+ uint32_t i = 0;
/* Reset AHB domain and buffer domian */
base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,10 +48,43 @@
/*! @name Driver version */
/*@{*/
-/*! @brief I2C driver version 2.0.1. */
-#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief QSPI driver version 2.0.2. */
+#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
+/*! @brief Macro functions for LUT table */
+#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
+ QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
+
+/*! @brief Macro for QSPI LUT command */
+#define QSPI_CMD (0x1U)
+#define QSPI_ADDR (0x2U)
+#define QSPI_DUMMY (0x3U)
+#define QSPI_MODE (0x4U)
+#define QSPI_MODE2 (0x5U)
+#define QSPI_MODE4 (0x6U)
+#define QSPI_READ (0x7U)
+#define QSPI_WRITE (0x8U)
+#define QSPI_JMP_ON_CS (0x9U)
+#define QSPI_ADDR_DDR (0xAU)
+#define QSPI_MODE_DDR (0xBU)
+#define QSPI_MODE2_DDR (0xCU)
+#define QSPI_MODE4_DDR (0xDU)
+#define QSPI_READ_DDR (0xEU)
+#define QSPI_WRITE_DDR (0xFU)
+#define QSPI_DATA_LEARN (0x10U)
+#define QSPI_CMD_DDR (0x11U)
+#define QSPI_CADDR (0x12U)
+#define QSPI_CADDR_DDR (0x13U)
+#define QSPI_STOP (0x0U)
+
+/*! @brief Macro for QSPI PAD */
+#define QSPI_PAD_1 (0x0U)
+#define QSPI_PAD_2 (0x1U)
+#define QSPI_PAD_4 (0x2U)
+#define QSPI_PAD_8 (0x3U)
+
/*! @brief Status structure of QSPI.*/
enum _status_t
{
@@ -91,15 +128,19 @@
/*! @brief QSPI error flags */
enum _qspi_error_flags
{
- kQSPI_DataLearningFail = QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
+ kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
@@ -108,16 +149,18 @@
kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
- kQSPI_FlagAll = 0x8C83F8D1U /*!< All error flag */
+ kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
};
/*! @brief QSPI state bit */
enum _qspi_flags
{
- kQSPI_DataLearningSamplePoint = QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
+ kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
@@ -135,14 +178,14 @@
kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
- kQSPI_StateAll = 0xEF897FE7U /*!< All flags */
+ kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
};
/*! @brief QSPI interrupt enable */
enum _qspi_interrupt_enable
{
kQSPI_DataLearningFailInterruptEnable =
- QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
+ (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
kQSPI_IllegalInstructionInterruptEnable =
@@ -150,10 +193,14 @@
kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransactionInterruptEnable =
QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSizeInterruptEnable =
QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
@@ -166,15 +213,21 @@
QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinishedInterruptEnable =
QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
- kQSPI_AllInterruptEnable = 0x8C83F8D1U /*!< All error interrupt enable */
+ kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
};
/*! @brief QSPI DMA request flag */
enum _qspi_dma_enable
{
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
+#else
+ kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
};
/*! @brief Phrase shift number for DQS mode. */
@@ -229,7 +282,9 @@
uint32_t flashB2Size; /*!< Flash B2 size */
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
uint32_t dataHoldTime; /*!< Data line hold time. */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
uint32_t CSHoldTime; /*!< CS line hold time */
uint32_t CSSetupTime; /*!< CS line setup time*/
uint32_t cloumnspace; /*!< Column space size */
@@ -258,6 +313,13 @@
*/
/*!
+* @brief Get the instance number for QSPI.
+*
+* @param base QSPI base pointer.
+*/
+uint32_t QSPI_GetInstance(QuadSPI_Type *base);
+
+/*!
* @brief Initializes the QSPI module and internal state.
*
* This function enables the clock for QSPI and also configures the QSPI with the
@@ -462,9 +524,9 @@
* @param base Pointer to QuadSPI Type.
* @param size IP command size.
*/
-static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
+static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint16_t size)
{
- base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_IDATSZ_MASK)) | QuadSPI_IPCR_IDATSZ(size));
+ base->IPCR_ACCESSBIT.IDATZ = size;
}
/*! @brief Executes IP commands located in LUT table.
@@ -546,6 +608,24 @@
base->SPTRCLR = seq;
}
+/*!
+ * @brief Enable or disable DDR mode.
+ *
+ * @param base QSPI base pointer
+ * @param eanble True means enable DDR mode, false means disable DDR mode.
+ */
+static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
+ }
+ else
+ {
+ base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
+ }
+}
+
/*!@ brief Set the RX buffer readout area.
*
* This function can set the RX buffer readout, from AHB bus or IP Bus.
@@ -576,7 +656,10 @@
/*!
* @brief Receives a buffer of data bytes using a blocking method.
- * @note This function blocks via polling until all bytes have been sent.
+ * @note This function blocks via polling until all bytes have been sent. Users shall notice that
+ * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
+ * For flash contents read, please use AHB bus read, this is much more efficiency.
+ *
* @param base QSPI base pointer
* @param buffer The data bytes to send
* @param size The number of data bytes to receive
@@ -616,7 +699,10 @@
* @brief Reads data from the QSPI receive buffer in polling way.
*
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
- * function and can return only when finished. This function uses polling methods.
+ * function and can return only when finished. This function uses polling methods. Users shall notice that
+ * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
+ * For flash contents read, please use AHB bus read, this is much more efficiency.
+ *
* @param base Pointer to QuadSPI Type.
* @param xfer QSPI transfer structure.
*/
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,16 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+ PIT_StopTimer(PIT, kPIT_Chnl_3);
+ PIT_StopTimer(PIT, kPIT_Chnl_2);
+ PIT_StopTimer(PIT, kPIT_Chnl_1);
+ PIT_StopTimer(PIT, kPIT_Chnl_0);
+
+ PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+ NVIC_DisableIRQ(PIT3_IRQn);
+
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -15,22 +15,40 @@
*/
#include "gpio_api.h"
#include "pinmap.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
/* Set the TPM clock source to be IRC48M, do not change as TPM2 is used for the usticker */
CLOCK_SetTpmClock(1U);
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -79,22 +79,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -104,7 +104,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -192,12 +192,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -206,13 +206,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -225,7 +225,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -234,7 +234,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -152,3 +152,8 @@
NVIC_SetPendingIRQ(TPM2_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -15,22 +15,40 @@
*/
#include "gpio_api.h"
#include "pinmap.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
/* Set the TPM clock source to be IRC48M, do not change as TPM2 is used for the usticker */
CLOCK_SetTpmClock(1U);
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_GCC_ARM/MKL43Z256xxx4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_GCC_ARM/MKL43Z256xxx4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -54,10 +54,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x2800;
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
@@ -80,22 +76,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -105,7 +101,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -193,12 +189,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -207,13 +203,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -226,7 +222,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -235,7 +231,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -152,3 +152,8 @@
NVIC_SetPendingIRQ(TPM2_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -95,6 +95,10 @@
DAC_0 = 0
} DACName;
+typedef enum {
+ QSPI_0 = 0
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -158,3 +158,28 @@
{NC , NC , 0}
};
+const PinMap PinMap_QSPI_DATA[] = {
+ {PTE0, QSPI_0, 5},
+ {PTE2, QSPI_0, 5},
+ {PTE3, QSPI_0, 5},
+ {PTE4, QSPI_0, 5},
+ {PTE6, QSPI_0, 5},
+ {PTE7, QSPI_0, 5},
+ {PTE8, QSPI_0, 5},
+ {PTE9, QSPI_0, 5},
+ {PTE10, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_QSPI_SCLK[] = {
+ {PTE1, QSPI_0, 5},
+ {PTE7, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_QSPI_SSEL[] = {
+ {PTE5, QSPI_0, 5},
+ {PTE11, QSPI_0, 5},
+ {NC , NC , 0}
+};
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -156,6 +156,14 @@
A4 = PTB1,
A5 = PTB0,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PTE2,
+ QSPI_FLASH1_IO1 = PTE4,
+ QSPI_FLASH1_IO2 = PTE3,
+ QSPI_FLASH1_IO3 = PTE0,
+ QSPI_FLASH1_SCK = PTE1,
+ QSPI_FLASH1_CSN = PTE5,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -15,20 +15,38 @@
*/
#include "gpio_api.h"
#include "pinmap.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -45,3 +63,10 @@
{
CLOCK_SetLpuartClock(2U);
}
+
+// Get the QSPI clock frequency
+uint32_t qspi_get_freq(void)
+{
+ return CLOCK_GetFreq(kCLOCK_McgPll0Clk);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/qspi_device.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_MBED_QSPI_DEVICE_H_
+#define _FSL_MBED_QSPI_DEVICE_H_
+
+#include "fsl_qspi.h"
+
+#define FLASH_SIZE 0x01000000U
+#define FLASH_PAGE_SIZE 256U
+
+qspi_flash_config_t single_config = {
+ .flashA1Size = FLASH_SIZE, /* 16MB */
+ .flashA2Size = 0,
+#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+ .flashB1Size = FLASH_SIZE,
+ .flashB2Size = 0,
+#endif
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+ .dataHoldTime = 0,
+#endif
+ .CSHoldTime = 0,
+ .CSSetupTime = 0,
+ .cloumnspace = 0,
+ .dataLearnValue = 0,
+ .endian = kQSPI_64LittleEndian,
+ .enableWordAddress = false
+};
+
+/* Pre-defined LUT definitions */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] =
+ {
+ /* Seq0 : Read */
+ /* CMD: 0x03 - Read, Single pad */
+ /* ADDR: 0x18 - 24bit address, Single pad */
+ /* READ: 0x80 - Read 128 bytes, Single pad */
+ /* JUMP_ON_CS: 0 */
+ [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x03, QSPI_ADDR, QSPI_PAD_1, 0x18),
+ [1] = QSPI_LUT_SEQ(QSPI_READ, QSPI_PAD_1, 0x80, QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0),
+
+ /* Seq1: Page Program */
+ /* CMD: 0x02 - Page Program, Single pad */
+ /* ADDR: 0x18 - 24bit address, Single pad */
+ /* WRITE: 0x80 - Write 128 bytes at one pass, Single pad */
+ [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+ [5] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+ /* Match MISRA rule */
+ [63] = 0
+ };
+
+#endif /* _FSL_MBED_QSPI_DEVICE_H_*/
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,13 +17,18 @@
#include "fsl_smc.h"
#include "fsl_rcm.h"
#include "fsl_pmc.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
//!< this contains the wakeup source
rcm_reset_source_t kinetisResetSource;
// called before main
-void mbed_sdk_init() {
+void mbed_sdk_init()
+{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
// check the power mode source
@@ -35,6 +40,27 @@
}
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -46,15 +72,6 @@
gpio_init_in(&gpio, PTA4);
}
-#if DEVICE_RTC || DEVICE_LPTICKER
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-#endif
-
// Set the UART clock source
void serial_clock_init(void)
{
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/MKL82Z7.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/MKL82Z7.h Thu Nov 08 11:46:34 2018 +0000
@@ -7691,7 +7691,14 @@
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
- __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
+ union { /* offset: 0x8 */
+ __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
+ struct {
+ __IO uint16_t IDATZ; /**< IP data transfer size, offset: 0x8 */
+ __IO uint8_t PAR_EN; /**< IP data transfer size, offset: 0xA */
+ __IO uint8_t SEQID; /**< IP data transfer size, offset: 0xB */
+ } IPCR_ACCESSBIT;
+ };
__IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */
__IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */
__IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld Thu Nov 08 11:46:34 2018 +0000
@@ -57,10 +57,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x6000;
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
@@ -85,29 +81,29 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.bootloader_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.BootloaderConfig)) /* Bootloader Configuration Area (BCA) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_bootloader_config
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -117,7 +113,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -205,12 +201,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -219,13 +215,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -238,7 +234,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -247,7 +243,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
#include "fsl_qspi.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.qspi"
+#endif
+
+
/*******************************************************************************
* Definitations
******************************************************************************/
@@ -40,25 +50,21 @@
kQSPI_TxError /*!< Transfer error occured. */
};
-#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))
+#define QSPI_AHB_BUFFER_REG(base, index) (((volatile uint32_t *)&((base)->BUF0CR))[(index)])
/*******************************************************************************
* Prototypes
******************************************************************************/
-/*!
-* @brief Get the instance number for QSPI.
-*
-* @param base QSPI base pointer.
-*/
-uint32_t QSPI_GetInstance(QuadSPI_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/* Base pointer array */
static QuadSPI_Type *const s_qspiBases[] = QuadSPI_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Clock name array */
static const clock_ip_name_t s_qspiClock[] = QSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
@@ -68,7 +74,7 @@
uint32_t instance;
/* Find the instance index from base address mappings. */
- for (instance = 0; instance < FSL_FEATURE_SOC_QuadSPI_COUNT; instance++)
+ for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++)
{
if (s_qspiBases[instance] == base)
{
@@ -76,7 +82,7 @@
}
}
- assert(instance < FSL_FEATURE_SOC_QuadSPI_COUNT);
+ assert(instance < ARRAY_SIZE(s_qspiBases));
return instance;
}
@@ -86,8 +92,10 @@
uint32_t i = 0;
uint32_t val = 0;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable QSPI clock */
CLOCK_EnableClock(s_qspiClock[QSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Do software reset to QSPI module */
QSPI_SoftwareReset(base);
@@ -98,12 +106,21 @@
/* Configure QSPI */
QSPI_Enable(base, false);
+#if !defined (FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL) || (!FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL)
/* Set qspi clock source */
base->SOCCR = config->clockSource;
/* Set the divider of QSPI clock */
base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
- base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
+
+ if (srcClock_Hz % config->baudRate) {
+ /* In case we cannot get the exact baudrate, get the closest lower value */
+ base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate);
+ } else {
+ base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
+ }
+
+#endif /* FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL */
/* Set AHB buffer size and buffer master */
for (i = 0; i < FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++)
@@ -123,8 +140,11 @@
/* Set watermark */
base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK;
base->RBCT |= QuadSPI_RBCT_WMRK(config->rxWatermark - 1);
+
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK;
base->TBCT |= QuadSPI_TBCT_WMRK(config->txWatermark - 1);
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
/* Enable QSPI module */
if (config->enableQspi)
@@ -149,7 +169,9 @@
void QSPI_Deinit(QuadSPI_Type *base)
{
QSPI_Enable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(s_qspiClock[QSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
@@ -165,14 +187,18 @@
base->SFA1AD = address;
address += config->flashA2Size;
base->SFA2AD = address;
+#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
address += config->flashB1Size;
base->SFB1AD = address;
address += config->flashB2Size;
base->SFB2AD = address;
+#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_SFACR) || (!FSL_FEATURE_QSPI_HAS_NO_SFACR)
/* Set Word Addressable feature */
val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace);
base->SFACR = val;
+#endif /* FSL_FEATURE_QSPI_HAS_NO_SFACR */
/* Config look up table */
base->LUTKEY = 0x5AF05AF0U;
@@ -184,9 +210,13 @@
base->LUTKEY = 0x5AF05AF0U;
base->LCKCR = 0x1U;
+#if !defined (FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
/* Config flash timing */
val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) |
QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
+#else
+ val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
base->FLSHCR = val;
/* Set flash endianness */
@@ -199,7 +229,7 @@
void QSPI_SoftwareReset(QuadSPI_Type *base)
{
- volatile uint32_t i = 0;
+ uint32_t i = 0;
/* Reset AHB domain and buffer domian */
base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
@@ -314,15 +344,27 @@
{
uint32_t i = 0;
uint32_t j = 0;
- uint32_t level = 0;
+ uint32_t temp = 0;
+ uint32_t level = (base->RBCT & QuadSPI_RBCT_WMRK_MASK) + 1U;
while (i < size / 4)
{
/* Check if there is data */
- do
+ if ((size / 4 - i) < level)
{
- level = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
- } while (!level);
+ do
+ {
+ temp = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
+ } while (!temp);
+ }
+ else
+ {
+ while ((QSPI_GetStatusFlags(base) & kQSPI_RxWatermark) == 0U)
+ {
+ }
+ }
+
+ level = (level < (size / 4 - i)) ? level : (size / 4 - i);
/* Data from RBDR */
if (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)
@@ -341,5 +383,8 @@
}
}
i += level;
+
+ /* Clear the Buffer */
+ QSPI_ClearErrorFlag(base, kQSPI_RxBufferDrain);
}
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -12,10 +15,11 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,17 +42,49 @@
* @{
*/
-
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
-/*! @brief I2C driver version 2.0.1. */
-#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief QSPI driver version 2.0.2. */
+#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
+/*! @brief Macro functions for LUT table */
+#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
+ QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
+
+/*! @brief Macro for QSPI LUT command */
+#define QSPI_CMD (0x1U)
+#define QSPI_ADDR (0x2U)
+#define QSPI_DUMMY (0x3U)
+#define QSPI_MODE (0x4U)
+#define QSPI_MODE2 (0x5U)
+#define QSPI_MODE4 (0x6U)
+#define QSPI_READ (0x7U)
+#define QSPI_WRITE (0x8U)
+#define QSPI_JMP_ON_CS (0x9U)
+#define QSPI_ADDR_DDR (0xAU)
+#define QSPI_MODE_DDR (0xBU)
+#define QSPI_MODE2_DDR (0xCU)
+#define QSPI_MODE4_DDR (0xDU)
+#define QSPI_READ_DDR (0xEU)
+#define QSPI_WRITE_DDR (0xFU)
+#define QSPI_DATA_LEARN (0x10U)
+#define QSPI_CMD_DDR (0x11U)
+#define QSPI_CADDR (0x12U)
+#define QSPI_CADDR_DDR (0x13U)
+#define QSPI_STOP (0x0U)
+
+/*! @brief Macro for QSPI PAD */
+#define QSPI_PAD_1 (0x0U)
+#define QSPI_PAD_2 (0x1U)
+#define QSPI_PAD_4 (0x2U)
+#define QSPI_PAD_8 (0x3U)
+
/*! @brief Status structure of QSPI.*/
enum _status_t
{
@@ -92,31 +128,39 @@
/*! @brief QSPI error flags */
enum _qspi_error_flags
{
- kQSPI_DataLearningFail = QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
- kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
- kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
- kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
- kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
- kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
- kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
- kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
- kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
- kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
+ kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
+ kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
+ kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
+ kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
+ kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
+ kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
+ kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
+ kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
+ kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
+ kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
+#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
+#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
- kQSPI_FlagAll = 0x8C83F8D1U /*!< All error flag */
+ kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
};
/*! @brief QSPI state bit */
enum _qspi_flags
{
- kQSPI_DataLearningSamplePoint = QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
+ kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
@@ -134,14 +178,14 @@
kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
- kQSPI_StateAll = 0xEF897FE7U /*!< All flags */
+ kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
};
/*! @brief QSPI interrupt enable */
enum _qspi_interrupt_enable
{
kQSPI_DataLearningFailInterruptEnable =
- QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
+ (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
kQSPI_IllegalInstructionInterruptEnable =
@@ -149,12 +193,18 @@
kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
kQSPI_AHBIllegalTransactionInterruptEnable =
QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
kQSPI_AHBIllegalBurstSizeInterruptEnable =
- QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
- kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
+ QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
+ kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
+#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
+#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
@@ -163,15 +213,21 @@
QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
kQSPI_IPCommandTransactionFinishedInterruptEnable =
QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
- kQSPI_AllInterruptEnable = 0x8C83F8D1U /*!< All error interrupt enable */
+ kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
};
/*! @brief QSPI DMA request flag */
enum _qspi_dma_enable
{
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
+#else
+ kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
};
/*! @brief Phrase shift number for DQS mode. */
@@ -219,12 +275,16 @@
/*! @brief External flash configuration items*/
typedef struct _qspi_flash_config
{
- uint32_t flashA1Size; /*!< Flash A1 size */
- uint32_t flashA2Size; /*!< Flash A2 size */
+ uint32_t flashA1Size; /*!< Flash A1 size */
+ uint32_t flashA2Size; /*!< Flash A2 size */
+#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
uint32_t flashB1Size; /*!< Flash B1 size */
uint32_t flashB2Size; /*!< Flash B2 size */
+#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
+#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
uint32_t dataHoldTime; /*!< Data line hold time. */
+#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
uint32_t CSHoldTime; /*!< CS line hold time */
uint32_t CSSetupTime; /*!< CS line setup time*/
uint32_t cloumnspace; /*!< Column space size */
@@ -253,6 +313,13 @@
*/
/*!
+* @brief Get the instance number for QSPI.
+*
+* @param base QSPI base pointer.
+*/
+uint32_t QSPI_GetInstance(QuadSPI_Type *base);
+
+/*!
* @brief Initializes the QSPI module and internal state.
*
* This function enables the clock for QSPI and also configures the QSPI with the
@@ -457,9 +524,9 @@
* @param base Pointer to QuadSPI Type.
* @param size IP command size.
*/
-static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
+static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint16_t size)
{
- base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_IDATSZ_MASK)) | QuadSPI_IPCR_IDATSZ(size));
+ base->IPCR_ACCESSBIT.IDATZ = size;
}
/*! @brief Executes IP commands located in LUT table.
@@ -476,6 +543,7 @@
*/
void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
+#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
/*! @brief Enables/disables the QSPI IP command parallel mode.
*
* @param base Pointer to QuadSPI Type.
@@ -509,6 +577,7 @@
base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
}
}
+#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
/*! @brief Updates the LUT table.
*
@@ -539,6 +608,24 @@
base->SPTRCLR = seq;
}
+/*!
+ * @brief Enable or disable DDR mode.
+ *
+ * @param base QSPI base pointer
+ * @param eanble True means enable DDR mode, false means disable DDR mode.
+ */
+static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
+ }
+ else
+ {
+ base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
+ }
+}
+
/*!@ brief Set the RX buffer readout area.
*
* This function can set the RX buffer readout, from AHB bus or IP Bus.
@@ -569,7 +656,10 @@
/*!
* @brief Receives a buffer of data bytes using a blocking method.
- * @note This function blocks via polling until all bytes have been sent.
+ * @note This function blocks via polling until all bytes have been sent. Users shall notice that
+ * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
+ * For flash contents read, please use AHB bus read, this is much more efficiency.
+ *
* @param base QSPI base pointer
* @param buffer The data bytes to send
* @param size The number of data bytes to receive
@@ -609,7 +699,10 @@
* @brief Reads data from the QSPI receive buffer in polling way.
*
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
- * function and can return only when finished. This function uses polling methods.
+ * function and can return only when finished. This function uses polling methods. Users shall notice that
+ * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
+ * For flash contents read, please use AHB bus read, this is much more efficiency.
+ *
* @param base Pointer to QuadSPI Type.
* @param xfer QSPI transfer structure.
*/
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -137,3 +137,8 @@
NVIC_SetPendingIRQ(PIT0_IRQn);
}
+void us_ticker_free(void)
+{
+
+}
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,20 +14,38 @@
* limitations under the License.
*/
#include "gpio_api.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld Thu Nov 08 11:46:34 2018 +0000
@@ -52,10 +52,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x4000;
#if !defined(MBED_APP_START)
@@ -87,22 +83,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -112,7 +108,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -190,12 +186,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -204,13 +200,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -223,7 +219,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -232,7 +228,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/trng_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/trng_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,10 +18,6 @@
*
*/
-/*
- * Reference: "K64 Sub-Family Reference Manual, Rev. 2", chapter 34
- */
-
#if defined(DEVICE_TRNG)
#include <stdlib.h>
@@ -46,10 +42,11 @@
/*
* Get one byte of entropy from the RNG, assuming it is up and running.
- * As recommended (34.1.1), get only one bit of each output.
+ * As recommended, get only one bit of each output.
*/
static void trng_get_byte(unsigned char *byte)
{
+ *byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
@@ -64,7 +61,6 @@
{
(void)obj;
size_t i;
- int ret;
/* Set "Interrupt Mask", "High Assurance" and "Go",
* unset "Clear interrupt" and "Sleep" */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,16 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+ PIT_StopTimer(PIT, kPIT_Chnl_3);
+ PIT_StopTimer(PIT, kPIT_Chnl_2);
+ PIT_StopTimer(PIT, kPIT_Chnl_1);
+ PIT_StopTimer(PIT, kPIT_Chnl_0);
+
+ PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+ NVIC_DisableIRQ(PIT3_IRQn);
+
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,22 +14,40 @@
* limitations under the License.
*/
#include "gpio_api.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
/* Set the TPM clock source to be OSCERCLK, do not change as TPM2 is used for the usticker */
CLOCK_SetTpmClock(2U);
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_GCC_ARM/MKW41Z512xxx4.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_GCC_ARM/MKW41Z512xxx4.ld Thu Nov 08 11:46:34 2018 +0000
@@ -52,10 +52,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x6000;
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
@@ -78,22 +74,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -103,7 +99,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -191,12 +187,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -205,13 +201,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -223,13 +219,13 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -152,3 +152,14 @@
NVIC_SetPendingIRQ(TPM2_IRQn);
}
+
+void us_ticker_free(void)
+{
+ PIT_StopTimer(PIT, kPIT_Chnl_1);
+ PIT_StopTimer(PIT, kPIT_Chnl_0);
+
+ TPM_DisableInterrupts(TPM2, kTPM_TimeOverflowInterruptEnable);
+ NVIC_DisableIRQ(TPM2_IRQn);
+
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -15,21 +15,39 @@
*/
#include "gpio_api.h"
#include "pinmap.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main - implement here if board needs it otherwise, let
// the application override this if necessary
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
pin_function(PTA2, 1); //By default the GREEN LED is enabled. This disables it
-}
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -40,3 +58,4 @@
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_GCC_ARM/MK22FN512xxx12.ld Thu Nov 08 11:46:34 2018 +0000
@@ -78,22 +78,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -103,7 +103,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -181,12 +181,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -195,13 +195,13 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -214,7 +214,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -223,7 +223,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/trng_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/trng_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -46,6 +46,7 @@
*/
static void trng_get_byte(unsigned char *byte)
{
+ *byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,16 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+ PIT_StopTimer(PIT, kPIT_Chnl_3);
+ PIT_StopTimer(PIT, kPIT_Chnl_2);
+ PIT_StopTimer(PIT, kPIT_Chnl_1);
+ PIT_StopTimer(PIT, kPIT_Chnl_0);
+
+ PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+ NVIC_DisableIRQ(PIT3_IRQn);
+
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,12 +17,37 @@
#define CRC16
#include "crc.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -34,10 +59,3 @@
gpio_init_in(&gpio, PTA4);
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,32 +85,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
- /* The program code and other data goes into internal flash */
- /* Note: The uVisor expects this section at a fixed location, as specified by
- * the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_TEXT_OFFSET = 0x410;
- __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;
- .text __UVISOR_TEXT_START :
+ .text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -120,7 +110,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -195,55 +185,15 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
- /* Ensure that the uVisor BSS section is put first after the relocated
- * interrupt table in SRAM. */
- /* Note: The uVisor expects this section at a fixed location, as specified by
- * the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x400;
- __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
- ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,
- "The ISR relocation region overlaps with the uVisor BSS section.")
- .uvisor.bss __UVISOR_BSS_START (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > m_data
-
- /* Heap space for the page allocator */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN(32);
- __uvisor_page_end = .;
- } > m_data_2
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
@@ -252,13 +202,13 @@
{
PROVIDE(__etext = LOADADDR(.data)); /* Define a global symbol at end of code, */
PROVIDE(__DATA_ROM = LOADADDR(.data)); /* Symbol is used by startup for data initialization. */
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data_2 AT > m_text
@@ -266,37 +216,6 @@
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
- /* uVisor configuration section
- * This section must be located after all other flash regions. */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uVisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* Pointers to the uVisor secure boxes configuration tables */
- /* Note: Do not add any further alignment here, as uVisor will need to have
- * access to the exact list of pointers. */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to allow
- * discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > m_text
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
@@ -316,7 +235,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -325,7 +244,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data_2
@@ -333,14 +252,12 @@
.heap :
{
. = ALIGN(8);
- __uvisor_heap_start = .;
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
- __uvisor_heap_end = .;
} > m_data_2
m_usb_bdt USB_RAM_START (NOLOAD) :
@@ -363,9 +280,4 @@
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
- /* Provide the physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(m_interrupts);
- __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);
- __uvisor_sram_start = ORIGIN(m_data);
- __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/trng_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/trng_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,10 +18,6 @@
*
*/
-/*
- * Reference: "K64 Sub-Family Reference Manual, Rev. 2", chapter 34
- */
-
#if defined(DEVICE_TRNG)
#include <stdlib.h>
@@ -46,10 +42,11 @@
/*
* Get one byte of entropy from the RNG, assuming it is up and running.
- * As recommended (34.1.1), get only one bit of each output.
+ * As recommended, get only one bit of each output.
*/
static void trng_get_byte(unsigned char *byte)
{
+ *byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,8 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -242,6 +242,12 @@
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+ //SPI Pins configuration
+ SPI_MOSI = PTE3,
+ SPI_MISO = PTE1,
+ SPI_SCK = PTE2,
+ SPI_PERSISTENT_MEM_CS = PTE4,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,12 +17,37 @@
#define CRC16
#include "crc.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -34,13 +59,6 @@
gpio_init_in(&gpio, PTA4);
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
// Provide ethernet devices with a semi-unique MAC address from the UUID
void mbed_mac_address(char *mac)
{
@@ -55,7 +73,7 @@
// generate three CRC16's using different slices of the UUID
MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
- MAC[1] = crcSlow((const uint8_t *)UID, 12);
+ MAC[1] = crcSlow((const uint8_t *)UID, 12);
MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
// The network stack expects an array of 6 bytes
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -215,6 +215,11 @@
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+ SPI_MOSI = PTE3,
+ SPI_MISO = PTE1,
+ SPI_SCK = PTE2,
+ SPI_PERSISTENT_MEM_CS = PTE4,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,19 +14,36 @@
* limitations under the License.
*/
#include "gpio_api.h"
-
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
-
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,16 +14,36 @@
* limitations under the License.
*/
#include "gpio_api.h"
+#include "fsl_rtc.h"
#include "fsl_clock_config.h"
+
// called before main
void mbed_sdk_init()
{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
}
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(RTC_Type *base)
-{
- /* Enable the RTC oscillator */
- RTC->CR |= RTC_CR_OSCE_MASK;
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+ UART_0 = 0,
+ UART_2 = 2,
+ UART_3 = 3,
+ UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1 = 1,
+} I2CName;
+
+#define TPM_SHIFT 8
+typedef enum {
+ PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
+ PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
+ PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
+ PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
+ PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
+ PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
+ PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
+ PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
+ PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
+ PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
+ PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
+ PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
+ PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
+ PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
+ PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
+ PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
+ PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
+ PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
+ PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
+ PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
+ PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
+ PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
+ PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
+ PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
+ PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
+ PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
+ PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
+ PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
+ PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
+ PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
+ PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
+ PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT 8
+#define ADC_B_CHANNEL_SHIFT 5
+typedef enum {
+ ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+ ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+ ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+ ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+ ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
+ ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
+ ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
+ ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
+ ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
+ ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
+ ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
+ ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
+ ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
+ ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
+ ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
+ ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
+ ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4,
+ ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5,
+ ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6,
+ ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7,
+ ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+ ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+ ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+ ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+ ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
+ ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
+ ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
+ ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
+ ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
+ ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
+ ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
+ ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
+ ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
+ ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23,
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1 = 1,
+ SPI_2 = 2,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+ {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ {PTA17, ADC1_SE17, 0},
+ {PTB0 , ADC0_SE8 , 0},
+ {PTB1 , ADC0_SE9 , 0},
+ {PTB2 , ADC0_SE12, 0},
+ {PTB3 , ADC0_SE13, 0},
+ {PTB6 , ADC1_SE12, 0},
+ {PTB7 , ADC1_SE13, 0},
+ {PTB10, ADC1_SE14, 0},
+ {PTB11, ADC1_SE15, 0},
+ {PTC0 , ADC0_SE14, 0},
+ {PTC1 , ADC0_SE15, 0},
+ {PTC2, ADC0_SE4b, 0},
+ {PTC8, ADC1_SE4b, 0},
+ {PTC9, ADC1_SE5b, 0},
+ {PTC10, ADC1_SE6b, 0},
+ {PTC11, ADC1_SE7b, 0},
+ {PTD1, ADC0_SE5b, 0},
+ {PTD5, ADC0_SE6b, 0},
+ {PTD6, ADC0_SE7b, 0},
+ {PTE0, ADC1_SE4a, 0},
+ {PTE1, ADC1_SE5a, 0},
+ {PTE2, ADC1_SE6a, 0},
+ {PTE3, ADC1_SE7a, 0},
+ //{PTE24, ADC0_SE17, 0}, //I2C pull up
+ //{PTE25, ADC0_SE18, 0}, //I2C pull up
+ {NC , NC , 0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+ {DAC0_OUT, DAC_0, 0},
+ {NC , NC , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {PTD9 , I2C_0, 2},
+ {PTB1 , I2C_0, 2},
+ {PTC11, I2C_1, 2},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PTD8 , I2C_0, 2},
+ {PTB0 , I2C_0, 2},
+ {PTC10, I2C_1, 2},
+ {NC , NC , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {PTB17, UART_0, 3},
+ {PTC17, UART_3, 3},
+ {PTD3 , UART_2, 3},
+ {PTE24, UART_4, 3},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PTB16, UART_0, 3},
+ {PTE25, UART_4, 3},
+ {PTC16, UART_3, 3},
+ {PTD2 , UART_2, 3},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {NC , NC , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ {PTE2 , SPI_1, 2},
+ {PTB21, SPI_2, 2},
+ {PTC5 , SPI_0, 2},
+ {PTD5 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PTE1 , SPI_1, 2},
+ {PTE3 , SPI_1, 7},
+ {PTB22, SPI_2, 2},
+ {PTC6 , SPI_0, 2},
+ {PTD6 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PTE1 , SPI_1, 7},
+ {PTE3 , SPI_1, 2},
+ {PTB23, SPI_2, 2},
+ {PTC7 , SPI_0, 2},
+ {PTD7 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PTE4 , SPI_1, 2},
+ {PTB20, SPI_2, 2},
+ {PTC4 , SPI_0, 2},
+ {PTD4 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+ {PTA0 , PWM_6 , 3},
+ {PTA1 , PWM_7 , 3},
+ {PTA2 , PWM_8 , 3},
+ {PTA3 , PWM_1 , 3},
+ {PTA4 , PWM_2 , 3},
+ {PTA5 , PWM_3 , 3},
+ {PTA6 , PWM_4 , 3},
+ {PTA7 , PWM_5 , 3},
+ {PTA8 , PWM_9 , 3},
+ {PTA9 , PWM_10, 3},
+ {PTA10, PWM_17, 3},
+ {PTA11, PWM_18, 3},
+ {PTA12, PWM_9 , 3},
+ {PTA13, PWM_10, 3},
+
+ {PTB0 , PWM_9 , 3},
+ {PTB1 , PWM_10, 3},
+ {PTB18, PWM_17, 3},
+ {PTB19, PWM_18, 3},
+
+ {PTC1 , PWM_1 , 4},
+ {PTC2 , PWM_2 , 4},
+ {PTC3 , PWM_3 , 4},
+ {PTC4 , PWM_4 , 4},
+ {PTC5 , PWM_3 , 7},
+ {PTC8 , PWM_29, 3},
+ {PTC9 , PWM_30, 3},
+ {PTC10, PWM_31, 3},
+ {PTC11, PWM_32, 3},
+
+ {PTD0 , PWM_25, 4},
+ {PTD1 , PWM_26, 4},
+ {PTD2 , PWM_27, 4},
+ {PTD3 , PWM_28, 4},
+ {PTD4 , PWM_5 , 4},
+ {PTD5 , PWM_6 , 4},
+ {PTD6 , PWM_7 , 4},
+ {PTD4 , PWM_5 , 4},
+ {PTD7 , PWM_8 , 4},
+
+ {PTE5 , PWM_25, 6},
+ {PTE6 , PWM_26, 6},
+
+ {NC , NC , 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,249 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define GPIO_PORT_SHIFT 12
+
+typedef enum {
+ PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
+ PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
+ PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
+ PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
+ PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
+ PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
+ PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
+ PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
+ PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
+ PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
+ PTA10 = (0 << GPIO_PORT_SHIFT | 10),
+ PTA11 = (0 << GPIO_PORT_SHIFT | 11),
+ PTA12 = (0 << GPIO_PORT_SHIFT | 12),
+ PTA13 = (0 << GPIO_PORT_SHIFT | 13),
+ PTA14 = (0 << GPIO_PORT_SHIFT | 14),
+ PTA15 = (0 << GPIO_PORT_SHIFT | 15),
+ PTA16 = (0 << GPIO_PORT_SHIFT | 16),
+ PTA17 = (0 << GPIO_PORT_SHIFT | 17),
+ PTA18 = (0 << GPIO_PORT_SHIFT | 18),
+ PTA19 = (0 << GPIO_PORT_SHIFT | 19),
+ PTA20 = (0 << GPIO_PORT_SHIFT | 20),
+ PTA21 = (0 << GPIO_PORT_SHIFT | 21),
+ PTA22 = (0 << GPIO_PORT_SHIFT | 22),
+ PTA23 = (0 << GPIO_PORT_SHIFT | 23),
+ PTA24 = (0 << GPIO_PORT_SHIFT | 24),
+ PTA25 = (0 << GPIO_PORT_SHIFT | 25),
+ PTA26 = (0 << GPIO_PORT_SHIFT | 26),
+ PTA27 = (0 << GPIO_PORT_SHIFT | 27),
+ PTA28 = (0 << GPIO_PORT_SHIFT | 28),
+ PTA29 = (0 << GPIO_PORT_SHIFT | 29),
+ PTA30 = (0 << GPIO_PORT_SHIFT | 30),
+ PTA31 = (0 << GPIO_PORT_SHIFT | 31),
+ PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
+ PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
+ PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
+ PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
+ PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
+ PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
+ PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
+ PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
+ PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
+ PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
+ PTB10 = (1 << GPIO_PORT_SHIFT | 10),
+ PTB11 = (1 << GPIO_PORT_SHIFT | 11),
+ PTB12 = (1 << GPIO_PORT_SHIFT | 12),
+ PTB13 = (1 << GPIO_PORT_SHIFT | 13),
+ PTB14 = (1 << GPIO_PORT_SHIFT | 14),
+ PTB15 = (1 << GPIO_PORT_SHIFT | 15),
+ PTB16 = (1 << GPIO_PORT_SHIFT | 16),
+ PTB17 = (1 << GPIO_PORT_SHIFT | 17),
+ PTB18 = (1 << GPIO_PORT_SHIFT | 18),
+ PTB19 = (1 << GPIO_PORT_SHIFT | 19),
+ PTB20 = (1 << GPIO_PORT_SHIFT | 20),
+ PTB21 = (1 << GPIO_PORT_SHIFT | 21),
+ PTB22 = (1 << GPIO_PORT_SHIFT | 22),
+ PTB23 = (1 << GPIO_PORT_SHIFT | 23),
+ PTB24 = (1 << GPIO_PORT_SHIFT | 24),
+ PTB25 = (1 << GPIO_PORT_SHIFT | 25),
+ PTB26 = (1 << GPIO_PORT_SHIFT | 26),
+ PTB27 = (1 << GPIO_PORT_SHIFT | 27),
+ PTB28 = (1 << GPIO_PORT_SHIFT | 28),
+ PTB29 = (1 << GPIO_PORT_SHIFT | 29),
+ PTB30 = (1 << GPIO_PORT_SHIFT | 30),
+ PTB31 = (1 << GPIO_PORT_SHIFT | 31),
+ PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
+ PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
+ PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
+ PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
+ PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
+ PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
+ PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
+ PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
+ PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
+ PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
+ PTC10 = (2 << GPIO_PORT_SHIFT | 10),
+ PTC11 = (2 << GPIO_PORT_SHIFT | 11),
+ PTC12 = (2 << GPIO_PORT_SHIFT | 12),
+ PTC13 = (2 << GPIO_PORT_SHIFT | 13),
+ PTC14 = (2 << GPIO_PORT_SHIFT | 14),
+ PTC15 = (2 << GPIO_PORT_SHIFT | 15),
+ PTC16 = (2 << GPIO_PORT_SHIFT | 16),
+ PTC17 = (2 << GPIO_PORT_SHIFT | 17),
+ PTC18 = (2 << GPIO_PORT_SHIFT | 18),
+ PTC19 = (2 << GPIO_PORT_SHIFT | 19),
+ PTC20 = (2 << GPIO_PORT_SHIFT | 20),
+ PTC21 = (2 << GPIO_PORT_SHIFT | 21),
+ PTC22 = (2 << GPIO_PORT_SHIFT | 22),
+ PTC23 = (2 << GPIO_PORT_SHIFT | 23),
+ PTC24 = (2 << GPIO_PORT_SHIFT | 24),
+ PTC25 = (2 << GPIO_PORT_SHIFT | 25),
+ PTC26 = (2 << GPIO_PORT_SHIFT | 26),
+ PTC27 = (2 << GPIO_PORT_SHIFT | 27),
+ PTC28 = (2 << GPIO_PORT_SHIFT | 28),
+ PTC29 = (2 << GPIO_PORT_SHIFT | 29),
+ PTC30 = (2 << GPIO_PORT_SHIFT | 30),
+ PTC31 = (2 << GPIO_PORT_SHIFT | 31),
+ PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
+ PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
+ PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
+ PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
+ PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
+ PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
+ PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
+ PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
+ PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
+ PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
+ PTD10 = (3 << GPIO_PORT_SHIFT | 10),
+ PTD11 = (3 << GPIO_PORT_SHIFT | 11),
+ PTD12 = (3 << GPIO_PORT_SHIFT | 12),
+ PTD13 = (3 << GPIO_PORT_SHIFT | 13),
+ PTD14 = (3 << GPIO_PORT_SHIFT | 14),
+ PTD15 = (3 << GPIO_PORT_SHIFT | 15),
+ PTD16 = (3 << GPIO_PORT_SHIFT | 16),
+ PTD17 = (3 << GPIO_PORT_SHIFT | 17),
+ PTD18 = (3 << GPIO_PORT_SHIFT | 18),
+ PTD19 = (3 << GPIO_PORT_SHIFT | 19),
+ PTD20 = (3 << GPIO_PORT_SHIFT | 20),
+ PTD21 = (3 << GPIO_PORT_SHIFT | 21),
+ PTD22 = (3 << GPIO_PORT_SHIFT | 22),
+ PTD23 = (3 << GPIO_PORT_SHIFT | 23),
+ PTD24 = (3 << GPIO_PORT_SHIFT | 24),
+ PTD25 = (3 << GPIO_PORT_SHIFT | 25),
+ PTD26 = (3 << GPIO_PORT_SHIFT | 26),
+ PTD27 = (3 << GPIO_PORT_SHIFT | 27),
+ PTD28 = (3 << GPIO_PORT_SHIFT | 28),
+ PTD29 = (3 << GPIO_PORT_SHIFT | 29),
+ PTD30 = (3 << GPIO_PORT_SHIFT | 30),
+ PTD31 = (3 << GPIO_PORT_SHIFT | 31),
+ PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
+ PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
+ PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
+ PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
+ PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
+ PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
+ PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
+ PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
+ PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
+ PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
+ PTE10 = (4 << GPIO_PORT_SHIFT | 10),
+ PTE11 = (4 << GPIO_PORT_SHIFT | 11),
+ PTE12 = (4 << GPIO_PORT_SHIFT | 12),
+ PTE13 = (4 << GPIO_PORT_SHIFT | 13),
+ PTE14 = (4 << GPIO_PORT_SHIFT | 14),
+ PTE15 = (4 << GPIO_PORT_SHIFT | 15),
+ PTE16 = (4 << GPIO_PORT_SHIFT | 16),
+ PTE17 = (4 << GPIO_PORT_SHIFT | 17),
+ PTE18 = (4 << GPIO_PORT_SHIFT | 18),
+ PTE19 = (4 << GPIO_PORT_SHIFT | 19),
+ PTE20 = (4 << GPIO_PORT_SHIFT | 20),
+ PTE21 = (4 << GPIO_PORT_SHIFT | 21),
+ PTE22 = (4 << GPIO_PORT_SHIFT | 22),
+ PTE23 = (4 << GPIO_PORT_SHIFT | 23),
+ PTE24 = (4 << GPIO_PORT_SHIFT | 24),
+ PTE25 = (4 << GPIO_PORT_SHIFT | 25),
+ PTE26 = (4 << GPIO_PORT_SHIFT | 26),
+ PTE27 = (4 << GPIO_PORT_SHIFT | 27),
+ PTE28 = (4 << GPIO_PORT_SHIFT | 28),
+ PTE29 = (4 << GPIO_PORT_SHIFT | 29),
+ PTE30 = (4 << GPIO_PORT_SHIFT | 30),
+ PTE31 = (4 << GPIO_PORT_SHIFT | 31),
+
+ LED_RED = PTC8,
+ LED_GREEN = PTE7,
+ LED_BLUE = PTC9,
+
+ RGB_R = LED_RED,
+ RGB_G = LED_GREEN,
+ RGB_B = LED_BLUE,
+
+ // mbed original LED naming
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_RED,
+
+ // Standardized button names
+ BUTTON1 = PTE8,
+ BUTTON2 = PTE9,
+ BUTTON3 = PTE10,
+ BUTTON4 = PTE28,
+
+ USER_SW1 = BUTTON1,
+ USER_SW2 = BUTTON2,
+ USER_SW3 = BUTTON3,
+ USER_SW4 = BUTTON4,
+
+ // USB Pins
+ USBTX = PTB17,
+ USBRX = PTB16,
+
+ I2C_SCL = PTC10,
+ I2C_SDA = PTC11,
+
+ //SPI Pins configuration
+ SPI_MOSI = PTC6,
+ SPI_MISO = PTC7,
+ SPI_SCK = PTC5,
+ SPI_PERSISTENT_MEM_CS = PTC4,
+
+ DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 2,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/fsl_clock_config.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_smc.h"
+#include "fsl_clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Clock configuration structure. */
+typedef struct _clock_config
+{
+ mcg_config_t mcgConfig; /*!< MCG configuration. */
+ sim_clock_config_t simConfig; /*!< SIM configuration. */
+ osc_config_t oscConfig; /*!< OSC configuration. */
+ uint32_t coreClock; /*!< core clock frequency. */
+} clock_config_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/* Configuration for enter VLPR mode. Core clock = 4MHz. */
+const clock_config_t g_defaultClockConfigVlpr = {
+ .mcgConfig =
+ {
+ .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
+ .ircs = kMCG_IrcFast, /* Select IRC4M. */
+ .fcrdiv = 0U, /* FCRDIV is 0. */
+
+ .frdiv = 0U,
+ .drs = kMCG_DrsLow, /* Low frequency range. */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
+ .oscsel = kMCG_OscselOsc, /* Select OSC. */
+
+ .pll0Config =
+ {
+ .enableMode = 0U, /* Don't eanble PLL. */
+ .prdiv = 0U,
+ .vdiv = 0U,
+ },
+ },
+ .simConfig =
+ {
+ .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
+ .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
+ .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
+ },
+ .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
+ .capLoad = 0,
+ .workMode = kOSC_ModeOscLowPower,
+ .oscerConfig =
+ {
+ .enableMode = kOSC_ErClkEnable,
+#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
+ .erclkDiv = 0U,
+#endif
+ }},
+ .coreClock = 4000000U, /* Core clock frequency */
+};
+
+/* Configuration for enter RUN mode. Core clock = 120MHz. */
+const clock_config_t g_defaultClockConfigRun = {
+ .mcgConfig =
+ {
+ .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
+ .ircs = kMCG_IrcSlow, /* Select IRC32k. */
+ .fcrdiv = 0U, /* FCRDIV is 0. */
+
+ .frdiv = 7U,
+ .drs = kMCG_DrsLow, /* Low frequency range. */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
+ .oscsel = kMCG_OscselOsc, /* Select OSC. */
+
+ .pll0Config =
+ {
+ .enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x10U,
+ },
+ },
+ .simConfig =
+ {
+ .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
+ .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
+ .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
+ },
+ .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
+ .capLoad = 0,
+ .workMode = kOSC_ModeOscLowPower,
+ .oscerConfig =
+ {
+ .enableMode = kOSC_ErClkEnable,
+#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
+ .erclkDiv = 0U,
+#endif
+ }},
+ .coreClock = 120000000U, /* Core clock frequency */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ * and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ * internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ * explicitly to setup MCGIRCLK.
+ *
+ * 3). Don't need to configure FLL explicitly, because if target mode is FLL
+ * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ * if the target mode is not FLL mode, the FLL is disabled.
+ *
+ * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+void BOARD_BootClockVLPR(void)
+{
+ CLOCK_SetSimSafeDivs();
+
+ CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
+ g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
+
+ CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
+
+ SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
+
+ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+ SMC_SetPowerModeVlpr(SMC, false);
+ while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+ {
+ }
+}
+
+void BOARD_BootClockRUN(void)
+{
+ CLOCK_SetSimSafeDivs();
+
+ CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
+ CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+
+ CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
+ &g_defaultClockConfigRun.mcgConfig.pll0Config);
+
+ CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
+ g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
+
+ CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
+
+ SystemCoreClock = g_defaultClockConfigRun.coreClock;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/fsl_clock_config.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * DEFINITION
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 12000000U
+#define BOARD_XTAL32K_CLK_HZ 32768U
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockVLPR(void);
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "fsl_rtc.h"
+#include "fsl_clock_config.h"
+
+// called before main
+void mbed_sdk_init()
+{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
+ BOARD_BootClockRUN();
+
+ /* Setup the 32K OSC */
+ gpio_t gpio;
+ gpio_init_out_ex(&gpio, PTD14, 1);
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
+}
+
+void rtc_setup_oscillator(void)
+{
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,137 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+ UART_0 = 0,
+ UART_1 = 1,
+ UART_2 = 2,
+ UART_3 = 3,
+ UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1 = 1,
+ I2C_2 = 2,
+} I2CName;
+
+#define TPM_SHIFT 8
+typedef enum {
+ PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
+ PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
+ PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
+ PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
+ PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
+ PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
+ PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
+ PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
+ PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
+ PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
+ PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
+ PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
+ PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
+ PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
+ PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
+ PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
+ PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
+ PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
+ PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
+ PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
+ PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
+ PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
+ PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
+ PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
+ PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
+ PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
+ PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
+ PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
+ PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
+ PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
+ PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
+ PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT 8
+#define ADC_B_CHANNEL_SHIFT 5
+typedef enum {
+ ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+ ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+ ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+ ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+ ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
+ ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
+ ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
+ ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
+ ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
+ ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
+ ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
+ ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
+ ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
+ ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
+ ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
+ ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
+ ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4,
+ ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5,
+ ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6,
+ ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7,
+ ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+ ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+ ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+ ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+ ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
+ ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
+ ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
+ ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
+ ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
+ ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
+ ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
+ ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
+ ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
+ ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23,
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1 = 1,
+ SPI_2 = 2,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+ {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ {PTA17, ADC1_SE17, 0},
+ {PTB0 , ADC0_SE8 , 0},
+ {PTB1 , ADC0_SE9 , 0},
+ {PTB2 , ADC0_SE12, 0},
+ {PTB3 , ADC0_SE13, 0},
+ {PTB6 , ADC1_SE12, 0},
+ {PTB7 , ADC1_SE13, 0},
+ {PTB10, ADC1_SE14, 0},
+ {PTB11, ADC1_SE15, 0},
+ {PTC0 , ADC0_SE14, 0},
+ {PTC1 , ADC0_SE15, 0},
+ {PTC2, ADC0_SE4b, 0},
+ {PTC8, ADC1_SE4b, 0},
+ {PTC9, ADC1_SE5b, 0},
+ {PTC10, ADC1_SE6b, 0},
+ {PTC11, ADC1_SE7b, 0},
+ {PTD1, ADC0_SE5b, 0},
+ {PTD5, ADC0_SE6b, 0},
+ {PTD6, ADC0_SE7b, 0},
+ {PTE0, ADC1_SE4a, 0},
+ {PTE1, ADC1_SE5a, 0},
+ {PTE2, ADC1_SE6a, 0},
+ {PTE3, ADC1_SE7a, 0},
+ //{PTE24, ADC0_SE17, 0}, //I2C pull up
+ //{PTE25, ADC0_SE18, 0}, //I2C pull up
+ {NC , NC , 0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+ {DAC0_OUT, DAC_0, 0},
+ {NC , NC , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {PTE25, I2C_0, 5},
+ {PTB1 , I2C_0, 2},
+ {PTB3 , I2C_0, 2},
+ {PTC11, I2C_1, 2},
+ {PTA13, I2C_2, 5},
+ {PTD3 , I2C_0, 7},
+ {PTE0 , I2C_1, 6},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PTE24, I2C_0, 5},
+ {PTB0 , I2C_0, 2},
+ {PTB2 , I2C_0, 2},
+ {PTC10, I2C_1, 2},
+ {PTA12, I2C_2, 5},
+ {PTA14, I2C_2, 5},
+ {PTD2 , I2C_0, 7},
+ {PTE1 , I2C_1, 6},
+ {NC , NC , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {PTB17, UART_0, 3},
+ {PTC17, UART_3, 3},
+ {PTD7 , UART_0, 3},
+ {PTD3 , UART_2, 3},
+ {PTC4 , UART_1, 3},
+ {PTC15, UART_4, 3},
+ {PTB11, UART_3, 3},
+ {PTA14, UART_0, 3},
+ {PTE24, UART_4, 3},
+ {PTE4 , UART_3, 3},
+ {PTE0, UART_1, 3},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PTB16, UART_0, 3},
+ {PTE1 , UART_1, 3},
+ {PTE5 , UART_3, 3},
+ {PTE25, UART_4, 3},
+ {PTA15, UART_0, 3},
+ {PTC16, UART_3, 3},
+ {PTB10, UART_3, 3},
+ {PTC3 , UART_1, 3},
+ {PTC14, UART_4, 3},
+ {PTD2 , UART_2, 3},
+ {PTD6 , UART_0, 3},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PTB13, UART_3, 2},
+ {PTE2 , UART_1, 3},
+ {PTE6 , UART_3, 3},
+ {PTE26, UART_4, 3},
+ {PTA0 , UART_0, 2},
+ {PTA16, UART_0, 3},
+ {PTB3 , UART_0, 3},
+ {PTB9 , UART_3, 3},
+ {PTC2 , UART_1, 3},
+ {PTC13, UART_4, 3},
+ {PTC19, UART_3, 3},
+ {PTD1 , UART_2, 3},
+ {PTD5 , UART_0, 3},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PTB12, UART_3, 2},
+ {PTE3 , UART_1, 3},
+ {PTE7 , UART_3, 3},
+ {PTE27, UART_4, 3},
+ {PTA17, UART_0, 3},
+ {PTB8 , UART_3, 3},
+ {PTC1 , UART_1, 3},
+ {PTC12, UART_4, 3},
+ {PTC18, UART_3, 3},
+ {PTD0 , UART_2, 3},
+ {PTD4 , UART_0, 3},
+ {PTA3 , UART_0, 2},
+ {PTB2 , UART_0, 3},
+ {NC , NC , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ {PTD1 , SPI_0, 2},
+ {PTE2 , SPI_1, 2},
+ {PTA15, SPI_0, 2},
+ {PTB11, SPI_1, 2},
+ {PTB21, SPI_2, 2},
+ {PTC5 , SPI_0, 2},
+ {PTD5 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PTD2 , SPI_0, 2},
+ {PTE1 , SPI_1, 2},
+ {PTE3 , SPI_1, 7},
+ {PTA16, SPI_0, 2},
+ {PTB16, SPI_1, 2},
+ {PTB22, SPI_2, 2},
+ {PTC6 , SPI_0, 2},
+ {PTD6 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PTD3 , SPI_0, 2},
+ {PTE1 , SPI_1, 7},
+ {PTE3 , SPI_1, 2},
+ {PTA17, SPI_0, 2},
+ {PTB17, SPI_1, 2},
+ {PTB23, SPI_2, 2},
+ {PTC7 , SPI_0, 2},
+ {PTD7 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PTD0 , SPI_0, 2},
+ {PTE4 , SPI_1, 2},
+ {PTA14, SPI_0, 2},
+ {PTB10, SPI_1, 2},
+ {PTB20, SPI_2, 2},
+ {PTC4 , SPI_0, 2},
+ {PTD4 , SPI_1, 7},
+ {NC , NC , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+ {PTA0 , PWM_6 , 3},
+ {PTA1 , PWM_7 , 3},
+ {PTA2 , PWM_8 , 3},
+ {PTA3 , PWM_1 , 3},
+ {PTA4 , PWM_2 , 3},
+ {PTA5 , PWM_3 , 3},
+ {PTA6 , PWM_4 , 3},
+ {PTA7 , PWM_5 , 3},
+ {PTA8 , PWM_9 , 3},
+ {PTA9 , PWM_10, 3},
+ {PTA10, PWM_17, 3},
+ {PTA11, PWM_18, 3},
+ {PTA12, PWM_9 , 3},
+ {PTA13, PWM_10, 3},
+
+ {PTB0 , PWM_9 , 3},
+ {PTB1 , PWM_10, 3},
+ {PTB18, PWM_17, 3},
+ {PTB19, PWM_18, 3},
+
+ {PTC1 , PWM_1 , 4},
+ {PTC2 , PWM_2 , 4},
+ {PTC3 , PWM_3 , 4},
+ {PTC4 , PWM_4 , 4},
+ {PTC5 , PWM_3 , 7},
+ {PTC8 , PWM_29, 3},
+ {PTC9 , PWM_30, 3},
+ {PTC10, PWM_31, 3},
+ {PTC11, PWM_32, 3},
+
+ {PTD0 , PWM_25, 4},
+ {PTD1 , PWM_26, 4},
+ {PTD2 , PWM_27, 4},
+ {PTD3 , PWM_28, 4},
+ {PTD4 , PWM_5 , 4},
+ {PTD5 , PWM_6 , 4},
+ {PTD6 , PWM_7 , 4},
+ {PTD4 , PWM_5 , 4},
+ {PTD7 , PWM_8 , 4},
+
+ {PTE5 , PWM_25, 6},
+ {PTE6 , PWM_26, 6},
+
+ {NC , NC , 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,318 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define DAC0_OUT 0xFEFE /* DAC does not have Pin Name in RM */
+#define NOT_CONNECTED (int)0xFFFFFFFF
+#define GPIO_PORT_SHIFT 12
+
+typedef enum {
+ PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
+ PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
+ PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
+ PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
+ PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
+ PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
+ PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
+ PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
+ PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
+ PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
+ PTA10 = (0 << GPIO_PORT_SHIFT | 10),
+ PTA11 = (0 << GPIO_PORT_SHIFT | 11),
+ PTA12 = (0 << GPIO_PORT_SHIFT | 12),
+ PTA13 = (0 << GPIO_PORT_SHIFT | 13),
+ PTA14 = (0 << GPIO_PORT_SHIFT | 14),
+ PTA15 = (0 << GPIO_PORT_SHIFT | 15),
+ PTA16 = (0 << GPIO_PORT_SHIFT | 16),
+ PTA17 = (0 << GPIO_PORT_SHIFT | 17),
+ PTA18 = (0 << GPIO_PORT_SHIFT | 18),
+ PTA19 = (0 << GPIO_PORT_SHIFT | 19),
+ PTA20 = (0 << GPIO_PORT_SHIFT | 20),
+ PTA21 = (0 << GPIO_PORT_SHIFT | 21),
+ PTA22 = (0 << GPIO_PORT_SHIFT | 22),
+ PTA23 = (0 << GPIO_PORT_SHIFT | 23),
+ PTA24 = (0 << GPIO_PORT_SHIFT | 24),
+ PTA25 = (0 << GPIO_PORT_SHIFT | 25),
+ PTA26 = (0 << GPIO_PORT_SHIFT | 26),
+ PTA27 = (0 << GPIO_PORT_SHIFT | 27),
+ PTA28 = (0 << GPIO_PORT_SHIFT | 28),
+ PTA29 = (0 << GPIO_PORT_SHIFT | 29),
+ PTA30 = (0 << GPIO_PORT_SHIFT | 30),
+ PTA31 = (0 << GPIO_PORT_SHIFT | 31),
+ PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
+ PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
+ PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
+ PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
+ PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
+ PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
+ PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
+ PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
+ PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
+ PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
+ PTB10 = (1 << GPIO_PORT_SHIFT | 10),
+ PTB11 = (1 << GPIO_PORT_SHIFT | 11),
+ PTB12 = (1 << GPIO_PORT_SHIFT | 12),
+ PTB13 = (1 << GPIO_PORT_SHIFT | 13),
+ PTB14 = (1 << GPIO_PORT_SHIFT | 14),
+ PTB15 = (1 << GPIO_PORT_SHIFT | 15),
+ PTB16 = (1 << GPIO_PORT_SHIFT | 16),
+ PTB17 = (1 << GPIO_PORT_SHIFT | 17),
+ PTB18 = (1 << GPIO_PORT_SHIFT | 18),
+ PTB19 = (1 << GPIO_PORT_SHIFT | 19),
+ PTB20 = (1 << GPIO_PORT_SHIFT | 20),
+ PTB21 = (1 << GPIO_PORT_SHIFT | 21),
+ PTB22 = (1 << GPIO_PORT_SHIFT | 22),
+ PTB23 = (1 << GPIO_PORT_SHIFT | 23),
+ PTB24 = (1 << GPIO_PORT_SHIFT | 24),
+ PTB25 = (1 << GPIO_PORT_SHIFT | 25),
+ PTB26 = (1 << GPIO_PORT_SHIFT | 26),
+ PTB27 = (1 << GPIO_PORT_SHIFT | 27),
+ PTB28 = (1 << GPIO_PORT_SHIFT | 28),
+ PTB29 = (1 << GPIO_PORT_SHIFT | 29),
+ PTB30 = (1 << GPIO_PORT_SHIFT | 30),
+ PTB31 = (1 << GPIO_PORT_SHIFT | 31),
+ PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
+ PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
+ PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
+ PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
+ PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
+ PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
+ PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
+ PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
+ PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
+ PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
+ PTC10 = (2 << GPIO_PORT_SHIFT | 10),
+ PTC11 = (2 << GPIO_PORT_SHIFT | 11),
+ PTC12 = (2 << GPIO_PORT_SHIFT | 12),
+ PTC13 = (2 << GPIO_PORT_SHIFT | 13),
+ PTC14 = (2 << GPIO_PORT_SHIFT | 14),
+ PTC15 = (2 << GPIO_PORT_SHIFT | 15),
+ PTC16 = (2 << GPIO_PORT_SHIFT | 16),
+ PTC17 = (2 << GPIO_PORT_SHIFT | 17),
+ PTC18 = (2 << GPIO_PORT_SHIFT | 18),
+ PTC19 = (2 << GPIO_PORT_SHIFT | 19),
+ PTC20 = (2 << GPIO_PORT_SHIFT | 20),
+ PTC21 = (2 << GPIO_PORT_SHIFT | 21),
+ PTC22 = (2 << GPIO_PORT_SHIFT | 22),
+ PTC23 = (2 << GPIO_PORT_SHIFT | 23),
+ PTC24 = (2 << GPIO_PORT_SHIFT | 24),
+ PTC25 = (2 << GPIO_PORT_SHIFT | 25),
+ PTC26 = (2 << GPIO_PORT_SHIFT | 26),
+ PTC27 = (2 << GPIO_PORT_SHIFT | 27),
+ PTC28 = (2 << GPIO_PORT_SHIFT | 28),
+ PTC29 = (2 << GPIO_PORT_SHIFT | 29),
+ PTC30 = (2 << GPIO_PORT_SHIFT | 30),
+ PTC31 = (2 << GPIO_PORT_SHIFT | 31),
+ PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
+ PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
+ PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
+ PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
+ PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
+ PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
+ PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
+ PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
+ PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
+ PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
+ PTD10 = (3 << GPIO_PORT_SHIFT | 10),
+ PTD11 = (3 << GPIO_PORT_SHIFT | 11),
+ PTD12 = (3 << GPIO_PORT_SHIFT | 12),
+ PTD13 = (3 << GPIO_PORT_SHIFT | 13),
+ PTD14 = (3 << GPIO_PORT_SHIFT | 14),
+ PTD15 = (3 << GPIO_PORT_SHIFT | 15),
+ PTD16 = (3 << GPIO_PORT_SHIFT | 16),
+ PTD17 = (3 << GPIO_PORT_SHIFT | 17),
+ PTD18 = (3 << GPIO_PORT_SHIFT | 18),
+ PTD19 = (3 << GPIO_PORT_SHIFT | 19),
+ PTD20 = (3 << GPIO_PORT_SHIFT | 20),
+ PTD21 = (3 << GPIO_PORT_SHIFT | 21),
+ PTD22 = (3 << GPIO_PORT_SHIFT | 22),
+ PTD23 = (3 << GPIO_PORT_SHIFT | 23),
+ PTD24 = (3 << GPIO_PORT_SHIFT | 24),
+ PTD25 = (3 << GPIO_PORT_SHIFT | 25),
+ PTD26 = (3 << GPIO_PORT_SHIFT | 26),
+ PTD27 = (3 << GPIO_PORT_SHIFT | 27),
+ PTD28 = (3 << GPIO_PORT_SHIFT | 28),
+ PTD29 = (3 << GPIO_PORT_SHIFT | 29),
+ PTD30 = (3 << GPIO_PORT_SHIFT | 30),
+ PTD31 = (3 << GPIO_PORT_SHIFT | 31),
+ PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
+ PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
+ PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
+ PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
+ PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
+ PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
+ PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
+ PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
+ PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
+ PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
+ PTE10 = (4 << GPIO_PORT_SHIFT | 10),
+ PTE11 = (4 << GPIO_PORT_SHIFT | 11),
+ PTE12 = (4 << GPIO_PORT_SHIFT | 12),
+ PTE13 = (4 << GPIO_PORT_SHIFT | 13),
+ PTE14 = (4 << GPIO_PORT_SHIFT | 14),
+ PTE15 = (4 << GPIO_PORT_SHIFT | 15),
+ PTE16 = (4 << GPIO_PORT_SHIFT | 16),
+ PTE17 = (4 << GPIO_PORT_SHIFT | 17),
+ PTE18 = (4 << GPIO_PORT_SHIFT | 18),
+ PTE19 = (4 << GPIO_PORT_SHIFT | 19),
+ PTE20 = (4 << GPIO_PORT_SHIFT | 20),
+ PTE21 = (4 << GPIO_PORT_SHIFT | 21),
+ PTE22 = (4 << GPIO_PORT_SHIFT | 22),
+ PTE23 = (4 << GPIO_PORT_SHIFT | 23),
+ PTE24 = (4 << GPIO_PORT_SHIFT | 24),
+ PTE25 = (4 << GPIO_PORT_SHIFT | 25),
+ PTE26 = (4 << GPIO_PORT_SHIFT | 26),
+ PTE27 = (4 << GPIO_PORT_SHIFT | 27),
+ PTE28 = (4 << GPIO_PORT_SHIFT | 28),
+ PTE29 = (4 << GPIO_PORT_SHIFT | 29),
+ PTE30 = (4 << GPIO_PORT_SHIFT | 30),
+ PTE31 = (4 << GPIO_PORT_SHIFT | 31),
+
+ // Analog
+ A0 = PTB6,
+ A1 = PTB7,
+ A2 = DAC0_OUT,
+ //A3 = DAC1_OUT,
+
+ // General Pin Input Output (GPIO)
+ GPIO0 = PTC1,
+ GPIO1 = PTC5,
+ GPIO2 = PTD6,
+ GPIO3 = PTC9,
+ GPIO4 = PTC3,
+ GPIO5 = PTC6,
+ GPIO6 = NOT_CONNECTED,
+
+ // Pulse Width Modulation (PWM)
+ PWM0 = GPIO2,
+ PWM1 = GPIO3,
+ PWM2 = GPIO0,
+ PWM3 = GPIO1,
+
+ // LEDs
+ LED0 = GPIO0,
+ LED1 = GPIO1,
+ LED2 = GPIO2,
+
+ LED_RED = LED0,
+ LED_GREEN = LED1,
+ LED_BLUE = LED2,
+
+ // USB bridge and SWD UART connected UART pins
+ USBTX = PTC15,
+ USBRX = PTC14,
+
+ // UART pins
+ UART0_RX = PTD8,
+ UART0_TX = PTD9,
+ UART0_CTS = PTD11,
+ UART0_RTS = PTD10,
+
+ UART1_RX = USBRX,
+ UART1_TX = USBTX,
+ UART1_CTS = PTC13,
+ UART1_RTS = PTC12,
+
+ UART2_RX = PTC16,
+ UART2_TX = PTC17,
+ UART2_CTS = PTC19,
+ UART2_RTS = PTC18,
+
+ // I2C pins
+ I2C0_SCL = PTC10,
+ I2C0_SDA = PTC11,
+
+ I2C1_SCL = PTB2,
+ I2C1_SDA = PTB3,
+
+ I2C2_SCL = NOT_CONNECTED,
+ I2C2_SDA = NOT_CONNECTED,
+
+ // SPI pins
+ SPI0_SCK = PTB11,
+ SPI0_MOSI = PTB16,
+ SPI0_MISO = PTB17,
+ SPI0_SS0 = PTB10,
+ SPI0_SS1 = PTB9,
+ SPI0_SS2 = PTB8,
+
+ SPI1_SCK = PTB21,
+ SPI1_MOSI = PTB22,
+ SPI1_MISO = PTB23,
+ SPI1_SS0 = PTB20,
+ SPI1_SS1 = PTB19,
+ SPI1_SS2 = PTB18,
+
+ SPI2_SCK = PTD1,
+ SPI2_MOSI = PTD2,
+ SPI2_MISO = PTD3,
+ SPI2_SS0 = PTD0,
+ SPI2_SS1 = PTD4,
+ SPI2_SS2 = PTD5,
+
+ SPI3_SCK = NOT_CONNECTED,
+ SPI3_MOSI = NOT_CONNECTED,
+ SPI3_MISO = NOT_CONNECTED,
+ SPI3_SS0 = NOT_CONNECTED,
+ SPI3_SS1 = NOT_CONNECTED,
+ SPI3_SS2 = NOT_CONNECTED,
+
+ // SWD UART
+ SWD_TGT_TX = UART1_TX,
+ SWD_TGT_RX = UART1_RX,
+ SWD_TGT_CTS = UART1_CTS,
+ SWD_TGT_RTS = UART1_RTS,
+
+ // Generics
+ SERIAL_TX = UART0_TX,
+ SERIAL_RX = UART0_RX,
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_SS0,
+ PWM_OUT = PWM0,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 2,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,234 @@
+/**********************************************************************
+ *
+ * Filename: crc.c
+ *
+ * Description: Slow and fast implementations of the CRC standards.
+ *
+ * Notes: The parameters for each supported CRC standard are
+ * defined in the header file crc.h. The implementations
+ * here should stand up to further additions to that list.
+ *
+ *
+ * Copyright (c) 2000 by Michael Barr. This software is placed into
+ * the public domain and may be used for any purpose. However, this
+ * notice must not be changed or removed and no warranty is either
+ * expressed or implied by its publication or distribution.
+ **********************************************************************/
+
+#include "crc.h"
+
+
+/*
+ * Derive parameters from the standard-specific parameters in crc.h.
+ */
+#define WIDTH (8 * sizeof(crc))
+#define TOPBIT (1 << (WIDTH - 1))
+
+#if (REFLECT_DATA == TRUE)
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
+#else
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) (X)
+#endif
+
+#if (REFLECT_REMAINDER == TRUE)
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
+#else
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) (X)
+#endif
+
+
+/*********************************************************************
+ *
+ * Function: reflect()
+ *
+ * Description: Reorder the bits of a binary sequence, by reflecting
+ * them about the middle position.
+ *
+ * Notes: No checking is done that nBits <= 32.
+ *
+ * Returns: The reflection of the original data.
+ *
+ *********************************************************************/
+static unsigned long
+reflect(unsigned long data, unsigned char nBits)
+{
+ unsigned long reflection = 0x00000000;
+ unsigned char bit;
+
+ /*
+ * Reflect the data about the center bit.
+ */
+ for (bit = 0; bit < nBits; ++bit)
+ {
+ /*
+ * If the LSB bit is set, set the reflection of it.
+ */
+ if (data & 0x01)
+ {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+
+ data = (data >> 1);
+ }
+
+ return (reflection);
+
+} /* reflect() */
+
+
+/*********************************************************************
+ *
+ * Function: crcSlow()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes:
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+crc
+crcSlow(unsigned char const message[], int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ int byte;
+ unsigned char bit;
+
+
+ /*
+ * Perform modulo-2 division, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte)
+ {
+ /*
+ * Bring the next byte into the remainder.
+ */
+ remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit)
+ {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT)
+ {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ }
+ else
+ {
+ remainder = (remainder << 1);
+ }
+ }
+ }
+
+ /*
+ * The final remainder is the CRC result.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+
+} /* crcSlow() */
+
+
+crc crcTable[256];
+
+
+/*********************************************************************
+ *
+ * Function: crcInit()
+ *
+ * Description: Populate the partial CRC lookup table.
+ *
+ * Notes: This function must be rerun any time the CRC standard
+ * is changed. If desired, it can be run "offline" and
+ * the table results stored in an embedded system's ROM.
+ *
+ * Returns: None defined.
+ *
+ *********************************************************************/
+void
+crcInit(void)
+{
+ crc remainder;
+ int dividend;
+ unsigned char bit;
+
+
+ /*
+ * Compute the remainder of each possible dividend.
+ */
+ for (dividend = 0; dividend < 256; ++dividend)
+ {
+ /*
+ * Start with the dividend followed by zeros.
+ */
+ remainder = dividend << (WIDTH - 8);
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit)
+ {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT)
+ {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ }
+ else
+ {
+ remainder = (remainder << 1);
+ }
+ }
+
+ /*
+ * Store the result into the table.
+ */
+ crcTable[dividend] = remainder;
+ }
+
+} /* crcInit() */
+
+
+/*********************************************************************
+ *
+ * Function: crcFast()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes: crcInit() must be called first.
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+crc
+crcFast(unsigned char const message[], int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ unsigned char data;
+ int byte;
+
+
+ /*
+ * Divide the message by the polynomial, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte)
+ {
+ data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
+ remainder = crcTable[data] ^ (remainder << 8);
+ }
+
+ /*
+ * The final remainder is the CRC.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+
+} /* crcFast() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,77 @@ +/********************************************************************** + * + * Filename: crc.h + * + * Description: A header file describing the various CRC standards. + * + * Notes: + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#ifndef _crc_h +#define _crc_h + + +#define FALSE 0 +#define TRUE !FALSE + +/* + * Select the CRC standard from the list that follows. + */ +#define CRC16 + + +#if defined(CRC_CCITT) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-CCITT" +#define POLYNOMIAL 0x1021 +#define INITIAL_REMAINDER 0xFFFF +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA FALSE +#define REFLECT_REMAINDER FALSE +#define CHECK_VALUE 0x29B1 + +#elif defined(CRC16) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-16" +#define POLYNOMIAL 0x8005 +#define INITIAL_REMAINDER 0x0000 +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xBB3D + +#elif defined(CRC32) + +typedef unsigned long crc; + +#define CRC_NAME "CRC-32" +#define POLYNOMIAL 0x04C11DB7 +#define INITIAL_REMAINDER 0xFFFFFFFF +#define FINAL_XOR_VALUE 0xFFFFFFFF +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xCBF43926 + +#else + +#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." + +#endif + + +void crcInit(void); +crc crcSlow(unsigned char const message[], int nBytes); +crc crcFast(unsigned char const message[], int nBytes); + + +#endif /* _crc_h */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_smc.h"
+#include "fsl_clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Clock configuration structure. */
+typedef struct _clock_config
+{
+ mcg_config_t mcgConfig; /*!< MCG configuration. */
+ sim_clock_config_t simConfig; /*!< SIM configuration. */
+ osc_config_t oscConfig; /*!< OSC configuration. */
+ uint32_t coreClock; /*!< core clock frequency. */
+} clock_config_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/* Configuration for enter VLPR mode. Core clock = 4MHz. */
+const clock_config_t g_defaultClockConfigVlpr = {
+ .mcgConfig =
+ {
+ .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
+ .ircs = kMCG_IrcFast, /* Select IRC4M. */
+ .fcrdiv = 0U, /* FCRDIV is 0. */
+
+ .frdiv = 0U,
+ .drs = kMCG_DrsLow, /* Low frequency range. */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
+ .oscsel = kMCG_OscselOsc, /* Select OSC. */
+
+ .pll0Config =
+ {
+ .enableMode = 0U, /* Don't eanble PLL. */
+ .prdiv = 0U,
+ .vdiv = 0U,
+ },
+ },
+ .simConfig =
+ {
+ .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
+ .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
+ .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
+ },
+ .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
+ .capLoad = 0,
+ .workMode = kOSC_ModeExt,
+ .oscerConfig =
+ {
+ .enableMode = kOSC_ErClkEnable,
+#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
+ .erclkDiv = 0U,
+#endif
+ }},
+ .coreClock = 4000000U, /* Core clock frequency */
+};
+
+/* Configuration for enter RUN mode. Core clock = 120MHz. */
+const clock_config_t g_defaultClockConfigRun = {
+ .mcgConfig =
+ {
+ .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
+ .ircs = kMCG_IrcSlow, /* Select IRC32k. */
+ .fcrdiv = 0U, /* FCRDIV is 0. */
+
+ .frdiv = 7U,
+ .drs = kMCG_DrsLow, /* Low frequency range. */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
+ .oscsel = kMCG_OscselOsc, /* Select OSC. */
+
+ .pll0Config =
+ {
+ .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
+ },
+ },
+ .simConfig =
+ {
+ .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
+ .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
+ .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
+ },
+ .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
+ .capLoad = 0,
+ .workMode = kOSC_ModeExt,
+ .oscerConfig =
+ {
+ .enableMode = kOSC_ErClkEnable,
+#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
+ .erclkDiv = 0U,
+#endif
+ }},
+ .coreClock = 120000000U, /* Core clock frequency */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ * and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ * internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ * explicitly to setup MCGIRCLK.
+ *
+ * 3). Don't need to configure FLL explicitly, because if target mode is FLL
+ * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ * if the target mode is not FLL mode, the FLL is disabled.
+ *
+ * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+void BOARD_BootClockVLPR(void)
+{
+ CLOCK_SetSimSafeDivs();
+
+ CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
+ g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
+
+ CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
+
+ SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
+
+ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+ SMC_SetPowerModeVlpr(SMC, false);
+ while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+ {
+ }
+}
+
+void BOARD_BootClockRUN(void)
+{
+ CLOCK_SetSimSafeDivs();
+
+ CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
+ CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+
+ CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
+ &g_defaultClockConfigRun.mcgConfig.pll0Config);
+
+ CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
+ g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
+
+ CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
+
+ SystemCoreClock = g_defaultClockConfigRun.coreClock;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * DEFINITION
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 50000000U
+#define BOARD_XTAL32K_CLK_HZ 32768U
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockVLPR(void);
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_phy.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines the timeout macro. */
+#define PHY_TIMEOUT_COUNT 0xFFFFFU
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+extern uint32_t ENET_GetInstance(ENET_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
+{
+ uint32_t counter = PHY_TIMEOUT_COUNT;
+ uint32_t idReg = 0;
+ status_t result = kStatus_Success;
+ uint32_t instance = ENET_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Set SMI first. */
+ CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+ ENET_SetSMI(base, srcClock_Hz, false);
+
+ /* Initialization after PHY stars to work. */
+ while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
+ {
+ PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+ counter --;
+ }
+
+ if (!counter)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Reset PHY. */
+ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
+
+ return result;
+}
+
+status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
+{
+ status_t result = kStatus_Success;
+ uint32_t bssReg;
+ uint32_t counter = PHY_TIMEOUT_COUNT;
+
+ /* Set the negotiation. */
+ result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
+ (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
+ PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
+ if (result == kStatus_Success)
+ {
+ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
+ (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+ if (result == kStatus_Success)
+ {
+ /* Check auto negotiation complete. */
+ while (counter --)
+ {
+ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
+ if ( result == kStatus_Success)
+ {
+ if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
+ {
+ break;
+ }
+ }
+
+ if (!counter)
+ {
+ return kStatus_PHY_AutoNegotiateFail;
+ }
+ }
+ }
+ }
+
+ return result;
+}
+
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+ uint32_t counter;
+
+ /* Clear the SMI interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ /* Starts a SMI write command. */
+ ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
+
+ /* Wait for SMI complete. */
+ for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+ {
+ if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+ {
+ break;
+ }
+ }
+
+ /* Check for timeout. */
+ if (!counter)
+ {
+ return kStatus_PHY_SMIVisitTimeout;
+ }
+
+ /* Clear MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ return kStatus_Success;
+}
+
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
+{
+ assert(dataPtr);
+
+ uint32_t counter;
+
+ /* Clear the MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ /* Starts a SMI read command operation. */
+ ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
+
+ /* Wait for MII complete. */
+ for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+ {
+ if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+ {
+ break;
+ }
+ }
+
+ /* Check for timeout. */
+ if (!counter)
+ {
+ return kStatus_PHY_SMIVisitTimeout;
+ }
+
+ /* Get data from MII register. */
+ *dataPtr = ENET_ReadSMIData(base);
+
+ /* Clear MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ return kStatus_Success;
+}
+
+status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable)
+{
+ status_t result;
+ uint32_t data = 0;
+
+ /* Set the loop mode. */
+ if (enable)
+ {
+ if (mode == kPHY_LocalLoop)
+ {
+ /* First read the current status in control register. */
+ result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
+ if (result == kStatus_Success)
+ {
+ return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK));
+ }
+ }
+ else
+ {
+ /* First read the current status in control register. */
+ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+ if (result == kStatus_Success)
+ {
+ return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
+ }
+ }
+ }
+ else
+ {
+ /* Disable the loop mode. */
+ if (mode == kPHY_LocalLoop)
+ {
+ /* First read the current status in the basic control register. */
+ result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
+ if (result == kStatus_Success)
+ {
+ return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK));
+ }
+ }
+ else
+ {
+ /* First read the current status in control one register. */
+ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+ if (result == kStatus_Success)
+ {
+ return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
+ }
+ }
+ }
+ return result;
+}
+
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
+{
+ assert(status);
+
+ status_t result = kStatus_Success;
+ uint32_t data;
+
+ /* Read the basic status register. */
+ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
+ if (result == kStatus_Success)
+ {
+ if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
+ {
+ /* link down. */
+ *status = false;
+ }
+ else
+ {
+ /* link up. */
+ *status = true;
+ }
+ }
+ return result;
+}
+
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+ assert(duplex);
+
+ status_t result = kStatus_Success;
+ uint32_t data, ctlReg;
+
+ /* Read the control two register. */
+ result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
+ if (result == kStatus_Success)
+ {
+ data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
+ if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
+ {
+ /* Full duplex. */
+ *duplex = kPHY_FullDuplex;
+ }
+ else
+ {
+ /* Half duplex. */
+ *duplex = kPHY_HalfDuplex;
+ }
+
+ data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
+ if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
+ {
+ /* 100M speed. */
+ *speed = kPHY_Speed100M;
+ }
+ else
+ { /* 10M speed. */
+ *speed = kPHY_Speed10M;
+ }
+ }
+
+ return result;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PHY_H_
+#define _FSL_PHY_H_
+
+#include "fsl_enet.h"
+
+/*!
+ * @addtogroup phy_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief PHY driver version */
+#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*! @brief Defines the PHY registers. */
+#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
+#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
+#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
+#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
+#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
+#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
+#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
+
+#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
+
+/*! @brief Defines the mask flag in basic control register. */
+#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
+#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
+#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
+#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
+#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
+#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
+
+/*!@brief Defines the mask flag of operation mode in control two register*/
+#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
+#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
+#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
+#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
+#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
+#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
+
+/*! @brief Defines the mask flag in basic status register. */
+#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
+#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
+#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
+
+/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
+#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
+#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
+#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
+#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
+#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
+
+/*! @brief Defines the PHY status. */
+enum _phy_status
+{
+ kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
+ kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
+};
+
+/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
+typedef enum _phy_speed
+{
+ kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
+ kPHY_Speed100M /*!< ENET PHY 100M speed. */
+} phy_speed_t;
+
+/*! @brief Defines the PHY link duplex. */
+typedef enum _phy_duplex
+{
+ kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
+ kPHY_FullDuplex /*!< ENET PHY full duplex. */
+} phy_duplex_t;
+
+/*! @brief Defines the PHY loopback mode. */
+typedef enum _phy_loop
+{
+ kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
+ kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
+} phy_loop_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name PHY Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes PHY.
+ *
+ * This function initialize the SMI interface and initialize PHY.
+ * The SMI is the MII management interface between PHY and MAC, which should be
+ * firstly initialized before any other operation for PHY.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
+ * @retval kStatus_Success PHY initialize success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Initiates auto negotiation.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @retval kStatus_Success PHY auto negotiation success
+ * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
+ */
+status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr);
+
+/*!
+ * @brief PHY Write function. This function write data over the SMI to
+ * the specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param data The data written to the PHY register.
+ * @retval kStatus_Success PHY write success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/*!
+ * @brief PHY Read function. This interface read data over the SMI from the
+ * specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param dataPtr The address to store the data read from the PHY register.
+ * @retval kStatus_Success PHY read success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
+
+/*!
+ * @brief Enables/disables PHY loopback.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param mode The loopback mode to be enabled, please see "phy_loop_t".
+ * the two loopback mode should not be both set. when one loopback mode is set
+ * the other one should be disabled.
+ * @param enable True to enable, false to disable.
+ * @retval kStatus_Success PHY loopback success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable);
+
+/*!
+ * @brief Gets the PHY link status.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param status The link up or down status of the PHY.
+ * - true the link is up.
+ * - false the link is down.
+ * @retval kStatus_Success PHY get link status success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
+
+/*!
+ * @brief Gets the PHY link speed and duplex.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param speed The address of PHY link speed.
+ * @param duplex The link duplex of PHY.
+ * @retval kStatus_Success PHY get link speed and duplex success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PHY_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+#define CRC16
+#include "crc.h"
+#include "fsl_rtc.h"
+#include "fsl_clock_config.h"
+
+// called before main
+void mbed_sdk_init()
+{
+ rtc_config_t rtc_basic_config;
+ uint32_t u32cTPR_counter = 0;
+
+ BOARD_BootClockRUN();
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Check if the Rtc oscillator is enabled */
+ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
+ /* Setup the 32K RTC OSC */
+ RTC_Init(RTC, &rtc_basic_config);
+
+ /* Enable the RTC 32KHz oscillator */
+ RTC->CR |= RTC_CR_OSCE_MASK;
+
+ /* Start the RTC time counter */
+ RTC_StartTimer(RTC);
+
+ /* Verify TPR register reaches 4096 counts */
+ while (u32cTPR_counter < 4096) {
+ u32cTPR_counter = RTC->TPR;
+ }
+ /* 32kHz Oscillator is ready. */
+ RTC_Deinit(RTC);
+ }
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+// be used as a low power mode wakeup. The application will
+// need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+ gpio_t gpio;
+ gpio_init_in(&gpio, PTA4);
+}
+
+// Provide ethernet devices with a semi-unique MAC address from the UUID
+void mbed_mac_address(char *mac)
+{
+ uint16_t MAC[3]; // 3 16 bits words for the MAC
+
+ // get UID via SIM_UID macros defined in the K64F MCU CMSIS header file
+ uint32_t UID[4];
+ UID[0] = SIM->UIDH;
+ UID[1] = SIM->UIDMH;
+ UID[2] = SIM->UIDML;
+ UID[3] = SIM->UIDL;
+
+ // generate three CRC16's using different slices of the UUID
+ MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
+ MAC[1] = crcSlow((const uint8_t *)UID, 12);
+ MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
+
+ // The network stack expects an array of 6 bytes
+ // so we copy, and shift and copy from the half-word array to the byte array
+ mac[0] = MAC[0] >> 8;
+ mac[1] = MAC[0];
+ mac[2] = MAC[1] >> 8;
+ mac[3] = MAC[1];
+ mac[4] = MAC[2] >> 8;
+ mac[5] = MAC[2];
+
+ // We want to force bits [1:0] of the most significant byte [0]
+ // to be "10"
+ // http://en.wikipedia.org/wiki/MAC_address
+
+ mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
+ mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
+
+}
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld Thu Nov 08 11:46:34 2018 +0000
@@ -57,10 +57,6 @@
* the stack where main runs is determined via the RTOS. */
__stack_size__ = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
__heap_size__ = 0x6000;
#if !defined(MBED_APP_START)
@@ -92,32 +88,22 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
- /* The program code and other data goes into internal flash */
- /* Note: The uVisor expects this section at a fixed location, as specified by
- * the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_FLASH_OFFSET = 0x410;
- __UVISOR_FLASH_START = ORIGIN(m_interrupts) + __UVISOR_FLASH_OFFSET;
- .text __UVISOR_FLASH_START :
+ .text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -127,7 +113,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -202,57 +188,15 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
- /* uVisor own memory and private box memories
- /* If uVisor shares the SRAM with the OS/app, ensure that this section is
- * the first one after the VTOR relocation section. */
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x400;
- __UVISOR_SRAM_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* Protected uVisor own BSS section */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* Protected uVisor boxes' static memories */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > m_data
-
- /* Heap space for the page allocator
- /* If uVisor shares the SRAM with the OS/app, ensure that this section is
- * the first one after the uVisor BSS section. Otherwise, ensure it is the
- * first one after the VTOR relocation section. */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN(32);
- __uvisor_page_end = .;
- } > m_data_2
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
@@ -261,13 +205,13 @@
{
PROVIDE(__etext = LOADADDR(.data)); /* Define a global symbol at end of code, */
PROVIDE(__DATA_ROM = LOADADDR(.data)); /* Symbol is used by startup for data initialization. */
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data_2 AT > m_text
@@ -275,37 +219,6 @@
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
- /* uVisor configuration section
- * This section must be located after all other flash regions. */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uVisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* Pointers to the uVisor secure boxes configuration tables */
- /* Note: Do not add any further alignment here, as uVisor will need to have
- * access to the exact list of pointers. */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to allow
- * discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > m_text
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
@@ -326,7 +239,7 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
@@ -335,7 +248,7 @@
USB_RAM_START = .;
. += USB_RAM_GAP;
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data_2
@@ -343,14 +256,12 @@
.heap :
{
. = ALIGN(8);
- __uvisor_heap_start = .;
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
- __uvisor_heap_end = .;
} > m_data_2
m_usb_bdt USB_RAM_START (NOLOAD) :
@@ -373,11 +284,4 @@
ASSERT(__StackLimit >= __HeapLimit, "Region m_data_2 overflowed with stack and heap")
- /* Provide the physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(m_interrupts);
- __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);
- __uvisor_sram_start = ORIGIN(m_data);
- __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);
- __uvisor_public_sram_start = __uvisor_sram_start;
- __uvisor_public_sram_end = __uvisor_sram_end;
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S Thu Nov 08 11:46:34 2018 +0000
@@ -333,13 +333,6 @@
blx r0
#endif
-/* The call to uvisor_init() happens independently of uVisor being enabled or
- * not, so it is conditionally compiled only based on FEATURE_UVISOR. */
-#ifdef FEATURE_UVISOR
-/* Call uvisor_init() */
- ldr r0, =uvisor_init
- blx r0
-#endif /* FEATURE_UVISOR */
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -67,30 +67,30 @@
#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
-#define MCG_C1_FRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
-#define MCG_C2_LP_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
-#define MCG_C2_RANGE_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
-#define MCG_SC_FCRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
-#define MCG_C7_OSCSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
-#define MCG_C7_PLL32KREFSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
-#define MCG_C5_PLLREFSEL0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
+#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
+#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
-#define MCG_C5_PRDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
-#define MCG_C6_VDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C6) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
-#define SIM_CLKDIV1_OUTDIV1_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
-#define SIM_CLKDIV1_OUTDIV2_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
-#define SIM_CLKDIV1_OUTDIV3_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
-#define SIM_CLKDIV1_OUTDIV4_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
-#define SIM_SOPT1_OSC32KSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT1) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
-#define SIM_SOPT2_PLLFLLSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT2) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
/* MCG_S_CLKST definition. */
enum _mcg_clkout_stat
@@ -491,8 +491,7 @@
void CLOCK_SetSimConfig(sim_clock_config_t const *config)
{
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, config->clkdiv1);
-
+ SIM->CLKDIV1 = config->clkdiv1;
CLOCK_SetPllFllSelClock(config->pllFllSel);
CLOCK_SetEr32kClock(config->er32kSrc);
}
@@ -505,30 +504,30 @@
if (kCLOCK_UsbSrcExt == src)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&SIM->SOPT2, SIM_SOPT2_USBSRC_MASK);
+ SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
}
else
{
switch (freq)
{
case 120000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
break;
case 96000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
break;
case 72000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
break;
case 48000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
break;
default:
ret = false;
break;
}
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK, (uint32_t)src);
+ SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
}
CLOCK_EnableClock(kCLOCK_Usbfs0);
@@ -575,7 +574,7 @@
uint32_t freq;
/* If FLL is not enabled currently, then return 0U. */
- if ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
+ if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
{
return 0U;
}
@@ -596,7 +595,7 @@
uint32_t CLOCK_GetInternalRefClkFreq(void)
{
/* If MCGIRCLK is gated. */
- if (!(__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK))
+ if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
{
return 0U;
}
@@ -666,10 +665,10 @@
needDelay = false;
}
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C7, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(oscsel));
+ MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
if (kMCG_OscselOsc == oscsel)
{
- if (__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_EREFS_MASK)
+ if (MCG->C2 & MCG_C2_EREFS_MASK)
{
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
@@ -712,20 +711,20 @@
if (fcrdiv != curFcrdiv)
{
/* If fast IRC is in use currently, change to slow IRC. */
- if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK)))
+ if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(kMCG_IrcSlow));
+ MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
{
}
}
/* Update FCRDIV. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->SC, MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK, MCG_SC_FCRDIV(fcrdiv));
+ MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
}
/* Set internal reference clock selection. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(ircs));
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK, (uint8_t)enableMode);
+ MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
+ MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;
/* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
@@ -842,12 +841,12 @@
uint8_t mcg_c5 = 0U;
mcg_c5 |= MCG_C5_PRDIV0(config->prdiv);
- __FSL_CLOCK_SECURE_WRITE(&MCG->C5, mcg_c5); /* Disable the PLL first. */
+ MCG->C5 = mcg_c5; /* Disable the PLL first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C6, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(config->vdiv));
+ MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv);
/* Set enable mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C5, ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode));
+ MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode);
/* Wait for PLL lock. */
while (!(MCG->S & MCG_S_LOCK0_MASK))
@@ -862,25 +861,25 @@
if (kMCG_MonitorNone == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_CME0_MASK);
+ MCG->C6 &= ~MCG_C6_CME0_MASK;
}
else
{
if (kMCG_MonitorInt == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LOCRE0_MASK);
+ MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
}
else
{
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LOCRE0_MASK);
+ MCG->C2 |= MCG_C2_LOCRE0_MASK;
}
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_CME0_MASK);
+ MCG->C6 |= MCG_C6_CME0_MASK;
}
}
void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
{
- uint8_t mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
+ uint8_t mcg_c8 = MCG->C8;
mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
@@ -892,7 +891,7 @@
}
mcg_c8 |= MCG_C8_CME1_MASK;
}
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
+ MCG->C8 = mcg_c8;
}
void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
@@ -904,11 +903,11 @@
if (kMCG_MonitorNone == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_LOLIE0_MASK);
+ MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
}
else
{
- mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
+ mcg_c8 = MCG->C8;
mcg_c8 &= ~MCG_C8_LOCS1_MASK;
@@ -920,8 +919,8 @@
{
mcg_c8 |= MCG_C8_LOLRE_MASK;
}
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_LOLIE0_MASK);
+ MCG->C8 = mcg_c8;
+ MCG->C6 |= MCG_C6_LOLIE0_MASK;
}
}
@@ -930,7 +929,7 @@
uint32_t ret = 0U;
uint8_t mcg_s = MCG->S;
- if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_LOCS0_MASK)
+ if (MCG->SC & MCG_SC_LOCS0_MASK)
{
ret |= kMCG_Osc0LostFlag;
}
@@ -938,7 +937,7 @@
{
ret |= kMCG_Osc0InitFlag;
}
- if (__FSL_CLOCK_SECURE_READ(&MCG->C8) & MCG_C8_LOCS1_MASK)
+ if (MCG->C8 & MCG_C8_LOCS1_MASK)
{
ret |= kMCG_RtcOscLostFlag;
}
@@ -963,8 +962,8 @@
}
if (mask & kMCG_RtcOscLostFlag)
{
- reg = __FSL_CLOCK_SECURE_READ(&MCG->C8);
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, reg);
+ reg = MCG->C8;
+ MCG->C8 = reg;
}
if (mask & kMCG_Pll0LostFlag)
{
@@ -979,7 +978,7 @@
OSC_SetCapLoad(OSC0, config->capLoad);
OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, OSC_MODE_MASK, MCG_C2_RANGE(range) | (uint8_t)config->workMode);
+ MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
{
@@ -993,7 +992,7 @@
void CLOCK_DeinitOsc0(void)
{
OSC0->CR = 0U;
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, OSC_MODE_MASK);
+ MCG->C2 &= ~OSC_MODE_MASK;
}
status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
@@ -1040,21 +1039,21 @@
MCG->ATCVL = (uint8_t)actv;
MCG->ATCVH = (uint8_t)(actv >> 8U);
- mcg_sc = __FSL_CLOCK_SECURE_READ(&MCG->SC);
+ mcg_sc = MCG->SC;
mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK);
mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms));
- __FSL_CLOCK_SECURE_WRITE(&MCG->SC, (mcg_sc | MCG_SC_ATME_MASK));
+ MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
/* Wait for finished. */
- while (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATME_MASK)
+ while (MCG->SC & MCG_SC_ATME_MASK)
{
}
/* Error occurs? */
- if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATMF_MASK)
+ if (MCG->SC & MCG_SC_ATMF_MASK)
{
/* Clear the failed flag. */
- __FSL_CLOCK_SECURE_WRITE(&MCG->SC, mcg_sc);
+ MCG->SC = mcg_sc;
return kStatus_MCG_AtmHardwareFail;
}
@@ -1201,7 +1200,7 @@
/* Set CLKS and IREFS. */
MCG->C1 =
- ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
/* Wait and check status. */
@@ -1260,7 +1259,7 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_FRDIV(frdiv) /* FRDIV */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@@ -1317,7 +1316,7 @@
mcg_c4 = MCG->C4;
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/*
Errata: ERR007993
@@ -1333,8 +1332,8 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
- (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
/* Wait and check status. */
@@ -1378,13 +1377,13 @@
#endif
/* Change to FLL mode. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Set LP bit to enable the FLL */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
mcg_c4 = MCG->C4;
@@ -1402,7 +1401,7 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@@ -1445,7 +1444,7 @@
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Set LP. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1460,7 +1459,7 @@
#endif
/* Set LP bit to enter BLPE mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1473,10 +1472,10 @@
This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
but with this workflow, the source mode could be all modes except PEI/PBI.
*/
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/* Change to use external clock first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
/* Wait for CLKST clock status bits to show clock source is ext ref clk */
while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
@@ -1485,7 +1484,7 @@
}
/* Disable PLL first, then configure PLL. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@@ -1496,7 +1495,7 @@
}
/* Change to PLL mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 |= MCG_C6_PLLS_MASK;
/* Wait for PLL mode changed. */
while (!(MCG->S & MCG_S_PLLST_MASK))
@@ -1517,7 +1516,7 @@
#endif
/* Change to use PLL/FLL output clock first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
/* Wait for clock status bits to update */
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
@@ -1537,15 +1536,15 @@
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Disable low power */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
/* Disable PLL. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@@ -1563,9 +1562,9 @@
#endif
/* Disable low power */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
@@ -1592,13 +1591,13 @@
CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
/* If reset mode is not BLPI, first enter FBI mode. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
/* Enter BLPI mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1608,8 +1607,8 @@
CLOCK_SetExternalRefClkConfig(oscsel);
/* Set to FBE mode. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
- (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
@@ -1619,7 +1618,7 @@
}
/* In FBE now, start to enter BLPE. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1633,7 +1632,7 @@
CLOCK_SetPbeMode(pllcs, config);
/* Change to use PLL output clock. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
{
}
@@ -1693,7 +1692,7 @@
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
@@ -1739,7 +1738,7 @@
}
else
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
@@ -1763,7 +1762,7 @@
}
else
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, (uint32_t)kMCG_PllEnableIndependent);
+ MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
}
return kStatus_Success;
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.h Thu Nov 08 11:46:34 2018 +0000
@@ -31,52 +31,8 @@
#ifndef _FSL_CLOCK_H_
#define _FSL_CLOCK_H_
-#include "core_cmSecureAccess.h"
#include "fsl_common.h"
-#ifdef FEATURE_UVISOR
-
-/* We cannot use the register gateway to secure this access,
- * since some accesses use dynamically computed addresses and
- * values, which are not supported by the register gateway.
- * Therefore, these accesses are implemented using the uVisor
- * secure access.
- */
-#define __FSL_CLOCK_SECURE_WRITE(addr, val) \
- ADDRESS_WRITE(*addr, addr, val)
-
-#define __FSL_CLOCK_SECURE_READ(addr) \
- ADDRESS_READ(*addr, addr)
-
-#define __FSL_CLOCK_SECURE_BITS_SET(addr, mask) \
- __FSL_CLOCK_SECURE_WRITE(addr, __FSL_CLOCK_SECURE_READ(addr) | (mask))
-
-#define __FSL_CLOCK_SECURE_BITS_CLEAR(addr, mask) \
- __FSL_CLOCK_SECURE_WRITE(addr, __FSL_CLOCK_SECURE_READ(addr) & ~(mask))
-
-#define __FSL_CLOCK_SECURE_BITS_SET_VALUE(addr, mask, val) \
- __FSL_CLOCK_SECURE_WRITE(addr, (__FSL_CLOCK_SECURE_READ(addr) & ~(mask)) | ((val) & (mask)))
-
-#else
-
-/* Fallback implementation. */
-#define __FSL_CLOCK_SECURE_WRITE(addr, val) \
- SECURE_WRITE(addr, val)
-
-#define __FSL_CLOCK_SECURE_READ(addr) \
- SECURE_READ(addr)
-
-#define __FSL_CLOCK_SECURE_BITS_SET(addr, mask) \
- SECURE_BITS_SET(addr, mask)
-
-#define __FSL_CLOCK_SECURE_BITS_CLEAR(addr, mask) \
- SECURE_BITS_CLEAR(addr, mask)
-
-#define __FSL_CLOCK_SECURE_BITS_SET_VALUE(addr, mask, val) \
- SECURE_BITS_SET_VALUE(addr, mask, val)
-
-#endif
-
/*! @addtogroup clock */
/*! @{ */
@@ -709,7 +665,7 @@
static inline void CLOCK_EnableClock(clock_ip_name_t name)
{
uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
- __FSL_CLOCK_SECURE_BITS_SET((volatile uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)));
+ (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
}
/*!
@@ -720,7 +676,7 @@
static inline void CLOCK_DisableClock(clock_ip_name_t name)
{
uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
- __FSL_CLOCK_SECURE_BITS_CLEAR((volatile uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)));
+ (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
}
/*!
@@ -730,7 +686,7 @@
*/
static inline void CLOCK_SetEr32kClock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT1, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(src));
+ SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
}
/*!
@@ -740,7 +696,7 @@
*/
static inline void CLOCK_SetSdhc0Clock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
}
/*!
@@ -750,7 +706,7 @@
*/
static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
}
/*!
@@ -760,7 +716,7 @@
*/
static inline void CLOCK_SetRmii0Clock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
}
/*!
@@ -770,7 +726,7 @@
*/
static inline void CLOCK_SetTraceClock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
}
/*!
@@ -780,7 +736,7 @@
*/
static inline void CLOCK_SetPllFllSelClock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
}
/*!
@@ -790,7 +746,7 @@
*/
static inline void CLOCK_SetClkOutClock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
}
/*!
@@ -800,7 +756,7 @@
*/
static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(src));
+ SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
}
/*! @brief Enable USB FS clock.
@@ -836,11 +792,8 @@
*/
static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
{
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1,
- SIM_CLKDIV1_OUTDIV1(outdiv1) |
- SIM_CLKDIV1_OUTDIV2(outdiv2) |
- SIM_CLKDIV1_OUTDIV3(outdiv3) |
- SIM_CLKDIV1_OUTDIV4(outdiv4));
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
+ SIM_CLKDIV1_OUTDIV4(outdiv4);
}
/*!
@@ -933,7 +886,7 @@
*/
static inline void CLOCK_SetSimSafeDivs(void)
{
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, 0x01240000UL);
+ SIM->CLKDIV1 = 0x01240000U;
}
/*! @name MCG frequency functions. */
@@ -1009,11 +962,11 @@
{
if (enable)
{
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
}
else
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
}
}
@@ -1082,7 +1035,7 @@
*/
static inline void CLOCK_DisablePll0(void)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
+ MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
}
/*!
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -70,6 +70,7 @@
PIT_StopTimer(PIT, kPIT_Chnl_2);
PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
+ PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
NVIC_SetVector(PIT3_IRQn, (uint32_t) pit_isr);
NVIC_EnableIRQ(PIT3_IRQn);
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
@@ -136,3 +137,16 @@
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
+
+void us_ticker_free(void)
+{
+ PIT_StartTimer(PIT, kPIT_Chnl_3);
+ PIT_StartTimer(PIT, kPIT_Chnl_2);
+ PIT_StartTimer(PIT, kPIT_Chnl_1);
+ PIT_StartTimer(PIT, kPIT_Chnl_0);
+
+ PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+ NVIC_DisableIRQ(PIT3_IRQn);
+
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/PeripheralPins.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/PeripheralPins.h Thu Nov 08 11:46:34 2018 +0000 @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H @@ -47,4 +47,11 @@ /************PWM***************/ extern const PinMap PinMap_PWM[]; +#if DEVICE_QSPI +/************QSPI***************/ +extern const PinMap PinMap_QSPI_DATA[]; +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; #endif + +#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/flash_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -102,8 +102,13 @@
uint32_t devicesize = 0;
uint32_t startaddr = 0;
+#if defined(TARGET_RAPIDIOT)
+ startaddr = MBED_ROM_START;
+ devicesize = MBED_ROM_SIZE;
+#else
FLASH_GetProperty((flash_config_t *)&obj->flash_config, kFLASH_PropertyPflashBlockBaseAddr, &startaddr);
FLASH_GetProperty((flash_config_t *)&obj->flash_config, kFLASH_PropertyPflashTotalSize, &devicesize);
+#endif
if ((address >= startaddr) && (address < (startaddr + devicesize))) {
FLASH_GetProperty((flash_config_t *)&obj->flash_config, kFLASH_PropertyPflashSectorSize, §orsize);
@@ -119,20 +124,28 @@
uint32_t flash_get_start_address(const flash_t *obj)
{
+#if defined(TARGET_RAPIDIOT)
+ return MBED_ROM_START;
+#else
uint32_t startaddr = 0;
FLASH_GetProperty((flash_config_t *)&obj->flash_config, kFLASH_PropertyPflashBlockBaseAddr, &startaddr);
return startaddr;
+#endif
}
uint32_t flash_get_size(const flash_t *obj)
{
+#if defined(TARGET_RAPIDIOT)
+ return MBED_ROM_SIZE;
+#else
uint32_t devicesize = 0;
FLASH_GetProperty((flash_config_t *)&obj->flash_config, kFLASH_PropertyPflashTotalSize, &devicesize);
return devicesize;
+#endif
}
#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -33,8 +33,6 @@
static bool lp_ticker_inited = false;
-extern void rtc_setup_oscillator(RTC_Type *base);
-
static void lptmr_isr(void)
{
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
@@ -52,9 +50,6 @@
/* Setup high resolution clock - LPTMR */
LPTMR_GetDefaultConfig(&lptmrConfig);
- /* Setup the RTC 32KHz oscillator */
- CLOCK_EnableClock(kCLOCK_Rtc0);
- rtc_setup_oscillator(RTC);
/* Use 32kHz drive */
CLOCK_SetXtal32Freq(OSC32K_CLK_HZ);
@@ -69,6 +64,7 @@
lp_ticker_inited = true;
} else {
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
+ NVIC_EnableIRQ(LPTMR0_IRQn);
}
}
@@ -119,10 +115,8 @@
void lp_ticker_free(void)
{
-#ifndef FEATURE_UVISOR
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
NVIC_DisableIRQ(LPTMR0_IRQn);
-#endif
}
#endif /* DEVICE_LPTICKER */
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -95,6 +95,12 @@
flash_config_t flash_config;
};
+#if DEVICE_QSPI
+struct qspi_s {
+ uint32_t instance;
+};
+#endif
+
#include "gpio_object.h"
#ifdef __cplusplus
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/qspi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,403 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if DEVICE_QSPI
+
+#include "qspi_api.h"
+#include "mbed_error.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "qspi_device.h"
+
+/* Look-up table entry indices */
+#define LUT1_SEQ_INDEX 0 // Pre-defined read sequence
+#define LUT2_SEQ_INDEX 4 // Pre-defined write sequence
+#define LUT3_SEQ_INDEX 8 // User-define sequence
+/* Minimum write size */
+#define MIN_SIZE 16 // At least four words of data must be written into the TX Buffer
+
+/* Array of QSPI peripheral base address. */
+static QuadSPI_Type *const qspi_addrs[] = QuadSPI_BASE_PTRS;
+
+extern uint32_t qspi_get_freq(void);
+
+qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
+{
+ uint32_t clockSourceFreq = 0;
+ qspi_config_t config = {0};
+
+ uint32_t qspiio0name = pinmap_peripheral(io0, PinMap_QSPI_DATA);
+ uint32_t qspiio1name = pinmap_peripheral(io1, PinMap_QSPI_DATA);
+ uint32_t qspiio2name = pinmap_peripheral(io2, PinMap_QSPI_DATA);
+ uint32_t qspiio3name = pinmap_peripheral(io3, PinMap_QSPI_DATA);
+ uint32_t qspiclkname = pinmap_peripheral(sclk, PinMap_QSPI_SCLK);
+ uint32_t qspisselname = pinmap_peripheral(ssel, PinMap_QSPI_SSEL);
+
+ uint32_t qspi_data_first = pinmap_merge(qspiio0name, qspiio1name);
+ uint32_t qspi_data_second = pinmap_merge(qspiio2name, qspiio3name);
+ uint32_t qspi_data_third = pinmap_merge(qspiclkname, qspisselname);
+
+ if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
+ qspi_data_first != qspi_data_third) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ clockSourceFreq = qspi_get_freq();
+
+ /*Get QSPI default settings and configure the qspi */
+ QSPI_GetDefaultQspiConfig(&config);
+
+ /*Set AHB buffer size for reading data through AHB bus */
+ config.AHBbufferSize[3] = FLASH_PAGE_SIZE;
+
+ // tested all combinations, take first
+ obj->instance = qspi_data_first;
+
+ QSPI_Init(qspi_addrs[obj->instance], &config, clockSourceFreq);
+
+ /* Copy the pre-defined LUT table */
+ memcpy(single_config.lookuptable, lut, sizeof(uint32_t) * FSL_FEATURE_QSPI_LUT_DEPTH);
+
+ /*According to serial flash feature to configure flash settings */
+ QSPI_SetFlashConfig(qspi_addrs[obj->instance], &single_config);
+
+ qspi_frequency(obj, hz);
+
+ pinmap_pinout(io0, PinMap_QSPI_DATA);
+ pinmap_pinout(io1, PinMap_QSPI_DATA);
+ pinmap_pinout(io2, PinMap_QSPI_DATA);
+ pinmap_pinout(io3, PinMap_QSPI_DATA);
+
+ pinmap_pinout(sclk, PinMap_QSPI_SCLK);
+ pinmap_pinout(ssel, PinMap_QSPI_SSEL);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_free(qspi_t *obj)
+{
+ QSPI_Deinit(qspi_addrs[obj->instance]);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_frequency(qspi_t *obj, int hz)
+{
+ qspi_status_t status = QSPI_STATUS_OK;
+ QuadSPI_Type *base = qspi_addrs[obj->instance];
+ int div = qspi_get_freq() / hz;
+
+ if ((qspi_get_freq() % hz) == 0) {
+ /* Incase the exact requested baud rate can be derived then set right div,
+ * else set baudrate to the closest lower value
+ */
+ div--;
+ }
+
+ if (div > 16 || div < 1) {
+ status = QSPI_STATUS_INVALID_PARAMETER;
+ return status;
+ }
+
+
+ /* Configure QSPI */
+ QSPI_Enable(base, false);
+
+ /* Set the divider of QSPI clock */
+ base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
+ base->MCR |= QuadSPI_MCR_SCLKCFG(div);
+
+ QSPI_Enable(base, true);
+
+ return status;
+}
+
+static void qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
+{
+ uint32_t lut_seq[4] = {0, 0, 0, 0};
+ uint8_t instr1 = QSPI_CMD, instr2 = 0;
+ uint8_t pad1 = command->instruction.bus_width, pad2 = 0;
+ uint8_t op1 = command->instruction.value, op2 = 0;
+ bool set_jmp_instr = false;
+ QuadSPI_Type *base = qspi_addrs[obj->instance];
+ uint32_t addr = FSL_FEATURE_QSPI_AMBA_BASE;
+
+ /* Check if the flash address is provided */
+ if (command->address.disabled) {
+ /* Check if a second instruction is needed, this is for register accesses */
+ if (tx_data != NULL && tx_size) {
+ instr2 = QSPI_WRITE;
+ pad2 = command->data.bus_width;
+ op2 = tx_size;
+ /* Read and write pointers of the TX buffer are reset to 0 */
+ QSPI_ClearFifo(base, kQSPI_TxFifo);
+ /* Clear underrun error flag */
+ QSPI_ClearErrorFlag(base, kQSPI_TxBufferUnderrun);
+ }
+ if (rx_data != NULL && rx_size) {
+ instr2 = QSPI_READ;
+ pad2 = command->data.bus_width;
+ op2 = rx_size;
+ /* Read and write pointers of the RX buffer are reset to 0 */
+ QSPI_ClearFifo(base, kQSPI_RxFifo);
+ }
+
+ /* Setup the LUT entry */
+ lut_seq[0] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
+ } else {
+ instr2 = QSPI_ADDR;
+ pad2 = command->address.bus_width;
+ /* Number of address bits */
+ op2 = (8 * (command->address.size + 1));
+ addr += command->address.value;
+
+ /* Setup the first LUT entry */
+ lut_seq[0] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
+
+ /* Clear the variables */
+ instr1 = instr2 = 0;
+ pad1 = pad2 = 0;
+ op1 = op2 = 0;
+
+ /* Check if a second LUT entry is needed */
+ if (tx_data != NULL && tx_size) {
+ instr1 = QSPI_WRITE;
+ pad1 = command->data.bus_width;
+ op1 = 0x80;
+ /* Read and write pointers of the TX buffer are reset to 0 */
+ QSPI_ClearFifo(base, kQSPI_TxFifo);
+ /* Clear underrun error flag */
+ QSPI_ClearErrorFlag(base, kQSPI_TxBufferUnderrun);
+ }
+ if (rx_data != NULL && rx_size) {
+ instr1 = QSPI_READ;
+ pad1 = command->data.bus_width;
+ op1 = 0x80;
+ /* Read operations need a jump command at the end of the sequence */
+ set_jmp_instr = true;
+ /* Read and write pointers of the TX buffer are reset to 0 */
+ QSPI_ClearFifo(base, kQSPI_RxFifo);
+ }
+
+ /* Setup more LUT entries if needed */
+ if (instr1 != 0) {
+ /* Check if we need to add dummy entries */
+ if (command->dummy_count > 0) {
+ instr2 = instr1;
+ pad2 = pad1;
+ op2 = op1;
+
+ instr1 = QSPI_DUMMY;
+ pad1 = command->address.bus_width;
+ op1 = command->dummy_count;
+ }
+ /* Check if need to add jump command entry */
+ if (set_jmp_instr) {
+ /* Need to add a jump command in the sequence */
+ if (command->dummy_count > 0) {
+ /* Third LUT entry for jump command */
+ lut_seq[2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, LUT3_SEQ_INDEX, 0, 0, 0);
+ } else {
+ /* As there is no dummy we have space in the second LUT entry to add jump command */
+ instr2 = QSPI_JMP_ON_CS;
+ pad2 = QSPI_PAD_1;
+ op2 = 8;
+ }
+ }
+ /* Second LUT entry for read & write operations */
+ lut_seq[1] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
+ }
+ }
+
+ /* Update the LUT registers from index 8, prior entries have pre-defined LUT sequences
+ * which is used when the instruction is disabled
+ */
+ if (!(command->instruction.disabled)) {
+ QSPI_UpdateLUT(base, LUT3_SEQ_INDEX, lut_seq);
+ }
+
+ /* Setup the address */
+ QSPI_SetIPCommandAddress(base, addr);
+
+ /* Reset AHB domain and serial flash domain flops */
+ QSPI_SoftwareReset(base);
+ while (QSPI_GetStatusFlags(base) & kQSPI_Busy) {
+ }
+}
+
+qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
+{
+ uint32_t to_write = *length;
+ uint8_t *data_send = (uint8_t *)data;
+ QuadSPI_Type *base = qspi_addrs[obj->instance];
+
+ /* At least four words of data must be written to the TX buffer */
+ if (to_write < MIN_SIZE) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ /* Enforce word-sized access */
+ if ((to_write & 0x3) != 0) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ /* Prepare the write command */
+ qspi_prepare_command(obj, command, data, to_write, NULL, 0);
+
+ QSPI_SetIPCommandSize(base, to_write);
+
+ if (to_write > (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4)) {
+ /* First write some data into TXFIFO to prevent underrun */
+ QSPI_WriteBlocking(base, (uint32_t *)data_send, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+ data_send += (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+ to_write -= (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+ } else {
+ QSPI_WriteBlocking(base, (uint32_t *)data_send, to_write);
+ to_write = 0;
+ }
+
+ /* Start the program */
+ if (command->instruction.disabled) {
+ /* If no instruction provided then use the pre-defined write sequence */
+ QSPI_ExecuteIPCommand(base, LUT2_SEQ_INDEX);
+ } else {
+ /* Use the user-defined write sequence */
+ QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
+ }
+
+ /* Write the remaining data to TXFIFO */
+ if (to_write) {
+ QSPI_WriteBlocking(base, (uint32_t *)data_send, to_write);
+ }
+
+ while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
+{
+ uint32_t dest_addr = FSL_FEATURE_QSPI_AMBA_BASE + command->address.value;
+ uint32_t to_read = *length;
+ QuadSPI_Type *base = qspi_addrs[obj->instance];
+
+ /* Enforce word-sized access */
+ if ((to_read & 0x3) != 0) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ /* Prepare for read command */
+ qspi_prepare_command(obj, command, NULL, 0, data, to_read);
+
+ /* Point to the read sequence in the LUT */
+ if (command->instruction.disabled) {
+ /* If no instruction provided then use the pre-defined read sequence */
+ QSPI_ExecuteAHBCommand(base, LUT1_SEQ_INDEX);
+ } else {
+ /* Use the user-defined write sequence */
+ QSPI_ExecuteAHBCommand(base, LUT3_SEQ_INDEX);
+ }
+
+ for (uint32_t i = 0; i < to_read / 4; i++) {
+ ((uint32_t*)data)[i] = *((uint32_t *)(dest_addr) + i);
+ }
+
+ while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_AHBAccess)) {
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
+{
+ QuadSPI_Type *base = qspi_addrs[obj->instance];
+
+ if (tx_size > MIN_SIZE || rx_size > MIN_SIZE) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) {
+ /* Setup the sequence in the Look-up Table (LUT) */
+ qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
+
+ /* Execute the sequence */
+ QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
+ while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
+ }
+ } else {
+ if (tx_data != NULL && tx_size) {
+ /* Transmit data to QSPI */
+ /* Need to write at least 16 bytes into TX buffer */
+ uint8_t val[MIN_SIZE];
+ memset(val, 0, sizeof(val));
+ memcpy(val, tx_data, tx_size);
+
+ /* Setup the sequence in the Look-up Table (LUT) */
+ qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
+
+ /* First write some data into TXFIFO to prevent from underrun */
+ QSPI_WriteBlocking(base, (uint32_t *)val, MIN_SIZE);
+
+ /* Use the user-defined write sequence */
+ QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
+ while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
+ }
+ }
+
+ if (rx_data != NULL && rx_size) {
+ /* Receive data from QSPI */
+ uint32_t val[MIN_SIZE / 4];
+ memset(val, 0, sizeof(val));
+
+ /* Read data from the IP read buffers */
+ QSPI_SetReadDataArea(base, kQSPI_ReadIP);
+
+ /* Setup the sequence in the Look-up Table (LUT) */
+ qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
+
+ /* Execute the sequence */
+ QSPI_SetIPCommandSize(base, rx_size);
+ QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
+ while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
+ }
+
+ for (uint32_t i = 0, j =0; i < rx_size; i += 4, j++) {
+ val[j] = QSPI_ReadData(base);
+ }
+
+ memcpy(rx_data, val, rx_size);
+ }
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+#endif
+
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -21,8 +21,6 @@
#include "fsl_rtc.h"
#include "PeripheralPins.h"
-extern void rtc_setup_oscillator(RTC_Type *base);
-
static bool rtc_time_set = false;
void rtc_init(void)
@@ -32,8 +30,6 @@
RTC_GetDefaultConfig(&rtcConfig);
RTC_Init(RTC, &rtcConfig);
- /* Setup the RTC 32KHz oscillator */
- rtc_setup_oscillator(RTC);
RTC_StartTimer(RTC);
}
--- a/targets/TARGET_Freescale/mbed_rtx.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Freescale/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000 @@ -89,6 +89,12 @@ #define INITIAL_SP (0x20030000UL) #endif +#elif defined(TARGET_SDT64B) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20030000UL) +#endif + #elif defined(TARGET_KW24D) #ifndef INITIAL_SP
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/max32600.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/max32600.ld Thu Nov 08 11:46:34 2018 +0000
@@ -120,13 +120,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -134,14 +134,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -255,3 +255,8 @@
{
return rtc_read64();
}
+
+void lp_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -268,3 +268,8 @@
NVIC_SetPendingIRQ(US_TIMER_IRQn);
}
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/max32610.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/max32610.ld Thu Nov 08 11:46:34 2018 +0000
@@ -120,13 +120,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -134,14 +134,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32610/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -252,3 +252,8 @@
{
return rtc_read64();
}
+
+void lp_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -268,3 +268,8 @@
NVIC_SetPendingIRQ(US_TIMER_IRQn);
}
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/max32620.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,13 +114,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +128,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -306,3 +306,8 @@
{
return rtc_read64();
}
+
+void lp_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -299,3 +299,8 @@
NVIC_SetPendingIRQ(US_TIMER_IRQn);
}
}
+
+void us_ticker_free(void)
+{
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = MXC_BASE_UART0,
+ UART_1 = MXC_BASE_UART1,
+ UART_2 = MXC_BASE_UART2,
+ UART_3 = MXC_BASE_UART3,
+ STDIO_UART = UART_1
+} UARTName;
+
+typedef enum {
+ I2C_0 = MXC_BASE_I2CM0,
+ I2C_1 = MXC_BASE_I2CM1,
+ I2C_2 = MXC_BASE_I2CM2
+} I2CName;
+
+typedef enum {
+ SPI_0 = MXC_BASE_SPIM0,
+ SPI_1 = MXC_BASE_SPIM1,
+ SPI_2 = MXC_BASE_SPIM2
+} SPIName;
+
+typedef enum {
+ PWM_0 = MXC_BASE_PT0,
+ PWM_1 = MXC_BASE_PT1,
+ PWM_2 = MXC_BASE_PT2,
+ PWM_3 = MXC_BASE_PT3,
+ PWM_4 = MXC_BASE_PT4,
+ PWM_5 = MXC_BASE_PT5,
+ PWM_6 = MXC_BASE_PT6,
+ PWM_7 = MXC_BASE_PT7,
+ PWM_8 = MXC_BASE_PT8,
+ PWM_9 = MXC_BASE_PT9,
+ PWM_10 = MXC_BASE_PT10,
+ PWM_11 = MXC_BASE_PT11,
+ PWM_12 = MXC_BASE_PT12,
+ PWM_13 = MXC_BASE_PT13,
+ PWM_14 = MXC_BASE_PT14,
+ PWM_15 = MXC_BASE_PT15
+} PWMName;
+
+typedef enum {
+ ADC = MXC_BASE_ADC
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,198 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z,
+ PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL
+} PinDirection;
+
+#define PORT_SHIFT 12
+#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
+#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+
+typedef enum {
+ P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
+ P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
+ P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
+ P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
+ P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
+ P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7,
+ P6_0 = (6 << PORT_SHIFT),
+
+ // Analog input pins
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, AIN_10, AIN_11,
+
+ // Analog
+ A0 = AIN_0,
+ A1 = AIN_1,
+ A2 = AIN_2,
+ A3 = AIN_3,
+
+ // General Pin Input Output (GPIO)
+ GPIO0 = P1_4,
+ GPIO1 = P1_5,
+ GPIO2 = P4_0,
+ GPIO3 = P4_1,
+ GPIO4 = P4_2,
+ GPIO5 = P4_3,
+ GPIO6 = P5_6,
+
+ //Purse Width Modulation (PWM)
+ PWM0 = GPIO2,
+ PWM1 = GPIO3,
+ PWM2 = GPIO0,
+ PWM3 = GPIO1,
+
+ // LEDs
+ LED0 = GPIO0,
+ LED1 = GPIO1,
+ LED2 = GPIO2,
+ LED3 = NOT_CONNECTED,
+ LED4 = NOT_CONNECTED,
+
+ LED_RED = LED0,
+ LED_GREEN = LED1,
+ LED_BLUE = LED2,
+
+ // USB bridge and SWD UART connected UART pins
+ USBTX = P2_1,
+ USBRX = P2_0,
+ STDIO_UART_TX = USBTX,
+ STDIO_UART_RX = USBRX,
+
+ // UART pins
+ UART0_RX = P0_0,
+ UART0_TX = P0_1,
+ UART0_CTS = P0_2,
+ UART0_RTS = P0_3,
+
+ UART1_RX = P2_0,
+ UART1_TX = P2_1,
+ UART1_CTS = P2_2,
+ UART1_RTS = P2_3,
+
+ UART2_RX = P3_0,
+ UART2_TX = P3_1,
+ UART2_CTS = P3_2,
+ UART2_RTS = P3_3,
+
+ // I2C pins
+ I2C0_SCL = P1_7,
+ I2C0_SDA = P1_6,
+
+ I2C1_SCL = P3_5,
+ I2C1_SDA = P3_4,
+
+ I2C2_SCL = P6_0,
+ I2C2_SDA = P5_7,
+
+ // SPI pins
+ SPI0_SCK = P0_4,
+ SPI0_MOSI = P0_5,
+ SPI0_MISO = P0_6,
+ SPI0_SS0 = P0_7,
+ SPI0_SS1 = P4_4,
+ SPI0_SS2 = P4_5,
+
+ SPI1_SCK = P1_0,
+ SPI1_MOSI = P1_1,
+ SPI1_MISO = P1_2,
+ SPI1_SS0 = P1_3,
+ SPI1_SS1 = P3_6,
+ SPI1_SS2 = P3_7,
+
+ SPI2_SCK = P2_4,
+ SPI2_MOSI = P2_5,
+ SPI2_MISO = P2_6,
+ SPI2_SS0 = P2_7,
+ SPI2_SS1 = P4_6,
+ SPI2_SS2 = P4_7,
+
+ SPI3_SCK = P5_0,
+ SPI3_MOSI = P5_1,
+ SPI3_MISO = P5_2,
+ SPI3_SS0 = P5_3,
+ SPI3_SS1 = P5_4,
+ SPI3_SS2 = P5_5,
+
+ // SWD UART
+ SWD_TGT_TX = UART1_TX,
+ SWD_TGT_RX = UART1_RX,
+ SWD_TGT_CTS = UART1_CTS,
+ SWD_TGT_RTS = UART1_RTS,
+
+ // Generics
+ SERIAL_TX = UART0_TX,
+ SERIAL_RX = UART0_RX,
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_SS0,
+ PWM_OUT = PWM0,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullUp,
+ PullDown,
+ OpenDrain,
+ PullNone,
+ PullDefault = PullUp
+} PinMode;
+
+typedef enum {
+ LED_ON = 0,
+ LED_OFF = 1
+} LedStates;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32620C/device/TOOLCHAIN_GCC_ARM/max32620.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620C/device/TOOLCHAIN_GCC_ARM/max32620.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,13 +114,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +128,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = MXC_BASE_UART0,
+ UART_1 = MXC_BASE_UART1,
+ UART_2 = MXC_BASE_UART2,
+ STDIO_UART = UART_1
+} UARTName;
+
+typedef enum {
+ I2C_0 = MXC_BASE_I2CM0,
+ I2C_1 = MXC_BASE_I2CM1
+} I2CName;
+
+typedef enum {
+ SPI_0 = MXC_BASE_SPIM0,
+ SPI_1 = MXC_BASE_SPIM1,
+ SPI_2 = MXC_BASE_SPIM2
+} SPIName;
+
+typedef enum {
+ PWM_0 = MXC_BASE_PT0,
+ PWM_1 = MXC_BASE_PT1,
+ PWM_2 = MXC_BASE_PT2,
+ PWM_3 = MXC_BASE_PT3,
+ PWM_4 = MXC_BASE_PT4,
+ PWM_5 = MXC_BASE_PT5,
+ PWM_6 = MXC_BASE_PT6,
+ PWM_7 = MXC_BASE_PT7,
+ PWM_8 = MXC_BASE_PT8,
+ PWM_9 = MXC_BASE_PT9,
+ PWM_10 = MXC_BASE_PT10,
+ PWM_11 = MXC_BASE_PT11,
+ PWM_12 = MXC_BASE_PT12,
+ PWM_13 = MXC_BASE_PT13,
+ PWM_14 = MXC_BASE_PT14,
+ PWM_15 = MXC_BASE_PT15
+} PWMName;
+
+typedef enum {
+ ADC = MXC_BASE_ADC
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,157 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT = 0, /* MXC_V_GPIO_OUT_MODE_HIGH_Z,*/
+ PIN_OUTPUT = 1 /* MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE */
+} PinDirection;
+
+#define PORT_SHIFT 12
+#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
+#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+
+typedef enum {
+ P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
+ P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
+ P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
+ P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
+ P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
+
+ // Analog input pins
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
+
+ // LEDs
+ LED1 = P2_4,
+ LED2 = P2_5,
+ LED3 = P2_6,
+ LED4 = LED1,
+ LED_RED = LED1,
+ LED_GREEN = LED2,
+ LED_BLUE = LED3,
+
+ // Push button
+ SW1 = P2_7,
+ // Standardized button names
+ BUTTON1 = SW1,
+
+ // USB bridge connected UART pins
+ USBTX = P2_1,
+ USBRX = P2_0,
+ STDIO_UART_TX = USBTX,
+ STDIO_UART_RX = USBRX,
+
+ // I2C pins
+ I2C0_SCL = P1_7,
+ I2C0_SDA = P1_6,
+
+ I2C1_SCL = P3_5,
+ I2C1_SDA = P3_4,
+
+ // UART pins
+ UART0_RX = P0_0,
+ UART0_TX = P0_1,
+ UART0_CTS = P0_2,
+ UART0_RTS = P0_3,
+
+ UART1_RX = P2_0,
+ UART1_TX = P2_1,
+
+ UART2_RX = P3_0,
+ UART2_TX = P3_1,
+ UART2_CTS = P3_2,
+ UART2_RTS = P3_3,
+
+ // SPI pins
+ SPI0_SCK = P0_4,
+ SPI0_MOSI = P0_5,
+ SPI0_MISO = P0_6,
+ SPI0_SS = P0_7,
+
+ SPI1_SCK = P1_0,
+ SPI1_MOSI = P1_1,
+ SPI1_MISO = P1_2,
+ SPI1_SS = P1_3,
+
+ SPI2_SCK = P2_4,
+ SPI2_MOSI = P2_5,
+ SPI2_MISO = P2_6,
+ SPI2_SS = P2_7,
+
+ // Default peripherals defines
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+
+ UART_RX = UART0_RX,
+ UART_TX = UART0_TX,
+ UART_CTS = UART0_CTS,
+ UART_RTS = UART0_RTS,
+
+ SPI_SCK = SPI0_SCK,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SS = SPI0_SS,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullUp,
+ PullDown,
+ OpenDrain,
+ PullNone,
+ PullDefault = PullUp
+} PinMode;
+
+typedef enum {
+ LED_ON = 0,
+ LED_OFF = 1
+} LedStates;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO/low_level_init.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,54 @@
+/*******************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "cmsis.h"
+#include "ioman_regs.h"
+#include "gpio_regs.h"
+
+//******************************************************************************
+// This function will get called early in system initialization
+void low_level_init(void)
+{
+ /* The MAX32625PICO board utilizes a bootloader that can leave some
+ * peripherals in a partially configured state. This function resets
+ * those to allow proper initialization.
+ */
+ MXC_IOMAN->uart0_req = 0x0; // Clear any requests
+ MXC_IOMAN->uart1_req = 0x0; // Clear any requests
+
+ MXC_GPIO->inten[2] = 0x0; // Clear interrupt enable
+ MXC_GPIO->int_mode[2] = 0x0; // Clear interrupt mode
+ MXC_GPIO->in_mode[2] = 0x22222222; // Clear input mode
+ MXC_GPIO->out_val[2] = 0x0; // Clear output value
+ MXC_GPIO->out_mode[2] = 0xFFFFFFFF; // Clear output mode
+}
--- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO_BASE/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = MXC_BASE_UART0,
- UART_1 = MXC_BASE_UART1,
- UART_2 = MXC_BASE_UART2,
- STDIO_UART = UART_1
-} UARTName;
-
-typedef enum {
- I2C_0 = MXC_BASE_I2CM0,
- I2C_1 = MXC_BASE_I2CM1
-} I2CName;
-
-typedef enum {
- SPI_0 = MXC_BASE_SPIM0,
- SPI_1 = MXC_BASE_SPIM1,
- SPI_2 = MXC_BASE_SPIM2
-} SPIName;
-
-typedef enum {
- PWM_0 = MXC_BASE_PT0,
- PWM_1 = MXC_BASE_PT1,
- PWM_2 = MXC_BASE_PT2,
- PWM_3 = MXC_BASE_PT3,
- PWM_4 = MXC_BASE_PT4,
- PWM_5 = MXC_BASE_PT5,
- PWM_6 = MXC_BASE_PT6,
- PWM_7 = MXC_BASE_PT7,
- PWM_8 = MXC_BASE_PT8,
- PWM_9 = MXC_BASE_PT9,
- PWM_10 = MXC_BASE_PT10,
- PWM_11 = MXC_BASE_PT11,
- PWM_12 = MXC_BASE_PT12,
- PWM_13 = MXC_BASE_PT13,
- PWM_14 = MXC_BASE_PT14,
- PWM_15 = MXC_BASE_PT15
-} PWMName;
-
-typedef enum {
- ADC = MXC_BASE_ADC
-} ADCName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO_BASE/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,157 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "gpio_regs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT = 0, /* MXC_V_GPIO_OUT_MODE_HIGH_Z,*/
- PIN_OUTPUT = 1 /* MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE */
-} PinDirection;
-
-#define PORT_SHIFT 12
-#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
-#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
-
-#define NOT_CONNECTED (int)0xFFFFFFFF
-
-typedef enum {
- P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
- P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
- P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
- P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
- P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
-
- // Analog input pins
- AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
-
- // LEDs
- LED1 = P2_4,
- LED2 = P2_5,
- LED3 = P2_6,
- LED4 = LED1,
- LED_RED = LED1,
- LED_GREEN = LED2,
- LED_BLUE = LED3,
-
- // Push button
- SW1 = P2_7,
- // Standardized button names
- BUTTON1 = SW1,
-
- // USB bridge connected UART pins
- USBTX = P2_1,
- USBRX = P2_0,
- STDIO_UART_TX = USBTX,
- STDIO_UART_RX = USBRX,
-
- // I2C pins
- I2C0_SCL = P1_7,
- I2C0_SDA = P1_6,
-
- I2C1_SCL = P3_5,
- I2C1_SDA = P3_4,
-
- // UART pins
- UART0_RX = P0_0,
- UART0_TX = P0_1,
- UART0_CTS = P0_2,
- UART0_RTS = P0_3,
-
- UART1_RX = P2_0,
- UART1_TX = P2_1,
-
- UART2_RX = P3_0,
- UART2_TX = P3_1,
- UART2_CTS = P3_2,
- UART2_RTS = P3_3,
-
- // SPI pins
- SPI0_SCK = P0_4,
- SPI0_MOSI = P0_5,
- SPI0_MISO = P0_6,
- SPI0_SS = P0_7,
-
- SPI1_SCK = P1_0,
- SPI1_MOSI = P1_1,
- SPI1_MISO = P1_2,
- SPI1_SS = P1_3,
-
- SPI2_SCK = P2_4,
- SPI2_MOSI = P2_5,
- SPI2_MISO = P2_6,
- SPI2_SS = P2_7,
-
- // Default peripherals defines
- I2C_SCL = I2C0_SCL,
- I2C_SDA = I2C0_SDA,
-
- UART_RX = UART0_RX,
- UART_TX = UART0_TX,
- UART_CTS = UART0_CTS,
- UART_RTS = UART0_RTS,
-
- SPI_SCK = SPI0_SCK,
- SPI_MOSI = SPI0_MOSI,
- SPI_MISO = SPI0_MISO,
- SPI_SS = SPI0_SS,
-
- // Not connected
- NC = NOT_CONNECTED
-} PinName;
-
-typedef enum {
- PullUp,
- PullDown,
- OpenDrain,
- PullNone,
- PullDefault = PullUp
-} PinMode;
-
-typedef enum {
- LED_ON = 0,
- LED_OFF = 1
-} LedStates;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625PICO_BASE/low_level_init.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of Maxim Integrated
- * Products, Inc. shall not be used except as stated in the Maxim Integrated
- * Products, Inc. Branding Policy.
- *
- * The mere transfer of this software does not imply any licenses
- * of trade secrets, proprietary technology, copyrights, patents,
- * trademarks, maskwork rights, or any other form of intellectual
- * property whatsoever. Maxim Integrated Products, Inc. retains all
- * ownership rights.
- *******************************************************************************
- */
-
-#include "cmsis.h"
-#include "ioman_regs.h"
-#include "gpio_regs.h"
-
-//******************************************************************************
-// This function will get called early in system initialization
-void low_level_init(void)
-{
- /* The MAX32625PICO board utilizes a bootloader that can leave some
- * peripherals in a partially configured state. This function resets
- * those to allow proper initialization.
- */
- MXC_IOMAN->uart0_req = 0x0; // Clear any requests
- MXC_IOMAN->uart1_req = 0x0; // Clear any requests
-
- MXC_GPIO->inten[2] = 0x0; // Clear interrupt enable
- MXC_GPIO->int_mode[2] = 0x0; // Clear interrupt mode
- MXC_GPIO->in_mode[2] = 0x22222222; // Clear input mode
- MXC_GPIO->out_val[2] = 0x0; // Clear output value
- MXC_GPIO->out_mode[2] = 0xFFFFFFFF; // Clear output mode
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = MXC_BASE_UART0,
+ UART_1 = MXC_BASE_UART1,
+ UART_2 = MXC_BASE_UART2,
+ STDIO_UART = UART_1
+} UARTName;
+
+typedef enum {
+ I2C_0 = MXC_BASE_I2CM0,
+ I2C_1 = MXC_BASE_I2CM1
+} I2CName;
+
+typedef enum {
+ SPI_0 = MXC_BASE_SPIM0,
+ SPI_1 = MXC_BASE_SPIM1,
+ SPI_2 = MXC_BASE_SPIM2
+} SPIName;
+
+typedef enum {
+ PWM_0 = MXC_BASE_PT0,
+ PWM_1 = MXC_BASE_PT1,
+ PWM_2 = MXC_BASE_PT2,
+ PWM_3 = MXC_BASE_PT3,
+ PWM_4 = MXC_BASE_PT4,
+ PWM_5 = MXC_BASE_PT5,
+ PWM_6 = MXC_BASE_PT6,
+ PWM_7 = MXC_BASE_PT7,
+ PWM_8 = MXC_BASE_PT8,
+ PWM_9 = MXC_BASE_PT9,
+ PWM_10 = MXC_BASE_PT10,
+ PWM_11 = MXC_BASE_PT11,
+ PWM_12 = MXC_BASE_PT12,
+ PWM_13 = MXC_BASE_PT13,
+ PWM_14 = MXC_BASE_PT14,
+ PWM_15 = MXC_BASE_PT15
+} PWMName;
+
+typedef enum {
+ ADC = MXC_BASE_ADC
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,196 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT = 0, /* MXC_V_GPIO_OUT_MODE_HIGH_Z,*/
+ PIN_OUTPUT = 1 /* MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE */
+} PinDirection;
+
+#define PORT_SHIFT 12
+#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
+#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+
+typedef enum {
+ P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
+ P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
+ P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
+ P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
+ P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
+
+ // Analog input pins
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
+
+ // Analog
+ A0 = AIN_0,
+ A1 = AIN_1,
+ A2 = AIN_2,
+ A3 = AIN_3,
+
+ // General Pin Input Output (GPIO)
+ GPIO0 = P1_4,
+ GPIO1 = P1_5,
+ GPIO2 = P4_0,
+ GPIO3 = P4_1,
+ GPIO4 = P4_2,
+ GPIO5 = P4_3,
+ GPIO6 = NOT_CONNECTED,
+
+ //Purse Width Modulation (PWM)
+ PWM0 = GPIO2,
+ PWM1 = GPIO3,
+ PWM2 = GPIO0,
+ PWM3 = GPIO1,
+
+ // LEDs
+ LED0 = GPIO0,
+ LED1 = GPIO1,
+ LED2 = GPIO2,
+ LED3 = NOT_CONNECTED,
+ LED4 = NOT_CONNECTED,
+
+ LED_RED = LED0,
+ LED_GREEN = LED1,
+ LED_BLUE = LED2,
+
+ // USB bridge and SWD UART connected UART pins
+ USBTX = P2_1,
+ USBRX = P2_0,
+ STDIO_UART_TX = USBTX,
+ STDIO_UART_RX = USBRX,
+
+ // UART pins
+ UART0_RX = P0_0,
+ UART0_TX = P0_1,
+ UART0_CTS = P0_2,
+ UART0_RTS = P0_3,
+
+ UART1_RX = P2_0,
+ UART1_TX = P2_1,
+ UART1_CTS = P2_2,
+ UART1_RTS = P2_3,
+
+ UART2_RX = P3_0,
+ UART2_TX = P3_1,
+ UART2_CTS = P3_2,
+ UART2_RTS = P3_3,
+
+ // I2C pins
+ I2C0_SCL = P1_7,
+ I2C0_SDA = P1_6,
+
+ I2C1_SCL = P3_5,
+ I2C1_SDA = P3_4,
+
+ I2C2_SCL = NOT_CONNECTED,
+ I2C2_SDA = NOT_CONNECTED,
+
+ // SPI pins
+ SPI0_SCK = P0_4,
+ SPI0_MOSI = P0_5,
+ SPI0_MISO = P0_6,
+ SPI0_SS0 = P0_7,
+ SPI0_SS1 = P4_4,
+ SPI0_SS2 = P4_5,
+
+ SPI1_SCK = P1_0,
+ SPI1_MOSI = P1_1,
+ SPI1_MISO = P1_2,
+ SPI1_SS0 = P1_3,
+ SPI1_SS1 = P3_6,
+ SPI1_SS2 = P3_7,
+
+ SPI2_SCK = P2_4,
+ SPI2_MOSI = P2_5,
+ SPI2_MISO = P2_6,
+ SPI2_SS0 = P2_7,
+ SPI2_SS1 = P4_6,
+ SPI2_SS2 = P4_7,
+
+ SPI3_SCK = NOT_CONNECTED,
+ SPI3_MOSI = NOT_CONNECTED,
+ SPI3_MISO = NOT_CONNECTED,
+ SPI3_SS0 = NOT_CONNECTED,
+ SPI3_SS1 = NOT_CONNECTED,
+ SPI3_SS2 = NOT_CONNECTED,
+
+ // SWD UART
+ SWD_TGT_TX = UART1_TX,
+ SWD_TGT_RX = UART1_RX,
+ SWD_TGT_CTS = UART1_CTS,
+ SWD_TGT_RTS = UART1_RTS,
+
+ // Generics
+ SERIAL_TX = UART0_TX,
+ SERIAL_RX = UART0_RX,
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_SS0,
+ PWM_OUT = PWM0,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullUp,
+ PullDown,
+ OpenDrain,
+ PullNone,
+ PullDefault = PullUp
+} PinMode;
+
+typedef enum {
+ LED_ON = 0,
+ LED_OFF = 1
+} LedStates;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/TARGET_MAX32625_BOOT/MAX32625.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/TARGET_MAX32625_BOOT/MAX32625.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,9 +1,18 @@
+#! armcc -E
; MAX32625
; 512KB FLASH (0x80000) @ 0x000000000
; 160KB RAM (0x28000) @ 0x20000000
-LR_IROM1 0x000010000 0x70000 { ; load region size_region
- ER_IROM1 0x000010000 0x70000 { ; load address = execution address
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x00010000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x00070000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625NEXPAQ/max32625.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625NEXPAQ/max32625.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,13 +114,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +128,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625_BOOT/max32625.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625_BOOT/max32625.ld Thu Nov 08 11:46:34 2018 +0000
@@ -31,9 +31,17 @@
*******************************************************************************
*/
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x00010000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x00070000
+#endif
+
MEMORY
{
- FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 0x00070000
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00028000
}
@@ -114,13 +122,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +136,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625_NO_BOOT/max32625.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_GCC_ARM/TARGET_MAX32625_NO_BOOT/max32625.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,13 +114,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +128,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625_BOOT/MAX32625.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625_BOOT/MAX32625.icf Thu Nov 08 11:46:34 2018 +0000
@@ -1,7 +1,14 @@
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = 0x00010000;
+}
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = 0x00070000;
+}
+
/* [ROM] */
-define symbol __intvec_start__ = 0x00010000;
-define symbol __region_ROM_start__ = 0x00010000;
-define symbol __region_ROM_end__ = 0x0007FFFF;
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
define symbol __NVIC_start__ = 0x00010000;
--- a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,13 +114,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -128,14 +128,14 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -116,11 +116,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -116,11 +116,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -116,11 +116,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -318,6 +318,11 @@
NRF_RTC1->EVENTS_COMPARE[0] = 0;
}
+void us_ticker_free(void)
+{
+
+}
+
#if defined (__CC_ARM) /* ARMCC Compiler */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+#define PORT_SHIFT 3
+
+typedef enum {
+ p0 = 0,
+ p1 = 1,
+ p2 = 2,
+ p3 = 3,
+ p4 = 4,
+ p5 = 5,
+ p6 = 6,
+ p7 = 7,
+ p8 = 8,
+ p9 = 9,
+ p10 = 10,
+ p11 = 11,
+ p12 = 12,
+ p13 = 13,
+ p14 = 14,
+ p15 = 15,
+ p16 = 16,
+ p17 = 17,
+ p18 = 18,
+ p19 = 19,
+ p20 = 20,
+ p21 = 21,
+ p22 = 22,
+ p23 = 23,
+ p24 = 24,
+ p25 = 25,
+ p26 = 26,
+ p27 = 27,
+ p28 = 28,
+ p29 = 29,
+ p30 = 30,
+
+ P0_0 = p0,
+ P0_1 = p1,
+ P0_2 = p2,
+ P0_3 = p3,
+ P0_4 = p4,
+ P0_5 = p5,
+ P0_6 = p6,
+ P0_7 = p7,
+
+ P0_8 = p8,
+ P0_9 = p9,
+ P0_10 = p10,
+ P0_11 = p11,
+ P0_12 = p12,
+ P0_13 = p13,
+ P0_14 = p14,
+ P0_15 = p15,
+
+ P0_16 = p16,
+ P0_17 = p17,
+ P0_18 = p18,
+ P0_19 = p19,
+ P0_20 = p20,
+ P0_21 = p21,
+ P0_22 = p22,
+ P0_23 = p23,
+
+ P0_24 = p24,
+ P0_25 = p25,
+ P0_26 = p26,
+ P0_27 = p27,
+ P0_28 = p28,
+ P0_29 = p29,
+ P0_30 = p30,
+
+ // Analog
+ A0 = P0_1,
+ A1 = P0_2,
+ A2 = P0_3,
+ A3 = P0_4,
+
+ // General Pin Input Output (GPIO)
+ GPIO0 = P0_5,
+ GPIO1 = P0_7,
+ GPIO2 = P0_12,
+ GPIO3 = NOT_CONNECTED,
+ GPIO4 = NOT_CONNECTED,
+ GPIO5 = NOT_CONNECTED,
+ GPIO6 = NOT_CONNECTED,
+
+ //Purse Width Modulation (PWM)
+ PWM0 = GPIO2,
+ PWM1 = GPIO3,
+ PWM2 = GPIO0,
+ PWM3 = GPIO1,
+
+ // LEDs
+ LED0 = GPIO0,
+ LED1 = GPIO1,
+ LED2 = GPIO2,
+
+ LED_RED = LED0,
+ LED_GREEN = LED1,
+ LED_BLUE = LED2,
+
+ // USB bridge and SWD UART connected UART pins
+ USBTX = P0_9,
+ USBRX = P0_11,
+
+ // UART pins
+ UART0_RX = NOT_CONNECTED,
+ UART0_TX = NOT_CONNECTED,
+ UART0_CTS = NOT_CONNECTED,
+ UART0_RTS = NOT_CONNECTED,
+
+ UART1_RX = P0_11,
+ UART1_TX = P0_9,
+ UART1_CTS = P0_10,
+ UART1_RTS = P0_8,
+
+ RX_PIN_NUMBER = p11,
+ TX_PIN_NUMBER = p9,
+ CTS_PIN_NUMBER = p10,
+ RTS_PIN_NUMBER = p8,
+
+
+ UART2_RX = NOT_CONNECTED,
+ UART2_TX = NOT_CONNECTED,
+ UART2_CTS = NOT_CONNECTED,
+ UART2_RTS = NOT_CONNECTED,
+
+ // I2C pins
+ I2C0_SCL = P0_20,
+ I2C0_SDA = P0_19,
+
+ I2C1_SCL = P0_30,
+ I2C1_SDA = P0_29,
+
+ I2C2_SCL = NOT_CONNECTED,
+ I2C2_SDA = NOT_CONNECTED,
+
+ // SPI pins
+ SPI0_SCK = P0_18,
+ SPI0_MOSI = P0_15,
+ SPI0_MISO = P0_16,
+ SPI0_SS0 = P0_17,
+ SPI0_SS1 = P0_14,
+ SPI0_SS2 = P0_13,
+
+ SPI1_SCK = P0_25,
+ SPI1_MOSI = P0_23,
+ SPI1_MISO = P0_24,
+ SPI1_SS0 = P0_22,
+ SPI1_SS1 = P0_21,
+ SPI1_SS2 = P0_28,
+
+ SPI2_SCK = NOT_CONNECTED,
+ SPI2_MOSI = NOT_CONNECTED,
+ SPI2_MISO = NOT_CONNECTED,
+ SPI2_SS0 = NOT_CONNECTED,
+ SPI2_SS1 = NOT_CONNECTED,
+ SPI2_SS2 = NOT_CONNECTED,
+
+ SPI3_SCK = NOT_CONNECTED,
+ SPI3_MOSI = NOT_CONNECTED,
+ SPI3_MISO = NOT_CONNECTED,
+ SPI3_SS0 = NOT_CONNECTED,
+ SPI3_SS1 = NOT_CONNECTED,
+ SPI3_SS2 = NOT_CONNECTED,
+
+ // SWD UART
+ SWD_TGT_TX = UART1_TX,
+ SWD_TGT_RX = UART1_RX,
+ SWD_TGT_CTS = UART1_CTS,
+ SWD_TGT_RTS = UART1_RTS,
+
+ // Generics
+ SERIAL_TX = UART1_TX,
+ SERIAL_RX = UART1_RX,
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_SS0,
+ PWM_OUT = PWM0,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,20 +100,20 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
PROVIDE(__start_fs_data = .);
KEEP(*(.fs_data))
PROVIDE(__stop_fs_data = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -130,11 +130,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -116,11 +116,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld Thu Nov 08 11:46:34 2018 +0000
@@ -2,8 +2,8 @@
MEMORY
{
- FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
- RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x1800
+ FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
+ RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0x1108
}
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,20 +100,20 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
PROVIDE(__start_fs_data = .);
KEEP(*(.fs_data))
PROVIDE(__stop_fs_data = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -128,11 +128,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -141,6 +141,8 @@
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
SPI_PSELMOSI0 = p23,
SPI_PSELMISO0 = p24,
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_DELTA_DFBM_NQ620/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-void mbed_sdk_init()
-{
- char* debug_date = __DATE__;
- char* debug_time = __TIME__;
-
-}
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -121,6 +121,8 @@
RTS_PIN_NUMBER = p31,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
I2C_SDA = p2,
I2C_SCL = p3,
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -132,6 +132,8 @@
RTS_PIN_NUMBER = p2,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+#define PORT_SHIFT 3
+
+typedef enum {
+ p0 = 0,
+ p1 = 1,
+ p2 = 2,
+ p3 = 3,
+ p4 = 4,
+ p5 = 5,
+ p6 = 6,
+ p7 = 7,
+ p8 = 8,
+ p9 = 9,
+ p10 = 10,
+ p11 = 11,
+ p12 = 12,
+ p13 = 13,
+ p14 = 14,
+ p15 = 15,
+ p16 = 16,
+ p17 = 17,
+ p18 = 18,
+ p19 = 19,
+ p20 = 20,
+ p21 = 21,
+ p22 = 22,
+ p23 = 23,
+ p24 = 24,
+ p25 = 25,
+ p26 = 26,
+ p27 = 27,
+ p28 = 28,
+ p29 = 29,
+ p30 = 30,
+ p31 = 31,
+
+ P0_0 = p0,
+ P0_1 = p1,
+ P0_2 = p2,
+ P0_3 = p3,
+ P0_4 = p4,
+ P0_5 = p5,
+ P0_6 = p6,
+ P0_7 = p7,
+
+ P0_8 = p8,
+ P0_9 = p9,
+ P0_10 = p10,
+ P0_11 = p11,
+ P0_12 = p12,
+ P0_13 = p13,
+ P0_14 = p14,
+ P0_15 = p15,
+
+ P0_16 = p16,
+ P0_17 = p17,
+ P0_18 = p18,
+ P0_19 = p19,
+ P0_20 = p20,
+ P0_21 = p21,
+ P0_22 = p22,
+ P0_23 = p23,
+
+ P0_24 = p24,
+ P0_25 = p25,
+ P0_26 = p26,
+ P0_27 = p27,
+ P0_28 = p28,
+ P0_29 = p29,
+ P0_30 = p30,
+ P0_31 = p31,
+
+ RX_PIN_NUMBER = p8,
+ TX_PIN_NUMBER = p6,
+ CTS_PIN_NUMBER = p7,
+ RTS_PIN_NUMBER = p5,
+
+ // mBed interface Pins
+ STDIO_UART_TX = TX_PIN_NUMBER,
+ STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
+
+ // Analog
+ A0 = P0_2,
+ A1 = P0_3,
+ A2 = P0_4,
+ A3 = P0_28,
+
+ // General Pin Input Output (GPIO)
+ GPIO0 = P0_9,
+ GPIO1 = P0_10,
+ GPIO2 = P0_17,
+ GPIO3 = P0_29,
+ GPIO4 = NOT_CONNECTED,
+ GPIO5 = NOT_CONNECTED,
+ GPIO6 = NOT_CONNECTED,
+
+ //Purse Width Modulation (PWM)
+ PWM0 = GPIO2,
+ PWM1 = GPIO3,
+ PWM2 = GPIO0,
+ PWM3 = GPIO1,
+
+ // LEDs
+ LED0 = GPIO0,
+ LED1 = GPIO1,
+ LED2 = GPIO2,
+
+ LED_RED = LED0,
+ LED_GREEN = LED1,
+ LED_BLUE = LED2,
+
+ // USB bridge and SWD UART connected UART pins
+ USBTX = TX_PIN_NUMBER,
+ USBRX = RX_PIN_NUMBER,
+
+ // UART pins
+ UART0_RX = NOT_CONNECTED,
+ UART0_TX = NOT_CONNECTED,
+ UART0_CTS = NOT_CONNECTED,
+ UART0_RTS = NOT_CONNECTED,
+
+ UART1_RX = P0_8,
+ UART1_TX = P0_6,
+ UART1_CTS = P0_7,
+ UART1_RTS = P0_5,
+
+ UART2_RX = NOT_CONNECTED,
+ UART2_TX = NOT_CONNECTED,
+ UART2_CTS = NOT_CONNECTED,
+ UART2_RTS = NOT_CONNECTED,
+
+ // I2C pins
+ I2C0_SCL = P0_27,
+ I2C0_SDA = P0_26,
+
+ I2C1_SCL = P0_31,
+ I2C1_SDA = P0_30,
+
+ I2C2_SCL = NOT_CONNECTED,
+ I2C2_SDA = NOT_CONNECTED,
+
+ // SPI pins
+ SPI0_SCK = P0_14,
+ SPI0_MOSI = P0_12,
+ SPI0_MISO = P0_13,
+ SPI0_SS0 = P0_11,
+ SPI0_SS1 = P0_15,
+ SPI0_SS2 = P0_16,
+
+ SPI1_SCK = P0_25,
+ SPI1_MOSI = P0_23,
+ SPI1_MISO = P0_24,
+ SPI1_SS0 = P0_22,
+ SPI1_SS1 = P0_19,
+ SPI1_SS2 = P0_20,
+
+ SPI2_SCK = NOT_CONNECTED,
+ SPI2_MOSI = NOT_CONNECTED,
+ SPI2_MISO = NOT_CONNECTED,
+ SPI2_SS0 = NOT_CONNECTED,
+ SPI2_SS1 = NOT_CONNECTED,
+ SPI2_SS2 = NOT_CONNECTED,
+
+ SPI3_SCK = NOT_CONNECTED,
+ SPI3_MOSI = NOT_CONNECTED,
+ SPI3_MISO = NOT_CONNECTED,
+ SPI3_SS0 = NOT_CONNECTED,
+ SPI3_SS1 = NOT_CONNECTED,
+ SPI3_SS2 = NOT_CONNECTED,
+
+ // SWD UART
+ SWD_TGT_TX = UART1_TX,
+ SWD_TGT_RX = UART1_RX,
+ SWD_TGT_CTS = UART1_CTS,
+ SWD_TGT_RTS = UART1_RTS,
+
+ // Generics
+ SERIAL_TX = UART1_TX,
+ SERIAL_RX = UART1_RX,
+ I2C_SCL = I2C0_SCL,
+ I2C_SDA = I2C0_SDA,
+ SPI_MOSI = SPI0_MOSI,
+ SPI_MISO = SPI0_MISO,
+ SPI_SCK = SPI0_SCK,
+ SPI_CS = SPI0_SS0,
+ PWM_OUT = PWM0,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_UBLOX_EVA_NINA/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_UBLOX_EVA_NINA/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -86,6 +86,8 @@
RTS_PIN_NUMBER = p31,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
I2C_SDA0 = p2,
I2C_SCL0 = p3,
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h Thu Nov 08 11:46:34 2018 +0000 @@ -8557,9 +8557,7 @@ // <1=> NRF_CLOCK_LF_SRC_XTAL // <2=> NRF_CLOCK_LF_SRC_SYNTH -#ifndef NRF_SDH_CLOCK_LF_SRC -#define NRF_SDH_CLOCK_LF_SRC 1 -#endif +#include "nrf5x_lf_clk_helper.h" // <o> NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. #ifndef NRF_SDH_CLOCK_LF_RC_CTIV
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct Thu Nov 08 11:46:34 2018 +0000
@@ -9,17 +9,19 @@
#define MBED_APP_SIZE 0x80000
#endif
-/* If app_start is 0, do not set aside space for the softdevice */
-#if MBED_APP_START == 0
- #define MBED_RAM_START 0x20000000
- #define MBED_RAM_SIZE 0x10000
-#else
- #define MBED_RAM_START 0x200031D0
- #define MBED_RAM_SIZE 0xCE30
+/* If softdevice is present, set aside space for it */
+#if !defined(MBED_RAM_START)
+ #if defined(SOFTDEVICE_PRESENT)
+ #define MBED_RAM_START 0x200031D0
+ #define MBED_RAM_SIZE 0xCE30
+ #else
+ #define MBED_RAM_START 0x20000000
+ #define MBED_RAM_SIZE 0x10000
+ #endif
#endif
#define MBED_RAM0_START MBED_RAM_START
-#define MBED_RAM0_SIZE 0xDC
+#define MBED_RAM0_SIZE 0xE0
#define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE)
@@ -31,7 +33,7 @@
}
RW_IRAM0 MBED_RAM0_START UNINIT MBED_RAM0_SIZE { ;no init section
- *(*noinit)
+ *(*nvictable)
}
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
.ANY (+RW +ZI)
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,17 +25,19 @@
#define MBED_APP_SIZE 0x80000
#endif
-/* If app_start is 0, do not set aside space for the softdevice */
-#if MBED_APP_START == 0
- #define MBED_RAM_START 0x20000000
- #define MBED_RAM_SIZE 0x10000
-#else
- #define MBED_RAM_START 0x200031D0
- #define MBED_RAM_SIZE 0xCE30
+/* If softdevice is present, set aside space for it */
+#if !defined(MBED_RAM_START)
+ #if defined(SOFTDEVICE_PRESENT)
+ #define MBED_RAM_START 0x200031D0
+ #define MBED_RAM_SIZE 0xCE30
+ #else
+ #define MBED_RAM_START 0x20000000
+ #define MBED_RAM_SIZE 0x10000
+ #endif
#endif
#define MBED_RAM0_START MBED_RAM_START
-#define MBED_RAM0_SIZE 0xDC
+#define MBED_RAM0_SIZE 0xE0
#define MBED_RAM1_START (MBED_RAM_START + MBED_RAM0_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_RAM0_SIZE)
@@ -145,14 +147,14 @@
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH
__exidx_end = .;
@@ -164,13 +166,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -178,20 +180,20 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
PROVIDE(__start_fs_data = .);
KEEP(*(.fs_data))
PROVIDE(__stop_fs_data = .);
-
+
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -199,20 +201,27 @@
__edata = .;
+ .nvictable (NOLOAD) :
+ {
+ PROVIDE(__start_nvictable = .);
+ KEEP(*(.nvictable))
+ PROVIDE(__stop_nvictable = .);
+ } > RAM_NVIC
+
.noinit (NOLOAD) :
{
PROVIDE(__start_noinit = .);
KEEP(*(.noinit))
PROVIDE(__stop_noinit = .);
- } > RAM_NVIC
-
+ } > RAM
+
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/nRF52832.icf Thu Nov 08 11:46:34 2018 +0000
@@ -11,17 +11,19 @@
define symbol MBED_APP_SIZE = 0x80000;
}
-/* If app_start is 0, do not set aside space for the softdevice */
-if (MBED_APP_START == 0) {
- define symbol MBED_RAM_START = 0x20000000;
- define symbol MBED_RAM_SIZE = 0x10000;
-} else {
- define symbol MBED_RAM_START = 0x200031D0;
- define symbol MBED_RAM_SIZE = 0xCE30;
+/* If softdevice is present, set aside space for it */
+if (!isdefinedsymbol(MBED_RAM_START)) {
+ if (isdefinedsymbol(SOFTDEVICE_PRESENT)) {
+ define symbol MBED_RAM_START = 0x200031D0;
+ define symbol MBED_RAM_SIZE = 0xCE30;
+ } else {
+ define symbol MBED_RAM_START = 0x20000000;
+ define symbol MBED_RAM_SIZE = 0x10000;
+ }
}
define symbol MBED_RAM0_START = MBED_RAM_START;
-define symbol MBED_RAM0_SIZE = 0xDC;
+define symbol MBED_RAM0_SIZE = 0xE0; /* 8-byte aligned(0xDC) = 0xE0 */
define symbol MBED_RAM1_START = (MBED_RAM_START + MBED_RAM0_SIZE);
define symbol MBED_RAM1_SIZE = (MBED_RAM_SIZE - MBED_RAM0_SIZE);
@@ -54,6 +56,9 @@
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
+do not initialize { section .nvictable };
+place at address mem:__ICFEDIT_region_RAM_NVIC_start__ { section .nvictable };
+
do not initialize { section .noinit };
place in RAM_region { section .noinit };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 3
+
+///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y)
+#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num)
+
+
+typedef enum {
+ PinDef(0 , 0), // P0_0 = 0...
+ PinDef(0 , 1),
+ PinDef(0 , 2),
+ PinDef(0 , 3),
+ PinDef(0 , 4),
+ PinDef(0 , 5),
+ PinDef(0 , 6),
+ PinDef(0 , 7),
+ PinDef(0 , 8),
+ PinDef(0 , 9),
+ PinDef(0 , 10),
+ PinDef(0 , 11),
+ PinDef(0 , 12),
+ PinDef(0 , 13),
+ PinDef(0 , 14),
+ PinDef(0 , 15),
+ PinDef(0 , 16),
+ PinDef(0 , 17),
+ PinDef(0 , 18),
+ PinDef(0 , 19),
+ PinDef(0 , 20),
+ PinDef(0 , 21),
+ PinDef(0 , 22),
+ PinDef(0 , 23),
+ PinDef(0 , 24),
+ PinDef(0 , 25),
+ PinDef(0 , 26),
+ PinDef(0 , 27),
+ PinDef(0 , 28),
+ PinDef(0 , 29),
+ PinDef(0 , 30),
+ PinDef(0 , 31),
+
+ PinDef(1 , 0), //P1_1 = 32...
+ PinDef(1 , 1),
+ PinDef(1 , 2),
+ PinDef(1 , 3),
+ PinDef(1 , 4),
+ PinDef(1 , 5),
+ PinDef(1 , 6),
+ PinDef(1 , 7),
+ PinDef(1 , 8),
+ PinDef(1 , 9),
+ PinDef(1 , 10),
+ PinDef(1 , 11),
+ PinDef(1 , 12),
+ PinDef(1 , 13),
+ PinDef(1 , 14),
+ PinDef(1 , 15),
+
+ // Port0
+ p0 = P0_0,
+ p1 = P0_1,
+ p2 = P0_2,
+ p3 = P0_3,
+ p4 = P0_4,
+ p5 = P0_5,
+ p6 = P0_6,
+ p7 = P0_7,
+
+ p8 = P0_8,
+ p9 = P0_9,
+ p10 = P0_10,
+ p11 = P0_11,
+ p12 = P0_12,
+ p13 = P0_13,
+ p14 = P0_14,
+ p15 = P0_15,
+
+ p16 = P0_16,
+ p17 = P0_17,
+ p18 = P0_18,
+ p19 = P0_19,
+ p20 = P0_20,
+ p21 = P0_21,
+ p22 = P0_22,
+ p23 = P0_23,
+
+ p24 = P0_24,
+ p25 = P0_25,
+ p26 = P0_26,
+ p27 = P0_27,
+ p28 = P0_28,
+ p29 = P0_29,
+ p30 = P0_30,
+ p31 = P0_31,
+
+ // Port1
+ p32 = P1_0,
+ p33 = P1_1,
+ p34 = P1_2,
+ p35 = P1_3,
+ p36 = P1_4,
+ p37 = P1_5,
+ p38 = P1_6,
+ p39 = P1_7,
+
+ p40 = P1_8,
+ p41 = P1_9,
+ p42 = P1_10,
+ p43 = P1_11,
+ p44 = P1_12,
+ p45 = P1_13,
+ p46 = P1_14,
+ p47 = P1_15,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ SIO_0 = P0_0,
+ SIO_1 = P0_1,
+ SIO_2 = P0_2,
+ SIO_3 = P0_3,
+ SIO_4 = P0_4,
+ SIO_5 = P0_5,
+ SIO_6 = P0_6,
+ SIO_7 = P0_7,
+ SIO_8 = P0_8,
+ SIO_9 = P0_9, //NFC1
+ SIO_10 = P0_10, //NFC2
+ SIO_11 = P0_11,
+ SIO_12 = P0_12,
+ SIO_13 = P0_13,
+ SIO_14 = P0_14,
+ SIO_15 = P0_15,
+
+ SIO_16 = P0_16,
+ SIO_17 = P0_17,
+ SIO_18 = NC,
+ SIO_19 = P0_19,
+ SIO_20 = P0_20,
+ SIO_21 = P0_21,
+ SIO_22 = P0_22,
+ SIO_23 = P0_23,
+ SIO_24 = P0_24,
+ SIO_25 = P0_25,
+ SIO_26 = P0_26,
+ SIO_27 = P0_27,
+ SIO_28 = P0_28,
+ SIO_29 = P0_29,
+ SIO_30 = P0_30,
+ SIO_31 = P0_31,
+
+ SIO_32 = P1_0,
+ SIO_33 = P1_1,
+ SIO_34 = P1_2,
+ SIO_35 = P1_3,
+ SIO_36 = P1_4,
+ SIO_37 = P1_5,
+ SIO_38 = P1_6,
+ SIO_39 = P1_7,
+ SIO_40 = P1_8,
+ SIO_41 = P1_9,
+ SIO_42 = P1_10,
+ SIO_43 = P1_11,
+ SIO_44 = P1_12,
+ SIO_45 = P1_13,
+ SIO_46 = P1_14,
+ SIO_47 = P1_15,
+
+ LED1 = SIO_38,
+ LED2 = SIO_39,
+ LED3 = SIO_37,
+ LED_RED = LED1,
+ LED_GREEN = LED3,
+ LED_BLUE = LED2,
+
+ BUTTON1 = SIO_33,
+ USER_BUTTON = BUTTON1,
+
+ //Nordic SDK pin names
+ RX_PIN_NUMBER = SIO_8,
+ TX_PIN_NUMBER = SIO_6,
+ CTS_PIN_NUMBER = SIO_7,
+ RTS_PIN_NUMBER = SIO_5,
+
+ // mBed interface Pins
+ USBTX = TX_PIN_NUMBER,
+ USBRX = RX_PIN_NUMBER,
+ STDIO_UART_TX = TX_PIN_NUMBER,
+ STDIO_UART_RX = RX_PIN_NUMBER,
+ STDIO_UART_CTS = CTS_PIN_NUMBER,
+ STDIO_UART_RTS = RTS_PIN_NUMBER,
+
+ SPI_PSELMOSI0 = SIO_45,
+ SPI_PSELMISO0 = SIO_46,
+ SPI_PSELSS0 = SIO_42, //CS for SD card on MTB
+ SPI_PSELSCK0 = SIO_47,
+
+ SPI_PSELMOSI1 = SIO_30,
+ SPI_PSELMISO1 = SIO_29,
+ SPI_PSELSS1 = SIO_41, //CS for LCD on MTB
+ SPI_PSELSCK1 = SIO_44,
+
+ //Default SPI
+ SPI_MOSI = SPI_PSELMOSI0,
+ SPI_MISO = SPI_PSELMISO0,
+ SPI_SCK = SPI_PSELSCK0,
+ SPI_CS = SPI_PSELSS0,
+
+/*
+ SPIS_PSELMOSI = P1_2,
+ SPIS_PSELMISO = P1_3,
+ SPIS_PSELSS = P1_1,
+ SPIS_PSELSCK = P1_4,
+*/
+
+ I2C_SDA0 = SIO_26,
+ I2C_SCL0 = SIO_27,
+
+ I2C_SDA1 = SIO_25,
+ I2C_SCL1 = SIO_28,
+
+ //Default I2C
+ I2C_SCL = I2C_SCL0,
+ I2C_SDA = I2C_SDA0,
+
+ UART_TX1 = SIO_16,
+ UART_RX1 = SIO_15,
+
+ UART_TX2 = SIO_21,
+ UART_RX2 = SIO_24,
+
+ //Default UART
+ UART_TX = UART_TX1,
+ UART_RX = UART_RX1,
+
+ /* QSPI */
+ QSPI1_IO0 = P0_20,
+ QSPI1_IO1 = P0_21,
+ QSPI1_IO2 = P0_22,
+ QSPI1_IO3 = P0_23,
+ QSPI1_SCK = P0_19,
+ QSPI1_CSN = P0_17,
+
+ /* QSPI FLASH */
+ QSPI_FLASH1_IO0 = QSPI1_IO0,
+ QSPI_FLASH1_IO1 = QSPI1_IO1,
+ QSPI_FLASH1_IO2 = QSPI1_IO2,
+ QSPI_FLASH1_IO3 = QSPI1_IO3,
+ QSPI_FLASH1_SCK = QSPI1_SCK,
+ QSPI_FLASH1_CSN = QSPI1_CSN,
+
+ //MTB aliases
+ GP0 = SIO_33,
+ GP1 = SIO_34,
+ AIN0 = SIO_2,
+ AIN1 = SIO_3,
+ AIN2 = SIO_4,
+ GP2 = SIO_42,
+ GP3 = SIO_43,
+ GP4 = SIO_19,
+ GP5 = SIO_17, //A0 for LCD on MTB
+ GP6 = SIO_40, //RESET for LCD on MTB
+ GP7 = SIO_41,
+ GP8 = SIO_12,
+
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,24 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + +#include "objects.h" + +#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -227,6 +227,22 @@
A4 = p30,
A5 = p31,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = P0_20,
+ QSPI1_IO1 = P0_21,
+ QSPI1_IO2 = P0_22,
+ QSPI1_IO3 = P0_23,
+ QSPI1_SCK = P0_19,
+ QSPI1_CSN = P0_17,
+
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = QSPI1_IO0,
+ QSPI_FLASH1_IO1 = QSPI1_IO1,
+ QSPI_FLASH1_IO2 = QSPI1_IO2,
+ QSPI_FLASH1_IO3 = QSPI1_IO3,
+ QSPI_FLASH1_SCK = QSPI1_SCK,
+ QSPI_FLASH1_CSN = QSPI1_CSN,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h Thu Nov 08 11:46:34 2018 +0000 @@ -2748,6 +2748,136 @@ // </e> +// <e> QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver. +//========================================================== +#ifndef QSPI_ENABLED +#define QSPI_ENABLED 1 +#endif +#if QSPI_ENABLED +// <o> QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef QSPI_CONFIG_SCK_DELAY +#define QSPI_CONFIG_SCK_DELAY 1 +#endif + +// <o> QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef QSPI_CONFIG_READOC +#define QSPI_CONFIG_READOC 4 +#endif + +// <o> QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef QSPI_CONFIG_WRITEOC +#define QSPI_CONFIG_WRITEOC 3 +#endif + +// <o> QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef QSPI_CONFIG_ADDRMODE +#define QSPI_CONFIG_ADDRMODE 0 +#endif + +// <o> QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef QSPI_CONFIG_MODE +#define QSPI_CONFIG_MODE 0 +#endif + +// <o> QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef QSPI_CONFIG_FREQUENCY +#define QSPI_CONFIG_FREQUENCY 1 +#endif + +// <s> QSPI_PIN_SCK - SCK pin value. +#ifndef QSPI_PIN_SCK +#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <s> QSPI_PIN_CSN - CSN pin value. +#ifndef QSPI_PIN_CSN +#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <s> QSPI_PIN_IO0 - IO0 pin value. +#ifndef QSPI_PIN_IO0 +#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <s> QSPI_PIN_IO1 - IO1 pin value. +#ifndef QSPI_PIN_IO1 +#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <s> QSPI_PIN_IO2 - IO2 pin value. +#ifndef QSPI_PIN_IO2 +#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <s> QSPI_PIN_IO3 - IO3 pin value. +#ifndef QSPI_PIN_IO3 +#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// <o> QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QSPI_CONFIG_IRQ_PRIORITY +#define QSPI_CONFIG_IRQ_PRIORITY 7 +#endif + +#endif //QSPI_ENABLED + +// </e> + +// </e> + // <e> TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver //========================================================== #ifndef TIMER_ENABLED @@ -8556,9 +8686,7 @@ // <1=> NRF_CLOCK_LF_SRC_XTAL // <2=> NRF_CLOCK_LF_SRC_SYNTH -#ifndef NRF_SDH_CLOCK_LF_SRC -#define NRF_SDH_CLOCK_LF_SRC 1 -#endif +#include "nrf5x_lf_clk_helper.h" // <o> NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. #ifndef NRF_SDH_CLOCK_LF_RC_CTIV
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52840.sct Thu Nov 08 11:46:34 2018 +0000 @@ -9,13 +9,15 @@ #define MBED_APP_SIZE 0x100000 #endif -/* If app_start is 0, do not set aside space for the softdevice */ -#if MBED_APP_START == 0 - #define MBED_RAM_START 0x20000000 - #define MBED_RAM_SIZE 0x40000 -#else - #define MBED_RAM_START 0x20003188 - #define MBED_RAM_SIZE 0x3CE78 +/* If softdevice is present, set aside space for it */ +#if !defined(MBED_RAM_START) + #if defined(SOFTDEVICE_PRESENT) + #define MBED_RAM_START 0x20003188 + #define MBED_RAM_SIZE 0x3CE78 + #else + #define MBED_RAM_START 0x20000000 + #define MBED_RAM_SIZE 0x40000 + #endif #endif #define MBED_RAM0_START MBED_RAM_START
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,13 +25,15 @@
#define MBED_APP_SIZE 0x100000
#endif
-/* If app_start is 0, do not set aside space for the softdevice */
-#if MBED_APP_START == 0
- #define MBED_RAM_START 0x20000000
- #define MBED_RAM_SIZE 0x40000
-#else
- #define MBED_RAM_START 0x20003188
- #define MBED_RAM_SIZE 0x3CE78
+/* If softdevice is present, set aside space for it */
+#if !defined(MBED_RAM_START)
+ #if defined(SOFTDEVICE_PRESENT)
+ #define MBED_RAM_START 0x20003188
+ #define MBED_RAM_SIZE 0x3CE78
+ #else
+ #define MBED_RAM_START 0x20000000
+ #define MBED_RAM_SIZE 0x40000
+ #endif
#endif
#define MBED_RAM0_START MBED_RAM_START
@@ -144,14 +146,14 @@
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- . = ALIGN(4);
+ . = ALIGN(8);
} > FLASH
__exidx_end = .;
@@ -163,13 +165,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -177,20 +179,20 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
PROVIDE(__start_fs_data = .);
KEEP(*(.fs_data))
PROVIDE(__stop_fs_data = .);
*(.jcr)
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -198,20 +200,27 @@
__edata = .;
+ .nvictable (NOLOAD) :
+ {
+ PROVIDE(__start_nvictable = .);
+ KEEP(*(.nvictable))
+ PROVIDE(__stop_nvictable = .);
+ } > RAM_NVIC
+
.noinit (NOLOAD) :
{
PROVIDE(__start_noinit = .);
KEEP(*(.noinit))
PROVIDE(__stop_noinit = .);
- } > RAM_NVIC
+ } > RAM
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52840.icf Thu Nov 08 11:46:34 2018 +0000
@@ -11,13 +11,15 @@
define symbol MBED_APP_SIZE = 0x100000;
}
-/* If app_start is 0, do not set aside space for the softdevice */
-if (MBED_APP_START == 0) {
- define symbol MBED_RAM_START = 0x20000000;
- define symbol MBED_RAM_SIZE = 0x40000;
-} else {
- define symbol MBED_RAM_START = 0x20003188;
- define symbol MBED_RAM_SIZE = 0x3CE78;
+/* If softdevice is present, set aside space for it */
+if (!isdefinedsymbol(MBED_RAM_START)) {
+ if (isdefinedsymbol(SOFTDEVICE_PRESENT)) {
+ define symbol MBED_RAM_START = 0x20003188;
+ define symbol MBED_RAM_SIZE = 0x3CE78;
+ } else {
+ define symbol MBED_RAM_START = 0x20000000;
+ define symbol MBED_RAM_SIZE = 0x40000;
+ }
}
define symbol MBED_RAM0_START = MBED_RAM_START;
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -63,7 +63,7 @@
"NRF52_PAN_64"
],
"target.lf_clock_src": "NRF_LF_SRC_RC",
- "target.console-uart-flow-control": "RTSCTS"
+ "target.console-uart-flow-control": null
},
"MTB_UBLOX_NINA_B1": {
"target.macros_add": [
@@ -101,8 +101,7 @@
"NRF52_PAN_62",
"NRF52_PAN_63",
"NRF52_PAN_64"
- ],
- "target.console-uart-flow-control": "RTSCTS"
+ ]
},
"RBLAB_BLENANO2": {
"target.macros_add": [
@@ -186,8 +185,15 @@
"target.macros_add": [
"CONFIG_GPIO_AS_PINRESET",
"NRF52_ERRATA_20"
+ ]
+ },
+ "MTB_LAIRD_BL654": {
+ "target.macros_add": [
+ "CONFIG_GPIO_AS_PINRESET",
+ "NRF52_ERRATA_20"
],
- "target.console-uart-flow-control": "RTSCTS"
+ "target.lf_clock_src": "NRF_LF_SRC_RC",
+ "target.console-uart-flow-control": null
}
}
}
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -142,6 +142,17 @@
uint32_t placeholder;
};
+#if DEVICE_QSPI
+
+#include "nrf_drv_qspi.h"
+
+struct qspi_s {
+ uint32_t placeholder;
+ //nrf_drv_qspi_config_t config;
+};
+
+#endif
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/reloc_vector_table.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/reloc_vector_table.c Thu Nov 08 11:46:34 2018 +0000
@@ -39,6 +39,8 @@
#include "nrf.h"
#include "cmsis_nvic.h"
#include "stdint.h"
+#include "PinNames.h"
+#include "hal/gpio_api.h"
#if defined(SOFTDEVICE_PRESENT)
#include "nrf_sdm.h"
@@ -46,13 +48,13 @@
#endif
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
- __attribute__ ((section(".bss.noinit"),zero_init))
+ __attribute__ ((section(".bss.nvictable"),zero_init))
uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
#elif defined(__GNUC__)
- __attribute__ ((section(".noinit")))
+ __attribute__ ((section(".nvictable")))
uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
#elif defined(__ICCARM__)
- uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".noinit";
+ uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".nvictable";
#endif
extern uint32_t __Vectors[];
@@ -110,3 +112,14 @@
SCB->VTOR = (uint32_t) nrf_dispatch_vector;
#endif
}
+
+
+void mbed_sdk_init(void)
+{
+ if (STDIO_UART_RTS != NC) {
+ gpio_t rts;
+ gpio_init_out(&rts, STDIO_UART_RTS);
+ /* Set STDIO_UART_RTS as gpio driven low */
+ gpio_write(&rts, 0);
+ }
+}
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -593,6 +593,20 @@
if (available > 0) {
+ /* Check if hardware flow control is set and signal sender to stop.
+ *
+ * This signal is set manually because the flow control logic in the UARTE module
+ * only works when the module is receiving and not after an ENDRX event.
+ *
+ * The RTS signal is kept high until the atomic FIFO is empty. This allow systems
+ * with flow control to reduce their FIFO and DMA buffers.
+ */
+ if ((nordic_nrf5_uart_state[instance].owner->hwfc == NRF_UART_HWFC_ENABLED) &&
+ (nordic_nrf5_uart_state[instance].owner->rts != NRF_UART_PSEL_DISCONNECTED)) {
+
+ nrf_gpio_pin_set(nordic_nrf5_uart_state[instance].owner->rts);
+ }
+
/* Copy data from DMA buffer to FIFO buffer. */
for (size_t index = 0; index < available; index++) {
@@ -810,6 +824,7 @@
/* Check if pin is set before configuring it. */
if (uart_object->rts != NRF_UART_PSEL_DISCONNECTED) {
+ nrf_gpio_pin_clear(uart_object->rts);
nrf_gpio_cfg_output(uart_object->rts);
}
@@ -819,8 +834,9 @@
nrf_gpio_cfg_input(uart_object->cts, NRF_GPIO_PIN_NOPULL);
}
+ /* Only let UARTE module handle CTS, RTS is handled manually due to buggy UARTE logic. */
nrf_uarte_hwfc_pins_set(nordic_nrf5_uart_register[uart_object->instance],
- uart_object->rts,
+ NRF_UART_PSEL_DISCONNECTED,
uart_object->cts);
}
@@ -1257,6 +1273,7 @@
/* Force reconfiguration next time object is owner. */
uart_object->update = true;
+ nordic_nrf5_serial_configure(obj);
}
/** Clear the serial peripheral
@@ -1428,6 +1445,20 @@
uint8_t *byte = (uint8_t *) nrf_atfifo_item_get(fifo, &context);
nrf_atfifo_item_free(fifo, &context);
+ /* Check if hardware flow control is set and the atomic FIFO buffer is empty.
+ *
+ * Receive is halted until the buffer has been completely handled to reduce RAM usage.
+ *
+ * This signal is set manually because the flow control logic in the UARTE module
+ * only works when the module is receiving and not after an ENDRX event.
+ */
+ if ((nordic_nrf5_uart_state[instance].owner->hwfc == NRF_UART_HWFC_ENABLED) &&
+ (nordic_nrf5_uart_state[instance].owner->rts != NRF_UART_PSEL_DISCONNECTED) &&
+ (*head == *tail)) {
+
+ nrf_gpio_pin_clear(nordic_nrf5_uart_state[instance].owner->rts);
+ }
+
return *byte;
}
@@ -1439,6 +1470,7 @@
*/
void serial_putc(serial_t *obj, int character)
{
+ bool done = false;
MBED_ASSERT(obj);
#if DEVICE_SERIAL_ASYNCH
@@ -1449,35 +1481,20 @@
int instance = uart_object->instance;
- /**
- * tx_in_progress acts like a mutex to ensure only one transmission can be active at a time.
- * The flag is modified using the atomic compare-and-set function.
- */
- bool mutex = false;
-
- do {
- uint8_t expected = 0;
- uint8_t desired = 1;
-
- mutex = core_util_atomic_cas_u8((uint8_t *) &nordic_nrf5_uart_state[instance].tx_in_progress, &expected, desired);
- } while (mutex == false);
-
- /* Take ownership and configure UART if necessary. */
nordic_nrf5_serial_configure(obj);
-
/* Arm Tx DMA buffer. */
nordic_nrf5_uart_state[instance].tx_data = character;
nrf_uarte_tx_buffer_set(nordic_nrf5_uart_register[instance],
&nordic_nrf5_uart_state[instance].tx_data,
1);
+ nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX);
+ nrf_uarte_task_trigger(nordic_nrf5_uart_register[instance], NRF_UARTE_TASK_STARTTX);
- /* Clear ENDTX event and enable interrupts. */
- nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_ENDTX);
- nrf_uarte_int_enable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_ENDTX_MASK);
+ do {
+ done = nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
+ } while(done == false);
- /* Trigger DMA transfer. */
- nrf_uarte_task_trigger(nordic_nrf5_uart_register[instance],
- NRF_UARTE_TASK_STARTTX);
+ nrf_uarte_event_extra_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
}
/** Check if the serial peripheral is readable
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -4,9 +4,6 @@
"SOFTDEVICE_PRESENT=1",
"S132",
"BLE_STACK_SUPPORT_REQD",
- "NRF_SDH_CLOCK_LF_SRC=1",
- "NRF_SDH_CLOCK_LF_RC_CTIV=0",
- "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0",
"NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7",
"NRF_SD_BLE_API_VERSION=5",
"NRF_SDH_ENABLED=1",
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -4,9 +4,6 @@
"SOFTDEVICE_PRESENT=1",
"S132",
"BLE_STACK_SUPPORT_REQD",
- "NRF_SDH_CLOCK_LF_SRC=1",
- "NRF_SDH_CLOCK_LF_RC_CTIV=0",
- "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0",
"NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7",
"NRF_SD_BLE_API_VERSION=5",
"NRF_SDH_ENABLED=1",
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -4,9 +4,6 @@
"SOFTDEVICE_PRESENT=1",
"S140",
"BLE_STACK_SUPPORT_REQD",
- "NRF_SDH_CLOCK_LF_SRC=1",
- "NRF_SDH_CLOCK_LF_RC_CTIV=0",
- "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0",
"NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7",
"NRF_SD_BLE_API_VERSION=5",
"NRF_SDH_ENABLED=1",
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json Thu Nov 08 11:46:34 2018 +0000
@@ -4,9 +4,6 @@
"SOFTDEVICE_PRESENT=1",
"S140",
"BLE_STACK_SUPPORT_REQD",
- "NRF_SDH_CLOCK_LF_SRC=1",
- "NRF_SDH_CLOCK_LF_RC_CTIV=0",
- "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0",
"NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7",
"NRF_SD_BLE_API_VERSION=5",
"NRF_SDH_ENABLED=1",
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/drivers_nrf/hal/nrf_uarte.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/drivers_nrf/hal/nrf_uarte.h Thu Nov 08 11:46:34 2018 +0000
@@ -229,6 +229,25 @@
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
/**
+ * @brief Function for checking the state of a specific extra UARTE event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to check.
+ *
+ * @retval True if event is set, False otherwise.
+ */
+__STATIC_INLINE bool nrf_uarte_event_extra_check(NRF_UARTE_Type * p_reg, uint32_t event);
+
+/**
+ * @brief Function for clearing a specific extra UARTE event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Extra event to clear.
+ */
+
+__STATIC_INLINE void nrf_uarte_event_extra_clear(NRF_UARTE_Type * p_reg, uint32_t event);
+
+/**
* @brief Function for returning the address of a specific UARTE event register.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
@@ -456,11 +475,25 @@
}
+__STATIC_INLINE void nrf_uarte_event_extra_clear(NRF_UARTE_Type * p_reg, uint32_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+ (void)dummy;
+#endif
+
+}
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
+__STATIC_INLINE bool nrf_uarte_event_extra_check(NRF_UARTE_Type * p_reg, uint32_t event)
+{
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
nrf_uarte_event_t event)
{
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/common_rtc.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/common_rtc.c Thu Nov 08 11:46:34 2018 +0000
@@ -180,6 +180,15 @@
m_common_rtc_enabled = true;
}
+void common_rtc_free()
+{
+ nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_STOP);
+ nrf_rtc_int_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
+ NVIC_DisableIRQ(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE));
+
+ m_common_rtc_enabled = false;
+}
+
void common_rtc_set_interrupt(uint32_t ticks_count, uint32_t cc_channel,
uint32_t int_mask)
{
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,7 @@
void lp_ticker_free(void)
{
- // A common counter is used for RTC, lp_ticker and us_ticker, so it can't be
- // disabled here, but this does not cause any extra cost.
+ common_rtc_free();
}
uint32_t lp_ticker_read()
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h Thu Nov 08 11:46:34 2018 +0000
@@ -43,6 +43,18 @@
#warning No configuration for LF clock source. Xtal source will be used as a default configuration.
#endif
+#define DEFAULT_LFCLK_CONF_ACCURACY NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM
+
+#ifdef NRF52
+ #define MAX_LFCLK_CONF_RC_CTIV 32
+#else
+ #define MAX_LFCLK_CONF_RC_CTIV 64
+#endif
+
+#define MAX_LFCLK_CONF_RC_TEMP_CTIV 33
+
+#define DEFAULT_LFCLK_CONF_RC_CTIV 16 // Check temperature every 16 * 250ms.
+#define DEFAULT_LFCLK_CONF_RC_TEMP_CTIV 1 // Only calibrate if temperature has changed.
#define NRF_LF_SRC_XTAL 2
@@ -50,10 +62,38 @@
#define NRF_LF_SRC_RC 4
#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH
+ #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_SYNTH
+ #define NRF_SDH_CLOCK_LF_RC_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+ #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth)
#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL
+ #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_XTAL
+ #define NRF_SDH_CLOCK_LF_RC_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+ #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal)
#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC
+ #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_RC
+
+ #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL
+ #define NRF_SDH_CLOCK_LF_RC_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL
+ #else
+ #define NRF_SDH_CLOCK_LF_RC_CTIV DEFAULT_LFCLK_CONF_RC_CTIV
+ #endif
+
+ #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG
+ #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG
+ #else
+ #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV DEFAULT_LFCLK_CONF_RC_TEMP_CTIV
+ #endif
+
+ #if (NRF_SDH_CLOCK_LF_RC_CTIV < 1) || (NRF_SDH_CLOCK_LF_RC_CTIV > MAX_LFCLK_CONF_RC_CTIV)
+ #error Calibration timer interval out of range!
+ #endif
+
+ #if (NRF_SDH_CLOCK_LF_RC_TEMP_CTIV < 0 ) || (NRF_SDH_CLOCK_LF_RC_TEMP_CTIV > 33)
+ #error Number/mode of LF RC calibration intervals out of range!
+ #endif
+
#define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC)
#else
#error Bad LFCLK configuration. Declare proper source through mbed configuration.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2017 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "qspi_api.h"
+
+#if DEVICE_QSPI
+
+#include "nrf_drv_common.h"
+#include "nrf_drv_qspi.h"
+
+/*
+TODO
+ - config inside obj - nordic headers have some problems with inclusion
+ - free - is it really empty, nothing to do there?
+ - prepare command - support more protocols that nordic can do (now limited)
+ - nordic does not support
+ - alt
+ - dummy cycles
+*/
+
+#define MBED_HAL_QSPI_HZ_TO_CONFIG(hz) ((32000000/(hz))-1)
+#define MBED_HAL_QSPI_MAX_FREQ 32000000UL
+
+// NRF supported R/W opcodes
+#define FAST_READ_opcode 0x0B
+#define READ2O_opcode 0x3B
+#define READ2IO_opcode 0xBB
+#define READ4O_opcode 0x6B
+#define READ4IO_opcode 0xEB
+
+#define PP_opcode 0x02
+#define PP2O_opcode 0xA2
+#define PP4O_opcode 0x32
+#define PP4IO_opcode 0x38
+
+static nrf_drv_qspi_config_t config;
+
+// Private helper function to track initialization
+static ret_code_t _qspi_drv_init(void);
+
+qspi_status_t qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, bool write)
+{
+ // we need to remap opcodes to NRF ID's
+ // most commmon are 1-1-1, 1-1-4, 1-4-4
+
+ // 1-1-1
+ if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->data.bus_width == QSPI_CFG_BUS_SINGLE) {
+ if (write) {
+ if (command->instruction.value == PP_opcode) {
+ config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ } else {
+ if (command->instruction.value == FAST_READ_opcode) {
+ config.prot_if.readoc = NRF_QSPI_READOC_FASTREAD;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+ // 1-1-4
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->data.bus_width == QSPI_CFG_BUS_QUAD) {
+ // 1_1_4
+ if (write) {
+ if (command->instruction.value == PP4O_opcode) {
+ config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP4O;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ } else {
+ if (command->instruction.value == READ4O_opcode) {
+ config.prot_if.readoc = NRF_QSPI_READOC_READ4O;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+ // 1-4-4
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->address.bus_width == QSPI_CFG_BUS_QUAD &&
+ command->data.bus_width == QSPI_CFG_BUS_QUAD) {
+ // 1_4_4
+ if (write) {
+ if (command->instruction.value == PP4IO_opcode) {
+ config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP4IO;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ } else {
+ if (command->instruction.value == READ4IO_opcode) {
+ config.prot_if.readoc = NRF_QSPI_READOC_READ4IO;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+ // 1-1-2
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->data.bus_width == QSPI_CFG_BUS_DUAL) {
+ // 1-1-2
+ if (write) {
+ if (command->instruction.value == PP2O_opcode) {
+ config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP2O;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ } else {
+ if (command->instruction.value == READ2O_opcode) {
+ config.prot_if.readoc = NRF_QSPI_READOC_READ2O;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+ // 1-2-2
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
+ command->address.bus_width == QSPI_CFG_BUS_DUAL &&
+ command->data.bus_width == QSPI_CFG_BUS_DUAL) {
+ // 1-2-2
+ if (write) {
+ // 1-2-2 write is not supported
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ if (command->instruction.value == READ2IO_opcode) {
+ config.prot_if.readoc = NRF_QSPI_READOC_READ2IO;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ // supporting only 24 or 32 bit address
+ if (command->address.size == QSPI_CFG_ADDR_SIZE_24) {
+ config.prot_if.addrmode = NRF_QSPI_ADDRMODE_24BIT;
+ } else if (command->address.size == QSPI_CFG_ADDR_SIZE_32) {
+ config.prot_if.addrmode = NRF_QSPI_ADDRMODE_32BIT;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ //Configure QSPI with new command format
+ ret_code_t ret_status = _qspi_drv_init();
+ if (ret_status != NRF_SUCCESS ) {
+ if (ret_status == NRF_ERROR_INVALID_PARAM) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
+{
+ (void)(obj);
+ if (hz > MBED_HAL_QSPI_MAX_FREQ) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ // memset(config, 0, sizeof(config));
+
+ config.pins.sck_pin = (uint32_t)sclk;
+ config.pins.csn_pin = (uint32_t)ssel;
+ config.pins.io0_pin = (uint32_t)io0;
+ config.pins.io1_pin = (uint32_t)io1;
+ config.pins.io2_pin = (uint32_t)io2;
+ config.pins.io3_pin = (uint32_t)io3;
+ config.irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY;
+
+ config.phy_if.sck_freq = (nrf_qspi_frequency_t)MBED_HAL_QSPI_HZ_TO_CONFIG(hz);
+ config.phy_if.sck_delay = 0x05;
+ config.phy_if.dpmen = false;
+ config.phy_if.spi_mode = mode == 0 ? NRF_QSPI_MODE_0 : NRF_QSPI_MODE_1;
+
+ //Use _qspi_drv_init private function to initialize
+ ret_code_t ret = _qspi_drv_init();
+ if (ret == NRF_SUCCESS ) {
+ return QSPI_STATUS_OK;
+ } else if (ret == NRF_ERROR_INVALID_PARAM) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+}
+
+qspi_status_t qspi_free(qspi_t *obj)
+{
+ (void)(obj);
+ // possibly here uninit from SDK driver
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_frequency(qspi_t *obj, int hz)
+{
+ config.phy_if.sck_freq = (nrf_qspi_frequency_t)MBED_HAL_QSPI_HZ_TO_CONFIG(hz);
+
+ // use sync version, no handler
+ ret_code_t ret = _qspi_drv_init();
+ if (ret == NRF_SUCCESS ) {
+ return QSPI_STATUS_OK;
+ } else if (ret == NRF_ERROR_INVALID_PARAM) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+}
+
+qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
+{
+ qspi_status_t status = qspi_prepare_command(obj, command, true);
+ if (status != QSPI_STATUS_OK) {
+ return status;
+ }
+
+ // write here does not return how much it transfered, we return transfered all
+ ret_code_t ret = nrf_drv_qspi_write(data, *length, command->address.value);
+ if (ret == NRF_SUCCESS ) {
+ return QSPI_STATUS_OK;
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+}
+
+qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
+{
+ qspi_status_t status = qspi_prepare_command(obj, command, false);
+ if (status != QSPI_STATUS_OK) {
+ return status;
+ }
+
+ ret_code_t ret = nrf_drv_qspi_read(data, *length, command->address.value);
+ if (ret == NRF_SUCCESS ) {
+ return QSPI_STATUS_OK;
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+}
+
+qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
+{
+ ret_code_t ret_code;
+ uint8_t data[8];
+ uint32_t data_size = tx_size + rx_size;
+
+ nrf_qspi_cinstr_conf_t qspi_cinstr_config;
+ qspi_cinstr_config.opcode = command->instruction.value;
+ qspi_cinstr_config.io2_level = true;
+ qspi_cinstr_config.io3_level = true;
+ qspi_cinstr_config.wipwait = false;
+ qspi_cinstr_config.wren = false;
+
+ if(!command->address.disabled && data_size == 0) {
+ // erase command with address
+ if (command->address.size == QSPI_CFG_ADDR_SIZE_24) {
+ qspi_cinstr_config.length = NRF_QSPI_CINSTR_LEN_4B;
+ } else if (command->address.size == QSPI_CFG_ADDR_SIZE_32) {
+ qspi_cinstr_config.length = NRF_QSPI_CINSTR_LEN_5B;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ uint32_t address_size = (uint32_t)qspi_cinstr_config.length - 1;
+ uint8_t *address_bytes = (uint8_t *)&command->address.value;
+ for (uint32_t i = 0; i < address_size; ++i) {
+ data[i] = address_bytes[address_size - 1 - i];
+ }
+ } else if (data_size < 9) {
+ qspi_cinstr_config.length = (nrf_qspi_cinstr_len_t)(NRF_QSPI_CINSTR_LEN_1B + data_size);
+ // preparing data to send
+ for (uint32_t i = 0; i < tx_size; ++i) {
+ data[i] = ((uint8_t *)tx_data)[i];
+ }
+ } else {
+ return QSPI_STATUS_ERROR;
+ }
+
+ ret_code = nrf_drv_qspi_cinstr_xfer(&qspi_cinstr_config, data, data);
+ if (ret_code != NRF_SUCCESS) {
+ return QSPI_STATUS_ERROR;
+ }
+
+ // preparing received data
+ for (uint32_t i = 0; i < rx_size; ++i) {
+ // Data is sending as a normal SPI transmission so there is one buffer to send and receive data.
+ ((uint8_t *)rx_data)[i] = data[i];
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+// Private helper function to track initialization
+static ret_code_t _qspi_drv_init(void)
+{
+ static bool _initialized = false;
+ ret_code_t ret = NRF_ERROR_INVALID_STATE;
+
+ if(_initialized) {
+ //NRF implementation prevents calling init again. But we need to call init again to program the new command settings in the IFCONFIG registers.
+ //So, we have to uninit qspi first and call init again.
+ nrf_drv_qspi_uninit();
+ }
+ ret = nrf_drv_qspi_init(&config, NULL , NULL);
+ if( ret == NRF_SUCCESS )
+ _initialized = true;
+ return ret;
+}
+
+
+#endif
+
+/** @}*/
--- a/targets/TARGET_NORDIC/TARGET_NRF5x/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5x/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -140,8 +140,7 @@
void us_ticker_free(void)
{
nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_STOP);
-
nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0));
-
+ NVIC_DisableIRQ(TIMER1_IRQn);
us_ticker_initialized = false;
}
--- a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -163,7 +163,7 @@
#endif
// NOTE: board-specific
- STDIO_UART = UART_3
+ STDIO_UART = UART_0
} UARTName;
--- a/targets/TARGET_NUVOTON/TARGET_M2351/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -94,15 +94,19 @@
} PinDirection;
typedef enum {
+ /* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
- PushPull,
+ /* I/O mode */
+ InputOnly,
+ PushPullOutput,
OpenDrain,
- Quasi,
+ QuasiBidirectional,
- PullDefault = PullUp,
+ /* Default input pull mode */
+ PullDefault = PullUp
} PinMode;
typedef enum {
@@ -124,13 +128,13 @@
A1 = PB_10,
A2 = PB_9,
A3 = PB_8,
- A4 = PB_7,
- A5 = PB_6,
+ A4 = PB_4,
+ A5 = PB_5,
D0 = PA_8,
D1 = PA_9,
- D2 = PB_5,
- D3 = PB_4,
+ D2 = PB_7,
+ D3 = PB_6,
D4 = PB_3,
D5 = PB_2,
D6 = PC_12,
@@ -161,7 +165,7 @@
LED2 = PA_11,
LED3 = PA_10, // No real LED. Just for passing ATS.
LED4 = PA_11, // No real LED. Just for passing ATS.
- LED_GREEN = LED2,
+ LED_GREEN = LED1,
// Button naming
SW2 = PB_0,
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/TARGET_M23_NS/LICENSE Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file
--- a/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/TARGET_M23_NS/NuMaker-mbed-TZ-secure-example.hex Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/TARGET_M23_NS/NuMaker-mbed-TZ-secure-example.hex Thu Nov 08 11:46:34 2018 +0000 @@ -1,797 +1,873 @@ :020000040000FA -:1000000000080020050F0000D90B0000D90B0000EC +:1000000000080020AB100000190D0000190D0000C1 :1000100000000000000000000000000000000000E0 -:10002000000000000000000000000000D90B0000EC -:100030000000000000000000D90B0000D90B0000F8 -:10004000D90B0000D90B0000D90B0000D90B000020 -:10005000D90B0000D90B0000D90B0000D90B000010 -:10006000D90B0000D90B0000D90B0000D90B000000 -:10007000D90B0000D90B0000D90B0000D90B0000F0 -:10008000D90B0000D90B0000D90B0000D90B0000E0 -:10009000D90B0000D90B0000D90B0000D90B0000D0 -:1000A000D90B0000D90B0000D90B0000D90B0000C0 -:1000B000D90B0000D90B0000D90B0000D90B0000B0 -:1000C000D90B0000D90B0000D90B0000D90B0000A0 -:1000D000D90B0000D90B0000D90B0000D90B000090 -:1000E000D90B0000D90B0000D90B0000D90B000080 -:1000F000D90B0000D90B0000D90B0000D90B000070 -:10010000D90B0000D90B0000D90B0000D90B00005F -:10011000D90B0000D90B0000D90B0000D90B00004F -:10012000D90B0000D90B0000D90B0000D90B00003F -:10013000D90B0000D90B0000D90B0000D90B00002F -:10014000D90B0000D90B0000D90B0000D90B00001F -:10015000D90B0000D90B0000D90B0000D90B00000F -:10016000D90B0000D90B0000D90B0000D90B0000FF -:10017000D90B0000D90B0000D90B0000D90B0000EF -:10018000D90B0000D90B0000D90B0000D90B0000DF -:10019000D90B0000D90B0000D90B0000D90B0000CF -:1001A000D90B0000D90B0000D90B0000D90B0000BF -:1001B000D90B0000D90B0000D90B0000D90B0000AF -:1001C000D90B0000D90B0000D90B0000D90B00009F -:1001D000D90B0000D90B000000F002F800F02EF857 +:10002000000000000000000000000000190D0000AA +:100030000000000000000000190D0000190D000074 +:10004000190D0000190D0000190D0000190D000018 +:10005000190D0000190D0000190D0000190D000008 +:10006000190D0000190D0000190D0000190D0000F8 +:10007000190D0000190D0000190D0000190D0000E8 +:10008000190D0000190D0000190D0000190D0000D8 +:10009000190D0000190D0000190D0000190D0000C8 +:1000A000190D0000190D0000190D0000190D0000B8 +:1000B000190D0000190D0000190D0000190D0000A8 +:1000C000190D0000190D0000190D0000190D000098 +:1000D000190D0000190D0000190D0000190D000088 +:1000E000190D0000190D0000190D0000190D000078 +:1000F000190D0000190D0000190D0000190D000068 +:10010000190D0000190D0000190D0000190D000057 +:10011000190D0000190D0000190D0000190D000047 +:10012000190D0000190D0000190D0000190D000037 +:10013000190D0000190D0000190D0000190D000027 +:10014000190D0000190D0000190D0000190D000017 +:10015000190D0000190D0000190D0000190D000007 +:10016000190D0000190D0000190D0000190D0000F7 +:10017000190D0000190D0000190D0000190D0000E7 +:10018000190D0000190D0000190D0000190D0000D7 +:10019000190D0000190D0000190D0000190D0000C7 +:1001A000190D0000190D0000190D0000190D0000B7 +:1001B000190D0000190D0000190D0000190D0000A7 +:1001C000190D0000190D0000190D0000190D000097 +:1001D000190D0000190D000000F002F800F02EF8D3 :1001E0000CA030C8083824182D18671EA246AB464C :1001F00054465D46AC4201D100F020F87E460F3EE9 :10020000B6460FCC0126334200D0FB1A3343A24638 -:10021000AB461847402B0000602B00000023002451 +:10021000AB461847F82F00001830000000230024D8 :1002200000250026103A01D378C1FBD8520700D32D :1002300030C100D50B6070471FB51FBD054885460E -:1002400003B401F0B5F803BCFFF7F6FF00F016F9B0 -:1002500001F0ACF9000800207046F04710B5202AE4 -:1002600004DB0146203A9140002010BD914020233C -:100270009C1A0346E3401943904010BD10B5202A54 -:1002800004DB0846203AD040002110BD0B46202454 -:10029000D340D040A21A91400843194610BD4343B1 -:1002A000514330B55C18010C130C0D4692B25D43FE -:1002B00080B251432C19054655430A0C09044D19C7 -:1002C00062415843010C00044019514130BDFEB554 -:1002D000054610460C46184373D0AE468C460020A7 -:1002E000AD1A01469C4167D36646002701243D466E -:1002F000B61A9D4102D313463A46212465467646F6 -:100300002F04360C3E432D0CB61A9D4104D3150C18 -:100310001B042B4312041034654676462F06360A1A -:100320003E432D0AB61A9D4104D3150E1B022B43E2 -:1003300012020834654676462F0736093E432D09DA -:10034000B61A9D4104D3150F1B012B431201241D26 -:1003500065467646AF07B6083E43AD08B61A9D41DE -:1003600004D3950F9B002B439200A41C6546764650 -:10037000EF0776083E436D08B61A9D411AD39218CE -:100380005B41641C16E00018764665464941B71A81 -:100390009D410191009009D36046B11A98418E4663 -:1003A0008446009801990025401C6941DD075208E8 -:1003B0002A435B08641EE6D57246634603B0F0BD6F -:1003C000FFE700200146C046C0462A462346F5E71F -:1003D00010B501469E240002CA15A307002A02D0C8 -:1003E0001843002A04DBA21A002A0CDDD04010BDFD -:1003F0001206120E01D140004008A21A03D4D040C8 -:1004000040420028F3DDFF2248001206904201D945 -:10041000002010BDC817C043584010BD70B58D18DE -:100420000478401CA207920F01D10278401C2311CE -:1004300006D10378401C03E00678401C0E70491C6E -:10044000521EF9D1002B15D002780C2634408A1A9E -:10045000401C0C2C03D0A401121B9B1C08E0047848 -:100460002402121B401CF8E714780C70491C521C23 -:100470005B1EF9D5A942D3D3002070BD80B501F031 -:100480005BFC80BC01BC864601F088BB1F2101409B -:1004900001228A40000F0C2101401C480B58934355 -:1004A0000B50704710B571460446C80714D1601C44 -:1004B0000FD02B48083040F24C210322D2438258FF -:1004C000A24204D00C390C300029F6D101E00068BA -:1004D00010B9244801F03AF82046FFF7D7FF10BCC6 -:1004E00001BC86467046714672467346F4468EF3EA -:1004F000008874471F21014001228A40000F0C210F -:10050000014002480B5813430B507047040200404F -:1005100010B571460446C80714D1601C0FD01048AE -:10052000083040F24C210322D2438258A24204D028 -:100530000C390C300029F6D101E0006810B90948E7 -:1005400001F004F82046FFF7D5FF10BC01BC864639 -:100550007046714672467346F4468EF300887447BF -:1005600068280000772C0000F0B584B001273A0419 -:10057000B04D2B6C13432B642B68484E68B104229A -:1005800013432B602B6D1022134212D133465B1C98 -:100590000FD02C6D1442FAD00BE0012213432B60D4 -:1005A0002B6D134205D133465B1C02D02C6D1442D7 -:1005B000FAD03B4A8A183B4C3B4B9A4255D80190A3 -:1005C0003E4BCB183A4C0020A34200D307463C4B8D -:1005D00003269A42344600D33C46009402259A42B0 -:1005E00000D33D46A940C34307460290B01E0428ED -:1005F000039620D8ED48B0FBF6F0420002263046C4 -:100600005043304C0419304DAC420CD8451A0C1AEA -:10061000884200D825469D4205D20020002D2B4659 -:100620000296039F04D0761C1E488642E7D302E060 -:1006300003460296039F039E761C212ED6D1780294 -:1006400022494018009B9903019A1143029CA21E63 -:100650000A430243E64D2A64581C7843D349B1FB50 -:10066000F0F0604340000D4E0EE00321C94369588D -:10067000FE34214204D00D49084328640C4803E0AD -:100680000C49084328640C482A6D042102E0761CBA -:1006900002D02A6D0A42FAD004B0F0BDFF60DBFF41 -:1006A00000CA91FE02020000000E27070EC20000E1 -:1006B000006CDC020E4400000090D003009423FD87 -:1006C00000366E01002847FA00EA320600FEFFFFFE -:1006D000ED490A6802430A607047C046F0B52D48EC -:1006E000036802221340846B05210D0400212C4273 -:1006F00015D1A103284912D4A50B03262E40274D5E -:10070000AD5D660A1F2737407E1C6E436400244D92 -:100710002540244C6C436118B1FBF6F18900224C52 -:100720002160856807242C40022C1AD0012C0ED1A0 -:1007300048F200011D4C73B903681343036023683A -:100740000468944304608022134208D109E0A100A8 -:1007500017A2515805E0226880231A4201D047F6BB -:10076000005180690F220240501CB1FBF0F0784923 -:10077000086017494118174AB1FBF2F1164A116097 -:10078000F0BC02BC8E46714672467346F4468EF348 -:100790000088744708020040001BB70024280000AE -:1007A000FE030000C0C62D004C0F002000110440C5 -:1007B000001BB700008000000000000010270000B0 -:1007C00000000000006CDC0200000000001BB7000D -:1007D00020A1070040420F00E009002080B500F092 -:1007E00009FC5B48006880BC02BC8E4671467246BC -:1007F0007346F4468EF300887447C046BA480068D2 -:1008000001210140494269480840714672467346D9 -:10081000F4468EF300887447B3480068810348F2B9 -:1008200000000840714672467346F4468EF3008815 -:100830007447C04600020040810ACAB2002162B17A -:1008400041091F230B409A40000C0C210140BD4878 -:100850004058064941581140D940084671467246F1 -:100860007346F4468EF300887447C0462002004069 -:1008700010B501461F48081803280ED8810001A2B0 -:1008800051188F4600F006B800F01CB800F01EB8F2 -:1008900000F020B8184801681FE04A0E07231A40EC -:1008A0000020E2B1080D1F240440A240880E0C2154 -:1008B0000140A548405810494018D94340581040BD -:1008C000E0400CE00C480068410806E00A48006877 -:1008D000010A02E008480068410A0120084010BCF3 -:1008E00002BC8E46714672467346F4468EF300880B -:1008F0007447C046F0FFFF7F1802004080B500F04B -:1009000079FB134800681349096807220A40D04060 -:1009100080BC02BC8E46714672467346F4468EF326 -:100920000088744780B500F065FB094800680949F4 -:100930000968090907220A40D04080BC02BC8E46E3 -:10094000714672467346F4468EF300887447C0467B -:10095000540F00203402004010B5134801680520F0 -:1009600002040020114215D18803104812D48A0BCA -:10097000032313400E4AD25C4B0A1F241C40631C05 -:10098000534349000B4A0A400B4951430818B0FB36 -:10099000F3F0800010BC02BC8E467146724673466E -:1009A000F4468EF30088744740020040001BB700F5 -:1009B00024280000FE030000C0C62D000B4801687B -:1009C00004229143016048480168802291430160FC -:1009D00030BF70470548016804220A43026042485C -:1009E000016880220A43026030BF704710ED00E0CA -:1009F00000020040F0B581B03B4D2E6D0321C9438C -:100A0000695840F200320A402049884200D95AB160 -:100A10001F49884203D940F200139A4204D01D496D -:100A2000884200D8084601462868042738432860D1 -:100A30002A6D1020024205D1664A521C02D02B6D4D -:100A40000342FAD02869072202432A61286A0F224A -:100A5000904328622A6D0120024205D1C004FFF7AD -:100A600083FD04462E6D03E00020FFF77DFD044664 -:100A70000220002100F010F8F00602D42868B843E4 -:100A80002860204601B0F0BD000200400090D00375 -:100A9000006CDC0200366E01F0B581B0124C266DA0 -:100AA000226804252A43226010221640236D134237 -:100AB00005D1484B5B1C02D0276D1742FAD0226942 -:100AC00007231A432261226A0F27BA430A4322628C -:100AD000216999430143216100F08CFA16B920681D -:100AE000A843206001B0F0BD00020040F0B5002333 -:100AF000DC43830ADDB2124B75B146091F2737402C -:100B0000BD406540060C0C2737400E4EF659F618CE -:100B100037692F4017433761450E07222A406AB1D3 -:100B2000050D1F262E40B2406240800E0C2404406A -:100B300005480059C45814400C43C450F0BDC04689 -:100B400010020040142800000428000070B573460D -:100B500014460D460646D80714D1701C0FD0114814 -:100B6000083040F24C210322D2438258B24204D0D2 -:100B70000C390C300029F6D101E0006810B90A48A0 -:100B800000F0E4FC304629462246FFF7AFFF70BC78 -:100B900001BC86467046714672467346F4468EF333 -:100BA0000088744768280000772C000010B5084AB8 -:100BB000116801400123814207D0064C0021641CCA -:100BC00004D0116801408142F8D11946084610BD91 -:100BD00050020040FF60DBFFFEE7F0B500231C463B -:100BE0000125A5400D4207D015469D4003269E4095 -:100BF0000768B7432F4307609B1C641C102CEFD180 -:100C0000F0BD0000F0B581B001273C07FFF724FBE1 -:100C10006B4D6C4E2042284600D0304600903F0479 -:100C2000FFF71AFB204204D0009A70683842FCD0CB -:100C300003E0009A68683842FCD0D06B042101437D -:100C4000D16301B0F0BDC046F0B581B004460125C6 -:100C50002E07FFF701FB304201D05A4900E0584906 -:100C6000486928400090E0618B6907273B40E360BA -:100C70000B691E0D0F231E40374806600E69360CA7 -:100C80001E40364806600E69360B2E40344806601A -:100C90000D692D0A1D40334805600D692D09032695 -:100CA0003540314805600D691D4030480560CD680C -:100CB0002D0D35402E4E3560CD68280C18402D4D39 -:100CC0002860C868000B38402B4A1060C868000ACA -:100CD00018402A4A1060C86800093840284F386018 -:100CE000C8681840274908601B4800680A23584311 -:100CF0001A4A1268101840F2D07280182060184802 -:100D000000685843174A12688018606016480068E7 -:100D10005843164A12688018A060306858432A6801 -:100D200085182561009840B9152D04D30220206252 -:100D3000143D256101E0012020620F4800685843FE -:100D40000E4A126880183A685A430968511860615F -:100D5000A16101B0F0BDC0467820002090200020A5 -:100D60007020002088200020642000207C200020AB -:100D700068200020802000206C200020842000209B -:100D8000742000208C200020B0B504460120050707 -:100D9000FFF762FA284201D00A4800E008480A49F1 -:100DA00001600268012A03D0016001680129FCD1B9 -:100DB0002CB12046B0BC02BC8E4600F007B8B0BDD6 -:100DC00000100440001004505713EBA5F0B585B097 -:100DD0000446012001900507474E301F0490474FFD -:100DE000381F0090FFF738FA0395284201D0009889 -:100DF00004902046002C7CD001980504FFF72CFAC3 -:100E00000399084204D0049B38682842FCD003E0D0 -:100E1000049B30682842FCD0E169586919B10199F6 -:100E20000843586108E0019988435861206A022804 -:100E300002D1206914302061E0680493986121692F -:100E40000A200294B1FBF0F213054243891A090407 -:100E500019436269B2FBF0F31C030C434343D11AFC -:100E600009022143029A9269B2FBF0F304465C4303 -:100E7000121B0A43190111430191029C2168204A67 -:100E80008918B1FBF0F203465343C91A090412054D -:100E90000A436168B1FBF0F31C0314434343C91ACE -:100EA00009022143029A9268B2FBF0F35843101AE8 -:100EB00008431C010443FFF7CFF90399084203D00C -:100EC00038682842FCD002E030682842FCD0049800 -:100ED00004610446FFF7C0F90399084204D0019960 -:100EE00038682842FCD003E0019930682842FCD0E1 -:100EF000E16005B0F0BDC046041004400410045089 -:100F000030F8FFFF80B59648592101601621016035 -:100F10008821016001680029F6D0DB21C943044A19 -:100F200042500021016000F081F8FFF755F9FEE71B -:100F3000A55A00008A480021016070467146724639 -:100F40007346F4468EF300887447C04610B5010E10 -:100F5000094A8B58FF242406A04301248440A3435C -:100F60008B5010BC01BC8646704671467246734673 -:100F7000F4468EF3008874470800004010B57146AF -:100F80000446C80711D1601C0CD00F4840F24C2118 -:100F90000268A24204D00C390C300029F8D101E0DB -:100FA000806810B9094800F0D1FA20463CF080F87A -:100FB00010BC01BC86467046714672467346F446C4 -:100FC0008EF300887447C04668280000772C000024 -:100FD0006348592101601621016088210160016880 -:100FE0000029F6D07046714672467346F4468EF379 -:100FF0000088744780B53CF057F8074908603CF01A -:1010000033F806490860064940180649B0FBF1F07C -:101010000549086080BDC0464C0F0020540F0020D9 -:1010200020A1070040420F00E009002070B5E84809 -:101030003D490160D021032343501F22D4433B4D3F -:101040002E462640D4228650394EAD196D1E2540BD -:101050001D43D823C55004244450364C8450364C8C -:10106000C45005244450354D8550354DC550062596 -:101070004550344D8550344DC55007254550210706 -:1010800081503249C150C822012181508268082311 -:101090009A4382602E4A42602E480246C3322E4B4B -:1010A0001A6058600020C2439A60DA602B4B1A60C5 -:1010B0005A60941E9C60DA601A615A619A611A62E1 -:1010C0000C22521E0C4694405D6A25435D62042A40 -:1010D000F7D88A04996A914200D170BD20495923FA -:1010E0000B6016230B6088230B600B68002BF6D077 -:1010F0001C4B11241C601C4C5C60D86001201861E2 -:1011000018690028FCD19868401C0BD19A602120F6 -:10111000D8600120186118690028FCD1F720C0436D -:1011200001220A50FEE7C0460000000000D0030084 -:101130000010000000000410E1FF0710007E800096 -:10114000E37F800000800030E17F0130E1FFFF5F3E -:101150000000FA05FCFEFFFF80E300E000F0024023 -:101160000001004000C000400008200010B5044607 -:1011700000201B498C4209DC1D498C4213D01D49BB -:101180008C4212D01C498C420BD021E015498C4274 -:1011900005D015498C4204D014498C4218D1174807 -:1011A00004E0174802E00D4800E016483BF070FFED -:1011B00002280AD140F2001004430E48844208D1AC -:1011C00010BC01BC86463BF067BF80000EA10858EA -:1011D00010BD10BC01BC86463BF062BF0200805EC1 -:1011E000FF1005400011054000100550001105508A -:1011F0000000054000010540001005400500405F6B -:101200000400005F0300C05E001BB7000080000008 -:101210000000000000000000000000001027000097 -:1012200000000000001BB7000020EFF3058171B142 -:10123000324A11684B1C0AD048025C4B18581060A7 -:101240000C204843584A131810589860481C71469F -:1012500072467346F4468EF30088744710B5411EFB -:10126000EFF305820020072910D87AB10C224A43F7 -:101270004D4B9A189368083243B100201060480221 -:101280001E4A1368494C23501160012010BC02BC57 -:101290008E46714672467346F4468EF30088744754 -:1012A000B0B50020EFF30581F1B1404C01203E497B -:1012B00040F200220023A5180D604C608B60206076 -:1012C0000C31401C09282C46F4D1D84340F600616B -:1012D000364A50500948036082F30B8882F309882C -:1012E000022080F314880120B0BC02BC8E467146F7 -:1012F00072467346F4468EF300887447500F002000 -:1013000001460020EFF30582B2B10223EFF314820D -:101310001A40491E07290FD872B10C224A432249AC -:101320008A1811460831936833B1506880F30B88EE -:10133000086880F309880120714672467346F446B6 -:101340008EF300887447C046B0B501460020EFF325 -:101350000582F2B10223EFF314821A40491E0729D5 -:1013600017D8B2B10C224A430F4B9D1829460831B9 -:10137000AC6874B1EFF309846D68AC4209D39A5834 -:10138000944206D80C60094880F30B8880F30988E2 -:101390000120B0BC02BC8E46714672467346F446CC -:1013A0008EF300887447C046780F0020D80F0020C5 -:1013B00010B5074801687622064B10C910C3521EAB -:1013C000FBD10449016010BC01BC864600F0B6BCEC -:1013D00008ED00E000080020F0B583B003460020CF -:1013E000002B59D0002957D0029159690D46463D2E -:1013F000882D51D803250D400020461B6E41C8277B -:101400004F40019217430125002F009500D13D4622 -:101410002E4030257543214E75191E69B600AF590F -:101420009D6840F610666E435D683C246C431D6801 -:101430002C19A419DB681A4E7343E318DB19194CF5 -:101440001B19CE290CD1019A1AB9174CA342019A43 -:1014500022D8012A07D1154CA342019A1CD802E0D8 -:101460004729019A15DB1120C043471CC82900DC1D -:10147000384602B1384640F26D144C434A1ED51727 -:10148000AD0F52199210A2181018094A801846433D -:101490009B1902980360009803B0F0BDB42A0000C5 -:1014A0008051010080AEFEFF7F223100FFD02F006F -:1014B000329CFFFF10B5074C2068401C04D106A0E9 -:1014C00012A1552200F096FB00F030FA2068401C73 -:1014D000206010BDDC1F0020637269746963616C59 -:1014E0005F73656374696F6E5F7265656E74726158 -:1014F0006E63795F636F756E746572203C20554929 -:101500004E5433325F4D4158000000002E5C6D6236 -:1015100065642D6F735C706C6174666F726D5C6D69 -:101520006265645F637269746963616C2E63000055 -:101530000548016821B10168491E0160006800B1D9 -:10154000704700F003BAC046DC1F002083B070B5BE -:1015500081B0044605A80EC00C4E3078012804D195 -:1015600001B070BC01BC03B000470948002100F085 -:101570005DFA08A000F084FC0125357005A90091F2 -:10158000204600F0D8FB284600F010F8E81F0020A5 -:101590000001FF80466174616C2052756E2D746984 -:1015A0006D65206572726F720000000080B508B131 -:1015B00000F04CFBFEE70000F0B58FB072460D4620 -:1015C0000746D00709D10020C64378684168A94280 -:1015D00042D880684018A8423ED9FFF76BFF0995B2 -:1015E00001200B900346029000260C969448006858 -:1015F0000A90B8680169426989180D9100688018DD -:101600000E9001978F4C1C4309A8A04704960395A0 -:1016100005960696B868016942698918079180683D -:101620008018089003A8A0470746099502980B90D8 -:101630000C96834800680A900198806801694269A5 -:1016400089180D91406880180E9009A8A047F643AC -:1016500007B93E46FFF76CFF30460FB0F0BC02BC46 -:101660008E46714672467346F4468EF30088744780 -:101670000020714672467346F4468EF30088744724 -:101680007146CA07011D02B101460868006871462B -:1016900072467346F4468EF30088744710B573465D -:1016A00002460020C043DB0715D153685A689C6886 -:1016B000A2188A4226D91A69521E002A22DBDB6848 -:1016C000D4001B191C688C421BD9C4001B19521E64 -:1016D000002AF7DA16E013685A689C68A2188A4252 -:1016E00010D91A69521E002A0CDBDB68D4001B19C2 -:1016F0001C688C4205D9C4001B19521E002AF7DA57 -:1017000000E0586810BC02BC8E46714672467346B3 -:10171000F4468EF3008874477146CA07011D02B172 -:10172000014608688068714672467346F4468EF337 -:10173000008874477146CA07011D02B10146086856 -:101740004068714672467346F4468EF300887447CB -:1017500080B500F079F8002080BC02BC8E4671464E -:1017600072467346F4468EF300887447F0B58FB026 -:1017700074460D46E10713D1E9184F1E0021CE43F0 -:10178000AF4250D344686168A9424CD8A468641839 -:10179000AC4248D9AF4203D0B94244D8BC4242D946 -:1017A000019200930746FFF785FE099502200290FB -:1017B0000B9000260C96224800680A90B8680169D0 -:1017C000426989180D91006880180E9001201D4C07 -:1017D000044309A8A0470098049003950198059038 -:1017E0000696B8684169026952180792C0684018A5 -:1017F000089003A8A0470190099502980B900C96B9 -:101800000F4800680A90B8680169426989180D910B -:10181000406880180E9009A8A0470198F64300B9C7 -:101820000646FFF785FE30460FB0F0BC02BC8E4680 -:10183000714672467346F4468EF300887447C0467C -:10184000540F00205C0F00200249034A034B0AC0DA -:10185000026070474028000028280000542800003B -:1018600000487047282D00000A460168481C0ED029 -:10187000880840F2C03303400548184312B1012ADA -:1018800005D10122CBB201219940FFF7A6B97047DB -:1018900000400050B0B50D4604460160481C07D01A -:1018A0000021284600F08AFAE8B2012181406160F7 -:1018B000B0BD0022C046C04670B515460E4604466F -:1018C000FFF7E8FF701C23D02068411C05D11148A8 -:1018D0001149262200F08EF920680121002D0A46C8 -:1018E00000D12A4640F2C03340F2C0353C35860074 -:1018F0002E4080081840094B03439A512046FFF7B9 -:10190000B3FF0021204670BC04BC964600F008B826 -:1019100070BDC046242B00003C2B00000048005046 -:101920000068421C01D000F073BA7047EFF31081D9 -:10193000EFF3108072B62148027802B1704701229D -:1019400013468B431E490B700270704780B501200F -:10195000EFF31081014204D106A00DA1362200F060 -:1019600049F91648002101701548007800B162B6A7 -:1019700080BDC046216172655F696E746572727563 -:101980007074735F656E61626C6564282900000085 -:101990002E5C6D6265642D6F735C68616C5C6D625A -:1019A00065645F637269746963616C5F73656374B6 -:1019B000696F6E5F6170692E63000000C9200020AE -:1019C000D81F002010B5FB4C592020601620206045 -:1019D0008820206020680028F6D0FEF7FBFF00205A -:1019E000206010BC01BC8646704671467246734644 -:1019F000F4468EF30088744710B5EE4C59202060F1 -:101A0000162020608820206020680028F6D0FEF78D -:101A1000D5FF0020206010BC01BC86467046714690 -:101A200072467346F4468EF300887447F0B58BB067 -:101A300077460C460546002800DB194D194E3078D4 -:101A4000012800D1FEE7FFF735FD01203070FFF7D8 -:101A50006FFD154801684A1C026069B91348A0C0AF -:101A60000460043001A94CC94CC04CC94CC000975B -:101A7000CCC9CCC0009F0B4E0D48A0C00460043000 -:101A800001A91CC91CC01CC91CC03CC93CC00948D8 -:101A9000016809B106488847002030700BB0F0BDDE -:101AA0000101FF80E81F0020E01F002030200020FF -:101AB00094200020E41F0020F0B583B00446406865 -:101AC0003821405C08B103B0F0BD02912068006885 -:101AD0008047206880698047064605682DB92C48F4 -:101AE0002C49292200F086F82B4D1F20C1B201227B -:101AF0008A40954205D0401E0027FF210842F5D1BB -:101B000000E007467168081F1D2805D320482149B9 -:101B1000372200F06FF820210091606800260660EF -:101B200046602068406880470194646839216754A2 -:101B30000121029AA154A662E6622062A5600846CD -:101B40003146009F3A46FEF789FB411E3A1F0720A7 -:101B50009040E1602061104A31463346FEF79FFB1A -:101B600028187141401EB1412A463346FEF7AFFBAB -:101B7000A061E16126636663019C204600F056FC8B -:101B8000204603B0F0BC02BC8E4600F083BBC046CA -:101B9000782B00007A2B000040420F0080B51448DB -:101BA000016881F38888406801218843F0B4444685 -:101BB0004D4656465F46F0B4012188430146024631 -:101BC0000346044605460646074680468146824649 -:101BD0008346844680F300888447F0BCA046A9462B -:101BE000B246BB46F0BC3F20000600F07FFDFAE79E -:101BF0000000041070B514460D460646FFF75AFC67 -:101C000005A031462A46234600F094F870BC01BC7A -:101C1000864600F01BB8C0466D6265642061737330 -:101C20006572746174696F6E206661696C65643A8F -:101C30002025732C2066696C653A2025732C206C56 -:101C4000696E65202564200A00000000F0B585B0AB -:101C5000FFF730FC03A80A21FFF72BFE002640F215 -:101C6000C037314D0398411C05D126222F483049F9 -:101C7000FFF7C0FF039840F2C0343C34810021409C -:101C8000800838402843012201924250962000F0FB -:101C90003BFD0398411C05D1262224482449FFF727 -:101CA000A9FF039881002140800838402843002282 -:101CB00002924250962000F027FD761C042ED1D1CE -:101CC00004272E460398411C05D12622174818499F -:101CD000FFF790FF039881002140800840F2C03553 -:101CE00028403043019A425040F2901000F00CFD21 -:101CF0000398411C05D126220C480D49FFF77AFFB5 -:101D0000039881002140800828403043029A4250C5 -:101D100040F2901000F0F8FC7F1E3546D1D1029EB3 -:101D200040F2C0379EE7C04600480050242B000018 -:101D30003C2B00007047704770470000F0B581B041 -:101D40001B48017891BB012404701A4F5920386058 -:101D5000162038608820386038680028F6D00420C3 -:101D6000FEF7B6FC2046FEF7B3FC08252846FEF732 -:101D7000AFFC02263046FEF7ABFCA004FEF7A8FC41 -:101D80001020FEF713FF2046FEF710FF2846FEF74F -:101D90000DFF3046FEF70AFF4020FEF707FF06481A -:101DA000FEF728FEFFF726F90020386001B0F0BDED -:101DB000C8200020000100400090D0033BF094B9FF -:101DC000B0B50C460546401C04D12A482A494B228E -:101DD000FFF710FF68087C21014068097822024063 -:101DE00050180A494258AB001C251D400F23AB4038 -:101DF0009A4322434250B0BC01BC864670467146AD -:101E000072467346F4468EF30088744730000040F3 -:101E1000B0B50D460446401C04D11648164926228A -:101E2000FFF7E8FEA00840F2C03101401348084324 -:101E30000022052D16D8A90001A359188F46C046C7 -:101E400000F00AB800F008B800F00CB800F005B8CF -:101E500000F005B800F005B8B0BD012202E0022292 -:101E600000E00322E3B201219940B0BC08BC9E46C9 -:101E7000FEF7B3BE292B0000B62C00000040005036 -:101E800070B582B00446032040072E4E31680A46E2 -:101E900002404D42824200D08DB2080CC3B22A48A3 -:101EA0002A46FFF747FF2948281807282DD8810020 -:101EB00001A251188F46C04600F00EB800F00FB8CE -:101EC00000F010B800F011B800F012B800F013B82C -:101ED00000F014B800F015B8B1683EA013E0B16886 -:101EE00038A010E0B16833A00DE0B1682CA00AE082 -:101EF000B16826A007E0B1681BA004E0B1681EA08D -:101F000001E0B16812A0FFF715FF2046FFF712FFAE -:101F100071683648FFF70EFFB1683548FFF70AFFD2 -:101F200033460C330ECBB069F4696D4611C53148A8 -:101F3000FFF700FF304802B070BC02BC8E46FFF7CE -:101F4000F9BEC04694200020B42B0000CFFEFFFF56 -:101F50004D65737361676551756575653A203078B5 -:101F600025582C200000000054696D65723A20301D -:101F70007825582C200000004576656E74466C610B -:101F800067733A20307825582C2000004D656D6F1E -:101F90007279506F6F6C3A20307825582C200000F1 -:101FA00053656D6170686F72653A20307825582CE2 -:101FB000200000004D757465783A20307825582C43 -:101FC000200000005468726561643A20307825581A -:101FD0002C2000004B65726E656C204572726F722A -:101FE0003A20307825582C2000000000672C000093 -:101FF000542C0000052C00009A2B000080B59F484F -:102000003BF05AF880BC01BC864670467146724669 -:102010007346F4468EF300887447C04610B5964860 -:1020200000680221084202D194483BF049F8184860 -:1020300000680121084207D100242046FEF7A4FED3 -:10204000204621463BF064F810BC01BC8646704631 -:10205000714672467346F4468EF300887447C04654 -:1020600080B5854800680221084202D183483BF0D0 -:1020700027F8074801680120084080BC02BC8E4652 -:10208000714672467346F4468EF300887447C04624 -:1020900000100440F0B597B077480068022108426C -:1020A00002D176483BF00CF80320C043744D285809 -:1020B0000127384201D13BF01FF83E043C073C4861 -:1020C000017891BB01940770642011900024109452 -:1020D0000F97062012900E940D940C940CA835497D -:1020E0002246FFF779F90028214656D0664CFEF7C4 -:1020F000B3F80199084203D020683042FCD002E0D6 -:1021000028683042FCD0FEF77DFDFEF7A5F8019966 -:10211000084203D020683042FCD002E028683042F8 -:10212000FCD0E86B57490860019CFEF795F8204207 -:1021300004D0554801683142FCD002E028683042A2 -:10214000FCD003A8FEF780FD05980F90069812902A -:1021500007980E901849039A511811910499491E35 -:1021600010910A9921B90B99022901D10C300E90D6 -:1021700008980D9009980C900CA802A900242246FA -:10218000FFF72AF90028214607D03E480068029947 -:10219000081808490968441A0021204617B0F0BC05 -:1021A00004BC964672467346F4468EF30088744724 -:1021B000D0200020CC20002094F8FFFFF0B581B0A3 -:1021C00005462D4800680221084202D12B483AF00A -:1021D00077FF03200090C043294F38580124204244 -:1021E00001D13AF089FF2748056025042407264ECF -:1021F000FEF732F8204203D030682842FCD002E0DB -:1022000038682842FCD0FEF7FDFCFEF725F8204296 -:1022100003D030682842FCD002E038682842FCD065 -:1022200018480068F863FEF717F8204203D03068BA -:102230002842FCD002E038682842FCD01348FEF760 -:10224000C5FD0D48416948F200020098014200D0E6 -:102250000F4AF349B1FBF2F1484300F05AFA01B0DA -:10226000F0BC01BC86467046714672467346F44621 -:102270008EF300887447C046080200400100807257 -:1022800004100440D420002004100450E027000073 -:1022900010270000F0B583B00446456800F0C6F88A -:1022A00067687968B9B301950294386B0B680125AA -:1022B000002483422E4600D826467A6B4968914214 -:1022C00000D82546914200D02E4686B30026181A23 -:1022D00034467441BB69012598422B4600D83346E9 -:1022E000641E9141FA69914200D835469142029CA0 -:1022F00000D02B463D69002B019E27D1BA68C84B00 -:102300009A4220D03923FB5CA3B11A46FDF7A6FF01 -:10231000C34A002315E0286AE9682A6910180840B2 -:102320002168096903B0F0BC04BC964608470298CE -:10233000006824E000230093009BFDF7B0FFB84A3B -:10234000009BFDF7C4FF854200D30546386A40195B -:10235000FD6805402068316A8D4210D00169284629 -:102360008847206840688047316A8D4202D9A84278 -:1023700002D303E0A84208D3884206D2206840690D -:1023800003B0F0BC02BC8E46004703B0F0BDC046AF -:10239000F0B581B00446FFF78DF82068C06880472B -:1023A00060684068F8B1204600F040F861680B6B47 -:1023B00048680668012200259E42134600D82B4635 -:1023C0004E6B4768B74200D82A46B74200D0134642 -:1023D0004BB9C2684A60096819B18068884760686B -:1023E0004268002ADFD12046FFF754FF01B0F0BC5D -:1023F00001BC8646FFF79CB880B500F001F880BDAF -:1024000010B50446FFF758FBFFF754F8204600F0DC -:102410000DF8FFF78DF86168086B496B10BD00007F -:1024200041480121016000F035B9C046F0B585B0E2 -:10243000044600686668406880476168096A8842A7 -:102440006CD0316A3062401AB268F46804400021EE -:10245000734882425CD00492714A00272046394674 -:102460003B46FDF71CFF3922B55C002D03901FD0C1 -:1024700001970F462A46FDF701FF044602912A46BE -:10248000FDF7ECFE039A101A019B1A465A41521EA0 -:102490008F41B16A0918B162F06A7841F062012295 -:1024A000049DA9421F4600D33A4608B33A461FE0AE -:1024B00000250F46049A2B46FDF709FF04460291BA -:1024C000049A2B46FDF7EBFE2B46039A101A2A4678 -:1024D0006A41521E8F41B16A4118B162F06A784177 -:1024E000049DF0620122A94200D31A4600B11A46A7 -:1024F000334628330AB102990AE00022491B1960C9 -:1025000011465141491E90415860641C0299514145 -:10251000306B00193063706B4841706305B0F0BDDB -:10252000014801210160704708000540374801213A -:102530000160BFF34F8FBFF36F8F704702480121D7 -:10254000016069480160704704E200E0004870479C -:102550004C2D0000F0B583B02B48018859B12B48B1 -:1025600001210160BFF34F8FBFF36F8F2848816057 -:102570002848016046E00126068027483AF0ACFD75 -:10258000264C0022204640F200213AF09DFD2046D4 -:102590003AF096FD1E4C2046FEF7E8FD204DB0FBBC -:1025A000F5F14F1E802F08D302901EA001912C49F7 -:1025B0006B22FFF71FFB019902984D43401B04D08B -:1025C00028A027496C22FFF715FB0320C00607430C -:1025D0002760434860602D480068C0212C4A425063 -:1025E0000A480660BFF34F8FBFF36F8F70072168F3 -:1025F00001432160B0072168014321607006216812 -:102600000142FBD003B0F0BDD820002084E100E0FF -:102610000000054084E200E0020000040200805E49 -:1026200040420F00287072657363616C655F746966 -:102630006D657220213D202875696E7433325F7498 -:1026400029202D3129202626207072657363616C44 -:10265000655F74696D6572203C3D20313237000042 -:10266000ED2C000028636C6B5F74696D657220252A -:10267000204E555F544D52434C4B5F5045525F5373 -:10268000454329203D3D20300000000008ED00E0DA -:10269000212400000248016809B102480847704738 -:1026A000580F0020282D000080B50448008808B984 -:1026B000FFF750FF0248006880BDC046D8200020C8 -:1026C0000C0005400221022800D80846044988422F -:1026D00000D30846034908600348012101607047A0 -:1026E000FFFFFF000400054004E100E080B505495C -:1026F00000F01EF8FDF76CFE80BC02BC8E4600F0B8 -:1027000008B8C0460024744940F2E8314843C04646 -:10271000C04670B50446FFF7A3F80546FFF76CFE08 -:1027200006462846FFF768FE801BA042F9D370BD1D -:1027300070B5420064414B005C41120E39D01B0E53 -:1027400038D0FF2A3CD0FF2B3AD0D2187F3A400233 -:102750004902400A490A4518ED0106004E43000AA5 -:10276000090A48430104731A4019190C4318990FB8 -:1027700004D05B08012149075B1A521CD80904D315 -:10278000401CF50301D19D0607D0FF2A08D2D505CC -:1027900006D0E4072043401970BD0125A843F4E7A3 -:1027A000002A01DCE00770BD2402FF202043C005A1 -:1027B00070BD1B0EFF2A03D0FF2B01D0E00770BDB8 -:1027C000FF2636064500B54206D84D00B54203D86F -:1027D000D218FF2A00D0E7E7004870BD0000C07F94 -:1027E000D00700000100000001000000060000000A -:1027F00000000000000000000000000001000000D8 -:1028000000000000000000000400000008000000BC -:102810000C000000000000000400000008000000A0 -:102820001000000001020204D7000000890100002E -:102830006F0200001903000064050000E409002095 -:10284000040000000000000000000400142B000041 -:10285000010000000400000000000410000004005B -:102860001C2B00000100000004000000903C8002CE -:10287000000200000600000006FF430700200000E1 -:10288000FFFFFFFFFFFFFFFF00400000030000000D -:1028900003000000000001001D0000000100000016 -:1028A0000000000107000000070000000000020017 -:1028B0000C0000000C00000000000400FFFFFFFF00 -:1028C00001008072000000001C0000041CFE034098 -:1028D000080000000700000407000040200000007E -:1028E000FFFFFFFFFFFFFFFF400000000C0000089C -:1028F0000C000080800000001D0000041D00007717 -:10290000000100001A0000049A3C804200200000F0 -:10291000040000040400005F000002000500000441 -:102920000500405F00000200100000081000008059 -:1029300000000001110000081100008000000002EA -:1029400012000008120000800000000413000008BC -:1029500013000080000000080D0000040D00406618 -:10296000010000000E0000040E006066020000007E -:102970000F0000040E00606604000000060000085E -:102980000600C0A608000000FFFFFFFFFFFFFFFFDB -:1029900010000000070000080700E0A6200000006B -:1029A00010000004103D80570000010011000004D9 -:1029B000913DA0570000020012000004123C8C77E9 -:1029C0000000040013000004933CAC7700000800F2 -:1029D00014000004143DCC77000010001500000422 -:1029E000953DEC770000200008000004080000403E -:1029F000010000000900000409000040020000007E -:102A00000A0000040A000040040000000000000862 -:102A100000FC07B6000001000100000801FD27B618 -:102A2000000002000200000802FE47B60000040099 -:102A30001800000418000040010000001600000803 -:102A40001600008000000100170000081700008039 -:102A5000000002001A0000081A00008000001000A8 -:102A60001B0000081B00008000002000170000046D -:102A7000177F345200008000FFFFFFFFFFFFFFFFC2 -:102A8000000000011F000004190000800000000287 -:102A90001B0000049B3C804201000000080000086D -:102AA0000800008000000100090000080900008003 -:102AB000000002000000000080DE280080C84D00F9 -:102AC00000A7760000349E008012C700809FEE00B1 -:102AD000007E1701805C400180E9670100C8900119 -:102AE0000055B8010000000080DE2800001A4F00E9 -:102AF00080F8770080859F000064C80000F1EF0037 -:102B000080CF180100AE4101003B6901801992019C -:102B100080A6B901000000000008000000000410B9 -:102B2000000800006F626A2D3E70696E20213D2012 -:102B30002850696E4E616D65294E43002E5C6D62B2 -:102B400065642D6F735C746172676574735C544166 -:102B5000524745545F4E55564F544F4E5C54415268 -:102B60004745545F4D323335315C6770696F5F6F35 -:102B7000626A6563742E680030002E5C6D62656465 -:102B80002D6F735C68616C5C6D6265645F74696312 -:102B90006B65725F6170692E63000A2D2D204D6296 -:102BA00065644F53204572726F7220496E666F20C4 -:102BB0002D2D0A000A0A2B2B204D6265644F5320ED -:102BC0004572726F7220496E666F202B2B0A457218 -:102BD000726F72205374617475733A20307825587F -:102BE00020436F64653A202564204D6F64756C65E1 -:102BF0003A2025640A4572726F72204D65737361C5 -:102C000067653A20000A43757272656E74205468D5 -:102C1000726561643A2049643A203078255820452D -:102C20006E7472793A203078255820537461636B42 -:102C300053697A653A203078255820537461636B64 -:102C40004D656D3A20307825582053503A20307821 -:102C5000255820000A4572726F722056616C7565A6 -:102C60003A2030782558000A4C6F636174696F6EA2 -:102C70003A2030782558004E6F6E2D73656375725B -:102C80006520646F6D61696E20747269657320746C -:102C90006F20636F6E74726F6C20736563757265FD -:102CA000206F7220756E646566696E6564206D6F55 -:102CB00064756C652E002E5C6D6265642D6F735CAF -:102CC000746172676574735C5441524745545F4E3A -:102CD00055564F544F4E5C5441524745545F4D3208 -:102CE0003335315C70696E6D61702E63002E5C6DE2 -:102CF0006265642D6F735C746172676574735C5494 -:102D000041524745545F4E55564F544F4E5C5441C7 -:102D1000524745545F4D323335315C75735F74698A -:102D2000636B65722E630000302D0000F01F0020E1 -:102D300055250000A92600002D25000021250000B2 -:102D4000C52600003D2500004D25000040420F0033 -:102D500018000000742D0000E00900209805000014 -:102D60001C04000050300000780F002064110000A7 -:102D70001C020000101D3000000085B00A4603460A -:102D8000039002A8017001920093FFE74CF2C0008B -:102D9000C4F21B100B680121084201D0FFE7F514B3 -:102DA000320014300C01684022114301604CF20CD7 -:102DB00010100B2221016003984CF204010E5015F3 -:102DC00001086002A80078002808D1FFE70020C0B1 -:102DD000434CF208181309E00C3132200B4AF60379 -:102DE00021C0F2550101606A421056114600051CCF -:102DF000BFF36F8F7C100400684090120B14E18EBB -:102E000010080120049002E00006201DFFE704984E -:102E100005B07047B0B587B013460C46054605901F -:102E20000491039240F200107E12596A12166E123B -:102E300088B841E0100802930194009503B210078E -:102E40000120069038E02A42205C3204EA50044017 -:102E5000F2041021F83006FFE740F250202404006D -:102E600068101EC6D11E56011E321CF8120A646379 -:102E700010425CE30AE0B812007204111EFFE7067C -:102E80009807B0B0BD82B001460190009180400427 -:102E900001229162452811D01004084602F2072C45 -:102EA00081B0BA16260615B8714696C8AE05489880 -:102EB0003600981600981004009801A6100480B5FA -:102EC00084E8100A029002984FF6FF72CE04431075 -:102ED000400E70040002CF0E14100F221205104095 -:102EE00001225205904201910B64170298C21015FD -:102EF00001CFF6E07140180121FFF7A4FE03900511 -:102F0000E00298000C129E0C380CFFE7039804B006 -:102F100080BD80B586D048090490039100200290BE -:102F2000D228090298039988420FD21E10120299E2 -:102F30004A1C029289004058FFF7B8FF002803B8E6 -:102F400018080120059003E0EBB416059010040565 -:102F500098064A5804B0B58842201206900591049C -:102F6000920598C01C03218843059006BC1271BCD1 -:102F70000C0C2C71084006900393029401953603C3 -:102F80001621702168140400283F369E0640030471 -:102F90000752049800F03CF88A100B07900CE006EA -:102FA00098001D06906410041D04907E1C051F05EA -:102FB00090BCA8031A078418040798088456839CB9 -:102FC00016422270040078010A90070002019A104C -:102FD0001810D204104206203C0601980091037E8E -:102FE0000305163C05322E76002E36532E857E853F -:102FF000386D5E0429CA0546341D98037F901DB8BC -:103000000428110068049900900846FFF76CFF003F -:1030100099814238212205125632A81A655642007B -:103020000110056CDC02FF01210800210091230042 -:103030000030B54D4620B4456903699946C368829E -:103040006841680068A84720BCA94630BD00000060 +:1002400003B401F0D4F903BC00F01DF900F025F966 +:1002500001F0DCFA000800207046F047704710B546 +:10026000202A04DB0146203A9140002010BD914035 +:1002700020239C1A0346E3401943904010BD10B55B +:10028000202A04DB0846203AD040002110BD0B464E +:100290002024D340D040A21A91400843194610BDF3 +:1002A0004343514330B55C18010C130C0D4692B218 +:1002B0005D4380B251432C19054655430A0C09048D +:1002C0004D1962415843010C00044019514130BDA1 +:1002D000FEB5054610460C46184373D0AE468C4614 +:1002E0000020AD1A01469C4167D3664600270124D1 +:1002F0003D46B61A9D4102D313463A46212465462F +:1003000076462F04360C3E432D0CB61A9D4104D37D +:10031000150C1B042B4312041034654676462F0639 +:10032000360A3E432D0AB61A9D4104D3150E1B0210 +:100330002B4312020834654676462F0736093E43A2 +:100340002D09B61A9D4104D3150F1B012B43120131 +:10035000241D65467646AF07B6083E43AD08B61A7B +:100360009D4104D3950F9B002B439200A41C65462E +:100370007646EF0776083E436D08B61A9D411AD3BC +:1003800092185B41641C16E00018764665464941A8 +:10039000B71A9D410191009009D36046B11A984166 +:1003A0008E468446009801990025401C6941DD076E +:1003B00052082A435B08641EE6D57246634603B0C2 +:1003C000F0BDFFE700200146C046C0462A4623464E +:1003D000F5E770477047704710B501469E2400024C +:1003E000CA15A307002A02D01843002A04DBA21A68 +:1003F000002A0CDDD04010BD1206120E01D14000C3 +:100400004008A21A03D4D04040420028F3DDFF2266 +:1004100048001206904201D9002010BDC817C04301 +:10042000584010BD704770B58D180478401CA20765 +:10043000920F01D10278401C231106D10378401C91 +:1004400003E00678401C0E70491C521EF9D1002BA7 +:1004500015D002780C2634408A1A401C0C2C03D08C +:10046000A401121B9B1C08E004782402121B401CF0 +:10047000F8E714780C70491C521C5B1EF9D5A94290 +:10048000D3D3002070BD42F2E000C2F2000048F277 +:100490000001C2F20001FFF7CFBE80B501F09AFD66 +:1004A00080BC01BC864601F0B1BC1F210140012285 +:1004B0008A40000F0C21014040F20420C4F20000E9 +:1004C0000B5893430B50704710B571460446C8074C +:1004D0001AD1601C12D042F6D040C0F200000830A1 +:1004E00040F24C210322D2438258A24204D00C395C +:1004F0000C300029F6D101E0006828B943F22B1036 +:10050000C0F2000001F04EF92046FFF7CEFF10BC0C +:1005100001BC86467046714672467346F4468EF3B9 +:10052000008874471F21014001228A40000F0C21DE +:10053000014040F20420C4F200000B5813430B505A +:10054000704710B571460446C8071AD1601C12D016 +:1005500042F6D040C0F20000083040F24C210322A5 +:10056000D2438258A24204D00C390C300029F6D173 +:1005700001E0006828B943F22B10C0F2000001F03E +:1005800011F92046FFF7CEFF10BC01BC864670462D +:10059000714672467346F4468EF300887447F0B590 +:1005A00084B001273A0440F20025C4F200052B6C08 +:1005B00013432B642B6846F2FF06CFF6DB7668B157 +:1005C000042213432B602B6D1022134212D13346A9 +:1005D0005B1C0FD02C6D1442FAD00BE001221343A8 +:1005E0002B602B6D134205D133465B1C02D02C6D62 +:1005F0001442FAD04CF60022CFF691628A1840F2EB +:10060000022440F60063C0F227739A4274D8019026 +:1006100049F20043CFF62353CB1846F60044C0F20C +:10062000DC240020A34200D3074643F20063C0F25B +:100630006E1303269A42344600D33C4600940225AA +:100640009A4200D33D46A940C34307460290B01EDC +:10065000042803962AD841F60030C0F2B700B0FB58 +:10066000F6F0420002263046504342F60004CFF630 +:10067000472404194EF60025C0F23265AC420CD86E +:10068000451A0C1A884200D825469D4205D2002002 +:10069000002D2B460296039F05D0761C40F20220C7 +:1006A0008642E0D302E003460296039F039E761C37 +:1006B000212ECCD178024FF60061CFF6FF714018A1 +:1006C000009B9903019A1143029CA21E0A43024314 +:1006D00040F20025C4F200052A64581C784341F614 +:1006E0000031C0F2B701B1FBF0F06043400046F2C8 +:1006F000FF06CFF6DB7616E00321C9436958FE34C6 +:10070000214208D04CF20E210843286446F60040EE +:10071000C0F2DC2007E044F20E410843286449F2AD +:100720000000C0F2D0302A6D042102E0761C02D015 +:100730002A6D0A42FAD004B0F0BD40F20021C4F2A2 +:1007400000010A6802430A6070470000F0B540F2F9 +:100750000820C4F20000036802221340846B0521C4 +:100760000D0400212C421FD1A10341F60031C0F23B +:10077000B70119D4A50B03262E4042F68C45C0F2D2 +:100780000005AD5D660A1F2737407E1C6E4364007E +:1007900040F2FE3525404CF2C064C0F22D046C439B +:1007A0006118B1FBF6F1890040F64C74C2F2000406 +:1007B0002160856807242C40022C1DD0012C11D10A +:1007C00048F2000141F20014C4F2040473B9036852 +:1007D0001343036023680468944304608022134237 +:1007E00008D109E0A10017A2515805E02268802332 +:1007F0001A4201D047F6005180690F220240501C76 +:10080000B1FBF0F040F65471C2F2000108604AF208 +:100810002011C0F20701411844F24022C0F20F0239 +:10082000B1FBF2F140F6E012C2F200021160F0BC3E +:1008300002BC8E46714672467346F4468EF30088BB +:100840007447C046001BB700008000000000000095 +:100850001027000000000000006CDC020000000017 +:10086000001BB70080B500F09FFC40F65470C2F248 +:100870000000006880BC02BC8E467146724673461A +:10088000F4468EF30088744740F20020C4F2000062 +:10089000006801210140494241F60030C0F2B70032 +:1008A0000840714672467346F4468EF300887447DA +:1008B00040F20020C4F200000068810348F200000A +:1008C0000840714672467346F4468EF300887447BA +:1008D000810ACAB2002192B141091F230B409A40FC +:1008E000000C0C21014042F67C40C0F20000405850 +:1008F00040F22021C4F2000141581140D94008467D +:10090000714672467346F4468EF3008874470000C1 +:1009100010B501464FF6F070C7F6FF7008180328AF +:1009200012D8810001A251188F46C04600F006B8C7 +:1009300000F025B800F02AB800F02FB840F21820D7 +:10094000C4F2000001682EE04A0E07231A4000207E +:100950005AB3080D1F240440A240880E0C21014008 +:1009600042F66C40C0F20000405840F21821C4F238 +:1009700000014018D94340581040E04015E040F2D3 +:100980001820C4F20000006841080CE040F2182072 +:10099000C4F200000068010A05E040F21820C4F229 +:1009A00000000068410A0120084010BC02BC8E46CD +:1009B000714672467346F4468EF30088744780B5DC +:1009C00000F0F2FB40F65470C2F20000006840F202 +:1009D0003421C4F20001096807220A40D04080BCDB +:1009E00002BC8E46714672467346F4468EF300880A +:1009F000744780B500F0D8FB40F65470C2F2000096 +:100A0000006840F23421C4F2000109680909072294 +:100A10000A40D04080BC02BC8E4671467246734686 +:100A2000F4468EF30088744710B540F24020C4F2BB +:100A30000000016805200204002011421FD1880334 +:100A400041F60030C0F2B70019D48A0B03231340DB +:100A500042F68C42C0F20002D25C4B0A1F241C40BA +:100A6000631C5343490040F2FE320A404CF2C0611D +:100A7000C0F22D0151430818B0FBF3F0800010BC08 +:100A800002BC8E46714672467346F4468EF3008869 +:100A900074474EF61050CEF20000016804229143D4 +:100AA000016040F20020C4F20000016880229143FE +:100AB000016030BF704780B5FFF7EBFF80BC01BC21 +:100AC00086467046714672467346F4468EF3008839 +:100AD00074474EF61050CEF20000016804220A431B +:100AE000026040F20020C4F20000016880220A4344 +:100AF000026030BF704780B5FFF7EBFF80BC01BCE0 +:100B000086467046714672467346F4468EF30088F8 +:100B10007447F0B581B040F20025C4F200052E6D97 +:100B20000321C943695840F200320A4049F20001EA +:100B3000C0F2D031884200D98AB146F60041C0F2F5 +:100B4000DC21884203D940F200139A4207D043F2D5 +:100B50000061C0F26E11884200D80846014628683C +:100B60000427384328602A6D1020024208D146F23B +:100B7000FF02CFF6DB72521C02D02B6D0342FAD07B +:100B80002869072202432A61286A0F2290432862BB +:100B90002A6D0120024205D1C004FFF700FD044682 +:100BA0002E6D03E00020FFF7FAFC0446022000212E +:100BB00000F008F8F00602D42868B8432860204600 +:100BC00001B0F0BDF0B581B040F20024C4F20004E1 +:100BD000266D226804252A43226010221640236DC8 +:100BE000134208D146F2FF03CFF6DB735B1C02D041 +:100BF000276D1742FAD0226907231A432261226A1D +:100C00000F27BA430A4322622169994301432161B4 +:100C100000F0CAFA16B92068A843206001B0F0BD00 +:100C2000F0B50023DC43830ADDB240F21023C4F2A6 +:100C300000038DB146091F273740BD406540060CB3 +:100C40000C27374042F67C46C0F20006F659F618EB +:100C500037692F4017433761450E07222A4082B17A +:100C6000050D1F262E40B2406240800E0C24044029 +:100C700042F66C40C0F200000059C45814400C43C6 +:100C8000C450F0BD70B5734614460D460646D807ED +:100C90001AD1701C12D042F6D040C0F200000830C9 +:100CA00040F24C210322D2438258B24204D00C3984 +:100CB0000C300029F6D101E0006828B943F22B106E +:100CC000C0F2000000F06EFD304629462246FFF7D4 +:100CD000A7FF70BC01BC86467046714672467346DB +:100CE000F4468EF30088744710B540F25022C4F2E7 +:100CF000000211680140012381420AD046F2FF043C +:100D0000CFF6DB740021641C04D0116801408142DD +:100D1000F8D11946084610BDFEE7F0B500231C4681 +:100D20000125A5400D4207D015469D4003269E4053 +:100D30000768B7432F4307609B1C641C102CEFD13E +:100D4000F0BDF0B581B001273C07FFF785FA41F20D +:100D50000005C4F2040541F20006C5F20406204273 +:100D6000284600D0304600903F04FFF775FA204235 +:100D700004D0009A70683842FCD003E0009A68689A +:100D80003842FCD0D06B04210143D16301B0F0BDE7 +:100D9000F0B581B0044601252E07FFF75DFA304219 +:100DA00004D041F20001C5F2040103E041F2000168 +:100DB000C4F20401486928400090E0618B6907276C +:100DC0003B40E3600B691E0D0F231E4042F278008A +:100DD000C2F2000006600E69360C1E4042F290001E +:100DE000C2F2000006600E69360B2E4042F270001F +:100DF000C2F2000006600D692D0A1D4042F2880013 +:100E0000C2F2000005600D692D090326354042F24B +:100E10006400C2F2000005600D691D4042F27C00D2 +:100E2000C2F200000560CD682D0D354042F2680623 +:100E3000C2F200063560CD68280C184042F28005E9 +:100E4000C2F200052860C868000B384042F26C020C +:100E5000C2F200021060C868000A184042F2840220 +:100E6000C2F200021060C8680009384042F27407FC +:100E7000C2F200073860C868184042F28C01C2F222 +:100E80000001086042F27800C2F2000000680A2304 +:100E9000584342F29002C2F200021268101840F267 +:100EA000D0728018206042F27000C2F20000006828 +:100EB000584342F28802C2F2000212688018606051 +:100EC00042F26400C2F200000068584342F27C0221 +:100ED000C2F2000212688018A060306858432A6885 +:100EE00085182561009840B9152D04D30220206291 +:100EF000143D256101E00120206242F26C00C2F243 +:100F000000000068584342F28402C2F200021268F4 +:100F100080183A685A43096851186061A16101B0AC +:100F2000F0BDB0B5044601200507FFF795F928424A +:100F300004D041F20000C5F2040003E041F20000D9 +:100F4000C4F2040041F25731CAF2EB510160026869 +:100F5000012A03D0016001680129FCD12CB120468F +:100F6000B0BC02BC8E4600F001B8B0BDF0B585B093 +:100F7000044601200190050741F20406C4F204066C +:100F8000301F049041F20407C5F20407381F009097 +:100F9000FFF762F90395284201D00098049020469B +:100FA000002C00D17FE001980504FFF755F9039963 +:100FB000084204D0049B38682842FCD003E0049B1C +:100FC00030682842FCD0E169586919B10199084399 +:100FD000586108E0019988435861206A022802D1CB +:100FE000206914302061E0680493986121690A2027 +:100FF0000294B1FBF0F213054243891A0904194324 +:101000006269B2FBF0F31C030C434343D11A09029B +:101010002143029A9269B2FBF0F304465C43121B2F +:101020000A43190111430191029C21684FF63002D5 +:10103000CFF6FF728918B1FBF0F203465343C91A89 +:10104000090412050A436168B1FBF0F31C03144361 +:101050004343C91A09022143029A9268B2FBF0F392 +:101060005843101A08431C010443FFF7F5F803998D +:10107000084203D038682842FCD002E03068284299 +:10108000FCD0049804610446FFF7E6F8039908428F +:1010900004D0019938682842FCD003E001993068F7 +:1010A0002842FCD0E16005B0F0BD80B540F20010F0 +:1010B000C4F20000592101601621016088210160FD +:1010C00001680029F6D0DB21C94345F6A52242502C +:1010D0000021016000F088F8FFF77EF8FEE740F29B +:1010E0000010C4F200000021016070467146724693 +:1010F0007346F4468EF3008874474FF6FF71C0F2D2 +:10110000FF01014001228A40000E40F20801C4F2B2 +:1011100000014358934343507046714672467346EC +:10112000F4468EF30088744710B571460446C8072C +:1011300017D1601C0FD042F6D040C0F2000040F240 +:101140004C210268A24204D00C390C300029F8D19D +:1011500001E0806828B943F22B10C0F2000000F0D3 +:1011600021FB20463BF0A4FF10BC01BC8646704624 +:10117000714672467346F4468EF30088744740F217 +:101180000010C4F20000592101601621016088217D +:10119000016001680029F6D07046714672467346B8 +:1011A000F4468EF30088744780B53BF07DFF40F62F +:1011B0004C71C2F2000108603BF056FF40F65471DA +:1011C000C2F2000108604AF22011C0F20701401883 +:1011D00044F24021C0F20F01B0FBF1F040F6E01103 +:1011E000C2F20001086080BD70B54EF60850CEF224 +:1011F000000040F20001C0F200010160D021032391 +:1012000043501F22D4434DF20005C0F203052E4681 +:101210002640D422865041F20006C0F20006AD19E5 +:101220006D1E25401D43D823C5500424445040F270 +:101230000004C1F2040484504FF6E174C1F20704C3 +:10124000C4500524445047F60065C0F2800585501F +:1012500047F6E375C0F28005C5500625455048F2B3 +:101260000005C3F20005855047F6E175C3F201059C +:10127000C55007254550210781504FF6E171C5F64D +:10128000FF71C150C82201218150826808239A430E +:10129000826040F20002C0F2FA5242604FF6FC60F7 +:1012A000CFF6FF700246C3324EF28033CEF2000317 +:1012B0001A6058600020C2439A60DA604FF200035F +:1012C000C4F202031A605A60941E9C60DA601A61CC +:1012D0005A619A611A620C22521E0C4694405D6A51 +:1012E00025435D62042AF7D88A04996A914200D1A5 +:1012F00070BD40F20011C4F2000159230B601623A7 +:101300000B6088230B600B68002BF6D04CF20003B7 +:10131000C4F2000311241C6040F60004C0F2200453 +:101320005C60D8600120186118690028FCD19868B9 +:10133000401C0BD19A602120D860012018611869E7 +:101340000028FCD1F720C04301220A50FEE700002C +:1013500010B50446002041F2FF01C4F205018C42A1 +:1013600012DC40F20001C4F205018C4228D040F2A8 +:101370000011C4F205018C4227D041F20001C4F2F1 +:1013800005018C4217D039E041F20011C4F2050189 +:101390008C420BD041F20001C5F205018C420AD00B +:1013A00041F20011C5F205018C4227D140F205003F +:1013B000C5F640700DE040F20400C5F6007008E08C +:1013C00040F20200C5F6806003E040F20300C5F67B +:1013D000C0603BF05DFE02280DD140F200100443D6 +:1013E00040F20010C4F20500844208D110BC01BCD8 +:1013F00086463BF051BE800003A1085810BD10BCCA +:1014000001BC86463BF04CBE001BB70000800000CC +:101410000000000000000000000000001027000095 +:1014200000000000001BB7000020EFF30581B9B1F8 +:1014300040F65072C2F2000211684B1C10D04802F4 +:1014400040F6D873C2F20003185810600C204843CD +:1014500040F67872C2F20002131810589860481CC7 +:10146000714672467346F4468EF30088744710B591 +:10147000411EEFF305820020072919D8C2B10C22C2 +:101480004A4340F67873C2F200039A189368083210 +:1014900073B100201060480240F65072C2F20002A0 +:1014A000136840F6D874C2F2000423501160012082 +:1014B00010BC02BC8E46714672467346F4468EF3EB +:1014C00000887447B0B50020EFF3058151B340F6B2 +:1014D000D874C2F20004012040F67871C2F2000113 +:1014E00040F200220023A5180D604C608B60206044 +:1014F0000C31401C09282C46F4D1D84340F6006139 +:1015000040F6D872C2F20002505040F65070C2F25B +:101510000000036082F30B8882F30988022080F3C5 +:1015200014880120B0BC02BC8E46714672467346D8 +:10153000F4468EF30088744701460020EFF30582DD +:10154000CAB10223EFF314821A40491E072912D8A8 +:101550008AB10C224A4340F67871C2F200018A181F +:1015600011460831936833B1506880F30B880868DE +:1015700080F309880120714672467346F4468EF363 +:1015800000887447B0B501460020EFF3058222B30E +:101590000223EFF314821A40491E07291DD8E2B135 +:1015A0000C224A4340F67873C2F200039D18294684 +:1015B0000831AC688CB1EFF309846D68AC420CD390 +:1015C0009A58944209D80C6040F6D870C2F20000D4 +:1015D00080F30B8880F309880120B0BC02BC8E46E2 +:1015E000714672467346F4468EF30088744710B510 +:1015F0004EF60850CEF200000168762240F6000355 +:10160000C2F2000310C910C3521EFBD140F6000104 +:10161000C2F20001016010BC01BC864600F0DBBCD8 +:10162000F0B583B003460020002B6BD0002969D0B1 +:10163000029159690D46463D882D63D803250D401A +:101640000020461B6E41C8274F40019217430125D9 +:10165000002F009500D13D462E403025754342F6BF +:101660001C76C0F2000675191E69B600AF599D6858 +:1016700040F610666E435D683C246C431D682C196F +:10168000A419DB6845F28016C0F201067343E31823 +:10169000DB194AF68064CFF6FE741B19CE2912D1ED +:1016A000019A32B942F27F24C0F23104A342019A76 +:1016B00028D8012A0AD14DF2FF04C0F22F04A34218 +:1016C000019A1FD802E04729019A18DB1120C04374 +:1016D000471CC82900DC384602B1384640F26D1478 +:1016E0004C434A1ED517AD0F52199210A21810186C +:1016F00049F63242CFF6FF72801846439B19029892 +:101700000360009803B0F0BD10B541F6DC74C2F27E +:1017100000042068401C04D105A012A1512200F051 +:10172000A3FB00F046FA2068401C206010BDC046B4 +:10173000637269746963616C5F73656374696F6E0A +:101740005F7265656E7472616E63795F636F756EEB +:10175000746572203C2055494E5433325F4D4158D8 +:10176000000000002E5C6D6265642D6F735C706C10 +:101770006174666F726D5C6D6265645F63726974DB +:101780006963616C2E63000041F6DC70C2F20000F8 +:10179000016821B10168491E0160006800B170470D +:1017A00000F01EBA83B070B581B07546044605A836 +:1017B0000EC041F6E876C2F200063078012804D166 +:1017C00001B070BC01BC03B0004740F20010C8F289 +:1017D000FF0000212A4600F041FA06A000F0AAFC12 +:1017E0000125357005A90091204600F0F2FB28463E +:1017F00000F00CF8466174616C2052756E2D7469AE +:101800006D65206572726F720000000080B508B1CE +:1018100000F056FBFEE7F0B58FB072460D46074666 +:10182000D00709D10020C64378684168A9424BD847 +:1018300080684018A84247D9FFF766FF0995012044 +:101840000B900346029000260C9640F65470C2F2AC +:10185000000000680A90B8680169426989180D9112 +:10186000006880180E90019740F65C74C2F2000484 +:101870001C4309A8A0470496039505960696B868E8 +:10188000016942698918079180688018089003A847 +:10189000A0470746099502980B900C9640F65470A5 +:1018A000C2F2000000680A900198806801694269EC +:1018B00089180D91406880180E9009A8A047F6433A +:1018C00007B93E46FFF760FF30460FB0F0BC02BCE0 +:1018D0008E46714672467346F4468EF3008874470E +:1018E0000020714672467346F4468EF300887447B2 +:1018F0007146CA07011D02B10146086800687146B9 +:1019000072467346F4468EF30088744710B57346EA +:1019100002460020C043DB0715D153685A689C6813 +:10192000A2188A4226D91A69521E002A22DBDB68D5 +:10193000D4001B191C688C421BD9C4001B19521EF1 +:10194000002AF7DA16E013685A689C68A2188A42DF +:1019500010D91A69521E002A0CDBDB68D4001B194F +:101960001C688C4205D9C4001B19521E002AF7DAE4 +:1019700000E0586810BC02BC8E4671467246734641 +:10198000F4468EF3008874477146CA07011D02B100 +:10199000014608688068714672467346F4468EF3C5 +:1019A000008874477146CA07011D02B101460868E4 +:1019B0004068714672467346F4468EF30088744759 +:1019C00080B500F07DF8002080BC02BC8E467146D8 +:1019D00072467346F4468EF300887447F0B58FB0B4 +:1019E00074460D46E10713D1E9184F1E0021CE437E +:1019F000AF4259D344686168A94255D8A4686418B5 +:101A0000AC4251D9AF4203D0B9424DD8BC424BD9B8 +:101A1000019200930746FFF777FE09950220029096 +:101A20000B9000260C9640F65470C2F2000000683D +:101A30000A90B8680169426989180D910068801898 +:101A40000E90012040F65C74C2F20004044309A821 +:101A5000A047009804900395019805900696B868F1 +:101A60004169026952180792C0684018089003A89B +:101A7000A0470190099502980B900C9640F654707F +:101A8000C2F2000000680A90B868016942698918CA +:101A90000D91406880180E9009A8A0470198F64360 +:101AA00000B90646FFF770FE30460FB0F0BC02BC2E +:101AB0008E46714672467346F4468EF3008874472C +:101AC00042F6A841C0F2000142F69042C0F2000284 +:101AD00042F6BC43C0F200030AC00260704743F202 +:101AE000DC10C0F2000070470A460168481C11D0A3 +:101AF000880840F2C033034044F20000C5F2000001 +:101B0000184312B1012A05D10122CBB2012199401B +:101B1000FFF703B97047B0B50D4604460160481C95 +:101B200007D00021284600F099FAE8B2012181404F +:101B30006160B0BD0022C046C04670B515460E4675 +:101B40000446FFF7E8FF701C2CD02068411C0BD125 +:101B500042F68C70C0F2000042F6A471C0F200019F +:101B6000262200F081F920680121002D0A4600D1CB +:101B70002A4640F2C03340F2C0353C3586002E4044 +:101B80008008184044F60003C5F2000303439A514D +:101B90002046FFF7A9FF0021204670BC04BC9646F2 +:101BA00000F001B870BD0068421C01D000F088BA96 +:101BB0007047EFF31081EFF3108072B642F2C90064 +:101BC000C2F20000027802B17047012213468B4333 +:101BD00041F6D871C2F200010B700270704700002C +:101BE00080B50120EFF31081014204D109A010A1BA +:101BF000352200F039F942F2C900C2F2000000219A +:101C0000017041F6D870C2F20000007800B162B6EF +:101C100080BDC046216172655F696E7465727275C0 +:101C20007074735F656E61626C65642829000000E2 +:101C30002E5C6D6265642D6F735C68616C5C6D62B7 +:101C400065645F637269746963616C5F7365637413 +:101C5000696F6E5F6170692E63000000F0B58BB034 +:101C600015460C460646002803DB40F20116C8F272 +:101C7000FF0641F6E877C2F200073878012800D164 +:101C8000FEE7FFF741FD01203870FFF77DFD41F6CB +:101C9000E070C2F2000001684A1C0260A1B942F281 +:101CA0003000C2F200000660456084600C3001A97B +:101CB0008CC98CC08CC98CC000949CC99CC0009CF1 +:101CC00041F6E877C2F2000742F29400C2F2000047 +:101CD0000660456084600C3001A91CC91CC01CC989 +:101CE0001CC03CC93CC041F6E470C2F2000001686F +:101CF00021B142F29400C2F20000884700203870FF +:101D00000BB0F0BDF0B583B0044640683821415CAB +:101D100011B93A21405C08B103B0F0BD20680068F9 +:101D2000804702942068C06980470446056875B9F9 +:101D300042F6E070C0F2000042F6E271C0F200012B +:101D40002C2200F091F844F24025C0F20F051F202C +:101D5000C1B2012632468A40954205D0401E002776 +:101D6000FF210842F4D100E007466168081F1D28E2 +:101D70000BD342F6E070C0F2000042F6E271C0F20E +:101D800000013A2200F070F8202101910299486880 +:101D90000022009202604260086840688047029911 +:101DA0004C683B2167543A22009FA754A762E76220 +:101DB0002062A56030463946019AFEF750FA411E6E +:101DC0000198021F07209040E160206144F2402208 +:101DD000C0F20F0239463B46FEF762FA28187941F5 +:101DE000401EB9412A463B46FEF772FAA061E16106 +:101DF000276367632687029C204600F002FD204689 +:101E000003B0F0BC02BC8E4600F0E2BB80B540F2ED +:101E10000000C1F20400016881F388884068012154 +:101E20008843F0B444464D4656465F46F0B401211F +:101E300088430146024603460446054606460746D1 +:101E40008046814682468346844680F300888447E4 +:101E5000F0BCA046A946B246BB46F0BC3F200006F7 +:101E600000F078FEFAE7000070B514460D4606460D +:101E7000FFF74AFC05A031462A46234600F0A8F8A1 +:101E800070BC01BC864600F01BB8C0466D6265643C +:101E9000206173736572746174696F6E2066616925 +:101EA0006C65643A2025732C2066696C653A2025A0 +:101EB000732C206C696E65202564200A00000000E8 +:101EC000F0B585B0FFF720FC03A80A21FFF732FE2A +:101ED000002640F2C03744F60005C5F2000503981D +:101EE000411C0BD1262242F68C70C0F2000042F653 +:101EF000A471C0F20001FFF7B7FF039840F2C034AD +:101F00003C3481002140800838402843012201925E +:101F10004250962000F02CFE0398411C0BD1262243 +:101F200042F68C70C0F2000042F6A471C0F20001CB +:101F3000FFF79AFF0398810021408008384028432A +:101F4000002202924250962000F012FE761C042ECF +:101F5000C5D104272E460398411C0BD1262242F6F8 +:101F60008C70C0F2000042F6A471C0F20001FFF7CD +:101F70007BFF039881002140800840F2C035284053 +:101F80003043019A425040F2901000F0F1FD039866 +:101F9000411C0BD1262242F68C70C0F2000042F6A2 +:101FA000A471C0F20001FFF75FFF03988100214098 +:101FB000800828403043029A425040F2901000F0CE +:101FC000D7FD7F1E3546C5D1029E40F2C03786E759 +:101FD000704770477047F0B581B042F2C800C2F256 +:101FE00000000178C1BB0124047040F20017C4F264 +:101FF000000759203860162038608820386038681B +:102000000028F6D00420FEF798FB2046FEF795FB4B +:1020100008252846FEF791FB02263046FEF78DFB89 +:10202000A004FEF78AFB1020FEF75EFE2046FEF7B6 +:102030005BFE2846FEF758FE3046FEF755FE402070 +:10204000FEF752FE49F20000C0F2D030FEF761FD0B +:10205000FFF7AAF80020386001B0F0BD3BF04CB8A3 +:10206000B0B50C460546401C0AD142F69170C0F24C +:10207000000043F26A11C0F200014B22FFF7F4FEA8 +:1020800068087C210140680978220240501840F21B +:102090003001C4F200014258AB001C251D400F2343 +:1020A000AB409A4322434250B0BC01BC86467046C6 +:1020B000714672467346F4468EF3008874470000FA +:1020C000B0B50D460446401C0AD142F69170C0F2EC +:1020D000000043F26A11C0F200012622FFF7C4FE9D +:1020E000A00840F2C031014044F20000C5F20000F7 +:1020F00008430022052D15D8A90001A359188F46C1 +:1021000000F00AB800F008B800F00CB800F005B80C +:1021100000F005B800F005B8B0BD012202E00222CF +:1021200000E00322E3B201219940B0BC08BC9E4606 +:10213000FEF7F3BD70B582B004460320400742F2BB +:102140009406C2F2000631680A4602404D428242BD +:1021500000D08DB2080CC3B243F21C00C0F20000E4 +:102160002A46FFF735FF4FF6CF60CFF6FF702818ED +:1021700007282CD8810001A251188F4600F00EB814 +:1021800000F00FB800F010B800F011B800F012B86D +:1021900000F013B800F014B800F015B8B16844A00E +:1021A00013E0B1683EA010E0B16839A00DE0B1685D +:1021B00032A00AE0B1682CA007E0B16821A004E0D9 +:1021C000B16824A001E0B16818A0FFF701FF204624 +:1021D000FFF7FEFE716843F2CF00C0F20000FFF788 +:1021E000F7FEB16843F2BC00C0F20000FFF7F0FE5A +:1021F00033460C330ECBB069F4696D4611C543F21A +:102200006D00C0F20000FFF7E3FE316843F2DF002B +:10221000C0F20000FFF7DCFE43F20200C0F2000053 +:1022200002B070BC02BC8E46FFF7D2BE4D65737320 +:1022300061676551756575653A20307825582C20A1 +:102240000000000054696D65723A20307825582CE2 +:10225000200000004576656E74466C6167733A2015 +:10226000307825582C2000004D656D6F7279506FC5 +:102270006F6C3A20307825582C20000053656D6132 +:1022800070686F72653A20307825582C2000000065 +:102290004D757465783A20307825582C2000000060 +:1022A0005468726561643A20307825582C2000000B +:1022B0004B65726E656C204572726F723A20307891 +:1022C00025582C200000000080B540F20100C7F224 +:1022D00080203AF0F1FE80BC01BC86467046714613 +:1022E00072467346F4468EF30088744710B540F288 +:1022F0000820C4F2000000680221084205D140F223 +:102300000100C7F280203AF0DBFE41F20000C4F287 +:10231000040000680121084207D100242046FEF78E +:1023200000FE204621463AF0FBFE10BC01BC86466A +:102330007046714672467346F4468EF300887447C1 +:1023400080B540F20820C4F2000000680221084273 +:1023500005D140F20100C7F280203AF0B1FE41F20F +:102360000000C4F2040001680120084080BC02BCE7 +:102370008E46714672467346F4468EF30088744763 +:10238000F0B597B040F20820C4F2000000680221C6 +:10239000084205D140F20100C7F280203AF090FED9 +:1023A0000320C04341F20405C4F204052858012764 +:1023B000384201D13AF0A8FE3E043C0742F2D00078 +:1023C000C2F200000178D9BB01940770642011901B +:1023D000002410940F97062012900E940D940C94E4 +:1023E0000CA842F2CC01C2F200012246FFF718F914 +:1023F0000028214668D041F20404C5F20404FDF728 +:102400002BFF0199084203D020683042FCD002E043 +:1024100028683042FCD0FEF794FCFDF71DFF0199BF +:10242000084203D020683042FCD002E028683042E5 +:10243000FCD0E86B42F2D401C2F200010860019CBA +:10244000FDF70AFF204207D041F20400C5F2040064 +:1024500001683142FCD002E028683042FCD003A879 +:10246000FEF796FC05980F900698129007980E902C +:102470004FF69401CFF6FF71039A51181191049908 +:10248000491E10910A9921B90B99022901D10C30EA +:102490000E9008980D9009980C900CA802A90024A1 +:1024A0002246FFF7BDF8002821460DD042F2D400A5 +:1024B000C2F2000000680299081842F2CC01C2F290 +:1024C00000010968441A0021204617B0F0BC04BC82 +:1024D000964672467346F4468EF300887447F0B50C +:1024E00081B0054640F20820C4F2000000680221D5 +:1024F000084205D140F20100C7F280203AF0E0FD29 +:1025000003200090C04341F20407C4F20407385886 +:102510000124204201D13AF0F7FD42F2D400C2F288 +:10252000000005602504240741F20406C5F20406F4 +:10253000FDF792FE204203D030682842FCD002E032 +:1025400038682842FCD0FEF7FCFBFDF785FE2042F0 +:1025500003D030682842FCD002E038682842FCD022 +:1025600042F2D400C2F200000068F863FDF774FE86 +:10257000204203D030682842FCD002E0386828426C +:10258000FCD042F64840C0F20000FEF7EFFC40F2FB +:102590000820C4F20000416948F20002009801429C +:1025A00001D042F2107244F24021C0F20F01B1FB9F +:1025B000F2F1484300F0E1FA01B0F0BC01BC8646FC +:1025C0007046714672467346F4468EF3008874472F +:1025D000F0B583B0044646683A20305C10B9392023 +:1025E000305C08B103B0F0BD204600F00AF9626823 +:1025F0005168C1B3156B0B68012700200195AB42F0 +:102600003D4600D905460292526B4968914200D975 +:102610000746914200D03D46002D7CD1002701980D +:102620001B1A01977F41029880690125009383421C +:10263000284600D801987F1E9141029AD2699142A2 +:1026400000D8019D914200D02846029A15690028C1 +:102650003ED11346926844F24020C0F20F008242FD +:102660000DD1009830E0306AF168326910180840E6 +:102670002168096903B0F0BC04BC964608473B20BA +:102680001B5C44F23F27C0F20F075BB100981A466B +:10269000FDF7E5FD0023C019594144F24022C0F284 +:1026A0000F020FE0002700983B46FDF7F9FD44F2CA +:1026B0003F22C0F20F028018794144F24022C0F25A +:1026C0000F023B46FDF704FE854200D30546029A01 +:1026D000106A4019D5680540306A854208D111A0BA +:1026E00042F6E271C0F2000140F20712FFF7BCFBB4 +:1026F0002068016928468847206840688047316A19 +:102700008D4202D9A84203D305E0A84200D269E76E +:10271000884200D366E72068406903B0F0BC02BC81 +:102720008E4600476D617463685F7469636B202136 +:102730003D2071756575652D3E7469636B5F6C61D5 +:1027400073745F7265616400F0B581B00546FEF791 +:10275000DBFF2868C068804768683A21415C79BB24 +:102760003921012747544168393021B30097284661 +:1027700000F047F82C466868026B41680D6800233A +:1027800095423A4600D81A46466B4D68B54200D885 +:102790001F46B54200D03A46002A25460AD1CA68EB +:1027A000426003681BB18868984768684268002ADD +:1027B000009FDCD13930002101702846FFF708FF67 +:1027C00001B0F0BC01BC8646FEF7DEBF80B500F06C +:1027D00001F880BD10B50446FFF794FAFEF794FFA8 +:1027E000204600F00EF8FEF7CFFF6168086B496BDA +:1027F00010BD40F20800C4F205000121016000F0A4 +:1028000071B9F0B585B0044646683A20305C0028BE +:1028100000D07EE02068406880476168096A88428D +:1028200077D0316A3062401AB168F46804400025FC +:1028300044F24020C0F20F00814264D0049144F27F +:102840004022C0F20F020027204639463B46FDF7E2 +:1028500027FD3B22B55C002D039026D001970F4643 +:102860002A46FDF70CFD044602912A46FDF7F7FCC7 +:10287000039A101A019B1A465A41521E8F41B16A9F +:102880000918B162F06A7841F0620122049DA94200 +:102890001F4600D33A4600B13A4633462833002A51 +:1028A000029D30D10022049F24E000250F46049AA7 +:1028B0002B46FDF70DFD04460291049A2B46FDF7C9 +:1028C000EFFC039A101A2A466A41521E8F41B16AE0 +:1028D0004118B162F06A7841049FF0620122B94266 +:1028E00000D32A4600B12A4633462833002A029DE7 +:1028F00009D10022C91B196011465141491E90415E +:102900005860641C5541306B00193063706B68412E +:10291000706305B0F0BD40F20800C4F2050001216B +:10292000016070474EF28410CEF200000121016078 +:10293000BFF34F8FBFF36F8F70474EF20420CEF27C +:102940000000012101604EF20410CEF2000001608F +:10295000704780B54EF28410CEF200000121016074 +:10296000BFF34F8FBFF36F8F40F20200C5F6806058 +:102970003AF0A2FB42F2D800C2F20000002101802E +:1029800080BD43F20420C0F200007047F0B583B070 +:1029900042F2D800C2F20000018851B14EF2841018 +:1029A000CEF2000001210160BFF34F8FBFF36F8FA4 +:1029B00064E00126068040F20200C0F200403AF0D6 +:1029C00093FB40F20204C5F680640022204640F2E8 +:1029D00000213AF081FB20463AF072FB40F20004FD +:1029E000C4F205042046FEF7B3FC44F24025C0F2D1 +:1029F0000F05B0FBF5F14F1E802F0BD3029020A0E6 +:102A0000019143F2A111C0F200016922FFF72CFAF3 +:102A1000019902984D43401B07D028A043F2A11111 +:102A2000C0F200016A22FFF71FFA0320C006074325 +:102A300027604FF6FF70C0F2FF0060604EF608504E +:102A4000CEF200000068C02142F2F372C0F2000230 +:102A500042504EF28410CEF200000660BFF34F8F5A +:102A6000BFF36F8F7007216801432160B0072168B1 +:102A700001432160700621680142FBD003B0F0BD24 +:102A8000287072657363616C655F74696D6572202F +:102A9000213D202875696E7433325F7429202D31F1 +:102AA00029202626207072657363616C655F7469E6 +:102AB0006D6572203C3D20313237000028636C6B1D +:102AC0005F74696D65722025204E555F544D5243E9 +:102AD0004C4B5F5045525F53454329203D3D2030CC +:102AE0000000000040F65870C2F20000016821B1F9 +:102AF00043F2DC10C0F200000847704780B542F294 +:102B0000D800C2F20000008808B9FFF73FFF40F28A +:102B10000C00C4F20500006880BD40F20402C4F25B +:102B20000502012151604EF28423CEF200031960A8 +:102B30000223022800D818464FF6FF73C0F2FF03A5 +:102B4000984200D3184610604EF20410CEF20000F6 +:102B50000160704780B542F20041C4F6741100F084 +:102B60001BF8FDF739FC80BC02BC8E4600F005B8AE +:102B700040F2E8314843C046C04670B50446FEF70F +:102B8000AEFF0546FFF722FE06462846FFF71EFE6B +:102B9000801BA042F9D370BD70B5420064414B0068 +:102BA0005C41120E39D01B0E38D0FF2A3CD0FF2BCF +:102BB0003AD0D2187F3A40024902400A490A4518E1 +:102BC000ED0106004E43000A090A48430104731A46 +:102BD0004019190C4318990F04D05B0801214907CB +:102BE0005B1A521CD80904D3401CF50301D19D0681 +:102BF00007D0FF2A08D2D50506D0E40720434019A4 +:102C000070BD0125A843F4E7002A01DCE00770BD90 +:102C10002402FF202043C00570BD1B0EFF2A03D0F5 +:102C2000FF2B01D0E00770BDFF2636064500B542F8 +:102C300006D84D00B54203D8D218FF2A00D0E7E7E6 +:102C4000004870BD0000C07FD007000001000000F8 +:102C5000010000000600000000000000000000006D +:102C60000000000001000000000000000000000063 +:102C700004000000080000000C000000000000003C +:102C8000040000000800000010000000010202041F +:102C9000D7000000890100006F0200001903000046 +:102CA00064050000E40900200400000000000000AA +:102CB000000004007C2F0000010000000400000060 +:102CC0000000041000000400842F00000100000038 +:102CD00004000000903C800200020000060000009A +:102CE00006FF430700200000FFFFFFFFFFFFFFFF7D +:102CF000004000000300000003000000000001008D +:102D00001D0000000100000000000001070000009D +:102D100007000000000002000C0000000C00000092 +:102D200000000400FFFFFFFF0100807200000000B0 +:102D30001C0000041CFE0340080000000700000403 +:102D40000700004020000000FFFFFFFFFFFFFFFF24 +:102D5000400000000C0000080C0000808000000013 +:102D60001D0000041D000077000100001A0000048F +:102D70009A3C804200200000040000040400005F30 +:102D800000000200050000040500405F0000020092 +:102D90001000000810000080000000011100000871 +:102DA00011000080000000021200000812000080E4 +:102DB0000000000413000008130000800000000859 +:102DC0000D0000040D004066010000000E0000042C +:102DD0000E006066020000000F0000040E00606636 +:102DE00004000000060000080600C0A6080000005D +:102DF000FFFFFFFFFFFFFFFF1000000007000008BC +:102E00000700E0A62000000010000004103D8057DD +:102E10000000010011000004913DA05700000200D5 +:102E200012000004123C8C77000004001300000420 +:102E3000933CAC770000080014000004143DCC77EC +:102E40000000100015000004953DEC770000200004 +:102E50000800000408000040010000000900000410 +:102E600009000040020000000A0000040A000040BF +:102E7000040000000000000800FC07B6000001008C +:102E80000100000801FD27B6000002000200000852 +:102E900002FE47B6000004001800000418000040BD +:102EA000010000001600000816000080000001006C +:102EB0001700000817000080000002001A00000838 +:102EC0001A000080000010001B0000081B0000809A +:102ED0000000200017000004177F3452000080001B +:102EE000FFFFFFFFFFFFFFFF000000011F000004C6 +:102EF00019000080000000021B0000049B3C80427F +:102F00000100000008000008080000800000010027 +:102F10000900000809000080000002000000000015 +:102F200080DE280080C84D0000A7760000349E0097 +:102F30008012C700809FEE00007E1701805C400178 +:102F400080E9670100C890010055B8010000000049 +:102F500080DE2800001A4F0080F8770080859F00EF +:102F60000064C80000F1EF0080CF180100AE4101FD +:102F7000003B69018019920180A6B90100000000A0 +:102F80000008000000000410000800006F626A2DB5 +:102F90003E70696E20213D202850696E4E616D653E +:102FA000294E43002E5C6D6265642D6F735C746105 +:102FB00072676574735C5441524745545F4E555671 +:102FC0004F544F4E5C5441524745545F4D32333558 +:102FD000312F6770696F5F6F626A6563742E680076 +:102FE00030002E5C6D6265642D6F735C68616C5C93 +:102FF0006D6265645F7469636B65725F6170692E91 +:1030000063000A2D2D204D6265644F532045727276 +:103010006F7220496E666F202D2D0A000A0A2B2B35 +:10302000204D6265644F53204572726F7220496E65 +:10303000666F202B2B0A4572726F72205374617475 +:1030400075733A203078255820436F64653A2025FF +:1030500064204D6F64756C653A2025640A45727270 +:103060006F72204D6573736167653A20000A43757E +:103070007272656E74205468726561643A204964A6 +:103080003A203078255820456E7472793A2030788D +:10309000255820537461636B53697A653A20307800 +:1030A000255820537461636B4D656D3A2030782547 +:1030B000582053503A203078255820000A45727223 +:1030C0006F722056616C75653A2030782558000A79 +:1030D0004C6F636174696F6E3A2030782558000A2E +:1030E000466F72206D6F726520696E666F2C207658 +:1030F000697369743A2068747470733A2F2F61721F +:103100006D6D6265642E6769746875622E696F2FD4 +:103110006D6265646F732D6572726F722F3F657299 +:10312000726F723D307825303858004E6F6E2D73B7 +:10313000656375726520646F6D61696E2074726974 +:10314000657320746F20636F6E74726F6C2073658B +:1031500063757265206F7220756E646566696E6551 +:1031600064206D6F64756C652E002E5C6D62656405 +:103170002D6F735C746172676574735C5441524760 +:1031800045545F4E55564F544F4E5C54415247453F +:10319000545F4D323335315C70696E6D61702E63F2 +:1031A000002E5C6D6265642D6F735C74617267657F +:1031B00074735C5441524745545F4E55564F544FBB +:1031C0004E5C5441524745545F4D323335315C7546 +:1031D000735F7469636B65722E630000E4310000F5 +:1031E000F01F00208D290000FD2A00002529000085 +:1031F000172900001B2B00003B2900005329000069 +:103200008329000040420F00180000002C3200000B +:10321000E0090020980500002604000008350000A1 +:10322000780F0020641100001C020000101D300007 +:10323000000085B00A460346039002A8017001927F +:103240000093FFE74CF2C000C4F21B100B68012191 +:10325000084201D0FFE7F514320014300C01684039 +:1032600022114301604CF20C10100B22210160036B +:10327000984CF204010E501501086002A800780075 +:103280002808D1FFE70020C0434CF208181309E0DA +:103290000C3132200B4AF60321C0F2550101606A5D +:1032A000421056114600051CBFF36F8F7C100400BE +:1032B000684090120B14E18E10080120049002E087 +:1032C0000006201DFFE7049805B07047B0B587B031 +:1032D00013460C46054605900491039240F20010F7 +:1032E0007E12596A12166E1288B841E010080293D5 +:1032F0000194009503B210070120069038E02A429D +:10330000205C3204EA500440F2041021F83006FF39 +:10331000E740F2502024040068101EC6D11E56015A +:103320001E321CF8120A646310425CE30AE0B81211 +:10333000007204111EFFE7069807B0B0BD82B0010D +:10334000460190009180400401229162452811D0ED +:103350001004084602F2072C81B0BA16260615B8EA +:10336000714696C8AE054898360098160098100425 +:10337000009801A6100480B584E8100A0290029813 +:103380004FF6FF72CE044310400E70040002CF0EC1 +:1033900014100F2212051040012252059042019193 +:1033A0000B64170298C2101501CFF6E071401801A6 +:1033B00021FFF7A4FE039005E00298000C129E0C7A +:1033C000380CFFE7039804B080BD80B586D048096B +:1033D0000490039100200290D22809029803998852 +:1033E000420FD21E101202994A1C029289004058C4 +:1033F000FFF7B8FF002803B818080120059003E084 +:10340000EBB416059010040598064A5804B0B58828 +:103410004220120690059104920598C01C03218851 +:1034200043059006BC1271BC0C0C2C710840069030 +:103430000393029401953603162170216814040049 +:10344000283F369E064003040752049800F03CF8DB +:103450008A100B07900CE00698001D06906410047B +:103460001D04907E1C051F0590BCA8031A07841834 +:10347000040798088456839C164222700400780141 +:103480000A90070002019A101810D2041042062078 +:103490003C0601980091037E0305163C05322E760A +:1034A000002E36532E857E85386D5E0429CA05466A +:1034B000341D98037F901DB80428110068049900FA +:1034C000900846FFF76CFF009981423821220512CF +:1034D0005632A81A655642000110056CDC02FF0145 +:1034E00021080021004927000030B54D4620B44591 +:1034F0006903699946C368826841680068A84720E3 +:08350000BCA94630BD0000002B :020000040003F7 -:10D000007FE97FE9C4F710B97FE97FE9C4F726B962 -:10D010007FE97FE9C4F744B97FE97FE9C4F770B9D4 -:10D020007FE97FE9C4F790B97FE97FE9C4F7C4BA23 -:10D030007FE97FE9C4F71CBB7FE97FE9C4F720BB28 -:10D040007FE97FE9C4F72ABB7FE97FE9C4F764BBC6 -:10D050007FE97FE9C4F76EBB7FE97FE9C4F778BB5E -:10D060007FE97FE9C4F782BB7FE97FE9C3F736BB7D -:10D070007FE97FE9C3F7B2BB7FE97FE9C3F7BEBBB6 -:10D080007FE97FE9C3F7C8BB7FE97FE9C3F7D4BB7A -:10D090007FE97FE9C3F7ECBB7FE97FE9C3F72EBCEB -:10D0A0007FE97FE9C3F73EBC7FE97FE9C3F754BC62 -:10D0B0007FE97FE9C3F74ABF7FE97FE9C3F7F2B9A8 -:10D0C0007FE97FE9C3F724BA7FE97FE9C3F73EBD73 -:10D0D0007FE97FE9C3F72EBF7FE97FE9C3F74EBF42 -:10D0E0007FE97FE9C3F774BF7FE97FE9C4F768BED2 -:10D0F0007FE97FE9C4F782BF7FE97FE9C4F78EBF8C -:10D100007FE97FE9C4F7ACBF7FE97FE9C4F7C2BF1D -:10D110007FE97FE9C5F752B87FE97FE9C4F752BCE0 -:10D120007FE97FE9C4F768BC000000000000000050 +:10D000007FE97FE9C4F710BA7FE97FE9C4F72FBA57 +:10D010007FE97FE9C4F756BA7FE97FE9C4F78CBAA4 +:10D020007FE97FE9C4F7AEBA7FE97FE9C4F7F3BBD4 +:10D030007FE97FE9C4F754BC7FE97FE9C4F758BCB6 +:10D040007FE97FE9C4F762BC7FE97FE9C4F79CBC54 +:10D050007FE97FE9C4F7A6BC7FE97FE9C4F7B0BCEC +:10D060007FE97FE9C4F7BABC7FE97FE9C3F76EBB0C +:10D070007FE97FE9C3F7F6BB7FE97FE9C3F704BC2B +:10D080007FE97FE9C3F714BC7FE97FE9C3F720BCE0 +:10D090007FE97FE9C3F73CBC7FE97FE9C3F78FBC39 +:10D0A0007FE97FE9C3F7A5BC7FE97FE9C3F7BCBC93 +:10D0B0007FE97FE9C4F721B87FE97FE9C3F704BAC4 +:10D0C0007FE97FE9C3F73DBA7FE97FE9C3F7F3BCA6 +:10D0D0007FE97FE9C3F70FBD7FE97FE9C3F7D2BDE1 +:10D0E0007FE97FE9C3F7FBBF7FE97FE9C4F71CB89D +:10D0F0007FE97FE9C4F743B87FE97FE9C4F7B0BFB0 +:10D100007FE97FE9C5F7E0B87FE97FE9C5F7EEB8C9 +:10D110007FE97FE9C5F714B97FE97FE9C5F730B941 +:10D120007FE97FE9C5F7DBB90000000000000000DF :10D1300000000000000000000000000000000000EF :10D14000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF :10D15000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF
Binary file targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/TARGET_M23_NS/cmse_lib.o has changed
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct Thu Nov 08 11:46:34 2018 +0000
@@ -10,7 +10,7 @@
* Secure: 32KiB
* Non-secure: 64KiB
*/
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START 0x10040000
@@ -64,14 +64,14 @@
/* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE))
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
#define NU_INITIAL_STACK_SIZE 0x800
#else
#define NU_INITIAL_STACK_SIZE 0x800
#endif
#endif
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
LR_IROM1 MBED_APP_START
{
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct Thu Nov 08 11:46:34 2018 +0000
@@ -10,7 +10,7 @@
* Secure: 32KiB
* Non-secure: 64KiB
*/
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START 0x10040000
@@ -64,14 +64,14 @@
/* Initial/ISR stack size */
#if (! defined(NU_INITIAL_STACK_SIZE))
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
#define NU_INITIAL_STACK_SIZE 0x800
#else
#define NU_INITIAL_STACK_SIZE 0x800
#endif
#endif
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
LR_IROM1 MBED_APP_START
{
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld Thu Nov 08 11:46:34 2018 +0000
@@ -12,7 +12,7 @@
* Secure: 32KiB
* Non-secure: 64KiB
*/
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
#ifndef MBED_APP_START
#define MBED_APP_START 0x10040000
@@ -50,7 +50,7 @@
#endif
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
StackSize = 0x800;
#else
StackSize = 0x800;
@@ -71,7 +71,7 @@
#endif
-#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#if defined(DOMAIN_NS) && DOMAIN_NS
MEMORY
{
@@ -132,7 +132,7 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
/* ensure that uvisor bss is at the beginning of memory */
@@ -164,7 +164,7 @@
.text :
{
/* uVisor code and data */
- . = ALIGN(4);
+ . = ALIGN(8);
__uvisor_main_start = .;
*(.uvisor.main)
__uvisor_main_end = .;
@@ -192,7 +192,7 @@
KEEP(*(.eh_frame*))
} > FLASH
-#if (! defined(__DOMAIN_NS)) || (! __DOMAIN_NS)
+#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS)
/* Veneer$$CMSE : */
.gnu.sgstubs :
{
@@ -253,20 +253,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf Thu Nov 08 11:46:34 2018 +0000
@@ -2,7 +2,7 @@
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-if (isdefinedsymbol(__DOMAIN_NS)) {
+if (isdefinedsymbol(DOMAIN_NS)) {
if (! isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0x10040000;
@@ -85,7 +85,7 @@
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-if (! isdefinedsymbol(__DOMAIN_NS)) {
+if (! isdefinedsymbol(DOMAIN_NS)) {
place at address mem:__ICFEDIT_region_NSCROM_start__ { readonly section Veneer$$CMSE };
}
place at start of IRAM_region { block CSTACK };
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/stddriver_secure.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/stddriver_secure.c Thu Nov 08 11:46:34 2018 +0000
@@ -197,6 +197,18 @@
SYS_UnlockReg();
}
+__NONSECURE_ENTRY
+void CLK_Idle_S(void)
+{
+ CLK_Idle();
+}
+
+__NONSECURE_ENTRY
+void CLK_PowerDown_S(void)
+{
+ CLK_PowerDown();
+}
+
static bool check_mod_ns(int modclass, uint32_t modidx)
{
const nu_modidx_ns_t *modidx_ns = modidx_ns_tab;
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/stddriver_secure.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/stddriver_secure.h Thu Nov 08 11:46:34 2018 +0000 @@ -71,6 +71,14 @@ __NONSECURE_ENTRY void SYS_UnlockReg_S(void); +/* Secure CLK_Idle */ +__NONSECURE_ENTRY +void CLK_Idle_S(void); + +/* Secure CLK_PowerDown */ +__NONSECURE_ENTRY +void CLK_PowerDown_S(void); + #ifdef __cplusplus } #endif
--- a/targets/TARGET_NUVOTON/TARGET_M2351/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -51,6 +51,9 @@
}
obj->mask = gpio_set(pin);
+ /* Default mode/direction */
+ obj->mode = PullUp;
+ obj->direction = PIN_INPUT;
}
void gpio_mode(gpio_t *obj, PinMode mode)
@@ -58,8 +61,45 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- pin_mode(obj->pin, mode);
+
+ switch (mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ obj->mode = QuasiBidirectional;
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode
+ * in the gpio_mode call here. */
+ if (mode == InputOnly) {
+ obj->direction = PIN_INPUT;
+ obj->mode = InputOnly;
+ } else {
+ obj->direction = PIN_OUTPUT;
+ obj->mode = PushPullOutput;
+ }
+ break;
+
+ default:
+ /* Allow for configuring other I/O modes directly */
+ obj->mode = mode;
+ break;
+ }
+
+ pin_mode(obj->pin, obj->mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
@@ -67,25 +107,36 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
+
+ obj->direction = direction;
+
+ switch (obj->mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
break;
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor direction
+ * in the gpio_dir call here. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
default:
- return;
+ break;
}
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ pin_mode(obj->pin, obj->mode);
}
--- a/targets/TARGET_NUVOTON/TARGET_M2351/gpio_object.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -29,8 +29,10 @@
#endif
typedef struct {
- PinName pin;
- uint32_t mask;
+ PinName pin;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
--- a/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,9 +19,9 @@
#if DEVICE_LPTICKER
#include "sleep_api.h"
-#include "mbed_wait_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
+#include "nu_timer.h"
#include "nu_miscutil.h"
#include "partition_M2351.h"
@@ -101,8 +101,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
lp_ticker_disable_interrupt();
- lp_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -137,10 +135,10 @@
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default.
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->CMP = cmp_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
// Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
@@ -148,13 +146,13 @@
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_EnableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
@@ -162,23 +160,7 @@
void lp_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
- /* Disable wakeup */
- TIMER_DisableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock
@@ -203,6 +185,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ lp_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_M2351/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -41,31 +41,40 @@
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
uint32_t mode_intern = GPIO_MODE_INPUT;
-
+
switch (mode) {
- case PullUp:
+ case InputOnly:
mode_intern = GPIO_MODE_INPUT;
break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
+
+ case PushPullOutput:
mode_intern = GPIO_MODE_OUTPUT;
break;
-
+
case OpenDrain:
mode_intern = GPIO_MODE_OPEN_DRAIN;
break;
-
- case Quasi:
+
+ case QuasiBidirectional:
mode_intern = GPIO_MODE_QUASI;
break;
+
+ default:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We expect upper layer would have translated input pull mode/direction
+ * to I/O mode */
+ return;
}
-
+
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ /* Invalid combinations of PinMode/PinDirection
+ *
+ * We assume developer would avoid the following combinations of PinMode/PinDirection
+ * which are invalid:
+ * 1. InputOnly/PIN_OUTPUT
+ * 2. PushPullOutput/PIN_INPUT
+ */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
--- a/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -25,6 +25,7 @@
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include <string.h>
+#include <stdbool.h>
#if DEVICE_SERIAL_ASYNCH
#include "dma_api.h"
@@ -87,6 +88,8 @@
static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
#endif
+bool serial_can_deep_sleep(void);
+
static struct nu_uart_var uart0_var = {
.ref_cnt = 0,
.obj = NULL,
@@ -1171,4 +1174,23 @@
}
#endif // #if DEVICE_SERIAL_ASYNCH
+
+bool serial_can_deep_sleep(void)
+{
+ bool sleep_allowed = 1;
+ const struct nu_modinit_s *modinit = uart_modinit_tab;
+ while (modinit->var != NULL) {
+ struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ if (uart_var->ref_cnt > 0) {
+ if (!UART_IS_TX_EMPTY(uart_base)) {
+ sleep_allowed = 0;
+ break;
+ }
+ }
+ modinit++;
+ }
+ return sleep_allowed;
+}
+
#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_M2351/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,30 +22,48 @@
#include "device.h"
#include "objects.h"
#include "PeripheralPins.h"
+#include <stdbool.h>
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if DEVICE_SERIAL
+bool serial_can_deep_sleep(void);
+#endif
/**
* Enter idle mode, in which just CPU is halted.
*/
-__NONSECURE_ENTRY
void hal_sleep(void)
{
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SYS_UnlockReg();
CLK_Idle();
SYS_LockReg();
+#else
+ SYS_UnlockReg_S();
+ CLK_Idle_S();
+ SYS_LockReg_S();
+#endif
}
/**
* Enter power-down mode, in which HXT/HIRC are halted.
*/
-__NONSECURE_ENTRY
void hal_deepsleep(void)
{
+#if DEVICE_SERIAL
+ if (!serial_can_deep_sleep()) {
+ return;
+ }
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
+#else
+ SYS_UnlockReg_S();
+ CLK_PowerDown_S();
+ SYS_LockReg_S();
+#endif
}
#endif
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -75,8 +75,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
- us_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -125,16 +123,7 @@
void us_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock
@@ -159,6 +148,10 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ us_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_M451/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,15 +55,19 @@
} PinDirection;
typedef enum {
+ /* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
- PushPull,
+ /* I/O mode */
+ InputOnly,
+ PushPullOutput,
OpenDrain,
- Quasi,
+ QuasiBidirectional,
- PullDefault = PullUp,
+ /* Default input pull mode */
+ PullDefault = PullUp
} PinMode;
typedef enum {
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld Thu Nov 08 11:46:34 2018 +0000
@@ -59,42 +59,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
.text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
-
*(.text*)
KEEP(*(.init))
@@ -165,20 +135,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -191,39 +161,6 @@
} >RAM_INTERN AT>FLASH
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
.uninitialized (NOLOAD):
{
@@ -255,9 +192,4 @@
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c Thu Nov 08 11:46:34 2018 +0000 @@ -60,7 +60,6 @@ extern uint32_t __bss_start__; extern uint32_t __bss_end__; -extern void uvisor_init(void); #if defined(TOOLCHAIN_GCC_ARM) extern void _start(void); #else
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -51,6 +51,9 @@
}
obj->mask = gpio_set(pin);
+ /* Default mode/direction */
+ obj->mode = PullUp;
+ obj->direction = PIN_INPUT;
}
void gpio_mode(gpio_t *obj, PinMode mode)
@@ -58,8 +61,45 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- pin_mode(obj->pin, mode);
+
+ switch (mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ obj->mode = QuasiBidirectional;
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode
+ * in the gpio_mode call here. */
+ if (mode == InputOnly) {
+ obj->direction = PIN_INPUT;
+ obj->mode = InputOnly;
+ } else {
+ obj->direction = PIN_OUTPUT;
+ obj->mode = PushPullOutput;
+ }
+ break;
+
+ default:
+ /* Allow for configuring other I/O modes directly */
+ obj->mode = mode;
+ break;
+ }
+
+ pin_mode(obj->pin, obj->mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
@@ -67,25 +107,36 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
+
+ obj->direction = direction;
+
+ switch (obj->mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
break;
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor direction
+ * in the gpio_dir call here. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
default:
- return;
+ break;
}
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ pin_mode(obj->pin, obj->mode);
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,8 +28,10 @@
#endif
typedef struct {
- PinName pin;
- uint32_t mask;
+ PinName pin;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,9 +19,9 @@
#if DEVICE_LPTICKER
#include "sleep_api.h"
-#include "mbed_wait_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
+#include "nu_timer.h"
#include "nu_miscutil.h"
/* Micro seconds per second */
@@ -76,8 +76,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
lp_ticker_disable_interrupt();
- lp_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -103,10 +101,10 @@
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->CMP = cmp_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
// Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
@@ -114,13 +112,13 @@
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_EnableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
@@ -128,23 +126,7 @@
void lp_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
- /* Disable wakeup */
- TIMER_DisableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -166,6 +148,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ lp_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -55,29 +55,38 @@
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
uint32_t mode_intern = GPIO_MODE_INPUT;
-
+
switch (mode) {
- case PullUp:
+ case InputOnly:
mode_intern = GPIO_MODE_INPUT;
break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
+
+ case PushPullOutput:
mode_intern = GPIO_MODE_OUTPUT;
break;
-
+
case OpenDrain:
mode_intern = GPIO_MODE_OPEN_DRAIN;
break;
-
- case Quasi:
+
+ case QuasiBidirectional:
mode_intern = GPIO_MODE_QUASI;
break;
+
+ default:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We expect upper layer would have translated input pull mode/direction
+ * to I/O mode */
+ return;
}
-
+
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ /* Invalid combinations of PinMode/PinDirection
+ *
+ * We assume developer would avoid the following combinations of PinMode/PinDirection
+ * which are invalid:
+ * 1. InputOnly/PIN_OUTPUT
+ * 2. PushPullOutput/PIN_INPUT
+ */
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -25,6 +25,7 @@
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include <string.h>
+#include <stdbool.h>
#if DEVICE_SERIAL_ASYNCH
#include "dma_api.h"
@@ -83,6 +84,8 @@
static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
#endif
+bool serial_can_deep_sleep(void);
+
static struct nu_uart_var uart0_var = {
.ref_cnt = 0,
.obj = NULL,
@@ -1088,4 +1091,23 @@
}
#endif // #if DEVICE_SERIAL_ASYNCH
+
+bool serial_can_deep_sleep(void)
+{
+ bool sleep_allowed = 1;
+ const struct nu_modinit_s *modinit = uart_modinit_tab;
+ while (modinit->var != NULL) {
+ struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ if (uart_var->ref_cnt > 0) {
+ if (!UART_IS_TX_EMPTY(uart_base)) {
+ sleep_allowed = 0;
+ break;
+ }
+ }
+ modinit++;
+ }
+ return sleep_allowed;
+}
+
#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,6 +22,11 @@
#include "device.h"
#include "objects.h"
#include "PeripheralPins.h"
+#include <stdbool.h>
+
+#if DEVICE_SERIAL
+bool serial_can_deep_sleep(void);
+#endif
/**
* Enter idle mode, in which just CPU is halted.
@@ -38,6 +43,12 @@
*/
void hal_deepsleep(void)
{
+#if DEVICE_SERIAL
+ if (!serial_can_deep_sleep()) {
+ return;
+ }
+#endif
+
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -52,8 +52,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
- us_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -93,16 +91,7 @@
void us_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -124,6 +113,10 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ us_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_M480/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,15 +55,19 @@
} PinDirection;
typedef enum {
+ /* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
- PushPull,
+ /* I/O mode */
+ InputOnly,
+ PushPullOutput,
OpenDrain,
- Quasi,
+ QuasiBidirectional,
- PullDefault = PullUp,
+ /* Default input pull mode */
+ PullDefault = PullUp
} PinMode;
typedef enum {
@@ -125,8 +129,14 @@
LED3 = LED_GREEN,
LED4 = LED1, // No real LED. Just for passing ATS.
// Button naming
+#if TARGET_NUMAKER_PFM_M487
SW2 = PG_15,
SW3 = PF_11,
+#elif TARGET_NUMAKER_IOT_M487
+ SW2 = PF_11,
+ SW3 = PG_5,
+#endif
+
} PinName;
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct Thu Nov 08 11:46:34 2018 +0000
@@ -18,9 +18,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct Thu Nov 08 11:46:34 2018 +0000
@@ -18,9 +18,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld Thu Nov 08 11:46:34 2018 +0000
@@ -61,59 +61,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* Note: Ensure that uVisor bss is at the beginning of SRAM to match vmpu_arch_init_hw of
- uvisor/core/system/src/mpu/vmpu_armv7m.c */
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x0;
- __UVISOR_BSS_START = ORIGIN(RAM_INTERN) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_BSS_START (NOLOAD):
+
+ .text :
{
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* uVisor main BSS section */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* Secure boxes BSS section */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > RAM_INTERN
-
- /* Heap space for the page allocator */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN((1 << LOG2CEIL(LENGTH(RAM_INTERN))) / 8);
- __uvisor_page_end = .;
- } > RAM_INTERN
-
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_TEXT_OFFSET = 0x400;
- __UVISOR_TEXT_START = ORIGIN(VECTORS) + __UVISOR_TEXT_OFFSET;
- .text __UVISOR_TEXT_START :
- {
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -185,20 +138,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -211,37 +164,6 @@
} >RAM_INTERN AT>FLASH
- /* uVisor configuration section
- * This section must be located after all other flash regions. */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uVisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* Pointers to the uVisor secure boxes configuration tables */
- /* Note: Do not add any further alignment here, as uVisor will need to
- have access to the exact list of pointers. */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to
- allow discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > FLASH
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
@@ -267,24 +189,15 @@
.heap (NOLOAD):
{
. = ALIGN(8);
- __uvisor_heap_start = .;
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
*(.heap*);
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
__HeapLimit = .;
- __uvisor_heap_end = . - 4;
} > RAM_INTERN
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
- __uvisor_public_sram_start = __uvisor_sram_start;
- __uvisor_public_sram_end = __uvisor_sram_end;
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c Thu Nov 08 11:46:34 2018 +0000
@@ -63,7 +63,6 @@
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
-extern void uvisor_init(void);
#if defined(TOOLCHAIN_GCC_ARM)
extern void _start(void);
#else
@@ -417,17 +416,6 @@
void Reset_Handler_2(void)
{
- /**
- * The call to uvisor_init() happens independently of uVisor being enabled or
- * not, so it is conditionally compiled only based on FEATURE_UVISOR.
- *
- * The call to uvisor_init() must be right after system initialization (usually called SystemInit()) and
- * right before the C/C++ library initialization (zeroing the BSS section, loading data from flash to SRAM).
- * Otherwise, we might get data corruption.
- */
-#if defined(FEATURE_UVISOR)
- uvisor_init();
-#endif
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
__main();
--- a/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -51,6 +51,9 @@
}
obj->mask = gpio_set(pin);
+ /* Default mode/direction */
+ obj->mode = PullUp;
+ obj->direction = PIN_INPUT;
}
void gpio_mode(gpio_t *obj, PinMode mode)
@@ -59,7 +62,44 @@
return;
}
- pin_mode(obj->pin, mode);
+ switch (mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ obj->mode = QuasiBidirectional;
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode
+ * in the gpio_mode call here. */
+ if (mode == InputOnly) {
+ obj->direction = PIN_INPUT;
+ obj->mode = InputOnly;
+ } else {
+ obj->direction = PIN_OUTPUT;
+ obj->mode = PushPullOutput;
+ }
+ break;
+
+ default:
+ /* Allow for configuring other I/O modes directly */
+ obj->mode = mode;
+ break;
+ }
+
+ pin_mode(obj->pin, obj->mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
@@ -68,24 +108,35 @@
return;
}
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
+ obj->direction = direction;
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
+ switch (obj->mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor direction
+ * in the gpio_dir call here. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
- default:
- return;
+ default:
+ break;
}
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+ pin_mode(obj->pin, obj->mode);
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/gpio_object.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,8 +28,10 @@
#endif
typedef struct {
- PinName pin;
- uint32_t mask;
+ PinName pin;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
--- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,9 +19,9 @@
#if DEVICE_LPTICKER
#include "sleep_api.h"
-#include "mbed_wait_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
+#include "nu_timer.h"
#include "nu_miscutil.h"
/* Micro seconds per second */
@@ -76,8 +76,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
lp_ticker_disable_interrupt();
- lp_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -103,10 +101,10 @@
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->CMP = cmp_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
// Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
@@ -114,13 +112,13 @@
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_EnableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
@@ -128,23 +126,7 @@
void lp_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
- /* Disable wakeup */
- TIMER_DisableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -166,6 +148,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ lp_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -47,27 +47,36 @@
uint32_t mode_intern = GPIO_MODE_INPUT;
switch (mode) {
- case PullUp:
- mode_intern = GPIO_MODE_INPUT;
- break;
+ case InputOnly:
+ mode_intern = GPIO_MODE_INPUT;
+ break;
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
+ case PushPullOutput:
+ mode_intern = GPIO_MODE_OUTPUT;
+ break;
- case PushPull:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
+ case OpenDrain:
+ mode_intern = GPIO_MODE_OPEN_DRAIN;
+ break;
- case OpenDrain:
- mode_intern = GPIO_MODE_OPEN_DRAIN;
- break;
+ case QuasiBidirectional:
+ mode_intern = GPIO_MODE_QUASI;
+ break;
- case Quasi:
- mode_intern = GPIO_MODE_QUASI;
- break;
+ default:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We expect upper layer would have translated input pull mode/direction
+ * to I/O mode */
+ return;
}
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ /* Invalid combinations of PinMode/PinDirection
+ *
+ * We assume developer would avoid the following combinations of PinMode/PinDirection
+ * which are invalid:
+ * 1. InputOnly/PIN_OUTPUT
+ * 2. PushPullOutput/PIN_INPUT
+ */
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -25,6 +25,7 @@
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include <string.h>
+#include <stdbool.h>
#if DEVICE_SERIAL_ASYNCH
#include "dma_api.h"
@@ -87,6 +88,8 @@
static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
#endif
+bool serial_can_deep_sleep(void);
+
static struct nu_uart_var uart0_var = {
.ref_cnt = 0,
.obj = NULL,
@@ -1145,4 +1148,23 @@
}
#endif // #if DEVICE_SERIAL_ASYNCH
+
+bool serial_can_deep_sleep(void)
+{
+ bool sleep_allowed = 1;
+ const struct nu_modinit_s *modinit = uart_modinit_tab;
+ while (modinit->var != NULL) {
+ struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ if (uart_var->ref_cnt > 0) {
+ if (!UART_IS_TX_EMPTY(uart_base)) {
+ sleep_allowed = 0;
+ break;
+ }
+ }
+ modinit++;
+ }
+ return sleep_allowed;
+}
+
#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_M480/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,6 +22,11 @@
#include "device.h"
#include "objects.h"
#include "PeripheralPins.h"
+#include <stdbool.h>
+
+#if DEVICE_SERIAL
+bool serial_can_deep_sleep(void);
+#endif
/**
* Enter idle mode, in which just CPU is halted.
@@ -38,6 +43,12 @@
*/
void hal_deepsleep(void)
{
+#if DEVICE_SERIAL
+ if (!serial_can_deep_sleep()) {
+ return;
+ }
+#endif
+
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
--- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -52,8 +52,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
- us_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -93,16 +91,7 @@
void us_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -124,6 +113,10 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ us_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,15 +55,18 @@
} PinDirection;
typedef enum {
+ /* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
- PushPull,
+ /* I/O mode */
+ InputOnly,
+ PushPullOutput,
OpenDrain,
- Quasi,
- PullDefault = PullUp,
+ /* Default input pull mode */
+ PullDefault = PullUp
} PinMode;
typedef enum {
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct Thu Nov 08 11:46:34 2018 +0000
@@ -6,9 +6,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct Thu Nov 08 11:46:34 2018 +0000
@@ -6,9 +6,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld Thu Nov 08 11:46:34 2018 +0000
@@ -51,41 +51,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
.text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -148,20 +119,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -174,39 +145,6 @@
} >RAM_INTERN AT>FLASH
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
.uninitialized (NOLOAD):
{
@@ -238,9 +176,4 @@
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf Thu Nov 08 11:46:34 2018 +0000 @@ -9,8 +9,8 @@ define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20004000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x600; -define symbol __ICFEDIT_size_heap__ = 0xE00; +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/startup_Nano100Series.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/startup_Nano100Series.c Thu Nov 08 11:46:34 2018 +0000 @@ -58,7 +58,6 @@ extern uint32_t __bss_start__; extern uint32_t __bss_end__; -extern void uvisor_init(void); #if defined(TOOLCHAIN_GCC_ARM) extern void _start(void); #else
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -48,6 +48,9 @@
}
obj->mask = gpio_set(pin);
+ /* Default mode/direction */
+ obj->mode = PullUp;
+ obj->direction = PIN_INPUT;
}
void gpio_mode(gpio_t *obj, PinMode mode)
@@ -55,8 +58,37 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- pin_mode(obj->pin, mode);
+
+ switch (mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode
+ * in the gpio_mode call here. */
+ if (mode == InputOnly) {
+ obj->direction = PIN_INPUT;
+ obj->mode = InputOnly;
+ } else {
+ obj->direction = PIN_OUTPUT;
+ obj->mode = PushPullOutput;
+ }
+ break;
+
+ default:
+ /* Allow for configuring other I/O modes directly */
+ obj->mode = mode;
+ break;
+ }
+
+ pin_mode(obj->pin, obj->mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
@@ -64,25 +96,28 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_PMD_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_PMD_INPUT;
+
+ obj->direction = direction;
+
+ switch (obj->mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_PMD_OUTPUT;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor direction
+ * in the gpio_dir call here. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
break;
-
+
default:
- return;
+ break;
}
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ pin_mode(obj->pin, obj->mode);
}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_object.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,8 +28,10 @@
#endif
typedef struct {
- PinName pin;
- uint32_t mask;
+ PinName pin;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,9 +19,9 @@
#if DEVICE_LPTICKER
#include "sleep_api.h"
-#include "mbed_wait_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
+#include "nu_timer.h"
#include "nu_miscutil.h"
/* Micro seconds per second */
@@ -78,8 +78,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
lp_ticker_disable_interrupt();
- lp_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -104,13 +102,13 @@
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
timer_base->CTL = TIMER_CONTINUOUS_MODE;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->PRECNT = prescale_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->CMPR = cmp_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
// Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
@@ -118,13 +116,13 @@
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_EnableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
@@ -132,23 +130,7 @@
void lp_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
-
- /* Disable wakeup */
- TIMER_DisableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -170,6 +152,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ lp_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -44,30 +44,35 @@
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
- uint32_t mode_intern = GPIO_PMD_INPUT;
-
+ uint32_t mode_intern;
+
switch (mode) {
- case PullUp:
+ case InputOnly:
mode_intern = GPIO_PMD_INPUT;
break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
+
+ case PushPullOutput:
mode_intern = GPIO_PMD_OUTPUT;
break;
-
+
case OpenDrain:
mode_intern = GPIO_PMD_OPEN_DRAIN;
break;
- case Quasi:
- // NOTE: Not support
- break;
+ default:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We expect upper layer would have translated input pull mode/direction
+ * to I/O mode */
+ return;
}
-
+
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ /* Invalid combinations of PinMode/PinDirection
+ *
+ * We assume developer would avoid the following combinations of PinMode/PinDirection
+ * which are invalid:
+ * 1. InputOnly/PIN_OUTPUT
+ * 2. PushPullOutput/PIN_INPUT
+ */
}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,13 +18,14 @@
#if DEVICE_SERIAL
-#include <string.h>
#include "cmsis.h"
#include "mbed_error.h"
#include "mbed_assert.h"
#include "PeripheralPins.h"
#include "nu_modutil.h"
#include "nu_bitutil.h"
+#include <string.h>
+#include <stdbool.h>
#if DEVICE_SERIAL_ASYNCH
#include "dma_api.h"
@@ -76,6 +77,8 @@
static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
#endif
+bool serial_can_deep_sleep(void);
+
static struct nu_uart_var uart0_var = {
.ref_cnt = 0,
.obj = NULL,
@@ -990,4 +993,23 @@
}
#endif // #if DEVICE_SERIAL_ASYNCH
+
+bool serial_can_deep_sleep(void)
+{
+ bool sleep_allowed = 1;
+ const struct nu_modinit_s *modinit = uart_modinit_tab;
+ while (modinit->var != NULL) {
+ struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ if (uart_var->ref_cnt > 0) {
+ if (!UART_IS_TX_EMPTY(uart_base)) {
+ sleep_allowed = 0;
+ break;
+ }
+ }
+ modinit++;
+ }
+ return sleep_allowed;
+}
+
#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,6 +22,11 @@
#include "device.h"
#include "objects.h"
#include "PeripheralPins.h"
+#include <stdbool.h>
+
+#if DEVICE_SERIAL
+bool serial_can_deep_sleep(void);
+#endif
/**
* Enter idle mode, in which just CPU is halted.
@@ -38,6 +43,12 @@
*/
void hal_deepsleep(void)
{
+#if DEVICE_SERIAL
+ if (!serial_can_deep_sleep()) {
+ return;
+ }
+#endif
+
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -54,8 +54,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
- us_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -95,16 +93,7 @@
void us_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -126,6 +115,10 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ us_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,15 +55,19 @@
} PinDirection;
typedef enum {
+ /* Input pull mode */
PullNone = 0,
PullDown,
PullUp,
- PushPull,
+ /* I/O mode */
+ InputOnly,
+ PushPullOutput,
OpenDrain,
- Quasi,
+ QuasiBidirectional,
- PullDefault = PullUp,
+ /* Default input pull mode */
+ PullDefault = PullUp
} PinMode;
typedef enum {
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct Thu Nov 08 11:46:34 2018 +0000
@@ -15,9 +15,6 @@
.ANY (+RO)
}
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld Thu Nov 08 11:46:34 2018 +0000
@@ -60,41 +60,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
.text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -166,20 +137,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -192,39 +163,6 @@
} >RAM_INTERN AT>FLASH
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
.uninitialized (NOLOAD):
{
@@ -269,9 +207,4 @@
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld Thu Nov 08 11:46:34 2018 +0000
@@ -59,41 +59,13 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
.text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -165,20 +137,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -191,39 +163,6 @@
} >RAM_INTERN AT>FLASH
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
.uninitialized (NOLOAD):
{
@@ -268,9 +207,4 @@
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c Thu Nov 08 11:46:34 2018 +0000 @@ -62,7 +62,6 @@ extern uint32_t __bss_extern_start__ WEAK; extern uint32_t __bss_extern_end__ WEAK; -extern void uvisor_init(void); #if defined(TOOLCHAIN_GCC_ARM) extern void _start(void); #else
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -51,6 +51,9 @@
}
obj->mask = gpio_set(pin);
+ /* Default mode/direction */
+ obj->mode = PullUp;
+ obj->direction = PIN_INPUT;
}
void gpio_mode(gpio_t *obj, PinMode mode)
@@ -58,8 +61,45 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- pin_mode(obj->pin, mode);
+
+ switch (mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ obj->mode = QuasiBidirectional;
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode
+ * in the gpio_mode call here. */
+ if (mode == InputOnly) {
+ obj->direction = PIN_INPUT;
+ obj->mode = InputOnly;
+ } else {
+ obj->direction = PIN_OUTPUT;
+ obj->mode = PushPullOutput;
+ }
+ break;
+
+ default:
+ /* Allow for configuring other I/O modes directly */
+ obj->mode = mode;
+ break;
+ }
+
+ pin_mode(obj->pin, obj->mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
@@ -67,25 +107,36 @@
if (obj->pin == (PinName) NC) {
return;
}
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
+
+ obj->direction = direction;
+
+ switch (obj->mode) {
+ case PullNone:
+ case PullDown:
+ case PullUp:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We translate to input-only/push-pull output I/O mode dependent on direction. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
break;
+ case QuasiBidirectional:
+ /* With quasi-bidirectional I/O mode, before digital input function is performed,
+ * the corresponding bit in GPIOx_DOUT must be set to 1. */
+ if (obj->direction == PIN_INPUT) {
+ gpio_write(obj, 1);
+ }
+ break;
+
+ case InputOnly:
+ case PushPullOutput:
+ /* We may meet contradictory I/O mode/direction configuration. Favor direction
+ * in the gpio_dir call here. */
+ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput;
+ break;
+
default:
- return;
+ break;
}
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ pin_mode(obj->pin, obj->mode);
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_object.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,8 +28,10 @@
#endif
typedef struct {
- PinName pin;
- uint32_t mask;
+ PinName pin;
+ uint32_t mask;
+ PinDirection direction;
+ PinMode mode;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,9 +19,9 @@
#if DEVICE_LPTICKER
#include "sleep_api.h"
-#include "mbed_wait_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
+#include "nu_timer.h"
#include "nu_miscutil.h"
/* Micro seconds per second */
@@ -76,8 +76,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
lp_ticker_disable_interrupt();
- lp_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -102,10 +100,10 @@
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
timer_base->CMP = cmp_timer;
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
// Set vector
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
@@ -113,13 +111,13 @@
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_EnableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
TIMER_Start(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
@@ -127,23 +125,7 @@
void lp_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
- /* Disable wakeup */
- TIMER_DisableWakeup(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
- wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -165,6 +147,10 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ lp_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -54,30 +54,39 @@
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
+ uint32_t mode_intern;
+
switch (mode) {
- case PullUp:
+ case InputOnly:
mode_intern = GPIO_MODE_INPUT;
break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
+
+ case PushPullOutput:
mode_intern = GPIO_MODE_OUTPUT;
break;
-
+
case OpenDrain:
mode_intern = GPIO_MODE_OPEN_DRAIN;
break;
-
- case Quasi:
+
+ case QuasiBidirectional:
mode_intern = GPIO_MODE_QUASI;
break;
+
+ default:
+ /* H/W doesn't support separate configuration for input pull mode/direction.
+ * We expect upper layer would have translated input pull mode/direction
+ * to I/O mode */
+ return;
}
-
+
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+
+ /* Invalid combinations of PinMode/PinDirection
+ *
+ * We assume developer would avoid the following combinations of PinMode/PinDirection
+ * which are invalid:
+ * 1. InputOnly/PIN_OUTPUT
+ * 2. PushPullOutput/PIN_INPUT
+ */
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -25,6 +25,7 @@
#include "nu_modutil.h"
#include "nu_bitutil.h"
#include <string.h>
+#include <stdbool.h>
#if DEVICE_SERIAL_ASYNCH
#include "dma_api.h"
@@ -87,6 +88,8 @@
static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
#endif
+bool serial_can_deep_sleep(void);
+
static struct nu_uart_var uart0_var = {
.ref_cnt = 0,
.obj = NULL,
@@ -1136,4 +1139,23 @@
}
#endif // #if DEVICE_SERIAL_ASYNCH
+
+bool serial_can_deep_sleep(void)
+{
+ bool sleep_allowed = 1;
+ const struct nu_modinit_s *modinit = uart_modinit_tab;
+ while (modinit->var != NULL) {
+ struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
+ UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+ if (uart_var->ref_cnt > 0) {
+ if (!UART_IS_TX_EMPTY(uart_base)) {
+ sleep_allowed = 0;
+ break;
+ }
+ }
+ modinit++;
+ }
+ return sleep_allowed;
+}
+
#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -22,6 +22,11 @@
#include "device.h"
#include "objects.h"
#include "PeripheralPins.h"
+#include <stdbool.h>
+
+#if DEVICE_SERIAL
+bool serial_can_deep_sleep(void);
+#endif
/**
* Enter idle mode, in which just CPU is halted.
@@ -38,6 +43,12 @@
*/
void hal_deepsleep(void)
{
+#if DEVICE_SERIAL
+ if (!serial_can_deep_sleep()) {
+ return;
+ }
+#endif
+
SYS_UnlockReg();
CLK_PowerDown();
SYS_LockReg();
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -52,8 +52,6 @@
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
- us_ticker_clear_interrupt();
- NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
return;
}
ticker_inited = 1;
@@ -92,16 +90,7 @@
void us_ticker_free(void)
{
- TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-
- /* Stop counting */
- TIMER_Stop(timer_base);
-
- /* Wait for timer to stop counting and unset active flag */
- while((timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
-
/* Disable interrupt */
- TIMER_DisableInt(timer_base);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
/* Disable IP clock */
@@ -123,6 +112,10 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
+ /* Clear any previously pending interrupts */
+ us_ticker_clear_interrupt();
+ NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n);
+
/* In continuous mode, counter will be reset to zero with the following sequence:
* 1. Stop counting
* 2. Configure new CMP value
--- a/targets/TARGET_NUVOTON/mbed_rtx.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000
@@ -45,6 +45,13 @@
#error "no toolchain defined"
#endif
+#if defined(TARGET_NANO100)
+#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
+#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
+#endif
+#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072
+#endif
+
#endif // TARGET_NUVOTON
#endif // MBED_MBED_RTX_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NUVOTON/nu_timer.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nu_timer.h"
+#include "mbed_power_mgmt.h"
+#include "mbed_critical.h"
+#include "us_ticker_api.h"
+#include "mbed_assert.h"
+
+void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us)
+{
+ core_util_critical_section_enter();
+ sleep_manager_lock_deep_sleep();
+ ctx->_ticker_data = get_us_ticker_data();
+ ctx->_interval_end_us = ticker_read_us(ctx->_ticker_data) + interval_us;
+ ctx->_expired = false;
+ core_util_critical_section_exit();
+}
+
+bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx)
+{
+ core_util_critical_section_enter();
+ if (! ctx->_expired) {
+ ctx->_expired = ticker_read_us(ctx->_ticker_data) >= ctx->_interval_end_us;
+ }
+ core_util_critical_section_exit();
+
+ return ctx->_expired;
+}
+
+void nu_countdown_free(struct nu_countdown_ctx_s *ctx)
+{
+ core_util_critical_section_enter();
+ sleep_manager_unlock_deep_sleep();
+ core_util_critical_section_exit();
+}
+
+
+void nu_busy_wait_us(uint32_t us)
+{
+ const uint32_t bits = us_ticker_get_info()->bits;
+ const uint32_t mask = (1 << bits) - 1;
+ MBED_ASSERT(us_ticker_get_info()->frequency == 1000000);
+ uint32_t prev = us_ticker_read();
+ while (1) {
+ const uint32_t cur = us_ticker_read();
+ const uint32_t elapsed = (cur - prev) & mask;
+ if (elapsed > us) {
+ break;
+ }
+ us -= elapsed;
+ prev = cur;
+ }
+}
+
+/* Delay 4 cycles per round by hand-counting instruction cycles
+ *
+ * The delay function here is implemented by just hand-counting instruction cycles rather than preferred
+ * H/W timer since it is to use in cases where H/W timer is not available. Usually, it can delay at least
+ * 4-cycles per round.
+ *
+ * In modern pipeline core, plus flash performance and other factors, we cannot rely accurately on hand-
+ * counting instruction cycles for expected delay cycles.
+ */
+#if defined(__CC_ARM)
+MBED_NOINLINE
+__asm void nu_delay_cycle_x4(uint32_t rounds)
+{
+// AStyle should not format inline assembly
+// *INDENT-OFF*
+1
+#if !defined(__CORTEX_M0)
+ NOP // 1 cycle
+#endif
+ SUBS a1, a1, #1 // 1 cycle
+ BCS %BT1 // 3 cycles(M0)/2 cycles(non-M0)
+ BX lr
+// *INDENT-ON*
+}
+#elif defined (__ICCARM__)
+MBED_NOINLINE
+void nu_delay_cycle_x4(uint32_t rounds)
+{
+ __asm volatile(
+ "loop: \n"
+#if !defined(__CORTEX_M0)
+ " NOP \n" // 1 cycle
+#endif
+ " SUBS %0, %0, #1 \n" // 1 cycle
+ " BCS.n loop\n" // 3 cycles(M0)/2 cycles(non-M0)
+ : "+r"(rounds)
+ :
+ : "cc"
+ );
+}
+#elif defined ( __GNUC__ ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+MBED_NOINLINE
+void nu_delay_cycle_x4(uint32_t rounds)
+{
+ __asm__ volatile(
+ "%=:\n\t"
+#if !defined(__CORTEX_M0)
+ "NOP\n\t" // 1 cycle
+#endif
+#if defined(__thumb__) && !defined(__thumb2__) && !defined(__ARMCC_VERSION)
+ "SUB %0, #1\n\t" // 1 cycle
+#else
+ "SUBS %0, %0, #1\n\t" // 1 cycle
+#endif
+ "BCS %=b\n\t" // 3 cycles(M0)/2 cycles(non-M0)
+ : "+l"(rounds)
+ :
+ : "cc"
+ );
+}
+#endif
--- a/targets/TARGET_NUVOTON/nu_timer.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NUVOTON/nu_timer.h Thu Nov 08 11:46:34 2018 +0000
@@ -20,8 +20,6 @@
#include <stdint.h>
#include <stdbool.h>
#include "cmsis.h"
-#include "mbed_power_mgmt.h"
-#include "mbed_critical.h"
#include "ticker_api.h"
#include "us_ticker_api.h"
@@ -58,33 +56,26 @@
bool _expired; // Expired or not
};
-__STATIC_INLINE void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us)
-{
- core_util_critical_section_enter();
- sleep_manager_lock_deep_sleep();
- ctx->_ticker_data = get_us_ticker_data();
- ctx->_interval_end_us = ticker_read_us(ctx->_ticker_data) + interval_us;
- ctx->_expired = false;
- core_util_critical_section_exit();
-}
+void nu_countdown_init(struct nu_countdown_ctx_s *ctx, us_timestamp_t interval_us);
+bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx);
+void nu_countdown_free(struct nu_countdown_ctx_s *ctx);
+
-__STATIC_INLINE bool nu_countdown_expired(struct nu_countdown_ctx_s *ctx)
-{
- core_util_critical_section_enter();
- if (! ctx->_expired) {
- ctx->_expired = ticker_read_us(ctx->_ticker_data) >= ctx->_interval_end_us;
- }
- core_util_critical_section_exit();
-
- return ctx->_expired;
-}
+/* Replacement for wait_us when intermediary us ticker layer is disabled
+ *
+ * Use of wait_us directly from the low power ticker causes the system to deadlock during
+ * the sleep test because the sleep test disables the intermediary us ticker layer during
+ * the test.
+ *
+ * To prevent this lockup, nu_busy_wait_us is created to replace wait_us, which uses the us ticker
+ * directly rather than go though the intermediary us ticker layer.
+ *
+ * During wait period through nu_busy_wait_us, CPU would be busy spinning.
+ */
+void nu_busy_wait_us(uint32_t us);
-__STATIC_INLINE void nu_countdown_free(struct nu_countdown_ctx_s *ctx)
-{
- core_util_critical_section_enter();
- sleep_manager_unlock_deep_sleep();
- core_util_critical_section_exit();
-}
+/* Delay 4 cycles per round by hand-counting instruction cycles */
+void nu_delay_cycle_x4(uint32_t rounds);
#ifdef __cplusplus
}
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld Thu Nov 08 11:46:34 2018 +0000
@@ -30,14 +30,14 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -66,18 +66,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -102,13 +102,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
@@ -124,14 +124,14 @@
} > Ram1_2
/* DATA section for Ram1_2 */
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_2)
*(.data.$RAM2*)
*(.data.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2 AT>MFlash256
/* possible MTB section for Ram2USB_2 */
.mtb_buffer_RAM3 (NOLOAD) :
@@ -141,14 +141,14 @@
} > Ram2USB_2
/* DATA section for Ram2USB_2 */
- .data_RAM3 : ALIGN(4)
+ .data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2USB_2)
*(.data.$RAM3*)
*(.data.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2 AT>MFlash256
/* MAIN DATA SECTION */
@@ -159,74 +159,74 @@
KEEP(*(.mtb*))
} > Ram0_32
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > Ram0_32
/* Main DATA section (Ram0_32) */
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = . ;
} > Ram0_32 AT>MFlash256
/* BSS section for Ram1_2 */
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2
/* BSS section for Ram2USB_2 */
- .bss_RAM3 : ALIGN(4)
+ .bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_32
/* NOINIT section for Ram1_2 */
- .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ .noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2
/* NOINIT section for Ram2USB_2 */
- .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ .noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > Ram0_32
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld Thu Nov 08 11:46:34 2018 +0000
@@ -31,7 +31,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -39,7 +39,7 @@
*(.text.SystemInit)
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -68,18 +68,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -104,13 +104,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
@@ -126,14 +126,14 @@
} > Ram1_2
/* DATA section for Ram1_2 */
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_2)
*(.data.$RAM2*)
*(.data.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2 AT>MFlash256
/* possible MTB section for Ram2USB_2 */
.mtb_buffer_RAM3 (NOLOAD) :
@@ -143,14 +143,14 @@
} > Ram2USB_2
/* DATA section for Ram2USB_2 */
- .data_RAM3 : ALIGN(4)
+ .data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2USB_2)
*(.data.$RAM3*)
*(.data.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2 AT>MFlash256
/* MAIN DATA SECTION */
@@ -161,74 +161,74 @@
KEEP(*(.mtb*))
} > Ram0_32
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > Ram0_32
/* Main DATA section (Ram0_32) */
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = . ;
} > Ram0_32 AT>MFlash256
/* BSS section for Ram1_2 */
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2
/* BSS section for Ram2USB_2 */
- .bss_RAM3 : ALIGN(4)
+ .bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_32
/* NOINIT section for Ram1_2 */
- .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ .noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_2
/* NOINIT section for Ram2USB_2 */
- .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ .noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2USB_2
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > Ram0_32
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -266,7 +266,7 @@
(parity == ParityForced1) || (parity == ParityForced0));
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
@@ -274,7 +274,7 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
- return;
+ break;
}
obj->uart->LCR = data_bits << 0
--- a/targets/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -65,3 +65,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,14 +106,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,14 +106,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld Thu Nov 08 11:46:34 2018 +0000
@@ -90,13 +90,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -104,14 +104,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,14 +106,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -21,13 +21,13 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -51,18 +51,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -88,13 +88,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -103,46 +103,46 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld Thu Nov 08 11:46:34 2018 +0000
@@ -21,7 +21,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -29,7 +29,7 @@
. = 0x200;
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -53,18 +53,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -90,13 +90,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -105,46 +105,46 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld Thu Nov 08 11:46:34 2018 +0000
@@ -21,7 +21,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -29,7 +29,7 @@
. = 0x200;
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -53,18 +53,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -90,13 +90,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -105,46 +105,46 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld Thu Nov 08 11:46:34 2018 +0000
@@ -23,7 +23,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -31,7 +31,7 @@
. = 0x200;
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -55,18 +55,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -92,13 +92,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -107,46 +107,46 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld Thu Nov 08 11:46:34 2018 +0000
@@ -21,7 +21,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -29,7 +29,7 @@
. = 0x200;
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -53,18 +53,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -90,13 +90,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -105,46 +105,46 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CS/LPC11U24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CS/LPC11U24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -75,15 +75,15 @@
*(.eh_frame_hdr)
*(.eh_frame)
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -95,10 +95,10 @@
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -109,7 +109,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
--- a/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -65,3 +65,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld Thu Nov 08 11:46:34 2018 +0000
@@ -87,13 +87,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,14 +101,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld Thu Nov 08 11:46:34 2018 +0000
@@ -87,13 +87,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,14 +101,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld Thu Nov 08 11:46:34 2018 +0000
@@ -19,7 +19,7 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
@@ -28,7 +28,7 @@
. = 0x200;
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -47,18 +47,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -84,13 +84,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -102,30 +102,30 @@
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -193,7 +193,7 @@
stop_bits -= 1;
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
@@ -201,7 +201,6 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
- parity_enable = 0, parity_select = 0;
break;
}
--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -65,3 +65,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC13XX/device/TOOLCHAIN_GCC_ARM/LPC1347.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/device/TOOLCHAIN_GCC_ARM/LPC1347.ld Thu Nov 08 11:46:34 2018 +0000
@@ -87,13 +87,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,14 +101,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC13XX/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -196,7 +196,7 @@
stop_bits -= 1;
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
--- a/targets/TARGET_NXP/TARGET_LPC13XX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -65,3 +65,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_CR/LPC1549.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_CR/LPC1549.ld Thu Nov 08 11:46:34 2018 +0000
@@ -31,13 +31,13 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -66,18 +66,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -102,13 +102,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
@@ -117,95 +117,95 @@
_etext = .;
/* DATA section for Ram1_16 */
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_16)
*(.data.$RAM2*)
*(.data.$Ram1_16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_16 AT>MFlash256
/* DATA section for Ram2_4 */
- .data_RAM3 : ALIGN(4)
+ .data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2_4)
*(.data.$RAM3*)
*(.data.$Ram2_4*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2_4 AT>MFlash256
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > Ram0_16
/* Main DATA section (Ram0_16) */
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = . ;
} > Ram0_16 AT>MFlash256
/* BSS section for Ram1_16 */
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_16
/* BSS section for Ram2_4 */
- .bss_RAM3 : ALIGN(4)
+ .bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$Ram2_4*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2_4
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_16
/* NOINIT section for Ram1_16 */
- .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ .noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram1_16
/* NOINIT section for Ram2_4 */
- .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ .noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2_4*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > Ram2_4
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > Ram0_16
--- a/targets/TARGET_NXP/TARGET_LPC15XX/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -203,7 +203,7 @@
stop_bits -= 1;
data_bits -= 7;
- int paritysel;
+ int paritysel = 0;
switch (parity) {
case ParityNone: paritysel = 0; break;
case ParityEven: paritysel = 2; break;
--- a/targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -86,3 +86,8 @@
// Clear SCT3 event 0 interrupt flag
LPC_SCT3->EVFLAG = (1 << 0);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld Thu Nov 08 11:46:34 2018 +0000
@@ -100,13 +100,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -114,14 +114,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/TARGET_XBED_LPC1768/XBED_LPC1768.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/TARGET_XBED_LPC1768/XBED_LPC1768.ld Thu Nov 08 11:46:34 2018 +0000
@@ -88,13 +88,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -102,14 +102,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CR/LPC1768.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CR/LPC1768.ld Thu Nov 08 11:46:34 2018 +0000
@@ -23,13 +23,13 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -53,18 +53,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -90,13 +90,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash512
@@ -105,52 +105,52 @@
_etext = .;
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamAHB32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_USB AT>MFlash512
/* MAIN DATA SECTION */
- .uninit_RESERVED(NOLOAD) : ALIGN(4)
+ .uninit_RESERVED(NOLOAD) : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc32
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc32 AT>MFlash512
- .bss_RAM2(NOLOAD) : ALIGN(4)
+ .bss_RAM2(NOLOAD) : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamAHB32*)
*(AHBSRAM0)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_USB
- .bss_RAM3(NOLOAD) : ALIGN(4)
+ .bss_RAM3(NOLOAD) : ALIGN(8)
{
*(AHBSRAM1)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_Eth
/* MAIN BSS SECTION */
- .bss(NOLOAD) : ALIGN(4)
+ .bss(NOLOAD) : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CS/LPC1768.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CS/LPC1768.ld Thu Nov 08 11:46:34 2018 +0000
@@ -76,15 +76,15 @@
*(.eh_frame_hdr)
*(.eh_frame)
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -96,10 +96,10 @@
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
@@ -110,7 +110,7 @@
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- . = ALIGN(4);
+ . = ALIGN(8);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
--- a/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -256,7 +256,7 @@
stop_bits -= 1;
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
@@ -264,7 +264,6 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
- parity_enable = 0, parity_select = 0;
break;
}
--- a/targets/TARGET_NXP/TARGET_LPC176X/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -28,8 +28,19 @@
static bool us_ticker_inited = false;
+#if MBED_CONF_TARGET_US_TICKER_TIMER == 0
+#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM0_BASE)
+#define US_TICKER_TIMER_IRQn TIMER0_IRQn
+#elif MBED_CONF_TARGET_US_TICKER_TIMER == 1
+#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM1_BASE)
+#define US_TICKER_TIMER_IRQn TIMER1_IRQn
+#elif MBED_CONF_TARGET_US_TICKER_TIMER == 1
+#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM2_BASE)
+#define US_TICKER_TIMER_IRQn TIMER2_IRQn
+#else
#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
#define US_TICKER_TIMER_IRQn TIMER3_IRQn
+#endif
void us_ticker_init(void) {
if (us_ticker_inited) {
@@ -77,3 +88,11 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+ US_TICKER_TIMER->TCR = 0;
+
+ US_TICKER_TIMER->MCR &= ~1;
+ NVIC_DisableIRQ(US_TICKER_TIMER_IRQn);
+}
--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -219,7 +219,7 @@
stop_bits -= 1;
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -206,7 +206,7 @@
stop_bits -= 1;
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
--- a/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_ARM/LPC4088.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_ARM/LPC4088.ld Thu Nov 08 11:46:34 2018 +0000
@@ -88,13 +88,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -102,14 +102,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_CR/LPC407x_8x.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_CR/LPC407x_8x.ld Thu Nov 08 11:46:34 2018 +0000
@@ -28,13 +28,13 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -58,18 +58,18 @@
*(.text*)
*(.rodata .rodata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -77,13 +77,13 @@
KEEP(*(.fini));
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
@@ -95,13 +95,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash512
@@ -111,68 +111,68 @@
/* DATA section for RamPeriph32 */
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamPeriph32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamPeriph32 AT>MFlash512
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc64
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = .;
} > RamLoc64 AT>MFlash512
/* BSS section for RamPeriph32 */
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamPeriph32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamPeriph32
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc64
/* NOINIT section for RamPeriph32 */
- .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ .noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$RamPeriph32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamPeriph32
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > RamLoc64
--- a/targets/TARGET_NXP/TARGET_LPC408X/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -67,3 +67,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_ARM/LPC4330.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_ARM/LPC4330.ld Thu Nov 08 11:46:34 2018 +0000
@@ -90,13 +90,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -104,14 +104,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_CR/LPC43xx.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_CR/LPC43xx.ld Thu Nov 08 11:46:34 2018 +0000
@@ -29,14 +29,14 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -75,22 +75,22 @@
} >SPIFI
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -98,13 +98,13 @@
KEEP(*(.fini));
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
@@ -116,13 +116,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SPIFI
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SPIFI
@@ -132,147 +132,147 @@
/* DATA section for RamLoc72 */
- .data_RAM2 : ALIGN(4)
+ .data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$RamLoc72)
*(.data.$RAM2*)
*(.data.$RamLoc72*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamLoc72 AT>SPIFI
/* DATA section for RamAHB32 */
- .data_RAM3 : ALIGN(4)
+ .data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$RamAHB32)
*(.data.$RAM3*)
*(.data.$RamAHB32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB32 AT>SPIFI
/* DATA section for RamAHB16 */
- .data_RAM4 : ALIGN(4)
+ .data_RAM4 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM4)
*(.ramfunc.$RamAHB16)
*(.data.$RAM4*)
*(.data.$RamAHB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB16 AT>SPIFI
/* DATA section for RamAHB_ETB16 */
- .data_RAM5 : ALIGN(4)
+ .data_RAM5 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM5)
*(.ramfunc.$RamAHB_ETB16)
*(.data.$RAM5*)
*(.data.$RamAHB_ETB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_ETB16 AT>SPIFI
/* MAIN DATA SECTION */
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc128
/* Main DATA section (RamLoc128) */
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = . ;
} > RamLoc128 AT>SPIFI
/* BSS section for RamLoc72 */
- .bss_RAM2 : ALIGN(4)
+ .bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamLoc72*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamLoc72
/* BSS section for RamAHB32 */
- .bss_RAM3 : ALIGN(4)
+ .bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$RamAHB32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB32
/* BSS section for RamAHB16 */
- .bss_RAM4 : ALIGN(4)
+ .bss_RAM4 : ALIGN(8)
{
*(.bss.$RAM4*)
*(.bss.$RamAHB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB16
/* BSS section for RamAHB_ETB16 */
- .bss_RAM5 : ALIGN(4)
+ .bss_RAM5 : ALIGN(8)
{
*(.bss.$RAM5*)
*(.bss.$RamAHB_ETB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_ETB16
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc128
/* NOINIT section for RamLoc72 */
- .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ .noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$RamLoc72*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamLoc72
/* NOINIT section for RamAHB32 */
- .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ .noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$RamAHB32*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB32
/* NOINIT section for RamAHB16 */
- .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ .noinit_RAM4 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM4*)
*(.noinit.$RamAHB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB16
/* NOINIT section for RamAHB_ETB16 */
- .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ .noinit_RAM5 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM5*)
*(.noinit.$RamAHB_ETB16*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > RamAHB_ETB16
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > RamLoc128
--- a/targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -89,7 +89,7 @@
static const PinMap PinMap_UART_CTS[] = {
{P1_11, UART_1, (SCU_PINIO_FAST | 1)},
- {P5_4, UART_1, (SCU_PINIO_FAST | 4),
+ {P5_4, UART_1, (SCU_PINIO_FAST | 4)},
{PC_2, UART_1, (SCU_PINIO_FAST | 2)},
{PE_7, UART_1, (SCU_PINIO_FAST | 2)},
{NC, NC, 0}
@@ -264,7 +264,7 @@
}
data_bits -= 5;
- int parity_enable, parity_select;
+ int parity_enable = 0, parity_select = 0;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
@@ -272,8 +272,7 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
- error("Invalid serial parity setting");
- return;
+ break;
}
obj->uart->LCR = data_bits << 0
--- a/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -67,3 +67,8 @@
void us_ticker_clear_interrupt(void) {
US_TICKER_TIMER->IR = 1;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_GCC_ARM/LPC812.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_ELEKTOR_COCORICO/device/TOOLCHAIN_GCC_ARM/LPC812.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/device/TOOLCHAIN_GCC_ARM/LPC810.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/device/TOOLCHAIN_GCC_ARM/LPC810.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC81X/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -188,7 +188,7 @@
stop_bits -= 1;
data_bits -= 7;
- int paritysel;
+ int paritysel = 0;
switch (parity) {
case ParityNone: paritysel = 0; break;
case ParityEven: paritysel = 2; break;
--- a/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -136,3 +136,8 @@
ticker_expired_count_us += ticker_fullcount_us;
}
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld Thu Nov 08 11:46:34 2018 +0000
@@ -89,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -103,14 +103,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_CR/LPC824.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_CR/LPC824.ld Thu Nov 08 11:46:34 2018 +0000
@@ -54,14 +54,14 @@
{
/* MAIN TEXT SECTION */
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
@@ -79,23 +79,23 @@
*(.after_vectors*)
} >MFlash32
- .text : ALIGN(4)
+ .text : ALIGN(8)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* C++ constructors etc */
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.init))
- . = ALIGN(4);
+ . = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
- . = ALIGN(4);
+ . = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
@@ -129,13 +129,13 @@
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
- .ARM.exidx : ALIGN(4)
+ .ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
@@ -152,45 +152,45 @@
KEEP(*(.mtb*))
} > RamLoc8
- .uninit_RESERVED : ALIGN(4)
+ .uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc8
/* Main DATA section (RamLoc8) */
- .data : ALIGN(4)
+ .data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_edata = . ;
} > RamLoc8 AT>MFlash32
/* MAIN BSS SECTION */
- .bss : ALIGN(4)
+ .bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc8
/* DEFAULT NOINIT SECTION */
- .noinit (NOLOAD): ALIGN(4)
+ .noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
_end_noinit = .;
} > RamLoc8
--- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld Thu Nov 08 11:46:34 2018 +0000
@@ -90,13 +90,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -104,14 +104,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -109,3 +109,8 @@
ticker_expired_count_us += ticker_fullcount_us;
}
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -112,4 +112,9 @@
GPT_ClearStatusFlags(GPT2, kGPT_OutputCompare1Flag);
}
+void lp_ticker_free(void)
+{
+
+}
+
#endif /* DEVICE_LPTICKER */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/pwmout_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/pwmout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -23,12 +23,13 @@
#include "fsl_pwm.h"
#include "PeripheralPins.h"
-static float pwm_clock_mhz;
+static float pwm_clock_mhz = 0;
+
/* Array of PWM peripheral base address. */
static PWM_Type *const pwm_addrs[] = PWM_BASE_PTRS;
-extern void pwm_setup_clock();
+extern void pwm_setup();
extern uint32_t pwm_get_clock();
void pwmout_init(pwmout_t* obj, PinName pin)
@@ -36,48 +37,57 @@
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
- pwm_setup_clock();
+ uint32_t pwm_base_clock;
+ uint32_t instance = (pwm >> PWM_SHIFT) & 0x7;
+ uint32_t module = (pwm >> PWM_MODULE_SHIFT) & 0x3;
+ uint32_t pwmchannel = pwm & 0x1;
+ pwm_config_t pwmInfo;
+ static uint32_t clkdiv;
obj->pwm_name = pwm;
+ pwm_base_clock = pwm_get_clock();
- uint32_t pwm_base_clock;
- pwm_base_clock = pwm_get_clock();
- float clkval = (float)pwm_base_clock / 1000000.0f;
- uint32_t clkdiv = 0;
- while (clkval > 1) {
- clkdiv++;
- clkval /= 2.0f;
- if (clkdiv == 7) {
- break;
+ if (pwm_clock_mhz == 0) {
+ float clkval = (float)pwm_base_clock / 1000000.0f;
+
+ while (clkval > 1) {
+ clkdiv++;
+ clkval /= 2.0f;
+ if (clkdiv == 7) {
+ break;
+ }
}
+ pwm_clock_mhz = clkval;
}
- pwm_clock_mhz = clkval;
- uint32_t instance = (pwm >> PWM_SHIFT) & 0x3;
- uint32_t module = pwm >> PWM_MODULE_SHIFT;
- uint8_t pwmchannel = pwm & 0x1;
- pwm_config_t pwmInfo;
+ pwm_setup(instance);
+ /* Initialize PWM module */
PWM_GetDefaultConfig(&pwmInfo);
pwmInfo.prescale = (pwm_clock_prescale_t)clkdiv;
- /* Initialize PWM module */
+
PWM_Init(pwm_addrs[instance], (pwm_submodule_t)module, &pwmInfo);
- pwm_signal_param_t config = {
+ pwm_signal_param_t channel_config = {
.level = kPWM_HighTrue,
.dutyCyclePercent = 0,
.deadtimeValue = 0
};
+
if (pwmchannel == 0) {
- config.pwmChannel = kPWM_PwmA;
+ channel_config.pwmChannel = kPWM_PwmA;
} else {
- config.pwmChannel = kPWM_PwmB;
+ channel_config.pwmChannel = kPWM_PwmB;
}
- // default to 20ms: standard for servos, and fine for e.g. brightness control
- PWM_SetupPwm(pwm_addrs[instance], (pwm_submodule_t)module, &config, 1, kPWM_EdgeAligned, 50, pwm_base_clock);
+ // Setup the module signals to be low
+ PWM_SetupPwm(pwm_addrs[instance], (pwm_submodule_t)module, &channel_config, 1, kPWM_EdgeAligned, 50, pwm_base_clock);
- PWM_StartTimer(pwm_addrs[instance], module);
+ /* Set the load okay bit for all submodules to load registers from their buffer */
+ PWM_SetPwmLdok(pwm_addrs[instance], (1 << module), true);
+
+ /* Start the timer for the sub-module */
+ PWM_StartTimer(pwm_addrs[instance], (1 << module));
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
@@ -85,10 +95,10 @@
void pwmout_free(pwmout_t* obj)
{
- uint32_t instance = (obj->pwm_name >> PWM_SHIFT) & 0x3;
- uint32_t module = obj->pwm_name >> PWM_MODULE_SHIFT;
+ uint32_t instance = (obj->pwm_name >> PWM_SHIFT) & 0x7;
+ uint32_t module = (obj->pwm_name >> PWM_MODULE_SHIFT) & 0x3;
- PWM_Deinit(pwm_addrs[instance], (pwm_submodule_t)module);
+ PWM_StopTimer(pwm_addrs[instance], (1 << module));
}
void pwmout_write(pwmout_t* obj, float value)
@@ -99,9 +109,9 @@
value = 1.0f;
}
- PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x3];
- uint32_t module = obj->pwm_name >> PWM_MODULE_SHIFT;
- uint32_t pwmchannel = obj->pwm_name & 0xF;
+ PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x7];
+ uint32_t module = (obj->pwm_name >> PWM_MODULE_SHIFT) & 0x3;
+ uint32_t pwmchannel = obj->pwm_name & 0x1;
uint16_t pulseCnt = 0;
pulseCnt = base->SM[module].VAL1;
@@ -117,15 +127,14 @@
}
/* Set the load okay bit */
- PWM_SetPwmLdok(base, module, true);
-
+ PWM_SetPwmLdok(base, (1 << module), true);
}
float pwmout_read(pwmout_t* obj)
{
- PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x3];
- uint32_t module = obj->pwm_name >> PWM_MODULE_SHIFT;
- uint32_t pwmchannel = obj->pwm_name & 0xF;
+ PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x7];
+ uint32_t module = (obj->pwm_name >> PWM_MODULE_SHIFT) & 0x3;
+ uint32_t pwmchannel = obj->pwm_name & 0x1;
uint16_t count;
uint16_t mod = (base->SM[module].VAL1) & PWM_VAL1_VAL1_MASK;
@@ -157,12 +166,30 @@
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us)
{
- PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x3];
- uint32_t module = obj->pwm_name >> PWM_MODULE_SHIFT;
+ PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x7];
+ uint32_t module = (obj->pwm_name >> PWM_MODULE_SHIFT) & 0x3;
float dc = pwmout_read(obj);
+ uint32_t pwm_base_clock;
+
+ pwm_base_clock = pwm_get_clock();
+ uint32_t clkdiv = 0;
+
+ pwm_clock_mhz = (float) pwm_base_clock / 1000000.0f;
+ uint32_t mod = (pwm_clock_mhz * (float) us) - 1;
+ while (mod > 0xFFFF) {
+ ++clkdiv;
+ pwm_clock_mhz /= 2.0f;
+ mod = (pwm_clock_mhz * (float) us) - 1;
+ if (clkdiv == 7) {
+ break;
+ }
+ }
+ uint32_t PRSC = base->SM[module].CTRL & ~PWM_CTRL_PRSC_MASK;
+ PRSC |= PWM_CTRL_PRSC(clkdiv);
+ base->SM[module].CTRL = PRSC;
/* Indicates the end of the PWM period */
- base->SM[module].VAL1 = PWM_VAL1_VAL1((pwm_clock_mhz * (float)us) - 1);
+ base->SM[module].VAL1 = PWM_VAL1_VAL1(mod);
pwmout_write(obj, dc);
}
@@ -179,9 +206,9 @@
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
- PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x3];
- uint32_t module = obj->pwm_name >> PWM_MODULE_SHIFT;
- uint32_t pwmchannel = obj->pwm_name & 0xF;
+ PWM_Type *base = pwm_addrs[(obj->pwm_name >> PWM_SHIFT) & 0x7];
+ uint32_t module = (obj->pwm_name >> PWM_MODULE_SHIFT) & 0x3;
+ uint32_t pwmchannel = obj->pwm_name & 0x1;
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
/* Setup the PWM dutycycle */
@@ -193,7 +220,7 @@
base->SM[module].VAL5 = value;
}
/* Set the load okay bit */
- PWM_SetPwmLdok(base, module, true);
+ PWM_SetPwmLdok(base, (1 << module), true);
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -17,21 +17,26 @@
#if DEVICE_RTC
-#include "fsl_snvs_hp.h"
+#include "fsl_snvs_lp.h"
+
+static bool rtc_time_set = false;
void rtc_init(void)
{
- snvs_hp_rtc_config_t snvsRtcConfig;
+ snvs_lp_srtc_config_t snvsRtcConfig;
- SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig);
- SNVS_HP_RTC_Init(SNVS, &snvsRtcConfig);
+ SNVS_LP_SRTC_GetDefaultConfig(&snvsRtcConfig);
+ SNVS_LP_SRTC_Init(SNVS, &snvsRtcConfig);
- SNVS_HP_RTC_StartTimer(SNVS);
+ SNVS_LP_SRTC_StartTimer(SNVS);
}
void rtc_free(void)
{
- SNVS_HP_RTC_Deinit(SNVS);
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+ defined(SNVS_LP_CLOCKS))
+ CLOCK_DisableClock(kCLOCK_SnvsLp0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*
@@ -40,19 +45,31 @@
*/
int rtc_isenabled(void)
{
- return (int)((SNVS->HPCR & SNVS_HPCR_RTC_EN_MASK) >> SNVS_HPCR_RTC_EN_SHIFT);
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+ defined(SNVS_LP_CLOCKS))
+ CLOCK_EnableClock(kCLOCK_SnvsLp0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+
+ const bool rtc_init_done = ((SNVS->LPCR & SNVS_LPCR_SRTC_ENV_MASK) >> SNVS_LPCR_SRTC_ENV_SHIFT);
+
+ /* If RTC is not initialized, then disable the clock gate on exit. */
+ if(!rtc_init_done) {
+ rtc_free();
+ }
+
+ return (rtc_init_done & rtc_time_set);
}
time_t rtc_read(void)
{
- uint64_t seconds = 0;
- uint64_t tmp = 0;
+ uint32_t seconds = 0;
+ uint32_t tmp = 0;
/* Do consecutive reads until value is correct */
- do
- {
+ do {
seconds = tmp;
- tmp = SNVS->HPRTCLR;
+ tmp = (SNVS->LPSRTCMR << 17U) | (SNVS->LPSRTCLR >> 15U);
} while (tmp != seconds);
return (time_t)seconds;
@@ -63,11 +80,15 @@
if (t == 0) {
t = 1;
}
- SNVS_HP_RTC_StopTimer(SNVS);
+
+ SNVS_LP_SRTC_StopTimer(SNVS);
- SNVS->HPRTCLR = (uint32_t)t;
+ SNVS->LPSRTCMR = (uint32_t)(t >> 17U);
+ SNVS->LPSRTCLR = (uint32_t)(t << 15U);
- SNVS_HP_RTC_StartTimer(SNVS);
+ SNVS_LP_SRTC_StartTimer(SNVS);
+
+ rtc_time_set = true;
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -107,15 +107,9 @@
int spi_master_write(spi_t *obj, int value)
{
- lpspi_transfer_t masterXfer;
uint32_t rx_data;
- masterXfer.txData = (uint8_t *)&value;
- masterXfer.rxData = NULL;
- masterXfer.dataSize = 1;
- masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap;
-
- LPSPI_MasterTransferBlocking(spi_address[obj->instance], &masterXfer);
+ LPSPI_WriteData(spi_address[obj->instance], value);
// wait rx buffer full
while (!spi_readable(obj));
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -140,3 +140,8 @@
{
NVIC_SetPendingIRQ(PIT_IRQn);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -97,3 +97,11 @@
{
NVIC_SetPendingIRQ(CTIMER1_IRQn);
}
+
+void us_ticker_free(void)
+{
+ CTIMER_StopTimer(CTIMER1);
+ CTIMER1->MCR &= ~1;
+ NVIC_DisableIRQ(CTIMER1_IRQn);
+ us_ticker_inited = false;
+}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_GCC_ARM/LPC54114J256_cm4_flash.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_GCC_ARM/LPC54114J256_cm4_flash.ld Thu Nov 08 11:46:34 2018 +0000
@@ -106,32 +106,32 @@
/* section for storing the secondary core image */
.m0code :
{
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
KEEP (*(.m0code))
*(.m0code*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > m_core1_image
/* NOINIT section for rpmsg_sh_mem */
- .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(8)
{
*(.noinit.$rpmsg_sh_mem*)
- . = ALIGN(4) ;
+ . = ALIGN(8) ;
} > rpmsg_sh_mem
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -141,7 +141,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -219,12 +219,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -233,14 +233,14 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.ramfunc*) /* for functions in ram */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -252,13 +252,13 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -27,7 +27,7 @@ /* Defines used by the sleep code */ #define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M() #define LPC_CLOCK_RUN ((SYSCON->DEVICE_ID0 == 0xFFF54628) ? \ - BOARD_BootClockPLL220M() : BOARD_BootClockFROHF48M()) + BOARD_BootClockPLL220M() : BOARD_BootClockPLL180M()) #define DEVICE_ID_LENGTH 24
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -41,10 +41,12 @@
void mbed_sdk_init()
{
if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
+ BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
/* LPC54628 runs at a higher core speed */
BOARD_BootClockPLL220M();
} else {
- BOARD_BootClockFROHF48M();
+ BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
+ BOARD_BootClockPLL180M();
}
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -27,7 +27,7 @@ /* Defines used by the sleep code */ #define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M() #define LPC_CLOCK_RUN ((SYSCON->DEVICE_ID0 == 0xFFF54628) ? \ - BOARD_BootClockPLL220M() : BOARD_BootClockFROHF48M()) + BOARD_BootClockPLL220M() : BOARD_BootClockPLL180M()) #define DEVICE_ID_LENGTH 24
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -57,10 +57,12 @@
void mbed_sdk_init()
{
if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
+ BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
/* LPC54628 runs at a higher core speed */
BOARD_BootClockPLL220M();
} else {
- BOARD_BootClockFROHF48M();
+ BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
+ BOARD_BootClockPLL180M();
}
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld Thu Nov 08 11:46:34 2018 +0000
@@ -73,15 +73,15 @@
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
/* The program code and other data goes into internal flash */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -91,7 +91,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -169,12 +169,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
@@ -183,14 +183,14 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.ramfunc*) /* for functions in ram */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -202,13 +202,13 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -52,14 +52,38 @@
#define PWM_SHIFT 8
typedef enum {
- PWM_1 = (0 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 0 PWMA
- PWM_2 = (0 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 0 PWMB
- PWM_3 = (0 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 1 PWMA
- PWM_4 = (0 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 1 PWMB
- PWM_5 = (0 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 2 PWMA
- PWM_6 = (0 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 2 PWMB
- PWM_7 = (0 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 3 PWMA
- PWM_8 = (0 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 3 PWMB
+ PWM_1 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 0 PWMA
+ PWM_2 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 0 PWMB
+ PWM_3 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 1 PWMA
+ PWM_4 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 1 PWMB
+ PWM_5 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 2 PWMA
+ PWM_6 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 2 PWMB
+ PWM_7 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 3 PWMA
+ PWM_8 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 3 PWMB
+ PWM_9 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 0 PWMA
+ PWM_10 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 0 PWMB
+ PWM_11 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 1 PWMA
+ PWM_12 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 1 PWMB
+ PWM_13 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 2 PWMA
+ PWM_14 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 2 PWMB
+ PWM_15 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 3 PWMA
+ PWM_16 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 3 PWMB
+ PWM_17 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 0 PWMA
+ PWM_18 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 0 PWMB
+ PWM_19 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 1 PWMA
+ PWM_20 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 1 PWMB
+ PWM_21 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 2 PWMA
+ PWM_22 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 2 PWMB
+ PWM_23 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 3 PWMA
+ PWM_24 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 3 PWMB
+ PWM_25 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 0 PWMA
+ PWM_26 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 0 PWMB
+ PWM_27 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 1 PWMA
+ PWM_28 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 1 PWMB
+ PWM_29 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 2 PWMA
+ PWM_30 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 2 PWMB
+ PWM_31 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 3 PWMA
+ PWM_32 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1) // PWM4 Submodule 3 PWMB
} PWMName;
#define ADC_INSTANCE_SHIFT 8
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -88,6 +88,9 @@
const PinMap PinMap_PWM[] = {
{GPIO_AD_B0_10, PWM_7, ((3U << DAISY_REG_VALUE_SHIFT) | (0x454 << DAISY_REG_SHIFT) | 1)},
{GPIO_AD_B0_11, PWM_8, ((3U << DAISY_REG_VALUE_SHIFT) | (0x464 << DAISY_REG_SHIFT) | 1)},
+ {GPIO_AD_B1_08, PWM_25, ((1U << DAISY_REG_VALUE_SHIFT) | (0x494 << DAISY_REG_SHIFT) | 1)},
+ {GPIO_SD_B0_00, PWM_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x458 << DAISY_REG_SHIFT) | 1)},
+ {GPIO_SD_B0_01, PWM_2, ((1U << DAISY_REG_VALUE_SHIFT) | (0x468 << DAISY_REG_SHIFT) | 1)},
{NC , NC , 0}
};
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -196,9 +196,6 @@
D14 = GPIO_AD_B0_01,
D15 = GPIO_AD_B0_00,
- I2C_SCL = D15,
- I2C_SDA = D14,
-
A0 = GPIO_AD_B1_10,
A1 = GPIO_AD_B1_11,
A2 = GPIO_AD_B1_04,
@@ -206,6 +203,9 @@
A4 = GPIO_AD_B1_01,
A5 = GPIO_AD_B1_00,
+ I2C_SCL = A5,
+ I2C_SDA = A4,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -16,6 +16,7 @@
#include "pinmap.h"
#include "fsl_clock_config.h"
#include "fsl_clock.h"
+#include "fsl_xbara.h"
#include "lpm.h"
#define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
@@ -217,9 +218,35 @@
return ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U));
}
-void pwm_setup_clock()
+void pwm_setup(uint32_t instance)
{
- /* Use default settings */
+ /* Use default clock settings */
+ /* Set the PWM Fault inputs to a low value */
+ XBARA_Init(XBARA1);
+
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault2);
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault3);
+
+ switch (instance) {
+ case 1:
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault0);
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault1);
+ break;
+ case 2:
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault0);
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault1);
+ break;
+ case 3:
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault0);
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault1);
+ break;
+ case 4:
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault0);
+ XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault1);
+ break;
+ default:
+ break;
+ }
}
uint32_t pwm_get_clock()
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,36 +84,36 @@
{
.flash_config :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__FLASH_BASE = .;
KEEP(* (.boot_hdr.conf)) /* flash config section */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_flash_config
ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config);
.ivt : AT(ivt_begin)
{
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_ivt
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
- . = ALIGN(4);
+ . = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_interrupts
/* The program code and other data goes into internal RAM */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
@@ -123,7 +123,7 @@
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
- . = ALIGN(4);
+ . = ALIGN(8);
} > m_text
.ARM.extab :
@@ -201,12 +201,12 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data2
@@ -215,14 +215,14 @@
.data : AT(__DATA_ROM)
{
- . = ALIGN(4);
+ . = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
@@ -245,14 +245,14 @@
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
- . = ALIGN(4);
+ . = ALIGN(8);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_ncache
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
- . = ALIGN(4);
+ . = ALIGN(8);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_ncache
@@ -264,14 +264,14 @@
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
+ . = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct Thu Nov 08 11:46:34 2018 +0000
@@ -7,7 +7,6 @@
.ANY (*)
}
- ; no uvisor support at this time
RW_IRAM1 0x3FFF4000 + 0x90 { ; 8_byte_aligned(35 vectors * 4 bytes each) = 0x90
.ANY(+RW +ZI)
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld Thu Nov 08 11:46:34 2018 +0000
@@ -53,40 +53,12 @@
{
__vector_table = .;
KEEP(*(.vector_table))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > RAM
.text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -132,20 +104,20 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -158,39 +130,6 @@
} >RAM AT>FLASH
- /* uvisor configuration data */
-.uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assetions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
.uninitialized (NOLOAD):
{
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S Thu Nov 08 11:46:34 2018 +0000 @@ -146,11 +146,6 @@ ldr r0, =SystemInit blx r0 -/* TODO - Uncomment when uvisor support is added */ -/* - ldr r0, =uvisor_init - blx r0 -*/ ldr r0, =_start bx r0 .pool
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -203,3 +203,8 @@
// we set the full reminder of 16 bit, the next ISR will do the upper part
ticker_set(delta & 0xFFFF);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -246,10 +246,11 @@
{P7_9 , PWM_TIOC1A, 6},
{P9_2 , PWM_TIOC1A, 5}, /* for 208QFP */
{P2_7 , PWM_TIOC1A, 3},
- {P5_14 , PWM_TIOC2A, 4},
- {P7_0 , PWM_TIOC2A, 5},
- {P9_4 , PWM_TIOC2A, 5}, /* for 208QFP */
- {P2_6 , PWM_TIOC2A, 3},
+ {P6_7 , PWM_TIOC3A, 5},
+ {P2_5 , PWM_TIOC3A, 3},
+ {P3_11 , PWM_TIOC3A, 3},
+ {P6_9 , PWM_TIOC3C, 5},
+ {P3_12 , PWM_TIOC3C, 3},
{P5_8 , PWM_TIOC4A, 3},
{P2_4 , PWM_TIOC4A, 3},
{P5_10 , PWM_TIOC4C, 3},
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct Thu Nov 08 11:46:34 2018 +0000
@@ -7,7 +7,21 @@
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
-#include "mem_RZ_A1LU.h"
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00300000
+#define __NC_RAM_SIZE 0x00100000
+#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+#define __TTB_BASE 0x20000000
+#define __TTB_SIZE 0x00004000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x18000000
@@ -52,7 +66,7 @@
RAM_CODE 0x20020000
{ * (RAM_CODE) } ; Application RAM_CODE
- RW_DATA +0 ALIGN 0x4
+ RW_DATA +0 ALIGN 0x8
{ * (+RW) } ; Application RW data (.data)
RW_IRAM1 +0 ALIGN 0x10
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/RZA1LU.ld Thu Nov 08 11:46:34 2018 +0000
@@ -117,7 +117,7 @@
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -133,7 +133,7 @@
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -142,7 +142,7 @@
__zero_table_end__ = .;
} > SFLASH
- .ram_code : ALIGN( 0x4 ) {
+ .ram_code : ALIGN( 0x8 ) {
__ram_code_load = .;
__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
@@ -150,7 +150,7 @@
*(RAM_CONST)
- . = ALIGN( 0x4 );
+ . = ALIGN( 0x8 );
__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
} > RAM AT > SFLASH
@@ -175,13 +175,13 @@
*(.data*)
Image$$RW_DATA$$Limit = .;
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -189,14 +189,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -245,7 +245,7 @@
__nc_data_start = .;
*(NC_DATA)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_data_end = .;
Image$$RW_DATA_NC$$Limit = .;
} > RAM_NC
@@ -256,7 +256,7 @@
__nc_bss_start = .;
*(NC_BSS)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c Thu Nov 08 11:46:34 2018 +0000
@@ -194,7 +194,7 @@
// Get Cortex-A9 OS Timer interrupt number
IRQn_ID_t mbed_get_a9_tick_irqn(){
- return OSTMI0TINT_IRQn;
+ return OSTM_IRQn;
}
#endif
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h Thu Nov 08 11:46:34 2018 +0000 @@ -34,7 +34,7 @@ #define RENESAS_RZ_A1_P0_CLK CM1_RENESAS_RZ_A1_P0_CLK -#define LP_TICKER_MTU2_CH 3 +#define LP_TICKER_MTU2_CH 2 /* flash (W25Q64JV) */ #define FLASH_BASE (0x18000000UL) /**< Flash Base Address */
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct Thu Nov 08 11:46:34 2018 +0000
@@ -7,7 +7,21 @@
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
-#include "mem_RZ_A1H.h"
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00A00000
+#define __NC_RAM_SIZE 0x00100000
+#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+#define __TTB_BASE 0x20000000
+#define __TTB_SIZE 0x00004000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x18000000
@@ -52,7 +66,7 @@
RAM_CODE 0x20020000
{ * (RAM_CODE) } ; Application RAM_CODE
- RW_DATA +0 ALIGN 0x4
+ RW_DATA +0 ALIGN 0x8
{ * (+RW) } ; Application RW data (.data)
RW_IRAM1 +0 ALIGN 0x10
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld Thu Nov 08 11:46:34 2018 +0000
@@ -117,7 +117,7 @@
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -133,7 +133,7 @@
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -142,7 +142,7 @@
__zero_table_end__ = .;
} > SFLASH
- .ram_code : ALIGN( 0x4 ) {
+ .ram_code : ALIGN( 0x8 ) {
__ram_code_load = .;
__ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
@@ -150,7 +150,7 @@
*(RAM_CONST)
- . = ALIGN( 0x4 );
+ . = ALIGN( 0x8 );
__ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
} > RAM AT > SFLASH
@@ -175,13 +175,13 @@
*(.data*)
Image$$RW_DATA$$Limit = .;
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -189,14 +189,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -245,7 +245,7 @@
__nc_data_start = .;
*(NC_DATA)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_data_end = .;
Image$$RW_DATA_NC$$Limit = .;
} > RAM_NC
@@ -256,7 +256,7 @@
__nc_bss_start = .;
*(NC_BSS)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c Thu Nov 08 11:46:34 2018 +0000
@@ -195,7 +195,7 @@
// Get Cortex-A9 OS Timer interrupt number
IRQn_ID_t mbed_get_a9_tick_irqn(){
- return OSTMI0TINT_IRQn;
+ return OSTM_IRQn;
}
#endif
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct Thu Nov 08 11:46:34 2018 +0000
@@ -8,7 +8,45 @@
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
#include "mbed_config.h"
-#include "mem_VK_RZ_A1H.h"
+
+#ifdef RUN_FROM_SDRAM
+ #define __ROM_BASE 0x08000000
+ #define __ROM_SIZE 0x02000000
+ #define __VECTOR_BASE 0x08000000
+ #define __DATA_BASE +0 ALIGN 0x100000
+#elif defined (RUN_FROM_SRAM)
+ #define __ROM_BASE 0x200A0000
+ #define __ROM_SIZE 0x00960000
+ #define __VECTOR_BASE 0x200A0000
+ #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS
+#else
+ #define __ROM_BASE 0x18020000
+ #define __ROM_SIZE 0x01FE0000
+ #define __VECTOR_BASE 0x18020000
+ #define __DATA_BASE 0x20020000
+#endif
+
+#ifdef RUN_FROM_SDRAM
+#define __RAM_BASE 0x08000000
+#define __RAM_SIZE 0x02000000
+#define __NC_RAM_SIZE 0x00200000
+#else
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00A00000
+#define __NC_RAM_SIZE 0x00100000
+#endif
+#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+#define __TTB_BASE 0x20000000
+#define __TTB_SIZE 0x00004000
LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld Thu Nov 08 11:46:34 2018 +0000
@@ -114,7 +114,7 @@
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -127,7 +127,7 @@
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -153,13 +153,13 @@
*(.data*)
Image$$RW_DATA$$Limit = .;
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -167,14 +167,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -223,7 +223,7 @@
__nc_data_start = .;
*(NC_DATA)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_data_end = .;
Image$$RW_DATA_NC$$Limit = .;
} > RAM_NC
@@ -234,7 +234,7 @@
__nc_bss_start = .;
*(NC_BSS)
- . = ALIGN(4);
+ . = ALIGN(8);
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,14 +18,22 @@
#include "mbed_critical.h"
#if DEVICE_FLASH
+#include <string.h>
#include "iodefine.h"
#include "spibsc_iobitmask.h"
#include "spibsc.h"
#include "mbed_drv_cfg.h"
/* ---- serial flash command ---- */
+#if (FLASH_SIZE > 0x1000000)
+#define SPIBSC_OUTPUT_ADDR SPIBSC_OUTPUT_ADDR_32
+#define SFLASHCMD_SECTOR_ERASE (0x21u) /* SE4B 4-byte address(1bit) */
+#define SFLASHCMD_PAGE_PROGRAM (0x12u) /* PP4B 4-byte address(1bit), data(1bit) */
+#else
+#define SPIBSC_OUTPUT_ADDR SPIBSC_OUTPUT_ADDR_24
#define SFLASHCMD_SECTOR_ERASE (0x20u) /* SE 3-byte address(1bit) */
#define SFLASHCMD_PAGE_PROGRAM (0x02u) /* PP 3-byte address(1bit), data(1bit) */
+#endif
#define SFLASHCMD_READ_STATUS_REG (0x05u) /* RDSR data(1bit) */
#define SFLASHCMD_WRITE_ENABLE (0x06u) /* WREN */
/* ---- serial flash register definitions ---- */
@@ -74,10 +82,6 @@
uint32_t smwdr[2]; /* write data */
} st_spibsc_spimd_reg_t;
-/* SPI Multi-I/O bus address space address definitions */
-#define SPIBSC_ADDR_START (0x18000000uL)
-#define SPIBSC_ADDR_END (0x1BFFFFFFuL)
-
typedef struct {
uint32_t b0 : 1 ; /* bit 0 : - (0) */
uint32_t b1 : 1 ; /* bit 1 : - (1) */
@@ -96,9 +100,10 @@
uint32_t base_addr : 12; /* bit 31-20 : PA[31:20] PA(physical address) bits:bit31-20 */
} mmu_ttbl_desc_section_t;
-static mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
+static mmu_ttbl_desc_section_t desc_tbl[(FLASH_SIZE >> 20)];
static volatile struct st_spibsc* SPIBSC = &SPIBSC0;
static st_spibsc_spimd_reg_t spimd_reg;
+static uint8_t write_tmp_buf[FLASH_PAGE_SIZE];
#if defined(__ICCARM__)
#define RAM_CODE_SEC __ramfunc
@@ -136,24 +141,12 @@
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
- int32_t ret;
-
- core_util_critical_section_enter();
- ret = _sector_erase(address - FLASH_BASE);
- core_util_critical_section_exit();
-
- return ret;
+ return _sector_erase(address - FLASH_BASE);
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
- int32_t ret;
-
- core_util_critical_section_enter();
- ret = _page_program(address - FLASH_BASE, data, size);
- core_util_critical_section_exit();
-
- return ret;
+ return _page_program(address - FLASH_BASE, data, size);
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
@@ -167,7 +160,7 @@
uint32_t flash_get_page_size(const flash_t *obj)
{
- return 1;
+ return 8;
}
uint32_t flash_get_start_address(const flash_t *obj)
@@ -184,12 +177,14 @@
{
int32_t ret;
+ core_util_critical_section_enter();
spi_mode();
/* ---- Write enable ---- */
ret = write_enable(); /* WREN Command */
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
@@ -202,7 +197,7 @@
spimd_reg.cmd = SFLASHCMD_SECTOR_ERASE;
/* ---- address ---- */
- spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
+ spimd_reg.ade = SPIBSC_OUTPUT_ADDR;
spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
spimd_reg.adb = SPIBSC_1BIT;
spimd_reg.addr = addr;
@@ -210,12 +205,14 @@
ret = spibsc_transfer(&spimd_reg);
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
ret = busy_wait();
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
@@ -226,8 +223,6 @@
int32_t remainder;
int32_t idx = 0;
- spi_mode();
-
while (size > 0) {
if (size > FLASH_PAGE_SIZE) {
program_size = FLASH_PAGE_SIZE;
@@ -239,10 +234,15 @@
program_size = remainder;
}
+ core_util_critical_section_enter();
+ memcpy(write_tmp_buf, &buf[idx], program_size);
+ spi_mode();
+
/* ---- Write enable ---- */
ret = write_enable(); /* WREN Command */
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
@@ -256,7 +256,7 @@
spimd_reg.cmd = SFLASHCMD_PAGE_PROGRAM;
/* ---- address ---- */
- spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
+ spimd_reg.ade = SPIBSC_OUTPUT_ADDR;
spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
spimd_reg.adb = SPIBSC_1BIT;
spimd_reg.addr = addr;
@@ -267,28 +267,33 @@
ret = spibsc_transfer(&spimd_reg); /* Command,Address */
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
/* ----------- 2. Data ---------------*/
- ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, &buf[idx], program_size);
+ ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, write_tmp_buf, program_size);
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
ret = busy_wait();
if (ret != 0) {
ex_mode();
+ core_util_critical_section_exit();
return ret;
}
+ ex_mode();
+ core_util_critical_section_exit();
+
addr += program_size;
idx += program_size;
size -= program_size;
}
- ex_mode();
return ret;
}
@@ -686,16 +691,16 @@
mmu_ttbl_desc_section_t * table = (mmu_ttbl_desc_section_t *)TTB;
/* ==== Modify SPI Multi-I/O bus space settings in the MMU translation table ==== */
- for (index = (SPIBSC_ADDR_START >> 20); index <= (SPIBSC_ADDR_END >> 20); index++) {
+ for (index = (FLASH_BASE >> 20); index < ((FLASH_BASE + FLASH_SIZE) >> 20); index++) {
/* Modify memory attribute descriptor */
if (type == 0) { /* Spi */
desc = table[index];
- desc_tbl[index - (SPIBSC_ADDR_START >> 20)] = desc;
+ desc_tbl[index - (FLASH_BASE >> 20)] = desc;
desc.AP1_0 = 0x0u; /* AP[2:0] = b'000 (No access) */
desc.AP2 = 0x0u;
desc.XN = 0x1u; /* XN = 1 (Execute never) */
} else { /* Xip */
- desc = desc_tbl[index - (SPIBSC_ADDR_START >> 20)];
+ desc = desc_tbl[index - (FLASH_BASE >> 20)];
}
/* Write descriptor back to translation table */
table[index] = desc;
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -149,9 +149,11 @@
hz_min = pclk_base / 2 / 256 / 8;
hz_max = pclk_base / 2;
- if (((uint32_t)hz < hz_min) || ((uint32_t)hz > hz_max)) {
- error("Couldn't setup requested SPI frequency");
- return;
+ if ((uint32_t)hz < hz_min) {
+ hz = hz_min;
+ }
+ if ((uint32_t)hz > hz_max) {
+ hz = hz_max;
}
div = (pclk_base / hz / 2);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -38,8 +38,6 @@
#define MAX_SCAN_TIMEOUT (15000)
-static bool _inited = false;
-
static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result )
{
wifi_scan_hdl *scan_handler = (wifi_scan_hdl *)malloced_scan_result->user_data;
@@ -88,14 +86,9 @@
}
RTWInterface::RTWInterface(RTW_EMAC &get_rtw_emac, OnboardNetworkStack &get_rtw_obn_stack) :
+ EMACInterface(get_rtw_emac, get_rtw_obn_stack),
rtw_emac(get_rtw_emac),
- rtw_obn_stack(get_rtw_obn_stack),
- rtw_interface(NULL),
- _dhcp(true),
- _ip_address(),
- _netmask(),
- _gateway(),
- _mac_address()
+ rtw_obn_stack(get_rtw_obn_stack)
{
rtw_emac.power_up();
}
@@ -103,22 +96,7 @@
RTWInterface::~RTWInterface()
{
rtw_emac.wlan_emac_link_change(false);
- rtw_interface->bringdown();
-}
-
-nsapi_error_t RTWInterface::set_network(const char *ip_address, const char *netmask, const char *gateway)
-{
- _dhcp = false;
- strncpy(_ip_address, ip_address ? ip_address : "", sizeof(_ip_address));
- strncpy(_netmask, netmask ? netmask : "", sizeof(_netmask));
- strncpy(_gateway, gateway ? gateway : "", sizeof(_gateway));
- return NSAPI_ERROR_OK;
-}
-
-nsapi_error_t RTWInterface::set_dhcp(bool dhcp)
-{
- _dhcp = dhcp;
- return NSAPI_ERROR_OK;
+ EMACInterface::disconnect();
}
/*
@@ -190,20 +168,10 @@
}
rtw_emac.wlan_emac_link_change(true);
- if (!rtw_interface) {
- nsapi_error_t err = rtw_obn_stack.add_ethernet_interface(rtw_emac, true, &rtw_interface);
- if (err != NSAPI_ERROR_OK) {
- rtw_interface = NULL;
- return err;
- }
- }
- int rtw_if_bringup = rtw_interface->bringup(_dhcp,
- _ip_address[0] ? _ip_address : 0,
- _netmask[0] ? _netmask : 0,
- _gateway[0] ? _gateway : 0,
- DEFAULT_STACK);
- return rtw_if_bringup;
+ ret = EMACInterface::connect();
+
+ return ret;
}
nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count)
@@ -257,7 +225,9 @@
char essid[33];
rtw_emac.wlan_emac_link_change(false);
- rtw_interface->bringdown();
+
+ EMACInterface::disconnect();
+
if (wifi_is_connected_to_ap() != RTW_SUCCESS) {
return NSAPI_ERROR_NO_CONNECTION;
}
@@ -277,38 +247,6 @@
return !wifi_is_connected_to_ap();
}
-const char *RTWInterface::get_mac_address()
-{
- if (rtw_interface->get_mac_address(_mac_address, sizeof _mac_address)) {
- return _mac_address;
- }
- return 0;
-}
-
-const char *RTWInterface::get_ip_address()
-{
- if (rtw_interface->get_ip_address(_ip_address, sizeof _ip_address)) {
- return _ip_address;
- }
- return 0;
-}
-
-const char *RTWInterface::get_netmask()
-{
- if (rtw_interface->get_netmask(_netmask, sizeof _netmask)) {
- return _netmask;
- }
- return 0;
-}
-
-const char *RTWInterface::get_gateway()
-{
- if (rtw_interface->get_gateway(_gateway, sizeof _gateway)) {
- return _gateway;
- }
- return 0;
-}
-
NetworkStack *RTWInterface::get_stack()
{
return &rtw_obn_stack;
--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h Thu Nov 08 11:46:34 2018 +0000
@@ -24,6 +24,7 @@
#include "netif.h"
#include "rtw_emac.h"
#include "OnboardNetworkStack.h"
+#include "EMACInterface.h"
#include "LWIPStack.h"
// Forward declaration
@@ -32,7 +33,7 @@
/** Realtek Wlan (RTW) interface class
* Implementation of the NetworkStack for Ameba
*/
-class RTWInterface: public WiFiInterface
+class RTWInterface: public WiFiInterface, public EMACInterface
{
public:
/** RTWWlanInterface lifetime
@@ -43,28 +44,6 @@
~RTWInterface();
- /** Set a static IP address
- *
- * Configures this network interface to use a static IP address.
- * Implicitly disables DHCP, which can be enabled in set_dhcp.
- * Requires that the network is disconnected.
- *
- * @param address Null-terminated representation of the local IP address
- * @param netmask Null-terminated representation of the local network mask
- * @param gateway Null-terminated representation of the local gateway
- * @return 0 on success, negative error code on failure
- */
- virtual nsapi_error_t set_network(const char *ip_address, const char *netmask, const char *gateway);
-
- /** Enable or disable DHCP on the network
- *
- * Requires that the network is disconnected
- *
- * @param dhcp False to disable dhcp (defaults to enabled)
- * @return 0 on success, negative error code on failure
- */
- virtual nsapi_error_t set_dhcp(bool dhcp);
-
/** Set the WiFi network credentials
*
* @param ssid Name of the network to connect to
@@ -112,42 +91,10 @@
* @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error
* see @a nsapi_error
*/
- virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count);
-
- virtual nsapi_error_t set_channel(uint8_t channel);
- virtual int8_t get_rssi();
-
- /** Get the local MAC address
- *
- * Provided MAC address is intended for info or debug purposes and
- * may not be provided if the underlying network interface does not
- * provide a MAC address
- *
- * @return Null-terminated representation of the local MAC address
- * or null if no MAC address is available
- */
- virtual const char *get_mac_address();
+ virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count);
- /** Get the local IP address
- *
- * @return Null-terminated representation of the local IP address
- * or null if no IP address has been recieved
- */
- virtual const char *get_ip_address();
-
- /** Get the local network mask
- *
- * @return Null-terminated representation of the local network mask
- * or null if no network mask has been recieved
- */
- virtual const char *get_netmask();
-
- /** Get the local gateways
- *
- * @return Null-terminated representation of the local gateway
- * or null if no network mask has been recieved
- */
- virtual const char *get_gateway();
+ virtual nsapi_error_t set_channel(uint8_t channel);
+ virtual int8_t get_rssi();
RTW_EMAC &get_emac() const { return rtw_emac; }
@@ -161,15 +108,9 @@
virtual NetworkStack *get_stack();
RTW_EMAC &rtw_emac;
OnboardNetworkStack &rtw_obn_stack;
- OnboardNetworkStack::Interface *rtw_interface;
- bool _dhcp;
char _ssid[256];
char _pass[256];
nsapi_security_t _security;
uint8_t _channel;
- char _ip_address[IPADDR_STRLEN_MAX];
- char _netmask[NSAPI_IPv4_SIZE];
- char _gateway[NSAPI_IPv4_SIZE];
- char _mac_address[NSAPI_MAC_SIZE];
};
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -41,8 +41,11 @@
HAL_ADC_INIT_DAT HalADCInitDataTmp;
PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp;
/* To backup user config first */
-
+
+#if defined(CONFIG_MBED_ENABLED)
_memset(&(obj->HalADCInitData), 0, sizeof(HAL_ADC_INIT_DAT));
+#endif
+
_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT));
_memset(obj, 0x00, sizeof(analogin_t));
@@ -92,17 +95,13 @@
pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB;
/*To assign user callback pointers*/
- pSalADCMngtAdpt->pUserCB->pTXCB = pSalADCUserCBAdpt;
- pSalADCMngtAdpt->pUserCB->pTXCCB = (pSalADCUserCBAdpt+1);
- pSalADCMngtAdpt->pUserCB->pRXCB = (pSalADCUserCBAdpt+2);
- pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+3);
- pSalADCMngtAdpt->pUserCB->pRDREQCB = (pSalADCUserCBAdpt+4);
- pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+5);
- pSalADCMngtAdpt->pUserCB->pDMATXCB = (pSalADCUserCBAdpt+6);
- pSalADCMngtAdpt->pUserCB->pDMATXCCB = (pSalADCUserCBAdpt+7);
- pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+8);
- pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+9);
-
+
+ pSalADCMngtAdpt->pUserCB->pRXCB = pSalADCUserCBAdpt;
+ pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+1);
+ pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+2);
+ pSalADCMngtAdpt->pUserCB->pIDMARXCCB= (pSalADCUserCBAdpt+3);
+ pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+4);
+ pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+5);
/* Set ADC Device Number */
pSalADCHND->DevNum = adc_idx;
@@ -136,9 +135,13 @@
uint8_t AnaloginIdx = 0;
uint32_t AnalogDat = 0;
+#if defined(CONFIG_MBED_ENABLED)
//no auto-calibration implemented yet, uses hard coded calibrate
uint32_t Offset = 0x2980;
uint32_t AnalogDatFull = 0xAA00;
+#else
+ uint32_t AnalogDatFull = 0;
+#endif
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
@@ -152,7 +155,12 @@
AnalogDat = AnaloginTmp[(AnaloginIdx/2)];
AnalogDat = (AnalogDat & AnaloginDatMsk);
AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01))));
+
+#if defined(CONFIG_MBED_ENABLED)
AnalogDat -= Offset;
+#else
+ AnalogDatFull = 0xCE80;
+#endif
value = (float)(AnalogDat) / (float)(AnalogDatFull);
return (float)value;
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogout_api.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogout_api.c Thu Nov 08 11:46:34 2018 +0000 @@ -26,6 +26,8 @@ #define DAC_POSITIVE_FULL_SCALE 0x7E0 #define DAC_NEGATIVE_FULL_SCALE 0x820 +extern void HalDACPinMuxInit(void *Data); +extern void HalDACPinMuxDeInit(void *Data); /** \brief analogout_init:\n * to initialize DAC
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar has changed
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar has changed
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a has changed
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Thu Nov 08 11:46:34 2018 +0000
@@ -66,7 +66,7 @@
.text.sram1 :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*rtl8195a_crypto*.o (.text* .rodata*)
*mbedtls*.o (.text* .rodata*)
*libc.a: (.text* .rodata*)
@@ -77,7 +77,7 @@
.text.sram2 :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text*)
KEEP(*(.init))
@@ -107,7 +107,7 @@
.data.sram1 :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__sram_data_start__ = .;
*rtl8195a_crypto*.o (.data*)
*mbedtls*.o (.data*)
@@ -121,27 +121,27 @@
*(.data*)
*(.sdram.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
__sdram_data_end__ = .;
/* All data end */
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a has changed
Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a has changed
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h Thu Nov 08 11:46:34 2018 +0000 @@ -18,9 +18,7 @@ /* * Target Platform Selection */ -#define CONFIG_WITHOUT_MONITOR 1 - -#undef CONFIG_RTL8195A +#undef CONFIG_RTL8195A #define CONFIG_RTL8195A 1 #undef CONFIG_FPGA #undef CONFIG_RTL_SIM @@ -54,12 +52,21 @@ #undef CONFIG_IMAGE_AUTO_LOAD //#undef CONFIG_IMAGE_PAGE_LOAD //#define CONFIG_IMAGE_AUTO_LOAD 1 -#define CONFIG_BOOT_TO_UPGRADE_IMG2 1 + +#undef CONFIG_BOOT_TO_UPGRADE_IMG2 + #undef CONFIG_PERI_UPDATE_IMG #define CONFIG_BOOT_FROM_JTAG 1 #undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE #define CONFIG_KERNEL 1 + #define PLATFORM_FREERTOS 1 +#define CONFIG_MBED_ENABLED 1 +#if defined(CONFIG_MBED_ENABLED) +#undef PLATFORM_FREERTOS +#define PLATFORM_CMSIS_RTOS 1 +#endif + #undef PLATFORM_UCOSII #undef PLATFORM_ECOS #undef CONFIG_TASK_SCHEDUL_DIS @@ -73,7 +80,11 @@ #define CONFIG_WDG 1 #undef CONFIG_WDG_NON #define CONFIG_WDG_NORMAL 1 -#define CONFIG_GDMA_EN 0 + +#undef CONFIG_WDG_TEST +#define CONFIG_WDG_MODULE 1 +#define CONFIG_GDMA_EN 1 + #define CONFIG_GDMA_NORMAL 1 #undef CONFIG_GDMA_TEST #define CONFIG_GDMA_MODULE 1 @@ -85,6 +96,7 @@ #define CONFIG_GPIO_NORMAL 1 #undef CONFIG_GPIO_TEST #define CONFIG_GPIO_MODULE 1 + #if defined(CONFIG_INIC) || (CONFIG_SDIOD) #define CONFIG_SDIO_DEVICE_EN 1 #define CONFIG_SDIO_DEVICE_NORMAL 1 @@ -107,6 +119,10 @@ #define DWC_HOST_ONLY 1 #define CONFIG_USB_HOST_ONLY 1 #endif + +#undef CONFIG_SDIO_HOST_EN +#undef CONFIG_USB_EN + #define CONFIG_SPI_COM_EN 1 #define CONFIG_SPI_COM_NORMAL 1 #undef CONFIG_SPI_COM_TEST @@ -121,24 +137,31 @@ #define CONFIG_I2C_MODULE 1 #undef CONFIG_DEBUG_LOG_I2C_HAL #undef CONFIG_PCM_EN -#undef CONFIG_I2S_EN -#undef CONFIG_I2S_NORMAL +#define CONFIG_I2S_EN 1 +#define CONFIG_I2S_NORMAL 1 #undef CONFIG_I2S_TEST -#undef CONFIG_I2S_MODULE +#define CONFIG_I2S_MODULE 1 + #undef CONFIG_DEBUG_LOG_I2S_HAL #undef CONFIG_NFC_EN #undef CONFIG_NFC_NORMAL #undef CONFIG_NFC_TEST #undef CONFIG_NFC_MODULE + +// power saving enable #define CONFIG_SOC_PS_EN 1 #define CONFIG_SOC_PS_NORMAL 1 #undef CONFIG_SOC_PS_TEST -//#define CONFIG_SOC_PS_MODULE 1 +#define CONFIG_SOC_PS_MODULE 1 + #define CONFIG_CRYPTO_EN 1 #define CONFIG_CRYPTO_NORMAL 1 #undef CONFIG_CRYPTO_TEST #define CONFIG_CRYPTO_MODULE 1 -#define CONFIG_MII_EN 1 + +//#define CONFIG_MII_EN 1 +#undef CONFIG_MII_EN + #define CONFIG_PWM_EN 1 #define CONFIG_PWM_NORMAL 1 #undef CONFIG_PWM_TEST @@ -186,19 +209,13 @@ #define CONFIG_UART_LOG_HISTORY 1 #undef CONFIG_CONSOLE_NORMALL_MODE #define CONFIG_CONSOLE_VERIFY_MODE 1 -#undef CONFIG_DEBUG_LOG + +//#undef CONFIG_DEBUG_LOG +#define CONFIG_DEBUG_LOG 1 + #define CONFIG_DEBUG_ERR_MSG 1 #undef CONFIG_DEBUG_WARN_MSG #undef CONFIG_DEBUG_INFO_MSG - -/* - * < SDK Option Config - */ -//#undef CONFIG_MBED_ENABLED -#ifdef CONFIG_MBED_ENABLED -#undef PLATFORM_FREERTOS -#define PLATFORM_CMSIS_RTOS 1 -#endif #undef CONFIG_APP_DEMO /*
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_opts.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_opts.h Thu Nov 08 11:46:34 2018 +0000 @@ -37,8 +37,9 @@ #define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode #define CONFIG_LOG_SERVICE_LOCK 0 -#define CONFIG_LOG_USE_HS_UART 0 //command/log via highspeed uart -#define CONFIG_LOG_USE_I2C 0 //command/log via I2C +#define CONFIG_ATCMD_MP 0 //support MP AT command +#define USE_MODE 1 //for test + #endif /** @@ -65,6 +66,7 @@ */ #define AP_SETTING_SECTOR 0x000FE000 #define UART_SETTING_SECTOR 0x000FC000 +#define SPI_SETTING_SECTOR 0x000FC000 #define FAST_RECONNECT_DATA (0x80000 - 0x1000) /** @@ -75,6 +77,8 @@ #define CONFIG_LWIP_LAYER 1 #define CONFIG_INIT_NET 1 //init lwip layer when start up #define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread +#define CONFIG_ENABLE_AP_POLLING_CLIENT_ALIVE 1 // on or off AP POLLING CLIENT + //on/off relative commands in log service #define CONFIG_SSL_CLIENT 0 @@ -95,6 +99,11 @@ /* For WPS and P2P */ #define CONFIG_ENABLE_WPS 0 #define CONFIG_ENABLE_P2P 0 + +#if CONFIG_ENABLE_WPS +#define CONFIG_ENABLE_WPS_DISCOVERY 1 +#endif + #if CONFIG_ENABLE_P2P #define CONFIG_ENABLE_WPS_AP 1 #undef CONFIG_WIFI_IND_USE_THREAD @@ -104,6 +113,17 @@ #error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1" #endif +/* For SSL/TLS */ +#define CONFIG_USE_POLARSSL 0 +#define CONFIG_USE_MBEDTLS 1 +#if ((CONFIG_USE_POLARSSL == 0) && (CONFIG_USE_MBEDTLS == 0)) || ((CONFIG_USE_POLARSSL == 1) && (CONFIG_USE_MBEDTLS == 1)) +#undef CONFIG_USE_POLARSSL +#define CONFIG_USE_POLARSSL 1 +#undef CONFIG_USE_MBEDTLS +#define CONFIG_USE_MBEDTLS 0 + +#endif + /* For Simple Link */ #define CONFIG_INCLUDE_SIMPLE_CONFIG 1 @@ -125,6 +145,9 @@ #endif //end of #if CONFIG_WLAN /*******************************************************************************/ +/* For LWIP configuration */ +#define CONFIG_LWIP_DHCP_COARSE_TIMER 60 + /** * For Ethernet configurations */ @@ -166,6 +189,10 @@ #endif /******************End of iNIC configurations*******************/ + +/* for CoAP example*/ +#define CONFIG_EXAMPLE_COAP 0 + /* For aj_basic_example */ #define CONFIG_EXAMPLE_AJ_BASIC 0 @@ -214,6 +241,12 @@ /* For http download example */ #define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0 +/* For httpc example */ +#define CONFIG_EXAMPLE_HTTPC 0 + +/* For httpd example */ +#define CONFIG_EXAMPLE_HTTPD 0 + /* For tcp keepalive example */ #define CONFIG_EXAMPLE_TCP_KEEPALIVE 0 @@ -232,6 +265,96 @@ #define FATFS_DISK_SD 1 #define CONFIG_EXAMPLE_CODEC_SGTL5000 1 #endif +/* For audio mp3 pcm example */ +#define CONFIG_EXAMPLE_AUDIO_MP3 0 +#if CONFIG_EXAMPLE_AUDIO_MP3 +#define FATFS_DISK_SD 1 +#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 1 +#endif + +/* For audio m4a example */ +#define CONFIG_EXAMPLE_AUDIO_M4A 0 +#if CONFIG_EXAMPLE_AUDIO_M4A +#define CONFIG_EXAMPLE_M4A_FROM_HTTP 1 // 1: From HTTP, 0: From SDCARD +#define FATFS_DISK_SD 1 +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#undef SUPPORT_MP_MODE +#define SUPPORT_MP_MODE 0 +#if (CONFIG_EXAMPLE_M4A_FROM_HTTP == 0) +#undef CONFIG_WLAN +#define CONFIG_WLAN 0 +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT +#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 +#undef SUPPORT_LOG_SERVICE +#define SUPPORT_LOG_SERVICE 0 +#else +#undef FAST_RECONNECT_DATA +#define FAST_RECONNECT_DATA (0x200000-0x1000) +#endif +#endif + +/* For audio m4a example */ +#define CONFIG_EXAMPLE_AUDIO_M4A_SELFPARSE 0 +#if CONFIG_EXAMPLE_AUDIO_M4A_SELFPARSE +#define FATFS_DISK_SD 1 +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMP LE_CONFIG 0 +#undef SUPPORT_MP_MODE +#define SUPPORT_MP_MODE 0 +#undef CONFIG_WLAN +#define CONFIG_WLAN 0 +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT +#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 +#undef SUPPORT_LOG_SERVICE +#define SUPPORT_LOG_SERVICE 0 +#endif + +/* For m4a,mp3 combined example */ +#define CONFIG_EXAMPLE_AUDIO_M4A_MP3 0 +#if CONFIG_EXAMPLE_AUDIO_M4A_MP3 +#define FATFS_DISK_SD 1 +#undef CONFIG_WLAN +#define CONFIG_WLAN 0 +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT +#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#undef SUPPORT_LOG_SERVICE +#define SUPPORT_LOG_SERVICE 0 +#undef SUPPORT_MP_MODE +#define SUPPORT_MP_MODE 0 +#endif + +/* For audio amr example */ +#define CONFIG_EXAMPLE_AUDIO_AMR 0 +#if CONFIG_EXAMPLE_AUDIO_AMR +#define FATFS_DISK_SD 1 +#undef CONFIG_WLAN +#define CONFIG_WLAN 0 +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT +#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#endif + +/* For audio HLS example */ +#define CONFIG_EXAMPLE_AUDIO_HLS 0 +#if CONFIG_EXAMPLE_AUDIO_HLS +#define FATFS_DISK_SD 1 +#undef FAST_RECONNECT_DATA +#define FAST_RECONNECT_DATA (0x200000-0x1000) +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#undef SUPPORT_MP_MODE +#define SUPPORT_MP_MODE 0 +#endif + +/*Foe alc audio dsp firmware upgrade */ +#define CONFIG_EXAMPLE_ALC_DSP_FW_UPGRADE 0 + +/*Foe audio pcm upload */ +#define CONFIG_EXAMPLE_AUDIO_PCM_UPLOAD 0 /* For UART Module AT command example */ #define CONFIG_EXAMPLE_UART_ATCMD 0 @@ -250,15 +373,50 @@ #define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 #endif +/* For SPI Module AT command example */ +#define CONFIG_EXAMPLE_SPI_ATCMD 0 + +#if CONFIG_EXAMPLE_SPI_ATCMD +#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED +#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1 +#undef CONFIG_OTA_UPDATE +#define CONFIG_OTA_UPDATE 1 +#undef CONFIG_TRANSPORT +#define CONFIG_TRANSPORT 1 +#undef LOG_SERVICE_BUFLEN +#define LOG_SERVICE_BUFLEN 1600 +#undef CONFIG_LOG_SERVICE_LOCK +#define CONFIG_LOG_SERVICE_LOCK 1 +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT +#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 +#endif #define CONFIG_EXAMPLE_MEDIA_SS 0 -#define CONFIG_EXAMPLE_MEDIA_MS 0 +#define CONFIG_EXAMPLE_MEDIA_MS 0 #define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 0 + +//Defines for mp3 streaming over wifi, default output through alc5651 +#define CONFIG_EXAMPLE_MP3_STREAM_RTP 0 + +#if CONFIG_EXAMPLE_MP3_STREAM_RTP +#undef CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP +#define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 1 +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +//Set this flag to 1 in case sgtl5000 to be used else alc5651 will be used +#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 0 +#endif + // Use media source/sink example -#if (CONFIG_EXAMPLE_MEDIA_SS==1) || (CONFIG_EXAMPLE_MEDIA_MS==1) + +#if (CONFIG_EXAMPLE_MEDIA_SS==1) || (CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP) + #undef CONFIG_INCLUDE_SIMPLE_CONFIG #define CONFIG_INCLUDE_SIMPLE_CONFIG 0 #define CONFIG_ENABLE_WPS 0 -#endif +#endif + +/* For ISP AT COMMAND config*/ +#define CONFIG_ISP 0 /* For Mjpeg capture example*/ #define CONFIG_EXAMPLE_MJPEG_CAPTURE 0 @@ -266,6 +424,17 @@ #define FATFS_DISK_SD 1 #endif +/* For DCT example*/ +#define CONFIG_EXAMPLE_DCT 0 + +/* For audio flash mp3 pcm example */ +#define CONFIG_EXAMPLE_FLASH_MP3 0 +#if CONFIG_EXAMPLE_FLASH_MP3 +#define FATFS_DISK_FLASH 1 +#define CONFIG_EXAMPLE_MP3_STREAM_SGTL5000 1 + +#endif + /****************** For EAP method example *******************/ #define CONFIG_EXAMPLE_EAP 0 @@ -279,6 +448,9 @@ #if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS #define CONFIG_ENABLE_EAP + +#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT + #define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0 #endif @@ -292,6 +464,11 @@ /* For usb mass storage example */ #define CONFIG_EXAMPLE_USB_MASS_STORAGE 0 +/* For vendor specific example */ +#define CONFIG_EXAMPLE_USB_VENDOR_SPECIFIC 0 + +#define CONFIG_EXAMPLE_USB_ISOC_DEVICE 0 + /* For FATFS example*/ #define CONFIG_EXAMPLE_FATFS 0 #if CONFIG_EXAMPLE_FATFS @@ -300,8 +477,9 @@ // fatfs version #define FATFS_R_10C // fatfs disk interface -#define FATFS_DISK_USB 0 -#define FATFS_DISK_SD 1 +#define FATFS_DISK_USB 0 +#define FATFS_DISK_SD 1 +#define FATFS_DISK_FLASH 0 #endif #endif @@ -380,7 +558,42 @@ /* For ssl server example */ #define CONFIG_EXAMPLE_SSL_SERVER 0 +/*For timelapse example */ +#define CONFIG_EXAMPLE_TIMELAPSE 0 +#if CONFIG_EXAMPLE_TIMELAPSE +#define CONFIG_USE_HTTP_SERVER 0 +#if CONFIG_USE_HTTP_SERVER +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#define CONFIG_ENABLE_WPS 0 +#else +#undef CONFIG_INCLUDE_SIMPLE_CONFIG +#define CONFIG_INCLUDE_SIMPLE_CONFIG 0 +#define CONFIG_ENABLE_WPS 0 +#define CONFIG_FATFS_EN 1 +#define FATFS_R_10C +#define FATFS_DISK_SD 1 +#endif +#endif + /* For ota update http example */ #define CONFIG_EXAMPLE_OTA_HTTP 0 +/* For Amazon AWS IoT example */ +#define CONFIG_EXAMPLE_AMAZON_AWS_IOT 0 +#define CONFIG_EXAMPLE_AMAZON_ALEXA 0 + +/*For wifi roaming example*/ +#define CONFIG_EXAMPLE_WIFI_ROAMING 0 +#if CONFIG_QQ_LINK +#define FATFS_R_10C +#define FATFS_DISK_USB 0 +#define FATFS_DISK_SD 1 #endif +#if CONFIG_ENABLE_WPS +#define WPS_CONNECT_RETRY_COUNT 4 +#define WPS_CONNECT_RETRY_INTERVAL 5000 // in ms +#endif +#define AUTO_RECONNECT_COUNT 8 +#define AUTO_RECONNECT_INTERVAL 5 // in sec +#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Thu Nov 08 11:46:34 2018 +0000
@@ -14,6 +14,8 @@
* limitations under the License.
*/
#include "rtl8195a.h"
+#include "basic_types.h"
+#include "hal_common.h"
#if defined(__CC_ARM) || \
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
@@ -67,15 +69,20 @@
extern VECTOR_Func NewVectorTable[];
extern void SystemCoreClockUpdate(void);
+extern VOID En32KCalibration(VOID);
extern void PLAT_Start(void);
extern void PLAT_Main(void);
IMAGE2_START_RAM_FUN_SECTION
+__USED
+
const RAM_START_FUNCTION gImage2EntryFun0 = {
PLAT_Start
};
IMAGE2_VALID_PATTEN_SECTION
+__USED
+
const uint8_t IMAGE2_SIGNATURE[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
@@ -166,11 +173,119 @@
#endif
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
+_WEAK void SDIO_Device_Off(void)
+{
+ /* Disable Clock for SDIO function */
+ ACTCK_SDIOD_CCTRL(OFF);
+
+ /* SDIO Function Disable */
+ SDIOD_ON_FCTRL(OFF);
+ SDIOD_OFF_FCTRL(OFF);
+ // SDIO Pin Mux off
+ SDIOD_PIN_FCTRL(OFF);
+}
+
+void SYSPlatformInit(void)
+{
+#ifdef CONFIG_CHIP_A_CUT
+ //Set SPS lower voltage
+ HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0, (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0)&0xf0ffffff));
+#else // B-Cut & C-Cut
+ //Set SPS lower voltage
+ HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0, ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0)&0xf0ffffff)|0x6000000));
+#endif
+
+ //xtal buffer driving current
+ HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1,
+ ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1)&(~(BIT_MASK_SYS_XTAL_DRV_RF1<<BIT_SHIFT_SYS_XTAL_DRV_RF1)))|(BIT_SYS_XTAL_DRV_RF1(1))));
+}
+
+void OSC_32_LINEAR_CALIBRATION(u32 num)
+{
+ u32 Rtemp;
+ u32 Ttemp = 0;
+ u32 flag = num;
+
+ while(flag){
+
+ //set parameter
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+ //offset 1 = 0x0942
+ Rtemp = 0x810942;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 2 = 0x00FF
+ Rtemp = 0x8200FF;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 3 = 0x4050
+ Rtemp = 0x834050;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 4 = 0x000A
+ Rtemp = 0x84000A;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 8 = 0x0004
+ Rtemp = 0x880004;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 0 = 0x7900
+ Rtemp = 0x807900;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ //offset 0 = 0xF900
+ Rtemp = 0x80F900;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+ while(1) {
+ //Polling LOCK
+ Rtemp = 0x110000;
+ HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+ HalDelayUs(40);
+
+ Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
+ if ((Rtemp & 0x3000) != 0x0){
+
+ if ((Rtemp & 0x3000) == 0x3000){
+
+ flag--;
+ }else {
+
+ flag = 0;
+ }
+ break;
+ }
+ else {
+ Ttemp++;
+ HalDelayUs(30);
+
+ if (Ttemp > 10000) { /*Delay 100ms*/
+ //DiagPrintf("32K linear Calibration Fail!!\n");
+ flag = 0;
+ break;
+ }
+ }
+ }
+ }
+}
// Image2 Entry Function
void PLAT_Init(void)
{
- uint32_t val;
-
// Overwrite vector table
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
#if defined ( __ICCARM__ )
@@ -185,25 +300,18 @@
__rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
- extern HAL_TIMER_OP_EXT HalTimerOpExt;
- __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
- __rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
+ HAL_WRITE32(SYSTEM_CTRL_BASE, REG_OSC32K_CTRL, (HAL_READ32(SYSTEM_CTRL_BASE, REG_OSC32K_CTRL)|BIT17|BIT18));
+ HalDelayUs(40);
+#ifdef CONFIG_TIMER_MODULE
+ // Re-init G-Timer HAL Function pointer with ROM Patch
+ if (HalCommonInit() != HAL_OK) {
+ DBG_8195A("Hal Common Init Failed.\n");
+ }
+#endif
- HalTimerOpInit_Patch(&HalTimerOp);
SystemCoreClockUpdate();
- // Set SPS lower voltage
- val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
- val &= 0xf0ffffff;
- val |= 0x6000000;
- __RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
-
- // xtal buffer driving current
- val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
- val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
- val |= BIT_SYS_XTAL_DRV_RF1(1);
- __RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
-
+ SYSPlatformInit();
// Initialize SPIC, then disable it for power saving.
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
SpicNVMCalLoadAll();
@@ -212,11 +320,19 @@
}
#ifdef CONFIG_TIMER_MODULE
+
+ OSC_32_LINEAR_CALIBRATION(10);
+ HalDelayUs(40);
+
Calibration32k();
#endif
+#ifdef CONFIG_SOC_PS_MODULE
+ InitSoCPM();
+#endif
+
#ifndef CONFIG_SDIO_DEVICE_EN
- SDIO_DEV_Disable();
+ SDIO_Device_Off();
#endif
// Enter App start function
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_trap.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_trap.h Thu Nov 08 11:46:34 2018 +0000
@@ -20,10 +20,6 @@
typedef struct {
void (*RamStartFun)(void);
-} RAM_START_FUNCTION;
-
-typedef struct {
- void (*RamStartFun)(void);
void (*RamWakeupFun)(void);
void (*RamPatchFun0)(void);
void (*RamPatchFun1)(void);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -20,6 +20,8 @@
#include "gpio_api.h"
+extern void HAL_GPIO_DeInit(HAL_GPIO_PIN *GPIO_Pin);
+
// convert Mbed pin mode to HAL Pin Mode
const u8 GPIO_InPinMode[] = {
DIN_PULL_NONE, // PullNone
@@ -193,10 +195,18 @@
HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type);
}
-
void gpio_deinit(gpio_t *obj)
{
HAL_GPIO_DeInit(&obj->hal_pin);
}
+int gpio_is_connected(const gpio_t *obj)
+{
+ if(obj->pin != (PinName)NC){
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_irq_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_irq_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,6 +19,8 @@
#if CONFIG_GPIO_EN
#include "gpio_irq_api.h"
+extern void HAL_GPIO_DeInit(HAL_GPIO_PIN *GPIO_Pin);
+
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint32_t pin_name;
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/i2c_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/i2c_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -15,7 +15,6 @@
*/
#include <string.h>
-
#include "objects.h"
#include "PinNames.h"
#include "hal_i2c.h"
@@ -79,7 +78,7 @@
extern u32 ConfigDebugErr;
extern u32 ConfigDebuginfo;
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
+{
int i2c_sel;
int i2c_idx;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
@@ -230,9 +229,9 @@
inline int i2c_start(i2c_t *obj)
{
- memset(address_save_int , 0, sizeof(address_save_int));
- memset(Byte_count , 0, sizeof(Byte_count));
- memset(address_save, 0, sizeof(address_save));
+ _memset(address_save_int , 0, sizeof(address_save_int));
+ _memset(Byte_count , 0, sizeof(Byte_count));
+ _memset(address_save, 0, sizeof(address_save));
return 0;
}
@@ -279,7 +278,7 @@
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
- if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
+ if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
@@ -345,7 +344,7 @@
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
- if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
+ if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
@@ -458,7 +457,7 @@
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
-
+
uint16_t i2c_user_addr = (uint16_t) address;
if (i2c_target_addr[pSalI2CHND->DevNum] != i2c_user_addr) {
@@ -528,7 +527,7 @@
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
- if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
+ if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,10 +1,10 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
+ *
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
@@ -12,11 +12,12 @@
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- */
+ */
#ifndef LOG_UART_API_H
#define LOG_UART_API_H
+#if defined(CONFIG_PLATFORM_8195A) && (CONFIG_PLATFORM_8195A == 1)
#include "device.h"
#include "serial_api.h"
#include "hal_log_uart.h"
@@ -25,43 +26,305 @@
extern "C" {
#endif
+/** @addtogroup log_uart LOG_UART
+ * @ingroup hal
+ * @brief log_uart functions
+ * @{
+ */
+
+///@name Ameba1 Only
+///@{
+
+/******************************************************
+ * Type Definitions
+ ******************************************************/
+/** Log uart irq handler function pointer type
+ *
+ * @param id : The argument for log uart interrupt handler
+ * @param event : The log uart interrupt indication ID. More details is shown in hal_log_uart.h
+ */
typedef void (*loguart_irq_handler)(uint32_t id, LOG_UART_INT_ID event);
-
typedef struct log_uart_s log_uart_t;
-int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits);
+/******************************************************
+ * Function Declarations
+ ******************************************************/
+/**
+ * @brief Initialize Realtek log uart.
+ * Initialize the required parts of the log uart.
+ * i.e. baudrate, data bits, parity, etc.
+ * @param[in] obj: The address of log uart object.
+ * @param[in] baudrate: Baud rate of the log uart object.
+ * @param[in] data_bits: Data bits of the log uart object.
+ * @param[in] parity: Parity type of the log uart object
+ - ParityNone, - Do not use parity
+ - ParityOdd, - Use odd parity
+ - ParityEven, - Use even parity
+ - ParityForced1, - Use even parity, the same as ParityEven
+ - ParityForced0 - Use odd parity, the same as ParityOdd
+ * @param[in] stop_bits: The number of stop bits for the log uart object.
+ * @return 0 if initialization is successful, -1 otherwise
+ */
+int32_t log_uart_init(log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits);
+
+/**
+ * @brief Release the resources related to Realtek log uart.
+
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_free(log_uart_t *obj);
+
+/**
+ * @brief Set the baud rate of log uart.
+
+ * @param[in] obj: The address of log uart object.
+ * @param[in] baudrate: Baud rate of the log uart object.
+ * @return None
+ */
void log_uart_baud(log_uart_t *obj, int baudrate);
+
+/**
+ * @brief Set parameters for log uart.
+ * including data bits, parity type and stop bits
+
+ * @param[in] obj: The address of log uart object.
+ * @param[in] data_bits: Data bits of log uart object.
+ * @param[in] parity: Parity type of the log uart object
+ - ParityNone, - Do not use parity
+ - ParityOdd, - Use odd parity
+ - ParityEven, - Use even parity
+ - ParityForced1, - Use even parity, the same as ParityEven
+ - ParityForced0 - Use odd parity, the same as ParityOdd
+ * @param[in] stop_bits: The number of stop bits for the log uart object.
+ * @return None
+ */
void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/**
+ * @brief Set irq handler for log uart.
+ * @param[in] obj: The address of log uart object.
+ * @param[in] handler: The interrupt handler for log uart.
+ * @param[in] id: The argument for log uart interrupt handler.
+ * @return None
+ */
void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id);
+
+/**
+ * @brief Enable/disable the specific irq indication ID.
+ * @param[in] obj: The address of log uart object.
+ * @param[in] irq: The log uart interrupt indication ID which will be enabled/disabled.
+ * @param[in] enable: 1 enable, 0 disable
+ * @return None
+ */
void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable);
+
+/**
+ * @brief Read one character from log uart.
+ This function will block untill the log uart gets something to read
+ * @param[in] obj: The address of log uart object.
+ * @return the character read from log uart
+ */
char log_uart_getc(log_uart_t *obj);
+
+/**
+ * @brief Write one character to log uart.
+ This function will block untill the data is successfully written to log uart
+ * @param[in] obj: The address of log uart object.
+ * @param[in] c: The one byte data to be written to log uart.
+ * @return None
+ */
void log_uart_putc(log_uart_t *obj, char c);
+
+/**
+ * @brief Check whether log uart is ready to read data
+ * @param[in] obj: The address of log uart object.
+ * @return 1 if there is data at log uart to be read, 0 otherwise
+ */
int log_uart_readable(log_uart_t *obj);
+
+/**
+ * @brief Check whether log uart is ready to write data
+ * @param[in] obj: The address of log uart object.
+ * @return 1 if log uart is ready for writing, 0 otherwise
+ */
int log_uart_writable(log_uart_t *obj);
+
+/**
+ * @brief Clear both data at log uart
+ This function will clear data in both TX FIFO and RX FIFO of log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_clear(log_uart_t *obj);
+
+/**
+ * @brief Clear TX FIFO of log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_clear_tx(log_uart_t *obj);
+
+/**
+ * @brief Clear RX FIFO of log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_clear_rx(log_uart_t *obj);
+
+/**
+ * @brief Set break control for log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_break_set(log_uart_t *obj);
+
+/**
+ * @brief Clear break control for log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None
+ */
void log_uart_break_clear(log_uart_t *obj);
+
+/**
+ * @brief Set the handler for complete TX
+ * @param[in] obj: The address of log uart object.
+ * @param[in] handler: The function which is called when log uart has finished transmitting data.
+ * @param[in] id: The parameter for handler.
+ * @return None
+ */
void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
+
+/**
+ * @brief Set the handler for complete RX
+ * @param[in] obj: The address of log uart object.
+ * @param[in] handler: The function which is called when log uart has finished receving data
+ * @param[in] id: The parameter for handler.
+ * @return None
+ */
void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
+
+/**
+ * @brief Set the handler for line status
+ * @param[in] obj: The address of log uart object.
+ * @param[in] handler: The function which is called when log uart gets an line status indication ID.
+ * @param[in] id: The parameter for handler.
+ * @return None
+ */
void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id);
-int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms);
-int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms);
-int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len);
-int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len);
-int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len,
+
+/**
+ * @brief Read data from log uart in blocking mode.
+ * @param[in] obj: The address of log uart object.
+ * @param[out] prxbuf: The buffer to store received data.
+ * @param[in] len: The maximum length of data to be read
+ * @param[in] timeout_ms: Blocking time in ms.
+ * @return the length of received data in bytes
+ */
+int32_t log_uart_recv(log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms);
+
+/**
+ * @brief Send data to log uart in blocking mode
+ * @param[in] obj: The address of log uart object.
+ * @param[in] ptxbuf: Data buffer to be sent to log uart
+ * @param[in] len: Length of data to be sent to log uart
+ * @param[in] timeout_ms: Blocking time in ms.
+ * @return the length of sent data in bytes
+ */
+int32_t log_uart_send(log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms);
+
+/**
+ * @brief Read data from log uart in interrupt mode(Non-blocking)
+ * @param[in] obj: The address of log uart object.
+ * @param[out] prxbuf: The buffer to store received data.
+ * @param[in] len: The maximum length of data to be read
+ * @return 0 if success
+ */
+int32_t log_uart_recv_stream(log_uart_t *obj, char *prxbuf, uint32_t len);
+
+/**
+ * @brief Send data to log uart in interrupt mode(Non-blocking)
+ * @param[in] obj: The address of log uart object.
+ * @param[in] ptxbuf: Data buffer to be sent to log uart
+ * @param[in] len: Length of data to be sent to log uart
+ * @return 0 if success
+ */
+int32_t log_uart_send_stream(log_uart_t *obj, char *ptxbuf, uint32_t len);
+
+/**
+ * @brief Read data from log uart with a given timeout in interrupt mode(Non-blocking)
+ * @param[in] obj: The address of log uart object.
+ * @param[out] prxbuf: The buffer to store received data.
+ * @param[in] len: The maximum length of data to be read
+ * @param[in] timeout_ms: The timeout for reading data in ms
+ * @param[in] force_cs: User callback function
+ * @return the length in Byte of received data before timeout, or error (< 0)
+ */
+int32_t log_uart_recv_stream_timeout(log_uart_t *obj, char *prxbuf, uint32_t len,
uint32_t timeout_ms, void *force_cs);
-int32_t log_uart_send_stream_abort (log_uart_t *obj);
-int32_t log_uart_recv_stream_abort (log_uart_t *obj);
-void log_uart_disable (log_uart_t *obj);
-void log_uart_enable (log_uart_t *obj);
+
+/**
+ * @brief Abort interrupt mode of sending data
+ * @param[in] obj: The address of log uart object.
+ * @return the length of data sent to log uart.
+ */
+int32_t log_uart_send_stream_abort(log_uart_t *obj);
+
+/**
+ * @brief Abort interrupt mode of receiving data
+ * @param[in] obj: The address of log uart object.
+ * @return the length of data received from log uart.
+ */
+int32_t log_uart_recv_stream_abort(log_uart_t *obj);
+
+/**
+ * @brief Disable log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None.
+ */
+void log_uart_disable(log_uart_t *obj);
+
+/**
+ * @brief Enable log uart
+ * @param[in] obj: The address of log uart object.
+ * @return None.
+ */
+void log_uart_enable(log_uart_t *obj);
+
+/**
+ * @brief Read Line-Status register
+ * @return value:
+ * - Bit 0: RX Data Ready
+ * - Bit 1: Overrun Error
+ * - Bit 2: Parity Error
+ * - Bit 3: Framing Error
+ * - Bit 4: Break Interrupt (received data input is held in 0 state for a longer than a full word tx time)
+ * - Bit 5: TX FIFO empty (THR empty)
+ * - Bit 6: TX FIFO empty (THR & TSR both empty)
+ * - Bit 7: Receiver FIFO Error (parity error, framing error or break indication)
+ */
uint8_t log_uart_raed_lsr(log_uart_t *obj);
+
+/**
+ * @brief Read Modem-Status register
+ * @return value:
+ * - Bit 0: DCTS, The CTS line has changed its state
+ * - Bit 1: DDSR, The DSR line has changed its state
+ * - Bit 2: TERI, RI line has changed its state from low to high state
+ * - Bit 3: DDCD, DCD line has changed its state
+ * - Bit 4: Complement of the CTS input
+ * - Bit 5: Complement of the DSR input
+ * - Bit 6: Complement of the RI input
+ * - Bit 7: Complement of the DCD input
+ */
uint8_t log_uart_raed_msr(log_uart_t *obj);
+///@}
+/*\@}*/
+
#ifdef __cplusplus
}
#endif
+#endif //CONFIG_PLATFORM_8195A
#endif // end of "#ifndef LOG_UART_API_H"
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -167,7 +167,7 @@
void OTA_ResetTarget(void)
{
__RTK_CTRL_WRITE32(0x14, 0x00000021);
- wait(1);
+ wait_ms(1000);
NVIC_SystemReset();
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/port_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/port_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -142,7 +142,7 @@
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
- pin_mode(obj->pin_def[i], mode);
+ pin_mode((PinName)obj->pin_def[i], mode);
}
}
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c Thu Nov 08 11:46:34 2018 +0000 @@ -73,13 +73,17 @@ #ifdef CONFIG_MBED_ENABLED #include "log_uart_api.h" + #include "hal_log_uart.h" + int stdio_uart_inited = 0; serial_t stdio_uart; log_uart_t stdio_uart_log; + static uint32_t serial_log_irq_ids; static uart_irq_handler log_irq_handler; static uint32_t serial_log_irq_en; + #endif static void SerialTxDoneCallBack(VOID *pAdapter);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -16,7 +16,7 @@
#include "objects.h"
#include "spi_api.h"
-
+#include "spi_ex_api.h"
#include "PinNames.h"
#include "pinmap.h"
#include "hal_ssi.h"
@@ -32,6 +32,11 @@
void spi_rx_done_callback(VOID *obj);
void spi_bus_tx_done_callback(VOID *obj);
+#ifdef CONFIG_GDMA_EN
+HAL_GDMA_OP SpiGdmaOp;
+#endif
+
+uint8_t SPI0_IS_AS_SLAVE = 0;
//TODO: Load default Setting: It should be loaded from external setting file.
extern const DW_SSI_DEFAULT_SETTING SpiDefaultSetting;
@@ -73,10 +78,12 @@
_memset((void*)obj, 0, sizeof(spi_t));
obj->state = 0;
- /* SsiClockDivider doesn't support odd number */
+ uint32_t SystemClock = SystemGetCpuClk();
+ uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1;
- DBG_SSI_INFO("SystemClock: %d\n", SystemGetCpuClk());
- DBG_SSI_INFO("MaxSsiFreq : %d\n", SystemGetCpuClk() >> 3);
+ /* SsiClockDivider doesn't support odd number */
+ DBG_SSI_INFO("SystemClock: %d\n", SystemClock);
+ DBG_SSI_INFO("MaxSsiFreq : %d\n", MaxSsiFreq);
ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI);
ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO);
@@ -119,7 +126,23 @@
DBG_SSI_ERR(ANSI_COLOR_RED"spi_init(): SPI %x init fails.\n"ANSI_COLOR_RESET,pHalSsiAdaptor->Index);
return;
}
- osDelay(1);
+
+ pHalSsiAdaptor->TxCompCallback = spi_tx_done_callback;
+ pHalSsiAdaptor->TxCompCbPara = (void*)obj;
+ pHalSsiAdaptor->RxCompCallback = spi_rx_done_callback;
+ pHalSsiAdaptor->RxCompCbPara = (void*)obj;
+ pHalSsiAdaptor->TxIdleCallback = spi_bus_tx_done_callback;
+ pHalSsiAdaptor->TxIdleCbPara = (void*)obj;
+
+#ifdef CONFIG_GDMA_EN
+ HalGdmaOpInit((VOID*)&SpiGdmaOp);
+ pHalSsiAdaptor->DmaConfig.pHalGdmaOp = &SpiGdmaOp;
+ pHalSsiAdaptor->DmaConfig.pRxHalGdmaAdapter = &obj->spi_gdma_adp_rx;
+ pHalSsiAdaptor->DmaConfig.pTxHalGdmaAdapter = &obj->spi_gdma_adp_tx;
+ obj->dma_en = 0;
+ pHalSsiAdaptor->HaveTxChannel = 0;
+ pHalSsiAdaptor->HaveRxChannel = 0;
+#endif
}
void spi_free (spi_t *obj)
@@ -129,6 +152,17 @@
HalSsiDeInit(pHalSsiAdaptor);
SPI0_MULTI_CS_CTRL(OFF);
+
+#ifdef CONFIG_GDMA_EN
+ if (obj->dma_en & SPI_DMA_RX_EN) {
+ HalSsiRxGdmaDeInit(pHalSsiAdaptor);
+ }
+
+ if (obj->dma_en & SPI_DMA_TX_EN) {
+ HalSsiTxGdmaDeInit(pHalSsiAdaptor);
+ }
+ obj->dma_en = 0;
+#endif
}
void spi_format (spi_t *obj, int bits, int mode, int slave)
@@ -183,6 +217,7 @@
if (pHalSsiAdaptor->Index == 0) {
pHalSsiAdaptor->Role = SSI_SLAVE;
pHalSsiAdaptor->SlaveOutputEnable = SLV_TXD_ENABLE; // <-- Slave only
+ SPI0_IS_AS_SLAVE = 1;
DBG_SSI_INFO("SPI0 is as slave\n");
} else {
DBG_SSI_ERR("The SPI%d cannot work as Slave mode, only SPI0 does.\r\n", pHalSsiAdaptor->Index);
@@ -247,10 +282,12 @@
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
+ int i;
+ char out, in;
- for (int i = 0; i < total; i++) {
- char out = (i < tx_length) ? tx_buffer[i] : write_fill;
- char in = spi_master_write(obj, out);
+ for (i = 0; i < total; i++) {
+ out = (i < tx_length) ? tx_buffer[i] : write_fill;
+ in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
@@ -296,3 +333,40 @@
}
+// Bus Idle: Real TX done, TX FIFO empty and bus shift all data out already
+void spi_bus_tx_done_callback(VOID *obj)
+{
+ spi_t *spi_obj = (spi_t *)obj;
+ spi_irq_handler handler;
+
+ if (spi_obj->bus_tx_done_handler) {
+ handler = (spi_irq_handler)spi_obj->bus_tx_done_handler;
+ handler(spi_obj->bus_tx_done_irq_id, (SpiIrq)0);
+ }
+}
+
+void spi_tx_done_callback(VOID *obj)
+{
+ spi_t *spi_obj = (spi_t *)obj;
+ spi_irq_handler handler;
+
+ if (spi_obj->state & SPI_STATE_TX_BUSY) {
+ spi_obj->state &= ~SPI_STATE_TX_BUSY;
+ if (spi_obj->irq_handler) {
+ handler = (spi_irq_handler)spi_obj->irq_handler;
+ handler(spi_obj->irq_id, SpiTxIrq);
+ }
+ }
+}
+
+void spi_rx_done_callback(VOID *obj)
+{
+ spi_t *spi_obj = (spi_t *)obj;
+ spi_irq_handler handler;
+
+ spi_obj->state &= ~SPI_STATE_RX_BUSY;
+ if (spi_obj->irq_handler) {
+ handler = (spi_irq_handler)spi_obj->irq_handler;
+ handler(spi_obj->irq_id, SpiRxIrq);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_ex_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_SPI_EXT_API_H
+#define MBED_SPI_EXT_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup spi_ex SPI_EX
+ * @ingroup hal
+ * @brief spi extended functions
+ * @{
+ */
+
+///@name Ameba Common
+///@{
+
+#define SPI_DMA_RX_EN (1<<0)
+#define SPI_DMA_TX_EN (1<<1)
+
+enum {
+ SPI_SCLK_IDLE_LOW=0, // the SCLK is Low when SPI is inactive
+ SPI_SCLK_IDLE_HIGH=2 // the SCLK is High when SPI is inactive
+};
+
+// SPI Master mode: for continuous transfer, how the CS toggle:
+enum {
+ SPI_CS_TOGGLE_EVERY_FRAME=0, // let SCPH=0 then the CS toggle every frame
+ SPI_CS_TOGGLE_START_STOP=1 // let SCPH=1 the CS toggle at start and stop
+};
+
+enum {
+ SPI_SCLK_TOGGLE_MIDDLE=0, // Serial Clk toggle at middle of 1st data bit and latch data at 1st Clk edge
+ SPI_SCLK_TOGGLE_START=1 // Serial Clk toggle at start of 1st data bit and latch data at 2nd Clk edge
+};
+
+typedef enum {
+ CS_0 = 0,
+ CS_1 = 1,
+ CS_2 = 2,
+ CS_3 = 3,
+ CS_4 = 4,
+ CS_5 = 5,
+ CS_6 = 6,
+ CS_7 = 7
+}ChipSelect;
+
+
+#define SPI_STATE_READY 0x00
+#define SPI_STATE_RX_BUSY (1<<1)
+#define SPI_STATE_TX_BUSY (1<<2)
+
+typedef enum {
+ SpiRxIrq,
+ SpiTxIrq
+} SpiIrq;
+
+typedef void (*spi_irq_handler)(uint32_t id, SpiIrq event);
+
+/**
+ * @brief Set SPI interrupt handler if needed.
+ * @param obj: spi object define in application software.
+ * @param handler: interrupt callback function
+ * @param id: interrupt callback parameter
+ * @retval none
+ */
+void spi_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id);
+
+/**
+ * @brief Set SPI interrupt bus tx done handler if needed.
+ * @param obj: spi object define in application software.
+ * @param handler: interrupt bus tx done callback function
+ * @param id: interrupt callback parameter
+ * @retval none
+ */
+void spi_bus_tx_done_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id);
+
+/**
+ * @brief Slave device to flush tx fifo.
+ * @param obj: spi slave object define in application software.
+ * @note : It will discard all data in both tx fifo and rx fifo
+ */
+void spi_slave_flush_fifo(spi_t * obj);
+
+/**
+ * @brief slave recv target length data use interrupt mode.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : stream init status
+ */
+int32_t spi_slave_read_stream(spi_t *obj, char *rx_buffer, uint32_t length);
+
+/**
+ * @brief slave send target length data use interrupt mode.
+ * @param obj: spi slave object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param length: number of data bytes to be send.
+ * @retval : stream init status
+ */
+int32_t spi_slave_write_stream(spi_t *obj, char *tx_buffer, uint32_t length);
+
+/**
+ * @brief master recv target length data use interrupt mode.
+ * @param obj: spi master object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : stream init status
+ */
+int32_t spi_master_read_stream(spi_t *obj, char *rx_buffer, uint32_t length);
+
+/**
+ * @brief master send target length data use interrupt mode.
+ * @param obj: spi master object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param length: number of data bytes to be send.
+ * @retval : stream init status
+ */
+int32_t spi_master_write_stream(spi_t *obj, char *tx_buffer, uint32_t length);
+
+/**
+ * @brief master send & recv target length data use interrupt mode.
+ * @param obj: spi master object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be send & recv.
+ * @retval : stream init status
+ */
+int32_t spi_master_write_read_stream(spi_t *obj, char *tx_buffer, char *rx_buffer, uint32_t length);
+
+/**
+ * @brief slave recv target length data use interrupt mode and timeout mechanism.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @param timeout_ms: timeout waiting time.
+ * @retval : number of bytes read already
+ */
+int32_t spi_slave_read_stream_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms);
+
+/**
+ * @brief slave recv target length data use interrupt mode and stop if the spi bus is idle.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : number of bytes read already
+ */
+int32_t spi_slave_read_stream_terminate(spi_t *obj, char *rx_buffer, uint32_t length);
+
+//#ifdef CONFIG_GDMA_EN
+/**
+ * @brief slave recv target length data use DMA mode.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : stream init status
+ */
+int32_t spi_slave_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length);
+
+/**
+ * @brief slave send target length data use DMA mode.
+ * @param obj: spi slave object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param length: number of data bytes to be send.
+ * @retval : stream init status
+ */
+int32_t spi_slave_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length);
+
+/**
+ * @brief master send & recv target length data use DMA mode.
+ * @param obj: spi master object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be send & recv.
+ * @retval : stream init status
+ */
+int32_t spi_master_write_read_stream_dma(spi_t * obj, char * tx_buffer, char * rx_buffer, uint32_t length);
+
+/**
+ * @brief master recv target length data use DMA mode.
+ * @param obj: spi master object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : stream init status
+ * @note : DMA or Interrupt mode can be used to TX dummy data
+ */
+int32_t spi_master_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length);
+
+/**
+ * @brief master send target length data use DMA mode.
+ * @param obj: spi master object define in application software.
+ * @param tx_buffer: buffer to be written to Tx FIFO.
+ * @param length: number of data bytes to be send.
+ * @retval : stream init status
+ */
+int32_t spi_master_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length);
+
+/**
+ * @brief slave recv target length data use DMA mode and timeout mechanism.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @param timeout_ms: timeout waiting time.
+ * @retval : number of bytes read already
+ */
+int32_t spi_slave_read_stream_dma_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms);
+
+/**
+ * @brief slave recv target length data use DMA mode and stop if the spi bus is idle.
+ * @param obj: spi slave object define in application software.
+ * @param rx_buffer: buffer to save data read from SPI FIFO.
+ * @param length: number of data bytes to be read.
+ * @retval : number of bytes read already
+ */
+int32_t spi_slave_read_stream_dma_terminate(spi_t * obj, char * rx_buffer, uint32_t length);
+//#endif
+
+///@}
+
+/*\@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -76,7 +76,7 @@
pTimerAdapter->TimerIrqPriority = 0;
pTimerAdapter->TimerLoadValueUs = 0xFFFFFFFF; // Just a whatever value
pTimerAdapter->TimerMode = USER_DEFINED;
-
+
HalTimerInit ((VOID*) pTimerAdapter);
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -29,7 +29,7 @@
TIMER3 = 5, // GTimer 5, share with PWM_2
TIMER4 = 0, // GTimer 0, share with software-RTC functions
- GTIMER_MAX = 5
+ GTIMER_MAX = 5
};
void gtimer_init (gtimer_t *obj, uint32_t tid);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -27,7 +27,7 @@
void trng_init(trng_t *obj)
{
_memset((void *)obj, 0, sizeof(trng_t));
- analogin_init(&obj->tradcng, ADC0);
+ analogin_init(&obj->tradcng, (PinName)ADC0);
obj->inited = 1;
}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -119,3 +119,8 @@
void us_ticker_clear_interrupt(void)
{
}
+
+void us_ticker_free(void)
+{
+ HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
+}
--- a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -56,7 +56,7 @@
uint8_t RTW_EMAC::get_hwaddr_size() const
{
- return ETHARP_HWADDR_LEN;
+ return ETH_HWADDR_LEN;
}
bool RTW_EMAC::get_hwaddr(uint8_t *addr) const
@@ -76,6 +76,7 @@
} else {
printf("Get HW address failed\r\n");
}
+ return true;
}
void RTW_EMAC::set_hwaddr(const uint8_t *addr)
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h Thu Nov 08 11:46:34 2018 +0000
@@ -16,272 +16,41 @@
#ifndef __PLATFORM_STDLIB_H__
#define __PLATFORM_STDLIB_H__
-#define USE_CLIB_PATCH 0
-#if defined (__GNUC__)
-/* build rom should set USE_RTL_ROM_CLIB=0 */
-#ifndef CONFIG_MBED_ENABLED
-#include <rt_lib_rom.h>
-#endif
+#ifdef __cplusplus
+extern "C" {
#endif
-#ifdef CONFIG_BUILD_ROM
-#define USE_RTL_ROM_CLIB 0
-#else
-#define BUFFERED_PRINTF 0
-#ifndef CONFIG_MBED_ENABLED
-#define USE_RTL_ROM_CLIB 1
-#else
-#define USE_RTL_ROM_CLIB 0
-#endif
+#if defined(CONFIG_PLATFORM_8195A)+\
+ defined(CONFIG_PLATFORM_8711B)+\
+ defined(CONFIG_PLATFORM_8721D)+\
+ defined(CONFIG_PLATFORM_8195BHP)+\
+ defined(USE_STM322xG_EVAL)+\
+ defined(USE_STM324xG_EVAL)+\
+ defined(STM32F10X_XL) > 1
+ #error "Cannot define two or more platform at one time"
#endif
#if defined(CONFIG_PLATFORM_8195A)
-#if defined (__IARSTDLIB__)
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <stdint.h>
- #include "diag.h"
-
- #define strsep(str, delim) _strsep(str, delim)
-#elif defined (__CC_ARM)
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <stdint.h>
- #include "diag.h"
- #define strsep(str, delim) _strsep(str, delim)
- #define _memset(dst, val, sz) memset(dst, val, sz)
-#else
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include "diag.h"
- #include "strproc.h"
- #include "basic_types.h"
- #include "hal_misc.h"
- #if USE_RTL_ROM_CLIB
- #include "rtl_lib.h"
- #endif
-
- #undef printf
- #undef sprintf
- #undef snprintf
- #undef atoi
- #undef memcmp
- #undef memcpy
- #undef memset
- #undef strcmp
- #undef strcpy
- #undef strlen
- #undef strncmp
- #undef strncpy
- #undef strsep
- #undef strtok
- #if USE_RTL_ROM_CLIB
- #undef memchr
- #undef memmove
- #undef strcat
- #undef strchr
- #undef strncat
- #undef strstr
- #endif
-
- #if USE_RTL_ROM_CLIB
-#if BUFFERED_PRINTF
- extern int buffered_printf(const char* fmt, ...);
- #define printf buffered_printf
+ #include "platform_stdlib_rtl8195a.h"
+#elif defined (CONFIG_PLATFORM_8711B)
+ #include "platform_stdlib_rtl8711b.h"
+#elif defined (CONFIG_PLATFORM_8721D)
+ #include "platform_stdlib_rtl8721d.h"
+#elif defined(CONFIG_PLATFORM_8195BHP)
+ #include "platform_stdlib_rtl8195bhp.h"
+#elif defined(USE_STM322xG_EVAL) || defined(USE_STM324xG_EVAL) || defined(STM32F10X_XL)
+ #include "platform_stdlib_stm32.h"
+#elif defined (CONFIG_PLATFORM_8710C)
+ #include "platform_stdlib_rtl8710c.h"
#else
- #define printf rtl_printf
-#endif
- #define sprintf rtl_sprintf
- #define snprintf rtl_snprintf
- #define memchr rtl_memchr
- #define memcmp rtl_memcmp
- #define memcpy rtl_memcpy
- #define memmove rtl_memmove
- #define memset rtl_memset
- #define strcat rtl_strcat
- #define strchr rtl_strchr
- #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2)
- #define strcpy rtl_strcpy
- #define strlen(str) rtl_strlen((const char *)str)
- #define strncat rtl_strncat
- #define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n)
- #define strncpy rtl_strncpy
- #define strstr rtl_strstr
- #define strsep rtl_strsep
- #define strtok rtl_strtok
- #else
- #if USE_CLIB_PATCH
- extern int DiagSscanfPatch(const char *buf, const char *fmt, ...);
- extern char* DiagStrtokPatch(char *str, const char* delim);
- extern char* DiagStrstrPatch(char *string, char *substring);
- extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...);
- extern u32 DiagPrintfPatch(const char *fmt, ...);
- extern u32 DiagSPrintfPatch(u8 *buf, const char *fmt, ...);
- #define printf DiagPrintfPatch
- #define sprintf DiagSPrintfPatch
- #define snprintf DiagSnPrintfPatch
- #define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b))
- #define strtok DiagStrtokPatch
- #else
- #define printf DiagPrintf
- #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg)
- #if defined (__GNUC__)
- #define snprintf DiagSnPrintf // NULL function
- #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function
- #endif
- #define strtok(str, delim) _strsep(str, delim)
- #endif
- #define memcmp(dst, src, sz) _memcmp(dst, src, sz)
- #define memcpy(dst, src, sz) _memcpy(dst, src, sz)
- #define memset(dst, val, sz) _memset(dst, val, sz)
- #define strchr(s, c) _strchr(s, c) // for B-cut ROM
- #define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2)
- #define strcpy(dest, src) _strcpy(dest, src)
- #define strlen(str) prvStrLen((const unsigned char *) str)
- #define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt)
- #define strncpy(dest, src, count) _strncpy(dest, src, count)
- #define strsep(str, delim) _strsep(str, delim)
- #endif
-
- #define atoi(str) prvAtoi(str)
- #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM
-
- #if USE_CLIB_PATCH
- #undef sscanf
- #define sscanf DiagSscanfPatch
- #else
- #if defined (__GNUC__)
- #undef sscanf //_sscanf
- //extern int DiagSscanfPatch(const char *buf, const char *fmt, ...);
- //#define sscanf DiagSscanfPatch
- #define sscanf sscanf // use libc sscanf
- #endif
- #endif
-#endif // defined (__IARSTDLIB__)
-
-//
-// memory management
-//
-#ifndef CONFIG_MBED_ENABLED
-extern void *pvPortMalloc( size_t xWantedSize );
-extern void vPortFree( void *pv );
-#define malloc pvPortMalloc
-#define free vPortFree
-#endif
-#elif defined (CONFIG_PLATFORM_8711B)
-
-#if defined (__IARSTDLIB__)
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <stdint.h>
- #include <stdarg.h> /* va_list */
- #include "diag.h"
-
- #define strsep(str, delim) _strsep(str, delim)
-#else
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <stdarg.h> /* va_list */
- #include "diag.h"
- #include "strproc.h"
- #include "memproc.h"
- #include "basic_types.h"
-#if USE_RTL_ROM_CLIB
- #include "rtl_lib.h"
- #include "rom_libc_string.h"
+ #error "Undefined Platform stdlib"
#endif
- #undef printf
- #undef sprintf
- #undef snprintf
- #undef memchr
- #undef memcmp
- #undef memcpy
- #undef memset
- #undef memmove
- #undef strcmp
- #undef strcpy
- #undef strlen
- #undef strncmp
- #undef strncpy
- #undef strsep
- #undef strtok
- #undef strcat
- #undef strchr
- #undef strncat
- #undef strstr
- #undef atol
- #undef atoi
- #undef strpbrk
-
-#if USE_RTL_ROM_CLIB
-#if BUFFERED_PRINTF
- extern int buffered_printf(const char* fmt, ...);
- #define printf buffered_printf
-#else
- #define printf rtl_printf
-#endif
- #define sprintf rtl_sprintf
- #define snprintf rtl_snprintf
- #define vsnprintf rtl_vsnprintf
-#else
- #define printf DiagPrintf
- #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg)
- #define snprintf DiagSnPrintf // NULL function
- #define vsnprintf(buf, size, fmt, ap) VSprintf(buf, fmt, ap)
-#endif
- #define memchr __rtl_memchr_v1_00
- #define memcmp(dst, src, sz) _memcmp(dst, src, sz)
- #define memcpy(dst, src, sz) _memcpy(dst, src, sz)
- #define memmove __rtl_memmove_v1_00
- #define memset(dst, val, sz) _memset(dst, val, sz)
-
- #define strchr(s, c) _strchr(s, c) // for B-cut ROM
- #define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2)
- #define strcpy(dest, src) _strcpy(dest, src)
- #define strlen(str) prvStrLen((const unsigned char *) str)
- #define strsep(str, delim) _strsep(str, delim)
- #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function
- #define strtok(str, delim) prvStrtok(str, delim)//_strsep(str, delim)
- #define strcat __rtl_strcat_v1_00
-
- #define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt)
- #define strncpy(dest, src, count) _strncpy(dest, src, count)
- #define strncat __rtl_strncat_v1_00
-
- #define atol(str) strtol(str,NULL,10)
- #define atoi(str) prvAtoi(str)
- #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM
-#if defined (__GNUC__)
- #undef sscanf
- #define sscanf _sscanf_patch
- #define rand Rand
-#endif
- //extern int _sscanf_patch(const char *buf, const char *fmt, ...);
- //#define sscanf _sscanf_patch
-
-
-#endif // defined (__IARSTDLIB__)
-
-//
-// memory management
-//
-extern void *pvPortMalloc( size_t xWantedSize );
-extern void vPortFree( void *pv );
-#define malloc pvPortMalloc
-#define free vPortFree
-#elif defined(USE_STM322xG_EVAL) || defined(USE_STM324xG_EVAL) || defined(STM32F10X_XL)
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
- #include <stdint.h>
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
+#include "basic_types.h"
#endif
-
+#ifdef __cplusplus
+}
+#endif
#endif //__PLATFORM_STDLIB_H__
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib_rtl8195a.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,166 @@ +#ifndef PLATFORM_STDLIB_RTL8195A_H +#define PLATFORM_STDLIB_RTL8195A_H + +#define USE_CLIB_PATCH 0 + +#if defined (__GNUC__) + /* build rom should set USE_RTL_ROM_CLIB=0 */ + #if !defined(CONFIG_MBED_ENABLED) + #include <rt_lib_rom.h> + #endif +#endif + +#if defined(CONFIG_BUILD_ROM) || defined(CONFIG_MBED_ENABLED) + #define USE_RTL_ROM_CLIB 0 +#else + #define BUFFERED_PRINTF 0 + #define USE_RTL_ROM_CLIB 1 +#endif + +#if defined (__IARSTDLIB__) + #include <stdio.h> + #include <stdlib.h> + #include <string.h> + #include <stdint.h> + #include "diag.h" + + #define strsep(str, delim) _strsep(str, delim) +#elif defined (__CC_ARM) + #include <stdio.h> + #include <stdlib.h> + #include <string.h> + #include <stdint.h> + #include "diag.h" + #define strsep(str, delim) _strsep(str, delim) +#elif defined (CONFIG_MBED_ENABLED) + #include <stdio.h> + #include <stdlib.h> + #include <string.h> + #include <stdint.h> + #include "diag.h" + + #define strsep(str, delim) _strsep(str, delim) +#else + #include <stdio.h> + #include <stdlib.h> + #include <string.h> + #include "diag.h" + #include "strproc.h" + #include "basic_types.h" + #include "hal_misc.h" + #if USE_RTL_ROM_CLIB + #include "rtl_lib.h" + #endif + + #undef printf + #undef sprintf + #undef snprintf + #undef atoi + #undef memcmp + #undef memcpy + #undef memset + #undef strcmp + #undef strcpy + #undef strlen + #undef strncmp + #undef strncpy + #undef strsep + #undef strtok + #if USE_RTL_ROM_CLIB + #undef memchr + #undef memmove + #undef strcat + #undef strchr + #undef strncat + #undef strstr + #endif + + #if USE_RTL_ROM_CLIB + #if BUFFERED_PRINTF + extern int buffered_printf(const char* fmt, ...); + #define printf buffered_printf + #else + #define printf rtl_printf + #endif + + #define sprintf rtl_sprintf + #define snprintf rtl_snprintf + #define memchr rtl_memchr + #define memcmp rtl_memcmp + #define memcpy rtl_memcpy + #define memmove rtl_memmove + #define memset rtl_memset + #define strcat rtl_strcat + #define strchr rtl_strchr + #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2) + #define strcpy rtl_strcpy + #define strlen(str) rtl_strlen((const char *)str) + #define strncat rtl_strncat + #define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n) + #define strncpy rtl_strncpy + #define strstr rtl_strstr + #define strsep rtl_strsep + #define strtok rtl_strtok + #else + #if USE_CLIB_PATCH + extern int DiagSscanfPatch(const char *buf, const char *fmt, ...); + extern char* DiagStrtokPatch(char *str, const char* delim); + extern char* DiagStrstrPatch(char *string, char *substring); + extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...); + extern u32 DiagPrintfPatch(const char *fmt, ...); + extern u32 DiagSPrintfPatch(u8 *buf, const char *fmt, ...); + #define printf DiagPrintfPatch + #define sprintf DiagSPrintfPatch + #define snprintf DiagSnPrintfPatch + #define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b)) + #define strtok DiagStrtokPatch + #else + #define printf DiagPrintf + #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg) + #if defined (__GNUC__) + #define snprintf DiagSnPrintf // NULL function + #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function + #endif + #define strtok(str, delim) _strsep(str, delim) + #endif + #define memcmp(dst, src, sz) _memcmp(dst, src, sz) + #define memcpy(dst, src, sz) _memcpy(dst, src, sz) + #define memset(dst, val, sz) _memset(dst, val, sz) + #define strchr(s, c) _strchr(s, c) // for B-cut ROM + #define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2) + #define strcpy(dest, src) _strcpy(dest, src) + #define strlen(str) prvStrLen((const unsigned char *) str) + #define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt) + #define strncpy(dest, src, count) _strncpy(dest, src, count) + #define strsep(str, delim) _strsep(str, delim) + #endif + + #define atoi(str) prvAtoi(str) + #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM + + #if USE_CLIB_PATCH + #undef sscanf + #define sscanf DiagSscanfPatch + #else + #if defined (__GNUC__) + #undef sscanf //_sscanf + //extern int DiagSscanfPatch(const char *buf, const char *fmt, ...); + //#define sscanf DiagSscanfPatch + #define sscanf sscanf // use libc sscanf + #endif + #endif +#endif // defined (__IARSTDLIB__) + +// +// memory management +// +#if defined(CONFIG_MBED_ENABLED) + //use libc memory functions +#else + extern void *pvPortMalloc( size_t xWantedSize ); + extern void vPortFree( void *pv ); + #define malloc pvPortMalloc + #define free vPortFree +#endif + +#endif // PLATFORM_STDLIB_RTL8195A_H
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1965 +0,0 @@
-/* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <dhcp/dhcps.h>
-//#include <flash/stm32_flash.h>
-#include <platform/platform_stdlib.h>
-#include <wifi/wifi_conf.h>
-#include <wifi/wifi_util.h>
-#include <wifi/wifi_ind.h>
-#include "tcpip.h"
-#include <osdep_service.h>
-#ifndef CONFIG_MBED_ENABLED
-#include <lwip_netconf.h>//
-#endif
-#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT || CONFIG_JD_SMART
-#include "wlan_fast_connect/example_wlan_fast_connect.h"
-#endif
-#if CONFIG_EXAMPLE_UART_ATCMD
-#include "at_cmd/atcmd_wifi.h"
-#endif
-extern u32 GlobalDebugEnable;
-#define WIFI_CONF_MSG(...) do {\
- if (GlobalDebugEnable) \
- printf("\r" __VA_ARGS__);\
-}while(0)
-
-#if CONFIG_INIC_EN
-extern int inic_start(void);
-extern int inic_stop(void);
-#endif
-
-/******************************************************
- * Constants
- ******************************************************/
-#define SCAN_USE_SEMAPHORE 0
-
-#define RTW_JOIN_TIMEOUT 15000
-
-#define JOIN_ASSOCIATED (uint32_t)(1 << 0)
-#define JOIN_AUTHENTICATED (uint32_t)(1 << 1)
-#define JOIN_LINK_READY (uint32_t)(1 << 2)
-#define JOIN_SECURITY_COMPLETE (uint32_t)(1 << 3)
-#define JOIN_COMPLETE (uint32_t)(1 << 4)
-#define JOIN_NO_NETWORKS (uint32_t)(1 << 5)
-#define JOIN_WRONG_SECURITY (uint32_t)(1 << 6)
-#define JOIN_HANDSHAKE_DONE (uint32_t)(1 << 7)
-#define JOIN_SIMPLE_CONFIG (uint32_t)(1 << 8)
-#define JOIN_AIRKISS (uint32_t)(1 << 9)
-
-/******************************************************
- * Type Definitions
- ******************************************************/
-
-/******************************************************
- * Variables Declarations
- ******************************************************/
-#if !defined(CONFIG_MBED_ENABLED)
-extern struct netif xnetif[NET_IF_NUM];
-#endif
-/******************************************************
- * Variables Definitions
- ******************************************************/
-static internal_scan_handler_t scan_result_handler_ptr = {0, 0, 0, RTW_FALSE, 0, 0, 0, 0, 0};
-static internal_join_result_t* join_user_data;
-#ifdef CONFIG_MBED_ENABLED
-static rtw_mode_t wifi_mode = RTW_MODE_STA;
-#else
-extern rtw_mode_t wifi_mode;
-#endif
-int error_flag = RTW_UNKNOWN;
-uint32_t rtw_join_status;
-#if ATCMD_VER == ATVER_2
-extern unsigned char dhcp_mode_sta;
-#endif
-
-/******************************************************
- * Variables Definitions
- ******************************************************/
-
-#ifndef WLAN0_NAME
- #define WLAN0_NAME "wlan0"
-#endif
-#ifndef WLAN1_NAME
- #define WLAN1_NAME "wlan1"
-#endif
-/* Give default value if not defined */
-#ifndef NET_IF_NUM
-#ifdef CONFIG_CONCURRENT_MODE
-#define NET_IF_NUM 2
-#else
-#define NET_IF_NUM 1
-#endif
-#endif
-
-/*Static IP ADDRESS*/
-#ifndef IP_ADDR0
-#define IP_ADDR0 192
-#define IP_ADDR1 168
-#define IP_ADDR2 1
-#define IP_ADDR3 80
-#endif
-
-/*NETMASK*/
-#ifndef NETMASK_ADDR0
-#define NETMASK_ADDR0 255
-#define NETMASK_ADDR1 255
-#define NETMASK_ADDR2 255
-#define NETMASK_ADDR3 0
-#endif
-
-/*Gateway Address*/
-#ifndef GW_ADDR0
-#define GW_ADDR0 192
-#define GW_ADDR1 168
-#define GW_ADDR2 1
-#define GW_ADDR3 1
-#endif
-
-/*Static IP ADDRESS*/
-#ifndef AP_IP_ADDR0
-#define AP_IP_ADDR0 192
-#define AP_IP_ADDR1 168
-#define AP_IP_ADDR2 43
-#define AP_IP_ADDR3 1
-#endif
-
-/*NETMASK*/
-#ifndef AP_NETMASK_ADDR0
-#define AP_NETMASK_ADDR0 255
-#define AP_NETMASK_ADDR1 255
-#define AP_NETMASK_ADDR2 255
-#define AP_NETMASK_ADDR3 0
-#endif
-
-/*Gateway Address*/
-#ifndef AP_GW_ADDR0
-#define AP_GW_ADDR0 192
-#define AP_GW_ADDR1 168
-#define AP_GW_ADDR2 43
-#define AP_GW_ADDR3 1
-#endif
-
-/******************************************************
- * Function Definitions
- ******************************************************/
-
-#if CONFIG_WLAN
-//----------------------------------------------------------------------------//
-static int wifi_connect_local(rtw_network_info_t *pWifi)
-{
- int ret = 0;
-
- if(is_promisc_enabled())
- promisc_set(0, NULL, 0);
-
- /* lock 4s to forbid suspend under linking */
- rtw_wakelock_timeout(4 *1000);
-
- if(!pWifi) return -1;
- switch(pWifi->security_type){
- case RTW_SECURITY_OPEN:
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_NONE, NULL, 0, 0, 0, 0, NULL, 0);
- break;
- case RTW_SECURITY_WEP_PSK:
- case RTW_SECURITY_WEP_SHARED:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_SHARED_KEY);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_WEP, NULL, pWifi->key_id, 1 /* set tx key */, 0, 0, pWifi->password, pWifi->password_len);
- break;
- case RTW_SECURITY_WPA_TKIP_PSK:
- case RTW_SECURITY_WPA2_TKIP_PSK:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_TKIP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(WLAN0_NAME, pWifi->password, pWifi->password_len);
- break;
- case RTW_SECURITY_WPA_AES_PSK:
- case RTW_SECURITY_WPA2_AES_PSK:
- case RTW_SECURITY_WPA2_MIXED_PSK:
- case RTW_SECURITY_WPA_WPA2_MIXED:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_CCMP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(WLAN0_NAME, pWifi->password, pWifi->password_len);
- break;
- default:
- ret = -1;
- WIFI_CONF_MSG("\n\rWIFICONF: security type(0x%x) is not supported.\n\r", pWifi->security_type);
- break;
- }
- if(ret == 0)
- ret = wext_set_ssid(WLAN0_NAME, pWifi->ssid.val, pWifi->ssid.len);
- return ret;
-}
-
-static int wifi_connect_bssid_local(rtw_network_info_t *pWifi)
-{
- int ret = 0;
- u8 bssid[12] = {0};
-
- if(is_promisc_enabled())
- promisc_set(0, NULL, 0);
-
- /* lock 4s to forbid suspend under linking */
- rtw_wakelock_timeout(4 *1000);
-
- if(!pWifi) return -1;
- switch(pWifi->security_type){
- case RTW_SECURITY_OPEN:
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_NONE, NULL, 0, 0, 0, 0, NULL, 0);
- break;
- case RTW_SECURITY_WEP_PSK:
- case RTW_SECURITY_WEP_SHARED:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_SHARED_KEY);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_WEP, NULL, pWifi->key_id, 1 /* set tx key */, 0, 0, pWifi->password, pWifi->password_len);
- break;
- case RTW_SECURITY_WPA_TKIP_PSK:
- case RTW_SECURITY_WPA2_TKIP_PSK:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_TKIP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(WLAN0_NAME, pWifi->password, pWifi->password_len);
- break;
- case RTW_SECURITY_WPA_AES_PSK:
- case RTW_SECURITY_WPA2_AES_PSK:
- case RTW_SECURITY_WPA2_MIXED_PSK:
- ret = wext_set_auth_param(WLAN0_NAME, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(WLAN0_NAME, IW_ENCODE_ALG_CCMP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(WLAN0_NAME, pWifi->password, pWifi->password_len);
- break;
- default:
- ret = -1;
- WIFI_CONF_MSG("\n\rWIFICONF: security type(0x%x) is not supported.\n\r", pWifi->security_type);
- break;
- }
- if(ret == 0){
- memcpy(bssid, pWifi->bssid.octet, ETH_ALEN);
- if(pWifi->ssid.len){
- bssid[ETH_ALEN] = '#';
- bssid[ETH_ALEN + 1] = '@';
- memcpy(bssid + ETH_ALEN + 2, &pWifi, sizeof(pWifi));
- }
- ret = wext_set_bssid(WLAN0_NAME, bssid);
- }
- return ret;
-}
-
-void wifi_rx_beacon_hdl( char* buf, int buf_len, int flags, void* userdata) {
- //printf("Beacon!\n");
-}
-
-
-static void wifi_no_network_hdl(char* buf, int buf_len, int flags, void* userdata)
-{
- if(join_user_data!=NULL)
- rtw_join_status = JOIN_NO_NETWORKS;
-}
-
-static void wifi_connected_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
-#ifdef CONFIG_ENABLE_EAP
- if(get_eap_phase()){
- rtw_join_status = JOIN_COMPLETE | JOIN_SECURITY_COMPLETE | JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY;
- return;
- }
-#endif /* CONFIG_ENABLE_EAP */
-
- if((join_user_data!=NULL)&&((join_user_data->network_info.security_type == RTW_SECURITY_OPEN) ||
- (join_user_data->network_info.security_type == RTW_SECURITY_WEP_PSK) ||
- (join_user_data->network_info.security_type == RTW_SECURITY_WEP_SHARED))){
- rtw_join_status = JOIN_COMPLETE | JOIN_SECURITY_COMPLETE | JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY;
- rtw_up_sema(&join_user_data->join_sema);
- }else if((join_user_data!=NULL)&&((join_user_data->network_info.security_type == RTW_SECURITY_WPA2_AES_PSK) )){
- rtw_join_status = JOIN_COMPLETE | JOIN_SECURITY_COMPLETE | JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY;
- }
-}
-static void wifi_handshake_done_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- rtw_join_status = JOIN_COMPLETE | JOIN_SECURITY_COMPLETE | JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY|JOIN_HANDSHAKE_DONE;
- if(join_user_data != NULL)
- rtw_up_sema(&join_user_data->join_sema);
-}
-
-static void wifi_disconn_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- if(join_user_data != NULL){
- if(join_user_data->network_info.security_type == RTW_SECURITY_OPEN){
-
- if(rtw_join_status == JOIN_NO_NETWORKS)
- error_flag = RTW_NONE_NETWORK;
-
- }else if(join_user_data->network_info.security_type == RTW_SECURITY_WEP_PSK){
-
- if(rtw_join_status == JOIN_NO_NETWORKS)
- error_flag = RTW_NONE_NETWORK;
-
- else if(rtw_join_status == 0)
- error_flag = RTW_CONNECT_FAIL;
-
- }else if(join_user_data->network_info.security_type == RTW_SECURITY_WPA2_AES_PSK){
-
- if(rtw_join_status ==JOIN_NO_NETWORKS)
- error_flag = RTW_NONE_NETWORK;
-
- else if(rtw_join_status == 0)
- error_flag = RTW_CONNECT_FAIL;
-
- else if(rtw_join_status == (JOIN_COMPLETE | JOIN_SECURITY_COMPLETE | JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY))
- error_flag = RTW_WRONG_PASSWORD;
- }
-
- }else{
- if(error_flag == RTW_NO_ERROR) //wifi_disconn_hdl will be dispatched one more time after join_user_data = NULL add by frankie
- error_flag = RTW_UNKNOWN;
- }
-
- if(join_user_data != NULL)
- rtw_up_sema(&join_user_data->join_sema);
- //printf("\r\nWiFi Disconnect. Error flag is %d.\n", error_flag);
-}
-
-#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT || CONFIG_JD_SMART
-#define WLAN0_NAME "wlan0"
-
-void restore_wifi_info_to_flash()
-{
-
- struct wlan_fast_reconnect * data_to_flash;
- u32 channel = 0;
- u8 index = 0;
- u8 *ifname[1] = {WLAN0_NAME};
- rtw_wifi_setting_t setting;
- //struct security_priv *psecuritypriv = &padapter->securitypriv;
- //WLAN_BSSID_EX *pcur_bss = pmlmepriv->cur_network.network;
-
- data_to_flash = (struct wlan_fast_reconnect *)rtw_zmalloc(sizeof(struct wlan_fast_reconnect));
-
- if(data_to_flash && p_write_reconnect_ptr){
- if(wifi_get_setting((const char*)ifname[0],&setting) || setting.mode == RTW_MODE_AP){
- WIFI_CONF_MSG("\r\n %s():wifi_get_setting fail or ap mode", __func__);
- return;
- }
- channel = setting.channel;
-
- rtw_memset(psk_essid[index], 0, sizeof(psk_essid[index]));
- strncpy(psk_essid[index], setting.ssid, strlen(setting.ssid));
- switch(setting.security_type){
- case RTW_SECURITY_OPEN:
- rtw_memset(psk_passphrase[index], 0, sizeof(psk_passphrase[index]));
- rtw_memset(wpa_global_PSK[index], 0, sizeof(wpa_global_PSK[index]));
- data_to_flash->security_type = RTW_SECURITY_OPEN;
- break;
- case RTW_SECURITY_WEP_PSK:
- channel |= (setting.key_idx) << 28;
- rtw_memset(psk_passphrase[index], 0, sizeof(psk_passphrase[index]));
- rtw_memset(wpa_global_PSK[index], 0, sizeof(wpa_global_PSK[index]));
- rtw_memcpy(psk_passphrase[index], setting.password, sizeof(psk_passphrase[index]));
- data_to_flash->security_type = RTW_SECURITY_WEP_PSK;
- break;
- case RTW_SECURITY_WPA_TKIP_PSK:
- data_to_flash->security_type = RTW_SECURITY_WPA_TKIP_PSK;
- break;
- case RTW_SECURITY_WPA2_AES_PSK:
- data_to_flash->security_type = RTW_SECURITY_WPA2_AES_PSK;
- break;
- default:
- break;
- }
-
- memcpy(data_to_flash->psk_essid, psk_essid[index], sizeof(data_to_flash->psk_essid));
- if (strlen(psk_passphrase64) == 64) {
- memcpy(data_to_flash->psk_passphrase, psk_passphrase64, sizeof(data_to_flash->psk_passphrase));
- } else {
- memcpy(data_to_flash->psk_passphrase, psk_passphrase[index], sizeof(data_to_flash->psk_passphrase));
- }
- memcpy(data_to_flash->wpa_global_PSK, wpa_global_PSK[index], sizeof(data_to_flash->wpa_global_PSK));
- memcpy(&(data_to_flash->channel), &channel, 4);
-
- //call callback function in user program
- p_write_reconnect_ptr((u8 *)data_to_flash, sizeof(struct wlan_fast_reconnect));
-
- }
- if(data_to_flash)
- rtw_free(data_to_flash);
-}
-
-#endif
-
-//----------------------------------------------------------------------------//
-int wifi_connect(
- char *ssid,
- rtw_security_t security_type,
- char *password,
- int ssid_len,
- int password_len,
- int key_id,
- void *semaphore)
-{
- _sema join_semaphore;
- rtw_result_t result = RTW_SUCCESS;
- u8 wep_hex = 0;
- u8 wep_pwd[14] = {0};
-
- if(rtw_join_status & JOIN_SIMPLE_CONFIG || rtw_join_status & JOIN_AIRKISS){
- return RTW_ERROR;
- }
-
- rtw_join_status = 0;//clear for last connect status
- error_flag = RTW_UNKNOWN ;//clear for last connect status
- if ( ( ( ( password_len > RTW_MAX_PSK_LEN ) ||
- ( password_len < RTW_MIN_PSK_LEN ) ) &&
- ( ( security_type == RTW_SECURITY_WPA_TKIP_PSK ) ||
- ( security_type == RTW_SECURITY_WPA_AES_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_AES_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_TKIP_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_MIXED_PSK ) ) )) {
- error_flag = RTW_WRONG_PASSWORD;
- return RTW_INVALID_KEY;
- }
-
- if ((security_type == RTW_SECURITY_WEP_PSK)||
- (security_type ==RTW_SECURITY_WEP_SHARED)) {
- if ((password_len != 5) && (password_len != 13) &&
- (password_len != 10)&& (password_len != 26)) {
- error_flag = RTW_WRONG_PASSWORD;
- return RTW_INVALID_KEY;
- } else {
-
- if(password_len == 10) {
-
- u32 p[5] = {0};
- u8 i = 0;
- sscanf((const char*)password, "%02lx%02lx%02lx%02lx%02lx", &p[0], &p[1], &p[2], &p[3], &p[4]);
- for(i=0; i< 5; i++)
- wep_pwd[i] = (u8)p[i];
- wep_pwd[5] = '\0';
- password_len = 5;
- wep_hex = 1;
- } else if (password_len == 26) {
- u32 p[13] = {0};
- u8 i = 0;
- sscanf((const char*)password, "%02lx%02lx%02lx%02lx%02lx%02lx%02lx"\
- "%02lx%02lx%02lx%02lx%02lx%02lx", &p[0], &p[1], &p[2], &p[3], &p[4],\
- &p[5], &p[6], &p[7], &p[8], &p[9], &p[10], &p[11], &p[12]);
- for(i=0; i< 13; i++)
- wep_pwd[i] = (u8)p[i];
- wep_pwd[13] = '\0';
- password_len = 13;
- wep_hex = 1;
- }
- }
- }
-
- internal_join_result_t *join_result = (internal_join_result_t *)rtw_zmalloc(sizeof(internal_join_result_t));
- if(!join_result) {
- return RTW_NOMEM;
- }
-
- join_result->network_info.ssid.len = ssid_len > 32 ? 32 : ssid_len;
- rtw_memcpy(join_result->network_info.ssid.val, ssid, ssid_len);
-
- join_result->network_info.password_len = password_len;
- if(password_len) {
- /* add \0 to the end */
- join_result->network_info.password = rtw_zmalloc(password_len + 1);
- if(!join_result->network_info.password) {
- result = RTW_NOMEM;
- goto error;
- }
- if (0 == wep_hex)
- rtw_memcpy(join_result->network_info.password, password, password_len);
- else
- rtw_memcpy(join_result->network_info.password, wep_pwd, password_len);
-
- }
-
- join_result->network_info.security_type = security_type;
- join_result->network_info.key_id = key_id;
-
- if(semaphore == NULL) {
- rtw_init_sema( &join_result->join_sema, 0 );
- if(!join_result->join_sema){
- result = RTW_NORESOURCE;
- goto error;
- }
- join_semaphore = join_result->join_sema;
- } else {
- join_result->join_sema = semaphore;
- }
- wifi_reg_event_handler(WIFI_EVENT_NO_NETWORK,wifi_no_network_hdl,NULL);
- wifi_reg_event_handler(WIFI_EVENT_CONNECT, wifi_connected_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_DISCONNECT, wifi_disconn_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, wifi_handshake_done_hdl, NULL);
-
- wifi_connect_local(&join_result->network_info);
-
- join_user_data = join_result;
-
- if(semaphore == NULL) {
-// for eap connection, timeout should be longer (default value in wpa_supplicant: 60s)
-#ifdef CONFIG_ENABLE_EAP
- if(get_eap_phase()){
- if(rtw_down_timeout_sema( &join_result->join_sema, 60000 ) == RTW_FALSE) {
- WIFI_CONF_MSG("RTW API: Join bss timeout\r\n");
- if(password_len) {
- rtw_free(join_result->network_info.password);
- }
- result = RTW_TIMEOUT;
- goto error;
- } else {
- if(wifi_is_connected_to_ap( ) != RTW_SUCCESS) {
- result = RTW_ERROR;
- goto error;
- }
- }
- }
- else
-#endif
- if(rtw_down_timeout_sema( &join_result->join_sema, RTW_JOIN_TIMEOUT ) == RTW_FALSE) {
- WIFI_CONF_MSG("RTW API: Join bss timeout\r\n");
- if(password_len) {
- rtw_free(join_result->network_info.password);
- }
- result = RTW_TIMEOUT;
- goto error;
- } else {
- if(join_result->network_info.password_len) {
- rtw_free(join_result->network_info.password);
- }
- if(wifi_is_connected_to_ap( ) != RTW_SUCCESS) {
- result = RTW_ERROR;
- goto error;
- }
- }
- }
-
- result = RTW_SUCCESS;
-
-#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT || CONFIG_JD_SMART
- restore_wifi_info_to_flash();
-#endif
-
-error:
- if(semaphore == NULL){
- rtw_free_sema( &join_semaphore);
- }
- join_user_data = NULL;
- rtw_free((u8*)join_result);
- wifi_unreg_event_handler(WIFI_EVENT_CONNECT, wifi_connected_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_NO_NETWORK,wifi_no_network_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, wifi_handshake_done_hdl);
- return result;
-}
-
-int wifi_connect_bssid(
- unsigned char bssid[ETH_ALEN],
- char *ssid,
- rtw_security_t security_type,
- char *password,
- int bssid_len,
- int ssid_len,
- int password_len,
- int key_id,
- void *semaphore)
-{
- _sema join_semaphore;
- rtw_result_t result = RTW_SUCCESS;
-
- if(rtw_join_status & JOIN_SIMPLE_CONFIG || rtw_join_status & JOIN_AIRKISS){
- return RTW_ERROR;
- }
-
- rtw_join_status = 0;//clear for last connect status
- error_flag = RTW_UNKNOWN;//clear for last connect status
- internal_join_result_t *join_result = (internal_join_result_t *)rtw_zmalloc(sizeof(internal_join_result_t));
- if(!join_result) {
- return RTW_NOMEM;
- }
- if(ssid_len && ssid){
- join_result->network_info.ssid.len = ssid_len > 32 ? 32 : ssid_len;
- rtw_memcpy(join_result->network_info.ssid.val, ssid, ssid_len);
- }
- rtw_memcpy(join_result->network_info.bssid.octet, bssid, bssid_len);
-
- if ( ( ( ( password_len > RTW_MAX_PSK_LEN ) ||
- ( password_len < RTW_MIN_PSK_LEN ) ) &&
- ( ( security_type == RTW_SECURITY_WPA_TKIP_PSK ) ||
- ( security_type == RTW_SECURITY_WPA_AES_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_AES_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_TKIP_PSK ) ||
- ( security_type == RTW_SECURITY_WPA2_MIXED_PSK ) ) )||
- (((password_len != 5)&& (password_len != 13))&&
- ((security_type == RTW_SECURITY_WEP_PSK)||
- (security_type ==RTW_SECURITY_WEP_SHARED ) ))) {
- return RTW_INVALID_KEY;
- }
- join_result->network_info.password_len = password_len;
- if(password_len) {
- /* add \0 to the end */
- join_result->network_info.password = rtw_zmalloc(password_len + 1);
- if(!join_result->network_info.password) {
- return RTW_NOMEM;
- }
- rtw_memcpy(join_result->network_info.password, password, password_len);
- }
-
- join_result->network_info.security_type = security_type;
- join_result->network_info.key_id = key_id;
-
- if(semaphore == NULL) {
- rtw_init_sema( &join_result->join_sema, 0 );
- if(!join_result->join_sema){
- return RTW_NORESOURCE;
- }
- join_semaphore = join_result->join_sema;
- } else {
- join_result->join_sema = semaphore;
- }
- wifi_reg_event_handler(WIFI_EVENT_NO_NETWORK,wifi_no_network_hdl,NULL);
- wifi_reg_event_handler(WIFI_EVENT_CONNECT, wifi_connected_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_DISCONNECT, wifi_disconn_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, wifi_handshake_done_hdl, NULL);
-
- wifi_connect_bssid_local(&join_result->network_info);
-
- join_user_data = join_result;
-
- if(semaphore == NULL) {
- if(rtw_down_timeout_sema( &join_result->join_sema, RTW_JOIN_TIMEOUT ) == RTW_FALSE) {
- WIFI_CONF_MSG("RTW API: Join bss timeout\r\n");
- if(password_len) {
- rtw_free(join_result->network_info.password);
- }
- rtw_free((u8*)join_result);
- rtw_free_sema( &join_semaphore);
- result = RTW_TIMEOUT;
- goto error;
- } else {
- rtw_free_sema( &join_semaphore );
- if(join_result->network_info.password_len) {
- rtw_free(join_result->network_info.password);
- }
- rtw_free((u8*)join_result);
- if( wifi_is_connected_to_ap( ) != RTW_SUCCESS) {
- result = RTW_ERROR;
- goto error;
- }
- }
- }
-
- result = RTW_SUCCESS;
-
-#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT || CONFIG_JD_SMART
- restore_wifi_info_to_flash();
-#endif
-
-error:
- join_user_data = NULL;
- wifi_unreg_event_handler(WIFI_EVENT_CONNECT, wifi_connected_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_NO_NETWORK,wifi_no_network_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, wifi_handshake_done_hdl);
- return result;
-}
-
-int wifi_disconnect(void)
-{
- int ret = 0;
-
- //set MAC address last byte to 1 since driver will filter the mac with all 0x00 or 0xff
- //add extra 2 zero byte for check of #@ in wext_set_bssid()
- const __u8 null_bssid[ETH_ALEN + 2] = {0, 0, 0, 0, 0, 1, 0, 0};
-
- if (wext_set_bssid(WLAN0_NAME, null_bssid) < 0){
- WIFI_CONF_MSG("\n\rWEXT: Failed to set bogus BSSID to disconnect");
- ret = -1;
- }
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_is_connected_to_ap( void )
-{
- return rltk_wlan_is_connected_to_ap();
-}
-
-//----------------------------------------------------------------------------//
-int wifi_is_up(rtw_interface_t interface)
-{
- if(interface == RTW_AP_INTERFACE) {
- if(wifi_mode == RTW_MODE_STA_AP) {
- return rltk_wlan_running(WLAN1_IDX);
- }
- }
-
- return rltk_wlan_running(WLAN0_IDX);
-}
-
-int wifi_is_ready_to_transceive(rtw_interface_t interface)
-{
- switch ( interface )
- {
- case RTW_AP_INTERFACE:
- return ( wifi_is_up(interface) == RTW_TRUE ) ? RTW_SUCCESS : RTW_ERROR;
-
- case RTW_STA_INTERFACE:
- switch ( error_flag)
- {
- case RTW_NO_ERROR:
- return RTW_SUCCESS;
-
- default:
- return RTW_ERROR;
- }
- default:
- return RTW_ERROR;
- }
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_mac_address(char * mac)
-{
- char buf[13+17+1];
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 13+17, "write_mac %s", mac);
- return wext_private_command(WLAN0_NAME, buf, 0);
-}
-
-int wifi_get_mac_address(char * mac)
-{
- int ret = 0;
- char buf[32];
- rtw_memset(buf, 0, sizeof(buf));
- rtw_memcpy(buf, "read_mac", 8);
- ret = wext_private_command_with_retval(WLAN0_NAME, buf, buf, 32);
- strcpy(mac, buf);
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_enable_powersave(void)
-{
- return wext_enable_powersave(WLAN0_NAME, 1, 1);
-}
-
-int wifi_disable_powersave(void)
-{
- return wext_disable_powersave(WLAN0_NAME);
-}
-
-#if 0 //Not ready
-//----------------------------------------------------------------------------//
-int wifi_get_txpower(int *poweridx)
-{
- int ret = 0;
- char buf[11];
-
- rtw_memset(buf, 0, sizeof(buf));
- rtw_memcpy(buf, "txpower", 11);
- ret = wext_private_command_with_retval(WLAN0_NAME, buf, buf, 11);
- sscanf(buf, "%d", poweridx);
-
- return ret;
-}
-
-int wifi_set_txpower(int poweridx)
-{
- int ret = 0;
- char buf[24];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 24, "txpower patha=%d", poweridx);
- ret = wext_private_command(WLAN0_NAME, buf, 0);
-
- return ret;
-}
-#endif
-
-//----------------------------------------------------------------------------//
-int wifi_get_associated_client_list(void * client_list_buffer, uint16_t buffer_length)
-{
- const char * ifname = WLAN0_NAME;
- int ret = 0;
- char buf[25];
-
- if(wifi_mode == RTW_MODE_STA_AP) {
- ifname = WLAN1_NAME;
- }
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 25, "get_client_list %x", client_list_buffer);
- ret = wext_private_command(ifname, buf, 0);
-
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_get_ap_info(rtw_bss_info_t * ap_info, rtw_security_t* security)
-{
- const char * ifname = WLAN0_NAME;
- int ret = 0;
- char buf[24];
-
- if(wifi_mode == RTW_MODE_STA_AP) {
- ifname = WLAN1_NAME;
- }
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 24, "get_ap_info %x", ap_info);
- ret = wext_private_command(ifname, buf, 0);
-
- snprintf(buf, 24, "get_security");
- ret = wext_private_command_with_retval(ifname, buf, buf, 24);
- sscanf(buf, "%lu", security);
-
- return ret;
-}
-
-int wifi_get_drv_ability(uint32_t *ability)
-{
- return wext_get_drv_ability(WLAN0_NAME, ability);
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_country(rtw_country_code_t country_code)
-{
- int ret;
-
- ret = wext_set_country(WLAN0_NAME, country_code);
-
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_channel_plan(uint8_t channel_plan)
-{
- const char * ifname = WLAN0_NAME;
- int ret = 0;
- char buf[24];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 24, "set_ch_plan %x", channel_plan);
- ret = wext_private_command(ifname, buf, 0);
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_get_rssi(int *pRSSI)
-{
- return wext_get_rssi(WLAN0_NAME, pRSSI);
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_channel(int channel)
-{
- return wext_set_channel(WLAN0_NAME, channel);
-}
-
-int wifi_get_channel(int *channel)
-{
- return wext_get_channel(WLAN0_NAME, (u8*)channel);
-}
-
-//----------------------------------------------------------------------------//
-int wifi_register_multicast_address(rtw_mac_t *mac)
-{
- return wext_register_multicast_address(WLAN0_NAME, mac);
-}
-
-int wifi_unregister_multicast_address(rtw_mac_t *mac)
-{
- return wext_unregister_multicast_address(WLAN0_NAME, mac);
-}
-
-//----------------------------------------------------------------------------//
-void wifi_set_mib(void)
-{
- // adaptivity
- wext_set_adaptivity(RTW_ADAPTIVITY_DISABLE);
-}
-
-//----------------------------------------------------------------------------//
-int wifi_rf_on(void)
-{
- int ret;
- ret = rltk_wlan_rf_on();
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_rf_off(void)
-{
- int ret;
- ret = rltk_wlan_rf_off();
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_on(rtw_mode_t mode)
-{
- int ret = 1;
- int timeout = 20;
- int idx;
- int devnum = 1;
- static int event_init = 0;
-
- if(rltk_wlan_running(WLAN0_IDX)) {
- WIFI_CONF_MSG("\n\rWIFI is already running");
- return 1;
- }
-
- if(event_init == 0){
- init_event_callback_list();
- event_init = 1;
- }
-
- wifi_mode = mode;
-
- if(mode == RTW_MODE_STA_AP)
- devnum = 2;
-
- // set wifi mib
- wifi_set_mib();
- WIFI_CONF_MSG("\n\rInitializing WIFI ...");
- for(idx=0;idx<devnum;idx++){
- ret = rltk_wlan_init(idx, mode);
- if(ret <0)
- return ret;
- }
- for(idx=0;idx<devnum;idx++){
- ret = rltk_wlan_start(idx);
- if(ret <0){
- WIFI_CONF_MSG("\n\rERROR: Start WIFI Failed!");
- rltk_wlan_deinit();
- return ret;
- }
- }
-
- while(1) {
- if(rltk_wlan_running(devnum-1)) {
- WIFI_CONF_MSG("\n\rWIFI initialized\n");
-
-
- /*
- * printf("set country code here\n");
- * wifi_set_country(RTW_COUNTRY_US);
- */
- break;
- }
-
- if(timeout == 0) {
- WIFI_CONF_MSG("\n\rERROR: Init WIFI timeout!");
- break;
- }
-
- rtw_msleep_os(1000);
- timeout --;
- }
-
- #if CONFIG_LWIP_LAYER
- #if !defined(CONFIG_MBED_ENABLED)
- netif_set_up(&xnetif[0]);
- if(mode == RTW_MODE_STA_AP) {
- netif_set_up(&xnetif[1]);
- }
- #endif
- #endif
-
-#if CONFIG_INIC_EN
- inic_start();
-#endif
-
- return ret;
-}
-
-int wifi_off(void)
-{
- int ret = 0;
- int timeout = 20;
-
- if((rltk_wlan_running(WLAN0_IDX) == 0) &&
- (rltk_wlan_running(WLAN1_IDX) == 0)) {
- WIFI_CONF_MSG("\n\rWIFI is not running");
- return 0;
- }
-#if CONFIG_LWIP_LAYER
-#ifndef CONFIG_MBED_ENABLED
- dhcps_deinit();
-#endif
-#if !defined(CONFIG_MBED_ENABLED)
- LwIP_DHCP(0, DHCP_STOP);
- netif_set_down(&xnetif[0]);
- netif_set_down(&xnetif[1]);
-#endif
-#endif
-#if defined(CONFIG_ENABLE_WPS_AP) && CONFIG_ENABLE_WPS_AP
- if((wifi_mode == RTW_MODE_AP) || (wifi_mode == RTW_MODE_STA_AP))
- wpas_wps_deinit();
-#endif
- WIFI_CONF_MSG("\n\rDeinitializing WIFI ...");
- rltk_wlan_deinit();
-
- while(1) {
- if((rltk_wlan_running(WLAN0_IDX) == 0) &&
- (rltk_wlan_running(WLAN1_IDX) == 0)) {
- WIFI_CONF_MSG("\n\rWIFI deinitialized");
- break;
- }
-
- if(timeout == 0) {
- WIFI_CONF_MSG("\n\rERROR: Deinit WIFI timeout!");
- break;
- }
-
- rtw_msleep_os(1000);
- timeout --;
- }
-
- wifi_mode = RTW_MODE_NONE;
-
-#if CONFIG_INIC_EN
- inic_stop();
-#endif
-
- return ret;
-}
-
-int wifi_off_fastly(void)
-{
-#if CONFIG_LWIP_LAYER
-#ifndef CONFIG_MBED_ENABLED
- dhcps_deinit();
-#endif
-#if !defined(CONFIG_MBED_ENABLED)
- LwIP_DHCP(0, DHCP_STOP);
-#endif
-#endif
- //printf("\n\rDeinitializing WIFI ...");
- rltk_wlan_deinit_fastly();
- return 0;
-}
-
-
-int wifi_set_power_mode(unsigned char ips_mode, unsigned char lps_mode)
-{
- return wext_enable_powersave(WLAN0_NAME, ips_mode, lps_mode);
-}
-
-int wifi_set_tdma_param(unsigned char slot_period, unsigned char rfon_period_len_1, unsigned char rfon_period_len_2, unsigned char rfon_period_len_3)
-{
- return wext_set_tdma_param(WLAN0_NAME, slot_period, rfon_period_len_1, rfon_period_len_2, rfon_period_len_3);
-}
-
-int wifi_set_lps_dtim(unsigned char dtim)
-{
- return wext_set_lps_dtim(WLAN0_NAME, dtim);
-}
-
-int wifi_get_lps_dtim(unsigned char *dtim)
-{
- return wext_get_lps_dtim(WLAN0_NAME, dtim);
-}
-//----------------------------------------------------------------------------//
-static void wifi_ap_sta_assoc_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- //USER TODO
-
-}
-static void wifi_ap_sta_disassoc_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- //USER TODO
-}
-
-int wifi_get_last_error(void)
-{
- return error_flag;
-}
-
-
-#if defined(CONFIG_ENABLE_WPS_AP) && CONFIG_ENABLE_WPS_AP
-int wpas_wps_init(const char* ifname);
-#endif
-
-int wifi_start_ap(
- char *ssid,
- rtw_security_t security_type,
- char *password,
- int ssid_len,
- int password_len,
- int channel)
-{
- const char *ifname = WLAN0_NAME;
- int ret = 0;
-
- if(wifi_mode == RTW_MODE_STA_AP) {
- ifname = WLAN1_NAME;
- }
-
- if(is_promisc_enabled())
- promisc_set(0, NULL, 0);
-
- wifi_reg_event_handler(WIFI_EVENT_STA_ASSOC, wifi_ap_sta_assoc_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_STA_DISASSOC, wifi_ap_sta_disassoc_hdl, NULL);
-
- ret = wext_set_mode(ifname, IW_MODE_MASTER);
- if(ret < 0) goto exit;
- ret = wext_set_channel(ifname, channel); //Set channel before starting ap
- if(ret < 0) goto exit;
-
- switch(security_type) {
- case RTW_SECURITY_OPEN:
- break;
- case RTW_SECURITY_WPA2_AES_PSK:
- ret = wext_set_auth_param(ifname, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(ifname, IW_ENCODE_ALG_CCMP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(ifname, (u8*)password, password_len);
- break;
- default:
- ret = -1;
- WIFI_CONF_MSG("\n\rWIFICONF: security type is not supported");
- break;
- }
- if(ret < 0) goto exit;
-
- ret = wext_set_ap_ssid(ifname, (u8*)ssid, ssid_len);
-#if defined(CONFIG_ENABLE_WPS_AP) && CONFIG_ENABLE_WPS_AP
- wpas_wps_init(ifname);
-#endif
-exit:
- return ret;
-}
-
-int wifi_start_ap_with_hidden_ssid(
- char *ssid,
- rtw_security_t security_type,
- char *password,
- int ssid_len,
- int password_len,
- int channel)
-{
- const char *ifname = WLAN0_NAME;
- int ret = 0;
-
- if(wifi_mode == RTW_MODE_STA_AP) {
- ifname = WLAN1_NAME;
- }
-
- if(is_promisc_enabled())
- promisc_set(0, NULL, 0);
-
- wifi_reg_event_handler(WIFI_EVENT_STA_ASSOC, wifi_ap_sta_assoc_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_STA_DISASSOC, wifi_ap_sta_disassoc_hdl, NULL);
-
- ret = wext_set_mode(ifname, IW_MODE_MASTER);
- if(ret < 0) goto exit;
- ret = wext_set_channel(ifname, channel); //Set channel before starting ap
- if(ret < 0) goto exit;
-
- switch(security_type) {
- case RTW_SECURITY_OPEN:
- break;
- case RTW_SECURITY_WPA2_AES_PSK:
- ret = wext_set_auth_param(ifname, IW_AUTH_80211_AUTH_ALG, IW_AUTH_ALG_OPEN_SYSTEM);
- if(ret == 0)
- ret = wext_set_key_ext(ifname, IW_ENCODE_ALG_CCMP, NULL, 0, 0, 0, 0, NULL, 0);
- if(ret == 0)
- ret = wext_set_passphrase(ifname, (u8*)password, password_len);
- break;
- default:
- ret = -1;
- WIFI_CONF_MSG("\n\rWIFICONF: security type is not supported");
- break;
- }
- if(ret < 0) goto exit;
-
- ret = set_hidden_ssid(ifname, 1);
- if(ret < 0) goto exit;
-
- ret = wext_set_ap_ssid(ifname, (u8*)ssid, ssid_len);
-#if defined(CONFIG_ENABLE_WPS_AP) && CONFIG_ENABLE_WPS_AP
- wpas_wps_init(ifname);
-#endif
-exit:
- return ret;
-}
-
-void wifi_scan_each_report_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- int i =0;
- int j =0;
- int insert_pos = 0;
- rtw_scan_result_t** result_ptr = (rtw_scan_result_t**)buf;
- rtw_scan_result_t* temp = NULL;
-
- for(i=0; i<scan_result_handler_ptr.scan_cnt; i++){
- if(CMP_MAC(scan_result_handler_ptr.pap_details[i]->BSSID.octet, (*result_ptr)->BSSID.octet)){
- if((*result_ptr)->signal_strength > scan_result_handler_ptr.pap_details[i]->signal_strength){
- temp = scan_result_handler_ptr.pap_details[i];
- for(j = i-1; j >= 0; j--){
- if(scan_result_handler_ptr.pap_details[j]->signal_strength >= (*result_ptr)->signal_strength)
- break;
- else
- scan_result_handler_ptr.pap_details[j+1] = scan_result_handler_ptr.pap_details[j];
- }
- scan_result_handler_ptr.pap_details[j+1] = temp;
- scan_result_handler_ptr.pap_details[j+1]->signal_strength = (*result_ptr)->signal_strength;
- }
- memset(*result_ptr, 0, sizeof(rtw_scan_result_t));
- return;
- }
- }
-
- scan_result_handler_ptr.scan_cnt++;
-
- if(scan_result_handler_ptr.scan_cnt > scan_result_handler_ptr.max_ap_size){
- scan_result_handler_ptr.scan_cnt = scan_result_handler_ptr.max_ap_size;
- if((*result_ptr)->signal_strength > scan_result_handler_ptr.pap_details[scan_result_handler_ptr.max_ap_size-1]->signal_strength){
- rtw_memcpy(scan_result_handler_ptr.pap_details[scan_result_handler_ptr.max_ap_size-1], *result_ptr, sizeof(rtw_scan_result_t));
- temp = scan_result_handler_ptr.pap_details[scan_result_handler_ptr.max_ap_size -1];
- }else
- return;
- }else{
- rtw_memcpy(&scan_result_handler_ptr.ap_details[scan_result_handler_ptr.scan_cnt-1], *result_ptr, sizeof(rtw_scan_result_t));
- }
-
- for(i=0; i< scan_result_handler_ptr.scan_cnt-1; i++){
- if((*result_ptr)->signal_strength > scan_result_handler_ptr.pap_details[i]->signal_strength)
- break;
- }
- insert_pos = i;
-
- for(i = scan_result_handler_ptr.scan_cnt-1; i>insert_pos; i--)
- scan_result_handler_ptr.pap_details[i] = scan_result_handler_ptr.pap_details[i-1];
-
- if(temp != NULL)
- scan_result_handler_ptr.pap_details[insert_pos] = temp;
- else
- scan_result_handler_ptr.pap_details[insert_pos] = &scan_result_handler_ptr.ap_details[scan_result_handler_ptr.scan_cnt-1];
- rtw_memset(*result_ptr, 0, sizeof(rtw_scan_result_t));
-}
-
-void wifi_scan_done_hdl( char* buf, int buf_len, int flags, void* userdata)
-{
- int i = 0;
- rtw_scan_handler_result_t scan_result_report;
-
- for(i=0; i<scan_result_handler_ptr.scan_cnt; i++){
- rtw_memcpy(&scan_result_report.ap_details, scan_result_handler_ptr.pap_details[i], sizeof(rtw_scan_result_t));
- scan_result_report.scan_complete = scan_result_handler_ptr.scan_complete;
- scan_result_report.user_data = scan_result_handler_ptr.user_data;
- (*scan_result_handler_ptr.gscan_result_handler)(&scan_result_report);
- }
-
- scan_result_handler_ptr.scan_complete = RTW_TRUE;
- scan_result_report.scan_complete = RTW_TRUE;
- (*scan_result_handler_ptr.gscan_result_handler)(&scan_result_report);
-
- rtw_free(scan_result_handler_ptr.ap_details);
- rtw_free(scan_result_handler_ptr.pap_details);
-#if SCAN_USE_SEMAPHORE
- rtw_up_sema(&scan_result_handler_ptr.scan_semaphore);
-#else
- scan_result_handler_ptr.scan_running = 0;
-#endif
- wifi_unreg_event_handler(WIFI_EVENT_SCAN_RESULT_REPORT, wifi_scan_each_report_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_SCAN_DONE, wifi_scan_done_hdl);
- return;
-}
-
-//int rtk_wifi_scan(char *buf, int buf_len, xSemaphoreHandle * semaphore)
-int wifi_scan(rtw_scan_type_t scan_type,
- rtw_bss_type_t bss_type,
- void* result_ptr)
-{
- int ret;
- scan_buf_arg * pscan_buf;
- u16 flags = scan_type | (bss_type << 8);
- if(result_ptr != NULL){
- pscan_buf = (scan_buf_arg *)result_ptr;
- ret = wext_set_scan(WLAN0_NAME, (char*)pscan_buf->buf, pscan_buf->buf_len, flags);
- }else{
- wifi_reg_event_handler(WIFI_EVENT_SCAN_RESULT_REPORT, wifi_scan_each_report_hdl, NULL);
- wifi_reg_event_handler(WIFI_EVENT_SCAN_DONE, wifi_scan_done_hdl, NULL);
- ret = wext_set_scan(WLAN0_NAME, NULL, 0, flags);
- }
-
- if(ret == 0) {
- if(result_ptr != NULL){
- ret = wext_get_scan(WLAN0_NAME, pscan_buf->buf, pscan_buf->buf_len);
- }
- }
- else if(ret == -1){
- if(result_ptr == NULL){
- wifi_unreg_event_handler(WIFI_EVENT_SCAN_RESULT_REPORT, wifi_scan_each_report_hdl);
- wifi_unreg_event_handler(WIFI_EVENT_SCAN_DONE, wifi_scan_done_hdl);
- }
- }
- return ret;
-}
-
-int wifi_scan_networks_with_ssid(int (results_handler)(char*buf, int buflen, char *ssid, void *user_data),
- OUT void* user_data, IN int scan_buflen, IN char* ssid, IN int ssid_len)
-{
- int scan_cnt = 0, add_cnt = 0;
- scan_buf_arg scan_buf;
- int ret;
-
- scan_buf.buf_len = scan_buflen;
- scan_buf.buf = (char*)rtw_malloc(scan_buf.buf_len);
- if(!scan_buf.buf){
- WIFI_CONF_MSG("\n\rERROR: Can't malloc memory(%d)", scan_buf.buf_len);
- return RTW_NOMEM;
- }
- //set ssid
- memset(scan_buf.buf, 0, scan_buf.buf_len);
- memcpy(scan_buf.buf, &ssid_len, sizeof(int));
- memcpy(scan_buf.buf+sizeof(int), ssid, ssid_len);
-
- //Scan channel
- scan_cnt = wifi_scan(RTW_SCAN_TYPE_ACTIVE, RTW_BSS_TYPE_ANY, &scan_buf);
- if(scan_cnt < 0){
- WIFI_CONF_MSG("\n\rERROR: wifi scan failed");
- ret = RTW_ERROR;
- }else{
- if(NULL == results_handler)
- {
- int plen = 0;
- while(plen < scan_buf.buf_len){
- int len, rssi, ssid_len, i, security_mode;
- int wps_password_id;
- char *mac, *ssid;
- //u8 *security_mode;
- printf("\n\r");
- // len
- len = (int)*(scan_buf.buf + plen);
- printf("len = %d,\t", len);
- // check end
- if(len == 0) break;
- // mac
- mac = scan_buf.buf + plen + 1;
- printf("mac = ");
- for(i=0; i<6; i++)
- printf("%02x ", (u8)*(mac+i));
- printf(",\t");
- // rssi
- rssi = *(int*)(scan_buf.buf + plen + 1 + 6);
- printf(" rssi = %d,\t", rssi);
- // security_mode
- security_mode = (int)*(scan_buf.buf + plen + 1 + 6 + 4);
- switch (security_mode) {
- case IW_ENCODE_ALG_NONE:
- printf("sec = open ,\t");
- break;
- case IW_ENCODE_ALG_WEP:
- printf("sec = wep ,\t");
- break;
- case IW_ENCODE_ALG_CCMP:
- printf("sec = wpa/wpa2,\t");
- break;
- }
- // password id
- wps_password_id = (int)*(scan_buf.buf + plen + 1 + 6 + 4 + 1);
- printf("wps password id = %d,\t", wps_password_id);
-
- printf("channel = %d,\t", *(scan_buf.buf + plen + 1 + 6 + 4 + 1 + 1));
- // ssid
- ssid_len = len - 1 - 6 - 4 - 1 - 1 - 1;
- ssid = scan_buf.buf + plen + 1 + 6 + 4 + 1 + 1 + 1;
- printf("ssid = ");
- for(i=0; i<ssid_len; i++)
- printf("%c", *(ssid+i));
- plen += len;
- add_cnt++;
- }
-
- printf("\n\rwifi_scan: add count = %d, scan count = %d", add_cnt, scan_cnt);
- }
- ret = RTW_SUCCESS;
- }
- if(results_handler)
- results_handler(scan_buf.buf, scan_buf.buf_len, ssid, user_data);
-
- if(scan_buf.buf)
- rtw_mfree((u8 *)scan_buf.buf, scan_buf.buf_len);
-
- return ret;
-}
-
-int wifi_scan_networks(rtw_scan_result_handler_t results_handler, void* user_data)
-{
- unsigned int max_ap_size = 64;
-
- /* lock 2s to forbid suspend under scan */
- rtw_wakelock_timeout(2*1000);
-
-#if SCAN_USE_SEMAPHORE
- rtw_bool_t result;
- if(NULL == scan_result_handler_ptr.scan_semaphore)
- rtw_init_sema(&scan_result_handler_ptr.scan_semaphore, 1);
-
- scan_result_handler_ptr.scan_start_time = rtw_get_current_time();
- /* Initialise the semaphore that will prevent simultaneous access - cannot be a mutex, since
- * we don't want to allow the same thread to start a new scan */
- result = (rtw_bool_t)rtw_down_timeout_sema(&scan_result_handler_ptr.scan_semaphore, SCAN_LONGEST_WAIT_TIME);
- if ( result != RTW_TRUE )
- {
- /* Return error result, but set the semaphore to work the next time */
- rtw_up_sema(&scan_result_handler_ptr.scan_semaphore);
- return RTW_TIMEOUT;
- }
-#else
- if(scan_result_handler_ptr.scan_running){
- int count = 100;
- while(scan_result_handler_ptr.scan_running && count > 0)
- {
- rtw_msleep_os(20);
- count --;
- }
- if(count == 0){
- WIFI_CONF_MSG("\n\r[%d]WiFi: Scan is running. Wait 2s timeout.", rtw_get_current_time());
- return RTW_TIMEOUT;
- }
- }
- scan_result_handler_ptr.scan_start_time = rtw_get_current_time();
- scan_result_handler_ptr.scan_running = 1;
-#endif
-
- scan_result_handler_ptr.gscan_result_handler = results_handler;
-
- scan_result_handler_ptr.max_ap_size = max_ap_size;
- scan_result_handler_ptr.ap_details = (rtw_scan_result_t*)rtw_zmalloc(max_ap_size*sizeof(rtw_scan_result_t));
- if(scan_result_handler_ptr.ap_details == NULL){
- goto err_exit;
- }
- rtw_memset(scan_result_handler_ptr.ap_details, 0, max_ap_size*sizeof(rtw_scan_result_t));
-
- scan_result_handler_ptr.pap_details = (rtw_scan_result_t**)rtw_zmalloc(max_ap_size*sizeof(rtw_scan_result_t*));
- if(scan_result_handler_ptr.pap_details == NULL)
- goto error2_with_result_ptr;
- rtw_memset(scan_result_handler_ptr.pap_details, 0, max_ap_size);
-
- scan_result_handler_ptr.scan_cnt = 0;
-
- scan_result_handler_ptr.scan_complete = RTW_FALSE;
- scan_result_handler_ptr.user_data = user_data;
-
- if (wifi_scan( RTW_SCAN_COMMAMD<<4 | RTW_SCAN_TYPE_ACTIVE, RTW_BSS_TYPE_ANY, NULL) != RTW_SUCCESS)
- {
- goto error1_with_result_ptr;
- }
-
- return RTW_SUCCESS;
-
-error1_with_result_ptr:
- rtw_free((u8*)scan_result_handler_ptr.pap_details);
- scan_result_handler_ptr.pap_details = NULL;
-
-error2_with_result_ptr:
- rtw_free((u8*)scan_result_handler_ptr.ap_details);
- scan_result_handler_ptr.ap_details = NULL;
-
-err_exit:
- rtw_memset((void *)&scan_result_handler_ptr, 0, sizeof(scan_result_handler_ptr));
- return RTW_ERROR;
-}
-//----------------------------------------------------------------------------//
-int wifi_set_pscan_chan(__u8 * channel_list,__u8 * pscan_config, __u8 length)
-{
- if(channel_list)
- return wext_set_pscan_channel(WLAN0_NAME, channel_list, pscan_config, length);
- else
- return -1;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_get_setting(const char *ifname, rtw_wifi_setting_t *pSetting)
-{
- int ret = 0;
- int mode = 0;
- unsigned short security = 0;
-
- memset(pSetting, 0, sizeof(rtw_wifi_setting_t));
- if(wext_get_mode(ifname, &mode) < 0)
- ret = -1;
-
- switch(mode) {
- case IW_MODE_MASTER:
- pSetting->mode = RTW_MODE_AP;
- break;
- case IW_MODE_INFRA:
- default:
- pSetting->mode = RTW_MODE_STA;
- break;
- //default:
- //printf("\r\n%s(): Unknown mode %d\n", __func__, mode);
- //break;
- }
-
- if(wext_get_ssid(ifname, pSetting->ssid) < 0)
- ret = -1;
- if(wext_get_channel(ifname, &pSetting->channel) < 0)
- ret = -1;
- if(wext_get_enc_ext(ifname, &security, &pSetting->key_idx, pSetting->password) < 0)
- ret = -1;
-
- switch(security){
- case IW_ENCODE_ALG_NONE:
- pSetting->security_type = RTW_SECURITY_OPEN;
- break;
- case IW_ENCODE_ALG_WEP:
- pSetting->security_type = RTW_SECURITY_WEP_PSK;
- break;
- case IW_ENCODE_ALG_TKIP:
- pSetting->security_type = RTW_SECURITY_WPA_TKIP_PSK;
- break;
- case IW_ENCODE_ALG_CCMP:
- pSetting->security_type = RTW_SECURITY_WPA2_AES_PSK;
- break;
- default:
- break;
- }
-
- if(security == IW_ENCODE_ALG_TKIP || security == IW_ENCODE_ALG_CCMP)
- if(wext_get_passphrase(ifname, pSetting->password) < 0)
- ret = -1;
-
- return ret;
-}
-//----------------------------------------------------------------------------//
-int wifi_show_setting(const char *ifname, rtw_wifi_setting_t *pSetting)
-{
- int ret = 0;
-
- printf("\n\r\nWIFI %s Setting:",ifname);
- printf("\n\r==============================");
-
- switch(pSetting->mode) {
- case RTW_MODE_AP:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("\r\nAP,");
-#endif
- printf("\n\r MODE => AP");
- break;
- case RTW_MODE_STA:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("\r\nSTA,");
-#endif
- printf("\n\r MODE => STATION");
- break;
- default:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("\r\nUNKNOWN,");
-#endif
- printf("\n\r MODE => UNKNOWN");
- }
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("%s,%d,", pSetting->ssid, pSetting->channel);
-#endif
- printf("\n\r SSID => %s", pSetting->ssid);
- printf("\n\r CHANNEL => %d", pSetting->channel);
-
- switch(pSetting->security_type) {
- case RTW_SECURITY_OPEN:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("OPEN,");
-#endif
- printf("\n\r SECURITY => OPEN");
- break;
- case RTW_SECURITY_WEP_PSK:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("WEP,%d,", pSetting->key_idx);
-#endif
- printf("\n\r SECURITY => WEP");
- printf("\n\r KEY INDEX => %d", pSetting->key_idx);
- break;
- case RTW_SECURITY_WPA_TKIP_PSK:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("TKIP,");
-#endif
- printf("\n\r SECURITY => TKIP");
- break;
- case RTW_SECURITY_WPA2_AES_PSK:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("AES,");
-#endif
- printf("\n\r SECURITY => AES");
- break;
- default:
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("UNKNOWN,");
-#endif
- printf("\n\r SECURITY => UNKNOWN");
- }
-
-#if CONFIG_EXAMPLE_UART_ATCMD
- at_printf("%s,", pSetting->password);
-#endif
- printf("\n\r PASSWORD => %s", pSetting->password);
- printf("\n\r");
-
- return ret;
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_network_mode(rtw_network_mode_t mode)
-{
- if((mode == RTW_NETWORK_B) || (mode == RTW_NETWORK_BG) || (mode == RTW_NETWORK_BGN))
- return rltk_wlan_wireless_mode((unsigned char) mode);
-
- return -1;
-}
-
-int wifi_set_wps_phase(unsigned char is_trigger_wps)
-{
- return rltk_wlan_set_wps_phase(is_trigger_wps);
-}
-
-//----------------------------------------------------------------------------//
-int wifi_set_promisc(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used)
-{
- return promisc_set(enabled, callback, len_used);
-}
-
-void wifi_enter_promisc_mode(){
- int mode = 0;
- unsigned char ssid[33];
-
- if(wifi_mode == RTW_MODE_STA_AP){
- wifi_off();
- rtw_msleep_os(20);
- wifi_on(RTW_MODE_PROMISC);
- }else{
- wext_get_mode(WLAN0_NAME, &mode);
-
- switch(mode) {
- case IW_MODE_MASTER: //In AP mode
- //rltk_wlan_deinit();
- wifi_off();//modified by Chris Yang for iNIC
- rtw_msleep_os(20);
- //rltk_wlan_init(0, RTW_MODE_PROMISC);
- //rltk_wlan_start(0);
- wifi_on(RTW_MODE_PROMISC);
- break;
- case IW_MODE_INFRA: //In STA mode
- if(wext_get_ssid(WLAN0_NAME, ssid) > 0)
- wifi_disconnect();
- }
- }
-}
-
-int wifi_restart_ap(
- unsigned char *ssid,
- rtw_security_t security_type,
- unsigned char *password,
- int ssid_len,
- int password_len,
- int channel)
-{
- unsigned char idx = 0;
-#if !defined(CONFIG_MBED_ENABLED)
- ip_addr_t ipaddr;
- ip_addr_t netmask;
- ip_addr_t gw;
- struct netif * pnetif = &xnetif[0];
-#endif
-#ifdef CONFIG_CONCURRENT_MODE
- rtw_wifi_setting_t setting;
- int sta_linked = 0;
-#endif
-
- if(rltk_wlan_running(WLAN1_IDX)){
- idx = 1;
- }
-
- // stop dhcp server
- dhcps_deinit();
-
-#ifdef CONFIG_CONCURRENT_MODE
- if(idx > 0){
- sta_linked = wifi_get_setting(WLAN0_NAME, &setting);
- wifi_off();
- rtw_msleep_os(20);
- wifi_on(RTW_MODE_STA_AP);
- }
- else
-#endif
- {
-#if !defined(CONFIG_MBED_ENABLED)
- IP4_ADDR(&ipaddr, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
- IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1 , NETMASK_ADDR2, NETMASK_ADDR3);
- IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
- netif_set_addr(pnetif, &ipaddr, &netmask,&gw);
-#endif
- wifi_off();
- rtw_msleep_os(20);
- wifi_on(RTW_MODE_AP);
- }
- // start ap
- if(wifi_start_ap((char*)ssid, security_type, (char*)password, ssid_len, password_len, channel) < 0) {
- WIFI_CONF_MSG("\n\rERROR: Operation failed!");
- return -1;
- }
-
-#if (INCLUDE_uxTaskGetStackHighWaterMark == 1)
- printf("\r\nWebServer Thread: High Water Mark is %ld\n", uxTaskGetStackHighWaterMark(NULL));
-#endif
-#ifdef CONFIG_CONCURRENT_MODE
- // connect to ap if wlan0 was linked with ap
- if(idx > 0 && sta_linked == 0){
-#if CONFIG_DHCP_CLIENT
- int ret;
-#endif
- printf("\r\nAP: ssid=%s", (char*)setting.ssid);
- printf("\r\nAP: security_type=%d", setting.security_type);
- printf("\r\nAP: password=%s", (char*)setting.password);
- printf("\r\nAP: key_idx =%d\n", setting.key_idx);
-#if CONFIG_DHCP_CLIENT
- ret =
-#endif
- wifi_connect((char*)setting.ssid,
- setting.security_type,
- (char*)setting.password,
- strlen((char*)setting.ssid),
- strlen((char*)setting.password),
- setting.key_idx,
- NULL);
-#if CONFIG_DHCP_CLIENT
- if(ret == RTW_SUCCESS) {
- /* Start DHCPClient */
- LwIP_DHCP(0, DHCP_START);
- }
-#endif
- }
-#endif
-#if (INCLUDE_uxTaskGetStackHighWaterMark == 1)
- printf("\r\nWebServer Thread: High Water Mark is %ld\n", uxTaskGetStackHighWaterMark(NULL));
-#endif
-#if !defined(CONFIG_MBED_ENABLED)
- // start dhcp server
- dhcps_init(&xnetif[idx]);
-#endif
- return 0;
-}
-
-#if CONFIG_AUTO_RECONNECT
-struct task_struct g_wifi_auto_reconnect_task;
-
-extern void (*p_wlan_autoreconnect_hdl)(rtw_security_t, char*, int, char*, int, int);
-
-struct wifi_autoreconnect_param {
- rtw_security_t security_type;
- char *ssid;
- int ssid_len;
- char *password;
- int password_len;
- int key_id;
-};
-
-static void wifi_autoreconnect_thread(void *param)
-{
-#if !defined(CONFIG_MBED_ENABLED) && CONFIG_LWIP_LAYER
- int ret = RTW_ERROR;
-#endif
- struct wifi_autoreconnect_param *reconnect_param = (struct wifi_autoreconnect_param *) param;
- WIFI_CONF_MSG("\n\rauto reconnect ...\n");
-#if !defined(CONFIG_MBED_ENABLED) && CONFIG_LWIP_LAYER
- ret =
-#endif
- wifi_connect(reconnect_param->ssid,
- reconnect_param->security_type,
- reconnect_param->password,
- reconnect_param->ssid_len,
- reconnect_param->password_len,
- reconnect_param->key_id,
- NULL);
-#if !defined(CONFIG_MBED_ENABLED) && CONFIG_LWIP_LAYER
- if(ret == RTW_SUCCESS) {
-#if ATCMD_VER == ATVER_2
- if (dhcp_mode_sta == 2){
- struct netif * pnetif = &xnetif[0];
- LwIP_UseStaticIP(pnetif);
- dhcps_init(pnetif);
- }
- else
-#endif
- {
- LwIP_DHCP(0, DHCP_START);
-#if LWIP_AUTOIP
- uint8_t *ip = LwIP_GetIP(&xnetif[0]);
- if((ip[0] == 0) && (ip[1] == 0) && (ip[2] == 0) && (ip[3] == 0)) {
- WIFI_CONF_MSG("\n\nIPv4 AUTOIP ...");
- LwIP_AUTOIP(&xnetif[0]);
- }
-#endif
- }
- }
-#endif
- rtw_delete_task(&g_wifi_auto_reconnect_task);
-}
-
-void wifi_autoreconnect_hdl(rtw_security_t security_type,
- char *ssid, int ssid_len,
- char *password, int password_len,
- int key_id)
-{
- static struct wifi_autoreconnect_param param;
- param.security_type = security_type;
- param.ssid = ssid;
- param.ssid_len = ssid_len;
- param.password = password;
- param.password_len = password_len;
- param.key_id = key_id;
-
- if(!rtw_create_task(&g_wifi_auto_reconnect_task,"wifi_autoreconnect",512,TASK_PRORITY_IDEL+1,wifi_autoreconnect_thread, ¶m))
- WIFI_CONF_MSG("\n\rTCP ERROR: Create TCP server task failed.");
-}
-
-int wifi_config_autoreconnect(__u8 mode, __u8 retry_times, __u16 timeout)
-{
- p_wlan_autoreconnect_hdl = wifi_autoreconnect_hdl;
- return wext_set_autoreconnect(WLAN0_NAME, mode, retry_times, timeout);
-}
-
-int wifi_set_autoreconnect(__u8 mode)
-{
- p_wlan_autoreconnect_hdl = wifi_autoreconnect_hdl;
- return wifi_config_autoreconnect(mode, 3, 5);//default retry 3 times, timeout 5 seconds
-}
-
-int wifi_get_autoreconnect(__u8 *mode)
-{
- return wext_get_autoreconnect(WLAN0_NAME, mode);
-}
-#endif
-
-#ifdef CONFIG_CUSTOM_IE
-/*
- * Example for custom ie
- *
- * u8 test_1[] = {221, 2, 2, 2};
- * u8 test_2[] = {221, 2, 1, 1};
- * rtw_custom_ie_t buf[2] = {{test_1, PROBE_REQ},
- * {test_2, PROBE_RSP | BEACON}};
- * u8 buf_test2[] = {221, 2, 1, 3} ;
- * rtw_custom_ie_t buf_update = {buf_test2, PROBE_REQ};
- *
- * add ie list
- * static void cmd_add_ie(int argc, char **argv)
- * {
- * wifi_add_custom_ie((void *)buf, 2);
- * }
- *
- * update current ie
- * static void cmd_update_ie(int argc, char **argv)
- * {
- * wifi_update_custom_ie(&buf_update, 2);
- * }
- *
- * delete all ie
- * static void cmd_del_ie(int argc, char **argv)
- * {
- * wifi_del_custom_ie();
- * }
- */
-
-int wifi_add_custom_ie(void *cus_ie, int ie_num)
-{
- return wext_add_custom_ie(WLAN0_NAME, cus_ie, ie_num);
-}
-
-
-int wifi_update_custom_ie(void *cus_ie, int ie_index)
-{
- return wext_update_custom_ie(WLAN0_NAME, cus_ie, ie_index);
-}
-
-int wifi_del_custom_ie()
-{
- return wext_del_custom_ie(WLAN0_NAME);
-}
-
-#endif
-
-#ifdef CONFIG_PROMISC
-extern void promisc_init_packet_filter(void);
-extern int promisc_add_packet_filter(u8 filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule);
-extern int promisc_enable_packet_filter(u8 filter_id);
-extern int promisc_disable_packet_filter(u8 filter_id);
-extern int promisc_remove_packet_filter(u8 filter_id);
-void wifi_init_packet_filter()
-{
- promisc_init_packet_filter();
-}
-
-int wifi_add_packet_filter(unsigned char filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule)
-{
- return promisc_add_packet_filter(filter_id, patt, rule);
-}
-
-int wifi_enable_packet_filter(unsigned char filter_id)
-{
- return promisc_enable_packet_filter(filter_id);
-}
-
-int wifi_disable_packet_filter(unsigned char filter_id)
-{
- return promisc_disable_packet_filter(filter_id);
-}
-
-int wifi_remove_packet_filter(unsigned char filter_id)
-{
- return promisc_remove_packet_filter(filter_id);
-}
-#endif
-
-#ifdef CONFIG_AP_MODE
-int wifi_enable_forwarding(void)
-{
- return wext_enable_forwarding(WLAN0_NAME);
-}
-
-int wifi_disable_forwarding(void)
-{
- return wext_disable_forwarding(WLAN0_NAME);
-}
-#endif
-
-/* API to set flag for concurrent mode wlan1 issue_deauth when channel switched by wlan0
- * usage: wifi_set_ch_deauth(0) -> wlan0 wifi_connect -> wifi_set_ch_deauth(1)
- */
-#ifdef CONFIG_CONCURRENT_MODE
-int wifi_set_ch_deauth(__u8 enable)
-{
- return wext_set_ch_deauth(WLAN1_NAME, enable);
-}
-#endif
-
-void wifi_set_indicate_mgnt(int enable)
-{
- wext_set_indicate_mgnt(enable);
- return;
-}
-
-//----------------------------------------------------------------------------//
-#endif //#if CONFIG_WLAN
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_conf.h Thu Nov 08 11:46:34 2018 +0000
@@ -12,26 +12,31 @@
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- *
- ******************************************************************************
- * @file wifi_conf.h
- * @author
- * @version
- * @brief This file provides user interface for Wi-Fi station and AP mode configuration
- * base on the functionalities provided by Realtek Wi-Fi driver.
- ******************************************************************************
*/
+
+/**
+ ******************************************************************************
+ * @file wifi_conf.h
+ * @author
+ * @version
+ * @brief This file provides user interface for Wi-Fi station and AP mode configuration
+ * base on the functionalities provided by Realtek Wi-Fi driver.
+ ******************************************************************************
+ */
#ifndef __WIFI_API_H
#define __WIFI_API_H
-#include "osdep_service.h"
-#include "wifi_constants.h"
-#include "wifi_structures.h"
-#include "wifi_util.h"
-#include "wifi_ind.h"
-#ifndef CONFIG_MBED_ENABLED
+/** @addtogroup nic NIC
+ * @ingroup wlan
+ * @brief NIC functions
+ * @{
+ */
+
+#include "wifi_constants.h"
+#include "wifi_structures.h"
+#include "wifi_util.h"
+#include "wifi_ind.h"
#include <platform/platform_stdlib.h>
-#endif
#ifdef __cplusplus
extern "C" {
@@ -44,7 +49,15 @@
#define RTW_ENABLE_API_INFO
#ifdef RTW_ENABLE_API_INFO
- #define RTW_API_INFO(args) do {printf args;} while(0)
+#if defined(CONFIG_MBED_ENABLED)
+ extern __u32 GlobalDebugEnable;
+ #define RTW_API_INFO(...) do {\
+ if (GlobalDebugEnable) \
+ printf(__VA_ARGS__);\
+ }while(0)
+#else
+ #define RTW_API_INFO printf
+#endif
#else
#define RTW_API_INFO(args)
#endif
@@ -225,18 +238,6 @@
* RTW_STA_INTERFACE, RTW_AP_INTERFACE
* @return RTW_SUCCESS : if the interface is ready to
* transceive ethernet packets
- * @return RTW_NOTFOUND : no AP with a matching SSID was
- * found
- * @return RTW_NOT_AUTHENTICATED: a matching AP was found but
- * it won't let you
- * authenticate. This can
- * occur if this device is
- * in the block list on the
- * AP.
- * @return RTW_NOT_KEYED: the device has authenticated and
- * associated but has not completed
- * the key exchange. This can occur
- * if the passphrase is incorrect.
* @return RTW_ERROR : if the interface is not ready to
* transceive ethernet packets
*/
@@ -298,6 +299,14 @@
int wifi_get_associated_client_list(void * client_list_buffer, unsigned short buffer_length);
/**
+ * @brief Get connected AP's BSSID
+ * @param[out] bssid : the location where the AP BSSID will be stored
+ * @return RTW_SUCCESS : if result was successfully get
+ * @return RTW_ERROR : if result was not successfully get
+ */
+int wifi_get_ap_bssid(unsigned char *bssid);
+
+/**
* @brief Get the SoftAP information.
* @param[out] ap_info: The location where the AP info will be stored.
* @param[out] security: The security type.
@@ -315,6 +324,15 @@
int wifi_set_country(rtw_country_code_t country_code);
/**
+ * @brief retrieved sta mode MAX data rate.
+ * @param[out] inidata_rate: MAX data rate.
+ * @return RTW_SUCCESS: If the INIDATA_RATE is successfully retrieved.
+ * @return RTW_ERROR: If the INIDATA_RATE is not retrieved.
+ * note: inidata_rate = 2 * (data rate), you need inidata_rate/2.0 to get the real rate
+ */
+int wifi_get_sta_max_data_rate(__u8 * inidata_rate);
+
+/**
* @brief Retrieve the latest RSSI value.
* @param[out] pRSSI: Points to the integer to store the RSSI value gotten from driver.
* @return RTW_SUCCESS: If the RSSI is succesfully retrieved.
@@ -362,11 +380,21 @@
int wifi_unregister_multicast_address(rtw_mac_t *mac);
/**
- * @brief Disable the adaptivity mode.
+ * @brief Setup the adaptivity mode.
+ * You can replace this weak function by the same name funcation to setup adaptivity mode you want.
* @param None
* @return If the function succeeds, the return value is 0.
*/
-void wifi_set_mib(void);
+_WEAK void wifi_set_mib(void);
+
+/**
+ * @brief Setup country code.
+ * You can replace this weak function by the same name funcation to setup country code you want.
+ * @param None
+ * @return If the function succeeds, the return value is 0.
+ */
+//----------------------------------------------------------------------------//
+_WEAK void wifi_set_country_code(void);
/**
* @brief Enable Wi-Fi RF.
@@ -621,18 +649,30 @@
int wifi_set_network_mode(rtw_network_mode_t mode);
/**
+ * @brief Get the network mode.
+ * Driver works in BGN mode in default after driver initialization. This function is used to
+ * get the current wireless network mode for station mode.
+ * @param[in] pmode: Network mode to get.
+ * @return RTW_SUCCESS or RTW_ERROR.
+ */
+int wifi_get_network_mode(rtw_network_mode_t *pmode);
+
+/**
* @brief Set the chip to start or stop the promiscuous mode.
- * @param[in] enabled: enabled can be set 0, 1 and 2. if enabled is zero, disable the promisc, else enable the promisc.
+ * @param[in] enabled: enabled can be set 0, 1, 2, 3 and 4. if enabled is zero, disable the promisc, else enable the promisc.
* - 0 means disable the promisc.
- * - 1 means enable the promisc.
- * - 2 means enable the promisc special for length is used.
+ * - 1 means enable the promisc special for all ethernet frames.
+ * - 2 means enable the promisc special for Broadcast/Multicast ethernet frames.
+ * - 3 means enable the promisc special for all 802.11 frames.
+ * - 4 means enable the promisc special for Broadcast/Multicast 802.11 frames.
* @param[in] callback: the callback function which will
* receive and process the netowork data.
- * @param[in] len_used: specify if the the promisc length is used.
- * If len_used set to 1, packet length will be saved and transferred to callback function.
+ * @param[in] len_used: specify if the the promisc data length is used.
+ * If len_used set to 1, packet(frame data) length will be saved and transferred to callback function.
*
* @return RTW_SUCCESS or RTW_ERROR
* @note This function can be used to implement vendor specified simple configure.
+ * @note To fetch Ethernet frames, the len_used should be set to 1
*/
int wifi_set_promisc(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used);
@@ -726,7 +766,6 @@
*/
int wifi_get_last_error(void);
-
#ifdef CONFIG_CUSTOM_IE
#ifndef BIT
#define BIT(x) ((__u32)1 << (x))
@@ -742,7 +781,7 @@
PROBE_RSP = BIT(1),
BEACON = BIT(2),
};
-typedef uint32_t rtw_custom_ie_type_t;
+typedef __u32 rtw_custom_ie_type_t;
#endif /* _CUSTOM_IE_TYPE_ */
/* ie format
@@ -837,13 +876,79 @@
int wifi_remove_packet_filter(unsigned char filter_id);
#endif
+/**
+ * @brief Get antenna infomation.
+ * @param[in] antenna: Points to store the antenna value gotten from driver, 0: main, 1: aux.
+ * @return 0 if success, otherwise return -1.
+ */
+#ifdef CONFIG_ANTENNA_DIVERSITY
+int wifi_get_antenna_info(unsigned char *antenna);
+#endif // #ifdef CONFIG_ANTENNA_DIVERSITY
+
void wifi_set_indicate_mgnt(int enable);
+/**
+ * @brief Get the information of MP driver
+ * @param[out] ability : 0x1 stand for mp driver, and 0x0 stand for normal driver
+ * @return RTW_SUCCESS
+ */
+int wifi_get_drv_ability(uint32_t *ability);
+
+/**
+ * @brief Set channel plan into flash/efuse, must reboot after setting channel plan
+ * @param[in] channel_plan : the value of channel plan, define in wifi_constants.h
+ * @return RTW_SUCCESS or RTW_ERROR
+ */
+int wifi_set_channel_plan(uint8_t channel_plan);
+
+/**
+ * @brief Get channel plan from calibration section
+ * @param[out] channel_plan : point to the value of channel plan, define in wifi_constants.h
+ * @return RTW_SUCCESS or RTW_ERROR
+ */
+int wifi_get_channel_plan(uint8_t *channel_plan);
+
+#ifdef CONFIG_AP_MODE
+/**
+ * @brief Enable packets forwarding in ap mode
+ * @return RTW_SUCCESS
+ */
+int wifi_enable_forwarding(void);
+
+/**
+ * @brief Disable packets forwarding in ap mode
+ * @return RTW_SUCCESS
+ */
+int wifi_disable_forwarding(void);
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+/**
+ * @brief Set flag for concurrent mode wlan1 issue_deauth when channel switched by wlan0
+ * usage: wifi_set_ch_deauth(0) -> wlan0 wifi_connect -> wifi_set_ch_deauth(1)
+ * @param[in] enable : 0 for disable and 1 for enable
+ * @return RTW_SUCCESS
+ */
+int wifi_set_ch_deauth(__u8 enable);
+#endif
+
+///@name Ameba1 Only
+///@{
+/**
+ * @brief enable AP sending QoS Null0 Data to poll Sta be alive
+ * @param[in] enabled: enabled can be set to 0,1.
+ * - 0 means enable.
+ * - 1 means disable.
+ * @return None
+ */
+void wifi_set_ap_polling_sta(__u8 enabled);
+///@}
#ifdef __cplusplus
}
#endif
+/*\@}*/
+
#endif // __WIFI_API_H
//----------------------------------------------------------------------------//
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,274 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-
-#include "wifi/wifi_ind.h"
-#include "wifi/wifi_conf.h"
-#include "osdep_service.h"
-#include "platform_stdlib.h"
-
-/******************************************************
- * Constants
- ******************************************************/
-
-#define WIFI_INDICATE_MSG 0
-#define WIFI_MANAGER_STACKSIZE 1300
-#define WIFI_MANAGER_PRIORITY (0) //Actual priority is 4 since calling rtw_create_task
-#define WIFI_MANAGER_Q_SZ 8
-
-#define WIFI_EVENT_MAX_ROW 3
-/******************************************************
- * Globals
- ******************************************************/
-
-static event_list_elem_t event_callback_list[WIFI_EVENT_MAX][WIFI_EVENT_MAX_ROW];
-#if CONFIG_WIFI_IND_USE_THREAD
-static rtw_worker_thread_t wifi_worker_thread;
-#endif
-
-//----------------------------------------------------------------------------//
-#if CONFIG_WIFI_IND_USE_THREAD
-static rtw_result_t rtw_send_event_to_worker(int event_cmd, char *buf, int buf_len, int flags)
-{
- rtw_event_message_t message;
- int i;
- rtw_result_t ret = RTW_SUCCESS;
- char *local_buf = NULL;
-
- if(event_cmd >= WIFI_EVENT_MAX)
- return RTW_BADARG;
-
- for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
- if(event_callback_list[event_cmd][i].handler == NULL)
- continue;
-
- message.function = (event_handler_t)event_callback_list[event_cmd][i].handler;
- message.buf_len = buf_len;
- if(buf_len){
- local_buf = (char*)pvPortMalloc(buf_len);
- if(local_buf == NULL)
- return RTW_NOMEM;
- memcpy(local_buf, buf, buf_len);
- //printf("\n!!!!!Allocate %p(%d) for evcmd %d\n", local_buf, buf_len, event_cmd);
- }
- message.buf = local_buf;
- message.flags = flags;
- message.user_data = event_callback_list[event_cmd][i].handler_user_data;
-
- ret = rtw_push_to_xqueue(&wifi_worker_thread.event_queue, &message, 0);
- if(ret != RTW_SUCCESS){
- if(local_buf){
- printf("\r\nrtw_send_event_to_worker: enqueue cmd %d failed and free %p(%d)\n", event_cmd, local_buf, buf_len);
- vPortFree(local_buf);
- }
- break;
- }
- }
- return ret;
-}
-#else
-static rtw_result_t rtw_indicate_event_handle(int event_cmd, char *buf, int buf_len, int flags)
-{
- rtw_event_handler_t handle = NULL;
- int i;
-
- if(event_cmd >= WIFI_EVENT_MAX)
- return RTW_BADARG;
-
- for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
- handle = event_callback_list[event_cmd][i].handler;
- if(handle == NULL)
- continue;
- handle(buf, buf_len, flags, event_callback_list[event_cmd][i].handler_user_data);
- }
-
- return RTW_SUCCESS;
-}
-#endif
-
-void wifi_indication( rtw_event_indicate_t event, char *buf, int buf_len, int flags)
-{
- //
- // If upper layer application triggers additional operations on receiving of wext_wlan_indicate,
- // please strictly check current stack size usage (by using uxTaskGetStackHighWaterMark() )
- // , and tries not to share the same stack with wlan driver if remaining stack space is
- // not available for the following operations.
- // ex: using semaphore to notice another thread.
- switch(event)
- {
- case WIFI_EVENT_DISCONNECT:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r %s():Disconnection indication received", __FUNCTION__);
-#endif
- break;
- case WIFI_EVENT_CONNECT:
- // For WPA/WPA2 mode, indication of connection does not mean data can be
- // correctly transmitted or received. Data can be correctly transmitted or
- // received only when 4-way handshake is done.
- // Please check WIFI_EVENT_FOURWAY_HANDSHAKE_DONE event
-#if(WIFI_INDICATE_MSG==1)
- // Sample: return mac address
- if(buf != NULL && buf_len == 6)
- {
- printf("\n\r%s():Connect indication received: %02x:%02x:%02x:%02x:%02x:%02x", __FUNCTION__,
- buf[0],buf[1],buf[2],buf[3],buf[4],buf[5]);
- }
-#endif
- break;
- case WIFI_EVENT_FOURWAY_HANDSHAKE_DONE:
-#if(WIFI_INDICATE_MSG==1)
- if(buf != NULL)
- {
- if(buf_len == strlen(IW_EXT_STR_FOURWAY_DONE))
- printf("\n\r%s():%s", __FUNCTION__, buf);
- }
-#endif
- break;
- case WIFI_EVENT_SCAN_RESULT_REPORT:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_SCAN_RESULT_REPORT\n", __func__);
-#endif
- break;
- case WIFI_EVENT_SCAN_DONE:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_SCAN_DONE\n", __func__);
-#endif
- break;
- case WIFI_EVENT_RECONNECTION_FAIL:
-#if(WIFI_INDICATE_MSG==1)
- if(buf != NULL){
- if(buf_len == strlen(IW_EXT_STR_RECONNECTION_FAIL))
- printf("\n\r%s", buf);
- }
-#endif
- break;
- case WIFI_EVENT_NO_NETWORK:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_NO_NETWORK\n", __func__);
-#endif
- break;
- case WIFI_EVENT_RX_MGNT:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_RX_MGNT\n", __func__);
-#endif
- break;
-#if CONFIG_ENABLE_P2P
- case WIFI_EVENT_SEND_ACTION_DONE:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_SEND_ACTION_DONE\n", __func__);
-#endif
- break;
-#endif //CONFIG_ENABLE_P2P
- case WIFI_EVENT_STA_ASSOC:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_STA_ASSOC\n", __func__);
-#endif
- break;
- case WIFI_EVENT_STA_DISASSOC:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_STA_DISASSOC\n", __func__);
-#endif
- break;
-#ifdef CONFIG_WPS
- case WIFI_EVENT_STA_WPS_START:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_STA_WPS_START\n", __func__);
-#endif
- break;
- case WIFI_EVENT_WPS_FINISH:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_WPS_FINISH\n", __func__);
-#endif
- break;
- case WIFI_EVENT_EAPOL_RECVD:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_EAPOL_RECVD\n", __func__);
-#endif
- break;
-#endif
- case WIFI_EVENT_BEACON_AFTER_DHCP:
-#if(WIFI_INDICATE_MSG==1)
- printf("\n\r%s(): WIFI_EVENT_BEACON_AFTER_DHCP\n", __func__);
-#endif
- break;
- }
-
-#if CONFIG_INIC_EN
- inic_indicate_event(event, buf, buf_len, flags);
-#endif//CONFIG_INIC_EN
-
-#if CONFIG_WIFI_IND_USE_THREAD
- rtw_send_event_to_worker(event, buf, buf_len, flags);
-#else
- rtw_indicate_event_handle(event, buf, buf_len, flags);
-#endif
-}
-
-void wifi_reg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func, void *handler_user_data)
-{
- int i = 0, j = 0;
- if(event_cmds < WIFI_EVENT_MAX){
- for(i=0; i < WIFI_EVENT_MAX_ROW; i++){
- if(event_callback_list[event_cmds][i].handler == NULL){
- for(j=0; j<WIFI_EVENT_MAX_ROW; j++){
- if(event_callback_list[event_cmds][j].handler == handler_func){
- return;
- }
- }
- event_callback_list[event_cmds][i].handler = handler_func;
- event_callback_list[event_cmds][i].handler_user_data = handler_user_data;
- return;
- }
- }
- }
-}
-
-void wifi_unreg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func)
-{
- int i;
- if(event_cmds < WIFI_EVENT_MAX){
- for(i = 0; i < WIFI_EVENT_MAX_ROW; i++){
- if(event_callback_list[event_cmds][i].handler == handler_func){
- event_callback_list[event_cmds][i].handler = NULL;
- event_callback_list[event_cmds][i].handler_user_data = NULL;
- return;
- }
- }
- }
-}
-
-void init_event_callback_list(){
- memset(event_callback_list, 0, sizeof(event_callback_list));
-}
-
-int wifi_manager_init()
-{
-#if CONFIG_WIFI_IND_USE_THREAD
- rtw_create_worker_thread(&wifi_worker_thread,
- WIFI_MANAGER_PRIORITY,
- WIFI_MANAGER_STACKSIZE,
- WIFI_MANAGER_Q_SZ);
-#endif
- return 0;
-}
-
-void rtw_wifi_manager_deinit()
-{
-#if CONFIG_WIFI_IND_USE_THREAD
- rtw_delete_worker_thread(&wifi_worker_thread);
-#endif
-}
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_ind.h Thu Nov 08 11:46:34 2018 +0000
@@ -13,16 +13,23 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*
- ******************************************************************************
- * @file wifi_ind.h
- * @author
- * @version
- * @brief This file provides the functions related to event handler mechanism.
- ******************************************************************************
- */
+ ******************************************************************************
+ * @file wifi_ind.h
+ * @author
+ * @version
+ * @brief This file provides the functions related to event handler mechanism.
+ ******************************************************************************
+ */
#ifndef _WIFI_INDICATE_H
#define _WIFI_INDICATE_H
+
+/** @addtogroup nic NIC
+ * @ingroup wlan
+ * @brief NIC functions
+ * @{
+ */
+
#include "wifi_conf.h"
typedef void (*rtw_event_handler_t)(char *buf, int buf_len, int flags, void* handler_user_data );
@@ -83,5 +90,7 @@
*/
extern void wifi_unreg_event_handler(unsigned int event_cmds, rtw_event_handler_t handler_func);
+/*\@}*/
+
#endif //_WIFI_INDICATE_H
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_promisc.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,482 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-#include "tcpip.h"
-#include "wifi/wifi_conf.h"
-
-#ifndef CONFIG_WLAN
-#define CONFIG_WLAN 1
-#endif
-
-#if CONFIG_WLAN
-#include <platform/platform_stdlib.h>
-
-// Add extra interfaces to make release sdk able to determine promisc API linking
-void promisc_deinit(void *padapter)
-{
-#ifdef CONFIG_PROMISC
- _promisc_deinit(padapter);
-#endif
-}
-
-int promisc_recv_func(void *padapter, void *rframe)
-{
- // Never reach here if not define CONFIG_PROMISC
-#ifdef CONFIG_PROMISC
- return _promisc_recv_func(padapter, rframe);
-#else
- return 0;
-#endif
-}
-
-int promisc_set(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used)
-{
-#ifdef CONFIG_PROMISC
- return _promisc_set(enabled, callback, len_used);
-#else
- return -1;
-#endif
-}
-
-unsigned char is_promisc_enabled(void)
-{
-#ifdef CONFIG_PROMISC
- return _is_promisc_enabled();
-#else
- return 0;
-#endif
-}
-
-int promisc_get_fixed_channel(void *fixed_bssid, u8 *ssid, int *ssid_length)
-{
-#ifdef CONFIG_PROMISC
- return _promisc_get_fixed_channel(fixed_bssid, ssid, ssid_length);
-#else
- return 0;
-#endif
-}
-// End of Add extra interfaces
-
-struct eth_frame {
- struct eth_frame *prev;
- struct eth_frame *next;
- unsigned char da[6];
- unsigned char sa[6];
- unsigned int len;
- unsigned char type;
- signed char rssi;
-};
-
-#if CONFIG_INIC_CMD_RSP
-#if defined(__IAR_SYSTEMS_ICC__)
-#pragma pack(1)
-#endif
-struct inic_eth_frame {
- unsigned char da[6];
- unsigned char sa[6];
- unsigned int len;
- unsigned char type;
-};
-#if defined(__IAR_SYSTEMS_ICC__)
-#pragma pack()
-#endif
-
-static struct inic_eth_frame *inic_frame, *inic_frame_tail = NULL;
-static int inic_frame_cnt = 0;
-#define MAX_INIC_FRAME_NUM 50 //maximum packets for each channel
-extern void inic_c2h_msg(const char *atcmd, char status, char *msg, u16 msg_len);
-#endif
-
-struct eth_buffer {
- struct eth_frame *head;
- struct eth_frame *tail;
-};
-
-static struct eth_buffer eth_buffer;
-
-#ifdef CONFIG_PROMISC
-#define MAX_PACKET_FILTER_INFO 5
-#define FILTER_ID_INIT_VALUE 10
-rtw_packet_filter_info_t paff_array[MAX_PACKET_FILTER_INFO]={{0}, {0}, {0}, {0}, {0}};
-static u8 packet_filter_enable_num = 0;
-
-void promisc_init_packet_filter()
-{
- int i = 0;
- for(i=0; i<MAX_PACKET_FILTER_INFO; i++){
- paff_array[i].filter_id = FILTER_ID_INIT_VALUE;
- paff_array[i].enable = 0;
- paff_array[i].patt.mask_size = 0;
- paff_array[i].rule = RTW_POSITIVE_MATCHING;
- paff_array[i].patt.mask = NULL;
- paff_array[i].patt.pattern = NULL;
- }
- packet_filter_enable_num = 0;
-}
-
-int promisc_add_packet_filter(u8 filter_id, rtw_packet_filter_pattern_t *patt, rtw_packet_filter_rule_t rule)
-{
- int i = 0;
- while(i < MAX_PACKET_FILTER_INFO){
- if(paff_array[i].filter_id == FILTER_ID_INIT_VALUE){
- break;
- }
- i++;
- }
-
- if(i == MAX_PACKET_FILTER_INFO)
- return -1;
-
- paff_array[i].filter_id = filter_id;
-
- paff_array[i].patt.offset= patt->offset;
- paff_array[i].patt.mask_size = patt->mask_size;
- paff_array[i].patt.mask = rtw_malloc(patt->mask_size);
- memcpy(paff_array[i].patt.mask, patt->mask, patt->mask_size);
- paff_array[i].patt.pattern= rtw_malloc(patt->mask_size);
- memcpy(paff_array[i].patt.pattern, patt->pattern, patt->mask_size);
-
- paff_array[i].rule = rule;
- paff_array[i].enable = 0;
-
- return 0;
-}
-
-int promisc_enable_packet_filter(u8 filter_id)
-{
- int i = 0;
- while(i < MAX_PACKET_FILTER_INFO){
- if(paff_array[i].filter_id == filter_id)
- break;
- i++;
- }
-
- if(i == MAX_PACKET_FILTER_INFO)
- return -1;
-
- paff_array[i].enable = 1;
- packet_filter_enable_num++;
- return 0;
-}
-
-int promisc_disable_packet_filter(u8 filter_id)
-{
- int i = 0;
- while(i < MAX_PACKET_FILTER_INFO){
- if(paff_array[i].filter_id == filter_id)
- break;
- i++;
- }
-
- if(i == MAX_PACKET_FILTER_INFO)
- return -1;
-
- paff_array[i].enable = 0;
- packet_filter_enable_num--;
- return 0;
-}
-
-int promisc_remove_packet_filter(u8 filter_id)
-{
- int i = 0;
- while(i < MAX_PACKET_FILTER_INFO){
- if(paff_array[i].filter_id == filter_id)
- break;
- i++;
- }
-
- if(i == MAX_PACKET_FILTER_INFO)
- return -1;
-
- paff_array[i].filter_id = FILTER_ID_INIT_VALUE;
- paff_array[i].enable = 0;
- paff_array[i].rule = 0;
- if(paff_array[i].patt.mask){
- rtw_mfree((void *) paff_array[i].patt.mask, paff_array[i].patt.mask_size);
- paff_array[i].patt.mask = NULL;
- }
-
- if(paff_array[i].patt.pattern){
- rtw_mfree((void *) paff_array[i].patt.pattern, paff_array[i].patt.mask_size);
- paff_array[i].patt.pattern = NULL;
- }
- paff_array[i].patt.mask_size = 0;
- return 0;
-}
-#endif
-
-/* Make callback simple to prevent latency to wlan rx when promiscuous mode */
-static void promisc_callback(unsigned char *buf, unsigned int len, void* userdata)
-{
- struct eth_frame *frame = (struct eth_frame *) rtw_malloc(sizeof(struct eth_frame));
-
- if(frame) {
- frame->prev = NULL;
- frame->next = NULL;
- memcpy(frame->da, buf, 6);
- memcpy(frame->sa, buf+6, 6);
- frame->len = len;
- frame->rssi = ((ieee80211_frame_info_t *)userdata)->rssi;
- _lock lock;
- _irqL irqL;
- rtw_enter_critical(&lock, &irqL);
-
- if(eth_buffer.tail) {
- eth_buffer.tail->next = frame;
- frame->prev = eth_buffer.tail;
- eth_buffer.tail = frame;
- }
- else {
- eth_buffer.head = frame;
- eth_buffer.tail = frame;
- }
-
- rtw_exit_critical(&lock, &irqL);
- }
-}
-
-struct eth_frame* retrieve_frame(void)
-{
- struct eth_frame *frame = NULL;
-
- _lock lock;
- _irqL irqL;
- rtw_enter_critical(&lock, &irqL);
-
- if(eth_buffer.head) {
- frame = eth_buffer.head;
-
- if(eth_buffer.head->next) {
- eth_buffer.head = eth_buffer.head->next;
- eth_buffer.head->prev = NULL;
- }
- else {
- eth_buffer.head = NULL;
- eth_buffer.tail = NULL;
- }
- }
-
- rtw_exit_critical(&lock, &irqL);
-
- return frame;
-}
-
-static void promisc_test(int duration, unsigned char len_used)
-{
- int ch;
- unsigned int start_time;
- struct eth_frame *frame;
- eth_buffer.head = NULL;
- eth_buffer.tail = NULL;
-
- wifi_enter_promisc_mode();
- wifi_set_promisc(RTW_PROMISC_ENABLE, promisc_callback, len_used);
-
- for(ch = 1; ch <= 13; ch ++) {
- if(wifi_set_channel(ch) == 0)
- printf("\n\n\rSwitch to channel(%d)", ch);
-
- start_time = rtw_get_current_time();
-
- while(1) {
- unsigned int current_time = rtw_get_current_time();
-
- if(rtw_systime_to_ms(current_time - start_time) < (unsigned int)duration) {
- frame = retrieve_frame();
-
- if(frame) {
- int i;
- printf("\n\rDA:");
- for(i = 0; i < 6; i ++)
- printf(" %02x", frame->da[i]);
- printf(", SA:");
- for(i = 0; i < 6; i ++)
- printf(" %02x", frame->sa[i]);
- printf(", len=%d", frame->len);
- printf(", RSSI=%d", frame->rssi);
-#if CONFIG_INIC_CMD_RSP
- if(inic_frame_tail){
- if(inic_frame_cnt < MAX_INIC_FRAME_NUM){
- memcpy(inic_frame_tail->da, frame->da, 6);
- memcpy(inic_frame_tail->sa, frame->sa, 6);
- inic_frame_tail->len = frame->len;
- inic_frame_tail++;
- inic_frame_cnt++;
- }
- }
-#endif
- rtw_mfree((void *) frame, sizeof(struct eth_frame));
- }
- else
- rtw_mdelay_os(1); //delay 1 tick
- }
- else
- break;
- }
-#if CONFIG_INIC_CMD_RSP
- if(inic_frame){
- inic_c2h_msg("ATWM", RTW_SUCCESS, (char *)inic_frame, sizeof(struct inic_eth_frame)*inic_frame_cnt);
- memset(inic_frame, '\0', sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
- inic_frame_tail = inic_frame;
- inic_frame_cnt = 0;
- rtw_msleep_os(10);
- }
-#endif
- }
-
- wifi_set_promisc(RTW_PROMISC_DISABLE, NULL, 0);
-
- while((frame = retrieve_frame()) != NULL)
- rtw_mfree((void *) frame, sizeof(struct eth_frame));
-}
-
-static void promisc_callback_all(unsigned char *buf, unsigned int len, void* userdata)
-{
- struct eth_frame *frame = (struct eth_frame *) rtw_malloc(sizeof(struct eth_frame));
-
- if(frame) {
- frame->prev = NULL;
- frame->next = NULL;
- memcpy(frame->da, buf+4, 6);
- memcpy(frame->sa, buf+10, 6);
- frame->len = len;
- /*
- * type is the first byte of Frame Control Field of 802.11 frame
- * If the from/to ds information is needed, type could be reused as follows:
- * frame->type = ((((ieee80211_frame_info_t *)userdata)->i_fc & 0x0100) == 0x0100) ? 2 : 1;
- * 1: from ds; 2: to ds
- */
- frame->type = *buf;
- frame->rssi = ((ieee80211_frame_info_t *)userdata)->rssi;
-
- _lock lock;
- _irqL irqL;
- rtw_enter_critical(&lock, &irqL);
-
-
- if(eth_buffer.tail) {
- eth_buffer.tail->next = frame;
- frame->prev = eth_buffer.tail;
- eth_buffer.tail = frame;
- }
- else {
- eth_buffer.head = frame;
- eth_buffer.tail = frame;
- }
-
- rtw_exit_critical(&lock, &irqL);
- }
-}
-static void promisc_test_all(int duration, unsigned char len_used)
-{
- int ch;
- unsigned int start_time;
- struct eth_frame *frame;
- eth_buffer.head = NULL;
- eth_buffer.tail = NULL;
-
- wifi_enter_promisc_mode();
- wifi_set_promisc(RTW_PROMISC_ENABLE_2, promisc_callback_all, len_used);
-
- for(ch = 1; ch <= 13; ch ++) {
- if(wifi_set_channel(ch) == 0)
- printf("\n\n\rSwitch to channel(%d)", ch);
-
- start_time = rtw_get_current_time();
-
- while(1) {
- unsigned int current_time = rtw_get_current_time();
-
- if(rtw_systime_to_ms(current_time - start_time) < (unsigned int)duration) {
- frame = retrieve_frame();
-
- if(frame) {
- int i;
- printf("\n\rTYPE: 0x%x, ", frame->type);
- printf("DA:");
- for(i = 0; i < 6; i ++)
- printf(" %02x", frame->da[i]);
- printf(", SA:");
- for(i = 0; i < 6; i ++)
- printf(" %02x", frame->sa[i]);
- printf(", len=%d", frame->len);
- printf(", RSSI=%d", frame->rssi);
-#if CONFIG_INIC_CMD_RSP
- if(inic_frame_tail){
- if(inic_frame_cnt < MAX_INIC_FRAME_NUM){
- memcpy(inic_frame_tail->da, frame->da, 6);
- memcpy(inic_frame_tail->sa, frame->sa, 6);
- inic_frame_tail->len = frame->len;
- inic_frame_tail->type = frame->type;
- inic_frame_tail++;
- inic_frame_cnt++;
- }
- }
-#endif
- rtw_mfree((void *) frame, sizeof(struct eth_frame));
- }
- else
- rtw_mdelay_os(1); //delay 1 tick
- }
- else
- break;
- }
-#if CONFIG_INIC_CMD_RSP
- if(inic_frame){
- inic_c2h_msg("ATWM", RTW_SUCCESS, (char *)inic_frame, sizeof(struct inic_eth_frame)*inic_frame_cnt);
- memset(inic_frame, '\0', sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
- inic_frame_tail = inic_frame;
- inic_frame_cnt = 0;
- rtw_msleep_os(10);
- }
-#endif
- }
-
- wifi_set_promisc(RTW_PROMISC_DISABLE, NULL, 0);
-
- while((frame = retrieve_frame()) != NULL)
- rtw_mfree((void *) frame, sizeof(struct eth_frame));
-}
-
-void cmd_promisc(int argc, char **argv)
-{
- int duration;
-#if CONFIG_INIC_CMD_RSP
- inic_frame_tail = inic_frame = rtw_malloc(sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
- if(inic_frame == NULL){
- inic_c2h_msg("ATWM", RTW_BUFFER_UNAVAILABLE_TEMPORARY, NULL, 0);
- return;
- }
-#endif
- #ifdef CONFIG_PROMISC
- wifi_init_packet_filter();
- #endif
- if((argc == 2) && ((duration = atoi(argv[1])) > 0))
- //promisc_test(duration, 0);
- promisc_test_all(duration, 0);
- else if((argc == 3) && ((duration = atoi(argv[1])) > 0) && (strcmp(argv[2], "with_len") == 0))
- promisc_test(duration, 1);
- else
- printf("\n\rUsage: %s DURATION_SECONDS [with_len]", argv[0]);
-#if CONFIG_INIC_CMD_RSP
- if(inic_frame)
- rtw_mfree(inic_frame, sizeof(struct inic_eth_frame)*MAX_INIC_FRAME_NUM);
- inic_frame_tail = NULL;
- inic_frame_cnt = 0;
-#endif
-}
-#endif //#if CONFIG_WLAN
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1344 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-#include <wifi_util.h>
-#include <platform/platform_stdlib.h>
-#include <wifi/wifi_conf.h>
-#include <wifi/wifi_ind.h>
-#include <osdep_service.h>
-
-extern u32 GlobalDebugEnable;
-#define WIFI_UTIL_MSG(...) do {\
- if (GlobalDebugEnable) \
- printf("\r" __VA_ARGS__);\
-}while(0)
-
-int iw_ioctl(const char *ifname, unsigned long request, struct iwreq *pwrq)
-{
- memcpy(pwrq->ifr_name, ifname, 5);
- return rltk_wlan_control(request, (void *) pwrq);
-}
-
-int wext_get_ssid(const char *ifname, __u8 *ssid)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.essid.pointer = ssid;
- iwr.u.essid.length = 32;
-
- if (iw_ioctl(ifname, SIOCGIWESSID, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWESSID] ssid = NULL, not connected"); //do not use perror
- ret = -1;
- } else {
- ret = iwr.u.essid.length;
- if (ret > 32)
- ret = 32;
- /* Some drivers include nul termination in the SSID, so let's
- * remove it here before further processing. WE-21 changes this
- * to explicitly require the length _not_ to include nul
- * termination. */
- if (ret > 0 && ssid[ret - 1] == '\0')
- ret--;
- ssid[ret] = '\0';
- }
-
- return ret;
-}
-
-int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.essid.pointer = (void *) ssid;
- iwr.u.essid.length = ssid_len;
- iwr.u.essid.flags = (ssid_len != 0);
-
- if (iw_ioctl(ifname, SIOCSIWESSID, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWESSID] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int wext_set_bssid(const char *ifname, const __u8 *bssid)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.ap_addr.sa_family = ARPHRD_ETHER;
- memcpy(iwr.u.ap_addr.sa_data, bssid, ETH_ALEN);
-
- if(bssid[ETH_ALEN]=='#' && bssid[ETH_ALEN + 1]=='@'){
- memcpy(iwr.u.ap_addr.sa_data + ETH_ALEN, bssid + ETH_ALEN, 6);
- }
-
- if (iw_ioctl(ifname, SIOCSIWAP, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWAP] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int is_broadcast_ether_addr(const unsigned char *addr)
-{
- return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
-}
-
-int wext_set_auth_param(const char *ifname, __u16 idx, __u32 value)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.param.flags = idx & IW_AUTH_INDEX;
- iwr.u.param.value = value;
-
- if (iw_ioctl(ifname, SIOCSIWAUTH, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rWEXT: SIOCSIWAUTH(param %d value 0x%x) failed)", idx, value);
- }
-
- return ret;
-}
-
-int wext_set_key_ext(const char *ifname, __u16 alg, const __u8 *addr, int key_idx, int set_tx, const __u8 *seq, __u16 seq_len, __u8 *key, __u16 key_len)
-{
- struct iwreq iwr;
- int ret = 0;
- struct iw_encode_ext *ext;
-
- ext = (struct iw_encode_ext *) rtw_malloc(sizeof(struct iw_encode_ext) + key_len);
- if (ext == NULL)
- return -1;
- else
- memset(ext, 0, sizeof(struct iw_encode_ext) + key_len);
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.encoding.flags = key_idx + 1;
- iwr.u.encoding.flags |= IW_ENCODE_TEMP;
- iwr.u.encoding.pointer = ext;
- iwr.u.encoding.length = sizeof(struct iw_encode_ext) + key_len;
-
- if (alg == IW_ENCODE_DISABLED)
- iwr.u.encoding.flags |= IW_ENCODE_DISABLED;
-
- if (addr == NULL || is_broadcast_ether_addr(addr))
- ext->ext_flags |= IW_ENCODE_EXT_GROUP_KEY;
-
- if (set_tx)
- ext->ext_flags |= IW_ENCODE_EXT_SET_TX_KEY;
-
- ext->addr.sa_family = ARPHRD_ETHER;
-
- if (addr)
- memcpy(ext->addr.sa_data, addr, ETH_ALEN);
- else
- memset(ext->addr.sa_data, 0xff, ETH_ALEN);
-
- if (key && key_len) {
- memcpy(ext->key, key, key_len);
- ext->key_len = key_len;
- }
-
- ext->alg = alg;
-
- if (seq && seq_len) {
- ext->ext_flags |= IW_ENCODE_EXT_RX_SEQ_VALID;
- memcpy(ext->rx_seq, seq, seq_len);
- }
-
- if (iw_ioctl(ifname, SIOCSIWENCODEEXT, &iwr) < 0) {
- ret = -2;
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWENCODEEXT] set key fail");
- }
-
- rtw_free(ext);
- return ret;
-}
-
-int wext_get_enc_ext(const char *ifname, __u16 *alg, __u8 *key_idx, __u8 *passphrase)
-{
- struct iwreq iwr;
- int ret = 0;
- struct iw_encode_ext *ext;
-
- ext = (struct iw_encode_ext *) rtw_malloc(sizeof(struct iw_encode_ext) + 16);
- if (ext == NULL)
- return -1;
- else
- memset(ext, 0, sizeof(struct iw_encode_ext) + 16);
-
- iwr.u.encoding.pointer = ext;
-
- if (iw_ioctl(ifname, SIOCGIWENCODEEXT, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWENCODEEXT] error");
- ret = -1;
- }
- else
- {
- *alg = ext->alg;
- if(key_idx)
- *key_idx = (__u8)iwr.u.encoding.flags;
- if(passphrase)
- memcpy(passphrase, ext->key, ext->key_len);
- }
-
- if (ext != NULL)
- rtw_free(ext);
-
- return ret;
-}
-
-int wext_set_passphrase(const char *ifname, const __u8 *passphrase, __u16 passphrase_len)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.passphrase.pointer = (void *) passphrase;
- iwr.u.passphrase.length = passphrase_len;
- iwr.u.passphrase.flags = (passphrase_len != 0);
-
- if (iw_ioctl(ifname, SIOCSIWPRIVPASSPHRASE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWESSID+0x1f] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int wext_get_passphrase(const char *ifname, __u8 *passphrase)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.passphrase.pointer = (void *) passphrase;
-
- if (iw_ioctl(ifname, SIOCGIWPRIVPASSPHRASE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWPRIVPASSPHRASE] error");
- ret = -1;
- }
- else {
- ret = iwr.u.passphrase.length;
- passphrase[ret] = '\0';
- }
-
- return ret;
-}
-
-#if 0
-int wext_set_mac_address(const char *ifname, char * mac)
-{
- char buf[13+17+1];
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 13+17, "write_mac %s", mac);
- return wext_private_command(ifname, buf, 0);
-}
-
-int wext_get_mac_address(const char *ifname, char * mac)
-{
- int ret = 0;
- char buf[32];
-
- rtw_memset(buf, 0, sizeof(buf));
- rtw_memcpy(buf, "read_mac", 8);
- ret = wext_private_command_with_retval(ifname, buf, buf, 32);
- strcpy(mac, buf);
- return ret;
-}
-#endif
-
-int wext_enable_powersave(const char *ifname, __u8 ips_mode, __u8 lps_mode)
-{
- struct iwreq iwr;
- int ret = 0;
- __u16 pindex = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("pm_set");
-
- // Encode parameters as TLV (type, length, value) format
- para = rtw_malloc( 7 + (1+1+1) + (1+1+1) );
- if(para == NULL) return -1;
-
- snprintf((char*)para, cmd_len, "pm_set");
- pindex = 7;
-
- para[pindex++] = 0; // type 0 for ips
- para[pindex++] = 1;
- para[pindex++] = ips_mode;
-
- para[pindex++] = 1; // type 1 for lps
- para[pindex++] = 1;
- para[pindex++] = lps_mode;
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = pindex;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-}
-
-int wext_disable_powersave(const char *ifname)
-{
- struct iwreq iwr;
- int ret = 0;
- __u16 pindex = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("pm_set");
-
- // Encode parameters as TLV (type, length, value) format
- para = rtw_malloc( 7 + (1+1+1) + (1+1+1) );
- if(para == NULL) return -1;
-
- snprintf((char*)para, cmd_len, "pm_set");
- pindex = 7;
-
- para[pindex++] = 0; // type 0 for ips
- para[pindex++] = 1;
- para[pindex++] = 0; // ips = 0
-
- para[pindex++] = 1; // type 1 for lps
- para[pindex++] = 1;
- para[pindex++] = 0; // lps = 0
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = pindex;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-
-}
-
-int wext_set_tdma_param(const char *ifname, __u8 slot_period, __u8 rfon_period_len_1, __u8 rfon_period_len_2, __u8 rfon_period_len_3)
-{
- struct iwreq iwr;
- int ret = 0;
- __u16 pindex = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("pm_set");
-
- // Encode parameters as TLV (type, length, value) format
- para = rtw_malloc( 7 + (1+1+4) );
-
- snprintf((char*)para, cmd_len, "pm_set");
- pindex = 7;
-
- para[pindex++] = 2; // type 2 tdma param
- para[pindex++] = 4;
- para[pindex++] = slot_period;
- para[pindex++] = rfon_period_len_1;
- para[pindex++] = rfon_period_len_2;
- para[pindex++] = rfon_period_len_3;
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = pindex;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-}
-
-int wext_set_lps_dtim(const char *ifname, __u8 lps_dtim)
-{
- struct iwreq iwr;
- int ret = 0;
- __u16 pindex = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("pm_set");
-
- // Encode parameters as TLV (type, length, value) format
- para = rtw_malloc( 7 + (1+1+1) );
-
- snprintf((char*)para, cmd_len, "pm_set");
- pindex = 7;
-
- para[pindex++] = 3; // type 3 lps dtim
- para[pindex++] = 1;
- para[pindex++] = lps_dtim;
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = pindex;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-}
-
-int wext_get_lps_dtim(const char *ifname, __u8 *lps_dtim)
-{
-
- struct iwreq iwr;
- int ret = 0;
- __u16 pindex = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("pm_get");
-
- // Encode parameters as TLV (type, length, value) format
- para = rtw_malloc( 7 + (1+1+1) );
-
- snprintf((char*)para, cmd_len, "pm_get");
- pindex = 7;
-
- para[pindex++] = 3; // type 3 for lps dtim
- para[pindex++] = 1;
- para[pindex++] = 0;
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = pindex;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- goto exit;
- }
-
- //get result at the beginning of iwr.u.data.pointer
- if((para[0]==3)&&(para[1]==1))
- *lps_dtim = para[2];
- else
- WIFI_UTIL_MSG("\n\r%s error", __func__);
-
-exit:
- rtw_free(para);
-
- return ret;
-}
-
-int wext_set_tos_value(const char *ifname, __u8 *tos_value)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = sizeof("set_tos_value");
-
- memset(&iwr, 0, sizeof(iwr));
-
- para = rtw_malloc(cmd_len + 4);
- snprintf((char*)para, cmd_len, "set_tos_value");
-
- if (*tos_value >= 0 && *tos_value <=32){
- *(para + cmd_len) = 0x4f;
- *(para + cmd_len+1) = 0xa4;
- *(para + cmd_len+2) = 0;
- *(para + cmd_len+3) = 0;
- }
- else if(*tos_value > 32 && *tos_value <=96){
- *(para + cmd_len) = 0x2b;
- *(para + cmd_len+1) = 0xa4;
- *(para + cmd_len+2) = 0;
- *(para + cmd_len+3) = 0;
- }
- else if(*tos_value > 96 && *tos_value <= 160){
- *(para + cmd_len) = 0x22;
- *(para + cmd_len+1) = 0x43;
- *(para + cmd_len+2) = 0x5e;
- *(para + cmd_len+3) = 0;
- }
- else if(*tos_value > 160){
- *(para + cmd_len) = 0x22;
- *(para + cmd_len+1) = 0x32;
- *(para + cmd_len+2) = 0x2f;
- *(para + cmd_len+3) = 0;
- }
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = cmd_len + 4;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_set_tos_value():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-}
-
-int wext_get_tx_power(const char *ifname, __u8 *poweridx)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = sizeof("get_tx_power");
-
- memset(&iwr, 0, sizeof(iwr));
- //Tx power size : 20 Bytes
- //CCK 1M,2M,5.5M,11M : 4 Bytes
- //OFDM 6M, 9M, 12M, 18M, 24M, 36M 48M, 54M : 8 Bytes
- //MCS 0~7 : 8 Bytes
- para = rtw_malloc(cmd_len + 20);
- snprintf((char*)para, cmd_len, "get_tx_power");
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = cmd_len + 20;
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_get_tx_power():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
-
- memcpy(poweridx,(__u8 *)(iwr.u.data.pointer),20);
- rtw_free(para);
- return ret;
-}
-
-#if 0
-int wext_set_txpower(const char *ifname, int poweridx)
-{
- int ret = 0;
- char buf[24];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 24, "txpower patha=%d", poweridx);
- ret = wext_private_command(ifname, buf, 0);
-
- return ret;
-}
-
-int wext_get_associated_client_list(const char *ifname, void * client_list_buffer, uint16_t buffer_length)
-{
- int ret = 0;
- char buf[25];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 25, "get_client_list %x", client_list_buffer);
- ret = wext_private_command(ifname, buf, 0);
-
- return ret;
-}
-
-int wext_get_ap_info(const char *ifname, rtw_bss_info_t * ap_info, rtw_security_t* security)
-{
- int ret = 0;
- char buf[24];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 24, "get_ap_info %x", ap_info);
- ret = wext_private_command(ifname, buf, 0);
-
- snprintf(buf, 24, "get_security");
- ret = wext_private_command_with_retval(ifname, buf, buf, 24);
- sscanf(buf, "%d", security);
-
- return ret;
-}
-#endif
-
-int wext_set_mode(const char *ifname, int mode)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.mode = mode;
- if (iw_ioctl(ifname, SIOCSIWMODE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWMODE] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int wext_get_mode(const char *ifname, int *mode)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
-
- if (iw_ioctl(ifname, SIOCGIWMODE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWMODE] error");
- ret = -1;
- }
- else
- *mode = iwr.u.mode;
-
- return ret;
-}
-
-int wext_set_ap_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.essid.pointer = (void *) ssid;
- iwr.u.essid.length = ssid_len;
- iwr.u.essid.flags = (ssid_len != 0);
-
- if (iw_ioctl(ifname, SIOCSIWPRIVAPESSID, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVAPESSID] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int wext_set_country(const char *ifname, rtw_country_code_t country_code)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
-
- iwr.u.param.value = country_code;
-
- if (iw_ioctl(ifname, SIOCSIWPRIVCOUNTRY, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWPRIVCOUNTRY] error");
- ret = -1;
- }
- return ret;
-}
-
-int wext_get_rssi(const char *ifname, int *rssi)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
-
- if (iw_ioctl(ifname, SIOCGIWSENS, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWSENS] error");
- ret = -1;
- } else {
- *rssi = 0 - iwr.u.sens.value;
- }
- return ret;
-}
-
-int wext_set_pscan_channel(const char *ifname, __u8 *ch, __u8 *pscan_config, __u8 length)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int i =0;
-
- memset(&iwr, 0, sizeof(iwr));
- //Format of para:function_name num_channel chan1... pscan_config1 ...
- para = rtw_malloc((length + length + 1) + 12);//size:num_chan + num_time + length + function_name
- if(para == NULL) return -1;
-
- //Cmd
- snprintf((char*)para, 12, "PartialScan");
- //length
- *(para+12) = length;
- for(i = 0; i < length; i++){
- *(para + 13 + i)= *(ch + i);
- *((__u16*) (para + 13 + length + i))= *(pscan_config + i);
- }
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = (length + length + 1) + 12;
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_set_pscan_channel():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- rtw_free(para);
- return ret;
-}
-int wext_set_channel(const char *ifname, __u8 ch)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.freq.m = 0;
- iwr.u.freq.e = 0;
- iwr.u.freq.i = ch;
-
- if (iw_ioctl(ifname, SIOCSIWFREQ, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWFREQ] error");
- ret = -1;
- }
-
- return ret;
-}
-
-int wext_get_channel(const char *ifname, __u8 *ch)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
-
- if (iw_ioctl(ifname, SIOCGIWFREQ, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWFREQ] error");
- ret = -1;
- }
- else
- *ch = iwr.u.freq.i;
-
- return ret;
-}
-
-int wext_register_multicast_address(const char *ifname, rtw_mac_t *mac)
-{
- int ret = 0;
- char buf[32];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 32, "reg_multicast "MAC_FMT, MAC_ARG(mac->octet));
- ret = wext_private_command(ifname, buf, 0);
-
- return ret;
-}
-
-int wext_unregister_multicast_address(const char *ifname, rtw_mac_t *mac)
-{
- int ret = 0;
- char buf[35];
-
- rtw_memset(buf, 0, sizeof(buf));
- snprintf(buf, 35, "reg_multicast -d "MAC_FMT, MAC_ARG(mac->octet));
- ret = wext_private_command(ifname, buf, 0);
-
- return ret;
-}
-
-int wext_set_scan(const char *ifname, char *buf, __u16 buf_len, __u16 flags)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
-#if 0 //for scan_with_ssid
- if(buf)
- memset(buf, 0, buf_len);
-#endif
- iwr.u.data.pointer = buf;
- iwr.u.data.flags = flags;
- iwr.u.data.length = buf_len;
- if (iw_ioctl(ifname, SIOCSIWSCAN, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWSCAN] error");
- ret = -1;
- }
- return ret;
-}
-
-int wext_get_scan(const char *ifname, char *buf, __u16 buf_len)
-{
- struct iwreq iwr;
- int ret = 0;
-
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_len;
- if (iw_ioctl(ifname, SIOCGIWSCAN, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCGIWSCAN] error");
- ret = -1;
- }else
- ret = iwr.u.data.flags;
- return ret;
-}
-
-int wext_private_command_with_retval(const char *ifname, char *cmd, char *ret_buf, int ret_len)
-{
- struct iwreq iwr;
- int ret = 0;
- size_t buf_size;
- char *buf;
-
- buf_size = 128;
- if(strlen(cmd) >= buf_size)
- buf_size = strlen(cmd) + 1; // 1 : '\0'
- buf = (char*)rtw_malloc(buf_size);
- if(!buf){
- WIFI_UTIL_MSG("\n\rWEXT: Can't malloc memory");
- return -1;
- }
- memset(buf, 0, buf_size);
- strcpy(buf, cmd);
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_size;
- iwr.u.data.flags = 0;
-
- if ((ret = iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr)) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCDEVPRIVATE] error. ret=%d\n", ret);
- }
- if(ret_buf){
- if(ret_len > iwr.u.data.length)
- ret_len = iwr.u.data.length;
- rtw_memcpy(ret_buf, (char *) iwr.u.data.pointer, ret_len);
- }
- rtw_free(buf);
- return ret;
-}
-
-int wext_private_command(const char *ifname, char *cmd, int show_msg)
-{
- struct iwreq iwr;
- int ret = 0;
- size_t buf_size;
- char *buf;
-
- u8 cmdname[17] = {0}; // IFNAMSIZ+1
-
- sscanf(cmd, "%16s", cmdname);
- if((strcmp((const char *)cmdname, "config_get") == 0)
- || (strcmp((const char *)cmdname, "config_set") == 0)
- || (strcmp((const char *)cmdname, "efuse_get") == 0)
- || (strcmp((const char *)cmdname, "efuse_set") == 0)
- || (strcmp((const char *)cmdname, "mp_psd") == 0))
- buf_size = 2600;//2600 for config_get rmap,0,512 (or realmap)
- else
- buf_size = 512;
-
- if (strlen(cmd) >= buf_size)
- buf_size = strlen(cmd) + 1; // 1 : '\0'
- buf = (char*)rtw_malloc(buf_size);
- if (!buf) {
- WIFI_UTIL_MSG("\n\rWEXT: Can't malloc memory");
- return -1;
- }
- memset(buf, 0, buf_size);
- strcpy(buf, cmd);
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_size;
- iwr.u.data.flags = 0;
-
- if ((ret = iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr)) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCDEVPRIVATE] error. ret=%d\n", ret);
- }
- if (show_msg && iwr.u.data.length) {
- if(iwr.u.data.length > buf_size)
- WIFI_UTIL_MSG("\n\rWEXT: Malloc memory is not enough");
- WIFI_UTIL_MSG("\n\rPrivate Message: %s", (char *) iwr.u.data.pointer);
- }
- rtw_free(buf);
- return ret;
-}
-
-void wext_wlan_indicate(unsigned int cmd, union iwreq_data *wrqu, char *extra)
-{
- unsigned char null_mac[6] = {0};
-
- switch(cmd)
- {
- case SIOCGIWAP:
- if(wrqu->ap_addr.sa_family == ARPHRD_ETHER)
- {
- if(!memcmp(wrqu->ap_addr.sa_data, null_mac, sizeof(null_mac)))
- wifi_indication(WIFI_EVENT_DISCONNECT, NULL, 0, 0);
- else
- wifi_indication(WIFI_EVENT_CONNECT, wrqu->ap_addr.sa_data, sizeof(null_mac), 0);
- }
- break;
-
- case IWEVCUSTOM:
- if(extra)
- {
- if(!memcmp(IW_EXT_STR_FOURWAY_DONE, extra, strlen(IW_EXT_STR_FOURWAY_DONE)))
- wifi_indication(WIFI_EVENT_FOURWAY_HANDSHAKE_DONE, extra, strlen(IW_EXT_STR_FOURWAY_DONE), 0);
- else if(!memcmp(IW_EXT_STR_RECONNECTION_FAIL, extra, strlen(IW_EXT_STR_RECONNECTION_FAIL)))
- wifi_indication(WIFI_EVENT_RECONNECTION_FAIL, extra, strlen(IW_EXT_STR_RECONNECTION_FAIL), 0);
- else if(!memcmp(IW_EVT_STR_NO_NETWORK, extra, strlen(IW_EVT_STR_NO_NETWORK)))
- wifi_indication(WIFI_EVENT_NO_NETWORK, extra, strlen(IW_EVT_STR_NO_NETWORK), 0);
-#if CONFIG_ENABLE_P2P || defined(CONFIG_AP_MODE)
- else if(!memcmp(IW_EVT_STR_STA_ASSOC, extra, strlen(IW_EVT_STR_STA_ASSOC)))
- wifi_indication(WIFI_EVENT_STA_ASSOC, wrqu->data.pointer, wrqu->data.length, 0);
- else if(!memcmp(IW_EVT_STR_STA_DISASSOC, extra, strlen(IW_EVT_STR_STA_DISASSOC)))
- wifi_indication(WIFI_EVENT_STA_DISASSOC, wrqu->addr.sa_data, sizeof(null_mac), 0);
- else if(!memcmp(IW_EVT_STR_SEND_ACTION_DONE, extra, strlen(IW_EVT_STR_SEND_ACTION_DONE)))
- wifi_indication(WIFI_EVENT_SEND_ACTION_DONE, NULL, 0, wrqu->data.flags);
-#endif
- }
- break;
- case SIOCGIWSCAN:
- if(wrqu->data.pointer == NULL)
- wifi_indication(WIFI_EVENT_SCAN_DONE, NULL, 0, 0);
- else
- wifi_indication(WIFI_EVENT_SCAN_RESULT_REPORT, wrqu->data.pointer, wrqu->data.length, 0);
- break;
- case IWEVMGNTRECV:
- wifi_indication(WIFI_EVENT_RX_MGNT, wrqu->data.pointer, wrqu->data.length, wrqu->data.flags);
- break;
-#ifdef REPORT_STA_EVENT
- case IWEVREGISTERED:
- if(wrqu->addr.sa_family == ARPHRD_ETHER)
- wifi_indication(WIFI_EVENT_STA_ASSOC, wrqu->addr.sa_data, sizeof(null_mac), 0);
- break;
- case IWEVEXPIRED:
- if(wrqu->addr.sa_family == ARPHRD_ETHER)
- wifi_indication(WIFI_EVENT_STA_DISASSOC, wrqu->addr.sa_data, sizeof(null_mac), 0);
- break;
-#endif
- default:
- break;
-
- }
-
-}
-
-
-int wext_send_eapol(const char *ifname, char *buf, __u16 buf_len, __u16 flags)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_len;
- iwr.u.data.flags = flags;
- if (iw_ioctl(ifname, SIOCSIWEAPOLSEND, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWEAPOLSEND] error");
- ret = -1;
- }
- return ret;
-}
-
-int wext_send_mgnt(const char *ifname, char *buf, __u16 buf_len, __u16 flags)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_len;
- iwr.u.data.flags = flags;
- if (iw_ioctl(ifname, SIOCSIWMGNTSEND, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWMGNTSEND] error");
- ret = -1;
- }
- return ret;
-}
-
-int wext_set_gen_ie(const char *ifname, char *buf, __u16 buf_len, __u16 flags)
-{
- struct iwreq iwr;
- int ret = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- iwr.u.data.pointer = buf;
- iwr.u.data.length = buf_len;
- iwr.u.data.flags = flags;
- if (iw_ioctl(ifname, SIOCSIWGENIE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rioctl[SIOCSIWGENIE] error");
- ret = -1;
- }
- return ret;
-}
-
-int wext_set_autoreconnect(const char *ifname, __u8 mode, __u8 retry_times, __u16 timeout)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("SetAutoRecnt");
- para = rtw_malloc((4) + cmd_len);//size:para_len+cmd_len
- if(para == NULL) return -1;
-
- //Cmd
- snprintf((char*)para, cmd_len, "SetAutoRecnt");
- //length
- *(para+cmd_len) = mode; //para1
- *(para+cmd_len+1) = retry_times; //para2
- *(para+cmd_len+2) = timeout; //para3
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = (4) + cmd_len;
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_set_autoreconnect():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- rtw_free(para);
- return ret;
-}
-
-int wext_get_autoreconnect(const char *ifname, __u8 *mode)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("GetAutoRecnt");
- para = rtw_malloc(cmd_len);//size:para_len+cmd_len
- //Cmd
- snprintf((char*)para, cmd_len, "GetAutoRecnt");
- //length
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = cmd_len;
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_get_autoreconnect():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- *mode = *(__u8 *)(iwr.u.data.pointer);
- rtw_free(para);
- return ret;
-}
-
-int wext_get_drv_ability(const char *ifname, __u32 *ability)
-{
- int ret = 0;
- char * buf = (char *)rtw_zmalloc(33);
- if(buf == NULL) return -1;
-
- snprintf(buf, 33, "get_drv_ability %x", (unsigned int)ability);
- ret = wext_private_command(ifname, buf, 0);
-
- rtw_free(buf);
- return ret;
-}
-
-#ifdef CONFIG_CUSTOM_IE
-int wext_add_custom_ie(const char *ifname, void *cus_ie, int ie_num)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
- if(ie_num <= 0 || !cus_ie){
- WIFI_UTIL_MSG("\n\rwext_add_custom_ie():wrong parameter");
- ret = -1;
- return ret;
- }
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("SetCusIE");
- para = rtw_malloc((4)* 2 + cmd_len);//size:addr len+cmd_len
- if(para == NULL) return -1;
-
- //Cmd
- snprintf(para, cmd_len, "SetCusIE");
- //addr length
- *(__u32 *)(para + cmd_len) = (__u32)cus_ie; //ie addr
- //ie_num
- *(__u32 *)(para + cmd_len + 4) = ie_num; //num of ie
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = (4)* 2 + cmd_len;// 2 input
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_add_custom_ie():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- rtw_free(para);
-
- return ret;
-}
-
-int wext_update_custom_ie(const char *ifname, void * cus_ie, int ie_index)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
- if(ie_index <= 0 || !cus_ie){
- WIFI_UTIL_MSG("\n\rwext_update_custom_ie():wrong parameter");
- ret = -1;
- return ret;
- }
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("UpdateIE");
- para = rtw_malloc((4)* 2 + cmd_len);//size:addr len+cmd_len
- if(para == NULL) return -1;
-
- //Cmd
- snprintf(para, cmd_len, "UpdateIE");
- //addr length
- *(__u32 *)(para + cmd_len) = (__u32)cus_ie; //ie addr
- //ie_index
- *(__u32 *)(para + cmd_len + 4) = ie_index; //num of ie
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = (4)* 2 + cmd_len;// 2 input
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_update_custom_ie():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- rtw_free(para);
-
- return ret;
-
-}
-
-int wext_del_custom_ie(const char *ifname)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("DelIE");
- para = rtw_malloc(cmd_len);//size:addr len+cmd_len
- //Cmd
- snprintf(para, cmd_len, "DelIE");
-
- iwr.u.data.pointer = para;
- iwr.u.data.length = cmd_len;
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_del_custom_ie():ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
- rtw_free(para);
-
- return ret;
-
-
-}
-
-#endif
-
-#ifdef CONFIG_AP_MODE
-int wext_enable_forwarding(const char *ifname)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("forwarding_set");
- para = rtw_malloc(cmd_len + 1);
- if(para == NULL) return -1;
-
- // forwarding_set 1
- snprintf((char *) para, cmd_len, "forwarding_set");
- *(para + cmd_len) = '1';
-
- iwr.u.essid.pointer = para;
- iwr.u.essid.length = cmd_len + 1;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_enable_forwarding(): ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-}
-
-int wext_disable_forwarding(const char *ifname)
-{
- struct iwreq iwr;
- int ret = 0;
- __u8 *para = NULL;
- int cmd_len = 0;
-
- memset(&iwr, 0, sizeof(iwr));
- cmd_len = sizeof("forwarding_set");
- para = rtw_malloc(cmd_len + 1);
- if(para == NULL) return -1;
-
- // forwarding_set 0
- snprintf((char *) para, cmd_len, "forwarding_set");
- *(para + cmd_len) = '0';
-
- iwr.u.essid.pointer = para;
- iwr.u.essid.length = cmd_len + 1;
-
- if (iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr) < 0) {
- WIFI_UTIL_MSG("\n\rwext_disable_forwarding(): ioctl[SIOCDEVPRIVATE] error");
- ret = -1;
- }
-
- rtw_free(para);
- return ret;
-
-}
-#endif
-
-#ifdef CONFIG_CONCURRENT_MODE
-int wext_set_ch_deauth(const char *ifname, __u8 enable)
-{
- int ret = 0;
- char * buf = (char *)rtw_zmalloc(16);
- if(buf == NULL) return -1;
-
- snprintf(buf, 16, "SetChDeauth %d", enable);
- ret = wext_private_command(ifname, buf, 0);
-
- rtw_free(buf);
- return ret;
-}
-#endif
-
-int wext_set_adaptivity(rtw_adaptivity_mode_t adaptivity_mode)
-{
- extern u8 rtw_adaptivity_en;
- extern u8 rtw_adaptivity_mode;
-
- switch(adaptivity_mode){
- case RTW_ADAPTIVITY_NORMAL:
- rtw_adaptivity_en = 1; // enable adaptivity
- rtw_adaptivity_mode = RTW_ADAPTIVITY_MODE_NORMAL;
- break;
- case RTW_ADAPTIVITY_CARRIER_SENSE:
- rtw_adaptivity_en = 1; // enable adaptivity
- rtw_adaptivity_mode = RTW_ADAPTIVITY_MODE_CARRIER_SENSE;
- break;
- case RTW_ADAPTIVITY_DISABLE:
- default:
- rtw_adaptivity_en = 0; //disable adaptivity
- break;
- }
- return 0;
-}
-
-int wext_set_adaptivity_th_l2h_ini(__u8 l2h_threshold)
-{
- extern s8 rtw_adaptivity_th_l2h_ini;
- rtw_adaptivity_th_l2h_ini = (__s8)l2h_threshold;
- return 0;
-}
-
-int wext_get_auto_chl(const char *ifname, unsigned char *channel_set, unsigned char channel_num)
-{
- int ret = -1;
- int channel = 0;
- wext_disable_powersave(ifname);
- if((channel = rltk_get_auto_chl(ifname,channel_set,channel_num)) != 0 )
- ret = channel;
- wext_enable_powersave(ifname, 1, 1);
- return ret;
-}
-
-int wext_set_sta_num(unsigned char ap_sta_num)
-{
- return rltk_set_sta_num(ap_sta_num);
-}
-
-int wext_del_station(const char *ifname, unsigned char* hwaddr)
-{
- return rltk_del_station(ifname, hwaddr);
-}
-
-extern struct list_head *mf_list_head;
-int wext_init_mac_filter(void)
-{
- if (mf_list_head != NULL){
- return -1;
- }
-
- mf_list_head = (struct list_head *)rtw_malloc(sizeof(struct list_head));
- if(mf_list_head == NULL){
- WIFI_UTIL_MSG("\n\r[ERROR] %s : can't allocate mf_list_head",__func__);
- return -1;
- }
-
- INIT_LIST_HEAD(mf_list_head);
-
- return 0;
-}
-
-int wext_deinit_mac_filter(void)
-{
- if (mf_list_head == NULL){
- return -1;
- }
- struct list_head *iterator;
- rtw_mac_filter_list_t *item;
- list_for_each(iterator, mf_list_head) {
- item = list_entry(iterator, rtw_mac_filter_list_t, node);
- list_del(iterator);
- rtw_free(item);
- item = NULL;
- iterator = mf_list_head;
- }
-
- rtw_free(mf_list_head);
- mf_list_head = NULL;
- return 0;
-}
-
-int wext_add_mac_filter(unsigned char* hwaddr)
-{
- if(mf_list_head == NULL){
- return -1;
- }
-
- rtw_mac_filter_list_t *mf_list_new;
- mf_list_new = (rtw_mac_filter_list_t *)rtw_malloc(sizeof(rtw_mac_filter_list_t));
- if(mf_list_new == NULL){
- WIFI_UTIL_MSG("\n\r[ERROR] %s : can't allocate mf_list_new",__func__);
- return -1;
- }
- memcpy(mf_list_new->mac_addr,hwaddr,6);
- list_add(&(mf_list_new->node), mf_list_head);
-
- return 0;
-}
-
-int wext_del_mac_filter(unsigned char* hwaddr)
-{
- if (mf_list_head == NULL){
- return -1;
- }
-
- struct list_head *iterator;
- rtw_mac_filter_list_t *item;
- list_for_each(iterator, mf_list_head) {
- item = list_entry(iterator, rtw_mac_filter_list_t, node);
- if (memcmp(item->mac_addr, hwaddr, 6) == 0) {
- list_del(iterator);
- rtw_free(item);
- item = NULL;
- return 0;
- }
- }
- return -1;
-}
-
-extern void rtw_set_indicate_mgnt(int enable);
-void wext_set_indicate_mgnt(int enable)
-{
- rtw_set_indicate_mgnt(enable);
- return;
-}
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/wifi/wifi_util.h Thu Nov 08 11:46:34 2018 +0000 @@ -28,6 +28,8 @@ int wext_get_ssid(const char *ifname, __u8 *ssid); int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len); +int wext_set_bssid(const char *ifname, const __u8 *bssid); +int wext_get_bssid(const char *ifname, __u8 *bssid); int wext_set_auth_param(const char *ifname, __u16 idx, __u32 value); int wext_set_key_ext(const char *ifname, __u16 alg, const __u8 *addr, int key_idx, int set_tx, const __u8 *seq, __u16 seq_len, __u8 *key, __u16 key_len); int wext_get_enc_ext(const char *ifname, __u16 *alg, __u8 *key_idx, __u8 *passphrase);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/autoconf.h Thu Nov 08 11:46:34 2018 +0000
@@ -14,7 +14,6 @@
* limitations under the License.
******************************************************************************/
-
#ifndef WLANCONFIG_H
#define WLANCONFIG_H
@@ -22,19 +21,42 @@
* Include user defined options first. Anything not defined in these files
* will be set to standard values. Override anything you dont like!
*/
-#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_HARDWARE_8188F)
#include "platform_opts.h"
+
+#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_PLATFORM_8721D) || defined(CONFIG_PLATFORM_8195BHP)
+#ifndef CONFIG_PLATFORM_AMEBA_X
+#define CONFIG_PLATFORM_AMEBA_X 1
+#endif
+#else
+#define CONFIG_PLATFORM_AMEBA_X 0
#endif
-#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
-#define CONFIG_PLATFORM_AMEBA_X
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
+ #if defined(CONFIG_PLATFORM_8195BHP)
+ #define CONFIG_AXI_HCI
+ #else
+ #define CONFIG_LX_HCI
+ #endif
+#else
+ #define PLATFORM_FREERTOS 1
+ #ifdef USE_SDIO_INTERFACE
+ #define CONFIG_SDIO_HCI
+ #else
+ #define CONFIG_GSPI_HCI
+#endif
+#endif // #if (CONFIG_PLATFORM_AMEBA_X == 1)
+
+#if defined(CONFIG_HARDWARE_8188F) || defined(CONFIG_HARDWARE_8192E)|| defined(CONFIG_HARDWARE_8723D) || defined(CONFIG_HARDWARE_8821C) || defined(CONFIG_PLATFORM_8195BHP) || defined(CONFIG_HARDWARE_8188E) || defined(CONFIG_PLATFORM_8721D)
+#define CONFIG_FW_C2H_PKT
+#define PHYDM_LINUX_CODING_STYLE 1
+#else
+#define PHYDM_LINUX_CODING_STYLE 0
#endif
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
-#define PLATFORM_FREERTOS 1
-#define CONFIG_GSPI_HCI
+#if (PHYDM_LINUX_CODING_STYLE == 1)
+#define PHYDM_NEW_INTERFACE 1
#else
-#define CONFIG_LX_HCI
+#define PHYDM_NEW_INTERFACE 0
#endif
#ifndef CONFIG_INIC_EN
@@ -51,20 +73,20 @@
#define RTW_NOTCH_FILTER 0
#define CONFIG_EMBEDDED_FWIMG
#define CONFIG_PHY_SETTING_WITH_ODM
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#define CONFIG_ODM_REFRESH_RAMASK
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#endif
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
/* Patch when dynamic mechanism is not ready */
//#define CONFIG_DM_PATCH
#endif
//#define CONFIG_DEBUG
//#define CONFIG_DEBUG_RTL871X
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE
#define WLAN_INTF_DBG 0
//#define CONFIG_DEBUG_DYNAMIC
@@ -81,15 +103,20 @@
//#define CONFIG_DONT_CARE_TP
//#define CONFIG_HIGH_TP
//#define CONFIG_MEMORY_ACCESS_ALIGNED
-#ifndef PLATFORM_CMSIS_RTOS // unsupported feature
#define CONFIG_POWER_SAVING
-#endif
#ifdef CONFIG_POWER_SAVING
#define CONFIG_IPS
#define CONFIG_LPS
//#define CONFIG_LPS_LCLK
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
+#ifdef CONFIG_LPS_LCLK
+ #define CONFIG_DETECT_CPWM_BY_POLLING
+ #define LPS_RPWM_WAIT_MS 300
+#endif
+#else
#define CONFIG_LPS_32K
#define TDMA_POWER_SAVING
+#endif
#define CONFIG_WAIT_PS_ACK
#endif
@@ -105,8 +132,12 @@
#define RX_AMSDU 0
#endif
-#if defined(CONFIG_PLATFORM_AMEBA_X)
- #if !defined(CONFIG_PLATFORM_8711B)
+#if defined(CONFIG_PLATFORM_8711B)
+ #define CONFIG_FW_C2H_PKT
+#endif
+
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
+ #if defined(CONFIG_PLATFORM_8195A)
#define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */
#endif
#define CONFIG_RECV_TASKLET_THREAD
@@ -126,7 +157,7 @@
#error "CONFIG_ISR_THREAD_MODE_POLLING and CONFIG_ISR_THREAD_MODE_INTERRUPT are mutually exclusive. "
#endif
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
/* CRC DMEM optimized mode consume 1k less SRM memory consumption */
#define CRC_IMPLEMENTATION_MODE CRC_IMPLEMENTATION_DMEM_OPTIMIZED
#endif
@@ -136,7 +167,7 @@
#define AES_IMPLEMENTATION_MODE AES_IMPLEMENTATION_DMEM_OPTIMIZED
#define USE_SKB_AS_XMITBUF 1
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define USE_XMIT_EXTBUFF 1
#else
#define USE_XMIT_EXTBUFF 0
@@ -149,7 +180,7 @@
#define NOT_SUPPORT_VHT
#define NOT_SUPPORT_40M
#define NOT_SUPPORT_80M
-#ifndef CONFIG_PLATFORM_8711B
+#if defined(CONFIG_PLATFORM_8195A)
#define NOT_SUPPORT_BBSWING
#endif
#define NOT_SUPPORT_OLD_CHANNEL_PLAN
@@ -164,7 +195,7 @@
#define CONFIG_AUTO_RECONNECT 1
#define ENABLE_HWPDN_PIN
#define SUPPORT_SCAN_BUF 1
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#define BE_I_CUT 1
#endif
@@ -175,7 +206,6 @@
//#define CONFIG_WPA2_PREAUTH
#define PSK_SUPPORT_TKIP 1
#endif
-//#define AP_PSK_SUPPORT_TKIP
/* For promiscuous mode */
#define CONFIG_PROMISC
@@ -190,7 +220,7 @@
// for probe request with custom vendor specific IE
#define CONFIG_CUSTOM_IE
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
/* For multicast */
#define CONFIG_MULTICAST
#endif
@@ -201,20 +231,11 @@
#if defined(CONFIG_PLATFORM_8195A)
#define CONFIG_RUNTIME_PORT_SWITCH
#endif
- #if defined(CONFIG_HARDWARE_8188F)
- #define NET_IF_NUM 2
- #else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN) + 1)
- #endif
#else
- #if defined(CONFIG_HARDWARE_8188F)
- #define NET_IF_NUM 1
- #else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN))
- #endif
#endif
-
/****************** For EAP auth configurations *******************/
#define CONFIG_TLS 0
#define CONFIG_PEAP 0
@@ -222,15 +243,17 @@
// DO NOT change the below config of EAP
#ifdef PRE_CONFIG_EAP
+#undef CONFIG_TLS
#define CONFIG_TLS 1
+#undef CONFIG_PEAP
#define CONFIG_PEAP 1
+#undef CONFIG_TTLS
#define CONFIG_TTLS 1
#endif
// enable 1X code in lib_wlan as default (increase 380 bytes)
-#ifndef PLATFORM_CMSIS_RTOS // unsupported feature
#define CONFIG_EAP
-#endif
+
#if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS
#define EAP_REMOVE_UNUSED_CODE 1
#endif
@@ -268,7 +291,7 @@
#define CONFIG_AP_MODE
extern unsigned char g_user_ap_sta_num;
#define USER_AP_STA_NUM g_user_ap_sta_num
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define AP_STA_NUM 3 //2014/10/27 modify to 3
#define USE_DEDICATED_BCN_TX 0
#if USE_DEDICATED_BCN_TX
@@ -284,7 +307,7 @@
#define CONFIG_AP_POLLING_CLIENT_ALIVE
#endif
#define CONFIG_NATIVEAP_MLME
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define CONFIG_INTERRUPT_BASED_TXBCN
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
@@ -292,14 +315,14 @@
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#endif
// #define CONFIG_GK_REKEY
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#define USE_DEDICATED_BCN_TX 1
#endif
#if CONFIG_INIC_EN
// #define REPORT_STA_EVENT //useless
#endif
#else
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#define USE_DEDICATED_BCN_TX 0
#endif
#endif
@@ -308,14 +331,14 @@
#error "If CONFIG_GK_REKEY when CONFIG_AP_MODE, need to CONFIG_MULTIPLE_WPA_STA"
#endif
-#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE)
#error "If CONFIG_CONCURRENT_MODEE, need to CONFIG_AP_MODE"
#endif
#endif
/* For efuse or flash config */
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define CONFIG_RW_PHYSICAL_EFUSE 0 // Mask efuse user blocks
#define CONFIG_HIDE_PROTECT_EFUSE 1
#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 1
@@ -333,7 +356,7 @@
#define MP_DRIVER 1
#define CONFIG_MP_IWPRIV_SUPPORT
// #define HAL_EFUSE_MEMORY
- #if defined(CONFIG_PLATFORM_AMEBA_X)
+ #if (CONFIG_PLATFORM_AMEBA_X == 1)
#define MP_REG_TEST
#endif
#else
@@ -342,10 +365,19 @@
//Control wifi mcu function
#define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
#define CONFIG_ODM_REFRESH_RAMASK
+ //#define CONFIG_ANTENNA_DIVERSITY
+ //#define CONFIG_BT_COEXIST
#endif
#endif // #ifdef CONFIG_MP_INCLUDED
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#ifdef CONFIG_BT_COEXIST
+ #undef NOT_SUPPORT_BT
+ #define CONFIG_BT_MAILBOX
+ #define CONFIG_BT_EFUSE
+ //#define CONFIG_BT_TWO_ANTENNA
+#endif
+
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#if defined(CONFIG_PLATFORM_8195A)
#undef CONFIG_RTL8195A
#define CONFIG_RTL8195A
@@ -363,9 +395,109 @@
#define CONFIG_MOVE_PSK_TO_ROM
#define CONFIG_WOWLAN
#define CONFIG_TRAFFIC_PROTECT
+ #define CONFIG_FABVERSION_UMC 1
+ #if (CONFIG_INIC_EN == 1)
+ #undef CONFIG_PROMISC
+ #undef CONFIG_WPS
+ #undef CONFIG_AP_MODE
+ #undef CONFIG_NATIVEAP_MLME
+ #undef CONFIG_INTERRUPT_BASED_TXBCN
+ #undef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+ #undef USE_DEDICATED_BCN_TX
+ //#undef SUPPORT_SCAN_BUF
+ #undef CONFIG_CONCURRENT_MODE
+ #undef CONFIG_AUTO_RECONNECT
+ #endif
+ #endif
+ #if defined(CONFIG_PLATFORM_8721D)
+ #ifndef CONFIG_RTL8721D
+ #define CONFIG_RTL8721D
+ #endif
+ #undef NOT_SUPPORT_5G
+ #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
+ #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
+ #define CONFIG_EFUSE_SEPARATE
+ #define CONFIG_WOWLAN
+ #define CONFIG_TRAFFIC_PROTECT
+ #define SUPPORT_5G_CHANNEL 1
+ #define DBG_DM_DIG 0 // DebugComponents: bit0
+ //#define CONFIG_SUPPORT_DYNAMIC_TXPWR //rtw_phydm_fill_desc_dpt todo
+ #if (CONFIG_INIC_EN == 1)
+ #undef CONFIG_PROMISC
+ #undef CONFIG_WPS
+ #undef CONFIG_AP_MODE
+ #undef CONFIG_NATIVEAP_MLME
+ #undef CONFIG_INTERRUPT_BASED_TXBCN
+ #undef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+ #undef USE_DEDICATED_BCN_TX
+ //#undef SUPPORT_SCAN_BUF
+ #undef CONFIG_CONCURRENT_MODE
+ #undef CONFIG_AUTO_RECONNECT
+ #endif
+ #endif
+ #if defined(CONFIG_PLATFORM_8195BHP)
+ #define CONFIG_RTL8195B
+ #undef CONFIG_EAP
+// #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
+// #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
+ #undef CHECK_FLASH_VALID_MASK
+ #define CHECK_FLASH_VALID_MASK 0
+ #undef CHECK_EFUSE_VALID_MASK
+ #define CHECK_EFUSE_VALID_MASK 0
+ #undef CONFIG_RW_PHYSICAL_EFUSE
+ #define CONFIG_RW_PHYSICAL_EFUSE 1 // efuse_get realraw
+ #undef NOT_SUPPORT_5G
+ #undef NOT_SUPPORT_VHT
+ #undef NOT_SUPPORT_40M
+ #undef NOT_SUPPORT_80M
+ #define CONFIG_BW_80
+ #define CONFIG_80211AC_VHT
+ #undef CONFIG_IPS
+// #define CONFIG_NO_FW
+ #define CONFIG_EX_FW_BIN
+ #define LOAD_FW_HEADER_FROM_DRIVER
+// #define RTW_IQK_FW_OFFLOAD
+ #define CONFIG_PHY_CAPABILITY_QUERY
+ #define CONFIG_FW_C2H_PKT
+ #define RTK_AC_SUPPORT
+ #define PHYDM_NEW_INTERFACE 1
+ #define CONFIG_ISR_THREAD_MODE_INTERRUPT /* Wlan IRQ Interrupt Mode*/
+// #define CONFIG_WLAN_RF_CNTL
+ #define SUPPORT_5G_CHANNEL 1
+ #define SUPPORTABLITY_PHYDMLIZE 1
+ #define CONFIG_DFS
+ #ifdef CONFIG_DFS
+ #define CONFIG_DFS_ACTION
+ #endif
+ #undef CONFIG_RF_GAIN_OFFSET
+
+ #define DBG_DM_DIG 0 // DebugComponents: bit0
+// #define CONFIG_DEBUG
+
+ #define RTW_HALMAC /* Use HALMAC architecture */
+ #define RTW_HALMAC_MU_BF 0
+ #define RTW_HALMAC_SU_BF 0
+ #define RTW_HALMAC_BT_COEX 0
+ #define RTW_HALMAC_DUMP_INFO 0
+ #define RTW_HALMAC_TXBF 0
+ #define RTW_HALMAC_FW_OFFLOAD 0
+ #define RTW_HALMAC_PHYSICAL_EFUSE 0
+ #define RTW_HALMAC_SIZE_OPTIMIZATION 1
+ #define RTW_HALMAC_SDIO_CIA_READ 0
+ #define RTW_HALMAC_LTE_COEX 0
+
+ #define CONFIG_MAC_LOOPBACK_DRIVER_RTL8195B 0
#endif
#elif defined(CONFIG_HARDWARE_8188F)
#define CONFIG_RTL8188F
+#elif defined(CONFIG_HARDWARE_8192E)
+#define CONFIG_RTL8192E
+#elif defined(CONFIG_HARDWARE_8821C)
+#define CONFIG_RTL8821C
+#elif defined(CONFIG_HARDWARE_8723D)
+#define CONFIG_RTL8723D
+#elif defined(CONFIG_HARDWARE_8188E)
+#define CONFIG_RTL8188E
#else
#define CONFIG_RTL8188E
#endif
@@ -386,37 +518,57 @@
#define RTL8188E_SUPPORT 0
#define RTL8188F_SUPPORT 0
#define RTL8711B_SUPPORT 0
+#define RTL8721D_SUPPORT 0
+#define RTL8821C_SUPPORT 0
+#define RTL8723D_SUPPORT 0
#if defined(CONFIG_PLATFORM_8195A)
#undef RTL8195A_SUPPORT
#define RTL8195A_SUPPORT 1
#elif defined(CONFIG_PLATFORM_8711B)
#undef RTL8711B_SUPPORT
#define RTL8711B_SUPPORT 1
+#elif defined(CONFIG_PLATFORM_8721D)
+#undef RTL8721D_SUPPORT
+#define RTL8721D_SUPPORT 1
+#elif defined(CONFIG_PLATFORM_8195BHP)
+#undef RTL8195B_SUPPORT
+#define RTL8195B_SUPPORT 1
#elif defined(CONFIG_HARDWARE_8188F)
#undef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 1
+#elif defined(CONFIG_HARDWARE_8192E)
+#undef RTL8192E_SUPPORT
+#define RTL8192E_SUPPORT 1
+#elif defined(CONFIG_HARDWARE_8821C)
+#undef RTL8821C_SUPPORT
+#define RTL8821C_SUPPORT 1
+#elif defined(CONFIG_HARDWARE_8723D)
+#undef RTL8723D_SUPPORT
+#define RTL8723D_SUPPORT 1
+#elif defined(CONFIG_HARDWARE_8188E)
+#undef RTL8188E_SUPPORT
+#define RTL8188E_SUPPORT 1
#else
#undef RTL8188E_SUPPORT
#define RTL8188E_SUPPORT 1
#endif
-#define TEST_CHIP_SUPPORT 0
-
-#define RTL8188E_FOR_TEST_CHIP 0
-#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
-
// for Debug message
#define DBG 0
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#if(DBG == 0)
#define ROM_E_RTW_MSG 1
+ #define ROM_F_RTW_MSG 1
+#if (CONFIG_INIC_EN == 0) && (PHYDM_LINUX_CODING_STYLE == 0)
/* For DM debug*/
// BB
#define DBG_RX_INFO 1
+ #define DBG_DM_DIG 1 // DebugComponents: bit0
+ #define DBG_DM_RA_MASK 1 // DebugComponents: bit1
+ #define DBG_DM_ANT_DIV 1 // DebugComponents: bit6
#define DBG_TX_RATE 1 // DebugComponents: bit9
#define DBG_DM_RA 1 // DebugComponents: bit9
- #define DBG_DM_DIG 1 // DebugComponents: bit0
- #define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit16
+ #define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit17
// RF
#define DBG_PWR_TRACKING 1 // DebugComponents: bit24
#define DBG_RF_IQK 1 // DebugComponents: bit26
@@ -424,13 +576,23 @@
#define DBG_PWR_INDEX 1 // DebugComponents: bit30
#endif
#endif
+#endif
/* For DM support */
-#if defined(CONFIG_RTL8188F)
+#if defined(CONFIG_RTL8188F)
+#define RATE_ADAPTIVE_SUPPORT 0
+#elif defined(CONFIG_RTL8821C)
+#define RATE_ADAPTIVE_SUPPORT 0
+#elif defined(CONFIG_RTL8192E)
+#define RATE_ADAPTIVE_SUPPORT 0
+#elif defined(CONFIG_RTL8723D)
#define RATE_ADAPTIVE_SUPPORT 0
#elif defined(CONFIG_PLATFORM_8711B)
-#define RATE_ADAPTIVE_SUPPORT 1
+#define RATE_ADAPTIVE_SUPPORT 0
#define CONFIG_ODM_REFRESH_RAMASK
+#elif defined(CONFIG_PLATFORM_8721D)
+#define RATE_ADAPTIVE_SUPPORT 0
+//#define CONFIG_ODM_REFRESH_RAMASK
#else
#define RATE_ADAPTIVE_SUPPORT 1
#endif
@@ -444,13 +606,13 @@
#define CONFIG_RTW_ADAPTIVITY_DML 0
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define CONFIG_POWER_TRAINING_WIL 0 // in RA
#else
#define POWER_BY_RATE_SUPPORT 0
#endif
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define RTL8195A_FOR_TEST_CHIP 0
//#define CONFIG_WIFI_TEST 1
@@ -466,7 +628,13 @@
#endif
#ifdef CONFIG_FPGA
//Enable mac loopback for test mode (Ameba)
- #define CONFIG_TWO_MAC_DRIVER // for test mode
+ #ifdef CONFIG_WIFI_NORMAL
+ #define CONFIG_TWO_MAC_DRIVER // for test mode
+ #else //CONFIG_WIFI_VERIFY
+ #define ENABLE_MAC_LB_FOR_TEST_MODE
+ #endif
+
+ #define AP_PSK_SUPPORT_TKIP
#endif
#ifdef ENABLE_MAC_LB_FOR_TEST_MODE
@@ -475,7 +643,7 @@
#define CONFIG_LWIP_LAYER 0
#define CONFIG_WLAN_HAL_TEST
#define CONFIG_WLAN_HAL_RX_TASK
- #define CONFIG_MAC_LOOPBACK_DRIVER_RTL8711B 1
+ #define CONFIG_MAC_LOOPBACK_DRIVER_AMEBA 1
#define HAL_MAC_ENABLE 1
#define CONFIG_TWO_MAC_TEST_MODE
#define DISABLE_BB_RF 1
@@ -508,4 +676,27 @@
#undef NOT_SUPPORT_40M
#undef CONFIG_CONCURRENT_MODE
#endif
+
+#if defined(CONFIG_HARDWARE_8821C)
+#define FW_IQK
+#define RTW_HALMAC
+#define LOAD_FW_HEADER_FROM_DRIVER
+#define RTW_HALMAC_SIZE_OPTIMIZATION 1
+//#define CONFIG_NO_FW
+#ifdef NOT_SUPPORT_5G
+#undef NOT_SUPPORT_5G
+#define SUPPORT_5G_CHANNEL 1
+#endif
+#endif
+
+#if defined(CONFIG_RTL8723D)
+#define HAL_EFUSE_MEMORY
+#endif
+
+#define CONFIG_DFS
+//#define CONFIG_EMPTY_EFUSE_PG_ENABLE
+
+#define WLAN_WAPPER_VERSION 1
+
#endif //WLANCONFIG_H
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/drv_conf.h Thu Sep 06 13:40:20 2018 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,104 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - - -#ifndef __DRV_CONF_H__ -#define __DRV_CONF_H__ - -#include "autoconf.h" -#if ((RTL8195A_SUPPORT==1) || (RTL8711B_SUPPORT==1)) -#include "platform_autoconf.h" -#endif - -#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) - -#error "Shall be Linux or Windows, but not both!\n" - -#endif - -//Older Android kernel doesn't has CONFIG_ANDROID defined, -//add this to force CONFIG_ANDROID defined -#ifdef CONFIG_PLATFORM_ANDROID -#define CONFIG_ANDROID -#endif - -#ifdef CONFIG_ANDROID -//Some Android build will restart the UI while non-printable ascii is passed -//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID -//for Android here. If you are sure there is no risk on your system about this, -//mask this macro define to support non-printable ascii ssid. -//#define CONFIG_VALIDATE_SSID -#ifdef CONFIG_PLATFORM_ARM_SUNxI - #ifdef CONFIG_VALIDATE_SSID - #undef CONFIG_VALIDATE_SSID - #endif -#endif - -//Android expect dbm as the rx signal strength unit -#define CONFIG_SIGNAL_DISPLAY_DBM -#endif - -#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE) - #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" - #undef CONFIG_RESUME_IN_WORKQUEUE -#endif - -#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE) - #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" - #undef CONFIG_RESUME_IN_WORKQUEUE -#endif - -#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this... - #if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) - #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." - #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." - #endif -#endif - -//About USB VENDOR REQ -#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) - #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" - #define CONFIG_USB_VENDOR_REQ_MUTEX -#endif -#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) - #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" - #define CONFIG_USB_VENDOR_REQ_MUTEX -#endif - -#ifndef CONFIG_RTW_ADAPTIVITY_EN - #define CONFIG_RTW_ADAPTIVITY_EN 0 -#endif - -#ifndef CONFIG_RTW_ADAPTIVITY_MODE - #define CONFIG_RTW_ADAPTIVITY_MODE 0 -#endif - -#ifndef CONFIG_RTW_ADAPTIVITY_DML - #define CONFIG_RTW_ADAPTIVITY_DML 0 -#endif - -#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF - #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 4 -#endif - -#ifndef CONFIG_RTW_NHM_EN - #define CONFIG_RTW_NHM_EN 0 -#endif - -//#include <rtl871x_byteorder.h> - -#endif // __DRV_CONF_H__ -
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rom_aes.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/******************************************************************************
- *
- * mbed Microcontroller Library
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- *
- * This is ROM code section.
- *
- ******************************************************************************/
-#ifndef ROM_AES_H
-#define ROM_AES_H
-
-typedef struct
-{
- u32 erk[64]; /* encryption round keys */
- u32 drk[64]; /* decryption round keys */
- int nr; /* number of rounds */
-}aes_context;
-
-
-#define AES_BLOCKSIZE8 8
-#define AES_BLK_SIZE 16 // # octets in an AES block
-typedef union _aes_block // AES cipher block
-{
- unsigned long x[AES_BLK_SIZE/4]; // access as 8-bit octets or 32-bit words
- unsigned char b[AES_BLK_SIZE];
-}aes_block;
-
-
-void AES_WRAP(unsigned char * plain, int plain_len,
- unsigned char * iv, int iv_len,
- unsigned char * kek, int kek_len,
- unsigned char *cipher, unsigned short *cipher_len);
-
-void AES_UnWRAP(unsigned char * cipher, int cipher_len,
- unsigned char * kek, int kek_len,
- unsigned char * plain);
-
-#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/rtw_debug.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,453 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- ******************************************************************************/
-
-#ifndef __RTW_DEBUG_H__
-#define __RTW_DEBUG_H__
-
-
-#define _drv_always_ 1
-#define _drv_emerg_ 2
-#define _drv_alert_ 3
-#define _drv_crit_ 4
-#define _drv_err_ 5
-#define _drv_warning_ 6
-#define _drv_notice_ 7
-#define _drv_info_ 8
-#define _drv_dump_ 9
-#define _drv_debug_ 10
-
-
-#define _module_rtl871x_xmit_c_ BIT(0)
-#define _module_xmit_osdep_c_ BIT(1)
-#define _module_rtl871x_recv_c_ BIT(2)
-#define _module_recv_osdep_c_ BIT(3)
-#define _module_rtl871x_mlme_c_ BIT(4)
-#define _module_mlme_osdep_c_ BIT(5)
-#define _module_rtl871x_sta_mgt_c_ BIT(6)
-#define _module_rtl871x_cmd_c_ BIT(7)
-#define _module_cmd_osdep_c_ BIT(8)
-#define _module_rtl871x_io_c_ BIT(9)
-#define _module_io_osdep_c_ BIT(10)
-#define _module_os_intfs_c_ BIT(11)
-#define _module_rtl871x_security_c_ BIT(12)
-#define _module_rtl871x_eeprom_c_ BIT(13)
-#define _module_hal_init_c_ BIT(14)
-#define _module_hci_hal_init_c_ BIT(15)
-#define _module_rtl871x_ioctl_c_ BIT(16)
-#define _module_rtl871x_ioctl_set_c_ BIT(17)
-#define _module_rtl871x_ioctl_query_c_ BIT(18)
-#define _module_rtl871x_pwrctrl_c_ BIT(19)
-#define _module_hci_intfs_c_ BIT(20)
-#define _module_hci_ops_c_ BIT(21)
-#define _module_osdep_service_c_ BIT(22)
-#define _module_mp_ BIT(23)
-#define _module_hci_ops_os_c_ BIT(24)
-#define _module_rtl871x_ioctl_os_c BIT(25)
-#define _module_rtl8712_cmd_c_ BIT(26)
-#define _module_fwcmd_c_ BIT(27)
-#define _module_rtl8192c_xmit_c_ BIT(28)
-#define _module_hal_xmit_c_ BIT(28)
-#define _module_efuse_ BIT(29)
-#define _module_rtl8712_recv_c_ BIT(30)
-#define _module_rtl8712_led_c_ BIT(31)
-
-#undef _MODULE_DEFINE_
-
-#if defined _RTW_XMIT_C_
- #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_
-#elif defined _XMIT_OSDEP_C_
- #define _MODULE_DEFINE_ _module_xmit_osdep_c_
-#elif defined _RTW_RECV_C_
- #define _MODULE_DEFINE_ _module_rtl871x_recv_c_
-#elif defined _RECV_OSDEP_C_
- #define _MODULE_DEFINE_ _module_recv_osdep_c_
-#elif defined _RTW_MLME_C_
- #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_
-#elif defined _MLME_OSDEP_C_
- #define _MODULE_DEFINE_ _module_mlme_osdep_c_
-#elif defined _RTW_MLME_EXT_C_
- #define _MODULE_DEFINE_ 1
-#elif defined _RTW_STA_MGT_C_
- #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_
-#elif defined _RTW_CMD_C_
- #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_
-#elif defined _CMD_OSDEP_C_
- #define _MODULE_DEFINE_ _module_cmd_osdep_c_
-#elif defined _RTW_IO_C_
- #define _MODULE_DEFINE_ _module_rtl871x_io_c_
-#elif defined _IO_OSDEP_C_
- #define _MODULE_DEFINE_ _module_io_osdep_c_
-#elif defined _OS_INTFS_C_
- #define _MODULE_DEFINE_ _module_os_intfs_c_
-#elif defined _RTW_SECURITY_C_
- #define _MODULE_DEFINE_ _module_rtl871x_security_c_
-#elif defined _RTW_EEPROM_C_
- #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_
-#elif defined _HAL_INTF_C_
- #define _MODULE_DEFINE_ _module_hal_init_c_
-#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_)
- #define _MODULE_DEFINE_ _module_hci_hal_init_c_
-#elif defined _RTL871X_IOCTL_C_
- #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_
-#elif defined _RTL871X_IOCTL_SET_C_
- #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_
-#elif defined _RTL871X_IOCTL_QUERY_C_
- #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_
-#elif defined _RTL871X_PWRCTRL_C_
- #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_
-#elif defined _RTW_PWRCTRL_C_
- #define _MODULE_DEFINE_ 1
-#elif defined _HCI_INTF_C_
- #define _MODULE_DEFINE_ _module_hci_intfs_c_
-#elif defined _HCI_OPS_C_
- #define _MODULE_DEFINE_ _module_hci_ops_c_
-#elif defined _SDIO_OPS_C_
- #define _MODULE_DEFINE_ 1
-#elif defined _OSDEP_HCI_INTF_C_
- #define _MODULE_DEFINE_ _module_hci_intfs_c_
-#elif defined _OSDEP_SERVICE_C_
- #define _MODULE_DEFINE_ _module_osdep_service_c_
-#elif defined _HCI_OPS_OS_C_
- #define _MODULE_DEFINE_ _module_hci_ops_os_c_
-#elif defined _RTL871X_IOCTL_LINUX_C_
- #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c
-#elif defined _RTL8712_CMD_C_
- #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_
-#elif defined _RTL8192C_XMIT_C_
- #define _MODULE_DEFINE_ 1
-#elif defined _RTL8723AS_XMIT_C_
- #define _MODULE_DEFINE_ 1
-#elif defined _RTL8712_RECV_C_
- #define _MODULE_DEFINE_ _module_rtl8712_recv_c_
-#elif defined _RTL8192CU_RECV_C_
- #define _MODULE_DEFINE_ _module_rtl8712_recv_c_
-#elif defined _RTL871X_MLME_EXT_C_
- #define _MODULE_DEFINE_ _module_mlme_osdep_c_
-#elif defined _RTW_MP_C_
- #define _MODULE_DEFINE_ _module_mp_
-#elif defined _RTW_MP_IOCTL_C_
- #define _MODULE_DEFINE_ _module_mp_
-#elif defined _RTW_EFUSE_C_
- #define _MODULE_DEFINE_ _module_efuse_
-#endif
-
-#ifdef PLATFORM_OS_CE
-extern void rtl871x_cedbg(const char *fmt, ...);
-#endif
-
-#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0)
-#define _func_enter_ do{}while(0)
-#define _func_exit_ do{}while(0)
-#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0)
-
-#ifdef PLATFORM_WINDOWS
- #define DBG_871X do {} while(0)
- #define MSG_8192C do {} while(0)
- #define DBG_8192C do {} while(0)
- #define DBG_871X_LEVEL do {} while(0)
-#else
- #define DBG_871X(x, ...) do {} while(0)
- #define MSG_8192C(x, ...) do {} while(0)
- #define DBG_8192C(x,...) do {} while(0)
- #define DBG_871X_LEVEL(x,...) do {} while(0)
-#endif
-
-#undef _dbgdump
-#ifdef PLATFORM_WINDOWS
-
- #ifdef PLATFORM_OS_XP
- #define _dbgdump DbgPrint
- #elif defined PLATFORM_OS_CE
- #define _dbgdump rtl871x_cedbg
- #endif
-
-#elif defined PLATFORM_LINUX
- #define _dbgdump printk
-#elif defined PLATFORM_ECOS
- #define _dbgdump diag_printf
-#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
- #define _dbgdump printf("\n\r"); printf
-#elif defined PLATFORM_FREEBSD
- #define _dbgdump printf
-#endif
-
-#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
-#define DRIVER_PREFIX "RTL871X: "
-#endif
-
-#define DEBUG_LEVEL (_drv_err_)
-#if defined (_dbgdump)
- #undef DBG_871X_LEVEL
-#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
- #define DBG_871X_LEVEL(level, ...) \
- do {\
- _dbgdump(DRIVER_PREFIX __VA_ARGS__);\
- }while(0)
-#else
- #define DBG_871X_LEVEL(level, fmt, arg...) \
- do {\
- if (level <= DEBUG_LEVEL) {\
- if (level <= _drv_err_ && level > _drv_always_) {\
- _dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
- } \
- else {\
- _dbgdump(DRIVER_PREFIX fmt, ##arg);\
- } \
- }\
- }while(0)
-#endif //#ifdef __CC_ARM
-#endif
-
-#ifdef CONFIG_DEBUG
-#if defined (_dbgdump)
- #undef DBG_871X
- #define DBG_871X(...) do {\
- _dbgdump(DRIVER_PREFIX __VA_ARGS__);\
- }while(0)
-
- #undef MSG_8192C
- #define MSG_8192C(...) do {\
- _dbgdump(DRIVER_PREFIX __VA_ARGS__);\
- }while(0)
-
- #undef DBG_8192C
- #define DBG_8192C(...) do {\
- _dbgdump(DRIVER_PREFIX __VA_ARGS__);\
- }while(0)
-#endif
-#endif /* CONFIG_DEBUG */
-
-#ifdef CONFIG_DEBUG_RTL871X
-#ifndef _RTL871X_DEBUG_C_
- extern u32 GlobalDebugLevel;
- extern u64 GlobalDebugComponents;
-#endif
-
-#if defined (_dbgdump) && defined (_MODULE_DEFINE_)
-
- #undef RT_TRACE
- #define RT_TRACE(_Comp, _Level, Fmt)\
- do {\
- if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
- _dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\
- _dbgdump Fmt;\
- }\
- }while(0)
-
-#endif
-
-
-#if defined (_dbgdump)
-
- #undef _func_enter_
- #define _func_enter_ \
- do { \
- if (GlobalDebugLevel >= _drv_debug_) \
- { \
- _dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\
- } \
- } while(0)
-
- #undef _func_exit_
- #define _func_exit_ \
- do { \
- if (GlobalDebugLevel >= _drv_debug_) \
- { \
- _dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \
- } \
- } while(0)
-
- #undef RT_PRINT_DATA
- #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
- if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
- { \
- int __i; \
- u8 *ptr = (u8 *)_HexData; \
- printf("\r\n%s", DRIVER_PREFIX); \
- printf(_TitleString "--------Len=%d\n\r", _HexDataLen); \
- for( __i=0; __i<(int)_HexDataLen; __i++ ) \
- { \
- printf("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
- if (((__i + 1) % 16) == 0) printf("\n\r"); \
- } \
- printf("\n\r"); \
- }
-#endif
-#endif /* CONFIG_DEBUG_RTL871X */
-
-
-#ifdef CONFIG_PROC_DEBUG
-
- int proc_get_drv_version(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_write_reg(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_write_reg(struct file *file, const char *buffer,
- unsigned long count, void *data);
-
- int proc_get_read_reg(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_read_reg(struct file *file, const char *buffer,
- unsigned long count, void *data);
-
-
- int proc_get_fwstate(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_sec_info(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_mlmext_state(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_qos_option(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_ht_option(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rf_info(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_ap_info(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_adapter_state(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_trx_info(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_mac_reg_dump1(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_mac_reg_dump2(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_mac_reg_dump3(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_bb_reg_dump1(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_bb_reg_dump2(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_bb_reg_dump3(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rf_reg_dump1(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rf_reg_dump2(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rf_reg_dump3(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rf_reg_dump4(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
-#ifdef CONFIG_AP_MODE
-
- int proc_get_all_sta_info(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
-#endif
-
-#ifdef DBG_MEMORY_LEAK
- int proc_get_malloc_cnt(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-#endif
-
-#ifdef CONFIG_FIND_BEST_CHANNEL
- int proc_get_best_channel(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-#endif
-
- int proc_get_rx_signal(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_rx_signal(struct file *file, const char *buffer,
- unsigned long count, void *data);
-#ifdef CONFIG_80211N_HT
- int proc_get_cbw40_enable(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_cbw40_enable(struct file *file, const char *buffer,
- unsigned long count, void *data);
-
- int proc_get_ampdu_enable(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_ampdu_enable(struct file *file, const char *buffer,
- unsigned long count, void *data);
-
- int proc_get_rx_stbc(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_rx_stbc(struct file *file, const char *buffer,
- unsigned long count, void *data);
-#endif //CONFIG_80211N_HT
-
- int proc_get_two_path_rssi(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_get_rssi_disp(char *page, char **start,
- off_t offset, int count,
- int *eof, void *data);
-
- int proc_set_rssi_disp(struct file *file, const char *buffer,
- unsigned long count, void *data);
-
-
-#endif //CONFIG_PROC_DEBUG
-
-#endif //__RTW_DEBUG_H__
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_constants.h Thu Nov 08 11:46:34 2018 +0000
@@ -23,6 +23,12 @@
#ifndef _WIFI_CONSTANTS_H
#define _WIFI_CONSTANTS_H
+/** @addtogroup nic NIC
+ * @ingroup wlan
+ * @brief NIC functions
+ * @{
+ */
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -46,7 +52,6 @@
#define RTW_MAX_PSK_LEN (64)
#define RTW_MIN_PSK_LEN (8)
-
#define MCSSET_LEN 16
/**
@@ -67,7 +72,6 @@
RTW_BUFFER_UNAVAILABLE_PERMANENT = 10, /**< Buffer unavailable permanently */
RTW_WPS_PBC_OVERLAP = 11, /**< WPS PBC overlap */
RTW_CONNECTION_LOST = 12, /**< Connection lost */
-
RTW_ERROR = -1, /**< Generic Error */
RTW_BADARG = -2, /**< Bad Argument */
RTW_BADOPTION = -3, /**< Bad option */
@@ -129,12 +133,9 @@
RTW_SECURITY_WPA2_TKIP_PSK = ( WPA2_SECURITY | TKIP_ENABLED ), /**< WPA2 Security with TKIP */
RTW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ), /**< WPA2 Security with AES & TKIP */
RTW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY | WPA2_SECURITY ), /**< WPA/WPA2 Security */
-
RTW_SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */
RTW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */
-
RTW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */
-
RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */
};
typedef unsigned long rtw_security_t;
@@ -181,6 +182,7 @@
RTW_COUNTRY_FCC2, // 0x2A
RTW_COUNTRY_WORLD2, // 0x47
RTW_COUNTRY_MKK2, // 0x58
+ RTW_COUNTRY_GLOBAL, // 0x41
/* SPECIAL */
RTW_COUNTRY_WORLD, // WORLD1
@@ -364,9 +366,7 @@
RTW_COUNTRY_YT,
RTW_COUNTRY_ZA,
RTW_COUNTRY_ZW,
-
RTW_COUNTRY_MAX
-
};
typedef unsigned long rtw_country_code_t;
@@ -402,6 +402,15 @@
typedef unsigned long rtw_scan_mode_t;
/**
+ * @brief The enumeration lists the supported autoreconnect mode by WIFI driver.
+ */
+typedef enum{
+ RTW_AUTORECONNECT_DISABLE,
+ RTW_AUTORECONNECT_FINITE,
+ RTW_AUTORECONNECT_INFINITE
+} rtw_autoreconnect_mode_t;
+
+/**
* @brief The enumeration lists the status to describe the connection link.
*/
enum {
@@ -449,7 +458,8 @@
RTW_WPS_TYPE_REKEY = 0x0003,
RTW_WPS_TYPE_PUSHBUTTON = 0x0004,
RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005,
- RTW_WPS_TYPE_NONE = 0x0006
+ RTW_WPS_TYPE_NONE = 0x0006,
+ RTW_WPS_TYPE_WSC = 0x0007
};
typedef unsigned long rtw_wps_type_t;
@@ -490,10 +500,21 @@
RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
+ RTW_PROMISC_ENABLE_4 = 5, /**< Fetch all 802.11 packets & MIMO PLCP headers. Please note that the PLCP header would be struct rtw_rx_info_t defined in wifi_structures.h*/
};
typedef unsigned long rtw_rcr_level_t;
/**
+ * @brief The enumeration lists the promisc rx type.
+ */
+#if CONFIG_UNSUPPORT_PLCPHDR_RPT
+enum {
+ RTW_RX_NORMAL = 0, /**< The supported 802.11 packet*/
+ RTW_RX_UNSUPPORT = 1, /**< Unsupported 802.11 packet info */
+};
+typedef unsigned long rtw_rx_type_t;
+#endif
+/**
* @brief The enumeration lists the disconnect reasons.
*/
enum{
@@ -501,7 +522,8 @@
RTW_NONE_NETWORK = 1,
RTW_CONNECT_FAIL = 2,
RTW_WRONG_PASSWORD = 3 ,
- RTW_DHCP_FAIL = 4,
+ RTW_4WAY_HANDSHAKE_TIMEOUT = 4,
+ RTW_DHCP_FAIL = 5,
RTW_UNKNOWN,
};
typedef unsigned long rtw_connect_error_flag_t;
@@ -535,10 +557,16 @@
WIFI_EVENT_EAPOL_RECVD = 13,
WIFI_EVENT_NO_NETWORK = 14,
WIFI_EVENT_BEACON_AFTER_DHCP = 15,
+ WIFI_EVENT_IP_CHANGED = 16,
+ WIFI_EVENT_ICV_ERROR = 17,
+ WIFI_EVENT_CHALLENGE_FAIL = 18,
WIFI_EVENT_MAX,
};
typedef unsigned long rtw_event_indicate_t;
#ifdef __cplusplus
}
#endif
+
+/*\@}*/
+
#endif /* _WIFI_CONSTANTS_H */
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_structures.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/include/wifi_structures.h Thu Nov 08 11:46:34 2018 +0000
@@ -12,7 +12,7 @@
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- ******************************************************************************
+ ******************************************************************************
* @file wifi_structures.h
* @author
* @version
@@ -23,6 +23,12 @@
#ifndef _WIFI_STRUCTURES_H
#define _WIFI_STRUCTURES_H
+/** @addtogroup nic NIC
+ * @ingroup wlan
+ * @brief NIC functions
+ * @{
+ */
+
//#include <freertos/freertos_service.h>
#include "wifi_constants.h"
#include "dlist.h"
@@ -30,7 +36,7 @@
extern "C" {
#endif
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack(1)
#endif
@@ -41,11 +47,11 @@
unsigned char len; /**< SSID length */
unsigned char val[33]; /**< SSID name (AP name) */
} rtw_ssid_t;
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack()
#endif
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack(1)
#endif
@@ -55,14 +61,15 @@
typedef struct rtw_mac {
unsigned char octet[6]; /**< Unique 6-byte MAC address */
} rtw_mac_t;
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined (__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack()
#endif
/**
* @brief The structure is used to describe the setting about SSID,
* security type, password and default channel, used to start AP mode.
- * @note The data length of string pointed by ssid and password should not exceed 32.
+ * @note The data length of string pointed by ssid should not exceed 32,
+ * and the data length of string pointed by password should not exceed 64.
*/
typedef struct rtw_ap_info {
rtw_ssid_t ssid;
@@ -75,7 +82,8 @@
/**
* @brief The structure is used to describe the station mode setting about SSID,
* security type and password, used when connecting to an AP.
- * @note The data length of string pointed by ssid and password should not exceed 32.
+ * @note The data length of string pointed by ssid should not exceed 32,
+ * and the data length of string pointed by password should not exceed 64.
*/
typedef struct rtw_network_info {
rtw_ssid_t ssid;
@@ -86,7 +94,7 @@
int key_id;
}rtw_network_info_t;
-#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack(1)
#endif
@@ -103,7 +111,7 @@
unsigned int channel; /**< Radio channel that the AP beacon was received on */
rtw_802_11_band_t band; /**< Radio band */
} rtw_scan_result_t;
-#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack()
#endif
@@ -117,7 +125,7 @@
} rtw_scan_handler_result_t;
-#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack(1)
#endif
@@ -132,7 +140,7 @@
unsigned char password[65];
unsigned char key_idx;
}rtw_wifi_setting_t;
-#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) || defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma pack()
#endif
@@ -210,8 +218,33 @@
unsigned char bssid[6];
unsigned char encrypt;
signed char rssi;
+#if CONFIG_UNSUPPORT_PLCPHDR_RPT
+ rtw_rx_type_t type;
+#endif
}ieee80211_frame_info_t;
+#if CONFIG_UNSUPPORT_PLCPHDR_RPT
+typedef struct rtw_rx_info {
+ uint16_t length; //length without FCS
+ uint8_t filter; // 2: 2T rate pkt; 3: LDPC pkt
+ signed char rssi; //-128~-1
+}rtw_rx_info_t;
+
+struct rtw_plcp_info {
+ struct rtw_plcp_info *prev;
+ struct rtw_plcp_info *next;
+ uint16_t length; //length without FCS
+ uint8_t filter; // 1: HT-20 pkt; 2: HT-40 and not LDPC pkt; 3: LDPC pkt
+ signed char rssi; //-128~-1
+};
+
+struct rtw_rx_buffer {
+ struct rtw_plcp_info *head;
+ struct rtw_plcp_info *tail;
+};
+
+#endif
+
typedef struct {
char filter_id;
rtw_packet_filter_pattern_t patt;
@@ -228,4 +261,6 @@
}
#endif
+/*\@}*/
+
#endif /* _WIFI_STRUCTURES_H */
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h Thu Nov 08 11:46:34 2018 +0000
@@ -18,7 +18,6 @@
#ifndef __WRAPPER_H__
#define __WRAPPER_H__
-
//----- ------------------------------------------------------------------
// Include Files
//----- ------------------------------------------------------------------
@@ -26,11 +25,8 @@
#include <string.h>
#include "wireless.h"
#include <skbuff.h>
-#ifdef PLATFORM_FREERTOS
-#include "freertos_service.h"
-#elif defined(PLATFORM_CMSIS_RTOS)
-#include "rtx_service.h"
-#endif
+#include "osdep_service.h"
+
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
//----- ------------------------------------------------------------------
@@ -50,7 +46,6 @@
// };
#define LIST_HEAD_INIT(name) { &(name), &(name) }
-
#define INIT_LIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
@@ -302,7 +297,6 @@
static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
struct sk_buff *prev, *next;
-
newsk->list = list;
list->qlen++;
next = (struct sk_buff *)list;
@@ -333,7 +327,7 @@
}
static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len)
-{
+{
skb->head = buf;
skb->data = buf;
skb->tail = buf;
@@ -452,5 +446,3 @@
#endif //__WRAPPER_H__
-
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c Thu Nov 08 11:46:34 2018 +0000
@@ -4,7 +4,7 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
@@ -19,31 +19,24 @@
#include <autoconf.h>
#include <lwip_intf.h>
#include <lwip/netif.h>
-
#if !defined(CONFIG_MBED_ENABLED)
#include <lwip_netconf.h>
#include <ethernetif.h>
#endif
-
#include <osdep_service.h>
#include <wifi/wifi_util.h>
-
//----- ------------------------------------------------------------------
// External Reference
//----- ------------------------------------------------------------------
#if (CONFIG_LWIP_LAYER == 1)
-#if defined(CONFIG_MBED_ENABLED)
- extern struct netif *xnetif[];
-#else
- extern struct netif xnetif[]; //LWIP netif
-#endif
+extern struct netif xnetif[]; //LWIP netif
#endif
/**
* rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device
* @idx_wlan: netif index
- * 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode,
- * 1 for SoftAP in STA+SoftAP concurrent mode
+ * 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode,
+ * 1 for SoftAP in STA+SoftAP concurrent mode
* @dev: register netdev pointer to LWIP. Reserved.
* @dev_addr: set netif hw address
*
@@ -53,11 +46,11 @@
{
#if (CONFIG_LWIP_LAYER == 1)
#if defined(CONFIG_MBED_ENABLED)
- //rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6);
- //set netif hwaddr later
+ //rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6);
+ //set netif hwaddr later
#else
- rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
- xnetif[idx_wlan].state = dev;
+ rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
+ xnetif[idx_wlan].state = dev;
#endif
#endif
}
@@ -74,45 +67,45 @@
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len)
{
#if (CONFIG_LWIP_LAYER == 1)
- struct eth_drv_sg *last_sg;
- struct sk_buff *skb = NULL;
- int ret = 0;
+ struct eth_drv_sg *last_sg;
+ struct sk_buff *skb = NULL;
+ int ret = 0;
- if (idx == -1) {
- DBG_ERR("netif is DOWN");
- return -1;
- }
- DBG_TRACE("%s is called", __FUNCTION__);
+ if(idx == -1){
+ DBG_ERR("netif is DOWN");
+ return -1;
+ }
+ DBG_TRACE("%s is called", __FUNCTION__);
- save_and_cli();
- if (rltk_wlan_check_isup(idx)) {
- rltk_wlan_tx_inc(idx);
- } else {
- DBG_ERR("netif is DOWN");
- restore_flags();
- return -1;
- }
- restore_flags();
+ save_and_cli();
+ if (rltk_wlan_check_isup(idx)) {
+ rltk_wlan_tx_inc(idx);
+ } else {
+ DBG_ERR("netif is DOWN");
+ restore_flags();
+ return -1;
+ }
+ restore_flags();
- skb = rltk_wlan_alloc_skb(total_len);
- if (skb == NULL) {
- //DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
- ret = -1;
- goto exit;
- }
+ skb = rltk_wlan_alloc_skb(total_len);
+ if (skb == NULL) {
+ //DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
+ ret = -1;
+ goto exit;
+ }
- for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
- rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
- skb_put(skb, sg_list->len);
- }
+ for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+ rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
+ skb_put(skb, sg_list->len);
+ }
- rltk_wlan_send_skb(idx, skb);
+ rltk_wlan_send_skb(idx, skb);
exit:
- save_and_cli();
- rltk_wlan_tx_dec(idx);
- restore_flags();
- return ret;
+ save_and_cli();
+ rltk_wlan_tx_dec(idx);
+ restore_flags();
+ return ret;
#endif
}
@@ -127,128 +120,130 @@
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
{
#if (CONFIG_LWIP_LAYER == 1)
- struct eth_drv_sg *last_sg;
- struct sk_buff *skb;
-
- DBG_TRACE("%s is called", __FUNCTION__);
-
- if (!rltk_wlan_check_isup(idx)) {
- return;
- }
+ struct eth_drv_sg *last_sg;
+ struct sk_buff *skb;
+
+ DBG_TRACE("%s is called", __FUNCTION__);
+ if(idx == -1){
+ DBG_ERR("skb is NULL");
+ return;
+ }
+ skb = rltk_wlan_get_recv_skb(idx);
+ DBG_ASSERT(skb, "No pending rx skb");
- if (idx == -1) {
- DBG_ERR("skb is NULL");
- return;
- }
-
- skb = rltk_wlan_get_recv_skb(idx);
- DBG_ASSERT(skb, "No pending rx skb");
-
- for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
- if (sg_list->buf != 0) {
- rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
- skb_pull(skb, sg_list->len);
- }
- }
+ for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+ if (sg_list->buf != 0) {
+ rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
+ skb_pull(skb, sg_list->len);
+ }
+ }
#endif
}
int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{
-#if CONFIG_LWIP_LAYER == 1
#if defined(CONFIG_MBED_ENABLED)
- return 1;
+ return 1;
#else
- struct netif *pnetif = &xnetif[idx];
+#if CONFIG_LWIP_LAYER == 1
+ struct netif * pnetif = &xnetif[idx];
- ip_addr_t addr = { 0 };
+ ip_addr_t addr = { 0 };
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
- unsigned int temp;
- memcpy(&temp, ip_dest, sizeof(unsigned int));
- u32_t *ip_dest_addr = &temp;
+ unsigned int temp;
+ memcpy(&temp, ip_dest, sizeof(unsigned int));
+ u32_t *ip_dest_addr = &temp;
#else
- u32_t *ip_dest_addr = (u32_t*)ip_dest;
+ u32_t *ip_dest_addr = (u32_t*)ip_dest;
#endif
- addr.addr = *ip_dest_addr;
-
- if (pnetif->ip_addr.addr == 0) {
- return 1;
- }
- if (ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)) {
- return 1;
- }
+#if LWIP_VERSION_MAJOR >= 2
+ ip_addr_set_ip4_u32(&addr, *ip_dest_addr);
+#else
+ addr.addr = *ip_dest_addr;
+#endif
+
+#if (LWIP_VERSION_MAJOR >= 2)
+ if((ip_addr_get_ip4_u32(netif_ip_addr4(pnetif))) == 0)
+ return 1;
+#else
- //if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
- // return 1;
+ if(pnetif->ip_addr.addr == 0)
+ return 1;
+#endif
- if (ip_addr_cmp(&(pnetif->ip_addr),&addr)) {
- return 1;
- }
+ if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){
+ return 1;
+ }
+
+ //if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
+ // return 1;
- DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
-#endif
+ if(ip_addr_cmp(&(pnetif->ip_addr),&addr))
+ return 1;
+
+ DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
+#endif
#ifdef CONFIG_DONT_CARE_TP
- if (pnetif->flags & NETIF_FLAG_IPSWITCH) {
- return 1;
- }
- else
+ if(pnetif->flags & NETIF_FLAG_IPSWITCH)
+ return 1;
+ else
#endif
- return 0;
+ return 0;
#endif
}
-#if defined(CONFIG_MBED_ENABLED)
-
-#else
-int netif_get_idx(struct netif *pnetif)
+#if !defined(CONFIG_MBED_ENABLED)
+int netif_get_idx(struct netif* pnetif)
{
#if (CONFIG_LWIP_LAYER == 1)
- int idx = pnetif - xnetif;
+ int idx = pnetif - xnetif;
- switch (idx) {
- case 0:
- return 0;
- case 1:
- return 1;
- default:
- return -1;
- }
-#else
- return -1;
+ switch(idx) {
+ case 0:
+ return 0;
+ case 1:
+ return 1;
+ default:
+ return -1;
+ }
+#else
+ return -1;
#endif
}
unsigned char *netif_get_hwaddr(int idx_wlan)
{
#if (CONFIG_LWIP_LAYER == 1)
- return xnetif[idx_wlan].hwaddr;
+ return xnetif[idx_wlan].hwaddr;
#else
- return NULL;
+ return NULL;
#endif
}
#endif
+#if defined(CONFIG_MBED_ENABLED)
emac_callback emac_callback_func = NULL;
void *emac_callback_data = NULL;
-void set_callback_func(emac_callback p, void *data) {
- emac_callback_func = p;
- emac_callback_data = data;
+void set_callback_func(emac_callback p, void *data)
+{
+ emac_callback_func = p;
+ emac_callback_data = data;
}
+#endif
void netif_rx(int idx, unsigned int len)
{
#if (CONFIG_LWIP_LAYER == 1)
#if defined(CONFIG_MBED_ENABLED)
- emac_callback_func(emac_callback_data, NULL, len);
+ emac_callback_func(emac_callback_data, NULL, len);
#else
- ethernetif_recv(&xnetif[idx], len);
+ ethernetif_recv(&xnetif[idx], len);
#endif
#endif
-
#if (CONFIG_INIC_EN == 1)
- inic_netif_rx(idx, len);
+ inic_netif_rx(idx, len);
#endif
}
@@ -257,7 +252,7 @@
#if (CONFIG_LWIP_LAYER == 1)
#if defined(CONFIG_MBED_ENABLED)
#else
- lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
+ lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
#endif
#endif
}
@@ -267,7 +262,7 @@
#if (CONFIG_LWIP_LAYER == 1)
#if defined(CONFIG_MBED_ENABLED)
#else
- lwip_PRE_SLEEP_PROCESSING();
+ lwip_PRE_SLEEP_PROCESSING();
#endif
#endif
}
@@ -275,9 +270,9 @@
#ifdef CONFIG_WOWLAN
unsigned char *rltk_wlan_get_ip(int idx){
#if (CONFIG_LWIP_LAYER == 1)
- return LwIP_GetIP(&xnetif[idx]);
+ return LwIP_GetIP(&xnetif[idx]);
#else
- return NULL;
+ return NULL;
#endif
}
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h Thu Nov 08 11:46:34 2018 +0000
@@ -30,12 +30,12 @@
//----- ------------------------------------------------------------------
#if defined(CONFIG_MBED_ENABLED)
struct eth_drv_sg {
- unsigned int buf;
- unsigned int len;
+ unsigned int buf;
+ unsigned int len;
};
-#define MAX_ETH_DRV_SG 32
-#define MAX_ETH_MSG 1540
+#define MAX_ETH_DRV_SG 32
+#define MAX_ETH_MSG 1540
#else
#include "ethernetif.h" // moved to ethernetif.h by jimmy 12/2/2015
#endif
@@ -52,8 +52,11 @@
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len);
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
+
+#if defined(CONFIG_MBED_ENABLED)
typedef void (*emac_callback)(void *param, struct netif *netif, unsigned int len);
void set_callback_func(emac_callback p, void *data);
+#endif
//----- ------------------------------------------------------------------
// Network Interface provided
@@ -73,7 +76,6 @@
extern void lwip_POST_SLEEP_PROCESSING(void);
#endif //CONFIG_LWIP_LAYER == 1
-
#ifdef CONFIG_WOWLAN
extern unsigned char *rltk_wlan_get_ip(int idx);
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h Thu Nov 08 11:46:34 2018 +0000 @@ -1206,4 +1206,6 @@ #define IW_EVT_STR_STA_DISASSOC "STA Disassoc" #define IW_EVT_STR_SEND_ACTION_DONE "Send Action Done" #define IW_EVT_STR_NO_NETWORK "No Assoc Network After Scan Done" +#define IW_EVT_STR_ICV_ERROR "ICV Eror" +#define IW_EVT_STR_CHALLENGE_FAIL "Auth Challenge Fail" #endif /* _LINUX_WIRELESS_H */
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h Thu Nov 08 11:46:34 2018 +0000 @@ -67,6 +67,7 @@ int rltk_wlan_rf_off(void); int rltk_wlan_check_bus(void); int rltk_wlan_wireless_mode(unsigned char mode); +int rltk_wlan_get_wireless_mode(unsigned char *pmode); int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps); int rtw_ps_enable(int enable); int rltk_wlan_is_connected_to_ap(void);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,757 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-#include "osdep_service.h"
-#include "dhcps.h"
-#include "tcpip.h"
-
-//static struct dhcp_server_state dhcp_server_state_machine;
-static uint8_t dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
-/* recorded the client MAC addr(default sudo mac) */
-//static uint8_t dhcps_record_first_client_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
-/* recorded transaction ID (default sudo id)*/
-static uint8_t dhcp_recorded_xid[4] = {0xff, 0xff, 0xff, 0xff};
-
-/* UDP Protocol Control Block(PCB) */
-static struct udp_pcb *dhcps_pcb;
-
-static ip_addr_t dhcps_send_broadcast_address;
-static ip_addr_t dhcps_local_address;
-static ip_addr_t dhcps_pool_start;
-static ip_addr_t dhcps_pool_end;
-static ip_addr_t dhcps_local_mask;
-static ip_addr_t dhcps_local_gateway;
-static ip_addr_t dhcps_network_id;
-static ip_addr_t dhcps_subnet_broadcast;
-static ip_addr_t dhcps_allocated_client_address;
-static int dhcps_addr_pool_set = 0;
-static ip_addr_t dhcps_addr_pool_start;
-static ip_addr_t dhcps_addr_pool_end;
-#if 1
-static ip_addr_t dhcps_owned_first_ip;
-static ip_addr_t dhcps_owned_last_ip;
-static uint8_t dhcps_num_of_available_ips;
-#endif
-static struct dhcp_msg *dhcp_message_repository;
-static int dhcp_message_total_options_lenth;
-
-/* allocated IP range */
-static struct table ip_table;
-static ip_addr_t client_request_ip;
-static uint8_t client_addr[6];
-
-static _mutex dhcps_ip_table_semaphore;
-
-static struct netif * dhcps_netif = NULL;
-/**
- * @brief latch the specific ip in the ip table.
- * @param d the specific index
- * @retval None.
- */
-#if (!IS_USE_FIXED_IP)
-static void mark_ip_in_table(uint8_t d)
-{
-#if (debug_dhcps)
- printf("\r\nmark ip %d\r\n",d);
-#endif
- rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
- if (0 < d && d <= 32) {
- ip_table.ip_range[0] = MARK_RANGE1_IP_BIT(ip_table, d);
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[0] = 0x%x\r\n",ip_table.ip_range[0]);
-#endif
- } else if (32 < d && d <= 64) {
- ip_table.ip_range[1] = MARK_RANGE2_IP_BIT(ip_table, (d - 32));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[1] = 0x%x\r\n",ip_table.ip_range[1]);
-#endif
- } else if (64 < d && d <= 96) {
- ip_table.ip_range[2] = MARK_RANGE3_IP_BIT(ip_table, (d - 64));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[2] = 0x%x\r\n",ip_table.ip_range[2]);
-#endif
- } else if (96 < d && d <= 128) {
- ip_table.ip_range[3] = MARK_RANGE4_IP_BIT(ip_table, (d - 96));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[3] = 0x%x\r\n",ip_table.ip_range[3]);
-#endif
- } else if(128 < d && d <= 160) {
- ip_table.ip_range[4] = MARK_RANGE5_IP_BIT(ip_table, d);
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[4] = 0x%x\r\n",ip_table.ip_range[4]);
-#endif
- } else if (160 < d && d <= 192) {
- ip_table.ip_range[5] = MARK_RANGE6_IP_BIT(ip_table, (d - 160));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[5] = 0x%x\r\n",ip_table.ip_range[5]);
-#endif
- } else if (192 < d && d <= 224) {
- ip_table.ip_range[6] = MARK_RANGE7_IP_BIT(ip_table, (d - 192));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[6] = 0x%x\r\n",ip_table.ip_range[6]);
-#endif
- } else if (224 < d) {
- ip_table.ip_range[7] = MARK_RANGE8_IP_BIT(ip_table, (d - 224));
-#if (debug_dhcps)
- printf("\r\n ip_table.ip_range[7] = 0x%x\r\n",ip_table.ip_range[7]);
-#endif
- } else {
- printf("\r\n Request ip over the range(1-128) \r\n");
- }
- rtw_mutex_put(&dhcps_ip_table_semaphore);
-
-}
-#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
-static void save_client_addr(ip_addr_t *client_ip, uint8_t *hwaddr)
-{
- uint8_t d = (uint8_t)ip4_addr4(client_ip);
-
- rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
- memcpy(ip_table.client_mac[d], hwaddr, 6);
-#if (debug_dhcps)
- printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
- ip4_addr1(client_ip), ip4_addr2(client_ip), ip4_addr3(client_ip), ip4_addr4(client_ip),
- hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
-#endif
- rtw_mutex_put(&dhcps_ip_table_semaphore);
-}
-
-static uint8_t check_client_request_ip(ip_addr_t *client_req_ip, uint8_t *hwaddr)
-{
- int ip_addr4 = 0, i;
-
-#if (debug_dhcps)
- printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
- ip4_addr1(client_req_ip), ip4_addr2(client_req_ip), ip4_addr3(client_req_ip), ip4_addr4(client_req_ip),
- hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
-#endif
-
- rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
- for(i=DHCP_POOL_START;i<=DHCP_POOL_END;i++)
- {
- //printf("client[%d] = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",i,ip_table.client_mac[i][0],ip_table.client_mac[i][0],ip_table.client_mac[i][1],ip_table.client_mac[i][2],ip_table.client_mac[i][3],ip_table.client_mac[i][4],ip_table.client_mac[i][5]);
- if(memcmp(ip_table.client_mac[i], hwaddr, 6) == 0){
- if((ip_table.ip_range[i/32]>>(i%32-1)) & 1){
- ip_addr4 = i;
- break;
- }
- }
- }
- rtw_mutex_put(&dhcps_ip_table_semaphore);
-
- if(i == DHCP_POOL_END+1)
- ip_addr4 = 0;
-
- return ip_addr4;
-}
-
-#if debug_dhcps
-static void dump_client_table()
-{
-#if 0
- int i;
- uint8_t *p = NULL;
- printf("\r\nip_range: %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x",
- ip_table.ip_range[0], ip_table.ip_range[1], ip_table.ip_range[2], ip_table.ip_range[3],
- ip_table.ip_range[4], ip_table.ip_range[5], ip_table.ip_range[6], ip_table.ip_range[7]);
- for(i=1; i<=DHCPS_MAX_CLIENT_NUM; i++)
- {
- p = ip_table.client_mac[i];
- printf("\r\nClient[%d]: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
- i, p[0], p[1], p[2], p[3], p[4], p[5]);
- }
- printf("\r\n");
-#endif
-}
-#endif
-#endif //CONFIG_DHCPS_KEPT_CLIENT_INFO
-#endif
-
-/**
- * @brief get one usable ip from the ip table of dhcp server.
- * @param: None
- * @retval the usable index which represent the ip4_addr(ip) of allocated ip addr.
- */
-#if (!IS_USE_FIXED_IP)
-static uint8_t search_next_ip(void)
-{
- uint8_t range_count, offset_count;
- uint8_t start, end;
- uint8_t max_count;
- if(dhcps_addr_pool_set){
- start = (uint8_t)ip4_addr4(&dhcps_addr_pool_start);
- end = (uint8_t)ip4_addr4(&dhcps_addr_pool_end);
- }else{
- start = 0;
- end = 255;
- }
- rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
- for (range_count = 0; range_count < (max_count = 8); range_count++) {
- for (offset_count = 0;offset_count < 32; offset_count++) {
- if ((((ip_table.ip_range[range_count] >> offset_count) & 0x01) == 0)
- &&(((range_count * 32) + (offset_count + 1)) >= start)
- &&(((range_count * 32) + (offset_count + 1)) <= end)) {
- rtw_mutex_put(&dhcps_ip_table_semaphore);
- return ((range_count * 32) + (offset_count + 1));
- }
- }
- }
- rtw_mutex_put(&dhcps_ip_table_semaphore);
- return 0;
-}
-#endif
-
-/**
- * @brief fill in the option field with message type of a dhcp message.
- * @param msg_option_base_addr: the addr be filled start.
- * message_type: the type code you want to fill in
- * @retval the start addr of the next dhcp option.
- */
-static uint8_t *add_msg_type(uint8_t *msg_option_base_addr, uint8_t message_type)
-{
- uint8_t *option_start;
- msg_option_base_addr[0] = DHCP_OPTION_CODE_MSG_TYPE;
- msg_option_base_addr[1] = DHCP_OPTION_LENGTH_ONE;
- msg_option_base_addr[2] = message_type;
- option_start = msg_option_base_addr + 3;
- if (DHCP_MESSAGE_TYPE_NAK == message_type)
- *option_start++ = DHCP_OPTION_CODE_END;
- return option_start;
-}
-
-
-static uint8_t *fill_one_option_content(uint8_t *option_base_addr,
- uint8_t option_code, uint8_t option_length, void *copy_info)
-{
- uint8_t *option_data_base_address;
- uint8_t *next_option_start_address = NULL;
- option_base_addr[0] = option_code;
- option_base_addr[1] = option_length;
- option_data_base_address = option_base_addr + 2;
- switch (option_length) {
- case DHCP_OPTION_LENGTH_FOUR:
- memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_FOUR);
- next_option_start_address = option_data_base_address + 4;
- break;
- case DHCP_OPTION_LENGTH_TWO:
- memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_TWO);
- next_option_start_address = option_data_base_address + 2;
- break;
- case DHCP_OPTION_LENGTH_ONE:
- memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_ONE);
- next_option_start_address = option_data_base_address + 1;
- break;
- }
-
- return next_option_start_address;
-}
-
-/**
- * @brief fill in the needed content of the dhcp offer message.
- * @param optptr the addr which the tail of dhcp magic field.
- * @retval the addr represent to add the end of option.
- */
-static void add_offer_options(uint8_t *option_start_address)
-{
- uint8_t *temp_option_addr;
- /* add DHCP options 1.
- The subnet mask option specifies the client's subnet mask */
- temp_option_addr = fill_one_option_content(option_start_address,
- DHCP_OPTION_CODE_SUBNET_MASK, DHCP_OPTION_LENGTH_FOUR,
- (void *)&dhcps_local_mask);
-
- /* add DHCP options 3 (i.e router(gateway)). The time server option
- specifies a list of RFC 868 [6] time servers available to the client. */
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_ROUTER, DHCP_OPTION_LENGTH_FOUR,
- (void *)&dhcps_local_address);
-
- /* add DHCP options 6 (i.e DNS).
- The option specifies a list of DNS servers available to the client. */
- //temp_option_addr = fill_one_option_content(temp_option_addr,
- // DHCP_OPTION_CODE_DNS_SERVER, DHCP_OPTION_LENGTH_FOUR,
- // (void *)&dhcps_local_address);
- /* add DHCP options 51.
- This option is used to request a lease time for the IP address. */
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_LEASE_TIME, DHCP_OPTION_LENGTH_FOUR,
- (void *)&dhcp_option_lease_time);
- /* add DHCP options 54.
- The identifier is the IP address of the selected server. */
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_SERVER_ID, DHCP_OPTION_LENGTH_FOUR,
- (void *)&dhcps_local_address);
- /* add DHCP options 28.
- This option specifies the broadcast address in use on client's subnet.*/
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_BROADCAST_ADDRESS, DHCP_OPTION_LENGTH_FOUR,
- (void *)&dhcps_subnet_broadcast);
- /* add DHCP options 26.
- This option specifies the Maximum transmission unit to use */
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_INTERFACE_MTU, DHCP_OPTION_LENGTH_TWO,
- (void *) &dhcp_option_interface_mtu);//dhcp_option_interface_mtu_576);
- /* add DHCP options 31.
- This option specifies whether or not the client should solicit routers */
- temp_option_addr = fill_one_option_content(temp_option_addr,
- DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY, DHCP_OPTION_LENGTH_ONE,
- NULL);
- *temp_option_addr++ = DHCP_OPTION_CODE_END;
-
-}
-
-
-/**
- * @brief fill in common content of a dhcp message.
- * @param m the pointer which point to the dhcp message store in.
- * @retval None.
- */
-static void dhcps_initialize_message(struct dhcp_msg *dhcp_message_repository)
-{
-
- dhcp_message_repository->op = DHCP_MESSAGE_OP_REPLY;
- dhcp_message_repository->htype = DHCP_MESSAGE_HTYPE;
- dhcp_message_repository->hlen = DHCP_MESSAGE_HLEN;
- dhcp_message_repository->hops = 0;
- memcpy((char *)dhcp_recorded_xid, (char *) dhcp_message_repository->xid,
- sizeof(dhcp_message_repository->xid));
- dhcp_message_repository->secs = 0;
- dhcp_message_repository->flags = htons(BOOTP_BROADCAST);
-
- memcpy((char *)dhcp_message_repository->yiaddr,
- (char *)&dhcps_allocated_client_address,
- sizeof(dhcp_message_repository->yiaddr));
-
- memset((char *)dhcp_message_repository->ciaddr, 0,
- sizeof(dhcp_message_repository->ciaddr));
- memset((char *)dhcp_message_repository->siaddr, 0,
- sizeof(dhcp_message_repository->siaddr));
- memset((char *)dhcp_message_repository->giaddr, 0,
- sizeof(dhcp_message_repository->giaddr));
- memset((char *)dhcp_message_repository->sname, 0,
- sizeof(dhcp_message_repository->sname));
- memset((char *)dhcp_message_repository->file, 0,
- sizeof(dhcp_message_repository->file));
- memset((char *)dhcp_message_repository->options, 0,
- dhcp_message_total_options_lenth);
- memcpy((char *)dhcp_message_repository->options, (char *)dhcp_magic_cookie,
- sizeof(dhcp_magic_cookie));
-}
-
-/**
- * @brief init and fill in the needed content of dhcp offer message.
- * @param packet_buffer packet buffer for UDP.
- * @retval None.
- */
-static void dhcps_send_offer(struct pbuf *packet_buffer)
-{
- uint8_t temp_ip = 0;
- dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
-#if (!IS_USE_FIXED_IP)
- temp_ip = check_client_request_ip(&client_request_ip, client_addr);
- /* create new client ip */
- if(temp_ip == 0)
- temp_ip = search_next_ip();
-#if (debug_dhcps)
- printf("\r\n temp_ip = %d",temp_ip);
-#endif
- if (temp_ip == 0) {
-#if 0
- memset(&ip_table, 0, sizeof(struct table));
- mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
- printf("\r\n reset ip table!!\r\n");
-#endif
- printf("\r\n No useable ip!!!!\r\n");
- }
- printf("\n\r[%d]DHCP assign ip = %d.%d.%d.%d\n", rtw_get_current_time(), ip4_addr1(&dhcps_network_id),ip4_addr2(&dhcps_network_id),ip4_addr3(&dhcps_network_id),temp_ip);
- IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
- ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), temp_ip);
-#endif
- dhcps_initialize_message(dhcp_message_repository);
- add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
- DHCP_MESSAGE_TYPE_OFFER));
- udp_sendto_if(dhcps_pcb, packet_buffer,
- &dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
-}
-
-/**
- * @brief init and fill in the needed content of dhcp nak message.
- * @param packet buffer packet buffer for UDP.
- * @retval None.
- */
-static void dhcps_send_nak(struct pbuf *packet_buffer)
-{
- dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
- dhcps_initialize_message(dhcp_message_repository);
- add_msg_type(&dhcp_message_repository->options[4], DHCP_MESSAGE_TYPE_NAK);
- udp_sendto_if(dhcps_pcb, packet_buffer,
- &dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
-}
-
-/**
- * @brief init and fill in the needed content of dhcp ack message.
- * @param packet buffer packet buffer for UDP.
- * @retval None.
- */
-static void dhcps_send_ack(struct pbuf *packet_buffer)
-{
- dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
- dhcps_initialize_message(dhcp_message_repository);
- add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
- DHCP_MESSAGE_TYPE_ACK));
- udp_sendto_if(dhcps_pcb, packet_buffer,
- &dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
-}
-
-/**
- * @brief according by the input message type to reflect the correspond state.
- * @param option_message_type the input server state
- * @retval the server state which already transfer to.
- */
-uint8_t dhcps_handle_state_machine_change(uint8_t option_message_type)
-{
- switch (option_message_type) {
- case DHCP_MESSAGE_TYPE_DECLINE:
- #if (debug_dhcps)
- printf("\r\nget message DHCP_MESSAGE_TYPE_DECLINE\n");
- #endif
- dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
- break;
- case DHCP_MESSAGE_TYPE_DISCOVER:
- #if (debug_dhcps)
- printf("\r\nget message DHCP_MESSAGE_TYPE_DISCOVER\n");
- #endif
- if (dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE) {
- dhcp_server_state_machine = DHCP_SERVER_STATE_OFFER;
- }
- break;
- case DHCP_MESSAGE_TYPE_REQUEST:
- #if (debug_dhcps)
- printf("\r\n[%d]get message DHCP_MESSAGE_TYPE_REQUEST\n", rtw_get_current_time());
- #endif
-#if (!IS_USE_FIXED_IP)
-#if (debug_dhcps)
- printf("\r\ndhcp_server_state_machine=%d", dhcp_server_state_machine);
- printf("\r\ndhcps_allocated_client_address=%d.%d.%d.%d",
- ip4_addr1(&dhcps_allocated_client_address),
- ip4_addr2(&dhcps_allocated_client_address),
- ip4_addr3(&dhcps_allocated_client_address),
- ip4_addr4(&dhcps_allocated_client_address));
- printf("\r\nclient_request_ip=%d.%d.%d.%d\n",
- ip4_addr1(&client_request_ip),
- ip4_addr2(&client_request_ip),
- ip4_addr3(&client_request_ip),
- ip4_addr4(&client_request_ip));
-#endif
- if (dhcp_server_state_machine == DHCP_SERVER_STATE_OFFER) {
- if (ip4_addr4(&dhcps_allocated_client_address) != 0) {
- if (memcmp((void *)&dhcps_allocated_client_address, (void *)&client_request_ip, 4) == 0) {
- dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
- } else {
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
- }
- } else {
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
- }
- } else if(dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE){
- uint8_t ip_addr4 = check_client_request_ip(&client_request_ip, client_addr);
- if(ip_addr4 > 0){
- IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
- ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), ip_addr4);
- dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
- }else{
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
- }
- } else {
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
- }
-#else
- if (!(dhcp_server_state_machine == DHCP_SERVER_STATE_ACK ||
- dhcp_server_state_machine == DHCP_SERVER_STATE_NAK)) {
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
- }
-#endif
- break;
- case DHCP_MESSAGE_TYPE_RELEASE:
- printf("get message DHCP_MESSAGE_TYPE_RELEASE\n");
- dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
- break;
- }
-
- return dhcp_server_state_machine;
-}
-/**
- * @brief parse the dhcp message option part.
- * @param optptr: the addr of the first option field.
- * len: the total length of all option fields.
- * @retval dhcp server state.
- */
-static uint8_t dhcps_handle_msg_options(uint8_t *option_start, int16_t total_option_length)
-{
-
- int16_t option_message_type = 0;
- uint8_t *option_end = option_start + total_option_length;
- //dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
-
- /* begin process the dhcp option info */
- while (option_start < option_end) {
- switch ((uint8_t)*option_start) {
- case DHCP_OPTION_CODE_MSG_TYPE:
- option_message_type = *(option_start + 2); // 2 => code(1)+lenth(1)
- break;
- case DHCP_OPTION_CODE_REQUEST_IP_ADDRESS :
-#if IS_USE_FIXED_IP
- if (memcmp((char *)&dhcps_allocated_client_address,
- (char *)option_start + 2, 4) == 0)
- dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
- else
- dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
-#else
- memcpy((char *)&client_request_ip, (char *)option_start + 2, 4);
-#endif
- break;
- }
- // calculate the options offset to get next option's base addr
- option_start += option_start[1] + 2; // optptr[1]: length value + (code(1)+ Len(1))
- }
- return dhcps_handle_state_machine_change(option_message_type);
-}
-
-/**
- * @brief get message from buffer then check whether it is dhcp related or not.
- * if yes , parse it more to undersatnd the client's request.
- * @param same as recv callback function definition
- * @retval if message is dhcp related then return dhcp server state,
- * otherwise return 0
- */
-static uint8_t dhcps_check_msg_and_handle_options(struct pbuf *packet_buffer)
-{
- int dhcp_message_option_offset;
- dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
- dhcp_message_option_offset = ((int)dhcp_message_repository->options
- - (int)packet_buffer->payload);
- dhcp_message_total_options_lenth = (packet_buffer->len
- - dhcp_message_option_offset);
- memcpy(client_addr, dhcp_message_repository->chaddr, 6);
- /* check the magic number,if correct parse the content of options */
- if (memcmp((char *)dhcp_message_repository->options,
- (char *)dhcp_magic_cookie, sizeof(dhcp_magic_cookie)) == 0) {
- return dhcps_handle_msg_options(&dhcp_message_repository->options[4],
- (dhcp_message_total_options_lenth - 4));
- }
-
- return 0;
-}
-
-
-/**
- * @brief handle imcoming dhcp message and response message to client
- * @param same as recv callback function definition
- * @retval None
- */
-static void dhcps_receive_udp_packet_handler(void *arg, struct udp_pcb *udp_pcb,
-struct pbuf *udp_packet_buffer, ip_addr_t *sender_addr, uint16_t sender_port)
-{
- int16_t total_length_of_packet_buffer;
- struct pbuf *merged_packet_buffer = NULL;
-
- dhcp_message_repository = (struct dhcp_msg *)udp_packet_buffer->payload;
- if (udp_packet_buffer == NULL) {
- printf("\n\r Error!!!! System doesn't allocate any buffer \n\r");
- return;
- }
- if (sender_port == DHCP_CLIENT_PORT) {
- total_length_of_packet_buffer = udp_packet_buffer->tot_len;
- if (udp_packet_buffer->next != NULL) {
- merged_packet_buffer = pbuf_coalesce(udp_packet_buffer,
- PBUF_TRANSPORT);
- if (merged_packet_buffer->tot_len !=
- total_length_of_packet_buffer) {
- pbuf_free(udp_packet_buffer);
- return;
- }
- }
- switch (dhcps_check_msg_and_handle_options(udp_packet_buffer)) {
- case DHCP_SERVER_STATE_OFFER:
- #if (debug_dhcps)
- printf("%s DHCP_SERVER_STATE_OFFER\n",__func__);
- #endif
- dhcps_send_offer(udp_packet_buffer);
- break;
- case DHCP_SERVER_STATE_ACK:
- #if (debug_dhcps)
- printf("%s DHCP_SERVER_STATE_ACK\n",__func__);
- #endif
- dhcps_send_ack(udp_packet_buffer);
-#if (!IS_USE_FIXED_IP)
- mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_allocated_client_address));
- #ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
- save_client_addr(&dhcps_allocated_client_address, client_addr);
- memset(&client_request_ip, 0, sizeof(client_request_ip));
- memset(&client_addr, 0, sizeof(client_addr));
- memset(&dhcps_allocated_client_address, 0, sizeof(dhcps_allocated_client_address));
- #if (debug_dhcps)
- dump_client_table();
- #endif
- #endif
-#endif
- dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
- break;
- case DHCP_SERVER_STATE_NAK:
- #if (debug_dhcps)
- printf("%s DHCP_SERVER_STATE_NAK\n",__func__);
- #endif
- dhcps_send_nak(udp_packet_buffer);
- dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
- break;
- case DHCP_OPTION_CODE_END:
- #if (debug_dhcps)
- printf("%s DHCP_OPTION_CODE_END\n",__func__);
- #endif
- break;
- }
- }
-
- /* free the UDP connection, so we can accept new clients */
- udp_disconnect(udp_pcb);
-
- /* Free the packet buffer */
- if (merged_packet_buffer != NULL)
- pbuf_free(merged_packet_buffer);
- else
- pbuf_free(udp_packet_buffer);
-}
-
-void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end)
-{
- //uint8_t *ip;
- if(addr_pool_set){
- dhcps_addr_pool_set = 1;
-
- memcpy(&dhcps_addr_pool_start, addr_pool_start,
- sizeof(ip_addr_t));
- //ip = &dhcps_addr_pool_start;
- //ip[3] = 100;
- memcpy(&dhcps_addr_pool_end, addr_pool_end,
- sizeof(ip_addr_t));
- //ip = &dhcps_addr_pool_end;
- //ip[3] = 200;
- }else{
- dhcps_addr_pool_set = 0;
- }
-}
-/**
- * @brief Initialize dhcp server.
- * @param None.
- * @retval None.
- * Note, for now,we assume the server latch ip 192.168.1.1 and support dynamic
- * or fixed IP allocation.
- */
-void dhcps_init(struct netif * pnetif)
-{
- uint8_t *ip;
-// printf("dhcps_init,wlan:%c\n\r",pnetif->name[1]);
-#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
- memset(&ip_table, 0, sizeof(struct table));
-// int i = 0;
-// for(i=0; i< DHCPS_MAX_CLIENT_NUM+2; i++)
-// memset(ip_table.client_mac[i], 0, 6);
-// dump_client_table();
-#endif
-
- dhcps_netif = pnetif;
-
- if (dhcps_pcb != NULL) {
- udp_remove(dhcps_pcb);
- dhcps_pcb = NULL;
- }
-
- dhcps_pcb = udp_new();
- if (dhcps_pcb == NULL) {
- printf("\n\r Error!!!upd_new error \n\r");
- return;
- }
- IP4_ADDR(&dhcps_send_broadcast_address, 255, 255, 255, 255);
- /* get net info from net interface */
-
- memcpy(&dhcps_local_address, &pnetif->ip_addr,
- sizeof(ip_addr_t));
- memcpy(&dhcps_local_mask, &pnetif->netmask,
- sizeof(ip_addr_t));
-
- memcpy(&dhcps_local_gateway, &pnetif->gw,
- sizeof(ip_addr_t));
-
- /* calculate the usable network ip range */
- dhcps_network_id.addr = ((pnetif->ip_addr.addr) &
- (pnetif->netmask.addr));
-
- dhcps_subnet_broadcast.addr = ((dhcps_network_id.addr |
- ~(pnetif->netmask.addr)));
-#if 1
- dhcps_owned_first_ip.addr = htonl((ntohl(dhcps_network_id.addr) + 1));
- dhcps_owned_last_ip.addr = htonl(ntohl(dhcps_subnet_broadcast.addr) - 1);
- dhcps_num_of_available_ips = ((ntohl(dhcps_owned_last_ip.addr)
- - ntohl(dhcps_owned_first_ip.addr)) + 1);
-#endif
-
-#if IS_USE_FIXED_IP
- IP4_ADDR(&dhcps_allocated_client_address, ip4_addr1(&dhcps_local_address)
- , ip4_addr2(&dhcps_local_address), ip4_addr3(&dhcps_local_address),
- (ip4_addr4(&dhcps_local_address)) + 1 );
-#else
- if (dhcps_ip_table_semaphore != NULL) {
- rtw_mutex_free(&dhcps_ip_table_semaphore);
- dhcps_ip_table_semaphore = NULL;
- }
- rtw_mutex_init(&dhcps_ip_table_semaphore);
-
- //dhcps_ip_table = (struct ip_table *)(pvPortMalloc(sizeof(struct ip_table)));
- memset(&ip_table, 0, sizeof(struct table));
- mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
- mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_gateway));
-#if 0
- for (i = 1; i < ip4_addr4(&dhcps_local_address); i++) {
- mark_ip_in_table(i);
- }
-#endif
-#endif
-
- memcpy(&dhcps_pool_start,&dhcps_local_address,sizeof(ip_addr_t));
- ip = (uint8_t *)&dhcps_pool_start;
- ip[3] = DHCP_POOL_START;
- memcpy(&dhcps_pool_end,&dhcps_local_address,sizeof(ip_addr_t));
- ip = (uint8_t *)&dhcps_pool_end;
- ip[3] = DHCP_POOL_END;
-
- dhcps_set_addr_pool(1,&dhcps_pool_start,&dhcps_pool_end);
-
- udp_bind(dhcps_pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
- udp_recv(dhcps_pcb, (udp_recv_fn)dhcps_receive_udp_packet_handler, NULL);
-}
-
-void dhcps_deinit(void)
-{
- if (dhcps_pcb != NULL) {
- udp_remove(dhcps_pcb);
- dhcps_pcb = NULL;
- }
- if (dhcps_ip_table_semaphore != NULL) {
- rtw_mutex_free(&dhcps_ip_table_semaphore);
- dhcps_ip_table_semaphore = NULL;
- }
-}
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,159 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-#ifndef __DHCPS_H__
-#define __DHCPS_H__
-
-#include "lwip/arch.h"
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-#include "lwip/stats.h"
-#include "lwip/sys.h"
-#include "lwip/ip_addr.h"
-#include <platform/platform_stdlib.h>
-
-
-#define CONFIG_DHCPS_KEPT_CLIENT_INFO
-
-#define DHCP_POOL_START 100
-#define DHCP_POOL_END 200
-
-#define DHCPS_MAX_CLIENT_NUM (DHCP_POOL_END-DHCP_POOL_START+1)
-
-#define IS_USE_FIXED_IP 0
-#define debug_dhcps 0
-
-/* dhcp server states */
-#define DHCP_SERVER_STATE_OFFER (1)
-#define DHCP_SERVER_STATE_DECLINE (2)
-#define DHCP_SERVER_STATE_ACK (3)
-#define DHCP_SERVER_STATE_NAK (4)
-#define DHCP_SERVER_STATE_IDLE (5)
-
-
-#define BOOTP_BROADCAST (0x8000)
-
-#define DHCP_MESSAGE_OP_REQUEST (1)
-#define DHCP_MESSAGE_OP_REPLY (2)
-
-#define DHCP_MESSAGE_HTYPE (1)
-#define DHCP_MESSAGE_HLEN (6)
-
-#define DHCP_SERVER_PORT (67)
-#define DHCP_CLIENT_PORT (68)
-
-#define DHCP_MESSAGE_TYPE_DISCOVER (1)
-#define DHCP_MESSAGE_TYPE_OFFER (2)
-#define DHCP_MESSAGE_TYPE_REQUEST (3)
-#define DHCP_MESSAGE_TYPE_DECLINE (4)
-#define DHCP_MESSAGE_TYPE_ACK (5)
-#define DHCP_MESSAGE_TYPE_NAK (6)
-#define DHCP_MESSAGE_TYPE_RELEASE (7)
-
-#define DHCP_OPTION_LENGTH_ONE (1)
-#define DHCP_OPTION_LENGTH_TWO (2)
-#define DHCP_OPTION_LENGTH_THREE (3)
-#define DHCP_OPTION_LENGTH_FOUR (4)
-
-#define DHCP_OPTION_CODE_SUBNET_MASK (1)
-#define DHCP_OPTION_CODE_ROUTER (3)
-#define DHCP_OPTION_CODE_DNS_SERVER (6)
-#define DHCP_OPTION_CODE_INTERFACE_MTU (26)
-#define DHCP_OPTION_CODE_BROADCAST_ADDRESS (28)
-#define DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY (31)
-#define DHCP_OPTION_CODE_REQUEST_IP_ADDRESS (50)
-#define DHCP_OPTION_CODE_LEASE_TIME (51)
-#define DHCP_OPTION_CODE_MSG_TYPE (53)
-#define DHCP_OPTION_CODE_SERVER_ID (54)
-#define DHCP_OPTION_CODE_REQ_LIST (55)
-#define DHCP_OPTION_CODE_END (255)
-
-#define IP_FREE_TO_USE (1)
-#define IP_ALREADY_IN_USE (0)
-
-#define HW_ADDRESS_LENGTH (6)
-
-/* Reference by RFC 2131 */
-struct dhcp_msg {
- uint8_t op; /* Message op code/message type. 1 = BOOTREQUEST, 2 = BOOTREPLY */
- uint8_t htype; /* Hardware address type */
- uint8_t hlen; /* Hardware address length */
- uint8_t hops; /* Client sets to zero, optionally used by relay agents
- when booting via a relay agent */
- uint8_t xid[4]; /* Transaction ID, a random number chosen by the client,
- used by the client and server to associate messages and
- responses between a client and a server */
- uint16_t secs; /* Filled in by client, seconds elapsed since client began address
- acquisition or renewal process.*/
- uint16_t flags; /* bit 0: Broadcast flag, bit 1~15:MBZ must 0*/
- uint8_t ciaddr[4]; /* Client IP address; only filled in if client is in BOUND,
- RENEW or REBINDING state and can respond to ARP requests. */
- uint8_t yiaddr[4]; /* 'your' (client) IP address */
- uint8_t siaddr[4]; /* IP address of next server to use in bootstrap;
- returned in DHCPOFFER, DHCPACK by server. */
- uint8_t giaddr[4]; /* Relay agent IP address, used in booting via a relay agent.*/
- uint8_t chaddr[16]; /* Client hardware address */
- uint8_t sname[64]; /* Optional server host name, null terminated string.*/
- uint8_t file[128]; /* Boot file name, null terminated string; "generic" name or
- null in DHCPDISCOVER, fully qualified directory-path name in DHCPOFFER.*/
- uint8_t options[312]; /* Optional parameters field. reference the RFC 2132 */
-};
-
-/* use this to check whether the message is dhcp related or not */
-static const uint8_t dhcp_magic_cookie[4] = {99, 130, 83, 99};
-static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x1c, 0x20}; //1 day
-//static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x0e, 0x10}; // one hour
-//static const uint8_t dhcp_option_interface_mtu_576[] = {0x02, 0x40};
-static const uint8_t dhcp_option_interface_mtu[] = {0x05, 0xDC};
-
-struct table {
- uint32_t ip_range[8];
-#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
- uint8_t client_mac[256][6];
-#endif
-};
-
-struct address_pool{
- uint32_t start;
- uint32_t end;
-};
-
-/* 01~32 */
-#define MARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) | (1 << ((ip) - 1)))
-/* 33~64 */
-#define MARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) | (1 << ((ip) - 1)))
-/* 65~96 */
-#define MARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) | (1 << ((ip) - 1)))
-/* 97~128 */
-#define MARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) | (1 << ((ip) - 1)))
-/* 129~160 */
-#define MARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) | (1 << ((ip) - 1)))
-/* 161~192 */
-#define MARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) | (1 << ((ip) - 1)))
-/* 193~224 */
-#define MARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) | (1 << ((ip) - 1)))
-/* 225~255 */
-#define MARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) | (1 << ((ip) - 1)))
-
-/* expose API */
-void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end);
-void dhcps_init(struct netif * pnetif);
-void dhcps_deinit(void);
-
-extern struct netif *netif_default;
-
-#endif /*__DHCPS_H__*/
-
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,48 +1,46 @@
/* RTX includes */
#include "osdep_service.h"
#include "tcm_heap.h"
-//#include <core_cmFunc.h>
-//#include <stdlib.h>//malloc(), free()
-//#include <string.h>//memcpy(), memcmp(), memset()
#include "platform_stdlib.h"
-//#include <rt_HAL_CM.h>
-//#include <RTX_CM_lib.h>
+
/********************* os depended utilities ********************/
#ifndef USE_MUTEX_FOR_SPINLOCK
#define USE_MUTEX_FOR_SPINLOCK 1
#endif
-#define USE_HEAP_INFO 0
-
-#define OS_TICK OS_TICK_FREQ
-#define OS_TICK_RATE_MS (1000/OS_TICK)
//-----------------------------------------------------------------------
// Private Variables
//-----------------------------------------------------------------------
static unsigned long CriticalNesting = 0;
+#if CONFIG_USE_TCM_HEAP
+void *tcm_heap_malloc(int size);
+#endif
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+extern int rtw_if_wifi_thread(char *name);
+#endif
//-----------------------------------------------------------------------
// Misc Function
//-----------------------------------------------------------------------
int osdep_print = 0;
#define _func_enter_ do{\
- if(osdep_print)\
- printf("enter %s\r\n", __FUNCTION__);\
- }while(0)
+ if(osdep_print)\
+ printf("enter %s\r\n", __FUNCTION__);\
+ }while(0)
#define _func_exit_ do{\
- if(osdep_print)\
- printf("exit %s\r\n", __FUNCTION__);\
- }while(0)
+ if(osdep_print)\
+ printf("exit %s\r\n", __FUNCTION__);\
+ }while(0)
void save_and_cli()
{
_func_enter_;
#if defined(__CC_ARM)
- rtw_enter_critical(NULL, NULL);
+ rtw_enter_critical(NULL, NULL);
#else
- __disable_irq();
+ __disable_irq();
#endif
_func_exit_;
}
@@ -51,9 +49,9 @@
{
_func_enter_;
#if defined(__CC_ARM)
- rtw_exit_critical(NULL, NULL);
+ rtw_exit_critical(NULL, NULL);
#else
- __enable_irq();
+ __enable_irq();
#endif
_func_exit_;
}
@@ -61,76 +59,66 @@
void cli()
{
_func_enter_;
- __disable_irq();
+ __disable_irq();
_func_exit_;
}
/* Not needed on 64bit architectures */
static unsigned int __div64_32(u64 *n, unsigned int base)
{
- u64 rem = *n;
- u64 b = base;
- u64 res, d = 1;
- unsigned int high = rem >> 32;
+ u64 rem = *n;
+ u64 b = base;
+ u64 res, d = 1;
+ unsigned int high = rem >> 32;
_func_enter_;
- /* Reduce the thing a bit first */
- res = 0;
- if (high >= base) {
- high /= base;
- res = (u64) high << 32;
- rem -= (u64) (high * base) << 32;
- }
+ /* Reduce the thing a bit first */
+ res = 0;
+ if (high >= base) {
+ high /= base;
+ res = (u64) high << 32;
+ rem -= (u64) (high * base) << 32;
+ }
- while ((u64)b > 0 && b < rem) {
- b = b+b;
- d = d+d;
- }
+ while ((u64)b > 0 && b < rem) {
+ b = b+b;
+ d = d+d;
+ }
- do {
- if (rem >= b) {
- rem -= b;
- res += d;
- }
- b >>= 1;
- d >>= 1;
- } while (d);
+ do {
+ if (rem >= b) {
+ rem -= b;
+ res += d;
+ }
+ b >>= 1;
+ d >>= 1;
+ } while (d);
_func_exit_;
- *n = res;
- return rem;
+ *n = res;
+ return rem;
}
/********************* os depended service ********************/
-#if USE_HEAP_INFO
-static uint32_t osFreeBytesRemaining=0x400;
-#endif
+
static void _rtx2_memset(void *pbuf, int c, u32 sz);
u8* _rtx2_malloc(u32 sz)
{
_func_enter_;
- void *p = NULL;
- p = (void *)malloc(sz);
- if(p != NULL){
-#if USE_HEAP_INFO
- osFreeBytesRemaining-=sz;
-#endif
- }
+ void *p = NULL;
+ p = (void *)malloc(sz);
_func_exit_;
- return p;
+ return p;
}
u8* _rtx2_zmalloc(u32 sz)
{
_func_enter_;
- u8 *pbuf = _rtx2_malloc(sz);
+ u8 *pbuf = _rtx2_malloc(sz);
- if (pbuf != NULL){
-#if USE_HEAP_INFO
- osFreeBytesRemaining-=sz;
-#endif
- _rtx2_memset(pbuf, 0, sz);
- }
+ if (pbuf != NULL){
+ _rtx2_memset(pbuf, 0, sz);
+ }
_func_exit_;
- return pbuf;
+ return pbuf;
}
static void (*ext_free)( void *p ) = NULL;
@@ -138,265 +126,279 @@
static uint32_t ext_lower = 0;
void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower )
{
- ext_free = free;
- ext_upper = upper;
- ext_lower = lower;
+ ext_free = free;
+ ext_upper = upper;
+ ext_lower = lower;
}
void _rtx2_mfree(u8 *pbuf, u32 sz)
{
_func_enter_;
- if( ((uint32_t)pbuf >= ext_lower) && ((uint32_t)pbuf < ext_upper) ){
- if(ext_free)
- ext_free(pbuf);
- }else{
- free(pbuf);
- }
-#if USE_HEAP_INFO
- osFreeBytesRemaining+=sz;
-#endif
+ if( ((uint32_t)pbuf >= ext_lower) && ((uint32_t)pbuf < ext_upper) ){
+ if(ext_free)
+ ext_free(pbuf);
+ }else{
+ free(pbuf);
+ }
}
static void _rtx2_memcpy(void* dst, void* src, u32 sz)
{
_func_enter_;
- memcpy(dst, src, sz);
+ memcpy(dst, src, sz);
_func_exit_;
}
static int _rtx2_memcmp(void *dst, void *src, u32 sz)
{
_func_enter_;
-//under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0
- if (!(memcmp(dst, src, sz)))
- return _SUCCESS;
+ //under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0
+ if (!(memcmp(dst, src, sz)))
+ return _SUCCESS;
_func_exit_;
- return _FAIL;
+ return _FAIL;
}
static void _rtx2_memset(void *pbuf, int c, u32 sz)
{
_func_enter_;
- memset(pbuf, c, sz);
+ memset(pbuf, c, sz);
_func_exit_;
}
static void _rtx2_init_sema(_sema *sem, int init_val)
{
_func_enter_;
- rtx_sema_t *p_sem = (rtx_sema_t *)_rtx2_zmalloc(sizeof(rtx_sema_t));
- if(p_sem == NULL){
- goto err_exit;
- }
- *sem = (_sema)p_sem;
- _rtx2_memset(&p_sem->data, 0, sizeof(p_sem->data));
- p_sem->attr.cb_mem = &p_sem->data;
- p_sem->attr.cb_size = sizeof(p_sem->data);
- p_sem->id = osSemaphoreNew(osRtxSemaphoreTokenLimit, (uint32_t)init_val, &p_sem->attr);
- if (p_sem->id == NULL){
- goto err_exit;
- }
+ rtx_sema_t *p_sem = (rtx_sema_t *)_rtx2_zmalloc(sizeof(rtx_sema_t));
+ if(p_sem == NULL){
+ goto err_exit;
+ }
+ *sem = (_sema)p_sem;
+ _rtx2_memset(&p_sem->data, 0, sizeof(p_sem->data));
+ p_sem->attr.cb_mem = &p_sem->data;
+ p_sem->attr.cb_size = sizeof(p_sem->data);
+ p_sem->id = osSemaphoreNew(osRtxSemaphoreTokenLimit, (uint32_t)init_val, &p_sem->attr);
+ if (p_sem->id == NULL){
+ goto err_exit;
+ }
_func_exit_;
- return;
+ return;
err_exit:
- DBG_ERR("error");
- if(p_sem)
- _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t));
- *sem = NULL;
- return;
+ DBG_ERR("error");
+ if(p_sem)
+ _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t));
+ *sem = NULL;
+ return;
}
static void _rtx2_free_sema(_sema *sema)
{
_func_enter_;
- if(*sema){
- rtx_sema_t *p_sem = (rtx_sema_t *)(*sema);
- osSemaphoreDelete(p_sem->id);
- if(p_sem)
- _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t));
- *sema = NULL;
- }else
- DBG_ERR("NULL pointer get");
+ if(*sema){
+ rtx_sema_t *p_sem = (rtx_sema_t *)(*sema);
+ osSemaphoreDelete(p_sem->id);
+ if(p_sem)
+ _rtx2_mfree((u8 *)p_sem, sizeof(rtx_sema_t));
+ *sema = NULL;
+ } else {
+ DBG_ERR("NULL pointer get");
+ }
_func_exit_;
}
static void _rtx2_up_sema(_sema *sema)
{
- if(*sema){
- rtx_sema_t *p_sem = (rtx_sema_t *)(*sema);
- osStatus_t status = osSemaphoreRelease(p_sem->id);
- if ( status != osOK){
- DBG_ERR("error %d", status);
- }
- }else
- DBG_ERR("NULL pointer get");
+_func_enter_;
+ if(*sema){
+ rtx_sema_t *p_sem = (rtx_sema_t *)(*sema);
+ osStatus_t status = osSemaphoreRelease(p_sem->id);
+ if (status != osOK){
+ DBG_ERR("error %d", status);
+ }
+ } else {
+ DBG_ERR("NULL pointer get");
+ }
_func_exit_;
}
static void _rtx2_up_sema_from_isr(_sema *sema)
{
_func_enter_;
- if(*sema){
- rtx_sema_t *p_sem = (rtx_sema_t *)*sema;
- osStatus_t status = osSemaphoreRelease(p_sem->id);
- if (status != osOK){
- DBG_ERR("error %d", status);
- }
- }else
- DBG_ERR("NULL pointer get");
+ if(*sema){
+ rtx_sema_t *p_sem = (rtx_sema_t *)*sema;
+ osStatus_t status = osSemaphoreRelease(p_sem->id);
+ if (status != osOK){
+ DBG_ERR("error %d", status);
+ }
+ } else {
+ DBG_ERR("NULL pointer get");
+ }
_func_exit_;
}
static u32 _rtx2_down_sema(_sema *sema, u32 timeout_ms)
{
- if(*sema){
- rtx_sema_t *p_sem = (rtx_sema_t *)*sema;
- if(timeout_ms == RTW_MAX_DELAY) {
- timeout_ms = osWaitForever;
- } else {
- timeout_ms = rtw_ms_to_systime(timeout_ms);
- }
- osStatus_t status = osSemaphoreAcquire(p_sem->id, timeout_ms);
- if (status == osOK){
- return _TRUE;
- };
- }
- return _FALSE;
+ if(*sema){
+ rtx_sema_t *p_sem = (rtx_sema_t *)*sema;
+ if(timeout_ms == RTW_MAX_DELAY) {
+ timeout_ms = osWaitForever;
+ } else {
+ timeout_ms = rtw_ms_to_systime(timeout_ms);
+ }
+ osStatus_t status = osSemaphoreAcquire(p_sem->id, timeout_ms);
+ if (status == osOK){
+ return _TRUE;
+ }
+ }
+ return _FALSE;
}
static void _rtx2_mutex_init(_mutex *mutex)
{
_func_enter_;
- rtx_mutex_t *p_mut = (rtx_mutex_t *)_rtx2_zmalloc(sizeof(rtx_mutex_t));
- if(p_mut == NULL)
- goto err_exit;
- memset(&p_mut->data, 0, sizeof(p_mut->data));
- p_mut->attr.cb_mem = &p_mut->data;
- p_mut->attr.cb_size = sizeof(p_mut->data);
- p_mut->id = osMutexNew(&p_mut->attr);
- if (p_mut->id == NULL)
- goto err_exit;
- *mutex = (_mutex)p_mut;
+ rtx_mutex_t *p_mut = (rtx_mutex_t *)_rtx2_zmalloc(sizeof(rtx_mutex_t));
+ if(p_mut == NULL)
+ goto err_exit;
+ memset(&p_mut->data, 0, sizeof(p_mut->data));
+ p_mut->attr.cb_mem = &p_mut->data;
+ p_mut->attr.cb_size = sizeof(p_mut->data);
+ p_mut->id = osMutexNew(&p_mut->attr);
+ if (p_mut->id == NULL)
+ goto err_exit;
+ *mutex = (_mutex)p_mut;
_func_exit_;
- return;
+ return;
err_exit:
- DBG_ERR("error");
- if(p_mut)
- _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t));
- *mutex = NULL;
- return;
+ DBG_ERR("error");
+ if(p_mut)
+ _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t));
+ *mutex = NULL;
+ return;
}
static void _rtx2_mutex_free(_mutex *pmutex)
{
_func_enter_;
- if(*pmutex){
- rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
- osMutexDelete(p_mut->id);
- if(p_mut)
- _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t));
- }
+ if(*pmutex){
+ rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
+ osMutexDelete(p_mut->id);
+ if(p_mut)
+ _rtx2_mfree((u8 *)p_mut, sizeof(rtx_mutex_t));
+ }
_func_exit_;
}
static void _rtx2_mutex_get(_mutex *pmutex)
{
_func_enter_;
- if(*pmutex){
- rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
- if (osMutexAcquire(p_mut->id, 60 * 1000 / OS_TICK_RATE_MS) != osOK)
- DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, p_mut);
- }
+ if(*pmutex){
+ rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
+ if (osMutexAcquire(p_mut->id, 60 * 1000 / OS_TICK_RATE_MS) != osOK)
+ DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, p_mut);
+ }
_func_exit_;
-}
+}
static int _rtx2_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms)
{
_func_enter_;
- if(*pmutex){
- rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
- if(timeout_ms == RTW_MAX_DELAY) {
- timeout_ms = osWaitForever;
- } else {
- timeout_ms = rtw_ms_to_systime(timeout_ms);
- }
- if(osMutexAcquire(p_mut->id, timeout_ms) == osOK){
- return _SUCCESS;
- }
- }
+ if(*pmutex){
+ rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
+ if(timeout_ms == RTW_MAX_DELAY) {
+ timeout_ms = osWaitForever;
+ } else {
+ timeout_ms = rtw_ms_to_systime(timeout_ms);
+ }
+ if(osMutexAcquire(p_mut->id, timeout_ms) == osOK){
+ return _SUCCESS;
+ }
+ }
_func_exit_;
- DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, pmutex);
- return _FAIL;
+ DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, pmutex);
+ return _FAIL;
}
static void _rtx2_mutex_put(_mutex *pmutex)
{
_func_enter_;
- if(*pmutex){
- rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
- if (osMutexRelease(p_mut->id) != osOK)
- DBG_ERR("\r\ninternal counter of mutex is 0 or calling task is not the owner of the mutex");
- }
+ if(*pmutex){
+ rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex);
+ if (osMutexRelease(p_mut->id) != osOK)
+ DBG_ERR("\r\ninternal counter of mutex is 0 or calling task is not the owner of the mutex");
+ }
_func_exit_;
}
static void _rtx2_enter_critical(_lock *plock, _irqL *pirqL)
{
_func_enter_;
- CriticalNesting++;
- if(CriticalNesting == 1){
- osKernelLock();//tsk_lock & tsk_unlock should not be called nested
- }
+ CriticalNesting++;
+ if(CriticalNesting == 1){
+ osKernelLock();//tsk_lock & tsk_unlock should not be called nested
+ }
_func_exit_;
}
void mbed_die(void){
- DBG_ERR(" %p die here", osThreadGetId());
- __disable_irq();
- while(1);
+ DBG_ERR(" %p die here", osThreadGetId());
+ __disable_irq();
+ while(1);
}
static void _rtx2_exit_critical(_lock *plock, _irqL *pirqL)
{
_func_enter_;
- if(CriticalNesting == 0){
- DBG_ERR("die here");
- HALT();
- }
- CriticalNesting--;
- if(CriticalNesting == 0){
- osKernelUnlock();
- }
+ if(CriticalNesting == 0){
+ DBG_ERR("die here");
+ HALT();
+ }
+ CriticalNesting--;
+ if(CriticalNesting == 0){
+ osKernelUnlock();
+ }
_func_exit_;
}
static void _rtx2_enter_critical_from_isr(_lock *plock, _irqL *pirqL)
{
_func_enter_;
- __disable_irq();
+ __disable_irq();
_func_exit_;
}
static void _rtx2_exit_critical_from_isr(_lock *plock, _irqL *pirqL)
{
_func_enter_;
- __enable_irq();
+ __enable_irq();
_func_exit_;
}
static int _rtx2_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
_func_enter_;
- while(_rtx2_mutex_get_timeout(pmutex, 60 * 1000) != _SUCCESS)
- DBG_ERR("\n\r[%p] %s(%p) failed, retry\n", osThreadGetId(), __FUNCTION__, pmutex);
+ while(_rtx2_mutex_get_timeout(pmutex, 60 * 1000) != _SUCCESS)
+ DBG_ERR("\n\r[%p] %s(%p) failed, retry\n", osThreadGetId(), __FUNCTION__, pmutex);
_func_exit_;
- return _SUCCESS;
+ return _SUCCESS;
}
static void _rtx2_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
_func_enter_;
- _rtx2_mutex_put(pmutex);
+ _rtx2_mutex_put(pmutex);
+_func_exit_;
+}
+
+static void _rtx2_cpu_lock(void)
+{
+_func_enter_;
+ printf(" Not yet ready. Should not come over here!\r\n");
+_func_exit_;
+}
+static void _rtx2_cpu_unlock(void)
+{
+_func_enter_;
+ printf(" Not yet ready. Should not come over here!\r\n");
_func_exit_;
}
@@ -404,7 +406,7 @@
{
_func_enter_;
#if USE_MUTEX_FOR_SPINLOCK
- _rtx2_mutex_init(plock);
+ _rtx2_mutex_init(plock);
#endif
_func_exit_;
}
@@ -413,9 +415,9 @@
{
_func_enter_;
#if USE_MUTEX_FOR_SPINLOCK
- if(plock != NULL){
- _rtx2_mutex_free(plock);
- }
+ if(plock != NULL){
+ _rtx2_mutex_free(plock);
+ }
#endif
_func_exit_;
}
@@ -424,7 +426,7 @@
{
_func_enter_;
#if USE_MUTEX_FOR_SPINLOCK
- _rtx2_mutex_get(plock);
+ _rtx2_mutex_get(plock);
#endif
_func_exit_;
}
@@ -433,7 +435,7 @@
{
_func_enter_;
#if USE_MUTEX_FOR_SPINLOCK
- _rtx2_mutex_put(plock);
+ _rtx2_mutex_put(plock);
#endif
_func_exit_;
}
@@ -441,9 +443,9 @@
static void _rtx2_spinlock_irqsave(_lock *plock, _irqL *irqL)
{
_func_enter_;
- _rtx2_enter_critical(plock, irqL);
+ _rtx2_enter_critical(plock, irqL);
#if USE_MUTEX_FOR_SPINLOCK
- _rtx2_spinlock(plock);
+ _rtx2_spinlock(plock);
#endif
_func_exit_;
}
@@ -452,129 +454,130 @@
{
_func_enter_;
#if USE_MUTEX_FOR_SPINLOCK
- _rtx2_spinunlock(plock);
+ _rtx2_spinunlock(plock);
#endif
- _rtx2_exit_critical(plock, irqL);
+ _rtx2_exit_critical(plock, irqL);
_func_exit_;
}
static int _rtx2_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages )
{
_func_enter_;
- rtx_mbox_t *mbox = (rtx_mbox_t *)_rtx2_zmalloc(sizeof(rtx_mbox_t));
- if (mbox == NULL ){
- goto err_exit;
- }
- mbox->queue_mem = _rtx2_zmalloc(number_of_messages * (message_size + sizeof(os_message_t)));
- if(mbox->queue_mem == NULL)
- goto err_exit;
- mbox->attr.mq_mem = mbox->queue_mem;
- mbox->attr.mq_size = number_of_messages * (message_size + sizeof(os_message_t));
- mbox->attr.cb_mem = &mbox->data;
- mbox->attr.cb_size = sizeof(mbox->data);
- *queue = (_xqueue)mbox;
- mbox->id = osMessageQueueNew(number_of_messages, message_size, &mbox->attr);
- if(mbox->id == NULL)
- goto err_exit;
+ rtx_mbox_t *mbox = (rtx_mbox_t *)_rtx2_zmalloc(sizeof(rtx_mbox_t));
+ if (mbox == NULL ){
+ goto err_exit;
+ }
+ mbox->queue_mem = _rtx2_zmalloc(number_of_messages * (message_size + sizeof(os_message_t)));
+ if(mbox->queue_mem == NULL)
+ goto err_exit;
+ mbox->attr.mq_mem = mbox->queue_mem;
+ mbox->attr.mq_size = number_of_messages * (message_size + sizeof(os_message_t));
+ mbox->attr.cb_mem = &mbox->data;
+ mbox->attr.cb_size = sizeof(mbox->data);
+ *queue = (_xqueue)mbox;
+ mbox->id = osMessageQueueNew(number_of_messages, message_size, &mbox->attr);
+ if(mbox->id == NULL)
+ goto err_exit;
_func_exit_;
- return _SUCCESS;
+ return _SUCCESS;
err_exit:
- DBG_ERR("%s error\r\n", __FUNCTION__);
- if(mbox){
- if(mbox->queue_mem)
- _rtx2_mfree(mbox->queue_mem, number_of_messages * (message_size + sizeof(os_message_t)));
- _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t));
- *queue = NULL;
- }
- return _FAIL;
+ DBG_ERR("%s error\r\n", __FUNCTION__);
+ if(mbox){
+ if(mbox->queue_mem)
+ _rtx2_mfree(mbox->queue_mem, number_of_messages * (message_size + sizeof(os_message_t)));
+ _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t));
+ *queue = NULL;
+ }
+ return _FAIL;
}
static int _rtx2_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms )
{
_func_enter_;
- rtx_mbox_t *mbox;
- if(timeout_ms == RTW_MAX_DELAY) {
- timeout_ms = osWaitForever;
- } else {
- timeout_ms = rtw_ms_to_systime(timeout_ms);
- }
-
- if (*queue != NULL){
- mbox = (rtx_mbox_t *)(*queue);
- if(osMessageQueuePut(mbox->id, message, NULL, timeout_ms) != osOK ){
- DBG_ERR("%s error\n", __FUNCTION__);
- return _FAIL;
- }
- }
+ rtx_mbox_t *mbox;
+ if(timeout_ms == RTW_MAX_DELAY) {
+ timeout_ms = osWaitForever;
+ } else {
+ timeout_ms = rtw_ms_to_systime(timeout_ms);
+ }
+
+ if (*queue != NULL){
+ mbox = (rtx_mbox_t *)(*queue);
+ if(osMessageQueuePut(mbox->id, message, 0, timeout_ms) != osOK ){
+ DBG_ERR("%s error\n", __FUNCTION__);
+ return _FAIL;
+ }
+ }
_func_exit_;
- return _SUCCESS;
+ return _SUCCESS;
}
static int _rtx2_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms )
{
_func_enter_;
- if(timeout_ms == RTW_WAIT_FOREVER) {
- timeout_ms = osWaitForever;
- } else {
- timeout_ms = rtw_ms_to_systime(timeout_ms);
- }
- if (*queue != NULL){
- rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue);
- osStatus_t res = osMessageQueueGet(mbox->id, message, NULL, timeout_ms);
- if (res == osOK) {
+ if(timeout_ms == RTW_WAIT_FOREVER) {
+ timeout_ms = osWaitForever;
+ } else {
+ timeout_ms = rtw_ms_to_systime(timeout_ms);
+ }
+ if (*queue != NULL){
+ rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue);
+ osStatus_t res = osMessageQueueGet(mbox->id, message, NULL, timeout_ms);
+ if (res == osOK) {
_func_exit_;
- return _SUCCESS;
- }
- }
+ return _SUCCESS;
+ }
+ }
- DBG_ERR("[%p] %s error", osThreadGetId(), __FUNCTION__);
- return _FAIL;
+ DBG_ERR("[%p] %s error", osThreadGetId(), __FUNCTION__);
+_func_exit_;
+ return _FAIL;
}
static int _rtx2_deinit_xqueue( _xqueue* queue )
{
_func_enter_;
- if(*queue != NULL){
- rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue);
- if(mbox->queue_mem)
- _rtx2_mfree(mbox->queue_mem, mbox->attr.mq_size);
- _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t));
- *queue = NULL;
- }
+ if(*queue != NULL){
+ rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue);
+ if(mbox->queue_mem)
+ _rtx2_mfree(mbox->queue_mem, mbox->attr.mq_size);
+ _rtx2_mfree((u8 *)mbox, sizeof(rtx_mbox_t));
+ *queue = NULL;
+ }
_func_exit_;
return 0;
}
static u32 _rtx2_get_current_time(void)
{
- return osKernelGetSysTimerCount();
+ return osKernelGetSysTimerCount();
}
static u32 _rtx2_systime_to_ms(u32 systime)
{
- return systime * OS_TICK_RATE_MS;
+ return systime * OS_TICK_RATE_MS;
}
static u32 _rtx2_systime_to_sec(u32 systime)
{
- return systime / OS_TICK;
+ return systime / OS_TICK;
}
static u32 _rtx2_ms_to_systime(u32 ms)
{
- return ms / OS_TICK_RATE_MS;
+ return ms / OS_TICK_RATE_MS;
}
static u32 _rtx2_sec_to_systime(u32 sec)
{
- return sec * OS_TICK;
+ return sec * OS_TICK;
}
static void _rtx2_msleep_os(int ms)
{
_func_enter_;
- osDelay(_rtx2_ms_to_systime(ms));
+ osDelay(_rtx2_ms_to_systime(ms));
_func_exit_;
}
@@ -582,13 +585,13 @@
{
_func_enter_;
#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL)
- // FreeRTOS does not provide us level delay. Use busy wait
- WLAN_BSP_UsLoop(us);
+ // FreeRTOS does not provide us level delay. Use busy wait
+ WLAN_BSP_UsLoop(us);
#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
- //DBG_ERR("%s: Please Implement micro-second delay\n", __FUNCTION__);
- HalDelayUs(us);
+ //DBG_ERR("%s: Please Implement micro-second delay\n", __FUNCTION__);
+ HalDelayUs(us);
#else
-// #error "Please implement hardware dependent micro second level sleep here"
+ // #error "Please implement hardware dependent micro second level sleep here"
#endif
_func_exit_;
}
@@ -596,7 +599,7 @@
static void _rtx2_mdelay_os(int ms)
{
_func_enter_;
- osDelay(_rtx2_ms_to_systime(ms));
+ osDelay(_rtx2_ms_to_systime(ms));
_func_exit_;
}
@@ -604,13 +607,13 @@
{
_func_enter_;
#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL)
- // FreeRTOS does not provide us level delay. Use busy wait
- WLAN_BSP_UsLoop(us);
+ // FreeRTOS does not provide us level delay. Use busy wait
+ WLAN_BSP_UsLoop(us);
#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
- //RtlUdelayOS(us);
- HalDelayUs(us);
+ //RtlUdelayOS(us);
+ HalDelayUs(us);
#else
-// #error "Please implement hardware dependent micro second level sleep here"
+ // #error "Please implement hardware dependent micro second level sleep here"
#endif
_func_exit_;
}
@@ -618,256 +621,258 @@
static void _rtx2_yield_os(void)
{
_func_enter_;
- osThreadYield();
+ osThreadYield();
_func_exit_;
}
static void _rtx2_ATOMIC_SET(ATOMIC_T *v, int i)
{
- atomic_set(v,i);
+ atomic_set(v,i);
}
static int _rtx2_ATOMIC_READ(ATOMIC_T *v)
{
- return atomic_read(v);
+ return atomic_read(v);
}
static void _rtx2_ATOMIC_ADD(ATOMIC_T *v, int i)
{
- save_and_cli();
- v->counter += i;
- restore_flags();
+ save_and_cli();
+ v->counter += i;
+ restore_flags();
}
static void _rtx2_ATOMIC_SUB(ATOMIC_T *v, int i)
{
- save_and_cli();
- v->counter -= i;
- restore_flags();
+ save_and_cli();
+ v->counter -= i;
+ restore_flags();
}
static void _rtx2_ATOMIC_INC(ATOMIC_T *v)
{
- save_and_cli();
- v->counter++;
- restore_flags();
+ save_and_cli();
+ v->counter++;
+ restore_flags();
}
static void _rtx2_ATOMIC_DEC(ATOMIC_T *v)
{
- save_and_cli();
- v->counter--;
- restore_flags();
+ save_and_cli();
+ v->counter--;
+ restore_flags();
}
static int _rtx2_ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)
{
- int temp;
+ int temp;
- save_and_cli();
- temp = v->counter;
- temp += i;
- v->counter = temp;
- restore_flags();
+ save_and_cli();
+ temp = v->counter;
+ temp += i;
+ v->counter = temp;
+ restore_flags();
- return temp;
+ return temp;
}
static int _rtx2_ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)
{
- int temp;
+ int temp;
- save_and_cli();
- temp = v->counter;
- temp -= i;
- v->counter = temp;
- restore_flags();
+ save_and_cli();
+ temp = v->counter;
+ temp -= i;
+ v->counter = temp;
+ restore_flags();
- return temp;
+ return temp;
}
static int _rtx2_ATOMIC_INC_RETURN(ATOMIC_T *v)
{
- return _rtx2_ATOMIC_ADD_RETURN(v, 1);
+ return _rtx2_ATOMIC_ADD_RETURN(v, 1);
}
static int _rtx2_ATOMIC_DEC_RETURN(ATOMIC_T *v)
{
- return _rtx2_ATOMIC_SUB_RETURN(v, 1);
+ return _rtx2_ATOMIC_SUB_RETURN(v, 1);
}
static u64 _rtx2_modular64(u64 n, u64 base)
{
- unsigned int __base = (base);
- unsigned int __rem;
+ unsigned int __base = (base);
+ unsigned int __rem;
_func_enter_;
- if (((n) >> 32) == 0) {
- __rem = (unsigned int)(n) % __base;
- (n) = (unsigned int)(n) / __base;
- }
- else
- __rem = __div64_32(&(n), __base);
+ if (((n) >> 32) == 0) {
+ __rem = (unsigned int)(n) % __base;
+ (n) = (unsigned int)(n) / __base;
+ } else {
+ __rem = __div64_32(&(n), __base);
+ }
_func_exit_;
- return __rem;
+ return __rem;
}
/* Refer to ecos bsd tcpip codes */
static int _rtx2_arc4random(void)
{
_func_enter_;
- u32 res = _rtx2_get_current_time();
- static unsigned long seed = 0xDEADB00B;
- seed = ((seed & 0x007F00FF) << 7) ^
- ((seed & 0x0F80FF00) >> 8) ^ // be sure to stir those low bits
- (res << 13) ^ (res >> 9); // using the clock too!
+ u32 res = _rtx2_get_current_time();
+ static unsigned long seed = 0xDEADB00B;
+ seed = ((seed & 0x007F00FF) << 7) ^
+ ((seed & 0x0F80FF00) >> 8) ^ // be sure to stir those low bits
+ (res << 13) ^ (res >> 9); // using the clock too!
_func_exit_;
- return (int)seed;
+ return (int)seed;
}
static int _rtx2_get_random_bytes(void *buf, u32 len)
{
-#if 1 //becuase of 4-byte align, we use the follow code style.
- unsigned int ranbuf;
- unsigned int *lp;
- int i, count;
- count = len / sizeof(unsigned int);
- lp = (unsigned int *) buf;
+ unsigned int ranbuf;
+ unsigned int *lp;
+ int i, count;
+ count = len / sizeof(unsigned int);
+ lp = (unsigned int *) buf;
_func_enter_;
- for(i = 0; i < count; i ++) {
- lp[i] = _rtx2_arc4random();
- len -= sizeof(unsigned int);
- }
+ for(i = 0; i < count; i ++) {
+ lp[i] = _rtx2_arc4random();
+ len -= sizeof(unsigned int);
+ }
- if(len > 0) {
- ranbuf = _rtx2_arc4random();
- _rtx2_memcpy(&lp[i], &ranbuf, len);
- }
+ if(len > 0) {
+ ranbuf = _rtx2_arc4random();
+ _rtx2_memcpy(&lp[i], &ranbuf, len);
+ }
_func_exit_;
- return 0;
-#else
- unsigned long ranbuf, *lp;
- lp = (unsigned long *)buf;
- while (len > 0) {
- ranbuf = _rtx2_arc4random();
- *lp++ = ranbuf; //this op need the pointer is 4Byte-align!
- len -= sizeof(ranbuf);
- }
- return 0;
-#endif
+ return 0;
}
static u32 _rtx2_GetFreeHeapSize(void)
{
-#if USE_HEAP_INFO
- return osFreeBytesRemaining;
-#else
- return 0;
-#endif
+ //TODO
+ return 0;
}
+/* Convert from wlan priority number to CMSIS type osPriority */
+static osPriority_t make_cmsis_priority (u32 fpriority)
+{
+ osPriority_t priority = (osPriority_t)fpriority;
+ priority += osPriorityHigh;
+ return priority;
+}
-#if CONFIG_USE_TCM_HEAP
-void *tcm_heap_malloc(int size);
-#endif
static int _rtx2_create_task(struct task_struct *ptask, const char *name,
u32 stack_size, u32 priority, thread_func_t func, void *thctx)
{
_func_enter_;
- rtx_thread_data_t *thread_hdl = NULL;
- u32 stacksize = stack_size * 4; //sizeof(DWORD)
- if(!func)
- goto err_exit;
- thread_hdl = (rtx_thread_data_t *)_rtx2_zmalloc(sizeof(rtx_thread_data_t));
- if(thread_hdl == NULL)
- goto err_exit;
- if(priority > osPriorityRealtime){
- DBG_ERR("[%s]priority is higher than osPriorityRealtime", name);
- priority = osPriorityRealtime;
- }
- thread_hdl->attr.name = name;
- thread_hdl->attr.priority = (osPriority_t)priority;
- thread_hdl->attr.cb_size = sizeof(thread_hdl->data);
- thread_hdl->attr.cb_mem = &thread_hdl->data;
- thread_hdl->attr.stack_size = stacksize;
- thread_hdl->attr.stack_mem = (void *)_rtx2_malloc(stacksize);
- if (thread_hdl->attr.stack_mem == NULL)
- goto err_exit;
+ rtx_thread_data_t *thread_hdl = NULL;
+ u32 stacksize = stack_size * 4; //sizeof(DWORD)
+ u8 *(*_customized_malloc)( u32 size ) = _rtx2_malloc;
+ u8 *(*_customized_zmalloc)( u32 size ) = _rtx2_zmalloc;
+ if(!func)
+ goto err_exit;
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+ if(rtw_if_wifi_thread((char *)name) == 0){
+ priority = make_cmsis_priority(priority);
+ _customized_malloc = _rtw_vmalloc;
+ _customized_zmalloc = _rtw_zvmalloc;
+ }
+#endif
+ thread_hdl = (rtx_thread_data_t *)_customized_zmalloc(sizeof(rtx_thread_data_t));
+ if(thread_hdl == NULL)
+ goto err_exit;
+ if(priority > osPriorityRealtime){
+ DBG_ERR("[%s]priority is higher than osPriorityRealtime", name);
+ priority = osPriorityRealtime;
+ }
+ thread_hdl->attr.name = name;
+ thread_hdl->attr.priority = (osPriority_t)priority;
+ thread_hdl->attr.cb_size = sizeof(thread_hdl->data);
+ thread_hdl->attr.cb_mem = &thread_hdl->data;
+ thread_hdl->attr.stack_size = stacksize;
+ thread_hdl->attr.stack_mem = (void *)_customized_malloc(stacksize);
+ if (thread_hdl->attr.stack_mem == NULL) {
+ DBG_ERR("[%s] malloc failed", name);
+ goto err_exit;
+ }
- ptask->task = (_thread_hdl_)thread_hdl;
- ptask->task_name = name;
- ptask->blocked = 0;
- ptask->callback_running = 0;
+ ptask->task = (_thread_hdl_)thread_hdl;
+ ptask->task_name = name;
+ ptask->blocked = 0;
+ ptask->callback_running = 0;
- _rtx2_init_sema(&ptask->wakeup_sema, 0);
- _rtx2_init_sema(&ptask->terminate_sema, 0);
- //rtw_init_queue(&wq->work_queue);
+ _rtx2_init_sema(&ptask->wakeup_sema, 0);
+ _rtx2_init_sema(&ptask->terminate_sema, 0);
+ //rtw_init_queue(&wq->work_queue);
- thread_hdl->id = osThreadNew((osThreadFunc_t)func, thctx, &thread_hdl->attr);
- if(thread_hdl->id == NULL)
- goto err_exit;
- return _SUCCESS;
+ thread_hdl->id = osThreadNew((osThreadFunc_t)func, thctx, &thread_hdl->attr);
+ if (thread_hdl->id == NULL) {
+ DBG_ERR("[%s] osThreadNew failed", name);
+ goto err_exit;
+ }
+ return _SUCCESS;
err_exit:
- if(thread_hdl){
- _rtx2_free_sema(&ptask->wakeup_sema);
- _rtx2_free_sema(&ptask->terminate_sema);
- _rtx2_memset((u8 *)ptask, 0, sizeof(*ptask));
- if(thread_hdl->attr.stack_mem)
- _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size);
- _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t));
- }
- DBG_ERR("Create Task \"%s\" Failed! \n", ptask->task_name);
- return _FAIL;
+ if(thread_hdl){
+ _rtx2_free_sema(&ptask->wakeup_sema);
+ _rtx2_free_sema(&ptask->terminate_sema);
+ _rtx2_memset((u8 *)ptask, 0, sizeof(*ptask));
+ if(thread_hdl->attr.stack_mem)
+ _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size);
+ _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t));
+ }
+ DBG_ERR("Create Task \"%s\" Failed! \n", name);
+ return _FAIL;
}
static void _rtx2_delete_task(struct task_struct *ptask)
{
_func_enter_;
- rtx_thread_data_t *thread_hdl = (rtx_thread_data_t *)ptask->task;
- if (!thread_hdl){
- DBG_ERR("_rtx2_delete_task(): ptask is NULL!\n");
- return;
- }
+ rtx_thread_data_t *thread_hdl = (rtx_thread_data_t *)ptask->task;
+ if (!thread_hdl){
+ DBG_ERR("_rtx2_delete_task(): ptask is NULL!\n");
+ return;
+ }
- ptask->blocked = 1;
+ ptask->blocked = 1;
- _rtx2_up_sema(&ptask->wakeup_sema);
- _rtx2_down_sema(&ptask->terminate_sema, TIMER_MAX_DELAY);
+ _rtx2_up_sema(&ptask->wakeup_sema);
+ _rtx2_down_sema(&ptask->terminate_sema, TIMER_MAX_DELAY);
- osThreadTerminate(thread_hdl->id);
- if(thread_hdl->attr.stack_mem)
- _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size);
- _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t));
-
- //rtw_deinit_queue(&wq->work_queue);
- _rtx2_free_sema(&ptask->wakeup_sema);
- _rtx2_free_sema(&ptask->terminate_sema);
+ osThreadTerminate(thread_hdl->id);
+ if(thread_hdl->attr.stack_mem)
+ _rtx2_mfree((void *)thread_hdl->attr.stack_mem, thread_hdl->attr.stack_size);
+ _rtx2_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t));
- ptask->task = NULL;
+ //rtw_deinit_queue(&wq->work_queue);
+ _rtx2_free_sema(&ptask->wakeup_sema);
+ _rtx2_free_sema(&ptask->terminate_sema);
- DBG_TRACE("Delete Task \"%s\"\n", ptask->task_name);
+ ptask->task = NULL;
+
+ DBG_TRACE("Delete Task \"%s\"\n", ptask->task_name);
_func_exit_;
}
void _rtx2_wakeup_task(struct task_struct *ptask)
{
_func_enter_;
- if(ptask)
- _rtx2_up_sema(&ptask->wakeup_sema);
+ if(ptask)
+ _rtx2_up_sema(&ptask->wakeup_sema);
_func_exit_;
}
static void _rtx2_thread_enter(char *name)
{
_func_enter_;
- DBG_INFO("\n\rRTKTHREAD %s\n", name);
+ DBG_INFO("\n\rRTKTHREAD %s\n", name);
_func_exit_;
}
static void _rtx2_thread_exit(void)
{
_func_enter_;
- osThreadExit();
-_func_exit_;
+ osThreadExit();
}
/*****************************************************
@@ -892,204 +897,335 @@
} os_timer_cb;
*****************************************************/
_timerHandle _rtx2_timerCreate( const signed char *pcTimerName,
- osdepTickType xTimerPeriodInTicks,
- u32 uxAutoReload,
- void * pvTimerID,
- TIMER_FUN pxCallbackFunction )
+ osdepTickType xTimerPeriodInTicks,
+ u32 uxAutoReload,
+ void * pvTimerID,
+ TIMER_FUN pxCallbackFunction )
{
_func_enter_;
- rtx_tmr_t *tmr = (rtx_tmr_t *)_rtx2_zmalloc(sizeof(rtx_tmr_t));
- osTimerType_t type = (uxAutoReload == _TRUE)?osTimerPeriodic:osTimerOnce;
- if(tmr == NULL)
- goto err_exit;
+ rtx_tmr_t *tmr = (rtx_tmr_t *)_rtx2_zmalloc(sizeof(rtx_tmr_t));
+ osTimerType_t type = (uxAutoReload == _TRUE)?osTimerPeriodic:osTimerOnce;
+ if(tmr == NULL)
+ goto err_exit;
- tmr->attr.name = pcTimerName;
- tmr->attr.cb_mem = (void *)&tmr->data;
- tmr->attr.cb_size = sizeof(tmr->data);
- if(pvTimerID == NULL)
- pvTimerID = (void *)tmr;
- tmr->id = osTimerNew(pxCallbackFunction, type, pvTimerID, &tmr->attr);
- if(tmr->id == NULL)
- goto err_exit;
+ tmr->attr.name = (const char *)pcTimerName;
+ tmr->attr.cb_mem = (void *)&tmr->data;
+ tmr->attr.cb_size = sizeof(tmr->data);
+ if(pvTimerID == NULL)
+ pvTimerID = (void *)tmr;
+ tmr->id = osTimerNew(pxCallbackFunction, type, pvTimerID, &tmr->attr);
+ if(tmr->id == NULL)
+ goto err_exit;
_func_exit_;
- return (_timerHandle)tmr;
+ return (_timerHandle)tmr;
err_exit:
- DBG_ERR("error");
- if(tmr)
- _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t));
- return NULL;
+ DBG_ERR("error");
+ if(tmr)
+ _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t));
+ return NULL;
}
-u32 _rtx2_timerDelete( _timerHandle xTimer,
- osdepTickType xBlockTime )
+u32 _rtx2_timerDelete(_timerHandle xTimer,
+ osdepTickType xBlockTime)
+{
+_func_enter_;
+ rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
+ osStatus_t status = osTimerDelete(tmr->id);
+ _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t));
+ if(status != osOK){
+ DBG_ERR("error %d", status);
+ return _FAIL;
+ }
+_func_exit_;
+ return _SUCCESS;
+}
+
+u32 _rtx2_timerIsTimerActive(_timerHandle xTimer)
{
_func_enter_;
- rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
- osStatus_t status = osTimerDelete(tmr->id);
- _rtx2_mfree((u8 *)tmr, sizeof(rtx_tmr_t));
- if(status != osOK){
- DBG_ERR("error %d", status);
- return _FAIL;
- }
-_func_exit_;
- return _SUCCESS;
+ rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
+ if (osTimerIsRunning(tmr->id)) {
+ return _TRUE;
+ }
+ return _FALSE;
}
-u32 _rtx2_timerIsTimerActive( _timerHandle xTimer )
+u32 _rtx2_timerStop(_timerHandle xTimer,
+ osdepTickType xBlockTime)
+{
+_func_enter_;
+ rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
+ if(_rtx2_timerIsTimerActive(xTimer) == _TRUE){
+ osStatus_t status = osTimerStop(tmr->id);
+ if(status != osOK){
+ DBG_ERR("error %d\n", status);
+_func_exit_;
+ return _FAIL;
+ }
+ }
+_func_exit_;
+ return _SUCCESS;
+}
+
+u32 _rtx2_timerChangePeriod(_timerHandle xTimer,
+ osdepTickType xNewPeriod,
+ osdepTickType xBlockTime)
{
_func_enter_;
- rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
- if(osTimerIsRunning(tmr->id))
- return _TRUE;
- return _FALSE;
+ rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
+ osStatus_t ret;
+
+ if(xNewPeriod == 0)
+ xNewPeriod += 1;
+ //xNewPeriod = _rtx2_systime_to_ms(xNewPeriod);
+ ret = osTimerStart(tmr->id, xNewPeriod);
+_func_exit_;
+ if(ret == osOK)
+ return _SUCCESS;
+
+ DBG_ERR("%s error\n", __FUNCTION__);
+ return _FAIL;
}
-u32 _rtx2_timerStop( _timerHandle xTimer,
- osdepTickType xBlockTime )
+void *_rtx2_timerGetID(_timerHandle xTimer)
+{
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return NULL;
+}
+
+u32 _rtx2_timerStart(_timerHandle xTimer,
+ osdepTickType xBlockTime)
{
-_func_enter_;
- rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
- if(_rtx2_timerIsTimerActive(xTimer) == _TRUE){
- osStatus_t status = osTimerStop(tmr->id);
-_func_exit_;
- if(status != osOK){
- DBG_ERR("error %d\n", status);
- return _FAIL;
- }
- }
- return _SUCCESS;
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
+}
+
+u32 _rtx2_timerStartFromISR(_timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken)
+{
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
+}
+
+u32 _rtx2_timerStopFromISR(_timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken)
+{
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
}
-u32 _rtx2_timerChangePeriod( _timerHandle xTimer,
- osdepTickType xNewPeriod,
- osdepTickType xBlockTime )
+u32 _rtx2_timerResetFromISR(_timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken)
{
-_func_enter_;
- rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer;
- osStatus_t ret;
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
+}
- if(xNewPeriod == 0)
- xNewPeriod += 1;
- //xNewPeriod = _rtx2_systime_to_ms(xNewPeriod);
- ret = osTimerStart(tmr->id, xNewPeriod);
-_func_exit_;
- if(ret == osOK)
- return _SUCCESS;
-
- DBG_ERR("%s error\n", __FUNCTION__);
- return _FAIL;
+u32 _rtx2_timerChangePeriodFromISR(_timerHandle xTimer,
+ osdepTickType xNewPeriod,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken)
+{
+ if(xNewPeriod == 0)
+ xNewPeriod += 1;
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
}
-//void _rtx2_acquire_wakelock()
-//{
-//#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
-// acquire_wakelock(WAKELOCK_WLAN);
-//#endif
-//}
+u32 _rtx2_timerReset(_timerHandle xTimer,
+ osdepTickType xBlockTime)
+{
+ DBG_ERR("%s: Not implemented yet\n", __FUNCTION__);
+ return _FAIL;
+}
-//void _rtx2_release_wakelock()
-//{
-//#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
-// release_wakelock(WAKELOCK_WLAN);
-//#endif
-//}
+void _rtx2_acquire_wakelock()
+{
+ //TODO
+ return;
+}
+
+void _rtx2_release_wakelock()
+{
+ //TODO
+ return;
+}
+
+void _rtx2_wakelock_timeout(uint32_t timeout)
+{
+ //TODO
+ return;
+}
u8 _rtx2_get_scheduler_state(void)
{
_func_enter_;
- osKernelState_t state = osKernelGetState();
- u8 state_out = OS_SCHEDULER_NOT_STARTED;
- switch(state){
- case osKernelRunning: state = OS_SCHEDULER_RUNNING; break;
- case osKernelSuspended: state = OS_SCHEDULER_SUSPENDED; break;
- default: break;
- }
+ osKernelState_t state = osKernelGetState();
+ u8 state_out = OS_SCHEDULER_NOT_STARTED;
+ switch(state){
+ case osKernelRunning:
+ state_out = OS_SCHEDULER_RUNNING;
+ break;
+ case osKernelSuspended:
+ state_out = OS_SCHEDULER_SUSPENDED;
+ break;
+ default:
+ break;
+ }
_func_exit_;
- return state_out;
+ return state_out;
}
const struct osdep_service_ops osdep_service = {
- _rtx2_malloc, //rtw_vmalloc
- _rtx2_zmalloc, //rtw_zvmalloc
- _rtx2_mfree, //rtw_vmfree
- _rtx2_malloc, //rtw_malloc
- _rtx2_zmalloc, //rtw_zmalloc
- _rtx2_mfree, //rtw_mfree
- _rtx2_memcpy, //rtw_memcpy
- _rtx2_memcmp, //rtw_memcmp
- _rtx2_memset, //rtw_memset
- _rtx2_init_sema, //rtw_init_sema
- _rtx2_free_sema, //rtw_free_sema
- _rtx2_up_sema, //rtw_up_sema
- _rtx2_up_sema_from_isr,//rtw_up_sema_from_isr
- _rtx2_down_sema, //rtw_down_sema
- _rtx2_mutex_init, //rtw_mutex_init
- _rtx2_mutex_free, //rtw_mutex_free
- _rtx2_mutex_get, //rtw_mutex_get
- _rtx2_mutex_get_timeout, //rtw_mutex_get_timeout
- _rtx2_mutex_put, //rtw_mutex_put
- _rtx2_enter_critical, //rtw_enter_critical
- _rtx2_exit_critical, //rtw_exit_critical
- _rtx2_enter_critical_from_isr, //rtw_enter_critical_from_isr
- _rtx2_exit_critical_from_isr, //rtw_exit_critical_from_isr
- NULL, //rtw_enter_critical_bh
- NULL, //rtw_exit_critical_bh
- _rtx2_enter_critical_mutex, //rtw_enter_critical_mutex
- _rtx2_exit_critical_mutex, //rtw_exit_critical_mutex
- _rtx2_spinlock_init, //rtw_spinlock_init
- _rtx2_spinlock_free, //rtw_spinlock_free
- _rtx2_spinlock, //rtw_spin_lock
- _rtx2_spinunlock, //rtw_spin_unlock
- _rtx2_spinlock_irqsave, //rtw_spinlock_irqsave
- _rtx2_spinunlock_irqsave, //rtw_spinunlock_irqsave
- _rtx2_init_xqueue,//rtw_init_xqueue
- _rtx2_push_to_xqueue,//rtw_push_to_xqueue
- _rtx2_pop_from_xqueue,//rtw_pop_from_xqueue
- _rtx2_deinit_xqueue,//rtw_deinit_xqueue
- _rtx2_get_current_time, //rtw_get_current_time
- _rtx2_systime_to_ms, //rtw_systime_to_ms
- _rtx2_systime_to_sec, //rtw_systime_to_sec
- _rtx2_ms_to_systime, //rtw_ms_to_systime
- _rtx2_sec_to_systime, //rtw_sec_to_systime
- _rtx2_msleep_os, //rtw_msleep_os
- _rtx2_usleep_os, //rtw_usleep_os
- _rtx2_mdelay_os, //rtw_mdelay_os
- _rtx2_udelay_os, //rtw_udelay_os
- _rtx2_yield_os, //rtw_yield_os
-
- _rtx2_ATOMIC_SET, //ATOMIC_SET
- _rtx2_ATOMIC_READ, //ATOMIC_READ
- _rtx2_ATOMIC_ADD, //ATOMIC_ADD
- _rtx2_ATOMIC_SUB, //ATOMIC_SUB
- _rtx2_ATOMIC_INC, //ATOMIC_INC
- _rtx2_ATOMIC_DEC, //ATOMIC_DEC
- _rtx2_ATOMIC_ADD_RETURN, //ATOMIC_ADD_RETURN
- _rtx2_ATOMIC_SUB_RETURN, //ATOMIC_SUB_RETURN
- _rtx2_ATOMIC_INC_RETURN, //ATOMIC_INC_RETURN
- _rtx2_ATOMIC_DEC_RETURN, //ATOMIC_DEC_RETURN
+ _rtx2_malloc, //rtw_vmalloc
+ _rtx2_zmalloc, //rtw_zvmalloc
+ _rtx2_mfree, //rtw_vmfree
+ _rtx2_malloc, //rtw_malloc
+ _rtx2_zmalloc, //rtw_zmalloc
+ _rtx2_mfree, //rtw_mfree
+ _rtx2_memcpy, //rtw_memcpy
+ _rtx2_memcmp, //rtw_memcmp
+ _rtx2_memset, //rtw_memset
+ _rtx2_init_sema, //rtw_init_sema
+ _rtx2_free_sema, //rtw_free_sema
+ _rtx2_up_sema, //rtw_up_sema
+ _rtx2_up_sema_from_isr, //rtw_up_sema_from_isr
+ _rtx2_down_sema, //rtw_down_timeout_sema
+ _rtx2_mutex_init, //rtw_mutex_init
+ _rtx2_mutex_free, //rtw_mutex_free
+ _rtx2_mutex_get, //rtw_mutex_get
+ _rtx2_mutex_get_timeout, //rtw_mutex_get_timeout
+ _rtx2_mutex_put, //rtw_mutex_put
+ _rtx2_enter_critical, //rtw_enter_critical
+ _rtx2_exit_critical, //rtw_exit_critical
+ _rtx2_enter_critical_from_isr, //rtw_enter_critical_from_isr
+ _rtx2_exit_critical_from_isr, //rtw_exit_critical_from_isr
+ NULL, //rtw_enter_critical_bh
+ NULL, //rtw_exit_critical_bh
+ _rtx2_enter_critical_mutex, //rtw_enter_critical_mutex
+ _rtx2_exit_critical_mutex, //rtw_exit_critical_mutex
+ _rtx2_cpu_lock, //rtw_cpu_lock
+ _rtx2_cpu_unlock, //rtw_cpu_unlock
+ _rtx2_spinlock_init, //rtw_spinlock_init
+ _rtx2_spinlock_free, //rtw_spinlock_free
+ _rtx2_spinlock, //rtw_spin_lock
+ _rtx2_spinunlock, //rtw_spin_unlock
+ _rtx2_spinlock_irqsave, //rtw_spinlock_irqsave
+ _rtx2_spinunlock_irqsave, //rtw_spinunlock_irqsave
+ _rtx2_init_xqueue, //rtw_init_xqueue
+ _rtx2_push_to_xqueue, //rtw_push_to_xqueue
+ _rtx2_pop_from_xqueue, //rtw_pop_from_xqueue
+ _rtx2_deinit_xqueue, //rtw_deinit_xqueue
+ _rtx2_get_current_time, //rtw_get_current_time
+ _rtx2_systime_to_ms, //rtw_systime_to_ms
+ _rtx2_systime_to_sec, //rtw_systime_to_sec
+ _rtx2_ms_to_systime, //rtw_ms_to_systime
+ _rtx2_sec_to_systime, //rtw_sec_to_systime
+ _rtx2_msleep_os, //rtw_msleep_os
+ _rtx2_usleep_os, //rtw_usleep_os
+ _rtx2_mdelay_os, //rtw_mdelay_os
+ _rtx2_udelay_os, //rtw_udelay_os
+ _rtx2_yield_os, //rtw_yield_os
- _rtx2_modular64, //rtw_modular64
- _rtx2_get_random_bytes, //rtw_get_random_bytes
- _rtx2_GetFreeHeapSize, //rtw_getFreeHeapSize
+ _rtx2_ATOMIC_SET, //ATOMIC_SET
+ _rtx2_ATOMIC_READ, //ATOMIC_READ
+ _rtx2_ATOMIC_ADD, //ATOMIC_ADD
+ _rtx2_ATOMIC_SUB, //ATOMIC_SUB
+ _rtx2_ATOMIC_INC, //ATOMIC_INC
+ _rtx2_ATOMIC_DEC, //ATOMIC_DEC
+ _rtx2_ATOMIC_ADD_RETURN, //ATOMIC_ADD_RETURN
+ _rtx2_ATOMIC_SUB_RETURN, //ATOMIC_SUB_RETURN
+ _rtx2_ATOMIC_INC_RETURN, //ATOMIC_INC_RETURN
+ _rtx2_ATOMIC_DEC_RETURN, //ATOMIC_DEC_RETURN
- _rtx2_create_task, //rtw_create_task
- _rtx2_delete_task, //rtw_delete_task
- _rtx2_wakeup_task, //rtw_wakeup_task
+ _rtx2_modular64, //rtw_modular64
+ _rtx2_get_random_bytes, //rtw_get_random_bytes
+ _rtx2_GetFreeHeapSize, //rtw_getFreeHeapSize
- _rtx2_thread_enter, //rtw_thread_enter
- _rtx2_thread_exit, //rtw_thread_exit
+ _rtx2_create_task, //rtw_create_task
+ _rtx2_delete_task, //rtw_delete_task
+ _rtx2_wakeup_task, //rtw_wakeup_task
- _rtx2_timerCreate, //rtw_timerCreate,
- _rtx2_timerDelete, //rtw_timerDelete,
- _rtx2_timerIsTimerActive, //rtw_timerIsTimerActive,
- _rtx2_timerStop, //rtw_timerStop,
- _rtx2_timerChangePeriod, //rtw_timerChangePeriod
+ _rtx2_thread_enter, //rtw_thread_enter
+ _rtx2_thread_exit, //rtw_thread_exit
- NULL, // rtw_acquire_wakelock
- NULL, // rtw_release_wakelock
- NULL, //rtw_wakelock_timeout
+ _rtx2_timerCreate, //rtw_timerCreate
+ _rtx2_timerDelete, //rtw_timerDelete
+ _rtx2_timerIsTimerActive, //rtw_timerIsTimerActive
+ _rtx2_timerStop, //rtw_timerStop
+ _rtx2_timerChangePeriod, //rtw_timerChangePeriod
+ _rtx2_timerGetID, //rtw_timerGetID
+ _rtx2_timerStart, //rtw_timerStart
+ _rtx2_timerStartFromISR, //rtw_timerStartFromISR
+ _rtx2_timerStopFromISR, //rtw_timerStopFromISR
+ _rtx2_timerResetFromISR, //rtw_timerResetFromISR
+ _rtx2_timerChangePeriodFromISR, //rtw_timerChangePeriodFromISR
+ _rtx2_timerReset, //rtw_timerReset
- _rtx2_get_scheduler_state // rtw_get_scheduler_state
+ _rtx2_acquire_wakelock, //rtw_acquire_wakelock
+ _rtx2_release_wakelock, //rtw_release_wakelock
+ _rtx2_wakelock_timeout, //rtw_wakelock_timeout
+ _rtx2_get_scheduler_state //rtw_get_scheduler_state
};
+/*
+* Below block is to remove the compilation error of ARMCC
+**/
+HAL_CUT_B_RAM_DATA_SECTION
+_WEAK unsigned int rand_x = 123456789;
+
+_WEAK u8* RtlZmalloc(u32 sz)
+{
+ u8 *pbuf;
+
+ pbuf= rtw_malloc(sz);
+
+ if (pbuf != NULL) {
+ _memset(pbuf, 0, sz);
+ }
+
+ return pbuf;
+}
+
+_WEAK void RtlMfree(u8 *pbuf, u32 sz)
+{
+ rtw_mfree(pbuf, sz);
+}
+
+_WEAK void UartLogIrqHandleRam(void * Data)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK void vPortSVCHandler(void)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK void xPortPendSVHandler(void)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK void xPortSysTickHandler(void)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK u8 __ram_start_table_start__[];
+
+_WEAK void rtw_odm_acquirespinlock(void * adapter, int type)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK void rtw_odm_releasespinlock(void * adapter, int type)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
+_WEAK void ROM_WIFI_BSSID_SET(u8 iface_type, u8 variable, u8 *val)
+{
+ printf("%s: Should not come over here!\r\n", __func__);
+}
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,25 +1,33 @@
-#ifndef _RTX2_SERVICE_H_
-#define _RTX2_SERVICE_H_
+#ifndef _CMSIS_RTOS_SERVICE_H_
+#define _CMSIS_RTOS_SERVICE_H_
//-----------------------------------------------------------------------
// Include Files
//-----------------------------------------------------------------------
-#include "wireless.h"
+//#include "wireless.h"
#include "dlist.h"
#include <cmsis_os2.h>
-//#include <rt_TypeDef.h>
#include "RTX_Config.h"
-//#include <rt_Task.h>
-//#include <rt_Semaphore.h>
-//#include <rt_System.h>
#include "rtx_lib.h"
// --------------------------------------------
// Platform dependent include file
// --------------------------------------------
-#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
-//#include "platform_stdlib.h"
-//#include "basic_types.h"
-#include <rtl8195a.h>
+#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8195BHP)
+#include "platform/platform_stdlib.h"
+extern VOID RtlUdelayOS(u32 us);
+#elif defined(CONFIG_PLATFORM_8711B)
+#include "platform/platform_stdlib.h"
+#elif defined(CONFIG_PLATFORM_8721D)
+#include "platform/platform_stdlib.h"
+#elif defined(CONFIG_HARDWARE_8821C)
+#include "basic_types.h"
+#include "wlan_basic_types.h"
+#elif defined(CONFIG_HARDWARE_8188F)
+#include "platform/platform_stdlib.h"
+#elif defined(CONFIG_HARDWARE_8192E)
+#include "platform/platform_stdlib.h"
+#elif defined(CONFIG_HARDWARE_8723D)
+#include "platform/platform_stdlib.h"
#else
// other MCU may use standard library
#include <string.h>
@@ -28,7 +36,7 @@
#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) || defined(CONFIG_LX_HCI)
/* For SPI interface transfer and us delay implementation */
-#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
+#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) && !defined(CONFIG_PLATFORM_8721D) && !defined(CONFIG_PLATFORM_8195BHP)
#include <rtwlan_bsp.h>
#endif
#endif
@@ -37,129 +45,101 @@
// --------------------------------------------
// Platform dependent type define
// --------------------------------------------
-#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned int u32;
-typedef signed char s8;
-typedef signed short s16;
-typedef signed int s32;
-typedef signed long long s64;
-typedef unsigned long long u64;
-typedef unsigned int uint;
-typedef signed int sint;
-
-#ifndef bool
-typedef int bool;
-#define true 1
-#define false 0
-#endif
-
-#define IN
-#define OUT
-#define VOID void
-#define NDIS_OID uint
-#define NDIS_STATUS uint
-#ifndef PVOID
-typedef void * PVOID;
-#endif
-
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef __kernel_size_t SIZE_T;
-typedef __kernel_ssize_t SSIZE_T;
-
-#endif //CONFIG_PLATFORM_8195A
+#define OS_TICK OS_TICK_FREQ
+#define OS_TICK_RATE_MS (1000/OS_TICK)
// === SEMAPHORE ===
typedef struct {
- osSemaphoreId_t id;
- osSemaphoreAttr_t attr;
- os_semaphore_t data;
+ osSemaphoreId_t id;
+ osSemaphoreAttr_t attr;
+ os_semaphore_t data;
} rtx_sema_t;
// === THREAD ===
typedef struct {
- osThreadId_t id;
- osThreadAttr_t attr;
- os_thread_t data;
+ osThreadId_t id;
+ osThreadAttr_t attr;
+ os_thread_t data;
} rtx_thread_data_t;
// === MUTEX ===
typedef struct {
- osMutexId_t id;
- osMutexAttr_t attr;
- os_mutex_t data;
+ osMutexId_t id;
+ osMutexAttr_t attr;
+ os_mutex_t data;
} rtx_mutex_t;
// === MAIL BOX ===
-#define RTX_MB_SIZE 8
+#define RTX_MB_SIZE 8
typedef struct {
- osEventFlagsId_t id;
- osEventFlagsAttr_t attr;
- os_event_flags_t data;
+ osEventFlagsId_t id;
+ osEventFlagsAttr_t attr;
+ os_event_flags_t data;
- uint8_t post_idx;
- uint8_t fetch_idx;
- void* queue[RTX_MB_SIZE];
+ uint8_t post_idx;
+ uint8_t fetch_idx;
+ void* queue[RTX_MB_SIZE];
} rtx_mqueue_t;
typedef struct {
- osMessageQueueId_t id;
- osMessageQueueAttr_t attr;
- void *queue_mem;
- os_message_queue_t data;
+ osMessageQueueId_t id;
+ osMessageQueueAttr_t attr;
+ void *queue_mem;
+ os_message_queue_t data;
} rtx_mbox_t;
typedef struct{
- osTimerId_t id;
- osTimerAttr_t attr;
- os_timer_t data;
-}rtx_tmr_t;
+ osTimerId_t id;
+ osTimerAttr_t attr;
+ os_timer_t data;
+} rtx_tmr_t;
-#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
+#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
// os types
-typedef char osdepCHAR;
-typedef float osdepFLOAT;
-typedef double osdepDOUBLE;
-typedef long osdepLONG;
-typedef short osdepSHORT;
-typedef unsigned long osdepSTACK_TYPE;
-typedef long osdepBASE_TYPE;
-typedef unsigned long osdepTickType;
+typedef char osdepCHAR;
+typedef float osdepFLOAT;
+typedef double osdepDOUBLE;
+typedef long osdepLONG;
+typedef short osdepSHORT;
+typedef unsigned long osdepSTACK_TYPE;
+typedef long osdepBASE_TYPE;
+typedef unsigned long osdepTickType;
-typedef void * _timerHandle;
-typedef void * _sema;
-typedef void * _mutex;
-typedef void * _lock;
-typedef void * _queueHandle;
-typedef void * _xqueue;
-typedef struct timer_list _timer;
+typedef void * _timerHandle;
+typedef void * _sema;
+typedef void * _mutex;
+typedef void * _lock;
+typedef void * _queueHandle;
+typedef void * _xqueue;
+typedef struct timer_list _timer;
-typedef struct sk_buff _pkt;
-typedef unsigned char _buffer;
+typedef struct sk_buff _pkt;
+typedef unsigned char _buffer;
+typedef unsigned int systime;
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
struct list_head {
- struct list_head *next, *prev;
+ struct list_head *next, *prev;
};
#endif
-struct __queue {
- struct list_head queue;
- _lock lock;
+struct __queue {
+ struct list_head queue;
+ _lock lock;
};
-typedef struct __queue _queue;
-typedef struct list_head _list;
-typedef unsigned long _irqL;
+typedef struct __queue _queue;
+typedef struct list_head _list;
+typedef unsigned long _irqL;
-typedef void* _thread_hdl_;
-typedef void thread_return;
-typedef void* thread_context;
+typedef void* _thread_hdl_;
+typedef void thread_return;
+typedef void* thread_context;
+
+typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_T atomic_t
#define HZ configTICK_RATE_HZ
@@ -168,33 +148,40 @@
/* emulate a modern version */
#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 17)
-static __inline _list *get_next(_list *list)
+static __inline _list *get_next(_list *list)
{
- return list->next;
-}
+ return list->next;
+}
-static __inline _list *get_list_head(_queue *queue)
+static __inline _list *get_list_head(_queue *queue)
{
- return (&(queue->queue));
+ return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
- ((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr)))
+ ((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr)))
//#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
#define container_of(ptr, type, member) \
- ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
-#define TASK_PRORITY_LOW osPriorityAboveNormal//osPriorityNormal
-#define TASK_PRORITY_MIDDLE osPriorityHigh//osPriorityAboveNormal
-#define TASK_PRORITY_HIGH osPriorityRealtime//osPriorityHigh
-#define TASK_PRORITY_SUPER osPriorityRealtime
-#define TASK_PRORITY_IDEL osPriorityIdle
+ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+#define TASK_PRORITY_LOW 1
+#define TASK_PRORITY_MIDDLE 2
+#define TASK_PRORITY_HIGH 3
+#define TASK_PRORITY_SUPER 4
+#define PRIORITIE_OFFSET 4
+#define TIMER_MAX_DELAY 0xFFFFFFFF
-#define TIMER_MAX_DELAY 0xFFFFFFFF
void save_and_cli(void);
void restore_flags(void);
void cli(void);
+#ifndef mdelay
+#define mdelay(t) ((t/OS_TICK_RATE_MS)>0)?(osDelay(t/OS_TICK_RATE_MS)):(osDelay(1))
+#endif
+
+#ifndef udelay
+#define udelay(t) ((t/(OS_TICK_RATE_MS*1000))>0)?osDelay(t/(OS_TICK_RATE_MS*1000)):(osDelay(1))
+#endif
//----- ------------------------------------------------------------------
// Common Definition
//----- ------------------------------------------------------------------
@@ -208,45 +195,43 @@
#define KERN_INFO
#define KERN_NOTICE
-#define GFP_KERNEL 1
-#define GFP_ATOMIC 1
+#undef GFP_KERNEL
+#define GFP_KERNEL 1
+#define GFP_ATOMIC 1
-#define SET_MODULE_OWNER(some_struct) do { } while (0)
-#define SET_NETDEV_DEV(dev, obj) do { } while (0)
-#define register_netdev(dev) (0)
-#define unregister_netdev(dev) do { } while (0)
-#define netif_queue_stopped(dev) (0)
-#define netif_wake_queue(dev) do { } while (0)
-#define printk printf
+#define SET_MODULE_OWNER(some_struct) do { } while (0)
+#define SET_NETDEV_DEV(dev, obj) do { } while (0)
+#define register_netdev(dev) (0)
+#define unregister_netdev(dev) do { } while (0)
+#define netif_queue_stopped(dev) (0)
+#define netif_wake_queue(dev) do { } while (0)
+#define printk printf
-#define DBG_ERR(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
+#define DBG_ERR(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
#if WLAN_INTF_DBG
-#define DBG_TRACE(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
-#define DBG_INFO(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
+#define DBG_TRACE(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
+#define DBG_INFO(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args)
#else
#define DBG_TRACE(fmt, args...)
#define DBG_INFO(fmt, args...)
#endif
-#define HALT() do { cli(); for(;;);} while(0)
-#define ASSERT(x) do { \
- if((x) == 0) \
- printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \
- HALT(); \
- } while(0)
+#define HALT() do { cli(); for(;;);} while(0)
+#undef ASSERT
+#define ASSERT(x) do { \
+ if((x) == 0){\
+ printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \
+ HALT();}\
+ } while(0)
#undef DBG_ASSERT
-#define DBG_ASSERT(x, msg) do { \
- if((x) == 0) \
- printf("\n\r%s, Assert(" #x ") failed on line %d in file %s", msg, __LINE__, __FILE__); \
- } while(0)
+#define DBG_ASSERT(x, msg) do { \
+ if((x) == 0) \
+ printf("\n\r%s, Assert(" #x ") failed on line %d in file %s", msg, __LINE__, __FILE__); \
+ } while(0)
//----- ------------------------------------------------------------------
// Atomic Operation
//----- ------------------------------------------------------------------
-#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) // for 8195A, it is defined in ..system../basic_types.h
-typedef struct { volatile int counter; } atomic_t;
-#endif
-
/*
* atomic_read - read atomic variable
@@ -255,6 +240,7 @@
* Atomically reads the value of @v. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
+#undef atomic_read
#define atomic_read(v) ((v)->counter)
/*
@@ -265,6 +251,7 @@
* Atomically sets the value of @v to @i. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
+#undef atomic_set
#define atomic_set(v,i) ((v)->counter = (i))
/*
@@ -292,6 +279,10 @@
extern void rtw_list_insert_head(_list *plist, _list *phead);
extern void rtw_list_insert_tail(_list *plist, _list *phead);
extern void rtw_list_delete(_list *plist);
-#define vPortExitCritical save_and_cli
-#endif /* _RTX_SERVICE_H_ */
+#if (defined CONFIG_PLATFORM_8711B) || (defined CONFIG_PLATFORM_8721D)
+extern u32 random_seed;
+#endif
+
+#endif /* _CMSIS_RTOS_SERVICE_H_ */
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c Thu Nov 08 11:46:34 2018 +0000
@@ -53,7 +53,7 @@
{
device_mutex_init(device);
while(rtw_mutex_get_timeout(&device_mutex[device], 10000)<0)
- printf("device lock timeout: %d\n", device);
+ printf("device lock timeout: %d\n", (int)device);
}
//======================================================
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/device_lock.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/device_lock.h Thu Nov 08 11:46:34 2018 +0000 @@ -15,7 +15,9 @@ RT_DEV_LOCK_EFUSE = 0, RT_DEV_LOCK_FLASH = 1, RT_DEV_LOCK_CRYPTO = 2, - RT_DEV_LOCK_MAX = 3 + RT_DEV_LOCK_PTA = 3, + RT_DEV_LOCK_WLAN = 4, + RT_DEV_LOCK_MAX = 5 }; typedef uint32_t RT_DEV_LOCK_E;
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/osdep_service.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/osdep_service.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,4 +1,4 @@
-/* mbed Microcontroller Library
+/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -12,42 +12,44 @@
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- */
-
+ ******************************************************************************/
+
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
-/* OS dep feature enable */
-#include <autoconf.h>
+/** @addtogroup RTOS
+ * @{
+ */
#ifdef __cplusplus
extern "C" {
#endif
+/*************************** OS dep feature enable *******************************/
+
+/******************************************************
+ * Macros
+ ******************************************************/
#define CONFIG_LITTLE_ENDIAN
-#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
-#define CONFIG_PLATFORM_AMEBA_X
+#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_PLATFORM_8721D) || defined(CONFIG_PLATFORM_8195BHP) || defined(CONFIG_PLATFORM_8710C)
+#define CONFIG_PLATFORM_AMEBA_X 1
#endif
#if defined(CONFIG_PLATFORM_8195A)
- #ifndef CONFIG_USE_TCM_HEAP
#define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */
- #endif
#define USE_MUTEX_FOR_SPINLOCK 1
#endif
-#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE
#else
#define CONFIG_MEM_MONITOR MEM_MONITOR_LEAK
#endif
/* Define compilor specific symbol */
-//
-// inline function
-//
+/*************************** inline functions *******************************/
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
@@ -71,9 +73,20 @@
#endif
#include <stdio.h>
-#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
+
+#if defined(CONFIG_PLATFORM_8710C) || defined(CONFIG_PLATFORM_8195BHP)
+#include <platform_conf.h>
+#include <basic_types.h>
+#if (CONFIG_CMSIS_FREERTOS_EN==1)
+#define PLATFORM_FREERTOS 1
+#endif
+#else
+#if (CONFIG_PLATFORM_AMEBA_X == 1)
#include "platform_autoconf.h"
-#else //for 8189FM/8189FTV add by frankie_li 20160408
+#endif
+#endif
+
+#if (CONFIG_PLATFORM_AMEBA_X == 0)
#ifndef SUCCESS
#define SUCCESS 0
#endif
@@ -90,38 +103,64 @@
#define FALSE 0
#endif
+#ifndef false
+ #define false 0
+#endif
+
#ifndef TRUE
#define TRUE (!FALSE)
#endif
+
+#ifndef true
+ #define true (!false)
+#endif
+
+
+#ifndef DBG_8195A
+#define DBG_8195A
+#endif
#define _TRUE TRUE
#define _FALSE FALSE
#endif
-#if defined( PLATFORM_FREERTOS)
+#if defined(PLATFORM_FREERTOS)
#include "freertos_service.h"
-#elif defined( PLATFORM_ECOS)
+#elif defined(PLATFORM_ECOS)
#include "ecos/ecos_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "cmsis_rtos_service.h"
+#elif defined(CONFIG_PLATFOMR_CUSTOMER_RTOS)
+#include "customer_rtos_service.h"
#endif
#define RTW_MAX_DELAY 0xFFFFFFFF
#define RTW_WAIT_FOREVER 0xFFFFFFFF
-/* Definitions returned by xTaskGetSchedulerState(). */
+/******************************************************
+ * Constants
+ ******************************************************/
+/**
+ * @brief Definitions returned by xTaskGetSchedulerState().
+ */
+
#define OS_SCHEDULER_NOT_STARTED 0
#define OS_SCHEDULER_RUNNING 1
#define OS_SCHEDULER_SUSPENDED 2
-
+/******************************************************
+ * Structures
+ ******************************************************/
struct timer_list {
_timerHandle timer_hdl;
unsigned long data;
void (*function)(void *);
};
+/******************************************************
+ * Type Definitions
+ ******************************************************/
typedef thread_return (*thread_func_t)(thread_context context);
typedef void (*TIMER_FUN)(void *context);
typedef int (*event_handler_t)(char *buf, int buf_len, int flags, void *user_data);
@@ -129,19 +168,18 @@
#define CONFIG_THREAD_COMM_SEMA
struct task_struct {
const char *task_name;
- _thread_hdl_ task; /* I: workqueue thread */
+ _thread_hdl_ task; /* I: workqueue thread */
#ifdef CONFIG_THREAD_COMM_SIGNAL
- const char *name; /* I: workqueue thread name */
- u32 queue_num; /* total signal num */
- u32 cur_queue_num; /* cur signal num should < queue_num */
+ const char *name; /* I: workqueue thread name */
+ u32 queue_num; /* total signal num */
+ u32 cur_queue_num; /* cur signal num should < queue_num */
#elif defined(CONFIG_THREAD_COMM_SEMA)
- _sema wakeup_sema;
- _sema terminate_sema;
-// _queue work_queue; //TODO
+ _sema wakeup_sema; /* for internal use only */
+ _sema terminate_sema; /* for internal use only */
#endif
- u32 blocked;
- u32 callback_running;
+ u32 blocked; /* for internal use only */
+ u32 callback_running; /* for internal use only */
};
typedef struct {
@@ -165,6 +203,7 @@
rtw_worker_thread_t *worker_thread;
u32 timeout;
};
+
#ifdef CONFIG_THREAD_COMM_SIGNAL
struct work_struct;
typedef void (*work_func_t)(void *context);
@@ -182,10 +221,10 @@
};
#endif
+
#ifdef CONFIG_MEM_MONITOR
-//----- ------------------------------------------------------------------
-// Memory Monitor
-//----- ------------------------------------------------------------------
+
+/*************************** Memory Monitor *******************************/
#define MEM_MONITOR_SIMPLE 0x1
#define MEM_MONITOR_LEAK 0x2
@@ -194,19 +233,59 @@
#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK
struct mem_entry {
struct list_head list;
- int size;
- void *ptr;
+ int size;
+ void *ptr;
};
#endif
+/**
+ * @brief This function initializes a memory table.
+ * @param[in] pmem_table: The pointer to the memory table.
+ * @param[in] used_num: The number of mem_entry kept in monitor which will be set to 0.
+ * @return None
+ */
void init_mem_monitor(_list *pmem_table, int *used_num);
+
+/**
+ * @brief This function deinitializes a memory table.
+ * @param[in] pmem_table: The pointer to the memory table.
+ * @param[in] used_num: The number of mem_entry kept in monitor.
+ * @return None
+ */
void deinit_mem_monitor(_list *pmem_table, int *used_num);
+
+/**
+ * @brief This function alloc mem_entry to the memory table.
+ * @param[in] pmem_table: The pointer to the memory table to be added.
+ * @param[in] ptr: The pointer to the position to be added.
+ * @param[in] size: The size of added memory.
+ * @param[in] used_num: The number of mem_entry kept in monitor which will add 1 after.
+ * @param[in] flag: MEM_MONITOR_FLAG_WPAS/MEM_MONITOR_FLAG_WIFI_DRV
+ * @return None
+ */
void add_mem_usage(_list *pmem_table, void *ptr, int size, int *used_num, int flag);
+
+/**
+ * @brief This function frees memory from the memory table.
+ * @param[in] pmem_table: The pointer to the memory table
+ * @param[in] ptr: The pointer to the position to be free.
+ * @param[in] used_num: The number of mem_entry kept in monitor.
+ * @param[in] flag: MEM_MONITOR_FLAG_WPAS/MEM_MONITOR_FLAG_WIFI_DRV
+ * @return None
+ */
void del_mem_usage(_list *pmem_table, void *ptr, int *used_num, int flag);
+
+/**
+ * @brief This function get the memory usage of a memory table.
+ * @param[in] pmem_table: The pointer to the memory table.
+ * @return The size of the memory used
+ */
int get_mem_usage(_list *pmem_table);
+/*************************** End Memory Monitor *******************************/
#endif
-/*********************************** OSDEP API *****************************************/
+
+/*************************** Memory Management *******************************/
u8* _rtw_vmalloc(u32 sz);
u8* _rtw_zvmalloc(u32 sz);
void _rtw_vmfree(u8 *pbuf, u32 sz);
@@ -214,11 +293,51 @@
u8* _rtw_malloc(u32 sz);
void _rtw_mfree(u8 *pbuf, u32 sz);
#ifdef CONFIG_MEM_MONITOR
+
+/**
+ * @brief This function allocates the virtually contiguous memory.
+ * @param[in] sz: The size of memory to be allocated.
+ * @return The pointer to the beginning of the memory
+ */
u8* rtw_vmalloc(u32 sz);
+
+/**
+ * @brief This function allocates the virtually contiguous memory
+ * and the values of the memory are setted to 0.
+ * @param[in] sz: The size of memory to be allocated.
+ * @return The pointer to the beginning of the memory
+ */
u8* rtw_zvmalloc(u32 sz);
+
+/**
+ * @brief This function frees the virtually contiguous memory.
+ * @param[in] pbuf: The pointer to the beginning of the memory to be free
+ * @param[in] sz: The size of memory allocated.
+ * @return None
+ */
void rtw_vmfree(u8 *pbuf, u32 sz);
+
+/**
+ * @brief This function allocates the memory
+ * and the values of the memory are setted to 0.
+ * @param[in] sz: The size of memory to be allocated.
+ * @return The pointer to the beginning of the memory
+ */
u8* rtw_zmalloc(u32 sz);
+
+/**
+ * @brief This function allocates the memory.
+ * @param[in] sz: The size of memory to be allocated.
+ * @return The pointer to the beginning of the memory
+ */
u8* rtw_malloc(u32 sz);
+
+/**
+ * @brief This function frees the virtually contiguous memory.
+ * @param[in] pbuf: The pointer to the beginning of the memory to be free
+ * @param[in] sz: The size of memory allocated.
+ * @return None
+ */
void rtw_mfree(u8 *pbuf, u32 sz);
#else
#define rtw_vmalloc _rtw_vmalloc
@@ -229,100 +348,666 @@
#define rtw_mfree _rtw_mfree
#endif
#define rtw_free(buf) rtw_mfree((u8 *)buf, 0)
+
+/**
+ * @brief This function allocates a 2 dimensional array memory.
+ * @param[in] h: The height of the 2D array.
+ * @param[in] w: The width of the 2D array.
+ * @param[in] size: The size of the each charactor in array.
+ * @return the pointer to the beginning of the block
+ */
void* rtw_malloc2d(int h, int w, int size);
+
+/**
+ * @brief This function deallocates the block of memory previously allocated to make it available again.
+ * @param[in] pbuf: Pointer to a memory block previously allocated.
+ * @param[in] h: The height of the 2D array.
+ * @param[in] w: The width of the 2D array.
+ * @param[in] size: The size of the each charactor in array.
+ * @return None
+ */
void rtw_mfree2d(void *pbuf, int h, int w, int size);
+
+/**
+ * @brief This function copies the values of "sz" bytes from the location pointed to by "src"
+ * directly to the memory block pointed to by "des".
+ * @param[in] dst: Pointer to the destination array where the content is to be copied, type-casted to a pointer of type void*.
+ * @param[in] src: Pointer to the source of data to be copied, type-casted to a pointer of type void*.
+ * @param[in] sz: Size of memory to copy.
+ * @return None
+ */
void rtw_memcpy(void* dst, void* src, u32 sz);
+
+/**
+ * @brief This function compares the first "sz" bytes of the block of memory pointed by "dst"
+ * to the first "sz" bytes pointed by "src".
+ * @param[in] dst: Pointer to block of memory to be compared.
+ * @param[in] src: pointer to block of memory to compare.
+ * @param[in] sz: Size of memory to compare.
+ * @return <0: The first byte that does not match in both memory blocks has a lower value in dst than in src.
+ * @return 0: The contents of both memory blocks are equal.
+ * @return <0: The first byte that does not match in both memory blocks has a greater value in dst than in src.
+ */
int rtw_memcmp(void *dst, void *src, u32 sz);
+
+/**
+ * @brief This function sets the first "sz" bytes of the block of memory pointed by "pbuf" to the specified "c".
+ * @param[in] pbuf: Pointer to the block of memory to fill.
+ * @param[in] c: Value to be set.
+ * @param[in] sz: Size of memory to be set to the value "c".
+ * @return None
+ */
void rtw_memset(void *pbuf, int c, u32 sz);
+/*************************** End Memory Management *******************************/
+/*************************** List *******************************/
+
+/**
+ * @brief This function initializes the head of the list.
+ * @param[in] list: Pointer to the list to be initialized.
+ * @return None
+ */
void rtw_init_listhead(_list *list);
+
+/**
+ * @brief This function tests whether a list is empty.
+ * @param[in] phead: Pointer to the list to test.
+ * @return _TRUE/_FALSE
+ */
u32 rtw_is_list_empty(_list *phead);
+
+/**
+ * @brief This function adds a new entry after "phead" for the list.
+ * @param[in] plist: Pointer to the list to be added.
+ * @param[in] phead: List head to add it after.
+ * @return None
+ */
void rtw_list_insert_head(_list *plist, _list *phead);
+
+/**
+ * @brief This function adds a new entry before "phead" for the list.
+ * @param[in] plist: Pointer to the list to be added.
+ * @param[in] phead: List head to add it before.
+ * @return None
+ */
void rtw_list_insert_tail(_list *plist, _list *phead);
+
+/**
+ * @brief This function deletes entry from list and reinitialize it.
+ * @param[in] plist: The element to delete from the list.
+ * @return None
+ * @note Caller must check if the list is empty before calling rtw_list_delete
+ */
void rtw_list_delete(_list *plist);
+/*************************** End List *******************************/
+
+/*************************** Semaphores *******************************/
+/**
+ * @brief This function initializes the unnamed semaphore referred to by "sema" to the value "init_val".
+ * @param[in] sema: Pointer to the semaphore handle to be initialized.
+ * @param[in] init_val: Initial value for semaphore.
+ * @return None
+ */
void rtw_init_sema(_sema *sema, int init_val);
-void rtw_free_sema(_sema *sema);
+
+/**
+ * @brief This function deletes the semaphore.
+ * @param[in] sema: The semaphore to be deleted.
+ * @return None
+ */
+void rtw_free_sema(_sema *sema);
+
+/**
+ * @brief This function releases the semaphore.
+ * This macro must not be used from an ISR.
+ * @param[in] sema: The semaphore to be released.
+ * @return None
+ */
void rtw_up_sema(_sema *sema);
-void rtw_up_sema_from_isr(_sema *sema);
+
+/**
+ * @brief This function releases the semaphore.
+ * This macro can be used from an ISR.
+ * @param[in] sema: The semaphore to be released.
+ * @return None
+ */
+void rtw_up_sema_from_isr(_sema *sema);
+
+/**
+ * @brief This function acquires the semaphore. If no more tasks are allowed to acquire the semaphore,
+ * calling this function will put the task to sleep until the semaphore is up.
+ * @param[in] sema: The semaphore to be acquired.
+ * @return pdTRUE: The semaphore was obtained.
+ * @return pdFALSE: Obtain the semaphore failed.
+ */
u32 rtw_down_sema(_sema *sema);
+
+/**
+ * @brief This function acquires the semaphore. If no more tasks are allowed to acquire the semaphore,
+ * calling this function will put the task to sleep until the semaphore is up.
+ * @param[in] sema: The semaphore to be acquired.
+ * @param[in] timeout: The time in ms to wait for the semaphore to become available.
+ * @return pdTRUE: The semaphore was obtained.
+ * @return pdFALSE: Timeout without the semaphore becoming available.
+ */
u32 rtw_down_timeout_sema(_sema *sema, u32 timeout);
+/*************************** End Semaphores *******************************/
+
+/*************************** Mutexes *******************************/
+/**
+ * @brief This function implements a mutex semaphore by using the existing queue mechanism.
+ * @param[in] pmutex: Pointer to the created mutex semaphore.
+ * @return None
+ */
void rtw_mutex_init(_mutex *pmutex);
+
+/**
+ * @brief This function deletes the mutex semaphore.
+ * @param[in] pmutex: Pointer to the mutex semaphore to be deleted.
+ * @return None
+ */
void rtw_mutex_free(_mutex *pmutex);
+
+/**
+ * @brief This function releases a mutex semaphore.
+ * @param[in] pmutex: Pointer to the mutex semaphore to be released.
+ * @return None
+ */
void rtw_mutex_put(_mutex *pmutex);
+
+/**
+ * @brief This function obtains a mutex semaphore.
+ * @param[in] pmutex: Pointer to the mutex semaphore being taken - obtained when
+ * the mutex semaphore was created.
+ * @return None
+ */
void rtw_mutex_get(_mutex *pmutex);
-int rtw_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms);
+
+/**
+ * @brief This function obtains a mutex semaphore with a timeout setting.
+ * @param[in] pmutex: Pointer to the mutex semaphore being taken - obtained when
+ * the mutex semaphore was created.
+ * @param[in] timeout: The time in ms to wait for the semaphore to become available.
+ * @return 0: The semaphore was obtained.
+ * @return -1: Timeout without the semaphore becoming available.
+ */
+int rtw_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms);
+/*************************** End Mutexes *******************************/
+
+/*************************** SchedulerControl *******************************/
+/**
+ * @brief This function marks the start of a critical code region.
+ * Preemptive context switches cannot occur when in a critical region.
+ * @param[in] plock: Pointer to the spin lock semaphore.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ * @note: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ */
void rtw_enter_critical(_lock *plock, _irqL *pirqL);
+
+/**
+ * @brief This function marks end of a critical code region. Preemptive context
+ * switches cannot occur when in a critical region.
+ * @param[in] plock: Pointer to the spin lock semaphore.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ * @note: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ */
void rtw_exit_critical(_lock *plock, _irqL *pirqL);
+
+/**
+ * @brief This function marks the start of a critical code region from isr.
+ * @param[in] plock: Pointer to the spin lock semaphore.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_enter_critical_from_isr(_lock *plock, _irqL *pirqL);
+
+/**
+ * @brief This function marks the end of a critical code region from isr.
+ * @param[in] plock: Pointer to the spin lock semaphore.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_exit_critical_from_isr(_lock *plock, _irqL *pirqL);
+
+/**
+ * @brief This function obtains a spin lock semaphore.
+ * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when
+ * the mutex semaphore was created.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_enter_critical_bh(_lock *plock, _irqL *pirqL);
+
+/**
+ * @brief This function releases a spin lock semaphore.
+ * @param[in] plock: Pointer to the spin lock semaphore to be released.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_exit_critical_bh(_lock *plock, _irqL *pirqL);
-int rtw_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL);
+
+/**
+ * @brief This function obtains a semaphore.
+ * @param[in] pmutex: The handle to the mutex semaphore to be obtained.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
+int rtw_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL);
+
+/**
+ * @brief This function releases a semaphore.
+ * @param[in] pmutex: The handle to the mutex semaphore to be released.
+ * @param[in] pirqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL);
+
+/**
+ * @brief This function will lock cpu. Can be used when xip active and want to do some flash operation.
+ * @return None
+ */
+void rtw_cpu_lock(void);
+
+ /**
+ * @brief This function unlock cpu.
+ * @return None
+ */
+void rtw_cpu_unlock(void);
+
+/*************************** End SchedulerControl *******************************/
+
+/*************************** Semaphores *******************************/
+
+/**
+ * @brief This function implements a spin lock semaphore by using the existing queue mechanism.
+ * @param[in] plock: Pointer to the created spin lock semaphore.
+ * @return None
+ */
void rtw_spinlock_init(_lock *plock);
+
+/**
+ * @brief This function deletes the spin lock semaphore.
+ * @param[in] pmutex: Pointer to the spin lock semaphore to be deleted.
+ * @return None
+ */
void rtw_spinlock_free(_lock *plock);
-void rtw_spinlock_init(_lock *plock);
-void rtw_spinlock_free(_lock *plock);
+
+/**
+ * @brief This function obtains a spin lock semaphore.
+ * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when
+ * the mutex semaphore was created.
+ * @return None
+ */
void rtw_spin_lock(_lock *plock);
+
+/**
+ * @brief This function releases a spin lock semaphore.
+ * @param[in] plock: Pointer to the spin lock semaphore to be released.
+ * @return None
+ */
void rtw_spin_unlock(_lock *plock);
+
+/**
+ * @brief This function marks the start of a critical code region and
+ * obtains a spin lock semaphore.
+ * @param[in] plock: Pointer to the spin lock semaphore being taken - obtained when
+ * the mutex semaphore was created.
+ * @param[in] irqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_spinlock_irqsave(_lock *plock, _irqL *irqL);
+
+/**
+ * @brief This function releases a spin lock semaphore and
+ marks the end of a critical code region.
+ * @param[in] plock: Pointer to the spin lock semaphore to be released.
+ * @param[in] irqL: Pointer to the IRQ.
+ * @return None
+ */
void rtw_spinunlock_irqsave(_lock *plock, _irqL *irqL);
+/*************************** End Semaphores *******************************/
+/*************************** Queues *******************************/
+
+/**
+ * @brief This function creates a new queue instance.
+ * @param[in] queue: The handle to the newly created queue.
+ * @param[in] name: The name of the queue
+ * @param[in] message_size: The number of bytes each message in the queue will require.
+ * @param[in] number_of_messages: The maximum number of messages that kthe queue can contain.
+ * @return 0: Creating queue success
+ * @return -1: Creating queue fail
+ */
int rtw_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages );
+
+/**
+ * @brief This function posts a message to the back of a queue.
+ * The message is queued by copy, not by reference.
+ * @param[in] queue: The handle to the queue on which the message is to be posted.
+ * @param[in] message: The pointer to the message that is to be placed on the queue.
+ * @param[in] timeout_ms: The maximum amout of time the task should block waiting for
+ the space to become available on the queue, should it already be full.
+ The time is defined in ms.
+ * @return 0: The message was successfully posted.
+ * @return -1: The message was not posted.
+ */
int rtw_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms );
+
+/**
+ * @brief This function receives a message from a queue.
+ * The message is recieved by copy so a buffer adequate size must be provided.
+ * @param[in] queue: The handle to the queue from which the message is to be received.
+ * @param[in] message: The pointer to the buffer into which the received message will be copied.
+ * @param[in] timeout_ms: The maximum amout of time the task should block waiting for a message to
+ * receive should the queue be empty at the time of the call.
+ The time is defined in ms.
+ * @return 0: A message was successfully received from the queue.
+ * @return -1: No message was received from the queue.
+ */
int rtw_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms );
+
+/**
+ * @brief Delete a queue - freeing all the memory allocated for storing of messages placed on the queue.
+ * @param[in] queue: The handle to the queue to be deleted.
+ * @return 0: The queue was successfully deleted.
+ * @return -1: The queue was not empty so cannot be deleted.
+ */
int rtw_deinit_xqueue( _xqueue* queue );
+/**
+ * @brief This function creates a new queue instance.
+ * @param[in] pqueue: The handle to the newly created queue.
+ * @return None
+ */
void rtw_init_queue(_queue *pqueue);
void rtw_deinit_queue(_queue *pqueue);
u32 rtw_is_queue_empty(_queue *pqueue);
+
+/**
+ * @brief This function tests whether the queue is empty.
+ * @param[in] pqueue: The handle to the queue to be tested.
+ * @return None
+ */
u32 rtw_queue_empty(_queue *pqueue);
+
+/**
+ * @brief This function tests whether the "pelement" is at the "queue".
+ * @param[in] queue: The pointer to the queue that to be tested.
+ * @param[in] pelement: The element that to be tested.
+ * @return _TRUE/_FALSE
+ */
u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
_list* rtw_get_queue_head(_queue *queue);
+/*************************** End Queues *******************************/
+/*************************** Time Management *******************************/
+
+/**
+ * @brief Get the count of ticks since the vTaskStartScheduler was called.
+ * @return The count of ticks since the vTaskStartScheduler was called.
+ */
u32 rtw_get_current_time(void);
+
+/**
+ * @brief Convert system time to milliseconds.
+ * @param[in] systime: The system time to be converted.
+ * @return : The milliseconds that converted by the system time.
+ */
u32 rtw_systime_to_ms(u32 systime);
+
+/**
+ * @brief Convert system time to seconds.
+ * @param[in] systime: The system time to be converted.
+ * @return : The seconds that converted by the system time.
+ */
u32 rtw_systime_to_sec(u32 systime);
+
+/**
+ * @brief Convert milliseconds to system time.
+ * @param[in] systime: The milliseconds to be converted.
+ * @return : The system time that converted by the milliseconds.
+ */
u32 rtw_ms_to_systime(u32 ms);
+
+/**
+ * @brief Convert seconds to system time.
+ * @param[in] systime: The seconds to be converted.
+ * @return : The system time that converted by the seconds.
+ */
u32 rtw_sec_to_systime(u32 sec);
+
+/**
+ * @brief Get the passing time from the "start" in milliseconds.
+ * @param[in] start: The start time which is in system time format.
+ * @return : The passing time from "start" in milliseconds.
+ */
s32 rtw_get_passing_time_ms(u32 start);
+
+/**
+ * @brief Get the interval time from the "start" to "end" in milliseconds.
+ * @param[in] start: The start time which is in system time format.
+ * @param[in] end: The end time which is in system time format.
+ * @return : The interval time from "start" to "end" in milliseconds.
+ */
s32 rtw_get_time_interval_ms(u32 start, u32 end);
+/*************************** End Time Management *******************************/
+/**
+ * @brief This function suspends execution of the calling thread for "ms" milliseconds.
+ * @param[in] ms: The time that the function sleep in milliseconds
+ * @return None
+*/
void rtw_msleep_os(int ms);
+
+/**
+ * @brief This function suspends execution of the calling thread for "us" microseconds.
+ * @param[in] ms: The time that the function sleep in microseconds
+ * @return None
+*/
void rtw_usleep_os(int us);
+
+/**
+ * @brief This function converts the initial portion of the string to integer.
+ * @param[in] s: The pointer to the string to be converted.
+ * @return The converted value.
+*/
u32 rtw_atoi(u8* s);
+
+/**
+ * @brief This function delays a task for the giving time in milliseconds.
+ * @param[in] ms: The amount of time, in milliseconds, that the calling task should block.
+ * @return None
+*/
void rtw_mdelay_os(int ms);
+
+/**
+ * @brief This function delays a task for the giving time in microseconds.
+ * @param[in] ms: The amount of time, in microseconds, that the calling task should block.
+ * @return None
+*/
void rtw_udelay_os(int us);
+
+/**
+ * @brief This function for forcing a context switch.
+ * @return None
+*/
void rtw_yield_os(void);
-//Atomic integer operations
+/*************************** ATOMIC Integer *******************************/
+
+/**
+ * @brief This function atomically sets the value of the variable.
+ * @param[in] v: Pointer of type atomic_t that to be set value.
+ * @param[in] i: Required value.
+ * @return None
+ * @note The guaranteed useful range of an atomic_t is only 24 bits.
+*/
void ATOMIC_SET(ATOMIC_T *v, int i);
+
+/**
+ * @brief This function atomically reads the value of the variable.
+ * @param[in] v: Pointer of type atomic_t that to be read.
+ * @return The value of the variable.
+ * @note The guaranteed useful range of an atomic_t is only 24 bits.
+*/
int ATOMIC_READ(ATOMIC_T *v);
+
+/**
+ * @brief This function adds "i" to the contained "v".
+ * @param[in] v: Pointer of type atomic_t.
+ * @param[in] i: value to add.
+ * @return None
+*/
void ATOMIC_ADD(ATOMIC_T *v, int i);
+
+/**
+ * @brief This function subtracts "i" from th econtained "v".
+ * @param[in] v: Pointer of type atomic_t.
+ * @param[in] i: value to subtract.
+ * @return None
+*/
void ATOMIC_SUB(ATOMIC_T *v, int i);
+
+/**
+ * @brief This function adds 1 to the contained "v".
+ * @param[in] v: Pointer of type atomic_t.
+ * @return None
+*/
void ATOMIC_INC(ATOMIC_T *v);
+
+/**
+ * @brief This function subtracts 1 from th econtained "v".
+ * @param[in] v: Pointer of type atomic_t.
+ * @return None
+*/
void ATOMIC_DEC(ATOMIC_T *v);
+
+/**
+ * @brief This function adds "i" to the contained "v" and returns the result.
+ * @param[in] v: Pointer of type atomic_t.
+ * @param[in] i: value to add.
+ * @return None
+*/
int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
+
+/**
+ * @brief This function subtracts "i" from th econtained "v" and returns the result.
+ * @param[in] v: Pointer of type atomic_t.
+ * @param[in] i: value to subtract.
+ * @return None
+*/
int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
+
+/**
+ * @brief This function adds 1 to the contained "v" and returns the result.
+ * @param[in] v: Pointer of type atomic_t.
+ * @return None
+*/
int ATOMIC_INC_RETURN(ATOMIC_T *v);
+
+/**
+ * @brief This function subtracts 1 from th econtained "v" and returns the result.
+ * @param[in] v: Pointer of type atomic_t.
+ * @return None
+*/
int ATOMIC_DEC_RETURN(ATOMIC_T *v);
+
+/**
+ * @brief This function subtracts 1 from th econtained "v" and test if the result equals 0.
+ * @param[in] v: Pointer of type atomic_t.
+ * @return 0: The result after subtracting 1 is 0
+ * @return -1: The result after subtracting 1 is not 0
+*/
int ATOMIC_DEC_AND_TEST(ATOMIC_T *v);
+/*************************** End ATOMIC *******************************/
u64 rtw_modular64(u64 x, u64 y);
+
+/**
+ * @brief This function generates random bytes.
+ * @param[in] dst: The pointer to the buffer to store the random bytes.
+ * @param[in] size: The size of the random bytes.
+ * @return 0
+*/
int rtw_get_random_bytes(void* dst, u32 size);
+
+/**
+ * @brief This function gets the available heap size.
+ * @return The value of the available heap size.
+*/
u32 rtw_getFreeHeapSize(void);
+
void flush_signals_thread(void);
+/**
+ * @brief This function indicates that the WLAN needs to stay on which means cannot go into power saving mode.
+ * @return None
+ * @note Defining configUSE_WAKELOCK_PMU 1 in "FreeRTOSConfig.h" needs to be done before compiling,
+ * or this API won't be effective.
+ */
void rtw_acquire_wakelock(void);
+
+/**
+ * @brief This function indicates that the WLAN does not need to stay on which means can go into power saving mode.
+ * @return None
+ * @note Defining configUSE_WAKELOCK_PMU 1 in "FreeRTOSConfig.h" needs to be done before compiling,
+ * or this API won't be effective.
+ */
void rtw_release_wakelock(void);
void rtw_wakelock_timeout(u32 timeout);
/*********************************** Thread related *****************************************/
+
+/**
+ * @brief This function creates a new task and adds it to the list of tasks that are ready to run.
+ * @param[in] task: The task stucture which will store the task related infomation.
+ * @param[in] name: A descriptive name for the task.
+ * @param[in] stack_size: The size of the task stack specified as the variables the stack can hold.
+ * @param[in] priority: The priority at which the task should run.
+ * @param[in] func: The task entry function.
+ * @param[in] thctx: The pointer that will be used as the parameter for the task being created.
+ * @return pdPASS: The task was successfully created and added to a ready list.
+ * @return other error code defined in the file errors.h.
+ * @note For the task name, please do not use "rtw_little_wifi_mcu_thread", "rtw_check_in_req_state_thread",
+ "rtw_TDMA_change_state_thread", "xmit_thread", "recv_thread", "rtw_recv_tasklet", "rtw_xmit_tasklet",
+ "rtw_interrupt_thread", "cmd_thread", "usb_init", "MSC_BULK_CMD" and "MSC_BULK_DATA".
+ */
int rtw_create_task(struct task_struct *task, const char *name, u32 stack_size, u32 priority, thread_func_t func, void *thctx);
+
+/**
+ * @brief This function deletes a task.
+ * @param[in] task: The task stucture which will be deleted.
+ * @return None
+ */
void rtw_delete_task(struct task_struct * task);
+
+/**
+ * @brief This function wake up a task.
+ * @param[in] task: The task stucture which will be waked up.
+ * @return None
+ */
void rtw_wakeup_task(struct task_struct *task);
+
+/**
+ * @brief This function creates a new worker thread.
+ * @param[in] worker_thread: The pointer to the worker thread stucture.
+ * @param[in] priority: The priority of the thread.
+ * @param[in] stack_size: The size of the thread stack specified as the variables the stack can hold.
+ * @param[in] event_queue_size: The queue size of events.
+ * @return SUCCESS/FAIL.
+ */
int rtw_create_worker_thread( rtw_worker_thread_t* worker_thread, u8 priority, u32 stack_size, u32 event_queue_size );
+
+/**
+ * @brief This function deletes a worker thread.
+ * @param[in] worker_thread: The pointer to the worker thread stucture to be deleted.
+ * @return SUCCESS/FAIL.
+ */
int rtw_delete_worker_thread( rtw_worker_thread_t* worker_thread );
#if 0 //TODO
@@ -332,32 +1017,136 @@
BOOLEAN rtw_cancel_delayed_work(struct delayed_work *dwork);
#endif
+/**
+ * @brief This function prints the name of the thread in DBG_INFO.
+ * @param[in] name: The name of the thread.
+ * @return None
+ */
void rtw_thread_enter(char *name);
+
+/**
+ * @brief This function exits the calling thread.
+ * @return None
+ */
void rtw_thread_exit(void);
+
+/**
+ * @brief This function gets the scheduler state of the calling thread.
+ * @return OS_SCHEDULER_NOT_STARTED
+ * @return OS_SCHEDULER_RUNNING
+ * @return OS_SCHEDULER_SUSPENDED
+ */
u8 rtw_get_scheduler_state(void);
+/*************************** End Threads *******************************/
#ifdef PLATFORM_LINUX
#define rtw_warn_on(condition) WARN_ON(condition)
#else
#define rtw_warn_on(condition) do {} while (0)
#endif
-/*********************************** Timer related *****************************************/
+/*************************** Timers *******************************/
+
+/**
+ * @brief This function creates a new software timer instance.
+ * @param[in] pcTimerName: A text name that is assigned to the timer.
+ * @param[in] xTimerPeriodInTicks: The timer period which is defined in tick periods.
+ * @param[in] uxAutoReload: If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ * @param[in] pvTimerID: An identifier that is assigned to the timer being created.
+ * @param[in] pxCallbackFunction: The function to call when the timer expires.
+ * @return If the timer is successfully create then a handle to the newly
+ * created timer is returned. If the timer cannot be created, then 0 is returned.
+ */
_timerHandle rtw_timerCreate( const signed char *pcTimerName,
osdepTickType xTimerPeriodInTicks,
u32 uxAutoReload,
void * pvTimerID,
TIMER_FUN pxCallbackFunction );
-u32 rtw_timerDelete( _timerHandle xTimer,
- osdepTickType xBlockTime );
+
+/**
+ * @brief This function deletes a timer that was previously created using rtw_timerCreate.
+ * @param[in] xTimer: The handle of the timer being deleted.
+ * @param[in] xBlockTime: Specifies th etime, in ticks, that the calling task should be held in the Blocked
+ * State to wait for the delete command to be successfully sent to the timer command queue,
+ * should the queue already be full when rtw_timerDelete was called.
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.
+ */
+u32 rtw_timerDelete( _timerHandle xTimer, osdepTickType xBlockTime );
+
+/**
+ * @brief This function queries a timer to see if it is active or dormant.
+ * @param[in] xTimer: The timer being queried.
+ * @return pdFALSE will be returned if the timer is dormant. A value other than
+ * pdFALSE will be returned if the timer is active.
+ * @note A timer will be dormant if:
+ * 1) It has been created but not started, or
+ * 2) It is an expired one-shot timer that has not been restarted.
+ */
u32 rtw_timerIsTimerActive( _timerHandle xTimer );
-u32 rtw_timerStop( _timerHandle xTimer,
- osdepTickType xBlockTime );
+
+/**
+ * @brief This function stops a timer that was previously started.
+ * @param[in] xTimer: The handle of the timer being stopped.
+ * @param[in] xBlockTime: Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * rtw_timerStop() was called.
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.
+ */
+u32 rtw_timerStop( _timerHandle xTimer, osdepTickType xBlockTime );
+
+/**
+ * @brief This function changes the period of a timer that was previously created.
+ * @param[in] xTimer: The handle of the timer that is having its period changed.
+ * @param[in] xNewPeriod: The new period for xTimer.
+ * @param[in] xBlockTime: Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when rtw_timerChangePeriod() was called.
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue. When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.
+ */
u32 rtw_timerChangePeriod( _timerHandle xTimer,
osdepTickType xNewPeriod,
osdepTickType xBlockTime );
-/*********************************** OSDEP API end *****************************************/
+void *rtw_timerGetID( _timerHandle xTimer );
+
+u32 rtw_timerStart( _timerHandle xTimer, osdepTickType xBlockTime );
+
+u32 rtw_timerStartFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+u32 rtw_timerStopFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+u32 rtw_timerResetFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+u32 rtw_timerChangePeriodFromISR( _timerHandle xTimer,
+ osdepTickType xNewPeriod,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+u32 rtw_timerReset( _timerHandle xTimer,
+ osdepTickType xBlockTime );
+
+
+/*************************** End Timers *******************************/
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr)))
@@ -424,6 +1213,8 @@
return i;
}
+#define rtw_min(a, b) ((a > b) ? b : a)
+
/* Macros for handling unaligned memory accesses */
#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
@@ -518,6 +1309,8 @@
void (*rtw_exit_critical_bh)(_lock *plock, _irqL *pirqL);
int (*rtw_enter_critical_mutex)(_mutex *pmutex, _irqL *pirqL);
void (*rtw_exit_critical_mutex)(_mutex *pmutex, _irqL *pirqL);
+ void (*rtw_cpu_lock)(void);
+ void (*rtw_cpu_unlock)(void);
void (*rtw_spinlock_init)(_lock *plock);
void (*rtw_spinlock_free)(_lock *plock);
void (*rtw_spin_lock)(_lock *plock);
@@ -576,16 +1369,36 @@
u32 (*rtw_timerChangePeriod)( _timerHandle xTimer,
osdepTickType xNewPeriod,
osdepTickType xBlockTime );
+ void* (*rtw_timerGetID)( _timerHandle xTimer );
+ u32 (*rtw_timerStart)( _timerHandle xTimer,
+ osdepTickType xBlockTime );
+ u32 (*rtw_timerStartFromISR)( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+ u32 (*rtw_timerStopFromISR)( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+ u32 (*rtw_timerResetFromISR)( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+ u32 (*rtw_timerChangePeriodFromISR)( _timerHandle xTimer,
+ osdepTickType xNewPeriod,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken );
+
+ u32 (*rtw_timerReset)( _timerHandle xTimer,
+ osdepTickType xBlockTime );
void (*rtw_acquire_wakelock)(void);
void (*rtw_release_wakelock)(void);
void (*rtw_wakelock_timeout)(u32 timeoutMs);
u8 (*rtw_get_scheduler_state)(void);
};
-/*********************************** OSDEP API end *****************************************/
#ifdef __cplusplus
}
#endif
+/*\@}*/
+
#endif //#ifndef __OSDEP_SERVICE_H_
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c Thu Nov 08 11:46:34 2018 +0000
@@ -5,6 +5,10 @@
******************************************************************************/
#include <osdep_service.h>
+#if CONFIG_USE_TCM_HEAP
+#include "tcm_heap.h"
+#endif
+
#define OSDEP_DBG(x, ...) do {} while(0)
extern struct osdep_service_ops osdep_service;
@@ -53,7 +57,7 @@
u32 rtw_atoi(u8* s)
{
int num=0,flag=0;
- size_t i;
+ int i;
for(i=0;i<=strlen((char *)s);i++)
{
@@ -70,8 +74,10 @@
return(num);
}
+#if CONFIG_USE_TCM_HEAP
void *tcm_heap_malloc(int size);
void *tcm_heap_calloc(int size);
+#endif
u8* _rtw_vmalloc(u32 sz)
{
u8 *pbuf = NULL;
@@ -202,11 +208,10 @@
return;
}
else{
- if(flag == MEM_MONITOR_FLAG_WPAS) {
+ if(flag == MEM_MONITOR_FLAG_WPAS)
DBG_INFO("Alloc memory at %p with size of %d", ptr, size);
- } else {
+ else
DBG_INFO("Alloc memory at %p with size of %d", ptr, size);
- }
}
#if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK
mem_entry = (struct mem_entry *) _rtw_malloc(sizeof(struct mem_entry));
@@ -608,6 +613,22 @@
OSDEP_DBG("Not implement osdep service: rtw_exit_critical_mutex");
}
+void rtw_cpu_lock(void)
+{
+ if(osdep_service.rtw_cpu_lock)
+ osdep_service.rtw_cpu_lock();
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_cpu_lock");
+}
+
+void rtw_cpu_unlock(void)
+{
+ if(osdep_service.rtw_cpu_unlock)
+ osdep_service.rtw_cpu_unlock();
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_cpu_unlock");
+}
+
void rtw_init_queue(_queue *pqueue)
{
rtw_init_listhead(&(pqueue->queue));
@@ -1159,6 +1180,83 @@
return 0;
}
+void *rtw_timerGetID( _timerHandle xTimer )
+{
+ if(osdep_service.rtw_timerGetID)
+ return osdep_service.rtw_timerGetID(xTimer);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerGetID");
+
+ return NULL;
+}
+
+u32 rtw_timerStart( _timerHandle xTimer, osdepTickType xBlockTime )
+{
+ if(osdep_service.rtw_timerStart)
+ return osdep_service.rtw_timerStart(xTimer, xBlockTime);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerStart");
+
+ return 0;
+}
+
+u32 rtw_timerStartFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken )
+{
+ if(osdep_service.rtw_timerStartFromISR)
+ return osdep_service.rtw_timerStartFromISR(xTimer, pxHigherPriorityTaskWoken);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerStartFromISR");
+
+ return 0;
+}
+
+u32 rtw_timerStopFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken )
+{
+ if(osdep_service.rtw_timerStopFromISR)
+ return osdep_service.rtw_timerStopFromISR(xTimer, pxHigherPriorityTaskWoken);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerStopFromISR");
+
+ return 0;
+}
+
+u32 rtw_timerResetFromISR( _timerHandle xTimer,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken )
+{
+ if(osdep_service.rtw_timerResetFromISR)
+ return osdep_service.rtw_timerResetFromISR(xTimer, pxHigherPriorityTaskWoken);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerResetFromISR");
+
+ return 0;
+}
+
+u32 rtw_timerChangePeriodFromISR( _timerHandle xTimer,
+ osdepTickType xNewPeriod,
+ osdepBASE_TYPE *pxHigherPriorityTaskWoken )
+{
+ if(osdep_service.rtw_timerChangePeriodFromISR)
+ return osdep_service.rtw_timerChangePeriodFromISR(xTimer, xNewPeriod, pxHigherPriorityTaskWoken);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerChangePeriodFromISR");
+
+ return 0;
+}
+
+u32 rtw_timerReset( _timerHandle xTimer,
+ osdepTickType xBlockTime )
+{
+ if(osdep_service.rtw_timerReset)
+ return osdep_service.rtw_timerReset(xTimer, xBlockTime);
+ else
+ OSDEP_DBG("Not implement osdep service: rtw_timerReset");
+
+ return 0;
+}
+
+
#if 0 //TODO
void rtw_init_delayed_work(struct delayed_work *dwork, work_func_t func, const char *name)
{
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c Thu Nov 08 11:46:34 2018 +0000
@@ -13,7 +13,7 @@
#define ROUND_UP2(x, pad) (((x) + ((pad) - 1)) & ~((pad) - 1))
-#define TCM_HEAP_SIZE (40*1024)
+#define TCM_HEAP_SIZE (40*1024)
static struct Heap g_tcm_heap;
@@ -27,9 +27,9 @@
static int g_heap_inited=0;
static _lock tcm_lock;
-#ifdef PLATFORM_FREERTOS
+#if defined(PLATFORM_FREERTOS)
extern void vPortSetExtFree( void (*free)( void *p ), uint32_t upper, uint32_t lower );
-#else
+#elif defined(PLATFORM_CMSIS_RTOS)
extern void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower );
#endif
void tcm_heap_init(void)
@@ -52,7 +52,7 @@
#if defined(PLATFORM_FREERTOS)
// let RTOS know how to free memory if using as task stack
vPortSetExtFree(tcm_heap_free, 0x20000000, 0x1fff0000);
-#elif defined (PLATFORM_CMSIS_RTOS)
+#elif defined(PLATFORM_CMSIS_RTOS)
rtw_set_mfree_ext(tcm_heap_free, 0x20000000, 0x1fff0000);
#endif
}
@@ -67,7 +67,7 @@
chunk;
prev = chunk, chunk = chunk->next)
{
- printf(" prev %p, chunk %p, size %d \n\r", prev, chunk, chunk->size);
+ printf(" prev %x, chunk %x, size %d \n\r", prev, chunk, chunk->size);
}
printf("--------------\n\r");
}
@@ -246,10 +246,20 @@
*/
void *tcm_heap_malloc(int size)
{
+#if defined(PLATFORM_CMSIS_RTOS)
+ int64_t *mem;
+ // Make sure that block is 8-byte aligned
+ size = (size + 7U) & ~((uint32_t)7U);
+ size += sizeof(int64_t);
+ mem = (int64_t *)tcm_heap_allocmem(size);
+#else
int *mem;
+ size += sizeof(int);
+ mem = (int*)tcm_heap_allocmem(size);
+#endif
- size += sizeof(int);
- if ((mem = (int*)tcm_heap_allocmem(size))){
+
+ if (mem){
*mem++ = size;
}
@@ -262,8 +272,8 @@
void *tcm_heap_calloc(int size)
{
void *mem;
-
- if ((mem = tcm_heap_malloc(size)))
+ mem = tcm_heap_malloc(size);
+ if (mem)
memset(mem, 0, size);
return mem;
@@ -284,7 +294,11 @@
*/
void tcm_heap_free(void *mem)
{
+#if defined(PLATFORM_CMSIS_RTOS)
+ int64_t *_mem = (int64_t *)mem;
+#else
int *_mem = (int *)mem;
+#endif
if (_mem)
{
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h Thu Nov 08 11:46:34 2018 +0000
@@ -45,7 +45,8 @@
typedef uint32_t ADC_DBG_LVL;
typedef uint32_t * PADC_DBG_LVL;
-#if defined (CONFIG_DEBUG_LOG) && defined (CONFIG_DEBUG_LOG_ADC_HAL)
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_ADC_HAL
#define DBG_8195A_ADC(...) do{ \
_DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
@@ -63,6 +64,7 @@
#define DBG_8195A_ADC(...)
#define DBG_8195A_ADC_LVL(...)
#endif
+#endif
//================ ADC HAL Related Enumeration ==================
@@ -213,14 +215,10 @@
// ADC user callback structure
typedef struct _SAL_ADC_USER_CB_ {
- PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback
- PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback
PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback
- PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback
PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback
- PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback
- PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback
+ PSAL_ADC_USERCB_ADPT pIDMARXCCB; //ADC Error Callback
PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback
PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback
}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
@@ -229,7 +227,7 @@
typedef struct _SAL_ADC_TRANSFER_BUF_ {
u32 DataLen; //ADC Transmfer Length
u32 *pDataBuf; //ADC Transfer Buffer Pointer
- u32 RSVD; //
+ u16 *pUserDataBuf; //
}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
typedef struct _SAL_ADC_DMA_USER_DEF_ {
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_common.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,17 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_COMMON_H_ +#define _HAL_COMMON_H_ + +//================= Function Prototype START =================== +HAL_Status HalCommonInit(void); +//================= Function Prototype END =================== + +#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h Thu Nov 08 11:46:34 2018 +0000
@@ -228,14 +228,9 @@
typedef struct _SAL_DAC_USER_CB_ {
PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback
PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback
- PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback
- PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback
- PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback
PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback
PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback
PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback
- PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback
- PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback
}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
// DAC Transmit Buffer
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h Thu Nov 08 11:46:34 2018 +0000 @@ -16,10 +16,12 @@ _LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage); extern u32 HALEFUSEOneByteReadRAM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage); extern u32 HALEFUSEOneByteWriteRAM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage); +u32 HALOneByteWriteRAM(IN u32 CtrlSetting,IN u16 Addr,IN u8 Data,IN u8 L25OutVoltage); #define EFUSERead8 HALEFUSEOneByteReadRAM #define EFUSEWrite8 HALEFUSEOneByteWriteRAM #define L25EOUTVOLTAGE 7 +#define DISABLE 0 #endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h Thu Nov 08 11:46:34 2018 +0000
@@ -308,25 +308,26 @@
I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated
I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK,
//but there are data in slave TX FIFO
- I2C_ERR_MST_A_NACK = 0x12,
- I2C_ERR_MST_D_NACK = 0x13,
- I2C_ERR_USER_REG_TO = 0x20,
+ I2C_ERR_MST_A_NACK = 0x20,
+ I2C_ERR_MST_D_NACK = 0x40,
+ I2C_ERR_USER_REG_TO = 0x80,
- I2C_ERR_RX_CMD_TO = 0x21,
- I2C_ERR_RX_FF_TO = 0x22,
- I2C_ERR_TX_CMD_TO = 0x23,
- I2C_ERR_TX_FF_TO = 0x24,
+ I2C_ERR_RX_CMD_TO = 0x100,
+ I2C_ERR_RX_FF_TO = 0x200,
+ I2C_ERR_TX_CMD_TO = 0x400,
+ I2C_ERR_TX_FF_TO = 0x800,
- I2C_ERR_TX_ADD_TO = 0x25,
- I2C_ERR_RX_ADD_TO = 0x26,
+ I2C_ERR_TX_ADD_TO = 0x1000,
+ I2C_ERR_RX_ADD_TO = 0x2000,
};
typedef uint32_t I2C_ERR_TYPE;
typedef uint32_t *PI2C_ERR_TYPE;
// I2C Time Out type
-#define I2C_TIMEOOUT_DISABLE 0x00
-#define I2C_TIMEOOUT_ENDLESS 0xFFFFFFFF
-
+enum _I2C_TIMEOUT_TYPE_ {
+ I2C_TIMEOUT_DISABLE = 0x00,
+ I2C_TIMEOUT_ENDLESS = 0xFFFFFFFF,
+};
typedef uint32_t I2C_TIMEOUT_TYPE;
typedef uint32_t *PI2C_TIMEOUT_TYPE;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2s.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,347 @@
+/*
+ * Routines to access hardware
+ *
+ * Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ * This module is a confidential and proprietary property of RealTek and
+ * possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_I2S_H_
+#define _HAL_I2S_H_
+
+#include "rtl8195a_i2s.h"
+
+/* User Define Flags */
+
+#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID
+
+/**********************************************************************/
+/* I2S HAL initial data structure */
+typedef struct _HAL_I2S_INIT_DAT_ {
+ u8 I2SIdx; /*I2S index used*/
+ u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/
+ u8 I2SMaster; /*I2S Master or Slave mode*/
+ u8 I2SWordLen; /*I2S Word length 16 or 24bits*/
+
+ u8 I2SChNum; /*I2S Channel number mono or stereo*/
+ u8 I2SPageNum; /*I2S Page Number 2~4*/
+ u16 I2SPageSize; /*I2S page Size 1~4096 word*/
+
+ u8 *I2STxData; /*I2S Tx data pointer*/
+
+ u8 *I2SRxData; /*I2S Rx data pointer*/
+
+ u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
+ u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */
+
+ u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
+ u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/
+
+ u16 I2STxIdx; /*I2S TX page index */
+ u16 I2SRxIdx; /*I2S RX page index */
+
+ u16 I2SHWTxIdx; /*I2S HW TX page index */
+ u16 I2SHWRxIdx; /*I2S HW RX page index */
+
+
+ u16 I2SRate; /*I2S sample rate*/
+ u8 I2STRxAct; /*I2S tx rx act*/
+}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
+
+/**********************************************************************/
+/* I2S Data Structures */
+/* I2S Module Selection */
+typedef enum _I2S_MODULE_SEL_ {
+ I2S0_SEL = 0x0,
+ I2S1_SEL = 0x1,
+}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
+/*
+typedef struct _HAL_I2S_ADAPTER_ {
+ u32 Enable:1;
+ I2S_CTL_REG I2sCtl;
+ I2S_SETTING_REG I2sSetting;
+ u32 abc;
+ u8 I2sIndex;
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+*/
+/* I2S HAL Operations */
+typedef struct _HAL_I2S_OP_ {
+ RTK_STATUS (*HalI2SInit) (VOID *Data);
+ RTK_STATUS (*HalI2SDeInit) (VOID *Data);
+ RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff);
+ RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff);
+ RTK_STATUS (*HalI2SEnable) (VOID *Data);
+ RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data);
+ u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg);
+ RTK_STATUS (*HalI2SSetRate) (VOID *Data);
+ RTK_STATUS (*HalI2SSetWordLen) (VOID *Data);
+ RTK_STATUS (*HalI2SSetChNum) (VOID *Data);
+ RTK_STATUS (*HalI2SSetPageNum) (VOID *Data);
+ RTK_STATUS (*HalI2SSetPageSize) (VOID *Data);
+
+ RTK_STATUS (*HalI2SClrIntr) (VOID *Data);
+ RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data);
+ RTK_STATUS (*HalI2SDMACtrl) (VOID *Data);
+/*
+ VOID (*HalI2sOnOff)(VOID *Data);
+ BOOL (*HalI2sInit)(VOID *Data);
+ BOOL (*HalI2sSetting)(VOID *Data);
+ BOOL (*HalI2sEn)(VOID *Data);
+ BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
+ BOOL (*HalI2sDumpReg)(VOID *Data);
+ BOOL (*HalI2s)(VOID *Data);
+*/
+}HAL_I2S_OP, *PHAL_I2S_OP;
+
+
+/**********************************************************************/
+
+/* I2S Pinmux Selection */
+#if 0
+typedef enum _I2S0_PINMUX_ {
+ I2S0_TO_S0 = 0x0,
+ I2S0_TO_S1 = 0x1,
+ I2S0_TO_S2 = 0x2,
+}I2S0_PINMUX, *PI2S0_PINMUX;
+
+typedef enum _I2S1_PINMUX_ {
+ I2S1_TO_S0 = 0x0,
+ I2S1_TO_S1 = 0x1,
+}I2S1_PINMUX, *PI2S1_PINMUX;
+#endif
+
+typedef enum _I2S_PINMUX_ {
+ I2S_S0 = 0,
+ I2S_S1 = 1,
+ I2S_S2 = 2,
+ I2S_S3 = 3
+}I2S_PINMUX, *PI2S_PINMUX;
+
+
+/* I2S Module Status */
+typedef enum _I2S_MODULE_STATUS_ {
+ I2S_DISABLE = 0x0,
+ I2S_ENABLE = 0x1,
+}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
+
+
+/* I2S Device Status */
+typedef enum _I2S_Device_STATUS_ {
+ I2S_STS_UNINITIAL = 0x00,
+ I2S_STS_INITIALIZED = 0x01,
+ I2S_STS_IDLE = 0x02,
+
+ I2S_STS_TX_READY = 0x03,
+ I2S_STS_TX_ING = 0x04,
+
+ I2S_STS_RX_READY = 0x05,
+ I2S_STS_RX_ING = 0x06,
+
+ I2S_STS_TRX_READY = 0x07,
+ I2S_STS_TRX_ING = 0x08,
+
+ I2S_STS_ERROR = 0x09,
+}I2S_Device_STATUS, *PI2S_Device_STATUS;
+
+
+/* I2S Feature Status */
+typedef enum _I2S_FEATURE_STATUS_{
+ I2S_FEATURE_DISABLED = 0,
+ I2S_FEATURE_ENABLED = 1,
+}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
+
+/* I2S Device Mode */
+typedef enum _I2S_DEV_MODE_ {
+ I2S_MASTER_MODE = 0x0,
+ I2S_SLAVE_MODE = 0x1
+}I2S_DEV_MODE, *PI2S_DEV_MODE;
+
+/* I2S Word Length */
+typedef enum _I2S_WORD_LEN_ {
+ I2S_WL_16 = 0x0,
+ I2S_WL_24 = 0x1,
+}I2S_WORD_LEN, *PI2S_WORD_LEN;
+
+/* I2S Bus Transmit/Receive */
+typedef enum _I2S_DIRECTION_ {
+ I2S_ONLY_RX = 0x0,
+ I2S_ONLY_TX = 0x1,
+ I2S_TXRX = 0x2
+}I2S_DIRECTION, *PI2S_DIRECTION;
+
+/* I2S Channel number */
+typedef enum _I2S_CH_NUM_ {
+ I2S_CH_STEREO = 0x0,
+ I2S_CH_RSVD = 0x1,
+ I2S_CH_MONO = 0x2
+}I2S_CH_NUM, *PI2S_CH_NUM;
+
+/* I2S Page number */
+typedef enum _I2S_PAGE_NUM_ {
+ I2S_1PAGE = 0x0,
+ I2S_2PAGE = 0x1,
+ I2S_3PAGE = 0x2,
+ I2S_4PAGE = 0x3
+}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
+
+/* I2S Sample rate*/
+typedef enum _I2S_SAMPLE_RATE_ {
+ I2S_SR_8KHZ = 0x00, // /12
+ I2S_SR_16KHZ = 0x01, // /6
+ I2S_SR_24KHZ = 0x02, // /4
+ I2S_SR_32KHZ = 0x03, // /3
+ I2S_SR_48KHZ = 0x05, // /2
+ I2S_SR_96KHZ = 0x06, // x1, base 96kHz
+ I2S_SR_7p35KHZ = 0x10,
+ I2S_SR_14p7KHZ = 0x11,
+ I2S_SR_22p05KHZ = 0x12,
+ I2S_SR_29p4KHZ = 0x13,
+ I2S_SR_44p1KHZ = 0x15,
+ I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz
+}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
+
+/* I2S TX interrupt mask/status */
+typedef enum _I2S_TX_IMR_ {
+ I2S_TX_INT_PAGE0_OK = (1<<0),
+ I2S_TX_INT_PAGE1_OK = (1<<1),
+ I2S_TX_INT_PAGE2_OK = (1<<2),
+ I2S_TX_INT_PAGE3_OK = (1<<3),
+ I2S_TX_INT_FULL = (1<<4),
+ I2S_TX_INT_EMPTY = (1<<5)
+} I2S_TX_IMR, *PI2S_TX_IMR;
+
+/* I2S RX interrupt mask/status */
+typedef enum _I2S_RX_IMR_ {
+ I2S_RX_INT_PAGE0_OK = (1<<0),
+ I2S_RX_INT_PAGE1_OK = (1<<1),
+ I2S_RX_INT_PAGE2_OK = (1<<2),
+ I2S_RX_INT_PAGE3_OK = (1<<3),
+ I2S_RX_INT_EMPTY = (1<<4),
+ I2S_RX_INT_FULL = (1<<5)
+} I2S_RX_IMR, *PI2S_RX_IMR;
+
+/* I2S User Callbacks */
+typedef struct _SAL_I2S_USER_CB_{
+ VOID (*TXCB) (VOID *Data);
+ VOID (*TXCCB) (VOID *Data);
+ VOID (*RXCB) (VOID *Data);
+ VOID (*RXCCB) (VOID *Data);
+ VOID (*RDREQCB) (VOID *Data);
+ VOID (*ERRCB) (VOID *Data);
+ VOID (*GENCALLCB) (VOID *Data);
+}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
+
+typedef struct _I2S_USER_CB_{
+ VOID (*TxCCB)(uint32_t id, char *pbuf);
+ u32 TxCBId;
+ VOID (*RxCCB)(uint32_t id, char *pbuf);
+ u32 RxCBId;
+}I2S_USER_CB,*PI2S_USER_CB;
+
+/* Software API Level I2S Handler */
+typedef struct _HAL_I2S_ADAPTER_{
+ u8 DevNum; //I2S device number
+ u8 PinMux; //I2S pin mux seletion
+ u8 RSVD0; //Reserved
+ volatile u8 DevSts; //I2S device status
+
+ u32 RSVD2; //Reserved
+ u32 I2SExd; //I2S extended options:
+ //bit 0: I2C RESTART supported,
+ // 0 for NOT supported,
+ // 1 for supported
+ //bit 1: I2C General Call supported
+ // 0 for NOT supported,
+ // 1 for supported
+ //bit 2: I2C START Byte supported
+ // 0 for NOT supported,
+ // 1 for supported
+ //bit 3: I2C Slave-No-Ack
+ // supported
+ // 0 for NOT supported,
+ // 1 for supported
+ //bit 4: I2C bus loading,
+ // 0 for 100pf,
+ // 1 for 400pf
+ //bit 5: I2C slave ack to General
+ // Call
+ //bit 6: I2C User register address
+ //bit 7: I2C 2-Byte User register
+ // address
+ //bit 31~bit 8: Reserved
+ u32 ErrType; //
+ u32 TimeOut; //I2S IO Timeout count
+
+ PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct
+ I2S_USER_CB UserCB; //Pointer to I2S User Callback
+ IRQ_HANDLE IrqHandle; // Irq Handler
+
+ u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page
+ u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+
+typedef struct _HAL_I2S_DEF_SETTING_{
+ u8 I2SMaster; // Master or Slave mode
+ u8 DevSts; //I2S device status
+ u8 I2SChNum; //I2S Channel number mono or stereo
+ u8 I2SPageNum; //I2S Page number 2~4
+ u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx
+ u8 I2SWordLen; //I2S Word length 16bit or 24bit
+ u16 I2SPageSize; //I2S Page size 1~4096 word
+
+ u16 I2SRate; //I2S sample rate 8k ~ 96khz
+
+ u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
+ u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
+}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
+
+
+
+/**********************************************************************/
+HAL_Status
+RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting);
+
+HAL_Status
+RtkI2SInit(IN VOID *Data);
+
+HAL_Status
+RtkI2SDeInit(IN VOID *Data);
+
+HAL_Status
+RtkI2SEnable(IN VOID *Data);
+
+HAL_Status
+RtkI2SDisable(IN VOID *Data);
+
+extern HAL_Status
+HalI2SInit( IN VOID *Data);
+
+extern VOID
+HalI2SDeInit( IN VOID *Data);
+
+extern HAL_Status
+HalI2SDisable( IN VOID *Data);
+
+extern HAL_Status
+HalI2SEnable( IN VOID *Data);
+
+
+
+
+/**********************************************************************/
+
+
+VOID I2S0ISRHandle(VOID *Data);
+VOID I2S1ISRHandle(VOID *Data);
+
+
+/**********************************************************************/
+
+VOID HalI2SOpInit(
+ IN VOID *Data
+);
+
+
+#endif
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h Thu Nov 08 11:46:34 2018 +0000
@@ -24,6 +24,19 @@
#define CHIP_ID_8710AM 0xFA
#define CHIP_ID_SIP 0xF9
#define CHIP_ID_COMBO_SIP 0xF8
+#define CHIP_ID_SIP2 0xF7
+#define CHIP_ID_MICO100 0xF1
+
+enum _HAL_RESET_REASON{
+ REASON_DEFAULT_RST = 0, /**< normal startup by power on */
+ REASON_WDT_RST, /**< hardware watch dog reset */
+ REASON_EXCEPTION_RST, /**< exception reset, GPIO status won't change */
+ REASON_SOFT_WDT_RST, /**< software watch dog reset, GPIO status won't change */
+ REASON_SOFT_RESTART, /**< software restart ,system_restart , GPIO status won't change */
+ REASON_DEEP_SLEEP_AWAKE, /**< wake up from deep-sleep */
+ REASON_EXT_SYS_RST /**< external system reset */
+};
+typedef u32 HAL_RESET_REASON;
#ifdef CONFIG_TIMER_MODULE
extern _LONG_CALL_ u32 HalDelayUs(u32 us);
@@ -43,5 +56,7 @@
extern _LONG_CALL_ROM_ SIZE_T _strlen(const char *s);
extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct);
+VOID HalSetResetCause(IN HAL_RESET_REASON reason);
+HAL_RESET_REASON HalGetResetCause(VOID);
#endif //_MISC_H_
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h Thu Nov 08 11:46:34 2018 +0000
@@ -15,6 +15,9 @@
#define _HAL_PWM_H_
#define MAX_PWM_CTRL_PIN 4
+#define MAX_GTIMER_NUM 4
+#define MAX_DEVID_TICK 1020
+
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
@@ -32,6 +35,10 @@
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
+typedef struct _HAL_PWM_GTIMER_ {
+ u32 tick_time; // the tick time for the G-timer
+ u8 reference; // map of referenced by PWM
+}HAL_PWM_TIMER, *PHAL_PWM_TIMER;
extern HAL_Status
HAL_Pwm_Init(
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h Thu Nov 08 11:46:34 2018 +0000 @@ -69,6 +69,8 @@ #define FLASH_WINBOND 3 #define FLASH_MICRON 4 #define FLASH_EON 5 +#define FLASH_GD 6 +#define FLASH_CYPRESS 7 //#define FLASH_MXIC_MX25L4006E 0 //#define FLASH_MXIC_MX25L8073E 0 @@ -82,40 +84,41 @@ #define FLASH_CMD_WRDI 0x04 //write disable #define FLASH_CMD_WRSR 0x01 //write status register #define FLASH_CMD_RDID 0x9F //read idenfication +#define FLASH_CMD_RDUID 0x4B //Read Unique ID #define FLASH_CMD_RDSR 0x05 //read status register #define FLASH_CMD_RDSFDP 0x5A //Read SFDP #define FLASH_CMD_READ 0x03 //read data #define FLASH_CMD_FREAD 0x0B //fast read data #define FLASH_CMD_PP 0x02 //Page Program -#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2 -#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2 -#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4 -#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4 -#define FLASH_CMD_DPP 0xA2 // 1-1-2 -#define FLASH_CMD_2PP 0xD2 // 1-2-2 -#define FLASH_CMD_QPP 0x32 // 1-1-4 -#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4 +#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2 +#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2 +#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4 +#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4 +#define FLASH_CMD_DPP 0xA2 // 1-1-2 +#define FLASH_CMD_2PP 0xD2 // 1-2-2 +#define FLASH_CMD_QPP 0x32 // 1-1-4 +#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4 #define FLASH_CMD_SE 0x20 //Sector Erase -#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) -#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7) -#define FLASH_CMD_DP 0xB9 //Deep Power Down -#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down +#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) +#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7) +#define FLASH_CMD_DP 0xB9 //Deep Power Down +#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down /*Micron Special command*/ -#define FLASH_CMD_DE 0xC4 -#define FLASH_CMD_4PP2 0x12 -#define FLASH_CMD_RFSR 0x70 -#define FLASH_CMD_CFSR 0x50 -#define FLASH_CMD_RNCR 0xB5 -#define FLASH_CMD_WNCR 0xB1 -#define FLASH_CMD_RVCR 0x85 -#define FLASH_CMD_WVCR 0x81 -#define FLASH_CMD_REVCR 0x65 -#define FLASH_CMD_WEVCR 0x61 -#define FLASH_CMD_REAR 0xC8 -#define FLASH_CMD_WEAR 0xC5 -#define FLASH_CMD_ENQUAD 0x35 -#define FLASH_CMD_EXQUAD 0xF5 +#define FLASH_CMD_DE 0xC4 +#define FLASH_CMD_4PP2 0x12 +#define FLASH_CMD_RFSR 0x70 +#define FLASH_CMD_CFSR 0x50 +#define FLASH_CMD_RNCR 0xB5 +#define FLASH_CMD_WNCR 0xB1 +#define FLASH_CMD_RVCR 0x85 +#define FLASH_CMD_WVCR 0x81 +#define FLASH_CMD_REVCR 0x65 +#define FLASH_CMD_WEVCR 0x61 +#define FLASH_CMD_REAR 0xC8 +#define FLASH_CMD_WEAR 0xC5 +#define FLASH_CMD_ENQUAD 0x35 +#define FLASH_CMD_EXQUAD 0xF5 /*MXIC Special command*/ #define FLASH_CMD_RDCR 0x15 //read configurate register @@ -126,6 +129,19 @@ #define FLASH_CMD_RDSCUR 0x2B // read security register #define FLASH_CMD_WRSCUR 0x2F // write security register +/*WINBOND Special command*/ +#define FLASH_CMD_GLOCK 0x7E +#define FLASH_CMD_GUNLOCK 0x98 +#define FLASH_CMD_RLOCK 0x3D +#define FLASH_CMD_SLOCK 0x36 +#define FLASH_CMD_SUNLOCK 0x39 +#define FLASH_CMD_WRSR3 0x11 +#define FLASH_CMD_RDSR3 0x15 + +/*Cypress Special command*/ +#define FLASH_CMD_RDSR4 0x07 //read status register 2 +#define FLASH_CMD_CLSR 0x30 //Clear status register 2 error bit + //#endif #if 0 #if FLASH_MXIC_MX25L4006E @@ -331,11 +347,16 @@ VOID SpicSectorEraseFlashRtl8195A(IN u32 Address); VOID SpicDieEraseFlashRtl8195A(IN u32 Address); VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect); -VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara); +VOID SpicTxCmdWithDataRtl8195A(IN u8 cmd,IN u8 DataPhaseLen,IN u8* pData,IN SPIC_INIT_PARA SpicInitPara); +VOID SpicTxCmdWithDataNoCheckRtl8195A(IN u8 cmd, IN u8 DataPhaseLen,IN u8* pData); +VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara); +VOID SpicRxCmdWithDataRtl8195A(IN u8 cmd,IN u8 DataPhaseLen, IN u8* pData,IN SPIC_INIT_PARA SpicInitPara); u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); -VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode); +u8 SpicGetFlashStatus3Rtl8195A(IN SPIC_INIT_PARA SpicInitPara); +u8 SpicGetFlashStatus4Rtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode); u32 SpicWaitWipRtl8195A(VOID); u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk); VOID SpicDisableRtl8195A(VOID); @@ -343,10 +364,18 @@ VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo); VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data, IN u8 BitMode); VOID SpicUserReadFourByteRtl8195A(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode); +VOID SpicReadUniqueIDRtl8195A(IN u8 *buff,IN u8 len); VOID SpicReadIDRtl8195A(VOID); VOID SpicSetFlashStatusRefinedRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara); VOID SpicSetExtendAddrRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara); u8 SpicGetExtendAddrRtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicSetLockModeRtl8195A(IN u8 Mode); +VOID SpicLockFlashRtl8195A(VOID); +VOID SpicUnlockFlashRtl8195A(VOID); +VOID SpicSingleLockRtl8195A(IN u32 Address); +VOID SpicSingleUnlockRtl8195A(IN u32 Address); +u8 SpicReadLockStateRtl8195A(IN u32 Address); + #if SPIC_CALIBRATION_IN_NVM VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk); VOID SpicNVMCalLoadAll(void);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h Thu Nov 08 11:46:34 2018 +0000
@@ -21,6 +21,7 @@
*/
extern u32 SSI_DBG_CONFIG;
+extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,14 +1,10 @@
-/*******************************************************************************
- *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
- * SPDX-License-Identifier: LicenseRef-PBL
- *
- * Licensed under the Permissive Binary License, Version 1.0 (the "License");
- * you may not use this file except in compliance with the License.
- *
- * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
- *
- * See the License for the specific language governing permissions and limitations under the License.
- *******************************************************************************
+/*
+ * Routines to access hardware
+ *
+ * Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ * This module is a confidential and proprietary property of RealTek and
+ * possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
@@ -44,19 +40,17 @@
u32 (*HalGetTimerId)(u32 *TimerId);
BOOL (*HalTimerInit)(VOID *Data);
u32 (*HalTimerReadCount)(u32 TimerId);
- //VOID (*HalTimerIrqEn)(u32 TimerId);
VOID (*HalTimerIrqClear)(u32 TimerId);
VOID (*HalTimerDis)(u32 TimerId);
VOID (*HalTimerEn)(u32 TimerId);
VOID (*HalTimerDumpReg)(u32 TimerId);
- //VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs);
}HAL_TIMER_OP, *PHAL_TIMER_OP;
typedef struct _HAL_TIMER_OP_EXT_ {
- PHAL_TIMER_OP phal_timer_op_rom;
- VOID (*HalTimerIrqEn)(u32 TimerId);
- VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs);
- VOID (*HalTimerSync)(u32 TimerId);
+ PHAL_TIMER_OP phal_timer_op_rom;
+ VOID (*HalTimerIrqEn)(u32 TimerId);
+ VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs);
+ VOID (*HalTimerSync)(u32 TimerId);
}HAL_TIMER_OP_EXT, *PHAL_TIMER_OP_EXT;
#ifdef CONFIG_TIMER_MODULE
@@ -108,5 +102,6 @@
HalTimerDeInit(
void *Data
);
+
#endif // #ifdef CONFIG_RELEASE_BUILD_LIBRARIES
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h Thu Nov 08 11:46:34 2018 +0000
@@ -28,6 +28,7 @@
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "rtl8195a_spi_flash.h"
+#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
@@ -148,11 +149,9 @@
#include "rtl8195a_trap.h"
#include "rtl8195a_clk.h"
#include "rtl8195a_misc.h"
-#include "rtl8195a_sdio.h"
#endif
-
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
@@ -198,6 +197,10 @@
#include "rtl8195a_i2c.h"
#endif
+#ifdef CONFIG_PCM_EN
+#include "hal_pcm.h"
+#include "rtl8195a_pcm.h"
+#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
@@ -226,7 +229,7 @@
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
-//#include "hal_sdio.h"
+#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,714 @@
+/*
+ * Routines to access hardware
+ *
+ * Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ * This module is a confidential and proprietary property of RealTek and
+ * possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_I2S_H_
+#define _RTL8195A_I2S_H_
+
+
+//=============== Register Bit Field Definition ====================
+// REG_I2S_CONTROL
+#define BIT_CTLX_I2S_EN BIT(0)
+#define BIT_SHIFT_CTLX_I2S_EN 0
+#define BIT_MASK_CTLX_I2S_EN 0x1
+#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
+
+#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
+#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
+#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
+#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
+
+#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
+#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
+#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
+#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
+
+#define BIT_CTLX_I2S_WL BIT(6)
+#define BIT_SHIFT_CTLX_I2S_WL 6
+#define BIT_MASK_CTLX_I2S_WL 0x1
+#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
+
+#define BIT_CTLX_I2S_LRSWAP BIT(10)
+#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
+#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
+#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
+
+#define BIT_CTLX_I2S_SCK_INV BIT(11)
+#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
+#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
+#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
+
+#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
+#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
+#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
+#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
+
+#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
+#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
+#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
+#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
+
+#define BIT_CTLX_I2S_CLK_SRC BIT(30)
+#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
+#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
+#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
+
+#define BIT_CTLX_I2S_SW_RSTN BIT(31)
+#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
+#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
+#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
+
+// REG_I2S_SETTING
+#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
+#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
+#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
+#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
+
+#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
+#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
+#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
+#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
+
+#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
+#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
+#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
+#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
+
+// i2s trx page own bit
+#define BIT_PAGE_I2S_OWN_BIT BIT(31)
+#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
+#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
+#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
+
+//=============== Register Address Definition ====================
+#define REG_I2S_PAGE_OWN_OFF 0x004
+
+#define REG_I2S_CTL 0x000
+#define REG_I2S_TX_PAGE_PTR 0x004
+#define REG_I2S_RX_PAGE_PTR 0x008
+#define REG_I2S_SETTING 0x00C
+
+#define REG_I2S_TX_MASK_INT 0x010
+#define REG_I2S_TX_STATUS_INT 0x014
+#define REG_I2S_RX_MASK_INT 0x018
+#define REG_I2S_RX_STATUS_INT 0x01c
+
+
+#define REG_I2S_TX_PAGE0_OWN 0x020
+#define REG_I2S_TX_PAGE1_OWN 0x024
+#define REG_I2S_TX_PAGE2_OWN 0x028
+#define REG_I2S_TX_PAGE3_OWN 0x02C
+#define REG_I2S_RX_PAGE0_OWN 0x030
+#define REG_I2S_RX_PAGE1_OWN 0x034
+#define REG_I2S_RX_PAGE2_OWN 0x038
+#define REG_I2S_RX_PAGE3_OWN 0x03C
+
+/*I2S Essential Functions and Macros*/
+VOID
+HalI2SWrite32(
+ IN u8 I2SIdx,
+ IN u8 I2SReg,
+ IN u32 I2SVal
+);
+
+u32
+HalI2SRead32(
+ IN u8 I2SIdx,
+ IN u8 I2SReg
+);
+
+/*
+#define HAL_I2SX_READ32(I2sIndex, addr) \
+ HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
+#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
+ HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
+*/
+
+#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
+#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
+
+/* I2S debug output*/
+#define I2S_PREFIX "RTL8195A[i2s]: "
+#define I2S_PREFIX_LVL " [i2s_DBG]: "
+
+typedef enum _I2S_DBG_LVL_ {
+ HAL_I2S_LVL = 0x01,
+ SAL_I2S_LVL = 0x02,
+ VERI_I2S_LVL = 0x03,
+}I2S_DBG_LVL,*PI2S_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_I2S_HAL
+
+ #define DBG_8195A_I2S(...) do{ \
+ _DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
+ }while(0)
+
+
+ #define I2SDBGLVL 0xFF
+ #define DBG_8195A_I2S_LVL(LVL,...) do{\
+ if (LVL&I2SDBGLVL){\
+ _DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
+ }\
+ }while(0)
+#else
+ #define DBG_I2S_LOG_PERD 100
+ #define DBG_8195A_I2S(...)
+ #define DBG_8195A_I2S_LVL(...)
+#endif
+#else
+ #define DBG_I2S_LOG_PERD 100
+ #define DBG_8195A_I2S(...)
+ #define DBG_8195A_I2S_LVL(...)
+#endif
+
+/*
+#define REG_I2S_PAGE_OWN_OFF 0x004
+#define REG_I2S_CTL 0x000
+#define REG_I2S_TX_PAGE_PTR 0x004
+#define REG_I2S_RX_PAGE_PTR 0x008
+#define REG_I2S_SETTING 0x00C
+
+#define REG_I2S_TX_MASK_INT 0x010
+#define REG_I2S_TX_STATUS_INT 0x014
+#define REG_I2S_RX_MASK_INT 0x018
+#define REG_I2S_RX_STATUS_INT 0x01c
+
+
+
+#define REG_I2S_TX_PAGE0_OWN 0x020
+#define REG_I2S_TX_PAGE1_OWN 0x024
+#define REG_I2S_TX_PAGE2_OWN 0x028
+#define REG_I2S_TX_PAGE3_OWN 0x02C
+#define REG_I2S_RX_PAGE0_OWN 0x030
+#define REG_I2S_RX_PAGE1_OWN 0x034
+#define REG_I2S_RX_PAGE2_OWN 0x038
+#define REG_I2S_RX_PAGE3_OWN 0x03C
+*/
+/* template
+#define BIT_SHIFT_CTLX_ 7
+#define BIT_MASK_CTLX_ 0x1
+#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
+#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
+*//*
+#define BIT_SHIFT_CTLX_IIS_EN 0
+#define BIT_MASK_CTLX_IIS_EN 0x1
+#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
+#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
+
+#define BIT_SHIFT_CTLX_TRX 1
+#define BIT_MASK_CTLX_TRX 0x3
+#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
+#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
+
+#define BIT_SHIFT_CTLX_CH_NUM 3
+#define BIT_MASK_CTLX_CH_NUM 0x3
+#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
+#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
+
+#define BIT_SHIFT_CTLX_EDGE_SW 5
+#define BIT_MASK_CTLX_EDGE_SW 0x1
+#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
+#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
+
+#define BIT_SHIFT_CTLX_WL 6
+#define BIT_MASK_CTLX_WL 0x1
+#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
+#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
+
+#define BIT_SHIFT_CTLX_LOOP_BACK 7
+#define BIT_MASK_CTLX_LOOP_BACK 0x1
+#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
+#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
+
+
+#define BIT_SHIFT_CTLX_FORMAT 8
+#define BIT_MASK_CTLX_FORMAT 0x3
+#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
+#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
+
+#define BIT_SHIFT_CTLX_LRSWAP 10
+#define BIT_MASK_CTLX_LRSWAP 0x1
+#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
+#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
+
+#define BIT_SHIFT_CTLX_SCK_INV 11
+#define BIT_MASK_CTLX_SCK_INV 0x1
+#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
+#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
+
+#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
+#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
+#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
+#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
+
+
+#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
+#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
+#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
+#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
+
+#define BIT_SHIFT_CTLX_SLAVE_SEL 29
+#define BIT_MASK_CTLX_SLAVE_SEL 0x1
+#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
+#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
+
+
+#define BIT_SHIFT_CTLX_CLK_SRC 30
+#define BIT_MASK_CTLX_CLK_SRC 0x1
+#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
+#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
+
+
+
+#define BIT_SHIFT_CTLX_SW_RSTN 31
+#define BIT_MASK_CTLX_SW_RSTN 0x1
+#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
+#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
+
+
+#define BIT_SHIFT_SETTING_PAGE_SZ 0
+#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
+#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
+#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
+
+#define BIT_SHIFT_SETTING_PAGE_NUM 12
+#define BIT_MASK_SETTING_PAGE_NUM 0x3
+#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
+#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
+
+#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
+#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
+#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
+#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
+*/
+
+typedef enum _I2S_CTL_FORMAT {
+ FormatI2s = 0x00,
+ FormatLeftJustified = 0x01,
+ FormatRightJustified = 0x02
+}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
+
+typedef enum _I2S_CTL_CHNUM {
+ ChannelStereo = 0x00,
+ Channel5p1 = 0x01,
+ ChannelMono = 0x02
+}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
+
+typedef enum _I2S_CTL_TRX_ACT {
+ RxOnly = 0x00,
+ TxOnly = 0x01,
+ TXRX = 0x02
+}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
+/*
+typedef struct _I2S_CTL_REG_ {
+ I2S_CTL_FORMAT Format;
+ I2S_CTL_CHNUM ChNum;
+ I2S_CTL_TRX_ACT TrxAct;
+
+ u32 I2s_En :1; // Bit 0
+ u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
+ u32 EdgeSw :1; // Bit 5 Edge switch
+ u32 WordLength :1; // Bit 6
+ u32 LoopBack :1; // Bit 7
+ u32 Rsvd8to9 :2; // Bit 8-9 is Format
+ u32 DacLrSwap :1; // Bit 10
+ u32 SckInv :1; // Bit 11
+ u32 EndianSwap :1; // Bit 12
+ u32 Rsvd13to14 :2; // Bit 11-14
+ u32 DebugSwitch :2; // Bit 15-16
+ u32 Rsvd17to28 :12; // Bit 17-28
+ u32 SlaveMode :1; // Bit 29
+ u32 SR44p1KHz :1; // Bit 30
+ u32 SwRstn :1; // Bit 31
+} I2S_CTL_REG, *PI2S_CTL_REG;
+*/
+typedef enum _I2S_SETTING_PAGE_NUM {
+ I2s1Page = 0x00,
+ I2s2Page = 0x01,
+ I2s3Page = 0x02,
+ I2s4Page = 0x03
+}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
+
+//sampling rate
+typedef enum _I2S_SETTING_SR {
+ I2sSR8K = 0x00,
+ I2sSR16K = 0x01,
+ I2sSR24K = 0x02,
+ I2sSR32K = 0x03,
+ I2sSR48K = 0x05,
+ I2sSR44p1K = 0x15,
+ I2sSR96K = 0x06,
+ I2sSR88p2K = 0x16
+}I2S_SETTING_SR, *PI2S_SETTING_SR;
+/*
+typedef struct _I2S_SETTING_REG_ {
+ I2S_SETTING_PAGE_NUM PageNum;
+ I2S_SETTING_SR SampleRate;
+
+ u32 PageSize:12; // Bit 0-11
+}I2S_SETTING_REG, *PI2S_SETTING_REG;
+
+typedef enum _I2S_TX_ISR {
+ I2sTxP0OK = 0x01,
+ I2sTxP1OK = 0x02,
+ I2sTxP2OK = 0x04,
+ I2sTxP3OK = 0x08,
+ I2sTxPageUn = 0x10,
+ I2sTxFifoEmpty = 0x20
+}I2S_TX_ISR, *PI2S_TX_ISR;
+
+typedef enum _I2S_RX_ISR {
+ I2sRxP0OK = 0x01,
+ I2sRxP1OK = 0x02,
+ I2sRxP2OK = 0x04,
+ I2sRxP3OK = 0x08,
+ I2sRxPageUn = 0x10,
+ I2sRxFifoFull = 0x20
+}I2S_RX_ISR, *PI2S_RX_ISR;
+*/
+
+/* Hal I2S function prototype*/
+RTK_STATUS
+HalI2SInitRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SInitRtl8195a_Patch(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SDeInitRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2STxRtl8195a(
+ IN VOID *Data,
+ IN u8 *pBuff
+);
+
+RTK_STATUS
+HalI2SRxRtl8195a(
+ IN VOID *Data,
+ OUT u8 *pBuff
+);
+
+RTK_STATUS
+HalI2SEnableRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SIntrCtrlRtl8195a(
+ IN VOID *Data
+);
+
+u32
+HalI2SReadRegRtl8195a(
+ IN VOID *Data,
+ IN u8 I2SReg
+);
+
+RTK_STATUS
+HalI2SSetRateRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetWordLenRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetChNumRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetPageNumRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetPageSizeRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetDirectionRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SSetDMABufRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SClrIntrRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SClrAllIntrRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SDMACtrlRtl8195a(
+ IN VOID *Data
+);
+
+u8
+HalI2SGetTxPageRtl8195a(
+ IN VOID *Data
+);
+
+u8
+HalI2SGetRxPageRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SPageSendRtl8195a(
+ IN VOID *Data,
+ IN u8 PageIdx
+);
+
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+ IN VOID *Data
+);
+
+RTK_STATUS
+HalI2SClearAllOwnBitRtl8195a(
+ IN VOID *Data
+);
+
+#ifdef CONFIG_CHIP_E_CUT
+_LONG_CALL_ RTK_STATUS
+HalI2SInitRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetRateRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetWordLenRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetChNumRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetPageNumRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetPageSizeRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetDirectionRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SSetDMABufRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ u8
+HalI2SGetTxPageRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ u8
+HalI2SGetRxPageRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SPageSendRtl8195a_V04(
+ IN VOID *Data,
+ IN u8 PageIdx
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SPageRecvRtl8195a_V04(
+ IN VOID *Data
+);
+
+_LONG_CALL_ RTK_STATUS
+HalI2SClearAllOwnBitRtl8195a_V04(
+ IN VOID *Data
+);
+
+#endif // #ifdef CONFIG_CHIP_E_CUT
+
+// HAL functions Wrapper
+static __inline VOID
+HalI2SSetRate(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetRateRtl8195a(Data);
+#else
+ HalI2SSetRateRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetWordLen(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetWordLenRtl8195a(Data);
+#else
+ HalI2SSetWordLenRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetChNum(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetChNumRtl8195a(Data);
+#else
+ HalI2SSetChNumRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetPageNum(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetPageNumRtl8195a(Data);
+#else
+ HalI2SSetPageNumRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetPageSize(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetPageSizeRtl8195a(Data);
+#else
+ HalI2SSetPageSizeRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetDirection(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetDirectionRtl8195a(Data);
+#else
+ HalI2SSetDirectionRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SSetDMABuf(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SSetDMABufRtl8195a(Data);
+#else
+ HalI2SSetDMABufRtl8195a_V04(Data);
+#endif
+}
+
+static __inline u8
+HalI2SGetTxPage(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ return HalI2SGetTxPageRtl8195a(Data);
+#else
+ return HalI2SGetTxPageRtl8195a_V04(Data);
+#endif
+}
+
+static __inline u8
+HalI2SGetRxPage(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ return HalI2SGetRxPageRtl8195a(Data);
+#else
+ return HalI2SGetRxPageRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SPageSend(
+ IN VOID *Data,
+ IN u8 PageIdx
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SPageSendRtl8195a(Data, PageIdx);
+#else
+ HalI2SPageSendRtl8195a_V04(Data, PageIdx);
+#endif
+}
+
+static __inline VOID
+HalI2SPageRecv(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SPageRecvRtl8195a(Data);
+#else
+ HalI2SPageRecvRtl8195a_V04(Data);
+#endif
+}
+
+static __inline VOID
+HalI2SClearAllOwnBit(
+ IN VOID *Data
+)
+{
+#ifndef CONFIG_CHIP_E_CUT
+ HalI2SClearAllOwnBitRtl8195a(Data);
+#else
+ HalI2SClearAllOwnBitRtl8195a_V04(Data);
+#endif
+}
+
+#endif /* _RTL8195A_I2S_H_ */
+
+
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h Thu Nov 08 11:46:34 2018 +0000
@@ -37,6 +37,10 @@
HAL_PWM_ADAPTER *pPwmAdapt
);
+extern void
+HAL_Pwm_Dinit_8195a(
+ HAL_PWM_ADAPTER *pPwmAdapt
+);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h Thu Nov 08 11:46:34 2018 +0000
@@ -13,46 +13,1028 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#ifndef MBED_RTL8195A_SDIO_H
-#define MBED_RTL8195A_SDIO_H
+
+
+#ifndef _RTL8195A_SDIO_H_
+#define _RTL8195A_SDIO_H_
+
+#include "hal_api.h"
+#include "hal_util.h"
+#if defined(CONFIG_SDIO_BOOT_SIM) || defined(CONFIG_SDIO_BOOT_ROM)
+#define SDIO_BOOT_DRIVER 1 // is this SDIO driver works for booting
+#else
+#include "osdep_api.h"
+#define SDIO_BOOT_DRIVER 0 // is this SDIO driver works for booting
+#endif
+
+#if defined(__IAR_SYSTEMS_ICC__) //for IAR SDK
+#include "platform_opts.h"
+#endif
+
+#ifndef CONFIG_INIC_EN
+#define CONFIG_INIC_EN 0
+#endif
+#if CONFIG_INIC_EN
+#define CONFIG_INIC_SKB_TX 1 //use SKB for trx to improve the throughput
+#define CONFIG_INIC_SKB_RX 1
+#endif
+
+#if defined(__IAR_SYSTEMS_ICC__) && (CONFIG_INIC_EN == 0)//for IAR SDK
+ #define SDIO_API_DEFINED 1
+#else
+ #define SDIO_API_DEFINED 0
+#endif
+
+#ifndef PRIORITIE_OFFSET //PRIORITIE_OFFSET in FreeRTOSConfig.h
+#define PRIORITIE_OFFSET 0
+#endif
+
+#define SDIO_DEBUG 0
+#define SDIO_MP_MODE 0 // if includes MP mode function
+#define SDIO_MAX_WAIT_RX_DMA 100 // Wait RX DMA done
+#define SDIO_RX_PKT_SIZE_OVER_16K 0 /* is support SDIO RX packet size > 16K. if true,
+ a big packet will be transmited via multiple RX_BD */
+#define SDIO_MAILBOX_SIZE 10 // the maximum number of message block can be stored in this mailbox
+#define SDIO_PERIODICAL_TIMER_INTERVAL 2000 // in ms, the interval of SDIO periodical timer
+#define SDIO_AVG_TP_WIN_SIZE 20 // the number of entry to log the byte count for every periodical timer statistic, to calculate throughput
+
+#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
+#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
+#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
+#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
+
+/***** Register Address *****/
+#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes
+#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes
+#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes
+#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes
+#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes
+#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes
+#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes
+#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes
+#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte
+#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte
+#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes
+#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes
+#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes
+#define REG_SPDIO_CCPWM 0xC4 // 1 Byts
+#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte
+#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes
+#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes
+#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes
+#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes
+#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes
+#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes
+#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes
+#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes
+#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes
+#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes
+#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes
+
+// Register REG_SPDIO_CPU_RST_DMA
+#define BIT_CPU_RST_SDIO_DMA BIT(7)
+
+// Register REG_SPDIO_CPU_INT_MASK, REG_SPDIO_CPU_INT_STAS
+#define BIT_TXFIFO_H2C_OVF BIT(0)
+#define BIT_H2C_BUS_RES_FAIL BIT(1)
+#define BIT_H2C_DMA_OK BIT(2)
+#define BIT_C2H_DMA_OK BIT(3)
+#define BIT_H2C_MSG_INT BIT(4)
+#define BIT_RPWM1_INT BIT(5)
+#define BIT_RPWM2_INT BIT(6)
+#define BIT_SDIO_RST_CMD_INT BIT(7)
+#define BIT_RXBD_FLAG_ERR_INT BIT(8)
+#define BIT_RX_BD_AVAI_INT BIT(9)
+#define BIT_HOST_WAKE_CPU_INT BIT(10)
+
+// Register REG_SPDIO_CPU_IND
+#define BIT_SYSTEM_TRX_RDY_IND BIT(0)
+
+// Register REG_SPDIO_HCI_RX_REQ
+#define BIT_HCI_RX_REQ BIT(0)
+
+/* Register for SOC_HCI_COM_FUN_EN */
+#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) // SDIO Function Block on Power_Off domain
+#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) // SDIO Function Block on Power_On domain
+
+/* Register REG_PESOC_HCI_CLK_CTRL0 */
+#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) // SDIO_HST clock enable when CPU sleep command
+#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) // SDIO_HST clock enable in CPU run mode
+#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) // SDIO_DEV clock enable when CPU sleep command
+#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) // SDIO_DEV clock enable in CPU run mode
+
+/***** Structer for each Register *****/
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+// Little Endian
+// Register REG_SPDIO_HCI_RX_REQ @ 0xBA
+typedef struct _SPDIO_HCI_RX_REQ {
+ u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
+ u8 Reserved:7; /* bit[7:1], Reserved */
+} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
-__BUILD_CCTRL_MACRO(SDIOD, REG_PESOC_HCI_CLK_CTRL0)
-__BUILD_CCTRL_MACRO(SDIOH, REG_PESOC_HCI_CLK_CTRL0)
+// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
+typedef struct _SPDIO_CPU_RST_DMA {
+ u8 Reserved:7; /* bit[6:0], Reserved */
+ u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */
+} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
+
+// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
+typedef struct _SPDIO_CPU_INT_MASK {
+ u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+ u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+ u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
+ u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
+ u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
+ u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
+ u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
+ u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+ u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+ u16 Reserved:7; /* bit[15:9], Reserved */
+} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
+
+// Register REG_SPDIO_CPU_INT_STATUS @ 0xC2
+typedef struct _SPDIO_CPU_INT_STAS {
+ u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+ u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+ u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
+ u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
+ u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
+ u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
+ u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
+ u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+ u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+ u16 Reserved:7; /* bit[15:9], Reserved */
+} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
+
+// Register REG_SPDIO_CCPWM @ 0xC4
+typedef struct _SPDIO_CCPWM {
+ u8 :1; /* bit[0] */
+ u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
+ u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
+ u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+ u8 Reserved:3; /* bit[6:4], Reserved */
+ u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
+} SPDIO_CCPWM, *PSPDIO_CCPWM;
+
+// Register REG_SPDIO_CPU_IND @ 0xC5
+typedef struct _SPDIO_CPU_IND {
+ u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX
+ , to be sync to 0x87[0] */
+ u8 Reserved:7; /* bit[7:1], Reserved */
+} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
+
+// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
+typedef struct _SPDIO_CPU_H2C_MSG {
+ u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message, sync from REG_SDIO_H2C_MSG */
+ u32 Reserved:1; /* bit[31], Reserved */
+} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
+
+// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
+typedef struct _SPDIO_CPU_C2H_MSG {
+ u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
+ u32 Reserved:1; /* bit[31], Reserved */
+} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
+
+// Register REG_SPDIO_CRPWM @ 0xD0
+typedef struct _SPDIO_CRPWM {
+ u8 :1; /* bit[0] */
+ u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
+ u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
+ u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+ u8 Reserved:3; /* bit[6:4], Reserved */
+ u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
+} SPDIO_CRPWM, *PSPDIO_CRPWM;
+
+// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
+typedef struct _SPDIO_AHB_DMA_CTRL {
+ u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */
+ u32 :1; /* bit[7] */
+ u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */
+ u32 :1; /* bit[15] */
+ u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */
+ u32 :1; /* bit[20] */
+ u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */
+ u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */
+ u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */
+ u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */
+ u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */
+} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
+
+#else /* else of '#if LITTLE_ENDIAN' */
+// Big Endian
+typedef struct _SPDIO_HCI_RX_REQ {
+ u8 Reserved:7; /* bit[7:1], Reserved */
+ u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */
+} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ;
+
+// Register REG_SPDIO_CPU_RST_DMA @ 0xBB
+typedef struct _SPDIO_CPU_RST_DMA {
+ u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */
+ u8 Reserved:7; /* bit[6:0], Reserved */
+} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA;
+
+// Register REG_SPDIO_CPU_INT_MASK @ 0xC0
+typedef struct _SPDIO_CPU_INT_MASK {
+ u16 Reserved:7; /* bit[15:9], Reserved */
+ u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+ u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+ u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
+ u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
+ u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
+ u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
+ u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
+ u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+ u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK;
+
+// Register REG_SPDIO_CPU_INT_STAS @ 0xC2
+typedef struct _SPDIO_CPU_INT_STAS {
+ u16 Reserved:7; /* bit[15:9], Reserved */
+ u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */
+ u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */
+ u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */
+ u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */
+ u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */
+ u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */
+ u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */
+ u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */
+ u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */
+} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS;
-#define __SDIOD_Enable() \
- do { \
- __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \
- __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \
- } while (0)
+// Register REG_SPDIO_CCPWM @ 0xC4
+typedef struct _SPDIO_CCPWM {
+ u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
+ u8 Reserved:3; /* bit[6:4], Reserved */
+ u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+ u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
+ u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
+ u8 :1; /* bit[0] */
+} SPDIO_CCPWM, *PSPDIO_CCPWM;
+
+// Register REG_SPDIO_CPU_IND @ 0xC5
+typedef struct _SPDIO_CPU_IND {
+ u8 Reserved:7; /* bit[7:1], Reserved */
+ u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX
+ , to be sync to 0x87[0] */
+} SPDIO_CPU_IND, *PSPDIO_CPU_IND;
+
+// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8
+typedef struct _SPDIO_CPU_H2C_MSG {
+ u32 Reserved:1; /* bit[31], Reserved */
+ u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message */
+} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG;
+
+// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC
+typedef struct _SPDIO_CPU_C2H_MSG {
+ u32 Reserved:1; /* bit[31], Reserved */
+ u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */
+} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG;
+
+// Register REG_SPDIO_CRPWM @ 0xD0
+typedef struct _SPDIO_CRPWM {
+ u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */
+ u8 Reserved:3; /* bit[6:4], Reserved */
+ u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */
+ u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */
+ u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */
+ u8 :1; /* bit[0] */
+} SPDIO_CRPWM, *PSPDIO_CRPWM;
+
+// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4
+typedef struct _SPDIO_AHB_DMA_CTRL {
+ u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */
+ u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */
+ u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */
+ u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */
+ u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */
+ u32 :1; /* bit[20] */
+ u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */
+ u32 :1; /* bit[15] */
+ u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */
+ u32 :1; /* bit[7] */
+ u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */
+} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL;
+
+#endif /* end of '#if LITTLE_ENDIAN' */
+
+
+//#define TX_FIFO_ADDR 0x0000
+//#define TX_FIFO_SIZE 0x8000
+
+//TX BD setting
+#if SDIO_BOOT_DRIVER
+// for build ROM library
+#define SDIO_TX_BD_NUM 2 // Number of TX BD
+#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes
+#define SDIO_TX_PKT_NUM 10 // Number of TX packet handler
+
+//RX BD setting
+#define RX_BD_FREE_TH 4 // trigger the interrupt when free RX BD over this threshold
+
+#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned
+
+#define SDIO_RX_PKT_NUM 3 // Number of RX packet handler
+//#define SDIO_RX_BD_NUM 10 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_BD_NUM (SDIO_RX_PKT_NUM*2) // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_BD_BUF_SIZE (2048+24) // the size of a RX BD pointed buffer, sizeof(RX Desc) = 26 bytes
+#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2:
+ one for RX_Desc, the other for payload */
+
+// CCPWM2 bit map definition for Firmware download
+#define SDIO_INIT_DONE (BIT0)
+#define SDIO_MEM_WR_DONE (BIT1)
+#define SDIO_MEM_RD_DONE (BIT2)
+#define SDIO_MEM_ST_DONE (BIT3)
+
+#define SDIO_CPWM2_TOGGLE (BIT15)
+
+#else
+#if CONFIG_INIC_EN
+//TX BD setting
+#define SDIO_TX_BD_NUM 20 // Number of TX BD
+#define SDIO_TX_BD_BUF_SIZE 1540 //1514+24
+//#define SDIO_TX_PKT_NUM 1 // not used
+
+//RX BD setting
+#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold
+#define SDIO_RX_BD_BUF_SIZE 1540 //1514+24
+#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned
+#define SDIO_RX_BD_NUM 32 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler
+#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2:
+ one for RX_Desc, the other for payload */
+
+#else
+#define SDIO_TX_BD_NUM 24 // Number of TX BD
+#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes
+#define SDIO_TX_PKT_NUM 128 // Number of TX packet handler
+
+//RX BD setting
+#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold
+
+#define SDIO_RX_BD_BUF_SIZE 2048
+#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned
+
+//#define SDIO_TX_FIFO_SIZE (1024*64) // 64K
+#define SDIO_RX_BD_NUM 24 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least
+#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler
+#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2:
+ one for RX_Desc, the other for payload */
+#endif
+#endif
+
+#define SDIO_IRQ_PRIORITY 10
-#define __SDIOH_Enable() \
- do { \
- __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \
- } while (0)
+/* SDIO Events */
+#define SDIO_EVENT_IRQ BIT(0) // Interrupt triggered
+#define SDIO_EVENT_RX_PKT_RDY BIT(1) // A new SDIO packet ready
+#define SDIO_EVENT_C2H_DMA_DONE BIT(2) // Interrupt of C2H DMA done triggered
+#define SDIO_EVENT_DUMP BIT(3) // SDIO status dump periodically Enable
+#define SDIO_EVENT_TXBD_REFILL BIT(4) // To refill TX BD buffer
+#define SDIO_EVENT_EXIT BIT(28) // Request to exit the SDIO task
+#define SDIO_EVENT_MP_STOPPED BIT(29) // The SDIO task is stopped
+#define SDIO_EVENT_TX_STOPPED BIT(30) // The SDIO task is stopped
+#define SDIO_EVENT_RX_STOPPED BIT(31) // The SDIO task is stopped
+
+#define SDIO_TASK_PRIORITY 1 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
+#define SDIO_MP_TASK_PRIORITY 2 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest)
+//#if SDIO_TASK_PRIORITY > (configMAX_PRIORITIES - 1)
+#if SDIO_TASK_PRIORITY > (4 - 1)
+#error "SDIO Task Priority Should be 0~(configMAX_PRIORITIES-1)"
+#endif
+
+//#define TX_RX_PACKET_SIZE 0x144
+
+typedef struct _SDIO_TX_BD_ {
+ u32 Address; /* The TX buffer physical address, it must be 4-bytes aligned */
+}SDIO_TX_BD, *PSDIO_TX_BD;
+
+#define TX_BD_STRUCTURE_SIZE (sizeof(SDIO_TX_BD))
+
+
+/* The RX Buffer Descriptor format */
+
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+typedef struct _SDIO_RX_BD_ {
+ u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384-1 */
+ u32 LS:1; /* bit[14], is the Last Segment ? */
+ u32 FS:1; /* bit[15], is the First Segment ? */
+ u32 Seq:16; /* bit[31:16], The sequence number, it's no use for now */
+ u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */
+} SDIO_RX_BD, *PSDIO_RX_BD;
+#else
+typedef struct _SDIO_RX_BD_ {
+ u32 Seq:16; /* bit[31:16], The sequence number, be used for ?? */
+ u32 FS:1; /* bit[15], is the First Segment ? */
+ u32 LS:1; /* bit[14], is the Last Segment ? */
+ u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384 */
+ u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */
+} SDIO_RX_BD, *PSDIO_RX_BD;
+#endif
+#define RX_BD_STRUCTURE_SIZE (sizeof(SDIO_RX_BD))
+
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _SDIO_TX_DESC{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 txpktsize:16; // bit[15:0]
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+#else
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 txpktsize:16; // bit[15:0]
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the packet type
+ u32 rsvd0:24;
+#else
+ u32 rsvd0:24;
+ u32 type:8; // bit[7:0], the packet type
+#endif
+
+ // u4Byte 2
+ u32 rsvd1;
+
+ // u4Byte 3
+ u32 rsvd2;
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_TX_DESC, *PSDIO_TX_DESC;
+
+// TX Desc for Memory Write command
+typedef struct _SDIO_TX_DESC_MW{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 txpktsize:16; // bit[15:0]
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+#else
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 txpktsize:16; // bit[15:0]
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the packet type
+ u32 reply:1; // bit[8], request to send a reply message
+ u32 rsvd0:23;
+#else
+ u32 rsvd0:23;
+ u32 reply:1; // bit[8], request to send a reply message
+ u32 type:8; // bit[7:0], the packet type
+#endif
+
+ // u4Byte 2
+ u32 start_addr; // memory write start address
+
+ // u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 write_len:16; // bit[15:0], the length to write
+ u32 rsvd2:16; // bit[31:16]
+#else
+ u32 rsvd2:16; // bit[31:16]
+ u32 write_len:16; // bit[15:0], the length to write
+#endif
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_TX_DESC_MW, *PSDIO_TX_DESC_MW;
+
+// TX Desc for Memory Read command
+typedef struct _SDIO_TX_DESC_MR{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 txpktsize:16; // bit[15:0]
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+#else
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 txpktsize:16; // bit[15:0]
+#endif
-#define __SDIOD_Disable() \
- do { \
- __RTK_READ32(SDIO_DEVICE_REG_BASE, 0); \
- __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \
- __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \
- } while (0)
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the packet type
+ u32 rsvd0:24;
+#else
+ u32 rsvd0:24;
+ u32 type:8; // bit[7:0], the packet type
+#endif
+
+ // u4Byte 2
+ u32 start_addr; // memory write start address
+
+ // u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 read_len:16; // bit[15:0], the length to read
+ u32 rsvd2:16; // bit[31:16]
+#else
+ u32 rsvd2:16; // bit[31:16]
+ u32 read_len:16; // bit[15:0], the length to read
+#endif
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_TX_DESC_MR, *PSDIO_TX_DESC_MR;
+
+// TX Desc for Memory Set command
+typedef struct _SDIO_TX_DESC_MS{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 txpktsize:16; // bit[15:0]
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+#else
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 txpktsize:16; // bit[15:0]
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the packet type
+ u32 data:8; // bit[8:15], the value to be written to the memory
+ u32 reply:1; // bit[16], request to send a reply message
+ u32 rsvd0:15;
+#else
+ u32 rsvd0:15;
+ u32 reply:1; // bit[16], request to send a reply message
+ u32 data:8; // bit[8:15], the value to be written to the memory
+ u32 type:8; // bit[7:0], the packet type
+#endif
+
+ // u4Byte 2
+ u32 start_addr; // memory write start address
+
+ // u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 write_len:16; // bit[15:0], the length to write
+ u32 rsvd2:16; // bit[31:16]
+#else
+ u32 rsvd2:16; // bit[31:16]
+ u32 write_len:16; // bit[15:0], the length to write
+#endif
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_TX_DESC_MS, *PSDIO_TX_DESC_MS;
+
+// TX Desc for Jump to Start command
+typedef struct _SDIO_TX_DESC_JS{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 txpktsize:16; // bit[15:0]
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+#else
+ u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
+ u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
+ u32 txpktsize:16; // bit[15:0]
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the packet type
+ u32 rsvd0:24;
+#else
+ u32 rsvd0:24;
+ u32 type:8; // bit[7:0], the packet type
+#endif
+
+ // u4Byte 2
+ u32 start_fun; // the pointer of the startup function
+
+ // u4Byte 3
+ u32 rsvd2;
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_TX_DESC_JS, *PSDIO_TX_DESC_JS;
+
+
+#define SIZE_TX_DESC (sizeof(SDIO_TX_DESC))
+// define the TX BD buffer size with unite of 64 byets
+/* Be carefull!! the setting of hardware's TX BD buffer size may exceed the real size of
+ the TX BD buffer size, and then it may cause the hardware DMA write the buffer overflow */
+#define SDIO_TX_BUF_SZ_UNIT 64
+#define SDIO_TX_BD_BUF_USIZE ((((SDIO_TX_BD_BUF_SIZE+sizeof(SDIO_TX_DESC)-1)/SDIO_TX_BUF_SZ_UNIT)+1)&0xff)
+
+typedef struct _SDIO_TX_BD_BUFFER_ {
+ SDIO_TX_DESC TX_Desc;
+ u8 TX_Buffer[SDIO_TX_BD_BUF_SIZE];
+}SDIO_TX_BD_BUFFER, *PSDIO_TX_BD_BUFFER;
+
-#define __SDIOH_Disable() \
- do { \
- __RTK_READ32(SDIO_HOST_REG_BASE, 0); \
- __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \
- } while (0)
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _SDIO_RX_DESC{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 pkt_len:16; // bit[15:0], the packet size
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 rsvd0:6; // bit[29:24]
+ u32 icv:1; // bit[30], ICV error
+ u32 crc:1; // bit[31], CRC error
+#else
+ u32 crc:1; // bit[31], CRC error
+ u32 icv:1; // bit[30], ICV error
+ u32 rsvd0:6; // bit[29:24]
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 pkt_len:16; // bit[15:0], the packet size
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the type of this packet
+ u32 rsvd1:24; // bit[31:8]
+#else
+ u32 rsvd1:24; // bit[31:8]
+ u32 type:8; // bit[7:0], the type of this packet
+#endif
+
+ // u4Byte 2
+ u32 rsvd2;
+
+ // u4Byte 3
+ u32 rsvd3;
+
+ // u4Byte 4
+ u32 rsvd4;
+
+ // u4Byte 5
+ u32 rsvd5;
+} SDIO_RX_DESC, *PSDIO_RX_DESC;
+
+// For memory read command
+typedef struct _SDIO_RX_DESC_MR{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 pkt_len:16; // bit[15:0], the packet size
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 rsvd0:8; // bit[31:24]
+#else
+ u32 rsvd0:8; // bit[31:24]
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 pkt_len:16; // bit[15:0], the packet size
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the type of this packet
+ u32 rsvd1:24; // bit[31:8]
+#else
+ u32 rsvd1:24; // bit[31:8]
+ u32 type:8; // bit[7:0], the type of this packet
+#endif
+
+ // u4Byte 2
+ u32 start_addr;
+
+ // u4Byte 3
+ u32 rsvd2;
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_RX_DESC_MR, *PSDIO_RX_DESC_MR;
+
+// For memory write reply command
+typedef struct _SDIO_RX_DESC_MW{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 pkt_len:16; // bit[15:0], the packet size
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 rsvd0:8; // bit[31:24]
+#else
+ u32 rsvd0:8; // bit[31:24]
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 pkt_len:16; // bit[15:0], the packet size
+#endif
+
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the type of this packet
+ u32 rsvd1:24; // bit[31:8]
+#else
+ u32 rsvd1:24; // bit[31:8]
+ u32 type:8; // bit[7:0], the type of this packet
+#endif
+
+ // u4Byte 2
+ u32 start_addr;
+
+ // u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 write_len:16; // bit[15:0], the type of this packet
+ u32 result:8; // bit[23:16], the result of memory write command
+ u32 rsvd2:8; // bit[31:24]
+#else
+ u32 rsvd2:8; // bit[31:24]
+ u32 result:8; // bit[23:16], the result of memory write command
+ u32 write_len:16; // bit[15:0], the type of this packet
+#endif
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_RX_DESC_MW, *PSDIO_RX_DESC_MW;
+
+// For memory set reply command
+typedef struct _SDIO_RX_DESC_MS{
+ // u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 pkt_len:16; // bit[15:0], the packet size
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 rsvd0:8; // bit[31:24]
+#else
+ u32 rsvd0:8; // bit[31:24]
+ u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+ u32 pkt_len:16; // bit[15:0], the packet size
+#endif
-// PERI_MCTRL_HCI
-#define __SDIOD_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN)
-#define __SDIOH_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN)
-#define __SDIOD_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN)
-#define __SDIOH_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN)
-#define __MII_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN)
-#define __MII_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN)
+ // u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 type:8; // bit[7:0], the type of this packet
+ u32 rsvd1:24; // bit[31:8]
+#else
+ u32 rsvd1:24; // bit[31:8]
+ u32 type:8; // bit[7:0], the type of this packet
+#endif
+
+ // u4Byte 2
+ u32 start_addr;
+
+ // u4Byte 3
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+ u32 write_len:16; // bit[15:0], the type of this packet
+ u32 result:8; // bit[23:16], the result of memory write command
+ u32 rsvd2:8; // bit[31:24]
+#else
+ u32 rsvd2:8; // bit[31:24]
+ u32 result:8; // bit[23:16], the result of memory write command
+ u32 write_len:16; // bit[15:0], the type of this packet
+#endif
+
+ // u4Byte 4
+ u32 rsvd3;
+
+ // u4Byte 5
+ u32 rsvd4;
+} SDIO_RX_DESC_MS, *PSDIO_RX_DESC_MS;
+
+#define SIZE_RX_DESC (sizeof(SDIO_RX_DESC))
+
+typedef struct _SDIO_RX_BD_BUFFER_ {
+ SDIO_RX_DESC RX_Desc;
+ u8 RX_Buffer[SDIO_RX_BD_BUF_SIZE];
+}SDIO_RX_BD_BUFFER, *PSDIO_RX_BD_BUFFER;
+
+
+/* The data structer for a packet fordwarding to the WLan driver to transmit it */
+// TODO: This data structer just for test, we may need modify it for the normal driver
+typedef struct _SDIO_TX_PACKET_ {
+ u8 *pHeader; // Point to the 1st byte of the packets
+ u16 PktSize; // the size (bytes) of this packet
+ _LIST list; // the link list to chain packets
+ u8 isDyna; // is Dynamic allocated
+} SDIO_TX_PACKET, *PSDIO_TX_PACKET;
+
+/* the data structer to bind a TX_BD with a TX Packet */
+typedef struct _SDIO_TX_BD_HANDLE_ {
+ SDIO_TX_BD *pTXBD; // Point to the TX_BD buffer
+#if SDIO_API_DEFINED
+ VOID *priv;
+#else
+#if CONFIG_INIC_EN
+#if CONFIG_INIC_SKB_TX
+ struct sk_buff *skb;
+#endif
+#endif
+#endif
+ SDIO_TX_PACKET *pPkt; // point to the Tx Packet
+ u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end
+ u8 isFree; // is this TX BD free
+} SDIO_TX_BD_HANDLE, *PSDIO_TX_BD_HANDLE;
+
+/* The data structer for a packet which from the WLan driver to send to the Host */
+// TODO: This data structer just for test, we may need modify it for the normal driver
+
+#if SDIO_BOOT_DRIVER
+typedef struct _SDIO_RX_PACKET_ {
+// SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet
+ u8 *pData; // point to the head of payload of this packet
+ u16 Offset; // the offset from the pData to the payload buffer
+ _LIST list; // the link list to chain packets
+ u8 PktBuf[SDIO_RX_BD_BUF_SIZE]; // the Rx_Desc + payload data buffer, the first 24 bytes is reserved for RX_DESC
+} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
+#else
+typedef struct _SDIO_RX_PACKET_ {
+ SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet
+#if SDIO_API_DEFINED
+ VOID *priv;
+#else
+#if CONFIG_INIC_EN
+#if CONFIG_INIC_SKB_RX
+ struct sk_buff *skb;
+#endif
+#endif
+#endif
+ u8 *pData; // point to the head of payload of this packet
+ u16 Offset; // the offset from the pData to the payload buffer
+ _LIST list; // the link list to chain packets
+ u8 isDyna; // is Dynamic allocated
+} SDIO_RX_PACKET, *PSDIO_RX_PACKET;
+#endif
+
+/* the data structer to bind a RX_BD with a RX Packet */
+typedef struct _SDIO_RX_BD_HANDLE_ {
+ SDIO_RX_BD *pRXBD; // Point to the RX_BD buffer
+ SDIO_RX_PACKET *pPkt; // point to the Rx Packet
+ u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end
+ u8 isFree; // is this RX BD free (DMA done and its RX packet has been freed)
+} SDIO_RX_BD_HANDLE, *PSDIO_RX_BD_HANDLE;
+
+#if SDIO_MP_MODE
+typedef struct _SDIO_MP_CMD_ {
+ u8 cmd_name[16];
+ u32 cmd_type;
+} SDIO_MP_CMD, *PSDIO_MP_CMD;
+
+typedef enum _SDIO_MP_CMD_TYPE_{
+ SDIO_MP_START=1,
+ SDIO_MP_STOP=2,
+ SDIO_MP_LOOPBACK=3,
+ SDIO_MP_STATUS=4,
+ SDIO_MP_READ_REG8=5,
+ SDIO_MP_READ_REG16=6,
+ SDIO_MP_READ_REG32=7,
+ SDIO_MP_WRITE_REG8=8,
+ SDIO_MP_WRITE_REG16=9,
+ SDIO_MP_WRITE_REG32=10,
+ SDIO_MP_WAKEUP=11, // wakeup the SDIO task manually, for debugging
+ SDIO_MP_DUMP=12, // start/stop to dump the SDIO status periodically
+ SDIO_MP_CTX=13, // setup continue TX test
+ SDIO_MP_CRX=14, // setup continue RX test
+ SDIO_MP_CRX_DA=15, // setup continue RX with dynamic allocate RX Buf test
+ SDIO_MP_CRX_STOP=16, // setup continue RX test
+ SDIO_MP_DBG_MSG=17, // Debug message On/Off
+
+}SDIO_MP_CMD_TYPE;
-// Interface for HAL functions
-extern void SDIO_HST_Disable(void);
-extern void SDIO_DEV_Disable(void);
+typedef enum _SDIO_CRX_MODE_{
+ SDIO_CRX_STATIC_BUF = 1,
+ SDIO_CRX_DYNA_BUF = 2,
+} SDIO_CRX_MODE;
+
+typedef struct _SDIO_MP_RX_PACKET_ {
+ _LIST list; // this member MUST be the 1st one, the link list to chain packets
+ u8 *pData; // point to the head of payload of this packet
+ u16 Offset; // the offset from the pData to the payload
+ u16 DataLen; // the data length of this packet
+} SDIO_MP_RX_PACKET, *PSDIO_MP_RX_PACKET;
+
+#endif // end of '#if SDIO_MP_MODE'
+
+#define SDIO_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
+#define SDIO_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
+#define SDIO_CMD_H2C 0x11 // H2C(host to device) command packet
+#define SDIO_CMD_MEMRD 0x51 // request to read a block of memory data
+#define SDIO_CMD_MEMWR 0x53 // request to write a block of memory
+#define SDIO_CMD_MEMST 0x55 // request to set a block of memory with a value
+#define SDIO_CMD_STARTUP 0x61 // request to jump to the start up function
+
+#define SDIO_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
+#define SDIO_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
+#define SDIO_CMD_C2H 0x10 // C2H(device to host) command packet
+#define SDIO_CMD_MEMRD_RSP 0x50 // response to memory block read command
+#define SDIO_CMD_MEMWR_RSP 0x52 // response to memory write command
+#define SDIO_CMD_MEMST_RSP 0x54 // response to memory set command
+#define SDIO_CMD_STARTED 0x60 // indicate the program has jumped to the given function
+
+enum SDIO_RPWM2_BITS {
+ RPWM2_ACT_BIT = BIT0, // Active
+ RPWM2_SLEEP_BIT = 0, // Sleep
+ RPWM2_DSTANDBY_BIT = BIT1, // Deep Standby
+ RPWM2_PG_BIT = 0, // Power Gated
+ RPWM2_FBOOT_BIT = BIT2, // fast reboot
+ RPWM2_NBOOT_BIT = 0, // normal reboot
+ RPWM2_WKPIN_A5_BIT = BIT3, // enable GPIO A5 wakeup
+ RPWM2_WKPIN_C7_BIT = BIT4, // enable GPIO C7 wakeup
+ RPWM2_WKPIN_D5_BIT = BIT5, // enable GPIO D5 wakeup
+ RPWM2_WKPIN_E3_BIT = BIT6, // enable GPIO E3 wakeup
+ RPWM2_PIN_A5_LV_BIT = BIT7, // GPIO A5 wakeup level
+ RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level
+ RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level
+ RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level
+ RPWM2_CG_BIT = BIT11, // Clock Gated
+ RPWM2_ACK_BIT = BIT14, // Acknowledge
+ RPWM2_TOGGLE_BIT = BIT15, // Toggle bit
+};
+
+enum SDIO_CPWM2_BITS {
+ CPWM2_ACT_BIT = BIT0, // Active
+ CPWM2_DSTANDBY_BIT = BIT1, // Deep Standby
+ CPWM2_FBOOT_BIT = BIT2, // fast reboot
+ CPWM2_INIC_FW_RDY_BIT = BIT3, // is the iNIC FW(1) or Boot FW(0)
+
+ CPWM2_TOGGLE_BIT = BIT15, // Toggle bit
+};
+
+#ifdef CONFIG_SDIO_DEVICE_VERIFY
+
+#define TX_BD_STRUCTURE_NUM 10
+#define RX_BD_STRUCTURE_NUM 10
+#define TX_BD_BUFFER_SIZE 0x1000//0x2000//0x800
+#define RX_BD_BUFFER_SIZE 0x400//0x800
-#endif
+#define SDIO_RAM_ADDR_BASE 0x20080000
+#define SDIO_BUFFER_HEAD(addr) SDIO_RAM_ADDR_BASE + addr
+#define HAL_SDIO_BUFFER_READ8(addr) HAL_READ8(SDIO_RAM_ADDR_BASE, addr)
+#define HAL_SDIO_BUFFER_READ32(addr) HAL_READ32(SDIO_RAM_ADDR_BASE, addr)
+#define HAL_SDIO_BUFFER_WRITE32(addr, value) HAL_WRITE32(SDIO_RAM_ADDR_BASE, addr, value)
+
+//#define RX_BD_ADDR 0x8000
+//#define RX_BUFFER_ADDR 0x8050
+
+typedef enum _SDIO_TEST_FUNC_ {
+ SDIO_TEST_INIT, // 0
+ SDIO_TEST_INT_ON, // 1
+ SDIO_TEST_INT_OFF, // 2
+ SDIO_HCI_RX_REQ, // 3
+ SDIO_RESET_TXFIFIO, // 4
+ SDIO_CPU_RST_DMA, // 5
+ SDIO_CPU_CLR_INT_REG, // 6
+ SDIO_TIMER_TEST, // 7
+ SDIO_TEST_DEBUG, // 8
+ SDIO_TEST, // 9
+ SDIO_HELP = 0xff
+}SDIO_TEST_FUNC, *PSDIO_TEST_FUNC;
+
+typedef struct _SDIO_TEST_ADAPTER_ {
+ u32 TXWritePtr;
+ u32 TXReadPtr;
+ u16 RXWritePtr;
+ u16 RXReadPtr;
+ u16 IntMask;
+ u16 IntStatus;
+} SDIO_TEST_ADAPTER, *PSDIO_TEST_ADAPTER;
+
+
+VOID
+MovePKTToRX(
+ IN u32 Source, IN u32 Destination, IN u32 PKTSize
+);
+
+BOOL
+PacketProcess(
+ IN SDIO_TEST_ADAPTER *pDevStatus
+);
+
+VOID
+SdioDeviceIrqHandleFunc(
+ IN VOID *DATA
+);
+
+VOID
+SdioDeviceTestApp(
+ IN u32 Data
+);
+
+VOID
+InitRXBD(VOID);
+
+VOID
+InitTXFIFO(VOID);
+
+VOID
+IrqRegister(VOID);
+
+#endif // end of "#ifdef CONFIG_SDIO_DEVICE_VERIFY"
+
+#endif /* #ifndef _RTL8195A_SDIO_H_ */
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h Thu Nov 08 11:46:34 2018 +0000
@@ -89,16 +89,16 @@
IN u32 LoadUs
);
+VOID
+HalTimerSyncRtl8195a(
+ IN u32 TimerId
+);
+
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
-VOID
-HalTimerSync(
- IN u32 TimerId
-);
-
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
@@ -125,6 +125,11 @@
);
VOID
+HalTimerSyncRtl8195a(
+ IN u32 TimerId
+);
+
+VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h Thu Nov 08 11:46:34 2018 +0000
@@ -74,8 +74,10 @@
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
-#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
-#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
+#define RUART_TXDMA_EN_MASK 0x02 // [1]
+#define RUART_RXDMA_EN_MASK 0x04 // [2]
+#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 // [7:3]
+#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 // [12:8]
#define RUART_DEBUG_REG_OFF 0x3C
@@ -551,6 +553,26 @@
IN VOID *Data
);
+VOID
+HalRuartTxGdmaEnable8195a(
+ IN VOID *pHalRuartAdapter
+);
+
+VOID
+HalRuartTxGdmaDisable8195a(
+ IN VOID *pHalRuartAdapter
+);
+
+VOID
+HalRuartRxGdmaEnable8195a(
+ IN VOID *pHalRuartAdapter
+);
+
+VOID
+HalRuartRxGdmaDisable8195a(
+ IN VOID *pHalRuartAdapter
+);
+
#if CONFIG_CHIP_E_CUT
_LONG_CALL_ HAL_Status
HalRuartResetTxFifoRtl8195a_V04(
@@ -649,33 +671,10 @@
HalRuartExitCriticalRtl8195a_V04(
IN VOID *Data
);
-
#endif // #if CONFIG_CHIP_E_CUT
#ifdef CONFIG_MBED_ENABLED
// Interface to ROM functions
-//extern __longcall void HalRuartAdapterLoadDefRtl8195a(UART_Handle *uart, uint8_t idx);
-//extern __longcall void HalRuartDeInitRtl8195a(UART_Handle *uart);
-//extern __longcall HAL_Status HalRuartDisableRtl8195a(UART_Handle *data);
-//extern __longcall HAL_Status HalRuartEnableRtl8195a(UART_Handle *data);
-//extern __longcall void HalRuartDmaInitRtl8195a(UART_Handle *data);
-//extern __longcall void HalRuartTxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg);
-//extern __longcall void HalRuartRxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg);
-//extern __longcall HAL_Status HalRuartGetCRtl8195a(UART_Handle *uart, uint8_t *byte);
-//extern __longcall HAL_Status HalRuartPutCRtl8195a(UART_Handle *uart, uint8_t byte);
-//extern __longcall HAL_Status RuartLock(UART_Handle * uart);
-//extern __longcall void RuartUnlock(UART_Handle * uart);
-//extern __longcall void HalRuartSetIMRRtl8195a(UART_Handle *uart);
-//extern __longcall uint8_t HalRuartGetIMRRtl8195a(UART_Handle *uart);
-//extern __longcall uint32_t HalRuartSendRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t);
-//extern __longcall HAL_Status HalRuartIntSendRtl8195a(UART_Handle *, uint8_t *, uint32_t);
-//extern __longcall HAL_Status HalRuartIntRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t);
-//extern __longcall uint32_t HalRuartRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t);
-//extern __longcall void HalRuartRegIrqRtl8195a(UART_Handle *Data);
-//extern __longcall void HalRuartIntEnableRtl8195a(UART_Handle *Data);
-//extern __longcall void HalRuartIntDisableRtl8195a(UART_Handle *Data);
-//extern __longcall uint32_t HalRuartGetDebugValueRtl8195a(HAL_RUART_ADAPTER *Data, uint32_t sel);
-//extern __longcall void HalRuartRTSCtrlRtl8195a(UART_Handle *Data, bool val);
extern __longcall HAL_Status RuartIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt);
#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/driver/rtl_consol.c Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,384 +0,0 @@
-/*******************************************************************************
- *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
- * SPDX-License-Identifier: LicenseRef-PBL
- *
- * Licensed under the Permissive Binary License, Version 1.0 (the "License");
- * you may not use this file except in compliance with the License.
- *
- * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
- *
- * See the License for the specific language governing permissions and limitations under the License.
- *******************************************************************************
- */
-
-#include "rtl8195a.h"
-//#include <stdarg.h>
-#include "rtl_consol.h"//#include "osdep_service.h"
-////#include "FreeRTOS.h"
-////#include "task.h"
-////#include "semphr.h"
-
-#include "tcm_heap.h"
-
-struct task_struct RtlConsolTaskRam_task;
-
-MON_RAM_BSS_SECTION
- volatile UART_LOG_CTL UartLogCtl;
-MON_RAM_BSS_SECTION
- volatile UART_LOG_CTL *pUartLogCtl;
-MON_RAM_BSS_SECTION
- u8 *ArgvArray[MAX_ARGV];
-MON_RAM_BSS_SECTION
- UART_LOG_BUF UartLogBuf;
-
-
-#ifdef CONFIG_UART_LOG_HISTORY
-MON_RAM_BSS_SECTION
- u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN];
-#endif
-
-_LONG_CALL_
-extern u8
-UartLogCmdChk(
- IN u8 RevData,
- IN UART_LOG_CTL *prvUartLogCtl,
- IN u8 EchoFlag
-);
-
-_LONG_CALL_
-extern VOID
-ArrayInitialize(
- IN u8 *pArrayToInit,
- IN u8 ArrayLen,
- IN u8 InitValue
-);
-
-_LONG_CALL_
-extern VOID
-UartLogHistoryCmd(
- IN u8 RevData,
- IN UART_LOG_CTL *prvUartLogCtl,
- IN u8 EchoFlag
-);
-
-_LONG_CALL_
-extern VOID
-UartLogCmdExecute(
- IN PUART_LOG_CTL pUartLogCtlExe
-);
-
-
-
-//=================================================
-
-
-/* Minimum and maximum values a `signed long int' can hold.
- (Same as `int'). */
-#ifndef __LONG_MAX__
-#if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9) || defined (__s390x__)
-#define __LONG_MAX__ 9223372036854775807L
-#else
-#define __LONG_MAX__ 2147483647L
-#endif /* __alpha__ || sparc64 */
-#endif
-#undef LONG_MIN
-#define LONG_MIN (-LONG_MAX-1)
-#undef LONG_MAX
-#define LONG_MAX __LONG_MAX__
-
-/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */
-#undef ULONG_MAX
-#define ULONG_MAX (LONG_MAX * 2UL + 1)
-
-#ifndef __LONG_LONG_MAX__
-#define __LONG_LONG_MAX__ 9223372036854775807LL
-#endif
-
-
-#if 0
-//======================================================
-//<Function>: UartLogIrqHandleRam
-//<Usage >: To deal with Uart-Log RX IRQ
-//<Argus >: VOID
-//<Return >: VOID
-//<Notes >: NA
-//======================================================
-//MON_RAM_TEXT_SECTION
-VOID
-UartLogIrqHandleRam
-(
- VOID * Data
-)
-{
- u8 UartReceiveData = 0;
- //For Test
- BOOL PullMode = _FALSE;
-
- u32 IrqEn = DiagGetIsrEnReg();
-
- DiagSetIsrEnReg(0);
-
- UartReceiveData = DiagGetChar(PullMode);
- if (UartReceiveData == 0) {
- goto exit;
- }
-
- //KB_ESC chk is for cmd history, it's a special case here.
- if (UartReceiveData == KB_ASCII_ESC) {
- //4 Esc detection is only valid in the first stage of boot sequence (few seconds)
- if (pUartLogCtl->ExecuteEsc != _TRUE)
- {
- pUartLogCtl->ExecuteEsc = _TRUE;
- (*pUartLogCtl).EscSTS = 0;
- }
- else
- {
- //4 the input commands are valid only when the task is ready to execute commands
- if ((pUartLogCtl->BootRdy == 1)
-#ifdef CONFIG_KERNEL
- ||(pUartLogCtl->TaskRdy == 1)
-#endif
- )
- {
- if ((*pUartLogCtl).EscSTS==0)
- {
- (*pUartLogCtl).EscSTS = 1;
- }
- }
- else
- {
- (*pUartLogCtl).EscSTS = 0;
- }
- }
- }
- else if ((*pUartLogCtl).EscSTS==1){
- if (UartReceiveData != KB_ASCII_LBRKT){
- (*pUartLogCtl).EscSTS = 0;
- }
- else{
- (*pUartLogCtl).EscSTS = 2;
- }
- }
-
- else{
- if ((*pUartLogCtl).EscSTS==2){
- (*pUartLogCtl).EscSTS = 0;
-#ifdef CONFIG_UART_LOG_HISTORY
- if ((UartReceiveData=='A')|| UartReceiveData=='B'){
- UartLogHistoryCmd(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1);
- }
-#endif
- }
- else{
- if (UartLogCmdChk(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1)==2)
- {
- //4 check UartLog buffer to prevent from incorrect access
- if (pUartLogCtl->pTmpLogBuf != NULL)
- {
- pUartLogCtl->ExecuteCmd = _TRUE;
-#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
- if (pUartLogCtl->TaskRdy)
- //RtlUpSemaFromISR((_Sema *)&pUartLogCtl->Sema);
- rtw_up_sema_from_isr((_sema *)&pUartLogCtl->Sema);
-#endif
- }
- else
- {
- ArrayInitialize((u8 *)pUartLogCtl->pTmpLogBuf->UARTLogBuf, UART_LOG_CMD_BUFLEN, '\0');
- }
- }
- }
- }
-exit:
- DiagSetIsrEnReg(IrqEn);
-
-}
-
-
-
-//MON_RAM_TEXT_SECTION
-VOID
-RtlConsolInitRam(
- IN u32 Boot,
- IN u32 TBLSz,
- IN VOID *pTBL
-)
-{
- UartLogBuf.BufCount = 0;
- ArrayInitialize(&UartLogBuf.UARTLogBuf[0],UART_LOG_CMD_BUFLEN,'\0');
- pUartLogCtl = &UartLogCtl;
-
- pUartLogCtl->NewIdx = 0;
- pUartLogCtl->SeeIdx = 0;
- pUartLogCtl->RevdNo = 0;
- pUartLogCtl->EscSTS = 0;
- pUartLogCtl->BootRdy = 0;
- pUartLogCtl->pTmpLogBuf = &UartLogBuf;
-#ifdef CONFIG_UART_LOG_HISTORY
- pUartLogCtl->CRSTS = 0;
- pUartLogCtl->pHistoryBuf = &UartLogHistoryBuf[0];
-#endif
- pUartLogCtl->pfINPUT = (VOID*)&DiagPrintf;
- pUartLogCtl->pCmdTbl = (PCOMMAND_TABLE) pTBL;
- pUartLogCtl->CmdTblSz = TBLSz;
-#ifdef CONFIG_KERNEL
- pUartLogCtl->TaskRdy = 0;
-#endif
- //executing boot sequence
- if (Boot == ROM_STAGE)
- {
- pUartLogCtl->ExecuteCmd = _FALSE;
- pUartLogCtl->ExecuteEsc = _FALSE;
- }
- else
- {
- pUartLogCtl->ExecuteCmd = _FALSE;
- pUartLogCtl->ExecuteEsc= _TRUE;//don't check Esc anymore
-#if defined(CONFIG_KERNEL)
- /* Create a Semaphone */
- //RtlInitSema((_Sema*)&(pUartLogCtl->Sema), 0);
- rtw_init_sema((_sema*)&(pUartLogCtl->Sema), 0);
- pUartLogCtl->TaskRdy = 0;
-#ifdef PLATFORM_FREERTOS
-#define LOGUART_STACK_SIZE 128 //USE_MIN_STACK_SIZE modify from 512 to 128
-//if(rtw_create_task(&g_tcp_client_task, "tcp_client_handler", LOGUART_STACK_SIZE, TASK_PRORITY_MIDDLE, tcp_client_handler, 0) != _SUCCESS)
-#if CONFIG_USE_TCM_HEAP
- {
- int ret = 0;
- void *stack_addr = tcm_heap_malloc(LOGUART_STACK_SIZE*sizeof(int));
- //void *stack_addr = rtw_malloc(stack_size*sizeof(int));
- if(stack_addr == NULL){
- DiagPrintf("Out of TCM heap in \"LOGUART_TASK\" ");
- }
- ret = xTaskGenericCreate(
- RtlConsolTaskRam,
- (const char *)"LOGUART_TASK",
- LOGUART_STACK_SIZE,
- NULL,
- tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET,
- NULL,
- stack_addr,
- NULL);
- if (pdTRUE != ret)
- {
- DiagPrintf("Create Log UART Task Err!!\n");
- }
- }
-#else
- if (pdTRUE != xTaskCreate( RtlConsolTaskRam, (const signed char * const)"LOGUART_TASK", LOGUART_STACK_SIZE, NULL, tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET, NULL))
- {
- DiagPrintf("Create Log UART Task Err!!\n");
- }
-#endif
-
-#endif
-
-#endif
- }
-
- CONSOLE_8195A();
-}
-
-extern u8** GetArgv(const u8 *string);
-#if SUPPORT_LOG_SERVICE
-extern char log_buf[LOG_SERVICE_BUFLEN];
-//extern osSemaphore(log_rx_interrupt_sema);
-_sema log_rx_interrupt_sema;
-#endif
-//======================================================
-void console_cmd_exec(PUART_LOG_CTL pUartLogCtlExe)
-{
- u8 CmdCnt = 0;
- u8 argc = 0;
- u8 **argv;
- //u32 CmdNum;
- PUART_LOG_BUF pUartLogBuf = pUartLogCtlExe->pTmpLogBuf;
-#if SUPPORT_LOG_SERVICE
- strncpy(log_buf, (const u8*)&(*pUartLogBuf).UARTLogBuf[0], LOG_SERVICE_BUFLEN-1);
-#endif
- argc = GetArgc((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
- argv = GetArgv((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
-
- if(argc > 0){
-#if SUPPORT_LOG_SERVICE
-// if(log_handler(argv[0]) == NULL)
-// legency_interactive_handler(argc, argv);
- //RtlUpSema((_Sema *)&log_rx_interrupt_sema);
- rtw_up_sema((_sema *)&log_rx_interrupt_sema);
-#endif
- ArrayInitialize(argv[0], sizeof(argv[0]) ,0);
- }else{
-#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
- pmu_acquire_wakelock(BIT(PMU_LOGUART_DEVICE));
-#endif
- CONSOLE_8195A(); // for null command
- }
-
- (*pUartLogBuf).BufCount = 0;
- ArrayInitialize(&(*pUartLogBuf).UARTLogBuf[0], UART_LOG_CMD_BUFLEN, '\0');
-}
-//======================================================
-// overload original RtlConsolTaskRam
-//MON_RAM_TEXT_SECTION
-VOID
-RtlConsolTaskRam(
- VOID *Data
-)
-{
-#if SUPPORT_LOG_SERVICE
- log_service_init();
-#endif
- //4 Set this for UartLog check cmd history
-#ifdef CONFIG_KERNEL
- pUartLogCtl->TaskRdy = 1;
-#endif
-#ifndef CONFIG_KERNEL
- pUartLogCtl->BootRdy = 1;
-#endif
- do{
-#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
- //RtlDownSema((_Sema *)&pUartLogCtl->Sema);
- rtw_down_sema((_sema *)&pUartLogCtl->Sema);
-#endif
- if (pUartLogCtl->ExecuteCmd) {
- // Add command handler here
- console_cmd_exec((PUART_LOG_CTL)pUartLogCtl);
- //UartLogCmdExecute((PUART_LOG_CTL)pUartLogCtl);
- pUartLogCtl->ExecuteCmd = _FALSE;
- }
- }while(1);
-}
-
-//======================================================
-extern void console_init_hs_uart(void);
-void console_init(void)
-{
- #if CONFIG_LOG_USE_HS_UART
- sys_log_uart_off();
- console_init_hs_uart();
- #elif(CONFIG_LOG_USE_I2C)
- sys_log_uart_off();
- // TODO:
- #else
- IRQ_HANDLE UartIrqHandle;
-
- //4 Register Log Uart Callback function
- UartIrqHandle.Data = NULL;//(u32)&UartAdapter;
- UartIrqHandle.IrqNum = UART_LOG_IRQ;
- UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
- UartIrqHandle.Priority = 6;
-
-
- //4 Register Isr handle
- InterruptUnRegister(&UartIrqHandle);
- InterruptRegister(&UartIrqHandle);
- #endif
-
-#if !TASK_SCHEDULER_DISABLED
- RtlConsolInitRam((u32)RAM_STAGE,(u32)0,(VOID*)NULL);
-#else
- RtlConsolInitRam((u32)ROM_STAGE,(u32)0,(VOID*)NULL);
-#endif
-}
-
-#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/driver/rtl_consol.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,139 +0,0 @@
-/*******************************************************************************
- *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
- * SPDX-License-Identifier: LicenseRef-PBL
- *
- * Licensed under the Permissive Binary License, Version 1.0 (the "License");
- * you may not use this file except in compliance with the License.
- *
- * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
- *
- * See the License for the specific language governing permissions and limitations under the License.
- *******************************************************************************
- */
-
-#ifndef _RTK_CONSOL_H_
-#define _RTK_CONSOL_H_
-/*
- * Include user defined options first. Anything not defined in these files
- * will be set to standard values. Override anything you dont like!
- */
- #if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
-#include "platform_opts.h"
-#endif
-
-//#include "osdep_api.h"
-#include "osdep_service.h"
-#include "hal_diag.h"
-
-#define CONSOLE_PREFIX "#"
-
-
-//Log UART
-//UART_LOG_CMD_BUFLEN: only 126 bytes could be used for keeping input
-// cmd, the last byte is for string end ('\0').
-#define UART_LOG_CMD_BUFLEN 127
-#define MAX_ARGV 10
-
-
-
-typedef u32 (*ECHOFUNC)(IN u8*,...); //UART LOG echo-function type.
-
-typedef struct _UART_LOG_BUF_ {
- u8 BufCount; //record the input cmd char number.
- u8 UARTLogBuf[UART_LOG_CMD_BUFLEN]; //record the input command.
-} UART_LOG_BUF, *PUART_LOG_BUF;
-
-
-
-typedef struct _UART_LOG_CTL_ {
- u8 NewIdx;
- u8 SeeIdx;
- u8 RevdNo;
- u8 EscSTS;
- u8 ExecuteCmd;
- u8 ExecuteEsc;
- u8 BootRdy;
- u8 Resvd;
- PUART_LOG_BUF pTmpLogBuf;
- VOID *pfINPUT;
- PCOMMAND_TABLE pCmdTbl;
- u32 CmdTblSz;
-#ifdef CONFIG_UART_LOG_HISTORY
- u32 CRSTS;
-#endif
-#ifdef CONFIG_UART_LOG_HISTORY
- u8 (*pHistoryBuf)[UART_LOG_CMD_BUFLEN];
-#endif
-#ifdef CONFIG_KERNEL
- u32 TaskRdy;
- //_Sema Sema;
- _sema Sema;
-#else
- // Since ROM code will reference this typedef, so keep the typedef same size
- u32 TaskRdy;
- void *Sema;
-#endif
-} UART_LOG_CTL, *PUART_LOG_CTL;
-
-
-#define KB_ASCII_NUL 0x00
-#define KB_ASCII_BS 0x08
-#define KB_ASCII_TAB 0x09
-#define KB_ASCII_LF 0x0A
-#define KB_ASCII_CR 0x0D
-#define KB_ASCII_ESC 0x1B
-#define KB_ASCII_SP 0x20
-#define KB_ASCII_BS_7F 0x7F
-#define KB_ASCII_LBRKT 0x5B //[
-
-#define KB_SPACENO_TAB 1
-
-#ifdef CONFIG_UART_LOG_HISTORY
-#define UART_LOG_HISTORY_LEN 5
-#endif
-
-#ifdef CONFIG_DEBUG_LOG
-#define _ConsolePrint DiagPrintf
-#else
-#define _ConsolePrint
-#endif
-
-#ifndef CONSOLE_PREFIX
-#define CONSOLE_PREFIX "<RTL8195A>"
-#endif
-
-#define CONSOLE_8195A(...) do {\
- _ConsolePrint("\r"CONSOLE_PREFIX __VA_ARGS__);\
-}while(0)
-
-
-_LONG_CALL_ VOID
-RtlConsolInit(
- IN u32 Boot,
- IN u32 TBLSz,
- IN VOID *pTBL
-);
-
-#if defined(CONFIG_KERNEL)
-_LONG_CALL_ VOID
-RtlConsolTaskRam(
- VOID *Data
-);
-#endif
-
-_LONG_CALL_ VOID
-RtlConsolTaskRom(
- VOID *Data
-);
-
-
-_LONG_CALL_ u32
-Strtoul(
- IN const u8 *nptr,
- IN u8 **endptr,
- IN u32 base
-);
-
-void console_init(void);
-
-#endif //_RTK_CONSOL_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,213 @@
+#if DEVICE_SLEEP
+
+//#include "FreeRTOS.h"
+#include "cmsis_pmu_8195a.h"
+
+#include <platform_opts.h>
+
+#include "platform_autoconf.h"
+#include "platform_stdlib.h"
+//#include "sys_api.h"
+
+#include "sleep_ex_api.h"
+
+#ifndef portNVIC_SYSTICK_CURRENT_VALUE_REG
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#endif
+
+uint32_t missing_tick = 0;
+
+static uint32_t wakelock = 0;
+//static uint32_t wakelock = DEFAULT_WAKELOCK;
+
+static uint32_t wakeup_event = DEFAULT_WAKEUP_EVENT;
+
+typedef struct {
+ uint32_t nDeviceId;
+ PSM_HOOK_FUN sleep_hook_fun;
+ void* sleep_param_ptr;
+ PSM_HOOK_FUN wakeup_hook_fun;
+ void* wakeup_param_ptr;
+} PSM_DD_HOOK_INFO;
+
+#define MAX_PSM_DD_HOOK_INFO_SIZE 8
+uint32_t psm_dd_hook_info_size = 0;
+PSM_DD_HOOK_INFO psm_dd_hook_infos[MAX_PSM_DD_HOOK_INFO_SIZE];
+
+static uint8_t last_wakelock_state[32] = {
+ DEFAULT_WAKELOCK & 0x01, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+static uint32_t last_acquire_wakelock_time[32] = {0};
+static uint32_t hold_wakelock_time[32] = {0};
+static uint32_t base_sys_time = 0;
+
+static uint32_t sys_sleep_time = 0;
+
+unsigned char reserve_pll = 0;
+unsigned char generate_wakelock_stats = 0;
+
+
+/* -------- FreeRTOS macro implementation -------- */
+
+int cmsis_ready_to_sleep() {
+ return wakelock == 0;
+}
+
+void pmu_acquire_wakelock(uint32_t lock_id) {
+
+ wakelock |= BIT(lock_id);
+
+ if (generate_wakelock_stats) {
+ uint32_t i;
+
+ //uint32_t current_timestamp = osKernelSysTick();
+ uint32_t current_timestamp = osKernelGetSysTimerCount();
+
+ for (i=0; i<32; i++) {
+ if ( (1<<i & BIT(lock_id)) && (last_wakelock_state[i] == 0) ) {
+ last_acquire_wakelock_time[i] = current_timestamp;
+ last_wakelock_state[i] = 1;
+ }
+ }
+ }
+}
+
+void pmu_release_wakelock(uint32_t lock_id) {
+ wakelock &= ~BIT(lock_id);
+
+ if (generate_wakelock_stats) {
+ uint32_t i;
+
+ //uint32_t current_timestamp = osKernelSysTick();
+ uint32_t current_timestamp = osKernelGetSysTimerCount();
+
+ for (i=0; i<32; i++) {
+ if ( (1<<i & BIT(lock_id)) && (last_wakelock_state[i] == 1) ) {
+ hold_wakelock_time[i] += current_timestamp - last_acquire_wakelock_time[i];
+ last_wakelock_state[i] = 0;
+ }
+ }
+ }
+}
+
+uint32_t pmu_get_wakelock_status() {
+ return wakelock;
+}
+
+void pmu_enable_wakelock_stats(unsigned char enable) {
+ generate_wakelock_stats = enable;
+}
+
+void pmu_get_wakelock_hold_stats( char *pcWriteBuffer ) {
+ uint32_t i;
+
+ //uint32_t current_timestamp = osKernelSysTick();
+ uint32_t current_timestamp = osKernelGetSysTimerCount();
+
+ *pcWriteBuffer = 0x00;
+
+ if (generate_wakelock_stats) {
+ // print header
+ sprintf(pcWriteBuffer, "wakelock_id\tholdtime\r\n");
+ pcWriteBuffer += strlen( pcWriteBuffer );
+
+ for (i=0; i<32; i++) {
+ if (last_wakelock_state[i] == 1) {
+ sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i]));
+ } else {
+ if (hold_wakelock_time[i] > 0) {
+ sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i]);
+ }
+ }
+ pcWriteBuffer += strlen( pcWriteBuffer );
+ }
+ sprintf(pcWriteBuffer, "time passed: %d ms, system sleep %d ms\r\n", current_timestamp - base_sys_time, sys_sleep_time);
+ }
+}
+
+void pmu_clean_wakelock_stat() {
+ uint32_t i;
+
+ //base_sys_time = osKernelSysTick();
+ base_sys_time = osKernelGetSysTimerCount();
+
+ for (i=0; i<32; i++) {
+ hold_wakelock_time[i] = 0;
+ if (last_wakelock_state[i] == 1) {
+ last_acquire_wakelock_time[i] = base_sys_time;
+ }
+ }
+ sys_sleep_time = 0;
+}
+
+void pmu_add_wakeup_event(uint32_t event) {
+ wakeup_event |= event;
+}
+
+void pmu_del_wakeup_event(uint32_t event) {
+ wakeup_event &= ~event;
+ // To fulfill tickless design, system timer is required to be wakeup event
+ wakeup_event |= SLEEP_WAKEUP_BY_STIMER;
+}
+
+void pmu_register_sleep_callback(uint32_t nDeviceId, PSM_HOOK_FUN sleep_hook_fun, void* sleep_param_ptr, PSM_HOOK_FUN wakeup_hook_fun, void* wakeup_param_ptr) {
+ uint32_t i;
+ for (i=0; i<psm_dd_hook_info_size; i++) {
+ if (psm_dd_hook_infos[i].nDeviceId == nDeviceId) {
+ psm_dd_hook_infos[i].sleep_hook_fun = sleep_hook_fun;
+ psm_dd_hook_infos[i].sleep_param_ptr = sleep_param_ptr;
+ psm_dd_hook_infos[i].wakeup_hook_fun = wakeup_hook_fun;
+ psm_dd_hook_infos[i].wakeup_param_ptr = wakeup_param_ptr;
+ break;
+ }
+ }
+ if (i == psm_dd_hook_info_size) {
+ psm_dd_hook_infos[psm_dd_hook_info_size].nDeviceId = nDeviceId;
+ psm_dd_hook_infos[psm_dd_hook_info_size].sleep_hook_fun = sleep_hook_fun;
+ psm_dd_hook_infos[psm_dd_hook_info_size].sleep_param_ptr = sleep_param_ptr;
+ psm_dd_hook_infos[psm_dd_hook_info_size].wakeup_hook_fun = wakeup_hook_fun;
+ psm_dd_hook_infos[psm_dd_hook_info_size].wakeup_param_ptr = wakeup_param_ptr;
+ psm_dd_hook_info_size++;
+ }
+}
+
+void pmu_unregister_sleep_callback(uint32_t nDeviceId) {
+ uint32_t i;
+ for (i=0; i<psm_dd_hook_info_size; i++) {
+ if (psm_dd_hook_infos[i].nDeviceId == nDeviceId) {
+ if (psm_dd_hook_info_size > 1) {
+ // if we have more than 2 items, just swap the last item into current slot
+ psm_dd_hook_infos[i].nDeviceId = psm_dd_hook_infos[psm_dd_hook_info_size-1].nDeviceId;
+ psm_dd_hook_infos[i].sleep_hook_fun = psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_hook_fun;
+ psm_dd_hook_infos[i].sleep_param_ptr = psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_param_ptr;
+ psm_dd_hook_infos[i].wakeup_hook_fun = psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_hook_fun;
+ psm_dd_hook_infos[i].wakeup_param_ptr = psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_param_ptr;
+
+ // Then erase the last item
+ psm_dd_hook_infos[psm_dd_hook_info_size-1].nDeviceId = 0;
+ psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_hook_fun = NULL;
+ psm_dd_hook_infos[psm_dd_hook_info_size-1].sleep_param_ptr = NULL;
+ psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_hook_fun = NULL;
+ psm_dd_hook_infos[psm_dd_hook_info_size-1].wakeup_param_ptr = NULL;
+ } else {
+ // we only have one item, just erase it
+ psm_dd_hook_infos[i].nDeviceId = 0;
+ psm_dd_hook_infos[i].sleep_hook_fun = NULL;
+ psm_dd_hook_infos[i].sleep_param_ptr = NULL;
+ psm_dd_hook_infos[i].wakeup_hook_fun = NULL;
+ psm_dd_hook_infos[i].wakeup_param_ptr = NULL;
+ }
+ psm_dd_hook_info_size--;
+ break;
+ }
+ }
+}
+
+void pmu_set_pll_reserved(unsigned char reserve) {
+ reserve_pll = reserve;
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/os/cmsis_pmu_8195a.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,110 @@
+#ifndef __FREERTOS_PMU_H_
+#define __FREERTOS_PMU_H_
+
+#if DEVICE_SLEEP
+#include "sleep_ex_api.h"
+
+#ifndef BIT
+#define BIT(n) (1<<n)
+#endif
+
+#ifdef CONFIG_PLATFORM_8195A
+#define DEFAULT_WAKEUP_EVENT (SLEEP_WAKEUP_BY_STIMER | SLEEP_WAKEUP_BY_GTIMER | SLEEP_WAKEUP_BY_GPIO_INT | SLEEP_WAKEUP_BY_WLAN)
+
+typedef enum PMU_DEVICE {
+
+ PMU_OS = 0,
+ PMU_WLAN_DEVICE = 1,
+ PMU_LOGUART_DEVICE = 2,
+ PMU_SDIO_DEVICE = 3,
+
+ PMU_DEV_USER_BASE= 16,
+
+ PMU_MAX = 31
+
+} PMU_DEVICE;
+
+// default locked by OS and not to sleep until OS release wakelock in somewhere
+#define DEFAULT_WAKELOCK (BIT(PMU_OS))
+typedef uint32_t (*PSM_HOOK_FUN)( unsigned int, void* param_ptr );
+#endif
+
+/** Acquire wakelock
+ *
+ * A wakelock is a 32-bit map. Each module own 1 bit in this bit map.
+ * FreeRTOS tickless reference the wakelock and decide that if it can or cannot enter sleep state.
+ * If any module acquire and hold a bit in wakelock, then the whole system won't enter sleep state.
+ *
+ * If wakelock is not equals to 0, then the system won't enter sleep.
+ *
+ * @param nDeviceId : The bit which is attempt to add into wakelock
+ */
+void pmu_acquire_wakelock(uint32_t nDeviceId);
+
+/** Release wakelock
+ *
+ * If wakelock equals to 0, then the system may enter sleep state if it is in idle state.
+ *
+ * @param nDeviceId : The bit which is attempt to remove from wakelock
+ */
+void pmu_release_wakelock(uint32_t nDeviceId);
+
+/** Get current wakelock bit map value
+ *
+ * @return : the current wakelock bit map value
+ */
+uint32_t pmu_get_wakelock_status(void);
+
+#if (configGENERATE_RUN_TIME_STATS == 1)
+
+/** enable to keep wakelock stats
+ *
+ */
+void pmu_enable_wakelock_stats( unsigned char enable );
+
+/** Get text report that contain the statics of wakelock holding time
+ *
+ * Each time a module acquries or releases wakelock, a holding time is calculated and sum up to a table.
+ * It is for debug that which module is power saving killer.
+ *
+ * @param pcWriteBuffer : The char buffer that contain the report
+ */
+void pmu_get_wakelock_hold_stats( char *pcWriteBuffer );
+
+/** Recalculate the wakelock statics
+ *
+ * By default the wakelock statics is calculated from system boot up.
+ * If we want to debug power saving killer from a specified timestamp, we can reset the statics.
+ */
+void pmu_clean_wakelock_stat(void);
+
+#endif
+
+/**
+ * @brief set system active time, system can not sleep beore timeout.
+ * @param timeout: system can not sleep beore timeout, unit is ms.
+ * @retval status value:
+ * - 0: _FAIL
+ * - 1: _SUCCESS
+ */
+uint32_t pmu_set_sysactive_time(uint32_t timeout_ms);
+
+void pmu_add_wakeup_event(uint32_t event);
+void pmu_del_wakeup_event(uint32_t event);
+
+#if (defined CONFIG_PLATFORM_8195A) || (defined CONFIG_PLATFORM_8195BHP) || (defined CONFIG_PLATFORM_8710C) || (defined CONFIG_PLATFORM_8711B)
+void pmu_register_sleep_callback(uint32_t nDeviceId, PSM_HOOK_FUN sleep_hook_fun, void* sleep_param_ptr, PSM_HOOK_FUN wakeup_hook_fun, void* wakeup_param_ptr);
+void pmu_unregister_sleep_callback(uint32_t nDeviceId);
+#endif
+
+#ifdef CONFIG_PLATFORM_8195A
+/** Set PLL reserved or not when sleep is called
+ *
+ * @param reserve: true for sleep with PLL reserve
+ */
+void pmu_set_pll_reserved(unsigned char reserve);
+#endif
+
+#endif
+
+#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,19 +1,22 @@
/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
*
- * http://www.apache.org/licenses/LICENSE-2.0
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
*
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
******************************************************************************/
-
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
@@ -34,7 +37,7 @@
#undef _FAIL
#define _FAIL 0
-#ifndef FALSE
+#ifndef FALSE
#define FALSE 0
#endif
@@ -63,6 +66,7 @@
typedef unsigned long long __uint64_t;
#endif
+#if defined(CONFIG_MBED_ENABLED)
typedef int8_t s8;
typedef uint8_t u8;
typedef int16_t s16;
@@ -71,17 +75,17 @@
typedef uint32_t u32;
typedef int64_t s64;
typedef uint64_t u64;
-
-#ifdef CONFIG_MBED_ENABLED
-#ifndef BOOL
-typedef unsigned int BOOL;
+#else
+#define s8 int8_t
+#define u8 uint8_t
+#define s16 int16_t
+#define u16 uint16_t
+#define s32 int32_t
+#define u32 uint32_t
+#define s64 int64_t
+#define u64 uint64_t
#endif
-#ifndef __cplusplus
-#ifndef bool
-typedef unsigned char bool;
-#endif
-#endif
-#else
+
#ifndef BOOL
typedef unsigned char BOOL;
#endif
@@ -90,14 +94,17 @@
typedef unsigned char bool;
#endif
#endif
-#endif
#define UCHAR uint8_t
#define USHORT uint16_t
-//#define UINT uint32_t
-#define ULONG uint32_t
-typedef struct { volatile int counter; } atomic_t;
+#if defined(CONFIG_MBED_ENABLED)
+typedef unsigned int UINT;
+#else
+#define UINT uint32_t
+#endif
+
+#define ULONG uint32_t
enum _RTK_STATUS_ {
_EXIT_SUCCESS = 0,
@@ -198,13 +205,20 @@
#define _LONG_CALL_
#define _LONG_CALL_ROM_
#define _WEAK __weak
+#if (__VER__ >= 8000000)
+#define _USED __attribute__((used))
+#else
+#define _USED _Pragma("__root")
+#endif
+
#elif defined(__CC_ARM)
// defined in rtl8195a_compiler.h
#define SECTION(_name) __attribute__ ((section(_name)))
#define _LONG_CALL_ __attribute__ ((long_call))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
-
#define _LONG_CALL_ROM_ _LONG_CALL_
+#define _WEAK __attribute__ ((weak))
+#define _USED __attribute__((used))
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define SECTION(_name) __attribute__ ((__section__(_name)))
@@ -222,6 +236,7 @@
#define _LONG_CALL_ROM_ _LONG_CALL_
#endif
#define _WEAK __attribute__ ((weak))
+#define _USED __attribute__((used))
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
@@ -239,6 +254,7 @@
#define _LONG_CALL_ROM_ _LONG_CALL_
#endif
#define _WEAK __attribute__ ((weak))
+#define _USED __attribute__((used))
#endif
@@ -526,11 +542,9 @@
#define __restrict /* Ignore */
#endif
-/* in rtl8195a_trap.h
typedef struct _RAM_START_FUNCTION_ {
VOID (*RamStartFun) (VOID);
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
-*/
typedef struct _RAM_FUNCTION_START_TABLE_ {
VOID (*RamStartFun) (VOID);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h Thu Nov 08 11:46:34 2018 +0000
@@ -1,21 +1,17 @@
-/*******************************************************************************
- *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
- * SPDX-License-Identifier: LicenseRef-PBL
- *
- * Licensed under the Permissive Binary License, Version 1.0 (the "License");
- * you may not use this file except in compliance with the License.
- *
- * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
- *
- * See the License for the specific language governing permissions and limitations under the License.
- *******************************************************************************
+/*
+ * Routines to access hardware
+ *
+ * Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ * This module is a confidential and proprietary property of RealTek and
+ * possession or use of this module requires written permission of RealTek.
*/
#ifndef _SECTION_CONFIG_H_
#define _SECTION_CONFIG_H_
+#include "basic_types.h"
#include "platform_autoconf.h"
-#include "basic_types.h"
#define RAM_DEDECATED_VECTOR_TABLE_SECTION \
SECTION(".ram_dedecated_vector_table")
@@ -131,16 +127,20 @@
#define E_CUT_ROM_DATA_SECTION \
SECTION(".cute.ram.data")
-//#define FWUROM_DATA_SECTION SECTION(".fwurom.data")
-
-//#define FWUROM_RODATA_SECTION SECTION(".fwurom.rodata")
-
+/*
+#define FWUROM_DATA_SECTION \
+ SECTION(".fwurom.data")
+
+#define FWUROM_RODATA_SECTION \
+ SECTION(".fwurom.rodata")
+*/
+
#define FWUROM_TEXT_SECTION \
SECTION(".fwurom.text")
-
+
#define XMPORT_ROM_TEXT_SECTION \
SECTION(".xmportrom.text")
-
+
#define XDMROM_TEXT_SECTION \
SECTION(".xmodemrom.text")
@@ -149,7 +149,6 @@
#if defined (__CC_ARM)
#define IMAGE1_VALID_PATTEN_SECTION \
SECTION(".image1.validate.rodata") __attribute__((used))
-
#define IMAGE2_VALID_PATTEN_SECTION \
SECTION(".image2.validate.rodata") __attribute__((used))
#else
@@ -230,7 +229,6 @@
#define SRAM_BF_DATA_SECTION \
SECTION(".bfsram.data")
-
#define START_RAM_FUN_SECTION \
SECTION(".start.ram.data")
@@ -288,10 +286,10 @@
#if defined (__CC_ARM)
#define IMAGE2_START_RAM_FUN_SECTION \
- SECTION(".image2.ram.data") __attribute__((used))
+ SECTION(".image2.ram.data") __attribute__((used))
#else
#define IMAGE2_START_RAM_FUN_SECTION \
- SECTION(".image2.ram.data")
+ SECTION(".image2.ram.data")
#endif
#define SDRAM_DATA_SECTION \
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/rtl_std_lib/include/rtl_lib.h Thu Sep 06 13:40:20 2018 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,155 +0,0 @@
-/******************************************************************************
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************/
-
-#ifndef _RTL_LIB_H_
-#define _RTL_LIB_H_
-
-
-#include <basic_types.h>
-#include <diag.h>
-
-
-extern int __rtl_errno;
-
-
-void init_rom_libgloss_ram_map(void);
-
-
-//
-// RTL library functions for Libc::stdio
-//
-
-extern int rtl_printf(IN const char* fmt, ...);
-extern int rtl_vprintf(const char *fmt, void *param);
-extern int rtl_sprintf(char* str, const char* fmt, ...);
-extern int rtl_snprintf(char* str, size_t size, const char* fmt, ...);
-extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param);
-
-//
-// RTL library functions for string
-//
-
-extern void * rtl_memchr(const void * src_void , int c , size_t length);
-extern int rtl_memcmp(const void * m1 , const void * m2 , size_t n);
-extern void * rtl_memcpy(void * dst0 , const void * src0 , size_t len0);
-extern void * rtl_memmove( void * dst_void , const void * src_void , size_t length);
-extern void * rtl_memset(void * m , int c , size_t n);
-extern char * rtl_strcat(char * s1 , const char * s2);
-extern char * rtl_strchr(const char *s1 , int i);
-extern int rtl_strcmp(const char *s1 , const char *s2);
-extern char* rtl_strcpy(char *dst0 , const char *src0);
-extern size_t rtl_strlen(const char *str);
-extern char * rtl_strncat(char * s1 , const char * s2 , size_t n);
-extern int rtl_strncmp(const char *s1 , const char *s2 , size_t n);
-extern char * rtl_strncpy(char * dst0 , const char * src0 , size_t count);
-extern char * rtl_strstr(const char *searchee , const char *lookfor);
-extern char * rtl_strsep(char **source_ptr , const char *delim);
-extern char * rtl_strtok(char * s , const char * delim);
-
-//
-// RTL library functions for math
-//
-
-
-extern double rtl_fabs(double);
-extern float rtl_fabsf(float a);
-extern float rtl_cos_f32(float a);
-extern float rtl_sin_f32(float a);
-
-extern float rtl_fadd(float a, float b);
-extern float rtl_fsub(float a, float b);
-extern float rtl_fmul(float a, float b);
-extern float rtl_fdiv(float a, float b);
-
-extern int rtl_fcmplt(float a, float b);
-extern int rtl_fcmpgt(float a, float b);
-
-
-
-
-
-//
-// RTL eabi functions
-
-extern double rtl_ftod(float f);
-
-extern double rtl_ddiv(double a, double b);
-
-
-//
-// Macro Library Functions
-//
-
-typedef union
-{
- float value;
- u32 word;
-} ieee_float_shape_type;
-
-/* Get a 32 bit int from a float. */
-
-#define GET_FLOAT_WORD(i,d) \
-do { \
- ieee_float_shape_type gf_u; \
- gf_u.value = (d); \
- (i) = gf_u.word; \
-} while (0)
-
-/* Set a float from a 32 bit int. */
-
-#define SET_FLOAT_WORD(d,i) \
-do { \
- ieee_float_shape_type sf_u; \
- sf_u.word = (i); \
- (d) = sf_u.value; \
-} while (0)
-
-static inline
-float rtl_nanf(void)
-{
- float x;
-
- SET_FLOAT_WORD(x,0x7fc00000);
- return x;
-}
-
-
-//
-// Library Test functions
-//
-
-extern int rtl_lib_test(IN u16 argc, IN u8 *argv[]);
-extern int rtl_math_test(IN u16 argc, IN u8 *argv[]);
-extern int rtl_string_test(IN u16 argc, IN u8 *argv[]);
-
-
-//
-// Macro functions
-//
-
-#undef dbg_printf
-#define dbg_printf(fmt, args...) \
- rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
-
-
-#undef err_printf
-#define err_printf(fmt, args...) \
- rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
-
-
-#endif /* _RTL_LIB_H_ */
-
--- a/targets/TARGET_Realtek/mbed_rtx.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Realtek/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000 @@ -1,3 +1,4 @@ + /* mbed Microcontroller Library * Copyright (c) 2013-2016 Realtek Semiconductor Corp. *
--- a/targets/TARGET_STM/PeripheralPins.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/PeripheralPins.h Thu Nov 08 11:46:34 2018 +0000 @@ -80,4 +80,10 @@ extern const PinMap PinMap_CAN_TD[]; #endif +#ifdef DEVICE_QSPI +extern const PinMap PinMap_QSPI_DATA[]; +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; #endif + +#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/STM32F0xx.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_GCC_ARM/STM32F0xx.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ ; 45 vectors = 180 bytes (0xB4) 8-byte aligned = 0xB8 (0xB4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB8) (0x2000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/stm32f0xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_ARM_STD/stm32f0xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 45 vectors = 180 bytes (0xB4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xB4) (0x2000-0xB4) { ; RW data
+ ; 45 vectors = 180 bytes (0xB4); 8-byte aligned = 0xB8 (0xB4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB8) (0x2000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/STM32F030X8.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/TOOLCHAIN_GCC_ARM/STM32F030X8.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/STM32F031X6.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/STM32F031X6.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/STM32F042X6.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/STM32F042X6.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/STM32F070XB.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/STM32F070XB.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,4 +1,5 @@
/* Linker script to configure memory regions. */
+StackSize = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,21 +107,35 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
+ /* .stack section doesn't contains any symbols. It is only
+ * used for linker to reserve space for the main stack section
+ */
+ .stack (NOLOAD):
+ {
+ __StackLimit = .;
+ *(.stack*);
+ . += StackSize - (. - __StackLimit);
+ } > RAM
+ __StackTop = ADDR(.stack) + SIZEOF(.stack);
+ _estack = __StackTop;
+ __StackLimit = ADDR(.stack);
+ PROVIDE(__stack = __StackTop);
+
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
@@ -129,25 +144,13 @@
{
__end__ = .;
end = __end__;
- *(.heap*)
+ *(.heap*);
+ . += (ORIGIN(RAM) + LENGTH(RAM) - .);
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_GCC_ARM/STM32F0xxx_retarget.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <errno.h>
+#include "stm32f0xx.h"
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+/* Support heap with two-region model
+ *
+ * The default implementation of _sbrk() (in mbed_retarget.cpp) for GCC_ARM requires one-region
+ * model (heap and stack share one region), which doesn't fit two-region model (heap and stack
+ * are two distinct regions)
+ * Hence, override _sbrk() here to support heap with two-region model.
+ */
+void *_sbrk(int incr)
+{
+ static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+ uint32_t heap_ind_old = heap_ind;
+ uint32_t heap_ind_new = heap_ind_old + incr;
+
+ if (heap_ind_new > (uint32_t) &__mbed_krbs_start) {
+ errno = ENOMEM;
+ return (void *) -1;
+ }
+
+ heap_ind = heap_ind_new;
+
+ return (void *) heap_ind_old;
+}
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/stm32f070xb.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_IAR/stm32f070xb.icf Thu Nov 08 11:46:34 2018 +0000 @@ -10,7 +10,7 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/ define memory mem with size = 4G;
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/STM32F072XB.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/STM32F072XB.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,4 +1,5 @@
/* Linker script to configure memory regions. */
+StackSize = 0x400;
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,21 +107,35 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
+ /* .stack section doesn't contains any symbols. It is only
+ * used for linker to reserve space for the main stack section
+ */
+ .stack (NOLOAD):
+ {
+ __StackLimit = .;
+ *(.stack*);
+ . += StackSize - (. - __StackLimit);
+ } > RAM
+ __StackTop = ADDR(.stack) + SIZEOF(.stack);
+ _estack = __StackTop;
+ __StackLimit = ADDR(.stack);
+ PROVIDE(__stack = __StackTop);
+
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
@@ -129,25 +144,13 @@
{
__end__ = .;
end = __end__;
- *(.heap*)
+ *(.heap*);
+ . += (ORIGIN(RAM) + LENGTH(RAM) - .);
__HeapLimit = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_GCC_ARM/STM32F0xxx_retarget.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <errno.h>
+#include "stm32f0xx.h"
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+/* Support heap with two-region model
+ *
+ * The default implementation of _sbrk() (in mbed_retarget.cpp) for GCC_ARM requires one-region
+ * model (heap and stack share one region), which doesn't fit two-region model (heap and stack
+ * are two distinct regions)
+ * Hence, override _sbrk() here to support heap with two-region model.
+ */
+void *_sbrk(int incr)
+{
+ static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+ uint32_t heap_ind_old = heap_ind;
+ uint32_t heap_ind_new = heap_ind_old + incr;
+
+ if (heap_ind_new > (uint32_t) &__mbed_krbs_start) {
+ errno = ENOMEM;
+ return (void *) -1;
+ }
+
+ heap_ind = heap_ind_new;
+
+ return (void *) heap_ind_old;
+}
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/stm32f072xb.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/TOOLCHAIN_IAR/stm32f072xb.icf Thu Nov 08 11:46:34 2018 +0000 @@ -10,7 +10,7 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/ define memory mem with size = 4G;
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/STM32F091XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/STM32F091XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Thu Nov 08 11:46:34 2018 +0000 @@ -148,7 +148,6 @@ #endif /* STM32F0 HAL doesn't provide this API called in rtc_api.c */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) #define RTC_WKUP_IRQn RTC_IRQn #endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,19 +26,35 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
+ *
+ * Automatically generated from STM32F103C(8-B)Tx.xml
*/
#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-// If you change them, you will have also to modify the corresponding xxx_api.c file
-// for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
//*** ADC ***
-const PinMap PinMap_ADC[] = {
+MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
@@ -55,7 +71,7 @@
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
- {NC, NC, 0}
+ {NC, NC, 0}
};
const PinMap PinMap_ADC_Internal[] = {
@@ -66,118 +82,135 @@
//*** I2C ***
-const PinMap PinMap_I2C_SDA[] = {
- {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
- {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1
- {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
};
-const PinMap PinMap_I2C_SCL[] = {
- {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
- {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1
- {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
};
//*** PWM ***
// TIM4 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
- {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM2_CH2 - Default
- {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM2_CH3 - Default (warning: not connected on D1 per default)
- {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM2_CH4 - Default (warning: not connected on D0 per default)
- {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM3_CH1 - Default
- {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM3_CH2 - Default
-// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 1, 1)}, // TIM1_CH1N - GPIO_PartialRemap_TIM1
- {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM1_CH1 - Default
- {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM1_CH2 - Default
- {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3 - Default
- {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4 - Default
- {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1_ETR - GPIO_FullRemap_TIM2
-
- {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3 - Default
-// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 2, 1)}, // TIM1_CH2N - GPIO_PartialRemap_TIM1
- {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4 - Default
-// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 3, 1)}, // TIM1_CH3N - GPIO_PartialRemap_TIM1
- {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 - GPIO_FullRemap_TIM2
- {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1 - GPIO_PartialRemap_TIM3
- {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2 - GPIO_PartialRemap_TIM3
-// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM4_CH1 - Default (used by ticker)
-// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM4_CH2 - Default (used by ticker)
-// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM4_CH3 - Default (used by ticker)
-// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM4_CH4 - Default (used by ticker)
- {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 3, 0)}, // TIM2_CH3 - GPIO_FullRemap_TIM2
- {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 4, 0)}, // TIM2_CH4 - GPIO_FullRemap_TIM2
- {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 1)}, // TIM1_CH1N - Default
- {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 1)}, // TIM1_CH2N - Default
- {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 1)}, // TIM1_CH3N - Default
-
- {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 1, 0)}, // TIM3_CH1 - GPIO_FullRemap_TIM3
- {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 2, 0)}, // TIM3_CH2 - GPIO_FullRemap_TIM3
- {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 3, 0)}, // TIM3_CH3 - GPIO_FullRemap_TIM3
- {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 4, 0)}, // TIM3_CH4 - GPIO_FullRemap_TIM3
- {NC, NC, 0}
+// You have to comment all PWM_4
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM2_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM2_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM2_CH3
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM2_CH4
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM1_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM1_CH2
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 6, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2
+// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM4_CH1
+// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM4_CH2
+// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM4_CH3
+// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM4_CH4
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 1)}, // TIM1_CH3N
+ {NC, NC, 0}
};
//*** SERIAL ***
-const PinMap PinMap_UART_TX[] = {
- {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
- {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
- {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1
- {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
- {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3
+ {NC, NC, 0}
};
-const PinMap PinMap_UART_RX[] = {
- {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
- {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
- {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1
- {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
- {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {NC, NC, 0}
};
//*** SPI ***
-const PinMap PinMap_SPI_MOSI[] = {
- {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1
- {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
};
-const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1
- {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
};
-const PinMap PinMap_SPI_SCLK[] = {
- {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1
- {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {NC, NC, 0}
};
-const PinMap PinMap_SPI_SSEL[] = {
- {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1
- {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {NC, NC, 0}
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 10)},
+ {NC, NC, 0}
};
-const PinMap PinMap_CAN_RD[] = {
- {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},
- {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)},
- {NC, NC, 0}
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 10)},
+ {NC, NC, 0}
};
-
-const PinMap PinMap_CAN_TD[] = {
- {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
- {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
- {NC, NC, 0}
-};
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -38,6 +38,13 @@
#endif
typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
@@ -46,6 +53,7 @@
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
+ PA_7_ALT0 = 0x07 | ALT0,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@@ -56,7 +64,9 @@
PA_15 = 0x0F,
PB_0 = 0x10,
+ PB_0_ALT0 = 0x10 | ALT0,
PB_1 = 0x11,
+ PB_1_ALT0 = 0x11 | ALT0,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,9 @@
/* Linker script to configure memory regions. */
+/* 0xEC reserved for vectors - 8byte aligned = 0xF0 */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x200000EC, LENGTH = 20K - 0xEC
+ RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_ARM_MICRO/stm32f100xb.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_ARM_MICRO/stm32f100xb.sct Thu Nov 08 11:46:34 2018 +0000
@@ -35,8 +35,8 @@
.ANY (+RO)
}
- ; 77 vectors (16 core + 61 peripheral) * 4 bytes = 308 bytes to reserve (0x134)
- RW_IRAM1 (0x20000000+0x134) (0x2000-0x134) { ; RW data
+ ; 77 vectors (16 core + 61 peripheral) * 4 bytes = 308 bytes to reserve (0x134) 8-byte aligned = 0x138
+ RW_IRAM1 (0x20000000+0x138) (0x2000-0x138) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_ARM_STD/stm32f100xb.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_ARM_STD/stm32f100xb.sct Thu Nov 08 11:46:34 2018 +0000
@@ -35,8 +35,8 @@
.ANY (+RO)
}
- ; 77 vectors (16 core + 61 peripheral) * 4 bytes = 308 bytes to reserve (0x134)
- RW_IRAM1 (0x20000000+0x134) (0x2000-0x134) { ; RW data
+ ; 77 vectors (16 core + 61 peripheral) * 4 bytes = 308 bytes to reserve (0x134) 8-byte aligned = 0x138
+ RW_IRAM1 (0x20000000+0x138) (0x2000-0x138) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_GCC_ARM/STM32F100.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/TOOLCHAIN_GCC_ARM/STM32F100.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -117,12 +117,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct Thu Nov 08 11:46:34 2018 +0000
@@ -35,8 +35,8 @@
.ANY (+RO)
}
- ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
- RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
+ ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC) 8-byte aligned = 0xF0
+ RW_IRAM1 (0x20000000+0xF0) (0x5000-0xF0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_ARM_STD/stm32f103xb.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_ARM_STD/stm32f103xb.sct Thu Nov 08 11:46:34 2018 +0000
@@ -35,8 +35,8 @@
.ANY (+RO)
}
- ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC)
- RW_IRAM1 (0x20000000+0xEC) (0x5000-0xEC) { ; RW data
+ ; 59 vectors (16 core + 43 peripheral) * 4 bytes = 236 bytes to reserve (0xEC) 8-byte aligned = 0xF0
+ RW_IRAM1 (0x20000000+0xF0) (0x5000-0xF0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_GCC_ARM/STM32F103XB.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,9 @@
/* Linker script to configure memory regions. */
+/* 0xEC reserved for vectors; 8-byte aligned = 0xF0 */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
- RAM (rwx) : ORIGIN = 0x200000EC, LENGTH = 20K - 0xEC
+ RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_IAR/stm32f103xb.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/TOOLCHAIN_IAR/stm32f103xb.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,8 +7,8 @@ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x200000EB; -define symbol __ICFEDIT_region_RAM_start__ = 0x200000EC; +define symbol __ICFEDIT_region_NVIC_end__ = 0x200000F0 - 0x1; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000F0; /* 8-byte aligned (0xEC) = 0xF0 */ define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Thu Nov 08 11:46:34 2018 +0000 @@ -137,8 +137,4 @@ } #endif -/* STM32F1 HAL doesn't provide this API called in rtc_api.c */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) - #endif -
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c Thu Nov 08 11:46:34 2018 +0000
@@ -188,8 +188,6 @@
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
-static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
-static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc);
static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter);
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
@@ -1355,7 +1353,7 @@
* the configuration information for RTC.
* @retval Time counter
*/
-static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
+uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
{
uint16_t high1 = 0U, high2 = 0U, low = 0U;
uint32_t timecounter = 0U;
@@ -1385,10 +1383,10 @@
* @param TimeCounter: Counter to write in RTC_CNT registers
* @retval HAL status
*/
-static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter)
+HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h Thu Nov 08 11:46:34 2018 +0000 @@ -518,6 +518,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); + +uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter); /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/stm32f207xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/stm32f207xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -34,8 +34,8 @@
.ANY (+RO)
}
- ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184)
- RW_IRAM1 (0x20000000+0x184) (0x00020000-0x184) { ; RW data
+ ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184) 8-byte aligned = 0x188
+ RW_IRAM1 (0x20000000+0x188) (0x00020000-0x188) { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S Thu Nov 08 11:46:34 2018 +0000
@@ -3,7 +3,7 @@
;* Author : MCD Application Team
;* Version : V2.1.1
;* Date : 20-November-2015
-;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain.
+;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
@@ -13,7 +13,7 @@
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
-;
+;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
@@ -35,33 +35,11 @@
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
+;
;*******************************************************************************
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20020000
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
PRESERVE8
THUMB
@@ -404,33 +382,6 @@
ENDP
ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
+ END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/stm32f207xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/stm32f207xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2016, STMicroelectronics
@@ -27,15 +28,23 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-LR_IROM1 0x08000000 0x00100000 { ; load region size_region
- ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184)
- RW_IRAM1 (0x20000000+0x184) (0x00020000-0x184) { ; RW data
+ ; 97 vectors * 4 bytes = 388 bytes to reserve (0x184) 8-byte aligned = 0x188 (0x184 + 0x4)
+ RW_IRAM1 (0x20000000+0x188) (0x00020000-0x188) { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/STM32F207ZGTx_FLASH.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/STM32F207ZGTx_FLASH.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,16 +1,25 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x8000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
/* Linker script to configure memory regions. */
/* 97 vectors * 4 bytes = 388 bytes to reserve (0x184) */
+/* 8-byte aligned(0x184) = 0x188 */
MEMORY
-{
- FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
- RAM (rwx) : ORIGIN = 0x20000184, LENGTH = 128K - 0x184
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
- *
+ *
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
@@ -85,13 +94,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +108,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +116,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +125,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/stm32f207xx.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/stm32f207xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -1,7 +1,10 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
/* [ROM = 1024kb = 0x100000] */
-define symbol __intvec_start__ = 0x08000000;
+define symbol __intvec_start__ = MBED_APP_START;
define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x080FFFFF;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 97 vectors = 388 bytes (0x184) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
@@ -15,9 +18,10 @@
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x4000;
-define symbol __size_heap__ = 0x8000;
+/* Stack: 1024B */
+/* Heap: 64kB */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0xF000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -30,6 +30,7 @@
**/
#include "stm32f2xx.h"
+#include "nvic_addr.h"
#include "mbed_error.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
@@ -88,7 +89,7 @@
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
#endif
}
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_GCC_ARM/STM32F302X8.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_GCC_ARM/STM32F302X8.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_GCC_ARM/STM32F303X8.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_GCC_ARM/STM32F303X8.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_GCC_ARM/STM32F303XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_GCC_ARM/STM32F303XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
+ ; 101 vectors = 404 bytes (0x194) 8-byte aligned = 0x198 (0x194 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x10000-0x198) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
+ ; 101 vectors = 404 bytes (0x194) 8-byte aligned = 0x198 (0x194 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x10000-0x198) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,4 +1,5 @@
/* Linker script to configure memory regions. */
+/* 0x194 resevered for vectors; 8-byte aligned = 0x198 (0x194 + 0x4)*/
#ifndef MBED_APP_START
#define MBED_APP_START 0x08000000
#endif
@@ -11,7 +12,7 @@
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
- RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64K - 0x194
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 64K - (0x194+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -93,13 +94,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +108,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +116,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +125,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_GCC_ARM/STM32F334X8.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_GCC_ARM/STM32F334X8.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c Thu Nov 08 11:46:34 2018 +0000
@@ -34,6 +34,7 @@
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
+#include "mbed_debug.h"
#include "PeripheralPins.h"
void analogin_init(analogin_t *obj, PinName pin)
@@ -211,16 +212,27 @@
return 0;
}
- HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+ if (HAL_ADC_ConfigChannel(&obj->handle, &sConfig) != HAL_OK) {
+ debug("HAL_ADC_ConfigChannel issue\n");;
+ }
- HAL_ADC_Start(&obj->handle); // Start conversion
+ if (HAL_ADC_Start(&obj->handle) != HAL_OK) {
+ debug("HAL_ADC_Start issue\n");;
+ }
+
+ uint16_t MeasuredValue = 0;
- // Wait end of conversion and get value
if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
- return (uint16_t)HAL_ADC_GetValue(&obj->handle);
+ MeasuredValue = (uint16_t)HAL_ADC_GetValue(&obj->handle);
} else {
- return 0;
+ debug("HAL_ADC_PollForConversion issue\n");
}
+
+ if (HAL_ADC_Stop(&obj->handle) != HAL_OK) {
+ debug("HAL_ADC_Stop issue\n");;
+ }
+
+ return MeasuredValue;
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Thu Nov 08 11:46:34 2018 +0000 @@ -145,8 +145,4 @@ } #endif -/* STM32F3 HAL doesn't provide this API called in rtc_api.c */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) - #endif -
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -87,13 +87,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,7 +101,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -109,7 +109,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -117,11 +117,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -87,13 +87,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,7 +101,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -109,7 +109,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -117,11 +117,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/STM32F405.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_GCC_ARM/STM32F405.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -115,11 +115,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -86,13 +86,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -100,7 +100,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -108,7 +108,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -117,12 +117,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/STM32F401XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/STM32F401XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -2,7 +2,7 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
- RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64k - 0x194
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 64k - 0x198
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ ; Total: 101 vectors = 404 bytes (0x194) 8-byte aligned = 0x198 (0x194 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x18000-0x198) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/stm32f401xe.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/stm32f401xe.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x18000-0x194) { ; RW data
+ ; Total: 101 vectors = 404 bytes (0x194) 8-byte aligned = 0x198 (0x194 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x18000-0x198) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/STM32F401XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/STM32F401XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,9 @@
/* Linker script to configure memory regions. */
+/* 0x194 reserved for vectors 8-byte aligned = 0x198 (0x194 + 0x4) */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
- RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 96k - 0x194
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 96k - (0x194+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -116,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -54,6 +54,10 @@
__IO uint32_t *reg_out;
};
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/STM32F410xB.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/STM32F410xB.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -114,7 +114,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -123,12 +123,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/stm32f411xe.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/stm32f411xe.icf Thu Nov 08 11:46:34 2018 +0000
@@ -18,9 +18,9 @@
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x4000;
-define symbol __size_heap__ = 0x8000;
+/*Heap 84kB and stack 1kB */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0x15000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -68,6 +68,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -347,3 +347,48 @@
{PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
+ {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
+ {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -307,6 +307,14 @@
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PD_11,
+ QSPI1_IO1 = PD_12,
+ QSPI1_IO2 = PE_2,
+ QSPI1_IO3 = PD_13,
+ QSPI1_SCK = PB_2,
+ QSPI1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data
+ ; Total: 113 vectors = 452 bytes (0x1C4) 8-byte aligned = 0x1C8 (0x1C4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x40000-0x1C8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1C4) (0x40000-0x1C4) { ; RW data
+ ; Total: 113 vectors = 452 bytes (0x1C4) 8-byte aligned = 0x1C8 (0x1C4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x40000-0x1C8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld Thu Nov 08 11:46:34 2018 +0000
@@ -6,10 +6,11 @@
#define MBED_APP_SIZE 1024K
#endif
/* Linker script to configure memory regions. */
+/* 0x1C4 reserved for vectors; 8-byte aligned = 0x1C8 (0x1C4 + 0x4) */
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 256K - 0x1C4
+ RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 256K - (0x1C4+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -91,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -105,7 +106,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -113,7 +114,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -122,12 +123,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -18,8 +18,9 @@
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
-define symbol __size_cstack__ = 0x8000;
-define symbol __size_heap__ = 0x10000;
+/*Heap 84kB and stack 1kB */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0x15000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -79,6 +79,10 @@
CAN_3 = (int)CAN3_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -359,8 +359,8 @@
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D8
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D8
{PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_OTG_FS_DM
- {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D10
- {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D10
+ {PA_15_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ARD_D10
+ {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to ARD_D10
{PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, // Connected to ARD_A4
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CODEC_WS [WM8994ECS_LRCLK1]
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ARD_D13 // Connected to WIFI module // Connected to LD5
@@ -399,3 +399,48 @@
{PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to WIFI_DRDY
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_A1
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to SD_CMD
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to DFSDM2_DATIN1
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4
+ {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to ARD_A5
+ {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LED2_GREEN
+ {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to SD_D0
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to SD_D1
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to SD_D2
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to PSRAM_A16 [IS66WV51216EBLL_A16]
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to PSRAM_A17 [IS66WV51216EBLL_A17]
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to LCD_PSRAM_D4
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to LCD_PSRAM_D5
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to LCD_PSRAM_D6
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LCD_PSRAM_D7
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D0
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D1
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+// {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 // Connected to STDIO_UART_RX
+// {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 // Connected to STDIO_UART_TX
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK // Connected to ARD_A4
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK [N25Q128A13EF840F_C]
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK // Connected to CODEC_CK [WM8994ECS_BCLK1]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -303,6 +303,23 @@
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PF_8,
+ QSPI_FLASH1_IO1 = PF_9,
+ QSPI_FLASH1_IO2 = PE_2,
+ QSPI_FLASH1_IO3 = PD_13,
+ QSPI_FLASH1_SCK = PB_2,
+ QSPI_FLASH1_CSN = PG_6,
+
+ /**** WIFI ISM43362 pins ****/
+ ISM43362_WIFI_MISO = PB_4,
+ ISM43362_WIFI_MOSI = PB_5,
+ ISM43362_WIFI_SCLK = PB_12,
+ ISM43362_WIFI_NSS = PG_11,
+ ISM43362_WIFI_RESET = PH_1,
+ ISM43362_WIFI_DATAREADY = PG_12,
+ ISM43362_WIFI_WAKEUP = PB_15,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -31,7 +31,7 @@
#include "stm32f4xx.h"
#include "mbed_error.h"
-
+#include "nvic_addr.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -94,9 +94,20 @@
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
#endif
+ /* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */
+ /* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */
+ /* See board User Manual: WIFI_SPI_CS = PG_11*/
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+ GPIO_InitStruct.Pin = GPIO_PIN_11;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+ HAL_GPIO_WritePin(GPIOG, GPIO_PIN_11, GPIO_PIN_SET);
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -79,6 +79,10 @@
CAN_3 = (int)CAN3_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -399,3 +399,48 @@
{PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
+ {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
+ {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -306,6 +306,14 @@
SYS_WKUP2 = PC_0,
SYS_WKUP3 = PC_1,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PD_11,
+ QSPI1_IO1 = PD_12,
+ QSPI1_IO2 = PE_2,
+ QSPI1_IO3 = PD_13,
+ QSPI1_SCK = PB_2,
+ QSPI1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/stm32f413xh.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2017, STMicroelectronics
@@ -27,15 +28,24 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; STM32F413ZH: 1536 KB FLASH (0x150000) + 320 KB SRAM (0x50000)
-LR_IROM1 0x08000000 0x150000 { ; load region size_region
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
- ER_IROM1 0x08000000 0x150000 { ; load address = execution address
+; 1536KB FLASH (0x180000)
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x180000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
+ ; 320KB SRAM (0x50000)
; Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM
RW_IRAM1 (0x20000000+0x1D8) (0x50000-0x1D8) { ; RW data
.ANY (+RW +ZI)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/stm32f413xh.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/stm32f413xh.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2017, STMicroelectronics
@@ -27,15 +28,24 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; STM32F413ZH: 1536 KB FLASH (0x150000) + 320 KB SRAM (0x50000)
-LR_IROM1 0x08000000 0x150000 { ; load region size_region
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
- ER_IROM1 0x08000000 0x150000 { ; load address = execution address
+; 1536KB FLASH (0x180000)
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x180000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
+ ; 320KB SRAM (0x50000)
; Total: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM
RW_IRAM1 (0x20000000+0x1D8) (0x50000-0x1D8) { ; RW data
.ANY (+RW +ZI)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/STM32F413xH.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,7 +1,15 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1536K
+#endif
+
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1D8
}
@@ -84,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +106,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +114,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +123,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/stm32f413xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -1,7 +1,10 @@
/* [ROM = 1536kb = 0x180000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0817FFFF;
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x180000; }
+
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 320kb = 0x50000] Vector table dynamic copy: 118 vectors = 472 bytes (0x1D8) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -44,6 +44,16 @@
RNG_HandleTypeDef handle;
};
+struct qspi_s {
+ QSPI_HandleTypeDef handle;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x20000-0x1AC) { ; RW data
+ ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x20000-0x1B0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x30000-0x1B0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld Thu Nov 08 11:46:34 2018 +0000
@@ -4,10 +4,6 @@
* the stack where main runs is determined via the RTOS. */
STACK_SIZE = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
HEAP_SIZE = 0x6000;
#if !defined(MBED_APP_START)
@@ -62,21 +58,11 @@
{
__vector_table = .;
KEEP(*(.isr_vector))
- . = ALIGN(4);
+ . = ALIGN(8);
} > VECTORS
- /* Note: The uVisor expects this section at a fixed location, as specified
- * by the porting process configuration parameter:
- * FLASH_OFFSET. */
- __UVISOR_FLASH_OFFSET = 0x400;
- __UVISOR_FLASH_START = ORIGIN(VECTORS) + __UVISOR_FLASH_OFFSET;
- .text __UVISOR_FLASH_START :
+ .text :
{
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -120,55 +106,15 @@
.interrupts_ram :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
+ . = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
- /* uVisor own memory and private box memories
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x0;
- __UVISOR_SRAM_START = ORIGIN(CCM) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* Protected uVisor own BSS section */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* Protected uVisor boxes' static memories */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > CCM
-
- /* Heap space for the page allocator
- /* If uVisor shares the SRAM with the OS/app, ensure that this section is
- * the first one after the uVisor BSS section. Otherwise, ensure it is the
- * first one after the VTOR relocation section. */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN((1 << LOG2CEIL(LENGTH(RAM))) / 8);
- __uvisor_page_end = .;
- } > RAM
.data :
{
@@ -179,13 +125,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -193,7 +139,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -201,44 +147,13 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM AT > FLASH
- /* uVisor configuration section
- * This section must be located after all other flash regions. */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uVisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* Pointers to the uVisor secure boxes configuration tables */
- /* Note: Do not add any further alignment here, as uVisor will need to
- * have access to the exact list of pointers. */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to
- allow discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > FLASH
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
@@ -255,24 +170,22 @@
.bss (NOLOAD):
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (NOLOAD):
{
- __uvisor_heap_start = .;
__end__ = .;
end = __end__;
. += HEAP_SIZE;
__HeapLimit = .;
- __uvisor_heap_end = .;
} > RAM
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
@@ -281,11 +194,4 @@
ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(CCM);
- __uvisor_sram_end = ORIGIN(CCM) + LENGTH(CCM);
- __uvisor_public_sram_start = ORIGIN(RAM);
- __uvisor_public_sram_end = ORIGIN(RAM) + LENGTH(RAM);
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -108,10 +108,6 @@ /* Call the clock system intitialization function.*/ bl SystemInitPre bl HAL_InitPre -#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) - ldr r0, =uvisor_init - blx r0 -#endif /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */ bl SystemInit /* Call static constructors */ //bl __libc_init_array
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_init_pre.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_init_pre.c Thu Nov 08 11:46:34 2018 +0000
@@ -19,14 +19,10 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
-/* note: if uVisor is present the definition must go in system_init_pre.c */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
-/* this function is needed to peform hardware initialization that must happen
- * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
- * put here as it depends on some APIs that need uVisor to be enabled */
void SystemInitPre(void)
{
/* FPU settings ------------------------------------------------------------*/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -43,6 +43,7 @@
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
{NC, NC, 0}
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -70,13 +70,8 @@
void onboard_modem_power_down()
{
-#if defined(TARGET_UBLOX_C030_R410M)
/* keep the power line low for 1.5 seconds */
press_power_button(1500000);
-#else
- /* keep the power line low for 1 seconds */
- press_power_button(1000000);
-#endif
}
#endif //MODEM_ON_BOARD
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -46,8 +46,8 @@
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x30000-0x1B0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld Thu Nov 08 11:46:34 2018 +0000
@@ -7,9 +7,10 @@
#endif
/* Linker script to configure memory regions. */
+/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/
MEMORY
{
-RAM (xrw) : ORIGIN = 0x200001AC, LENGTH = 192K - 0x1AC /* 0x1AC is to leave room for vectors */
+RAM (xrw) : ORIGIN = 0x200001B0, LENGTH = 192K - 0x1B0 /* 0x1AC+0x4 is to leave room for vectors */
CCM_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
BACKUP_SRAM (rw) : ORIGIN = 0x40024000, LENGTH = 4096
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
@@ -94,13 +95,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -108,7 +109,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -116,7 +117,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -125,12 +126,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -99,6 +99,7 @@
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_TX
{NC, NC, 0}
};
@@ -106,9 +107,20 @@
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
{PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_RX
{NC, NC, 0}
};
+const PinMap PinMap_UART_RTS[] = {
+ {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_USART6)}, // HCI UART_RTS
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLDOWN, GPIO_AF8_USART6)}, // HCI UART_CTS
+ {NC, NC, 0}
+};
+
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar has changed
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a has changed
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.cpp Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1852 @@
+/* ODIN-W2 implementation of WiFiInterface
+ * Copyright (c) 2016 u-blox Malmö AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "OdinWiFiInterface.h"
+#include "cb_main.h"
+#include "cb_wlan.h"
+#include "cb_wlan_types.h"
+
+#include "wifi_emac.h"
+#include "netsocket/WiFiAccessPoint.h"
+
+#define ODIN_WIFI_BSSID_CACHE (5)
+#define ODIN_WIFI_STA_DEFAULT_CONN_TMO (20000)
+
+#define ODIN_WIFI_AP_ALLOWED_RATE_MASK 0xfffffff
+#define ODIN_MAX_AP_STATIONS (10)
+
+#define APP_MASK_LOWESTBIT(BITMASK) ((BITMASK) & (-(BITMASK)))
+#define APP_MASK_SHIFTUP(MASK, SHIFTMASK) ((cbWLAN_RateMask)((SHIFTMASK != 0 ) ? (MASK * APP_MASK_LOWESTBIT(SHIFTMASK)) : MASK))
+
+enum user_msg_types_t {
+ // cbWLAN_StatusIndicationInfo use from 0 to ~10
+
+ cbWLAN_SCAN_INDICATION = 100,
+
+ ODIN_WIFI_MSG_USER_CONNECT,
+ ODIN_WIFI_MSG_USER_DISCONNECT,
+ ODIN_WIFI_MSG_USER_CONNECT_TIMEOUT,
+ ODIN_WIFI_MSG_USER_SCAN,
+ ODIN_WIFI_MSG_USER_SCAN_RSP,
+ ODIN_WIFI_MSG_USER_STOP,
+
+ ODIN_WIFI_MSG_USER_AP_START,
+ ODIN_WIFI_MSG_USER_AP_STOP
+};
+
+struct user_connect_s {
+ const char *ssid;
+ const char *passwd;
+ uint8_t channel;
+ nsapi_security_t security;
+ unsigned int timeout;
+};
+
+struct user_scan_s {
+ WiFiAccessPoint *ap_list;
+ nsapi_size_t ap_list_size;
+};
+
+struct user_scan_rsp_s {
+ WiFiAccessPoint *ap_list;
+ nsapi_size_or_error_t found_aps;
+};
+
+struct user_response_s {
+ nsapi_error_t error;
+};
+
+struct user_ap_start_s {
+ const char *ssid;
+ const char *passwd;
+ uint8_t channel;
+ nsapi_security_t security;
+ uint16_t beacon_interval;
+};
+
+struct wlan_status_started_s {
+ cbWLAN_StatusStartedInfo info;
+};
+
+struct wlan_status_connected_s {
+ cbWLAN_StatusConnectedInfo info;
+};
+
+struct wlan_status_connection_failure_s {
+ cbWLAN_StatusDisconnectedInfo info;
+};
+
+struct odin_wifi_msg_s {
+ unsigned int type;
+
+ union data_t {
+ struct user_connect_s user_connect;
+ struct user_response_s user_response;
+ struct user_scan_s user_scan;
+ struct user_scan_rsp_s user_scan_rsp;
+ struct user_ap_start_s user_ap_start;
+ struct wlan_status_started_s wlan_status_started;
+ struct wlan_status_connected_s wlan_status_connected;
+ struct wlan_status_connection_failure_s wlan_status_connection_failure;
+ } data;
+};
+
+static void generateWEPKeys(const char *passphrase, cbWLAN_WEPKey keys[4]);
+
+static void set_wpa_rsn_cipher(
+ nsapi_security_t security,
+ cbWLAN_CipherSuite &wpa_ciphers,
+ cbWLAN_CipherSuite &rsn_ciphers);
+
+static bool is_valid_AP_channel(cbWLAN_Channel channel);
+
+// Friend declared C-functions that calls corresponding wi-fi object member function
+struct wlan_callb_s {
+
+ static void scan_indication_callback(void *callb_context, cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result)
+ {
+ MBED_ASSERT(callb_context != NULL);
+
+ OdinWiFiInterface *wifi = (OdinWiFiInterface*)callb_context;
+
+ wifi->wlan_scan_indication(scan_info, is_last_result);
+ };
+
+ static void status_indication_callback(void *callb_context, cbWLAN_StatusIndicationInfo status, void *data)
+ {
+ MBED_ASSERT(callb_context != NULL);
+
+ OdinWiFiInterface *wifi = (OdinWiFiInterface*)callb_context;
+
+ wifi->wlan_status_indication(status, data);
+ };
+
+ static void odin_thread_fcn(OdinWiFiInterface *wifi)
+ {
+ wifi->handle_in_msg();
+ };
+};
+
+// Static declared class variables
+bool OdinWiFiInterface::_wlan_initialized = false;
+int32_t OdinWiFiInterface::_target_id = cbMAIN_TARGET_INVALID_ID;
+
+OdinWiFiInterface::OdinWiFiInterface(OdinWiFiEMAC &emac , OnboardNetworkStack &stack) :
+ EMACInterface(emac, stack),
+ _thread(osPriorityNormal, 4096)
+{
+ init(false);
+}
+
+OdinWiFiInterface::OdinWiFiInterface(bool debug, OdinWiFiEMAC &emac, OnboardNetworkStack &stack) :
+ EMACInterface(emac, stack),
+ _thread(osPriorityNormal, 4096)
+{
+ init(debug);
+}
+
+OdinWiFiInterface::~OdinWiFiInterface()
+{
+ osStatus ok;
+
+ // Allocate and initialize user_connect message
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_STOP;
+
+ // Put user_connect message in input queue or cache queue
+ switch(_state) {
+ case S_STARTED:
+ ok = _in_queue.put(msg, 0);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ case S_WAIT_START:
+ ok = _cache_queue.put(msg, 0);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_STOP);
+
+ //Final cleanup
+ _thread.terminate();
+ delete _msg_pool;
+}
+
+nsapi_error_t OdinWiFiInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
+{
+ int len;
+
+ if(ssid == NULL || *ssid == '\0' ) {
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ if ((pass == NULL || *pass == '\0') && (security == NSAPI_SECURITY_WEP || security == NSAPI_SECURITY_WPA
+ || security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA_WPA2)){
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ len = strlen(pass);
+
+ if (len > cbWLAN_MAX_PASSPHRASE_LENGTH -1){
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ strncpy(_sta.ssid, ssid, cbWLAN_SSID_MAX_LENGTH);
+ strncpy(_sta.passwd, pass, cbWLAN_MAX_PASSPHRASE_LENGTH);
+ _sta.security = security;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t OdinWiFiInterface::set_channel(uint8_t channel)
+{
+ if (channel > 165 || (channel > 11 && channel < 36)){
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _sta.channel = channel;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t OdinWiFiInterface::set_timeout(int ms)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _sta.timeout_ms = ms;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t OdinWiFiInterface::connect()
+{
+ return connect(_sta.ssid, _sta.passwd, _sta.security, _sta.channel);
+}
+
+nsapi_error_t OdinWiFiInterface::connect(
+ const char *ssid,
+ const char *pass,
+ nsapi_security_t security,
+ uint8_t channel)
+{
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+ osStatus ok;
+
+ if (ssid == NULL || *ssid == NULL) {
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ if ((pass == NULL || *pass == NULL) && (security == NSAPI_SECURITY_WEP || security == NSAPI_SECURITY_WPA
+ || security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA_WPA2)){
+ return NSAPI_ERROR_PARAMETER;
+ }
+
+ // Allocate and initialize user_connect message
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_CONNECT;
+ msg->data.user_connect.ssid = ssid; // Must be valid until task is completed
+ msg->data.user_connect.passwd = pass; // Must be valid until task is completed
+ msg->data.user_connect.security = security;
+ msg->data.user_connect.channel = channel;
+
+ // Put user_connect message in input queue or cache queue
+ switch(_state) {
+ case S_STARTED:
+ ok = _in_queue.put(msg, 0);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ case S_WAIT_START:
+ ok = _cache_queue.put(msg, 0); // handle once we are started
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_CONNECT);
+
+ // Return the result of the connect call
+ error_code = msg->data.user_response.error;
+
+ ok = _msg_pool->free(msg);
+ MBED_ASSERT(ok == osOK);
+
+ return error_code;
+}
+
+nsapi_error_t OdinWiFiInterface::disconnect()
+{
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+
+ // Allocate and init the user disconnect message
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_DISCONNECT;
+
+ // Put the user disconnect message in the input queue
+ osStatus ok = _in_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_DISCONNECT);
+
+ // Return the result of the disconnect call
+ error_code = msg->data.user_response.error;
+
+ _msg_pool->free(msg);
+
+ return error_code;
+}
+
+int8_t OdinWiFiInterface::get_rssi()
+{
+ cbMAIN_driverLock();
+ int8_t rssi = cbWLAN_STA_getRSSI();
+ cbMAIN_driverUnlock();
+
+ return rssi;
+}
+
+int OdinWiFiInterface::scan(WiFiAccessPoint *res_list, unsigned count)
+{
+ osStatus ok;
+ nsapi_size_or_error_t found_aps = NSAPI_ERROR_DEVICE_ERROR;
+
+ // Allocate and initialize user_connect message
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_SCAN;
+ msg->data.user_scan.ap_list = res_list; // Must be valid during execution
+ msg->data.user_scan.ap_list_size = count;
+
+ // Put user_connect message in input queue or cache queue
+ switch(_state) {
+ case S_STARTED:
+ ok = _in_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ case S_WAIT_START:
+ ok = _cache_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_SCAN_RSP);
+
+ found_aps = msg->data.user_scan_rsp.found_aps;
+
+ _msg_pool->free(msg);
+
+ return found_aps;
+}
+
+#ifdef DEVICE_WIFI_AP
+
+nsapi_error_t OdinWiFiInterface::set_ap_network(const char *ip_address, const char *netmask, const char *gateway)
+{
+ nsapi_error_t result = NSAPI_ERROR_PARAMETER;
+
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ if ((ip_address != NULL) && (netmask != NULL) && (gateway != NULL))
+ {
+ strncpy(_ap.ip_address, ip_address, sizeof(_ap.ip_address));
+ strncpy(_ap.netmask, netmask, sizeof(_ap.netmask));
+ strncpy(_ap.gateway, gateway, sizeof(_ap.gateway));
+
+ _ap.use_dhcp = false;
+
+ result = NSAPI_ERROR_OK;
+ }
+ else {
+ memset(_ap.ip_address, 0, sizeof(_ap.ip_address));
+ memset(_ap.netmask, 0, sizeof(_ap.netmask));
+ memset(_ap.gateway, 0, sizeof(_ap.gateway));
+
+ _ap.use_dhcp = true;
+
+ result = NSAPI_ERROR_OK;
+ }
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return result;
+}
+
+
+nsapi_error_t OdinWiFiInterface::set_ap_credentials(const char *ssid, const char *pass,
+ nsapi_security_t security)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _ap.ssid = ssid;
+ _ap.passwd = pass;
+ _ap.security = security;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t OdinWiFiInterface::set_ap_channel(uint8_t channel)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _ap.channel = channel;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+int OdinWiFiInterface::get_ap_connection_count()
+{
+ int cnt;
+
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ cnt = _ap.cnt_connected;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return cnt;
+}
+
+int OdinWiFiInterface::get_ap_max_connection_count()
+{
+ return ODIN_MAX_AP_STATIONS;
+}
+
+nsapi_error_t OdinWiFiInterface::set_ap_dhcp(bool dhcp)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _ap.use_dhcp = dhcp;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t OdinWiFiInterface::ap_start(const char *ssid, const char *pass,
+ nsapi_security_t security, uint8_t channel)
+{
+ int error_code = NSAPI_ERROR_OK;
+ osStatus ok;
+
+ // Allocate and initialize message
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_AP_START;
+ msg->data.user_ap_start.ssid = ssid; // Must be valid until task is completed
+ msg->data.user_ap_start.passwd = pass; // Must be valid until task is completed
+ msg->data.user_ap_start.security = security;
+ msg->data.user_ap_start.channel = channel; // Must be valid until task is completed
+ msg->data.user_ap_start.beacon_interval = _ap.beacon_interval;
+
+ // Put message in input queue or cache queue
+ switch(_state) {
+ case S_STARTED:
+ ok = _in_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ case S_WAIT_START:
+ ok = _cache_queue.put(msg); // handle once we are started
+ MBED_ASSERT(ok == osOK);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_AP_START);
+
+ // Return the result of the call
+ error_code = msg->data.user_response.error;
+
+ ok = _msg_pool->free(msg);
+ MBED_ASSERT(ok == osOK);
+
+ return error_code;
+}
+
+nsapi_error_t OdinWiFiInterface::ap_start()
+{
+ return ap_start(_ap.ssid, _ap.passwd, _ap.security, _ap.channel);
+}
+
+nsapi_error_t OdinWiFiInterface::ap_stop()
+{
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_AP_STOP;
+
+ // Put the user message in the input queue
+ osStatus ok = _in_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+
+ // To synchronize, wait until response message is available
+ osEvent evt = _out_queue.get();
+ MBED_ASSERT(evt.status == osEventMessage);
+
+ msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+ MBED_ASSERT(msg->type == ODIN_WIFI_MSG_USER_AP_STOP);
+
+ // Return the result of the disconnect call
+ error_code = msg->data.user_response.error;
+
+ _msg_pool->free(msg);
+
+ return error_code;
+}
+
+nsapi_error_t OdinWiFiInterface::set_ap_beacon_interval(uint16_t interval)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ _ap.beacon_interval = interval;
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ return NSAPI_ERROR_OK;
+}
+
+#endif
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_connect_fail_wait_disconnect(void)
+{
+ cbRTSL_Status error_code;
+
+ cbMAIN_driverLock();
+ error_code = cbWLAN_disconnect();
+ cbMAIN_driverUnlock();
+
+ MBED_ASSERT(error_code == cbSTATUS_OK);
+
+ return S_STA_CONNECTION_FAIL_WAIT_DISCONNECT;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_wait_connect()
+{
+ _timer.reset();
+ _timer.start();
+
+ return S_STA_WAIT_CONNECT;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_wait_disconnect()
+{
+ cbRTSL_Status error_code;
+
+ cbMAIN_driverLock();
+ error_code = cbWLAN_disconnect();
+ cbMAIN_driverUnlock();
+
+ MBED_ASSERT(error_code == cbSTATUS_OK);
+
+ return S_STA_WAIT_DISCONNECT;
+}
+
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_start()
+{
+ return S_AP_WAIT_START;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_started()
+{
+ _ap.cnt_connected = 0;
+
+ return S_AP_STARTED;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_stop()
+{
+ cbMAIN_driverLock();
+ cbRTSL_Status status = cbWLAN_apStop();
+ cbMAIN_driverUnlock();
+
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ return S_AP_WAIT_STOP;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_fail_wait_stop()
+{
+ cbMAIN_driverLock();
+ cbRTSL_Status status = cbWLAN_apStop();
+ cbMAIN_driverUnlock();
+
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ return S_AP_FAIL_WAIT_STOP;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_drv_stop()
+{
+ cbMAIN_driverLock();
+ cbRTSL_Status status = cbWLAN_stop();
+ cbMAIN_driverUnlock();
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ return S_AP_WAIT_DRV_STOP;
+}
+
+OdinWiFiInterface::OdinWifiState OdinWiFiInterface::entry_ap_wait_drv_start()
+{
+ cbMAIN_WlanStartParams startParams;
+
+ memset(&startParams, 0, sizeof(startParams));
+
+ startParams.txPowerSettings.lowTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+ startParams.txPowerSettings.medTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+ startParams.txPowerSettings.maxTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+
+ cbMAIN_driverLock();
+ cb_int32 status = cbMAIN_startWlan(_target_id, &startParams);
+ cbMAIN_driverUnlock();
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ return S_AP_WAIT_DRV_START;
+}
+
+void OdinWiFiInterface::handle_in_msg(void)
+{
+ while(true) {
+
+ osEvent evt = _in_queue.get(1000);
+
+ if(evt.status == osEventMessage) {
+
+ struct odin_wifi_msg_s *msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ switch(msg->type) {
+ case ODIN_WIFI_MSG_USER_CONNECT:
+ handle_user_connect(&(msg->data.user_connect));
+ break;
+
+ case ODIN_WIFI_MSG_USER_DISCONNECT:
+ handle_user_disconnect();
+ break;
+
+ case ODIN_WIFI_MSG_USER_CONNECT_TIMEOUT:
+ handle_user_connect_timeout();
+ break;
+
+ case ODIN_WIFI_MSG_USER_STOP:
+ handle_user_stop();
+ break;
+
+ case ODIN_WIFI_MSG_USER_SCAN:
+ handle_user_scan(&(msg->data.user_scan));
+ break;
+
+ case ODIN_WIFI_MSG_USER_AP_START:
+ handle_user_ap_start(&(msg->data.user_ap_start));
+ break;
+
+ case ODIN_WIFI_MSG_USER_AP_STOP:
+ handle_user_ap_stop();
+ break;
+
+ case cbWLAN_STATUS_STOPPED:
+ handle_wlan_status_stopped();
+ break;
+
+ case cbWLAN_STATUS_STARTED:
+ handle_wlan_status_started(&(msg->data.wlan_status_started));
+ break;
+
+ case cbWLAN_STATUS_ERROR:
+ handle_wlan_status_error();
+ break;
+
+ case cbWLAN_STATUS_DISCONNECTED:
+ handle_wlan_status_disconnected();
+ break;
+
+ case cbWLAN_STATUS_CONNECTION_FAILURE:
+ handle_wlan_status_connection_failure(&(msg->data.wlan_status_connection_failure));
+ break;
+
+ case cbWLAN_STATUS_CONNECTING:
+ handle_wlan_status_connecting();
+ break;
+
+ case cbWLAN_STATUS_CONNECTED:
+ handle_wlan_status_connected(&(msg->data.wlan_status_connected));
+ break;
+
+ case cbWLAN_SCAN_INDICATION:
+ handle_wlan_scan_indication();
+ break;
+
+ case cbWLAN_STATUS_AP_UP:
+ handle_wlan_status_ap_up();
+ break;
+
+ case cbWLAN_STATUS_AP_DOWN:
+ handle_wlan_status_ap_down();
+ break;
+
+ case cbWLAN_STATUS_AP_STA_ADDED:
+ _ap.cnt_connected++;
+ if(_debug) {printf("cbWLAN_STATUS_AP_STA_ADDED: %d\r\n", _ap.cnt_connected);}
+ break;
+
+ case cbWLAN_STATUS_AP_STA_REMOVED:
+ _ap.cnt_connected--;
+ if(_debug) {printf("cbWLAN_STATUS_AP_STA_REMOVED: %d\r\n", _ap.cnt_connected);}
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+
+ if(msg != 0) {
+ _msg_pool->free(msg);
+ }
+ }
+ else if(evt.status == osEventTimeout) {
+ //Make sure the connect timeout is checked
+ handle_user_connect_timeout();
+ }
+ else {
+ MBED_ASSERT(false);
+ }
+ }
+}
+
+void OdinWiFiInterface::handle_cached_msg(void)
+{
+ osEvent evt = _cache_queue.get(0);
+ if(evt.status == osEventMessage) {
+
+ struct odin_wifi_msg_s *msg = (odin_wifi_msg_s*)evt.value.p;
+ MBED_ASSERT(msg != 0);
+
+ switch(msg->type) {
+ case ODIN_WIFI_MSG_USER_CONNECT:
+ handle_user_connect(&(msg->data.user_connect));
+ break;
+
+ case ODIN_WIFI_MSG_USER_SCAN:
+ handle_user_scan(&(msg->data.user_scan));
+ break;
+
+ case ODIN_WIFI_MSG_USER_STOP:
+ handle_user_stop();
+ break;
+
+ case ODIN_WIFI_MSG_USER_AP_START:
+ handle_user_ap_start(&(msg->data.user_ap_start));
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+ if(msg != 0) {
+ _msg_pool->free(msg);
+ }
+ }
+}
+
+void OdinWiFiInterface::handle_user_connect(user_connect_s *user_connect)
+{
+ MBED_ASSERT(user_connect != 0);
+
+ nsapi_error_t error_code = NSAPI_ERROR_DEVICE_ERROR;
+
+ if((_state_sta == S_STA_IDLE) && (_state_ap == S_AP_IDLE)) {
+ // No STA or AP activity in progress
+
+ error_code = wlan_set_channel(user_connect->channel);
+
+ if (error_code == NSAPI_ERROR_OK) {
+ error_code = wlan_connect(user_connect->ssid, user_connect->passwd, user_connect->security);
+ }
+ }
+ else {
+ // Parallel STA or AP activity is not supported
+ error_code = NSAPI_ERROR_UNSUPPORTED;
+ }
+
+ if(error_code == NSAPI_ERROR_OK) {
+ memset(&_wlan_status_connected_info, 0, sizeof(cbWLAN_StatusConnectedInfo));
+ memcpy(&_wlan_status_disconnected_info, 0, sizeof(cbWLAN_StatusDisconnectedInfo));
+
+ _state_sta = entry_wait_connect();
+ }
+ else
+ {
+ // Remain in S_STA_IDLE
+ // Release user connect call
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, error_code);
+ }
+}
+
+void OdinWiFiInterface::handle_user_disconnect(void)
+{
+ switch(_state_sta) {
+ case S_STA_CONNECTED:
+ case S_STA_DISCONNECTED_WAIT_CONNECT:
+ _state_sta = entry_wait_disconnect();
+ break;
+
+ default:
+ send_user_response_msg(ODIN_WIFI_MSG_USER_DISCONNECT, NSAPI_ERROR_NO_CONNECTION);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_user_stop()
+{
+ MBED_ASSERT(_state == S_STARTED);
+ MBED_ASSERT(_state_sta == S_STA_IDLE);
+ MBED_ASSERT(_state_ap == S_AP_IDLE);
+
+ _interface->bringdown();
+
+ cbMAIN_driverLock();
+ cbRTSL_Status status = cbWLAN_stop();
+ cbMAIN_driverUnlock();
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ _state = S_WAIT_STOP;
+ _state_sta = S_INVALID;
+ _state_ap = S_INVALID;
+}
+
+void OdinWiFiInterface::handle_user_scan(user_scan_s *user_scan)
+{
+ MBED_ASSERT(_state == S_STARTED);
+ MBED_ASSERT(user_scan != 0);
+
+ cbWLAN_ScanParameters params;
+ params.ssid.ssidLength = 0; //Broadcast scan
+ params.channel = cbWLAN_CHANNEL_ALL;
+ memset(&_scan_cache, 0, sizeof(scan_cache_s));
+
+ cbRTSL_Status status = cbSTATUS_ERROR;
+ for(int i = 0; (i < 10) && (status != cbSTATUS_OK); i++) {
+ if(i > 0) {
+ wait_ms(500);
+ }
+
+ cbMAIN_driverLock();
+ status = cbWLAN_scan(¶ms, wlan_callb_s::scan_indication_callback, this);
+ if(status == cbSTATUS_OK) {
+ _scan_active = true;
+ _scan_list = user_scan->ap_list;
+ _scan_list_size = user_scan->ap_list_size;
+ _scan_list_cnt = 0;
+ }
+ cbMAIN_driverUnlock();
+ }
+
+ if(status != cbSTATUS_OK) {
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_SCAN_RSP;
+ msg->data.user_scan_rsp.ap_list = 0;
+ msg->data.user_scan_rsp.found_aps = NSAPI_ERROR_DEVICE_ERROR;
+
+ osStatus ok = _out_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+ }
+}
+
+void OdinWiFiInterface::handle_user_connect_timeout()
+{
+ if((_state_sta == S_STA_WAIT_CONNECT) && (_sta.timeout_ms > 0)) {
+ int elapsed_time = _timer.read_ms();
+
+ if(elapsed_time > _sta.timeout_ms) {
+ if(_debug) {
+ printf("TIMEOUT: %d ms, ACTUAL %d ms\n\r", _sta.timeout_ms, elapsed_time);
+ }
+ _timer.stop();
+
+ _state_sta = entry_connect_fail_wait_disconnect();
+ }
+ }
+}
+
+void OdinWiFiInterface::handle_user_ap_start(user_ap_start_s *user_ap_start)
+{
+ MBED_ASSERT(user_ap_start != 0);
+
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+
+ bool channel_ok = is_valid_AP_channel(user_ap_start->channel);
+
+ if((_state_sta == S_STA_IDLE) && (_state_ap == S_AP_IDLE) && channel_ok) {
+ // No STA or AP activity in progress
+
+ error_code = wlan_ap_start(
+ user_ap_start->ssid,
+ user_ap_start->passwd,
+ user_ap_start->security,
+ user_ap_start->channel,
+ user_ap_start->beacon_interval);
+ }
+ else {
+ // Parallel STA or AP activity is not supported
+ error_code = NSAPI_ERROR_UNSUPPORTED;
+ }
+
+ if(error_code == NSAPI_ERROR_OK) {
+ _state_ap = entry_ap_wait_start();
+ }
+ else
+ {
+ send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, error_code);
+ }
+}
+
+void OdinWiFiInterface::handle_user_ap_stop()
+{
+ switch(_state_ap) {
+ case S_AP_STARTED:
+ _state_ap = entry_ap_wait_stop();
+ break;
+
+ default:
+ send_user_response_msg(ODIN_WIFI_MSG_USER_AP_STOP, NSAPI_ERROR_DEVICE_ERROR);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_started(wlan_status_started_s *start)
+{
+ if (_debug) {
+ printf("cbWLAN_STATUS_STARTED\n\r");
+ }
+
+ MBED_ASSERT(start != 0);
+
+ switch(_state) {
+ case S_WAIT_START:
+ sprintf(_mac_addr_str,
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ start->info.macAddress[0],
+ start->info.macAddress[1],
+ start->info.macAddress[2],
+ start->info.macAddress[3],
+ start->info.macAddress[4],
+ start->info.macAddress[5]);
+
+ if(!_wlan_initialized) {
+ //Initialize network stack interface without activating it
+ }
+
+ if (!_interface) {
+ nsapi_error_t error_code = _stack.add_ethernet_interface(_emac, true, &_interface);
+ if (error_code != NSAPI_ERROR_OK) {
+ _interface = NULL;
+ }
+ else {
+ _interface->attach(_connection_status_cb);
+ }
+ }
+
+
+ #ifdef DEVICE_WIFI_AP
+ if(!_wlan_initialized) {
+ _wlan_initialized = true;
+ }
+ #else
+ if (!_wlan_initialized) {
+ _wlan_initialized = true;
+ }
+ #endif
+
+ // The OdinWifiInterface object is now fully initialized
+ _state = S_STARTED;
+ _state_sta = S_STA_IDLE;
+ _state_ap = S_AP_IDLE;
+
+ handle_cached_msg();
+ break;
+
+ case S_STARTED:
+ switch(_state_ap) {
+ case S_AP_WAIT_DRV_START:
+ _state_ap = S_AP_IDLE;
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_AP_STOP, NSAPI_ERROR_OK);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+
+}
+
+void OdinWiFiInterface::handle_wlan_status_stopped()
+{
+ if (_debug) {
+ printf("cbWLAN_STATUS_STOPPED\n\r");
+ }
+
+ cbRTSL_Status status;
+
+ switch(_state) {
+ case S_WAIT_START:
+ // Ignore
+ break;
+
+ case S_WAIT_STOP:
+ _state = S_INVALID;
+
+ cbMAIN_driverLock();
+ status = cbWLAN_deregisterStatusCallback(wlan_callb_s::status_indication_callback, this);
+ cbMAIN_driverUnlock();
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_STOP, NSAPI_ERROR_OK);
+ break;
+
+ case S_STARTED:
+ switch(_state_ap) {
+ case S_AP_WAIT_DRV_STOP:
+ _state_ap = entry_ap_wait_drv_start();
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+ break;
+
+ default:
+ MBED_ASSERT(FALSE);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_error()
+{
+ if (_debug) {
+ printf("cbWLAN_STATUS_ERROR\n\r");
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_connecting()
+{
+ if (_debug) {
+ printf("cbWLAN_STATUS_CONNECTING\n\r");
+ }
+
+ handle_user_connect_timeout();
+}
+
+void OdinWiFiInterface::handle_wlan_status_connected(wlan_status_connected_s *wlan_connect)
+{
+ nsapi_error_t error_code;
+
+ MBED_ASSERT(wlan_connect != 0);
+
+ switch(_state_sta) {
+ case S_STA_WAIT_CONNECT:
+ _timer.stop();
+
+ if(_debug) {
+ printf("MBED_IPSTACK_ \r\n");
+ }
+
+ error_code = _interface->bringup(_dhcp,
+ _ip_address[0] ? _ip_address : 0,
+ _netmask[0] ? _netmask : 0,
+ _gateway[0] ? _gateway : 0,
+ DEFAULT_STACK);
+
+
+ if (error_code == NSAPI_ERROR_OK || error_code == NSAPI_ERROR_IS_CONNECTED) {
+ memcpy(&_wlan_status_connected_info, &(wlan_connect->info), sizeof(cbWLAN_StatusConnectedInfo));
+ _state_sta = S_STA_CONNECTED;
+ send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, NSAPI_ERROR_OK);
+ }
+ else {
+ _state_sta = entry_connect_fail_wait_disconnect();
+ }
+ break;
+
+ case S_STA_DISCONNECTED_WAIT_CONNECT:
+ _state_sta = S_STA_CONNECTED;
+ break;
+
+ case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT:
+ case S_STA_WAIT_DISCONNECT:
+ //Ignore
+ break;
+
+ default:
+ MBED_ASSERT(FALSE);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_connection_failure(wlan_status_connection_failure_s *connect_failure)
+{
+ MBED_ASSERT(connect_failure != 0);
+
+ if(_debug) {
+ printf("WLAN STATUS CONNECTION FAILURE\r\n");
+ }
+
+ memcpy(&_wlan_status_disconnected_info, &(connect_failure->info), sizeof(cbWLAN_StatusDisconnectedInfo));
+
+ switch(_state_sta) {
+ case S_STA_WAIT_CONNECT:
+ //Ignore - wait until timeout or connection success
+ handle_user_connect_timeout();
+ break;
+
+ case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT:
+ //Ignore
+ break;
+
+ case S_STA_CONNECTED:
+ _state_sta = S_STA_DISCONNECTED_WAIT_CONNECT;
+ break;
+
+ case S_STA_DISCONNECTED_WAIT_CONNECT:
+ //Ignore
+ break;
+
+ case S_STA_WAIT_DISCONNECT:
+ //Ignore
+ break;
+
+ default:
+ if(_debug) printf("ASSERT: S %d\r\n", _state_sta);
+ MBED_ASSERT(FALSE);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_disconnected(void)
+{
+ nsapi_error_t error_code;
+
+ if(_debug) {
+ printf("WLAN STATUS DISCONNECTED\r\n");
+ }
+
+ switch(_state_sta) {
+ case S_STA_WAIT_CONNECT:
+ handle_user_connect_timeout();
+ break;
+
+ case S_STA_CONNECTED:
+ _state_sta = S_STA_DISCONNECTED_WAIT_CONNECT;
+ break;
+
+ case S_STA_DISCONNECTED_WAIT_CONNECT:
+ //Ignore
+ break;
+
+ case S_STA_CONNECTION_FAIL_WAIT_DISCONNECT:
+ _state_sta = S_STA_IDLE;
+
+ switch(_wlan_status_disconnected_info) {
+ case cbWLAN_STATUS_DISCONNECTED_NO_BSSID_FOUND:
+ error_code = NSAPI_ERROR_NO_SSID;
+ break;
+
+ case cbWLAN_STATUS_DISCONNECTED_AUTH_TIMEOUT:
+ case cbWLAN_STATUS_DISCONNECTED_MIC_FAILURE:
+ error_code = NSAPI_ERROR_AUTH_FAILURE;
+ break;
+ case cbWLAN_STATUS_DISCONNECTED_UNKNOWN:
+ error_code = NSAPI_ERROR_NO_CONNECTION;
+ break;
+ default:
+ error_code = NSAPI_ERROR_DEVICE_ERROR;
+ break;
+ }
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_CONNECT, error_code);
+ break;
+
+ case S_STA_WAIT_DISCONNECT:
+ if(_debug) {
+ printf("MBED_IPSTACK_BRINGDOWN\r\n");
+ }
+ _interface->bringdown();
+
+ _state_sta = S_STA_IDLE;
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_DISCONNECT, NSAPI_ERROR_OK);
+ break;
+
+ default:
+ MBED_ASSERT(FALSE);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_scan_indication()
+{
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = ODIN_WIFI_MSG_USER_SCAN_RSP;
+ msg->data.user_scan_rsp.ap_list = _scan_list;
+ msg->data.user_scan_rsp.found_aps = _scan_list_cnt;
+
+ _scan_active = false;
+ _scan_list = 0;
+ _scan_list_size = 0;
+ _scan_list_cnt = 0;
+ memset(&_scan_cache, 0, sizeof(scan_cache_s));
+
+ if(_debug) printf("SCAN END\r\n");
+
+ osStatus ok = _out_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+}
+
+void OdinWiFiInterface::handle_wlan_status_ap_up()
+{
+ nsapi_error_t error_code;
+
+ if (_debug) {
+ printf("cbWLAN_STATUS_AP_UP\n\r");
+ }
+
+ switch(_state_ap) {
+ case S_AP_WAIT_START:
+
+ if(_debug) {
+ printf("MBED_IPSTACK_BRINGUP\r\n");
+ }
+
+ error_code = _interface->bringup(_ap.use_dhcp,
+ _ap.ip_address[0] ? _ap.ip_address : 0,
+ _ap.netmask[0] ? _ap.netmask : 0,
+ _ap.gateway[0] ? _ap.gateway : 0,
+ DEFAULT_STACK);
+
+ if(error_code == NSAPI_ERROR_OK) {
+ _state_ap = S_AP_STARTED;
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, NSAPI_ERROR_OK);
+ }
+ else {
+ _ap.error_code = error_code;
+
+ _state_ap = entry_ap_fail_wait_stop();
+ }
+ break;
+
+ default:
+ MBED_ASSERT(FALSE);
+ break;
+ }
+}
+
+void OdinWiFiInterface::handle_wlan_status_ap_down()
+{
+ if (_debug) {
+ printf("cbWLAN_STATUS_AP_DOWN\n\r");
+ }
+
+ if(_debug) {
+ printf("MBED_IPSTACK_BRINGDOWN\r\n");
+ }
+
+ switch(_state_ap) {
+ case S_AP_WAIT_STOP:
+ _interface->bringdown();
+
+ _state_ap = entry_ap_wait_drv_stop();
+ break;
+
+ case S_AP_FAIL_WAIT_STOP:
+ _state_ap = S_AP_IDLE;
+
+ send_user_response_msg(ODIN_WIFI_MSG_USER_AP_START, _ap.error_code);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+}
+
+void OdinWiFiInterface::init(bool debug = false)
+{
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ // Initialise internal variables
+ _state = S_NOT_INITIALISED;
+ _state_sta = S_INVALID;
+ _state_ap = S_INVALID;
+
+ memset(&_sta, 0, sizeof(sta_s));
+ _sta.security = NSAPI_SECURITY_WPA_WPA2;
+ set_dhcp(true);
+ _sta.timeout_ms = ODIN_WIFI_STA_DEFAULT_CONN_TMO;
+
+ memset(&_ap, 0, sizeof(ap_s));
+ _sta.security = NSAPI_SECURITY_WPA_WPA2;
+ _ap.use_dhcp = true;
+ _ap.beacon_interval = 100;
+
+ _scan_active = false;
+ _scan_list = 0;
+ _scan_list_size = 0;
+ _scan_list_cnt = 0;
+ memset(&_scan_cache, 0, sizeof(scan_cache_s));
+
+ _debug = debug;
+ _dbg_timeout = 0;
+
+ memset(_mac_addr_str, 0, ODIN_WIFI_MAX_MAC_ADDR_STR);
+ memset(&_wlan_status_connected_info, 0, sizeof(cbWLAN_StatusConnectedInfo));
+ memset(&_wlan_status_disconnected_info, 0, sizeof(cbWLAN_StatusDisconnectedInfo));
+
+ _msg_pool = new MemoryPool<odin_wifi_msg_s, 7>();
+
+ if(!_wlan_initialized) {
+
+ _target_id = cbMAIN_initWlan();
+ MBED_ASSERT(_target_id != cbMAIN_TARGET_INVALID_ID);
+ }
+ cbMAIN_driverLock();
+ cbMAIN_WlanStartParams startParams;
+
+ memset(&startParams, 0, sizeof(startParams));
+
+ startParams.txPowerSettings.lowTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+ startParams.txPowerSettings.medTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+ startParams.txPowerSettings.maxTxPowerLevel = cbWLAN_TX_POWER_AUTO;
+
+ cb_int32 status = cbMAIN_startWlan(_target_id, &startParams);
+ MBED_ASSERT(status == cbSTATUS_OK);
+
+ cbRTSL_Status reg_status = cbWLAN_registerStatusCallback(wlan_callb_s::status_indication_callback, this);
+ MBED_ASSERT(reg_status == cbSTATUS_OK);
+
+ if(!_wlan_initialized) {
+ cbMAIN_startOS();
+ }
+ cbMAIN_driverUnlock();
+
+ _state = S_WAIT_START;
+
+ _thread.start(callback(wlan_callb_s::odin_thread_fcn, this));
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+}
+
+void OdinWiFiInterface::send_user_response_msg(unsigned int type, nsapi_error_t error_code)
+{
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = type;
+ msg->data.user_response.error = error_code;
+
+ osStatus ok = _out_queue.put(msg, 0);
+ MBED_ASSERT(ok == osOK);
+}
+
+nsapi_error_t OdinWiFiInterface::wlan_set_channel(uint8_t channel)
+{
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+ cbRTSL_Status status = cbSTATUS_OK;
+
+ if (channel != 0)
+ {
+ cbWLAN_ChannelList channel_list;
+
+ channel_list.length = 1;
+ channel_list.channels[0] = channel;
+
+ cbMAIN_driverLock();
+ status = cbWLAN_setChannelList(&channel_list);
+ cbMAIN_driverUnlock();
+ }
+ else
+ {
+ cbMAIN_driverLock();
+ status = cbWLAN_setChannelList(NULL);
+ cbMAIN_driverUnlock();
+ }
+
+ if(status != cbSTATUS_OK) {
+ error_code = NSAPI_ERROR_UNSUPPORTED;
+ }
+
+ return error_code;
+}
+
+nsapi_error_t OdinWiFiInterface::wlan_connect(
+ const char *ssid,
+ const char *passwd,
+ nsapi_security_t security)
+{
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+ cbRTSL_Status status = cbSTATUS_OK;
+ cbWLAN_CommonConnectParameters connect_params;
+
+ memset(&connect_params, 0, sizeof(cbWLAN_CommonConnectParameters));
+
+ strncpy((char*)connect_params.ssid.ssid, ssid, cbWLAN_SSID_MAX_LENGTH);
+ connect_params.ssid.ssidLength = strlen((const char*)connect_params.ssid.ssid);
+
+ switch (security)
+ {
+ case NSAPI_SECURITY_NONE:
+ cbMAIN_driverLock();
+ status = cbWLAN_connectOpen(&connect_params);
+ cbMAIN_driverUnlock();
+ break;
+ case NSAPI_SECURITY_WPA:
+ case NSAPI_SECURITY_WPA2:
+ case NSAPI_SECURITY_WPA_WPA2:
+ char temp_passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH];
+ cbWLAN_WPAPSKConnectParameters wpa_connect_params;
+
+ memset(temp_passphrase, 0, cbWLAN_MAX_PASSPHRASE_LENGTH);
+ strncpy(temp_passphrase, passwd, cbWLAN_MAX_PASSPHRASE_LENGTH);
+
+ cbMAIN_driverLock();
+ status = cbWLAN_Util_PSKFromPWD(temp_passphrase, connect_params.ssid, wpa_connect_params.psk.key);
+
+ if (status == cbSTATUS_OK) {
+ status = cbWLAN_connectWPAPSK(&connect_params, &wpa_connect_params);
+ }
+ cbMAIN_driverUnlock();
+ if(_debug) {printf("cbWLAN_connect: %d\r\n", status);}
+ break;
+
+ case NSAPI_SECURITY_WEP:
+ default:
+ status = cbSTATUS_ERROR;
+ break;
+ }
+
+ if(status != cbSTATUS_OK) {
+ error_code = NSAPI_ERROR_UNSUPPORTED;
+ }
+
+ return error_code;
+}
+
+nsapi_error_t OdinWiFiInterface::wlan_ap_start(
+ const char *ssid,
+ const char *pass,
+ nsapi_security_t security,
+ uint8_t channel,
+ uint16_t beacon_interval)
+{
+ cbRTSL_Status status = cbSTATUS_ERROR;
+ nsapi_error_t error_code = NSAPI_ERROR_OK;
+
+ cbWLAN_CommonApParameters params;
+ cbWLAN_WPAPSKApParameters wpa_params;
+
+ char temp_passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH];
+
+ memset(¶ms, 0, sizeof(cbWLAN_CommonApParameters));
+ memset(&wpa_params, 0, sizeof(cbWLAN_WPAPSKApParameters));
+ memset(temp_passphrase, 0, cbWLAN_MAX_PASSPHRASE_LENGTH);
+
+ params.ssid.ssidLength = strlen(ssid);
+ memcpy(params.ssid.ssid, ssid, params.ssid.ssidLength);
+ params.channel = channel;
+ params.basicRates = cbRATE_MASK_01 | APP_MASK_SHIFTUP(cbRATE_MASK_01, cbRATE_MASK_G);
+ params.allowedRates = ODIN_WIFI_AP_ALLOWED_RATE_MASK;
+ cbMAIN_driverLock();
+ status = cbWLAN_ioctl(cbWLAN_IOCTL_SET_AP_BEACON_INTERVAL, (void*)beacon_interval);
+ cbMAIN_driverUnlock();
+
+ if (status != cbSTATUS_OK) {
+ error_code = NSAPI_ERROR_PARAMETER;
+ } else {
+ switch (security) {
+ case NSAPI_SECURITY_NONE:
+ cbMAIN_driverLock();
+ status = cbWLAN_apStartOpen(¶ms);
+ cbMAIN_driverUnlock();
+ break;
+
+ case NSAPI_SECURITY_WEP:
+ status = cbSTATUS_ERROR;
+ break;
+
+ case NSAPI_SECURITY_WPA:
+ case NSAPI_SECURITY_WPA2:
+ case NSAPI_SECURITY_WPA_WPA2:
+ set_wpa_rsn_cipher(security, wpa_params.wpaCiphers, wpa_params.rsnCiphers);
+
+ memcpy(temp_passphrase, pass, strlen(pass));
+
+ cbMAIN_driverLock();
+ status = cbWLAN_Util_PSKFromPWD(temp_passphrase, params.ssid, wpa_params.psk.key);
+
+ if (status == cbSTATUS_OK) {
+ status = cbWLAN_apStartWPAPSK(¶ms, &wpa_params);
+ }
+ cbMAIN_driverUnlock();
+ break;
+
+ default:
+ status = cbSTATUS_ERROR;
+ break;
+ }
+
+ if (status != cbSTATUS_OK) {
+ error_code = NSAPI_ERROR_UNSUPPORTED;
+ }
+ }
+
+ return error_code;
+}
+
+void OdinWiFiInterface::wlan_scan_indication(cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result)
+{
+ //If ongoing scan
+ if(_scan_active) {
+
+ //To save msg buffers only send last result as a message to _in_queue
+ //Results before final one is stored
+
+ if(is_last_result == TRUE) {
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = cbWLAN_SCAN_INDICATION;
+
+ osStatus ok = _in_queue.put(msg);
+ MBED_ASSERT(ok == osOK);
+ }
+ else {
+ osStatus res = _mutex.lock();
+ MBED_ASSERT(res == osOK);
+
+ // Add scan result to scan_list
+ update_scan_list(scan_info);
+
+ res = _mutex.unlock();
+ MBED_ASSERT(res == osOK);
+ }
+ }
+ else {
+ if(_debug) printf("UNEXPECTED SCAN IND\r\n");
+ }
+}
+
+void OdinWiFiInterface::wlan_status_indication(cbWLAN_StatusIndicationInfo status, void *data)
+{
+ struct odin_wifi_msg_s* msg = _msg_pool->alloc();
+ MBED_ASSERT(msg != NULL);
+
+ msg->type = status;
+ memcpy(&(msg->data), data, sizeof(odin_wifi_msg_s::data_t));
+
+ osStatus ok = _in_queue.put(msg, 0);
+ MBED_ASSERT(ok == osOK);
+}
+
+static nsapi_security_t convertToNSAPI_security(cbWLAN_AuthenticationSuite authSuit)
+{
+ nsapi_security_t result = NSAPI_SECURITY_UNKNOWN;
+
+ if (authSuit == cbWLAN_AUTHENTICATION_SUITE_NONE)
+ result = NSAPI_SECURITY_NONE;
+ else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_SHARED_SECRET)
+ result = NSAPI_SECURITY_WEP;
+ else if ((authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA2) && (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA))
+ result = NSAPI_SECURITY_WPA_WPA2;
+ else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA)
+ result = NSAPI_SECURITY_WPA;
+ else if (authSuit & cbWLAN_AUTHENTICATION_SUITE_USE_WPA2)
+ result = NSAPI_SECURITY_WPA2;
+
+ return result;
+}
+
+static void set_wpa_rsn_cipher(
+ nsapi_security_t security,
+ cbWLAN_CipherSuite &wpa_ciphers,
+ cbWLAN_CipherSuite &rsn_ciphers)
+{
+ wpa_ciphers = cbWLAN_CIPHER_SUITE_NONE;
+ rsn_ciphers = cbWLAN_CIPHER_SUITE_NONE;
+
+ switch(security) {
+ case NSAPI_SECURITY_WPA:
+ wpa_ciphers = cbWLAN_CIPHER_SUITE_TKIP;
+ break;
+
+ case NSAPI_SECURITY_WPA2:
+ rsn_ciphers = cbWLAN_CIPHER_SUITE_AES_CCMP;
+ break;
+
+ case NSAPI_SECURITY_WPA_WPA2:
+ wpa_ciphers = (cbWLAN_CipherSuite)(cbWLAN_CIPHER_SUITE_TKIP | cbWLAN_CIPHER_SUITE_AES_CCMP);
+ rsn_ciphers = (cbWLAN_CipherSuite)(cbWLAN_CIPHER_SUITE_TKIP | cbWLAN_CIPHER_SUITE_AES_CCMP);
+ break;
+
+ default:
+ MBED_ASSERT(false);
+ break;
+ }
+}
+
+void OdinWiFiInterface::update_scan_list(cbWLAN_ScanIndicationInfo *scan_info)
+{
+ MBED_ASSERT(scan_info != 0);
+
+ bool found;
+
+ if(_scan_list != 0) {
+ //User included AP list in scan call
+ MBED_ASSERT(_scan_list_size > 0);
+ MBED_ASSERT(_scan_list_cnt <= _scan_list_size);
+
+ // If there is room for yet another found AP
+ if(_scan_list_cnt < _scan_list_size) {
+ found = false;
+
+ // Make sure it is not already previously found
+ for(nsapi_size_t i = 0; (i < _scan_list_cnt) && (!found); i++) {
+ if(memcmp(scan_info->bssid, _scan_list[i].get_bssid(), sizeof(cbWLAN_MACAddress)) == 0) {
+ found = true;
+ }
+ }
+
+ // If new AP, add it
+ if(!found) {
+ nsapi_wifi_ap_t ap;
+
+ memset(&ap, 0, sizeof(nsapi_wifi_ap_t));
+ memcpy(ap.bssid, scan_info->bssid, sizeof(ap.bssid));
+ strncpy((char*)ap.ssid, (char*)scan_info->ssid.ssid, scan_info->ssid.ssidLength);
+ ap.ssid[scan_info->ssid.ssidLength] = 0;
+ ap.security = convertToNSAPI_security(scan_info->authenticationSuites);
+ ap.rssi = (int8_t)(scan_info->rssi);
+ ap.channel = scan_info->channel;
+
+ WiFiAccessPoint wap(ap);
+
+ _scan_list[_scan_list_cnt] = wap;
+ _scan_list_cnt++;
+ }
+ }
+ }
+ else
+ {
+ //User did not include AP list in scan call. Instead use cache and report found number only
+ MBED_ASSERT(_scan_cache.count <= ODIN_WIFI_SCAN_CACHE_SIZE);
+
+ //New channel => clear cache
+ if(_scan_cache.last_channel != scan_info->channel) {
+ memset(&_scan_cache, 0, sizeof(scan_cache_s));
+ _scan_cache.last_channel = scan_info->channel;
+ }
+
+ //Check if already found
+ found = false;
+ if(_scan_cache.count > 0) {
+ for(int i = 0; (i < _scan_cache.count) && (!found); i++) {
+ if(memcmp(_scan_cache.bssid[i], scan_info->bssid, sizeof(cbWLAN_MACAddress)) == 0) {
+ found = true;
+ }
+ }
+ }
+
+ //If new AP
+ if(!found) {
+ //Add to cache (if space)
+ if(_scan_cache.count < ODIN_WIFI_SCAN_CACHE_SIZE) {
+ memcpy(_scan_cache.bssid[_scan_cache.count], scan_info->bssid, sizeof(cbWLAN_MACAddress));
+ _scan_cache.count++;
+ }
+
+ _scan_list_cnt++;
+ }
+ }
+}
+
+static void generateWEPKeys(const char *passphrase, cbWLAN_WEPKey keys[4])
+{
+ unsigned char pseed[4] = { 0 };
+ unsigned int randNumber, tmp, i, j;
+
+ for (i = 0; i < strlen(passphrase); i++)
+ {
+ pseed[i % 4] ^= (unsigned char)passphrase[i];
+ }
+
+ randNumber = pseed[0] | (pseed[1] << 8) | (pseed[2] << 16) | (pseed[3] << 24);
+
+ for (i = 0; i < 4; i++)
+ {
+ for (j = 0; j < 5; j++)
+ {
+ randNumber = (randNumber * 0x343fd + 0x269ec3) & 0xffffffff;
+ tmp = (randNumber >> 16) & 0xff;
+ keys[i].key[j] = (unsigned char)tmp;
+ }
+ keys[i].length = 5;
+ }
+}
+
+static bool is_valid_AP_channel(cbWLAN_Channel channel)
+{
+ bool ok = false;
+
+ switch (channel) {
+ case cbWLAN_CHANNEL_01:
+ case cbWLAN_CHANNEL_02:
+ case cbWLAN_CHANNEL_03:
+ case cbWLAN_CHANNEL_04:
+ case cbWLAN_CHANNEL_05:
+ case cbWLAN_CHANNEL_06:
+ case cbWLAN_CHANNEL_07:
+ case cbWLAN_CHANNEL_08:
+ case cbWLAN_CHANNEL_09:
+ case cbWLAN_CHANNEL_10:
+ case cbWLAN_CHANNEL_11:
+/*
+// TODO: DO NOT ENABLE UNTIL GUARANTEED EUROPEAN MODULE (or this is blocked in wlan driver..)
+ case cbWLAN_CHANNEL_12:
+ case cbWLAN_CHANNEL_13:
+*/
+ case cbWLAN_CHANNEL_36:
+ case cbWLAN_CHANNEL_40:
+ case cbWLAN_CHANNEL_44:
+ case cbWLAN_CHANNEL_48:
+ ok = true;
+ break;
+
+ default:
+ ok = false;
+ break;
+ }
+
+ return ok;
+}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h Thu Nov 08 11:46:34 2018 +0000
@@ -19,7 +19,7 @@
#include "WiFiInterface.h"
#ifdef DEVICE_WIFI_AP
-#include "WiFiSoftAPInterface.h"
+#include "UbloxWiFiSoftAPInterface.h"
#endif
#include "mbed.h"
@@ -29,6 +29,7 @@
#include "lwip/netif.h"
#include "rtos.h"
#include "cb_wlan.h"
+#include "wifi_emac.h"
#define ODIN_WIFI_MAX_MAC_ADDR_STR (18)
#define ODIN_WIFI_SCAN_CACHE_SIZE (5)
@@ -45,16 +46,18 @@
/** OdinWiFiInterface class
* Implementation of the WiFiInterface for the ODIN-W2 module
*/
-
+#ifdef DEVICE_WIFI_AP
+class OdinWiFiInterface : public WiFiInterface, public UbloxWiFiSoftAPInterface, public EMACInterface
+#else
class OdinWiFiInterface : public WiFiInterface, public EMACInterface
-
+#endif
{
public:
/** OdinWiFiInterface lifetime
*/
- OdinWiFiInterface();
+ OdinWiFiInterface(OdinWiFiEMAC &emac = OdinWiFiEMAC::get_instance(), OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance());
- OdinWiFiInterface(bool debug);
+ OdinWiFiInterface(bool debug, OdinWiFiEMAC &emac = OdinWiFiEMAC::get_instance(), OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance());
~OdinWiFiInterface();
@@ -138,6 +141,100 @@
*/
virtual nsapi_error_t set_timeout(int ms);
+#ifdef DEVICE_WIFI_AP
+
+ /** Set IP config for access point
+ *
+ * This function has to be called before the access point is started.
+ *
+ * @param gateway Null-terminated representation of the local gateway
+ * @param netmask Null-terminated representation of the network mask
+ * @return 0 on success, negative error code on failure
+ */
+ //TODO: In previous WiFiInterface.h but not in new UbloxWiFiSoftAPInterface
+ virtual nsapi_error_t set_ap_network(const char *ip_address, const char *netmask, const char *gateway);
+
+ /** Set the WiFi network credentials
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection
+ * (defaults to NSAPI_SECURITY_NONE)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_ap_credentials(const char *ssid, const char *pass = 0,
+ nsapi_security_t security = NSAPI_SECURITY_NONE);
+
+ /** Set the WiFi network channel
+ *
+ * @param channel Channel on which the connection is to be made.
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_ap_channel(uint8_t channel);
+
+ /** Gets the current number of active connections
+ *
+ * @return number of active connections
+ */
+ virtual int get_ap_connection_count();
+
+ /** Gets the max supported number of active connections
+ *
+ * @return maximum number of active connections
+ */
+ virtual int get_ap_max_connection_count();
+
+ /** Enable or disable DHCP on the network access point
+ *
+ * Enables DHCP in SoftAP mode. Defaults to enabled unless
+ * a static IP address has been assigned. Requires that the network is
+ * service stopped.
+ *
+ * @param dhcp True to enable DHCP
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t set_ap_dhcp(bool dhcp);
+
+ /** Set the beacon interval.
+ *
+ * Note that the value needs to be set before ap_start in order to take effect.
+ *
+ * @param interval Beason interval in time units (Default: 100 time units = 102.4 ms)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_ap_beacon_interval(uint16_t interval);
+
+ /** Start the interface
+ *
+ * Attempts to serve a WiFi network.
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
+ * @param channel Channel on which the connection is to be made.
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t ap_start(const char *ssid, const char *pass = 0,
+ nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0);
+
+ /** Start the interface
+ *
+ * Attempts to serve a WiFi network. Requires ssid to be set.
+ * passphrase is optional.
+ * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned.
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t ap_start();
+
+ /** Stop the interface
+ *
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t ap_stop();
+
+#endif
+
private:
enum OdinWifiState {
@@ -151,7 +248,6 @@
S_STA_CONNECTED,
S_STA_DISCONNECTED_WAIT_CONNECT,
S_STA_CONNECTION_FAIL_WAIT_DISCONNECT,
- //S_STA_LINK_LOSS_WAIT_DISCONNECT,
S_STA_WAIT_DISCONNECT,
S_AP_IDLE,
@@ -166,8 +262,8 @@
};
struct sta_s {
- const char *ssid;
- const char *passwd;
+ char ssid[cbWLAN_SSID_MAX_LENGTH];
+ char passwd[cbWLAN_MAX_PASSPHRASE_LENGTH];
nsapi_security_t security;
uint8_t channel;
int timeout_ms;
@@ -199,7 +295,6 @@
OdinWifiState entry_connect_fail_wait_disconnect();
OdinWifiState entry_wait_connect();
OdinWifiState entry_wait_disconnect();
- //OdinWifiState entry_link_loss_wait_disconnect(void);
OdinWifiState entry_ap_wait_start();
OdinWifiState entry_ap_started();
OdinWifiState entry_ap_wait_stop();
@@ -278,7 +373,6 @@
Queue<odin_wifi_msg_s, 1> _cache_queue;
MemoryPool<odin_wifi_msg_s, 7> *_msg_pool;
Thread _thread;
- //Timeout _timeout; //Randomly lost interrupts/callbacks; replaced by Timer
Timer _timer;
bool _debug;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/UbloxWiFiSoftAPInterface.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,108 @@
+
+/* UbloxWiFiSoftAPInterface
+ * Copyright (c) 2015 - 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef UBLOX_WIFI_SOFTAPINTERFACE_H
+#define UBLOX_WIFI_SOFTAPINTERFACE_H
+
+#include <string.h>
+#include "netsocket/WiFiAccessPoint.h"
+
+/** UbloxWiFiSoftAPInterface class
+ *
+ * Common interface that is shared between WiFi devices supporting SoftAP mode
+ */
+class UbloxWiFiSoftAPInterface
+{
+public:
+ /** UbloxWiFiSoftAPInterface lifetime
+ */
+ virtual ~UbloxWiFiSoftAPInterface() {};
+
+ /** Set the WiFi network credentials
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection
+ * (defaults to NSAPI_SECURITY_NONE)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_ap_credentials(const char *ssid, const char *pass = 0,
+ nsapi_security_t security = NSAPI_SECURITY_NONE) = 0;
+
+ /** Set the WiFi network channel
+ *
+ * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t set_ap_channel(uint8_t channel) = 0;
+
+ /** Gets the current number of active connections
+ *
+ * @return number of active connections
+ */
+ virtual int get_ap_connection_count() = 0;
+
+ /** Gets the max supported number of active connections
+ *
+ * @return maximum number of active connections
+ */
+ virtual int get_ap_max_connection_count() = 0;
+
+ /** Enable or disable DHCP on the network access point
+ *
+ * Enables DHCP in SoftAP mode. Defaults to enabled unless
+ * a static IP address has been assigned. Requires that the network is
+ * service stopped.
+ *
+ * @param dhcp True to enable DHCP
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t set_ap_dhcp(bool dhcp) = 0;
+
+ /** Start the interface
+ *
+ * Attempts to serve a WiFi network.
+ *
+ * @param ssid Name of the network to connect to
+ * @param pass Security passphrase to connect to the network
+ * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
+ * @param channel Channel on which the connection is to be made.
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t ap_start(const char *ssid, const char *pass = 0,
+ nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0) = 0;
+
+ /** Start the interface
+ *
+ * Attempts to serve a WiFi network. Requires ssid to be set.
+ * passphrase is optional.
+ * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned.
+ *
+ * @return 0 on success, negative error code on failure
+ */
+ virtual nsapi_error_t ap_start() = 0;
+
+ /** Stop the interface
+ *
+ * @return 0 on success, or error code on failure
+ */
+ virtual nsapi_error_t ap_stop() = 0;
+
+};
+
+#endif
+
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h Thu Nov 08 11:46:34 2018 +0000
@@ -55,6 +55,18 @@
cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */
} cbMAIN_WlanStartParams;
+#if (BLE_STACK_UBX != true)
+
+typedef void (*vs_cmd_send_t)(uint16_t opcode);
+
+typedef struct {
+ vs_cmd_send_t vs_command_callback;
+ char *Service_pack;
+ uint32_t service_pack_size;
+} cordio_callback_s;
+
+#endif /* !BLE_STACK_UBX */
+
/*---------------------------------------------------------------------------
* Callback to indicate that initialization of BT stack is completed.
*-------------------------------------------------------------------------*/
@@ -142,4 +154,31 @@
*/
extern void cbMAIN_dispatchEventQueue(void);
+#if (BLE_STACK_UBX != true)
+/**
+* Initialize BT Hardware by detecting if external LPO is connected else Emulate LPO by using TIMER1 and
+* configuring PORTA in alternate mode as source of external clk(LPO for BT).
+*
+* @return void
+*/
+void cbCordio_Btinit(cordio_callback_s *bt_callback_cordio);
+
+/**
+* Get BT address saved in OTP memory and provide it to stack for assignment.
+*
+* @param BdAddress Pointer to be initialized with BT address saved in OTP
+* @return void
+*/
+void cbCordio_Retreive_Btaddr(cb_uint8 *BdAddress);
+
+
+/**
+* Update HCI H4 UART baud-rate to 3Mbps to achieve minimum setup time.
+*
+* @return void
+*/
+void update_uart_baud_rate(void);
+
+#endif /* BLE_STACK_UBX */
+
#endif /*_CB_MAIN_H_*/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h Thu Nov 08 11:46:34 2018 +0000
@@ -295,7 +295,9 @@
* @ingroup wlan
*/
typedef enum {
- cbWLAN_IOCTL_FIRST
+ cbWLAN_IOCTL_FIRST = 0,
+ cbWLAN_IOCTL_SET_AP_BEACON_INTERVAL = 9, //!< Beacon period in TUs
+ cbWLAN_IOCTL_GET_AP_BEACON_INTERVAL = 10, //!< Beacon period in TUs
} cbWLAN_Ioctl;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,9 +45,9 @@
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be used
+ ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be used
; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
- RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4)) { ; RW data
+ RW_IRAM1 (0x20000000 + 0x1B0) (0x30000 - 0x1B0) { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 (0x10000000) 0x10000 {
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -45,8 +45,8 @@
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
+ ; Total: 107 vectors = 428 bytes(0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x30000-0x1B0) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld Thu Nov 08 11:46:34 2018 +0000
@@ -7,11 +7,12 @@
#endif
/* Linker script to configure memory regions. */
+/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
+ RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192k - (0x1AC+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -93,13 +94,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +108,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +116,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +125,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -89,6 +89,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,3 +309,25 @@
{PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -89,6 +89,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -380,3 +380,42 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
+ {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -325,6 +325,14 @@
SYS_WKUP0 = PA_0,
SYS_WKUP1 = PC_13,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PD_11,
+ QSPI1_IO1 = PD_12,
+ QSPI1_IO2 = PE_2,
+ QSPI1_IO3 = PD_13,
+ QSPI1_SCK = PB_2,
+ QSPI1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/stm32f446xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/stm32f446xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1C4) (0x20000-0x1C4) { ; RW data
+ ; Total: 113 vectors = 452 bytes (0x1C4) 8-byte aligned = 0x1C8 (0x1C4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x20000-0x1C8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/stm32f446xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/stm32f446xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1C4) (0x20000-0x1C4) { ; RW data
+ ; Total: 113 vectors = 452 bytes (0x1C4) 8-byte aligned = 0x1C8 (0x1C4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C8) (0x20000-0x1C8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -7,10 +7,11 @@
#endif
/* Linker script to configure memory regions. */
+/* 0x1C4 resevered for vectors; 8-byte aligned = 0x1C8 (0x1C4 + 0x4)*/
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 128k - 0x1C4
+ RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 128k - (0x1C4+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -92,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -114,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -123,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/stm32f446xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/stm32f446xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -3,10 +3,10 @@ define symbol __region_ROM_start__ = 0x08000000; define symbol __region_ROM_end__ = 0x0807FFFF; -/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM */ +/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 113 vectors * 4= 452 bytes (0x1C4) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200001C3; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200001C4; +define symbol __NVIC_end__ = 0x200001C7; /* Add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200001C8; define symbol __region_RAM_end__ = 0x2001FFFF; /* Memory regions */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -92,6 +92,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -388,3 +388,44 @@
{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D21
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+// {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to uSD_D1
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to uSD_D2
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to MIC_CK [MP34DT01TR_CLK]
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to AUDIO_RST [CS43L22_RESET]
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to D4
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to D5
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to D6
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to D7
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 // Connected to USART6_RX
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 // Connected to ARDUINO USART6_TX
+ {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO0 // Connected to SDCKE0 [MT48LC4M32B2B5-6A_CKE]
+ {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO1 // Connected to SDNE0 [MT48LC4M32B2B5-6A_CS]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_CLK
+ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK [N25Q128A13EF840F_C]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
+// {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -406,6 +406,14 @@
SYS_TRACED3_ALT0 = PE_6,
SYS_WKUP = PA_0,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PF_8,
+ QSPI_FLASH1_IO1 = PF_9,
+ QSPI_FLASH1_IO2 = PF_7,
+ QSPI_FLASH1_IO3 = PF_6,
+ QSPI_FLASH1_SCK = PF_10,
+ QSPI_FLASH1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data
+ ; Total: 109 vectors = 436 bytes (0x1B4) 8-byte aligned = 0x1B8 (0x1B4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B8) (0x50000-0x1B8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/stm32f469xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/stm32f469xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data
+ ; Total: 109 vectors = 436 bytes (0x1B4) 8-byte aligned = 0x1B8 (0x1B4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B8) (0x50000-0x1B8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/STM32F469XI.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/STM32F469XI.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,9 @@
/* Linker script to configure memory regions. */
+/* 0x1B4 resevered for vectors; 8-byte aligned = 0x1B8 (0x1B4 + 0x4)*/
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2M
- RAM (rwx) : ORIGIN = 0x200001B4, LENGTH = 320k - 0x1B4
+ RAM (rwx) : ORIGIN = 0x200001B8, LENGTH = 320k - (0x1B4+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +116,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/stm32f469xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -3,10 +3,10 @@ define symbol __region_ROM_start__ = 0x08000000; define symbol __region_ROM_end__ = 0x081FFFFF; -/* [RAM = 384kb = 0x60000] Vector table dynamic copy: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM */ +/* [RAM = 384kb = 0x60000] Vector table dynamic copy: 109 vectors * 4 = 436 bytes (0x1B4) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200001B3; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200001B4; +define symbol __NVIC_end__ = 0x200001B7; /* Add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200001B8; define symbol __region_RAM_end__ = 0x2004FFFF; /* Memory regions */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -58,6 +58,16 @@
RNG_HandleTypeDef handle;
};
+struct qspi_s {
+ QSPI_HandleTypeDef handle;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,9 +18,6 @@
HAL_StatusTypeDef HAL_InitPre(void);
-/* this function is needed to peform hardware initialization that must happen
- * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
- * put here as it depends on some APIs that need uVisor to be enabled */
HAL_StatusTypeDef HAL_InitPre(void)
{
/* Set Interrupt Group Priority */
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -93,6 +93,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -406,3 +406,41 @@
{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to DCMI_PWR_EN
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S]
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SDMMC1_D1
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SDMMC_D2
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to SDMMC_D3
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1]
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3]
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_D4 [MT48LC4M32B2B5-6A_DQ4]
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_D5 [MT48LC4M32B2B5-6A_DQ5]
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to FMC_D6 [MT48LC4M32B2B5-6A_DQ6]
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to FMC_D7 [MT48LC4M32B2B5-6A_DQ7]
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARDUINO A5
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARDUINO A4
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARDUINO A3
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARDUINO A2
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to DCMI_VSYNC
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to NC2
+ {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_SDNE0 [MT48LC4M32B2B5-6A_CS]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S]
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to SDMMC_D3
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -420,6 +420,14 @@
SYS_WKUP5 = PI_8,
SYS_WKUP6 = PI_11,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PD_11,
+ QSPI_FLASH1_IO1 = PD_12,
+ QSPI_FLASH1_IO2 = PE_2,
+ QSPI_FLASH1_IO3 = PD_13,
+ QSPI_FLASH1_SCK = PB_2,
+ QSPI_FLASH1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -93,6 +93,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -378,3 +378,39 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -354,6 +354,14 @@
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
+ /**** QSPI pins ****/
+ QSPI_FLASH1_IO0 = PD_11,
+ QSPI_FLASH1_IO1 = PD_12,
+ QSPI_FLASH1_IO2 = PE_2,
+ QSPI_FLASH1_IO3 = PD_13,
+ QSPI_FLASH1_SCK = PB_2,
+ QSPI_FLASH1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld Thu Nov 08 11:46:34 2018 +0000
@@ -93,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -58,6 +58,16 @@
RNG_HandleTypeDef handle;
};
+struct qspi_s {
+ QSPI_HandleTypeDef handle;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -93,6 +93,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -378,3 +378,39 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -354,6 +354,14 @@
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PD_11,
+ QSPI1_IO1 = PD_12,
+ QSPI1_IO2 = PE_2,
+ QSPI1_IO3 = PD_13,
+ QSPI1_SCK = PB_2,
+ QSPI1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_GCC_ARM/STM32F756xG.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -94,6 +94,10 @@
CAN_3 = (int)CAN3_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -418,3 +418,42 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -359,6 +359,14 @@
SYS_WKUP3 = PC_1,
SYS_WKUP4 = PC_13,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PD_11,
+ QSPI1_IO1 = PD_12,
+ QSPI1_IO2 = PE_2,
+ QSPI1_IO3 = PD_13,
+ QSPI1_SCK = PB_2,
+ QSPI1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld Thu Nov 08 11:46:34 2018 +0000
@@ -93,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -94,6 +94,10 @@
CAN_3 = (int)CAN3_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -450,3 +450,44 @@
{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D21
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S]
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 [USB3320C-EZK_D3]
+ {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
+ {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [MT25QL512ABB1EW9_DQ1]
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to DFSDM_DATIN5 [TP5]
+ {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SPDIF_TX [TP20]
+ {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to AUDIO_SCL [WM8994ECS/R_SCLK]
+ {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3]
+ {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
+ {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_D4 [MT48LC4M32B2B5-6A_DQ4]
+ {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_D5 [MT48LC4M32B2B5-6A_DQ5]
+ {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to FMC_D6 [MT48LC4M32B2B5-6A_DQ6]
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to FMC_D7 [MT48LC4M32B2B5-6A_DQ7]
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D3/PWM
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D6/PWM
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARDUINO A3
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARDUINO A2
+ {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to uSD_D0
+ {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+ {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_SDCKE0 [MT48LC4M32B2B5-6A_CKE]
+ {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_SDNE0 [MT48LC4M32B2B5-6A_CS]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK
+ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to ARDUINO A1
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S]
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 [USB3320C-EZK_D3]
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to DFSDM_DATIN5 [TP5]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -427,6 +427,14 @@
SYS_WKUP5 = PI_8,
SYS_WKUP6 = PI_11,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PC_9,
+ QSPI_FLASH1_IO1 = PC_10,
+ QSPI_FLASH1_IO2 = PE_2,
+ QSPI_FLASH1_IO3 = PD_13,
+ QSPI_FLASH1_SCK = PB_2,
+ QSPI_FLASH1_CSN = PB_6,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -31,6 +31,7 @@
#include "stm32f7xx.h"
#include "mbed_error.h"
+#include "nvic_addr.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -92,7 +93,7 @@
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
#endif
}
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_MICRO/stm32f769xi.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_MICRO/stm32f769xi.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2016, STMicroelectronics
@@ -27,16 +28,25 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000)
-LR_IROM1 0x08000000 0x200000 { ; load region size_region
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
- ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+; 2048 KB FLASH (0x200000)
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
+ ; 512KB SRAM (0x80000)
+ ; Total: 126 vectors = 504 bytes (0x1F8 + 0 byte for 8-byte data alignment) to be reserved in RAM
RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_STD/stm32f769xi.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_STD/stm32f769xi.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2016, STMicroelectronics
@@ -27,16 +28,25 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000)
-LR_IROM1 0x08000000 0x200000 { ; load region size_region
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
- ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+; 2048 KB FLASH (0x200000)
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
+ ; 512KB SRAM (0x80000)
+ ; Total: 126 vectors = 504 bytes (0x1F8 + 0 byte for 8-byte data alignment) to be reserved in RAM
RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_GCC_ARM/STM32F769xI.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_GCC_ARM/STM32F769xI.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,7 +1,16 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 2048K
+#endif
+
/* Linker script to configure memory regions. */
+/* Total: 126 vectors = 504 bytes (0x1F8 + 0 byte for 8-byte data alignment) to be reserved in RAM */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8
}
@@ -84,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_IAR/stm32f769xi.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_IAR/stm32f769xi.icf Thu Nov 08 11:46:34 2018 +0000
@@ -1,11 +1,15 @@
/* [ROM = 2048kb = 0x200000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x081FFFFF;
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
-/* [RAM = 512kb = 0x80000] Vector table dynamic copy: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM */
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 512kb = 0x80000] */
+/* Total: 126 vectors = 504 bytes (0x1F8 + 0 byte for 8-byte data alignment) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200001F7; /* Aligned on 8 bytes */
+define symbol __NVIC_end__ = 0x200001F7;
define symbol __region_RAM_start__ = 0x200001F8;
define symbol __region_RAM_end__ = 0x2007FFFF;
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/STM32L031K6.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/STM32L031K6.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/STM32L073XZ.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/STM32L073XZ.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/STM32L053X8.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/STM32L053X8.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -70,9 +70,8 @@
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
- {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
- {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
- {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17 // VREFINT
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 // VSENSE
{NC, NC, 0}
};
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/TOOLCHAIN_GCC_ARM/STM32L072XZ.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/TOOLCHAIN_GCC_ARM/STM32L072XZ.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -48,9 +48,8 @@
};
const PinMap PinMap_ADC_Internal[] = {
- {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // Internal channel
- {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // Internal channel
- {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // Internal channel
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17 // VREFINT
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 // VSENSE
{NC, NC, 0}
};
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/TOOLCHAIN_GCC_ARM/STM32L082xZ.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/TOOLCHAIN_GCC_ARM/STM32L082xZ.ld Thu Nov 08 11:46:34 2018 +0000
@@ -84,13 +84,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +98,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +115,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L0/analogin_device.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/analogin_device.c Thu Nov 08 11:46:34 2018 +0000
@@ -172,6 +172,12 @@
HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
+ /* need to wait for some stabilization time after setting the TSEN bit in the ADC_CCR
+ register to wake up the temperature sensor from power down mode */
+ if (sConfig.Channel == ADC_CHANNEL_TEMPSENSOR) {
+ wait_ms(20);
+ }
+
HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_STD/stm32l152rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_STD/stm32l152rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_GCC_ARM/STM32L152XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_GCC_ARM/STM32L152XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -3,9 +3,10 @@
{
/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
* bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+ * 8-byte aligned (0x13C) = 0x140
*/
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
- RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
+ RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-(0x13C+0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -87,13 +88,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,7 +102,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -109,7 +110,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -118,12 +119,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -46,8 +46,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -46,8 +46,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) + 0x4(8-byte aligned) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -10,9 +10,10 @@
{
/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
* bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+ * 8-byte aligned(0x13C) = 0x140
*/
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
+ RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140
}
/* Linker script to place sections and symbol values. Should be used together
@@ -94,13 +95,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -108,7 +109,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -116,7 +117,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -125,12 +126,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 61 vectors = 244 bytes (0xF4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xF4) (0x8000-0xF4) { ; RW data
+ ; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xF8) (0x8000-0xF8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 61 vectors = 244 bytes (0xF4) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xF4) (0x8000-0xF4) { ; RW data
+ ; 61 vectors = 244 bytes (0xF4) 8-byte aligned = 0xF8 (0xF4 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xF8) (0x8000-0xF8) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld Thu Nov 08 11:46:34 2018 +0000
@@ -3,10 +3,10 @@
MEMORY
{
/* 128KB FLASH, 32KB RAM, Reserve up till 0xF4. There are 61 vectors = 244
- * bytes (0xF4) in RAM.
+ * bytes (0xF4) in RAM. 8-byte aligned(0xF4) = 0xF8
*/
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
- RAM (rwx) : ORIGIN = 0x200000F4, LENGTH = 0x8000-0xF4
+ RAM (rwx) : ORIGIN = 0x200000F8, LENGTH = 0x8000-0xF8
}
/* Linker script to place sections and symbol values. Should be used together
@@ -88,13 +88,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -102,7 +102,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -110,7 +110,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -119,12 +119,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,8 +7,8 @@ /* [RAM = 32kb = 0x8000] Vector table dynamic copy: 61 vectors = 244 bytes (0xF4) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000F3; -define symbol __region_RAM_start__ = 0x200000F4; +define symbol __NVIC_end__ = 0x200000F7; /* Add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200000F8; define symbol __region_RAM_end__ = 0x20007FFF; /* Memory regions */
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_MICRO/stm32l152re.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_MICRO/stm32l152re.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x14000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_STD/stm32l152re.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_STD/stm32l152re.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4)to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x14000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_GCC_ARM/STM32L152XE.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_GCC_ARM/STM32L152XE.ld Thu Nov 08 11:46:34 2018 +0000
@@ -3,9 +3,10 @@
{
/* 512KB FLASH, 80KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
* bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+ * 8-byte aligned(0x13C) = 0x140
*/
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512k
- RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x14000-0x13C
+ RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x14000-0x140
}
/* Linker script to place sections and symbol values. Should be used together
@@ -87,13 +88,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -101,7 +102,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -109,7 +110,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -118,12 +119,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes(0x124) 8-byte aligned = 0x128 (0x124 + 0x4)to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -4,9 +4,10 @@
{
/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
* bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+ * 8-byte aligned(0x13C) = 0x140
*/
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
- RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
+ RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140
}
/* Linker script to place sections and symbol values. Should be used together
@@ -88,13 +89,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -102,7 +103,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -110,7 +111,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -119,12 +120,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -46,8 +46,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct Thu Nov 08 11:46:34 2018 +0000
@@ -46,8 +46,8 @@
.ANY (+RO)
}
- ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
+ ; 73 vectors = 292 bytes (0x124) 8-byte aligned = 0x128 (0x124 + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x128) (0x8000-0x128) { ; RW data
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld Thu Nov 08 11:46:34 2018 +0000
@@ -9,10 +9,11 @@
MEMORY
{
/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
- * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
+ * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138\
+ * 8-byte aligned(0x13C) = 0x140
*/
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
+ RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x8000-0x140
}
/* Linker script to place sections and symbol values. Should be used together
@@ -94,13 +95,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -108,7 +109,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -116,7 +117,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -125,12 +126,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > RAM
--- a/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c Thu Nov 08 11:46:34 2018 +0000
@@ -105,6 +105,9 @@
ADC_ChannelConfTypeDef sConfig = {0};
// Configure ADC channel
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_48CYCLES;
+
switch (obj->channel) {
case 0:
sConfig.Channel = ADC_CHANNEL_0;
@@ -156,9 +159,11 @@
break;
case 16:
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+ sConfig.SamplingTime = ADC_SAMPLETIME_384CYCLES;
break;
case 17:
sConfig.Channel = ADC_CHANNEL_VREFINT;
+ sConfig.SamplingTime = ADC_SAMPLETIME_384CYCLES;
break;
case 18:
sConfig.Channel = ADC_CHANNEL_18;
@@ -216,9 +221,6 @@
return 0;
}
- sConfig.Rank = ADC_REGULAR_RANK_1;
- sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES;
-
HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
HAL_ADC_Start(&obj->handle); // Start conversion
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX PB_6
+#define STDIO_UART_RX PB_7
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,268 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // IN5 - ARDUINO A0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6 - ARDUINO A1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // IN9 - ARDUINO A2
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // IN1 - ARDUINO A5
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // IN2 - ARDUINO A4
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // IN4
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin)
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (used by us_ticker)
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (used by us_ticker)
+ {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // PA_2 is used as SERIAL_TX
+ {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (used by us_ticker)
+ {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // PA_3 is used as SERIAL_RX
+ {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (used by us_ticker)
+// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+ {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11
+// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+// {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO D3
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D5
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO D10
+ {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO D6
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+ {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+ {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO D9
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+// {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // LED D4
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+// {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // LED D4
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,398 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino connector namings
+ A0 = PC_2,
+ A1 = PC_13, //rev b PC_0; rev c PC_13
+ A2 = PC_4,
+ A3 = PE_6, //reb b PB_1; rev c PE_6
+ A4 = PA_6,
+ A5 = PG_8,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PB_15,
+ D3 = PA_0,
+ D4 = PA_7,
+ D5 = PA_9,
+ D6 = PA_1,
+ D7 = PG_7,
+ D8 = PB_0,
+ D9 = PB_10,
+ D10 = PC_8,
+ D11 = PB_5,
+ D12 = PG_3,
+ D13 = PG_2,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // 40 pin
+ IO_00 = D1,
+ IO_01 = D4,
+ IO_02 = D8,
+ IO_03 = D6,
+ IO_04 = D11,
+ IO_05 = D13,
+ IO_06 = D15,
+ IO_07 = D2,
+ IO_08 = A0,
+ IO_09 = A3,
+ IO_10 = A1,
+ IO_11 = A4,
+ IO_12 = A2,
+ IO_13 = D9,
+ IO_14 = A5,
+ IO_15 = D14,
+ IO_16 = D12,
+ IO_17 = D10,
+ IO_18 = D3,
+ IO_19 = D5,
+ IO_20 = D7,
+ IO_21 = D0,
+
+ // 40 pin USB debug port
+ USBTX = PB_6,
+ USBRX = PB_7,
+
+ //UARTS
+ UART3_TX = PD_2,
+ UART3_RX = PD_9,
+ UART3_CTS = PD_11,
+ UART3_RTS = PD_12,
+
+ UART2_TX = PA_2,
+ UART2_RX = PA_3,
+ UART2_RTS = PA_1,
+ UART2_CTS = PA_0,
+ UART2_DSR = PA_9,
+ UART2_DTR = PG_7,
+ UART2_DCD = PA_7,
+
+
+ UART1_TX = PB_6,
+ UART1_RX = PB_7,
+ UART1_RTS = PA_12,
+ UART1_CTS = PA_11,
+
+ // 40 pin JTAG/SWD
+ J_TCK = PA_14, // a.k.a. SWCLK
+ J_TDI = PA_15,
+ J_RST = PB_4,
+ J_TDO = PB_3, // a.k.a. SWO
+ J_TMS = PA_13, // a.k.a. SWDIO
+
+ // Generic signals namings
+ LED1 = D3,
+ LED2 = D3,
+ LED3 = D3,
+ LED4 = D3,
+
+ // SERIAL PORT
+ SERIAL_TX = D1,
+ SERIAL_RX = D0,
+ SERIAL_RTS = D6,
+ SERIAL_CTS = D3,
+ SERIAL_DCD = D4,
+ SERIAL_DSR = D5,
+ SERIAL_DTR = D7,
+ SERIAL_RI = D8,
+
+ // SPI1 and SPI2 are available on Arduino pins
+ SPI1_MOSI = D11,
+ SPI1_MISO = D12,
+ SPI1_SCK = D13,
+ SPI2_MOSI = D2,
+ SPI2_MISO = A0,
+ SPI2_SCK = D9,
+
+ // SPI3 connects to flash part
+ SPI3_MOSI = PC_12,
+ SPI3_MISO = PC_11,
+ SPI3_SCK = PC_10,
+ SPI3_SSEL = PG_12,
+
+ // I2C1 and I2C3 are available on Arduino pins
+ I2C1_SCL = D15,
+ I2C1_SDA = D14,
+ I2C3_SCL = D7,
+ I2C3_SDA = A5,
+
+ // Modem
+ RADIO_PWR = PC_3,
+ RADIO_RESET = PF_3,
+ RADIO_TX = PD_8,
+ RADIO_RX = PD_9,
+ RADIO_RI = PD_10,
+ RADIO_CTS = PD_11,
+ RADIO_RTS = PD_12,
+ RADIO_DTR = PD_13,
+ RADIO_DCD = PD_14,
+ RADIO_DSR = PD_15,
+ RADIO_ONOFF = PE_4, //rev b PC_13; rev c PC_0 PE_4
+ MON_1V8 = PC_5,
+ VUSB_EN = PE_3,
+ // Power control for level shifter and SPI flash. Low powers on.
+ BUF_EN = PC_6,
+ VMEM_EN = PE_1,
+ VUSB_DET = PE_3,
+
+ MDMPWRON = RADIO_ONOFF, // 3G_ONOFF DragonFly Design Guide, Page No. 16
+ MDMTXD = RADIO_TX, // Transmit Data
+ MDMRXD = RADIO_RX, // Receive Data
+ MDMRTS = RADIO_RTS, // Request to Send
+ MDMCTS = RADIO_CTS, // Clear to Send
+ MDMDCD = RADIO_DCD, // Data Carrier Detect
+ MDMDSR = RADIO_DSR, // Data Set Ready
+ MDMDTR = RADIO_DTR, // Data Terminal Ready
+ MDMRI = RADIO_RI, // Ring Indicator
+
+ CELL_GPIO5 = PE_11,
+ CELL_GPIO2 = PE_13,
+ CELL_GPIO3 = PE_14,
+ CELL_GPIO4 = PE_15,
+
+ // Voltage measuring
+ VCC_IN_MEAS_EN = PB_12,
+ VCC_IN_MEAS = PC_0,
+
+ // added to support ppp
+ MDM_PIN_POLARITY = 0,
+ MDMRST = RADIO_RESET,
+ MDMCURRENTSENSE = (int) 0xFFFFFFFF,
+
+ // GNSS
+ GNSSEN = (int) 0xFFFFFFFF, // VCC_IO to GNSS, should be set to push-pull, no pull-up, output
+ GNSSTXD =(int) 0xFFFFFFFF,
+ GNSSRXD = (int) 0xFFFFFFFF,
+ PWR3V3 = (int) 0xFFFFFFFF,
+
+ WAKEUP = D3,
+
+ // TIMERS
+ TIM2_1 = PA_15,
+ TIM2_2 = PB_3,
+ TIM2_3 = PA_2,
+ TIM3_1 = PB_4,
+ TIM3_2 = PA_7,
+ TIM3_3 = PB_0,
+ TIM4_3 = PB_8,
+ TIM5_1 = PA_0,
+ TIM5_2 = PA_1,
+ TIM5_3 = PA_2,
+ TIM7_1 = PA_7,
+ TIM8_3 = PC_8,
+
+ // CAN
+ CAN1_TX = PB_9,
+ CAN1_RX = PB_8,
+
+ // ADC
+ ADC1_IN7 = PA_2,
+ ADC2_IN7 = PA_2,
+
+ ADC1_IN12 = PA_7,
+ ADC2_IN12 = PA_7,
+
+ ADC1_IN15 = PB_0,
+ ADC2_IN15 = PB_0,
+
+ ADC1_IN6 = PA_1,
+ ADC2_IN6 = PA_1,
+
+ ADC1_IN3 = PC_2,
+ ADC2_IN3 = PC_2,
+ ADC3_IN3 = PC_2,
+
+ ADC1_IN16 = PB_1,
+ ADC2_IN16 = PB_1,
+
+ ADC1_IN1 = PC_2,
+ ADC2_IN1 = PC_2,
+ ADC3_IN1 = PC_2,
+
+ ADC1_IN11 = PA_6,
+ ADC2_IN11 = PA_6,
+
+ ADC1_IN13 = PC_4,
+ ADC2_IN13 = PC_4,
+
+ //ADC1_IN13 = PA_0,
+ //ADC2_IN13 = PA_0,
+
+ ADC1_IN8 = PA_3,
+ ADC2_IN8 = PA_3,
+
+ // Not connected
+ NC = (int) 0xFFFFFFFF
+} PinName;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l471xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,408 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler) + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_ARM_MICRO/stm32l471xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1
+ .ANY (+RW +ZI)
+ }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+ RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_ARM_STD/startup_stm32l471xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,390 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_ARM_STD/stm32l471xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1
+ .ANY (+RW +ZI)
+ }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+ RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_GCC_ARM/STM32L471XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,166 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
+ SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > SRAM1
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > SRAM1
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
+ __HeapLimit = .;
+ } > SRAM1
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+ /* Check if data + heap exceeds RAM1 limit */
+ ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM2
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+ /* Check if stack exceeds RAM2 limit */
+ ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_GCC_ARM/startup_stm32l471xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,513 @@ +/** + ****************************************************************************** + * @file startup_stm32l476xx.s + * @author MCD Application Team + * @version V1.1.1 + * @date 29-April-2016 + * @brief STM32L476xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM1_FLT3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word DFSDM1_FLT2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word LCD_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_IAR/startup_stm32l471xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,637 @@ +;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L476xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_IAR/stm32l471xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,37 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 96kb + 32kb = 0x20000] */
+/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x10000000;
+define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM2_start__ = 0x10000188;
+define symbol __region_SRAM2_end__ = 0x10007FFF;
+define symbol __region_SRAM1_start__ = 0x20000000;
+define symbol __region_SRAM1_end__ = 0x20017FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack 1K of SRAM2 and Heap 1/3 of SRAM1 */
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in SRAM1_region { readwrite, block HEAP };
+place in SRAM2_region { block CSTACK };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/cmsis.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/cmsis_nvic.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of SRAM2 + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l471xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,18388 @@
+/**
+ ******************************************************************************
+ * @file stm32l475xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral�s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32l475xx
+ * @{
+ */
+
+#ifndef __STM32L475xx_H
+#define __STM32L475xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
+ LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
+ LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
+ QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
+ SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
+ SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
+ TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
+ RNG_IRQn = 80, /*!< RNG global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x1C */
+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x2C */
+ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, 0x48 */
+ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
+ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef DMA_Request_TypeDef
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
+ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
+ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
+ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
+ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+ * @brief Firewall
+ */
+
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
+ __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
+ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
+ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
+ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
+ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
+ uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
+ __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+ __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
+ __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
+ __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+ __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
+
+} GPIO_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
+ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
+ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
+ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
+ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
+ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
+ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
+ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
+ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
+ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
+ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
+ __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
+ __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
+ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
+ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
+ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
+ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
+ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief Single Wire Protocol Master Interface SPWMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
+ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
+ uint32_t RESERVED1; /*!< Reserved, 0x08 */
+ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
+ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
+ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
+ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
+ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
+ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
+ __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
+ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
+} SYSCFG_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
+ __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief VREFBUF
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
+ __IO uint32_t GHWCFG1; /* User HW config1 044h*/
+ __IO uint32_t GHWCFG2; /* User HW config2 048h*/
+ __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
+ uint32_t Reserved6; /* Reserved 050h*/
+ __IO uint32_t GLPMCFG; /* LPM Register 054h*/
+ __IO uint32_t GPWRDN; /* Power Down Register 058h*/
+ __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
+ __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
+ uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
+#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
+#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
+#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
+#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
+#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1 FMC_BASE
+#define FMC_BANK1_1 FMC_BANK1
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3 (FMC_BASE + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
+
+#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
+#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0 DFSDM1_Channel0
+#define DFSDM_Channel1 DFSDM1_Channel1
+#define DFSDM_Channel2 DFSDM1_Channel2
+#define DFSDM_Channel3 DFSDM1_Channel3
+#define DFSDM_Channel4 DFSDM1_Channel4
+#define DFSDM_Channel5 DFSDM1_Channel5
+#define DFSDM_Channel6 DFSDM1_Channel6
+#define DFSDM_Channel7 DFSDM1_Channel7
+#define DFSDM_Filter0 DFSDM1_Filter0
+#define DFSDM_Filter1 DFSDM1_Filter1
+#define DFSDM_Filter2 DFSDM1_Filter2
+#define DFSDM_Filter3 DFSDM1_Filter3
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_ISR register *******************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
+
+/******************** Bit definition for ADC_IER register *******************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC (ADC_IER_EOCIE)
+#define ADC_IER_EOS (ADC_IER_EOSIE)
+#define ADC_IER_OVR (ADC_IER_OVRIE)
+#define ADC_IER_JEOC (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos (30U)
+#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+
+/******************** Bit definition for ADC_CFGR register ******************/
+#define ADC_CFGR_DMAEN_Pos (0U)
+#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos (1U)
+#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos (3U)
+#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
+#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos (5U)
+#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos (6U)
+#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos (10U)
+#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos (12U)
+#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos (13U)
+#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos (14U)
+#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos (16U)
+#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos (17U)
+#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos (20U)
+#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos (21U)
+#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos (22U)
+#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos (23U)
+#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos (24U)
+#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos (25U)
+#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos (26U)
+#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos (31U)
+#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
+
+/******************** Bit definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/******************** Bit definition for ADC_SMPR1 register *****************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_SMPR2 register *****************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for ADC_TR1 register *******************/
+#define ADC_TR1_LT1_Pos (0U)
+#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
+#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
+#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
+#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
+#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
+#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
+#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
+#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
+#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
+#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
+#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
+#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos (16U)
+#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
+#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
+#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
+#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
+#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
+#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
+#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
+#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
+#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
+#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
+#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
+#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_TR2 register *******************/
+#define ADC_TR2_LT2_Pos (0U)
+#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
+#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
+#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
+#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
+#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
+#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
+#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
+#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos (16U)
+#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
+#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
+#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
+#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
+#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
+#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
+#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
+#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_TR3 register *******************/
+#define ADC_TR3_LT3_Pos (0U)
+#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
+#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
+#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
+#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
+#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
+#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
+#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
+#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos (16U)
+#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
+#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
+#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
+#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
+#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
+#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
+#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
+#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_SQR1 register ******************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ******************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ******************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ******************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
+#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
+#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
+#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
+#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
+#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
+#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
+#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
+#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
+#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
+#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
+#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
+#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
+#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
+#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
+#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JSQR register ******************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos (6U)
+#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos (8U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos (14U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos (20U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos (26U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_OFR1 register ******************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos (31U)
+#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ******************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos (31U)
+#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ******************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos (31U)
+#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ******************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos (31U)
+#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR2 register ******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR3 register ******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR4 register ******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_AWD2CR register ****************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_AWD3CR register ****************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_DIFSEL register ****************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_CALFACT register ***************/
+#define ADC_CALFACT_CALFACT_S_Pos (0U)
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos (16U)
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CSR register *******************/
+#define ADC_CSR_ADRDY_MST_Pos (0U)
+#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos (1U)
+#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos (2U)
+#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos (3U)
+#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos (4U)
+#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos (5U)
+#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos (6U)
+#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos (7U)
+#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos (8U)
+#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos (9U)
+#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos (10U)
+#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos (16U)
+#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos (17U)
+#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos (18U)
+#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos (19U)
+#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos (20U)
+#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos (21U)
+#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos (22U)
+#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos (23U)
+#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos (24U)
+#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos (25U)
+#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos (26U)
+#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/******************** Bit definition for ADC_CCR register *******************/
+#define ADC_CCR_DUAL_Pos (0U)
+#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
+#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos (13U)
+#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
+#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos (14U)
+#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos (16U)
+#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
+
+/******************** Bit definition for ADC_CDR register *******************/
+#define ADC_CDR_RDATA_MST_Pos (0U)
+#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos (16U)
+#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN1_Pos (14U)
+#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN2_Pos (30U)
+#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos (14U)
+#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos (15U)
+#define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
+#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos (30U)
+#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos (31U)
+#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
+#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
+
+/******************* Bit definition for DAC_CCR register ********************/
+#define DAC_CCR_OTRIM1_Pos (0U)
+#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos (16U)
+#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
+
+/******************* Bit definition for DAC_MCR register *******************/
+#define DAC_MCR_MODE1_Pos (0U)
+#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
+#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos (16U)
+#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
+#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for DAC_SHSR1 register ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
+
+/****************** Bit definition for DAC_SHSR2 register ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
+
+/****************** Bit definition for DAC_SHHR register ******************/
+#define DAC_SHHR_THOLD1_Pos (0U)
+#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos (16U)
+#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
+
+/****************** Bit definition for DAC_SHRR register ******************/
+#define DAC_SHRR_TREFRESH1_Pos (0U)
+#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos (16U)
+#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos (0U)
+#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos (0U)
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos (29U)
+#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos (24U)
+#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos (18U)
+#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos (0U)
+#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos (8U)
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos (24U)
+#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos (16U)
+#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos (14U)
+#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos (13U)
+#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos (4U)
+#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos (3U)
+#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos (2U)
+#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos (1U)
+#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos (0U)
+#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
+#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos (29U)
+#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos (16U)
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos (0U)
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR1 register ******************/
+#define EXTI_IMR1_IM0_Pos (0U)
+#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos (1U)
+#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos (2U)
+#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos (3U)
+#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos (4U)
+#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos (5U)
+#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos (6U)
+#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos (7U)
+#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos (8U)
+#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos (9U)
+#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos (10U)
+#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos (11U)
+#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos (12U)
+#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos (13U)
+#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos (14U)
+#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos (15U)
+#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos (16U)
+#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos (17U)
+#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos (18U)
+#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos (19U)
+#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos (20U)
+#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos (21U)
+#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos (22U)
+#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos (23U)
+#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos (24U)
+#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos (25U)
+#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos (26U)
+#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos (27U)
+#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
+#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos (28U)
+#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos (29U)
+#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos (30U)
+#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos (31U)
+#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos (0U)
+#define EXTI_IMR1_IM_Msk (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR1 register ******************/
+#define EXTI_EMR1_EM0_Pos (0U)
+#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos (1U)
+#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos (2U)
+#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos (3U)
+#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos (4U)
+#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos (5U)
+#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos (6U)
+#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos (7U)
+#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos (8U)
+#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos (9U)
+#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos (10U)
+#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos (11U)
+#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos (12U)
+#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos (13U)
+#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos (14U)
+#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos (15U)
+#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos (16U)
+#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos (17U)
+#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos (18U)
+#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos (19U)
+#define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos (20U)
+#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos (21U)
+#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos (22U)
+#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos (23U)
+#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos (24U)
+#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos (25U)
+#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos (26U)
+#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos (27U)
+#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
+#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos (28U)
+#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos (29U)
+#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos (30U)
+#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
+#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos (31U)
+#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
+
+/****************** Bit definition for EXTI_RTSR1 register ******************/
+#define EXTI_RTSR1_RT0_Pos (0U)
+#define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos (1U)
+#define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos (2U)
+#define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos (3U)
+#define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos (4U)
+#define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos (5U)
+#define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos (6U)
+#define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos (7U)
+#define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos (8U)
+#define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos (9U)
+#define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos (10U)
+#define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos (11U)
+#define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos (12U)
+#define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos (13U)
+#define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos (14U)
+#define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos (15U)
+#define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos (16U)
+#define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos (18U)
+#define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos (19U)
+#define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos (20U)
+#define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos (21U)
+#define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos (22U)
+#define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR1 register ******************/
+#define EXTI_FTSR1_FT0_Pos (0U)
+#define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos (1U)
+#define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos (2U)
+#define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos (3U)
+#define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos (4U)
+#define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos (5U)
+#define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos (6U)
+#define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos (7U)
+#define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos (8U)
+#define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos (9U)
+#define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos (10U)
+#define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos (11U)
+#define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos (12U)
+#define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos (13U)
+#define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos (14U)
+#define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos (15U)
+#define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos (16U)
+#define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos (18U)
+#define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos (19U)
+#define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos (20U)
+#define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos (21U)
+#define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos (22U)
+#define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER1 register *****************/
+#define EXTI_SWIER1_SWI0_Pos (0U)
+#define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos (1U)
+#define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos (2U)
+#define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos (3U)
+#define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos (4U)
+#define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos (5U)
+#define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos (6U)
+#define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos (7U)
+#define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos (8U)
+#define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos (9U)
+#define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos (10U)
+#define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos (11U)
+#define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos (12U)
+#define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos (13U)
+#define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos (14U)
+#define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos (15U)
+#define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos (16U)
+#define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos (18U)
+#define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos (19U)
+#define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos (20U)
+#define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos (21U)
+#define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos (22U)
+#define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR1 register *******************/
+#define EXTI_PR1_PIF0_Pos (0U)
+#define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos (1U)
+#define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos (2U)
+#define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos (3U)
+#define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos (4U)
+#define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos (5U)
+#define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos (6U)
+#define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos (7U)
+#define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos (8U)
+#define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos (9U)
+#define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos (10U)
+#define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos (11U)
+#define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos (12U)
+#define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos (13U)
+#define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos (14U)
+#define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos (15U)
+#define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos (16U)
+#define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos (18U)
+#define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
+#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos (19U)
+#define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos (20U)
+#define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos (21U)
+#define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos (22U)
+#define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_IM32_Pos (0U)
+#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
+#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos (1U)
+#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
+#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos (2U)
+#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
+#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos (3U)
+#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
+#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos (4U)
+#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos (5U)
+#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos (6U)
+#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM_Pos (0U)
+#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
+#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
+
+/******************* Bit definition for EXTI_EMR2 register ******************/
+#define EXTI_EMR2_EM32_Pos (0U)
+#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
+#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos (1U)
+#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
+#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos (2U)
+#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
+#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos (3U)
+#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
+#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos (4U)
+#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
+#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos (5U)
+#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
+#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos (6U)
+#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
+#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM_Pos (0U)
+#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
+#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
+
+/****************** Bit definition for EXTI_RTSR2 register ******************/
+#define EXTI_RTSR2_RT35_Pos (3U)
+#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos (4U)
+#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos (5U)
+#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos (6U)
+#define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_FT35_Pos (3U)
+#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos (4U)
+#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos (5U)
+#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos (6U)
+#define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWI35_Pos (3U)
+#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos (4U)
+#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos (5U)
+#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos (6U)
+#define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PIF35_Pos (3U)
+#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
+#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos (4U)
+#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
+#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos (5U)
+#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
+#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos (6U)
+#define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
+#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_RUN_PD_Pos (13U)
+#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos (14U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_OPERR_Pos (1U)
+#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
+#define FLASH_SR_PROGERR_Pos (3U)
+#define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_SIZERR_Pos (6U)
+#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_MISERR_Pos (8U)
+#define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
+#define FLASH_SR_FASTERR_Pos (9U)
+#define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
+#define FLASH_SR_RDERR_Pos (14U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_OPTVERR_Pos (15U)
+#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk
+#define FLASH_CR_MER1_Pos (2U)
+#define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
+#define FLASH_CR_PNB_Pos (3U)
+#define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
+#define FLASH_CR_PNB FLASH_CR_PNB_Msk
+#define FLASH_CR_BKER_Pos (11U)
+#define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_CR_BKER FLASH_CR_BKER_Msk
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_OPTSTRT_Pos (17U)
+#define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
+#define FLASH_CR_FSTPG_Pos (18U)
+#define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_ERRIE_Pos (25U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
+#define FLASH_CR_RDERRIE_Pos (26U)
+#define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
+#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
+#define FLASH_CR_OPTLOCK_Pos (30U)
+#define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_ECCR register ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
+#define FLASH_ECCR_BK_ECC_Pos (19U)
+#define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
+#define FLASH_ECCR_SYSF_ECC_Pos (20U)
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
+#define FLASH_ECCR_ECCIE_Pos (24U)
+#define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
+#define FLASH_ECCR_ECCC_Pos (30U)
+#define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
+#define FLASH_ECCR_ECCD_Pos (31U)
+#define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
+
+/******************* Bits definition for FLASH_OPTR register ***************/
+#define FLASH_OPTR_RDP_Pos (0U)
+#define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
+#define FLASH_OPTR_BOR_LEV_Pos (8U)
+#define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
+#define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos (12U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
+#define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
+#define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
+#define FLASH_OPTR_BFB2_Pos (20U)
+#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
+#define FLASH_OPTR_DUALBANK_Pos (21U)
+#define FLASH_OPTR_DUALBANK_Msk (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
+#define FLASH_OPTR_nBOOT1_Pos (23U)
+#define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
+#define FLASH_OPTR_SRAM2_PE_Pos (24U)
+#define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
+#define FLASH_OPTR_SRAM2_RST_Pos (25U)
+#define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
+
+/****************** Bits definition for FLASH_PCROP1SR register **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
+
+/****************** Bits definition for FLASH_PCROP1ER register ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
+#define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
+#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
+#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
+
+/****************** Bits definition for FLASH_WRP1AR register ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
+#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
+
+/****************** Bits definition for FLASH_WRPB1R register ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
+#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
+
+/****************** Bits definition for FLASH_PCROP2SR register **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
+
+/****************** Bits definition for FLASH_PCROP2ER register ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
+#define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
+
+/****************** Bits definition for FLASH_WRP2AR register ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
+#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
+#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
+#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
+
+/****************** Bits definition for FLASH_WRP2BR register ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
+#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
+#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
+#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
+#define FMC_BCRx_MBKEN_Pos (0U)
+#define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos (1U)
+#define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCRx_MTYP_Pos (2U)
+#define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos (4U)
+#define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos (6U)
+#define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos (8U)
+#define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos (9U)
+#define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos (11U)
+#define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCRx_WREN_Pos (12U)
+#define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
+#define FMC_BCRx_WAITEN_Pos (13U)
+#define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos (14U)
+#define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCRx_CPSIZE_Pos (16U)
+#define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos (19U)
+#define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
+#define FMC_BTRx_ADDSET_Pos (0U)
+#define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos (4U)
+#define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos (8U)
+#define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos (16U)
+#define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos (20U)
+#define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos (24U)
+#define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos (28U)
+#define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
+#define FMC_BWTRx_ADDSET_Pos (0U)
+#define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos (4U)
+#define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos (8U)
+#define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos (16U)
+#define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos (28U)
+#define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FMC_PCR register ********************/
+#define FMC_PCR_PWAITEN_Pos (1U)
+#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos (2U)
+#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos (3U)
+#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR_PWID_Pos (4U)
+#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos (6U)
+#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR_Pos (9U)
+#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos (13U)
+#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos (17U)
+#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR register ********************/
+#define FMC_SR_IRS_Pos (0U)
+#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS_Pos (1U)
+#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR_IFS_Pos (2U)
+#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN_Pos (3U)
+#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN_Pos (4U)
+#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN_Pos (5U)
+#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos (6U)
+#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET_Pos (0U)
+#define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos (8U)
+#define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos (16U)
+#define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos (24U)
+#define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT register *******************/
+#define FMC_PATT_ATTSET_Pos (0U)
+#define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
+#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos (8U)
+#define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos (16U)
+#define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos (24U)
+#define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_ECCR register *******************/
+#define FMC_ECCR_ECC_Pos (0U)
+#define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0 GPIO_BRR_BR0
+#define GPIO_BRR_BR_1 GPIO_BRR_BR1
+#define GPIO_BRR_BR_2 GPIO_BRR_BR2
+#define GPIO_BRR_BR_3 GPIO_BRR_BR3
+#define GPIO_BRR_BR_4 GPIO_BRR_BR4
+#define GPIO_BRR_BR_5 GPIO_BRR_BR5
+#define GPIO_BRR_BR_6 GPIO_BRR_BR6
+#define GPIO_BRR_BR_7 GPIO_BRR_BR7
+#define GPIO_BRR_BR_8 GPIO_BRR_BR8
+#define GPIO_BRR_BR_9 GPIO_BRR_BR9
+#define GPIO_BRR_BR_10 GPIO_BRR_BR10
+#define GPIO_BRR_BR_11 GPIO_BRR_BR11
+#define GPIO_BRR_BR_12 GPIO_BRR_BR12
+#define GPIO_BRR_BR_13 GPIO_BRR_BR13
+#define GPIO_BRR_BR_14 GPIO_BRR_BR14
+#define GPIO_BRR_BR_15 GPIO_BRR_BR15
+
+
+/****************** Bits definition for GPIO_ASCR register *******************/
+#define GPIO_ASCR_ASC0_Pos (0U)
+#define GPIO_ASCR_ASC0_Msk (0x1U << GPIO_ASCR_ASC0_Pos) /*!< 0x00000001 */
+#define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
+#define GPIO_ASCR_ASC1_Pos (1U)
+#define GPIO_ASCR_ASC1_Msk (0x1U << GPIO_ASCR_ASC1_Pos) /*!< 0x00000002 */
+#define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
+#define GPIO_ASCR_ASC2_Pos (2U)
+#define GPIO_ASCR_ASC2_Msk (0x1U << GPIO_ASCR_ASC2_Pos) /*!< 0x00000004 */
+#define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
+#define GPIO_ASCR_ASC3_Pos (3U)
+#define GPIO_ASCR_ASC3_Msk (0x1U << GPIO_ASCR_ASC3_Pos) /*!< 0x00000008 */
+#define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
+#define GPIO_ASCR_ASC4_Pos (4U)
+#define GPIO_ASCR_ASC4_Msk (0x1U << GPIO_ASCR_ASC4_Pos) /*!< 0x00000010 */
+#define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
+#define GPIO_ASCR_ASC5_Pos (5U)
+#define GPIO_ASCR_ASC5_Msk (0x1U << GPIO_ASCR_ASC5_Pos) /*!< 0x00000020 */
+#define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
+#define GPIO_ASCR_ASC6_Pos (6U)
+#define GPIO_ASCR_ASC6_Msk (0x1U << GPIO_ASCR_ASC6_Pos) /*!< 0x00000040 */
+#define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
+#define GPIO_ASCR_ASC7_Pos (7U)
+#define GPIO_ASCR_ASC7_Msk (0x1U << GPIO_ASCR_ASC7_Pos) /*!< 0x00000080 */
+#define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
+#define GPIO_ASCR_ASC8_Pos (8U)
+#define GPIO_ASCR_ASC8_Msk (0x1U << GPIO_ASCR_ASC8_Pos) /*!< 0x00000100 */
+#define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
+#define GPIO_ASCR_ASC9_Pos (9U)
+#define GPIO_ASCR_ASC9_Msk (0x1U << GPIO_ASCR_ASC9_Pos) /*!< 0x00000200 */
+#define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
+#define GPIO_ASCR_ASC10_Pos (10U)
+#define GPIO_ASCR_ASC10_Msk (0x1U << GPIO_ASCR_ASC10_Pos) /*!< 0x00000400 */
+#define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
+#define GPIO_ASCR_ASC11_Pos (11U)
+#define GPIO_ASCR_ASC11_Msk (0x1U << GPIO_ASCR_ASC11_Pos) /*!< 0x00000800 */
+#define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
+#define GPIO_ASCR_ASC12_Pos (12U)
+#define GPIO_ASCR_ASC12_Msk (0x1U << GPIO_ASCR_ASC12_Pos) /*!< 0x00001000 */
+#define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
+#define GPIO_ASCR_ASC13_Pos (13U)
+#define GPIO_ASCR_ASC13_Msk (0x1U << GPIO_ASCR_ASC13_Pos) /*!< 0x00002000 */
+#define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
+#define GPIO_ASCR_ASC14_Pos (14U)
+#define GPIO_ASCR_ASC14_Msk (0x1U << GPIO_ASCR_ASC14_Pos) /*!< 0x00004000 */
+#define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
+#define GPIO_ASCR_ASC15_Pos (15U)
+#define GPIO_ASCR_ASC15_Msk (0x1U << GPIO_ASCR_ASC15_Pos) /*!< 0x00008000 */
+#define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
+
+/* Legacy defines */
+#define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
+#define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
+#define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
+#define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
+#define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
+#define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
+#define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
+#define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
+#define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
+#define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
+#define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
+#define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
+#define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
+#define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
+#define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
+#define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos (13U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR1 register ********************/
+
+#define PWR_CR1_LPR_Pos (14U)
+#define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
+#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos (9U)
+#define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
+#define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos (8U)
+#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos (0U)
+#define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
+#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos (0U)
+#define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos (1U)
+#define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos (0U)
+#define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
+#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
+
+
+/******************** Bit definition for PWR_CR2 register ********************/
+#define PWR_CR2_USV_Pos (10U)
+#define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
+#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos (9U)
+#define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
+#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos (4U)
+#define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
+#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos (7U)
+#define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
+#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos (6U)
+#define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
+#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos (5U)
+#define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
+#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos (4U)
+#define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
+#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos (1U)
+#define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
+#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos (1U)
+#define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos (2U)
+#define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos (1U)
+#define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos (3U)
+#define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos (1U)
+#define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos (2U)
+#define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos (1U)
+#define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos (0U)
+#define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
+#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+/******************** Bit definition for PWR_CR3 register ********************/
+#define PWR_CR3_EIWUL_Pos (15U)
+#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
+#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos (10U)
+#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
+#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos (8U)
+#define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
+#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos (4U)
+#define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
+#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos (3U)
+#define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
+#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos (2U)
+#define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
+#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos (1U)
+#define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
+#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos (0U)
+#define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
+#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos (0U)
+#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
+#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
+
+/* Legacy defines */
+#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
+#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
+#define PWR_CR3_EIWF PWR_CR3_EIWUL
+
+
+/******************** Bit definition for PWR_CR4 register ********************/
+#define PWR_CR4_VBRS_Pos (9U)
+#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
+#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos (8U)
+#define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
+#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
+#define PWR_CR4_WP5_Pos (4U)
+#define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
+#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos (3U)
+#define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
+#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos (2U)
+#define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
+#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos (1U)
+#define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
+#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos (0U)
+#define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
+#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
+
+/******************** Bit definition for PWR_SR1 register ********************/
+#define PWR_SR1_WUFI_Pos (15U)
+#define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
+#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos (8U)
+#define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
+#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos (0U)
+#define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
+#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos (4U)
+#define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
+#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos (3U)
+#define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
+#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos (2U)
+#define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
+#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos (1U)
+#define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
+#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos (0U)
+#define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
+#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
+
+/******************** Bit definition for PWR_SR2 register ********************/
+#define PWR_SR2_PVMO4_Pos (15U)
+#define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
+#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos (14U)
+#define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
+#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos (13U)
+#define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
+#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos (12U)
+#define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
+#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos (11U)
+#define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
+#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos (10U)
+#define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
+#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos (9U)
+#define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
+#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos (8U)
+#define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
+#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
+
+/******************** Bit definition for PWR_SCR register ********************/
+#define PWR_SCR_CSBF_Pos (8U)
+#define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
+#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos (0U)
+#define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
+#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
+#define PWR_SCR_CWUF5_Pos (4U)
+#define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
+#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos (3U)
+#define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
+#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos (2U)
+#define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
+#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos (1U)
+#define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
+#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos (0U)
+#define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
+#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
+
+/******************** Bit definition for PWR_PUCRA register ********************/
+#define PWR_PUCRA_PA15_Pos (15U)
+#define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos (13U)
+#define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos (12U)
+#define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos (11U)
+#define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos (10U)
+#define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos (9U)
+#define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
+#define PWR_PUCRA_PA8_Pos (8U)
+#define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
+#define PWR_PUCRA_PA7_Pos (7U)
+#define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
+#define PWR_PUCRA_PA6_Pos (6U)
+#define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
+#define PWR_PUCRA_PA5_Pos (5U)
+#define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
+#define PWR_PUCRA_PA4_Pos (4U)
+#define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
+#define PWR_PUCRA_PA3_Pos (3U)
+#define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
+#define PWR_PUCRA_PA2_Pos (2U)
+#define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
+#define PWR_PUCRA_PA1_Pos (1U)
+#define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
+#define PWR_PUCRA_PA0_Pos (0U)
+#define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRA register ********************/
+#define PWR_PDCRA_PA14_Pos (14U)
+#define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos (12U)
+#define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos (11U)
+#define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos (10U)
+#define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos (9U)
+#define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
+#define PWR_PDCRA_PA8_Pos (8U)
+#define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
+#define PWR_PDCRA_PA7_Pos (7U)
+#define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
+#define PWR_PDCRA_PA6_Pos (6U)
+#define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
+#define PWR_PDCRA_PA5_Pos (5U)
+#define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
+#define PWR_PDCRA_PA4_Pos (4U)
+#define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
+#define PWR_PDCRA_PA3_Pos (3U)
+#define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
+#define PWR_PDCRA_PA2_Pos (2U)
+#define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
+#define PWR_PDCRA_PA1_Pos (1U)
+#define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
+#define PWR_PDCRA_PA0_Pos (0U)
+#define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRB register ********************/
+#define PWR_PUCRB_PB15_Pos (15U)
+#define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos (14U)
+#define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos (13U)
+#define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos (12U)
+#define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos (11U)
+#define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos (10U)
+#define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos (9U)
+#define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
+#define PWR_PUCRB_PB8_Pos (8U)
+#define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
+#define PWR_PUCRB_PB7_Pos (7U)
+#define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
+#define PWR_PUCRB_PB6_Pos (6U)
+#define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
+#define PWR_PUCRB_PB5_Pos (5U)
+#define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
+#define PWR_PUCRB_PB4_Pos (4U)
+#define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
+#define PWR_PUCRB_PB3_Pos (3U)
+#define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
+#define PWR_PUCRB_PB2_Pos (2U)
+#define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
+#define PWR_PUCRB_PB1_Pos (1U)
+#define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
+#define PWR_PUCRB_PB0_Pos (0U)
+#define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRB register ********************/
+#define PWR_PDCRB_PB15_Pos (15U)
+#define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos (14U)
+#define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos (13U)
+#define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos (12U)
+#define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos (11U)
+#define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos (10U)
+#define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos (9U)
+#define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
+#define PWR_PDCRB_PB8_Pos (8U)
+#define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
+#define PWR_PDCRB_PB7_Pos (7U)
+#define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
+#define PWR_PDCRB_PB6_Pos (6U)
+#define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
+#define PWR_PDCRB_PB5_Pos (5U)
+#define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
+#define PWR_PDCRB_PB3_Pos (3U)
+#define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
+#define PWR_PDCRB_PB2_Pos (2U)
+#define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
+#define PWR_PDCRB_PB1_Pos (1U)
+#define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
+#define PWR_PDCRB_PB0_Pos (0U)
+#define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRC register ********************/
+#define PWR_PUCRC_PC15_Pos (15U)
+#define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos (14U)
+#define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos (13U)
+#define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos (12U)
+#define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos (11U)
+#define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos (10U)
+#define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos (9U)
+#define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
+#define PWR_PUCRC_PC8_Pos (8U)
+#define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
+#define PWR_PUCRC_PC7_Pos (7U)
+#define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
+#define PWR_PUCRC_PC6_Pos (6U)
+#define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
+#define PWR_PUCRC_PC5_Pos (5U)
+#define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
+#define PWR_PUCRC_PC4_Pos (4U)
+#define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
+#define PWR_PUCRC_PC3_Pos (3U)
+#define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
+#define PWR_PUCRC_PC2_Pos (2U)
+#define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
+#define PWR_PUCRC_PC1_Pos (1U)
+#define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
+#define PWR_PUCRC_PC0_Pos (0U)
+#define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRC register ********************/
+#define PWR_PDCRC_PC15_Pos (15U)
+#define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos (14U)
+#define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos (13U)
+#define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos (12U)
+#define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos (11U)
+#define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos (10U)
+#define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos (9U)
+#define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
+#define PWR_PDCRC_PC8_Pos (8U)
+#define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
+#define PWR_PDCRC_PC7_Pos (7U)
+#define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
+#define PWR_PDCRC_PC6_Pos (6U)
+#define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
+#define PWR_PDCRC_PC5_Pos (5U)
+#define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
+#define PWR_PDCRC_PC4_Pos (4U)
+#define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
+#define PWR_PDCRC_PC3_Pos (3U)
+#define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
+#define PWR_PDCRC_PC2_Pos (2U)
+#define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
+#define PWR_PDCRC_PC1_Pos (1U)
+#define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
+#define PWR_PDCRC_PC0_Pos (0U)
+#define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRD register ********************/
+#define PWR_PUCRD_PD15_Pos (15U)
+#define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos (14U)
+#define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos (13U)
+#define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos (12U)
+#define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos (11U)
+#define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos (10U)
+#define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos (9U)
+#define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
+#define PWR_PUCRD_PD8_Pos (8U)
+#define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
+#define PWR_PUCRD_PD7_Pos (7U)
+#define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
+#define PWR_PUCRD_PD6_Pos (6U)
+#define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
+#define PWR_PUCRD_PD5_Pos (5U)
+#define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
+#define PWR_PUCRD_PD4_Pos (4U)
+#define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
+#define PWR_PUCRD_PD3_Pos (3U)
+#define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
+#define PWR_PUCRD_PD2_Pos (2U)
+#define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
+#define PWR_PUCRD_PD1_Pos (1U)
+#define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
+#define PWR_PUCRD_PD0_Pos (0U)
+#define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRD register ********************/
+#define PWR_PDCRD_PD15_Pos (15U)
+#define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos (14U)
+#define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos (13U)
+#define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos (12U)
+#define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos (11U)
+#define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos (10U)
+#define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos (9U)
+#define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
+#define PWR_PDCRD_PD8_Pos (8U)
+#define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
+#define PWR_PDCRD_PD7_Pos (7U)
+#define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
+#define PWR_PDCRD_PD6_Pos (6U)
+#define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
+#define PWR_PDCRD_PD5_Pos (5U)
+#define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
+#define PWR_PDCRD_PD4_Pos (4U)
+#define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
+#define PWR_PDCRD_PD3_Pos (3U)
+#define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
+#define PWR_PDCRD_PD2_Pos (2U)
+#define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
+#define PWR_PDCRD_PD1_Pos (1U)
+#define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
+#define PWR_PDCRD_PD0_Pos (0U)
+#define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRE register ********************/
+#define PWR_PUCRE_PE15_Pos (15U)
+#define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos (14U)
+#define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos (13U)
+#define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos (12U)
+#define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos (11U)
+#define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos (10U)
+#define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos (9U)
+#define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
+#define PWR_PUCRE_PE8_Pos (8U)
+#define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
+#define PWR_PUCRE_PE7_Pos (7U)
+#define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
+#define PWR_PUCRE_PE6_Pos (6U)
+#define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
+#define PWR_PUCRE_PE5_Pos (5U)
+#define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
+#define PWR_PUCRE_PE4_Pos (4U)
+#define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
+#define PWR_PUCRE_PE3_Pos (3U)
+#define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
+#define PWR_PUCRE_PE2_Pos (2U)
+#define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
+#define PWR_PUCRE_PE1_Pos (1U)
+#define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
+#define PWR_PUCRE_PE0_Pos (0U)
+#define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRE register ********************/
+#define PWR_PDCRE_PE15_Pos (15U)
+#define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos (14U)
+#define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos (13U)
+#define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos (12U)
+#define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos (11U)
+#define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos (10U)
+#define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos (9U)
+#define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
+#define PWR_PDCRE_PE8_Pos (8U)
+#define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
+#define PWR_PDCRE_PE7_Pos (7U)
+#define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
+#define PWR_PDCRE_PE6_Pos (6U)
+#define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
+#define PWR_PDCRE_PE5_Pos (5U)
+#define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
+#define PWR_PDCRE_PE4_Pos (4U)
+#define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
+#define PWR_PDCRE_PE3_Pos (3U)
+#define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
+#define PWR_PDCRE_PE2_Pos (2U)
+#define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
+#define PWR_PDCRE_PE1_Pos (1U)
+#define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
+#define PWR_PDCRE_PE0_Pos (0U)
+#define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRF register ********************/
+#define PWR_PUCRF_PF15_Pos (15U)
+#define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos (14U)
+#define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos (13U)
+#define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos (12U)
+#define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos (11U)
+#define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos (10U)
+#define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos (9U)
+#define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
+#define PWR_PUCRF_PF8_Pos (8U)
+#define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
+#define PWR_PUCRF_PF7_Pos (7U)
+#define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
+#define PWR_PUCRF_PF6_Pos (6U)
+#define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
+#define PWR_PUCRF_PF5_Pos (5U)
+#define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
+#define PWR_PUCRF_PF4_Pos (4U)
+#define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
+#define PWR_PUCRF_PF3_Pos (3U)
+#define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
+#define PWR_PUCRF_PF2_Pos (2U)
+#define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
+#define PWR_PUCRF_PF1_Pos (1U)
+#define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
+#define PWR_PUCRF_PF0_Pos (0U)
+#define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRF register ********************/
+#define PWR_PDCRF_PF15_Pos (15U)
+#define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos (14U)
+#define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos (13U)
+#define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos (12U)
+#define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos (11U)
+#define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos (10U)
+#define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos (9U)
+#define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
+#define PWR_PDCRF_PF8_Pos (8U)
+#define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
+#define PWR_PDCRF_PF7_Pos (7U)
+#define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
+#define PWR_PDCRF_PF6_Pos (6U)
+#define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
+#define PWR_PDCRF_PF5_Pos (5U)
+#define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
+#define PWR_PDCRF_PF4_Pos (4U)
+#define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
+#define PWR_PDCRF_PF3_Pos (3U)
+#define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
+#define PWR_PDCRF_PF2_Pos (2U)
+#define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
+#define PWR_PDCRF_PF1_Pos (1U)
+#define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
+#define PWR_PDCRF_PF0_Pos (0U)
+#define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRG register ********************/
+#define PWR_PUCRG_PG15_Pos (15U)
+#define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos (14U)
+#define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos (13U)
+#define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos (12U)
+#define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos (11U)
+#define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos (10U)
+#define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos (9U)
+#define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
+#define PWR_PUCRG_PG8_Pos (8U)
+#define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
+#define PWR_PUCRG_PG7_Pos (7U)
+#define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
+#define PWR_PUCRG_PG6_Pos (6U)
+#define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
+#define PWR_PUCRG_PG5_Pos (5U)
+#define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
+#define PWR_PUCRG_PG4_Pos (4U)
+#define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
+#define PWR_PUCRG_PG3_Pos (3U)
+#define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
+#define PWR_PUCRG_PG2_Pos (2U)
+#define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
+#define PWR_PUCRG_PG1_Pos (1U)
+#define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
+#define PWR_PUCRG_PG0_Pos (0U)
+#define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRG register ********************/
+#define PWR_PDCRG_PG15_Pos (15U)
+#define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos (14U)
+#define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos (13U)
+#define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos (12U)
+#define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos (11U)
+#define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos (10U)
+#define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos (9U)
+#define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
+#define PWR_PDCRG_PG8_Pos (8U)
+#define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
+#define PWR_PDCRG_PG7_Pos (7U)
+#define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
+#define PWR_PDCRG_PG6_Pos (6U)
+#define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
+#define PWR_PDCRG_PG5_Pos (5U)
+#define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
+#define PWR_PDCRG_PG4_Pos (4U)
+#define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
+#define PWR_PDCRG_PG3_Pos (3U)
+#define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
+#define PWR_PDCRG_PG2_Pos (2U)
+#define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
+#define PWR_PDCRG_PG1_Pos (1U)
+#define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
+#define PWR_PDCRG_PG0_Pos (0U)
+#define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRH register ********************/
+#define PWR_PUCRH_PH1_Pos (1U)
+#define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
+#define PWR_PUCRH_PH0_Pos (0U)
+#define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRH register ********************/
+#define PWR_PDCRH_PH1_Pos (1U)
+#define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
+#define PWR_PDCRH_PH0_Pos (0U)
+#define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_PLLSAI2_SUPPORT
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_MSION_Pos (0U)
+#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos (1U)
+#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos (2U)
+#define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos (3U)
+#define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos (4U)
+#define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos (8U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos (9U)
+#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (10U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos (11U)
+#define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos (26U)
+#define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos (27U)
+#define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos (28U)
+#define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos (29U)
+#define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
+
+/******************** Bit definition for RCC_ICSCR register ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos (0U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos (8U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos (16U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos (24U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos (4U)
+#define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos (8U)
+#define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos (16U)
+#define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
+#define RCC_PLLCFGR_PLLP_Pos (17U)
+#define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLQEN_Pos (20U)
+#define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
+
+#define RCC_PLLCFGR_PLLQ_Pos (21U)
+#define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos (24U)
+#define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
+#define RCC_PLLCFGR_PLLR_Pos (25U)
+#define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for RCC_CIER register ******************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_MSIRDYIE_Pos (2U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos (3U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos (4U)
+#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_PLLRDYIE_Pos (5U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
+#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
+#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
+#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
+#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos (9U)
+#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
+
+/******************** Bit definition for RCC_CIFR register ******************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_MSIRDYF_Pos (2U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos (3U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos (4U)
+#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos (5U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
+#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
+#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
+#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
+#define RCC_CIFR_CSSF_Pos (8U)
+#define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
+#define RCC_CIFR_LSECSSF_Pos (9U)
+#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
+
+/******************** Bit definition for RCC_CICR register ******************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_MSIRDYC_Pos (2U)
+#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos (3U)
+#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos (4U)
+#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos (5U)
+#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
+#define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
+#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
+#define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
+#define RCC_CICR_CSSC_Pos (8U)
+#define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
+#define RCC_CICR_LSECSSC_Pos (9U)
+#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
+#define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_TSCRST_Pos (16U)
+#define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
+#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
+#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
+#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
+#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
+#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
+#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
+#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+#define RCC_AHB2RSTR_ADCRST_Pos (13U)
+#define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos (18U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
+
+/******************** Bit definition for RCC_APB1RSTR1 register **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
+#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
+#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
+#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
+#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
+#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
+#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
+#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
+#define RCC_APB1RSTR1_USART2RST_Pos (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
+#define RCC_APB1RSTR1_USART3RST_Pos (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
+#define RCC_APB1RSTR1_UART4RST_Pos (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
+#define RCC_APB1RSTR1_UART5RST_Pos (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
+#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
+#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
+#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
+#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
+#define RCC_APB1RSTR1_PWRRST_Pos (28U)
+#define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
+#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
+#define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
+#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
+#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
+#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
+
+/******************** Bit definition for RCC_APB1RSTR2 register **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
+#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
+#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
+#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
+#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
+#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
+#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (13U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_FLASHEN_Pos (8U)
+#define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_TSCEN_Pos (16U)
+#define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
+#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
+#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
+#define RCC_AHB2ENR_GPIODEN_Pos (3U)
+#define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
+#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
+#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
+#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
+#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+#define RCC_AHB2ENR_ADCEN_Pos (13U)
+#define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (18U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos (8U)
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
+
+/******************** Bit definition for RCC_APB1ENR1 register ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
+#define RCC_APB1ENR1_TIM3EN_Pos (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
+#define RCC_APB1ENR1_TIM4EN_Pos (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
+#define RCC_APB1ENR1_TIM5EN_Pos (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
+#define RCC_APB1ENR1_TIM6EN_Pos (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
+#define RCC_APB1ENR1_TIM7EN_Pos (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
+#define RCC_APB1ENR1_WWDGEN_Pos (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
+#define RCC_APB1ENR1_SPI2EN_Pos (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
+#define RCC_APB1ENR1_SPI3EN_Pos (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
+#define RCC_APB1ENR1_USART2EN_Pos (17U)
+#define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
+#define RCC_APB1ENR1_USART3EN_Pos (18U)
+#define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
+#define RCC_APB1ENR1_UART4EN_Pos (19U)
+#define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
+#define RCC_APB1ENR1_UART5EN_Pos (20U)
+#define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
+#define RCC_APB1ENR1_I2C1EN_Pos (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
+#define RCC_APB1ENR1_I2C2EN_Pos (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
+#define RCC_APB1ENR1_I2C3EN_Pos (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
+#define RCC_APB1ENR1_CAN1EN_Pos (25U)
+#define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
+#define RCC_APB1ENR1_PWREN_Pos (28U)
+#define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
+#define RCC_APB1ENR1_DAC1EN_Pos (29U)
+#define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
+#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
+#define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
+#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
+
+/******************** Bit definition for RCC_APB1RSTR2 register **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
+#define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
+#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
+#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
+#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
+#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
+#define RCC_APB2ENR_SDMMC1EN_Pos (10U)
+#define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (13U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos (16U)
+#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos (17U)
+#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos (18U)
+#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (21U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos (22U)
+#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
+
+/******************** Bit definition for RCC_AHB1SMENR register ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
+#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
+#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
+#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
+#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
+#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
+#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
+#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
+#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
+#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
+
+/******************** Bit definition for RCC_AHB2SMENR register *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
+#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
+#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
+#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
+#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
+#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
+#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
+#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
+#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
+#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
+
+/******************** Bit definition for RCC_AHB3SMENR register *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
+#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
+#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
+#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
+
+/******************** Bit definition for RCC_APB1SMENR1 register *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
+#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
+#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
+#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
+#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
+#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
+#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
+#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
+#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
+#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
+#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
+#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
+#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
+#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
+#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
+#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
+#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
+#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
+#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
+#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
+#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
+#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
+#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
+#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
+#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
+#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
+#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
+#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
+#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
+#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
+
+/******************** Bit definition for RCC_APB1SMENR2 register *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
+
+/******************** Bit definition for RCC_APB2SMENR register *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
+#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
+#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
+#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
+#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
+#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
+#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
+#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
+#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
+#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
+#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
+#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
+#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
+#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
+#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
+
+/******************** Bit definition for RCC_CCIPR register ******************/
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
+#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
+#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos (4U)
+#define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
+#define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos (6U)
+#define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
+#define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos (8U)
+#define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
+#define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
+#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
+#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos (14U)
+#define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
+#define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos (16U)
+#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
+#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
+#define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
+#define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos (22U)
+#define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
+#define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos (24U)
+#define RCC_CCIPR_SAI2SEL_Msk (0x3U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
+#define RCC_CCIPR_SAI2SEL_0 (0x1U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1 (0x2U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos (26U)
+#define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
+#define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos (28U)
+#define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
+#define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
+#define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
+
+#define RCC_CCIPR_DFSDM1SEL_Pos (31U)
+#define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos (3U)
+#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos (5U)
+#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos (6U)
+#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+#define RCC_BDCR_LSCOEN_Pos (24U)
+#define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
+#define RCC_BDCR_LSCOSEL_Pos (25U)
+#define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+
+#define RCC_CSR_MSISRANGE_Pos (8U)
+#define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
+#define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_BORRSTF_Pos (27U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_ITSE_Pos (24U)
+#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_ITSF_Pos (17U)
+#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAMPCR register ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_0R register *******************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
+
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Bits definition for RTC_BKP20R register ***************/
+#define RTC_BKP20R_Pos (0U)
+#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP20R RTC_BKP20R_Msk
+
+/******************** Bits definition for RTC_BKP21R register ***************/
+#define RTC_BKP21R_Pos (0U)
+#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP21R RTC_BKP21R_Msk
+
+/******************** Bits definition for RTC_BKP22R register ***************/
+#define RTC_BKP22R_Pos (0U)
+#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP22R RTC_BKP22R_Msk
+
+/******************** Bits definition for RTC_BKP23R register ***************/
+#define RTC_BKP23R_Pos (0U)
+#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP23R RTC_BKP23R_Msk
+
+/******************** Bits definition for RTC_BKP24R register ***************/
+#define RTC_BKP24R_Pos (0U)
+#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP24R RTC_BKP24R_Msk
+
+/******************** Bits definition for RTC_BKP25R register ***************/
+#define RTC_BKP25R_Pos (0U)
+#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP25R RTC_BKP25R_Msk
+
+/******************** Bits definition for RTC_BKP26R register ***************/
+#define RTC_BKP26R_Pos (0U)
+#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP26R RTC_BKP26R_Msk
+
+/******************** Bits definition for RTC_BKP27R register ***************/
+#define RTC_BKP27R_Pos (0U)
+#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP27R RTC_BKP27R_Msk
+
+/******************** Bits definition for RTC_BKP28R register ***************/
+#define RTC_BKP28R_Pos (0U)
+#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP28R RTC_BKP28R_Msk
+
+/******************** Bits definition for RTC_BKP29R register ***************/
+#define RTC_BKP29R_Pos (0U)
+#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP29R RTC_BKP29R_Msk
+
+/******************** Bits definition for RTC_BKP30R register ***************/
+#define RTC_BKP30R_Pos (0U)
+#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP30R RTC_BKP30R_Msk
+
+/******************** Bits definition for RTC_BKP31R register ***************/
+#define RTC_BKP31R_Pos (0U)
+#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP31R RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 32U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+/******************************************************************************/
+/* */
+/* SDMMC Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDMMC_POWER register ******************/
+#define SDMMC_POWER_PWRCTRL_Pos (0U)
+#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
+
+/****************** Bit definition for SDMMC_CLKCR register ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDMMC_CLKCR_CLKEN_Pos (8U)
+#define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
+#define SDMMC_CLKCR_PWRSAV_Pos (9U)
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+#define SDMMC_CLKCR_BYPASS_Pos (10U)
+#define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos (11U)
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDMMC_ARG register *******************/
+#define SDMMC_ARG_CMDARG_Pos (0U)
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDMMC_CMD register *******************/
+#define SDMMC_CMD_CMDINDEX_Pos (0U)
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
+
+#define SDMMC_CMD_WAITRESP_Pos (6U)
+#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos (8U)
+#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDMMC_CMD_WAITPEND_Pos (9U)
+#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos (10U)
+#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
+#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDMMC_RESPCMD register *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDMMC_RESP1 register ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP2 register ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP3 register ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP4 register ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_DTIMER register *****************/
+#define SDMMC_DTIMER_DATATIME_Pos (0U)
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDMMC_DLEN register *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDMMC_DCTRL register ******************/
+#define SDMMC_DCTRL_DTEN_Pos (0U)
+#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDMMC_DCTRL_DTDIR_Pos (1U)
+#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos (2U)
+#define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDMMC_DCTRL_DMAEN_Pos (3U)
+#define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos (8U)
+#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDMMC_DCTRL_RWSTOP_Pos (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDMMC_DCTRL_RWMOD_Pos (10U)
+#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDMMC_DCTRL_SDIOEN_Pos (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDMMC_DCOUNT register *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDMMC_STA register ********************/
+#define SDMMC_STA_CCRCFAIL_Pos (0U)
+#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDMMC_STA_DCRCFAIL_Pos (1U)
+#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDMMC_STA_CTIMEOUT_Pos (2U)
+#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDMMC_STA_DTIMEOUT_Pos (3U)
+#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDMMC_STA_TXUNDERR_Pos (4U)
+#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDMMC_STA_RXOVERR_Pos (5U)
+#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDMMC_STA_CMDREND_Pos (6U)
+#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDMMC_STA_CMDSENT_Pos (7U)
+#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDMMC_STA_DATAEND_Pos (8U)
+#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDMMC_STA_STBITERR_Pos (9U)
+#define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos (10U)
+#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDMMC_STA_CMDACT_Pos (11U)
+#define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
+#define SDMMC_STA_TXACT_Pos (12U)
+#define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
+#define SDMMC_STA_RXACT_Pos (13U)
+#define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
+#define SDMMC_STA_TXFIFOHE_Pos (14U)
+#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos (15U)
+#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos (16U)
+#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDMMC_STA_RXFIFOF_Pos (17U)
+#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDMMC_STA_TXFIFOE_Pos (18U)
+#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDMMC_STA_RXFIFOE_Pos (19U)
+#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDMMC_STA_TXDAVL_Pos (20U)
+#define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
+#define SDMMC_STA_RXDAVL_Pos (21U)
+#define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
+#define SDMMC_STA_SDIOIT_Pos (22U)
+#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDMMC_ICR register *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos (5U)
+#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDMMC_ICR_CMDRENDC_Pos (6U)
+#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDMMC_ICR_CMDSENTC_Pos (7U)
+#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDMMC_ICR_DATAENDC_Pos (8U)
+#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDMMC_ICR_STBITERRC_Pos (9U)
+#define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos (10U)
+#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDMMC_ICR_SDIOITC_Pos (22U)
+#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDMMC_MASK register *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDMMC_MASK_RXOVERRIE_Pos (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDMMC_MASK_CMDRENDIE_Pos (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDMMC_MASK_DATAENDIE_Pos (8U)
+#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDMMC_MASK_DBCKENDIE_Pos (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDMMC_MASK_CMDACTIE_Pos (11U)
+#define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
+#define SDMMC_MASK_TXACTIE_Pos (12U)
+#define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
+#define SDMMC_MASK_RXACTIE_Pos (13U)
+#define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
+#define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
+#define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
+#define SDMMC_MASK_TXDAVLIE_Pos (20U)
+#define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos (21U)
+#define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos (22U)
+#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDMMC_FIFO register *******************/
+#define SDMMC_FIFO_FIFODATA_Pos (0U)
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_CRCL_Pos (11U)
+#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos (3U)
+#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos (8U)
+#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
+#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
+#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
+#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos (12U)
+#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos (13U)
+#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos (14U)
+#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos (9U)
+#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos (11U)
+#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
+
+/****************** Bit definition for SYSCFG_CFGR1 register ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos (0U)
+#define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
+#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
+#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
+#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
+#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
+
+/****************** Bit definition for SYSCFG_SCSR register ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
+#define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
+#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
+
+/****************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_CLL_Pos (0U)
+#define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos (1U)
+#define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos (2U)
+#define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos (3U)
+#define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos (8U)
+#define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
+
+/****************** Bit definition for SYSCFG_SWPR register ****************/
+#define SYSCFG_SWPR_PAGE0_Pos (0U)
+#define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos (1U)
+#define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos (2U)
+#define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos (3U)
+#define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos (4U)
+#define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos (5U)
+#define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos (6U)
+#define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos (7U)
+#define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos (8U)
+#define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos (9U)
+#define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos (10U)
+#define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos (11U)
+#define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos (12U)
+#define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos (13U)
+#define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos (14U)
+#define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos (15U)
+#define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos (16U)
+#define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos (17U)
+#define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos (18U)
+#define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos (19U)
+#define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos (20U)
+#define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos (21U)
+#define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos (22U)
+#define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos (23U)
+#define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos (24U)
+#define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos (25U)
+#define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos (26U)
+#define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos (27U)
+#define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos (28U)
+#define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos (29U)
+#define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos (30U)
+#define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos (31U)
+#define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
+
+/****************** Bit definition for SYSCFG_SKR register ****************/
+#define SYSCFG_SKR_KEY_Pos (0U)
+#define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
+
+
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos (11U)
+#define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos (16U)
+#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos (18U)
+#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos (20U)
+#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos (8U)
+#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos (13U)
+#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos (16U)
+#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos (17U)
+#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
+
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+#define TIM_EGR_B2G_Pos (8U)
+#define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
+
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE_Pos (2U)
+#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos (3U)
+#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos (4U)
+#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos (7U)
+#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos (10U)
+#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos (11U)
+#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos (12U)
+#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos (15U)
+#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos (16U)
+#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos (17U)
+#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos (20U)
+#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos (21U)
+#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos (31U)
+#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5_Pos (0U)
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos (29U)
+#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos (30U)
+#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos (31U)
+#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6_Pos (0U)
+#define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos (16U)
+#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos (20U)
+#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos (24U)
+#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos (25U)
+#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM1_OR1 register *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
+#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
+#define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0 (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1 (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos (4U)
+#define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
+
+/******************* Bit definition for TIM1_OR2 register *******************/
+#define TIM1_OR2_BKINE_Pos (0U)
+#define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos (1U)
+#define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos (2U)
+#define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos (8U)
+#define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos (9U)
+#define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos (10U)
+#define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos (11U)
+#define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos (14U)
+#define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM1_OR3 register *******************/
+#define TIM1_OR3_BK2INE_Pos (0U)
+#define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos (1U)
+#define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos (2U)
+#define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
+#define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos (9U)
+#define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos (10U)
+#define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos (11U)
+#define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
+
+/******************* Bit definition for TIM8_OR1 register *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
+#define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0 (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1 (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
+#define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0 (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1 (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos (4U)
+#define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
+
+/******************* Bit definition for TIM8_OR2 register *******************/
+#define TIM8_OR2_BKINE_Pos (0U)
+#define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos (1U)
+#define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos (2U)
+#define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos (8U)
+#define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos (9U)
+#define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos (10U)
+#define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos (11U)
+#define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos (14U)
+#define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM8_OR3 register *******************/
+#define TIM8_OR3_BK2INE_Pos (0U)
+#define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos (1U)
+#define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos (2U)
+#define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
+#define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos (9U)
+#define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos (10U)
+#define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos (11U)
+#define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
+
+/******************* Bit definition for TIM2_OR1 register *******************/
+#define TIM2_OR1_ITR1_RMP_Pos (0U)
+#define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos (1U)
+#define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos (2U)
+#define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
+
+/******************* Bit definition for TIM2_OR2 register *******************/
+#define TIM2_OR2_ETRSEL_Pos (14U)
+#define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM3_OR1 register *******************/
+#define TIM3_OR1_TI1_RMP_Pos (0U)
+#define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM3_OR2 register *******************/
+#define TIM3_OR2_ETRSEL_Pos (14U)
+#define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM15_OR1 register ******************/
+#define TIM15_OR1_TI1_RMP_Pos (0U)
+#define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos (1U)
+#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for TIM15_OR2 register ******************/
+#define TIM15_OR2_BKINE_Pos (0U)
+#define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos (1U)
+#define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos (2U)
+#define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos (8U)
+#define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos (9U)
+#define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos (10U)
+#define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos (11U)
+#define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************* Bit definition for TIM16_OR1 register ******************/
+#define TIM16_OR1_TI1_RMP_Pos (0U)
+#define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM16_OR2 register ******************/
+#define TIM16_OR2_BKINE_Pos (0U)
+#define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos (1U)
+#define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos (2U)
+#define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos (8U)
+#define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos (9U)
+#define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos (10U)
+#define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos (11U)
+#define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************* Bit definition for TIM17_OR1 register ******************/
+#define TIM17_OR1_TI1_RMP_Pos (0U)
+#define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM17_OR2 register ******************/
+#define TIM17_OR2_BKINE_Pos (0U)
+#define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos (1U)
+#define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos (2U)
+#define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos (8U)
+#define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos (9U)
+#define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos (10U)
+#define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos (11U)
+#define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register ********************/
+#define LPTIM_OR_OR_Pos (0U)
+#define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
+#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
+#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_EN_Pos (0U)
+#define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos (2U)
+#define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos (4U)
+#define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos (7U)
+#define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
+#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos (9U)
+#define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
+#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+#define COMP_CSR_POLARITY_Pos (15U)
+#define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos (16U)
+#define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
+#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
+#define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos (18U)
+#define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos (22U)
+#define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
+#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos (23U)
+#define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
+#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos (30U)
+#define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos (31U)
+#define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos (1U)
+#define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos (2U)
+#define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos (4U)
+#define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos (8U)
+#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos (10U)
+#define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos (12U)
+#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos (13U)
+#define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos (14U)
+#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos (15U)
+#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
+
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAEN_Pos (0U)
+#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos (1U)
+#define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos (2U)
+#define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos (4U)
+#define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos (8U)
+#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos (10U)
+#define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos (12U)
+#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos (13U)
+#define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos (14U)
+#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos (15U)
+#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos (31U)
+#define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAEN_Pos (0U)
+#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos (1U)
+#define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos (2U)
+#define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos (4U)
+#define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos (8U)
+#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos (10U)
+#define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos (12U)
+#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos (13U)
+#define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos (14U)
+#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos (15U)
+#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
+
+/******************* Bit definition for OPAMP_OTR register ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_OTR register ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_OTR register ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP_LPOTR register ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_LPOTR register ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_LPOTR register ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+/* MBED */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+/* MBED */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos (2U)
+#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Legacy defines */
+#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
+#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
+#define USART_ICR_NCF USART_ICR_NECF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Single Wire Protocol Master Interface (SWPMI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SWPMI_CR register ********************/
+#define SWPMI_CR_RXDMA_Pos (0U)
+#define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
+#define SWPMI_CR_TXDMA_Pos (1U)
+#define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
+#define SWPMI_CR_RXMODE_Pos (2U)
+#define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
+#define SWPMI_CR_TXMODE_Pos (3U)
+#define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
+#define SWPMI_CR_LPBK_Pos (4U)
+#define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
+#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
+#define SWPMI_CR_SWPACT_Pos (5U)
+#define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
+#define SWPMI_CR_DEACT_Pos (10U)
+#define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
+#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
+
+/******************* Bit definition for SWPMI_BRR register ********************/
+#define SWPMI_BRR_BR_Pos (0U)
+#define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
+#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/******************* Bit definition for SWPMI_ISR register ********************/
+#define SWPMI_ISR_RXBFF_Pos (0U)
+#define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
+#define SWPMI_ISR_TXBEF_Pos (1U)
+#define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
+#define SWPMI_ISR_RXBERF_Pos (2U)
+#define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
+#define SWPMI_ISR_RXOVRF_Pos (3U)
+#define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
+#define SWPMI_ISR_TXUNRF_Pos (4U)
+#define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
+#define SWPMI_ISR_RXNE_Pos (5U)
+#define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos (6U)
+#define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
+#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
+#define SWPMI_ISR_TCF_Pos (7U)
+#define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
+#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
+#define SWPMI_ISR_SRF_Pos (8U)
+#define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
+#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
+#define SWPMI_ISR_SUSP_Pos (9U)
+#define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
+#define SWPMI_ISR_DEACTF_Pos (10U)
+#define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
+
+/******************* Bit definition for SWPMI_ICR register ********************/
+#define SWPMI_ICR_CRXBFF_Pos (0U)
+#define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
+#define SWPMI_ICR_CTXBEF_Pos (1U)
+#define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
+#define SWPMI_ICR_CRXBERF_Pos (2U)
+#define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
+#define SWPMI_ICR_CRXOVRF_Pos (3U)
+#define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
+#define SWPMI_ICR_CTXUNRF_Pos (4U)
+#define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
+#define SWPMI_ICR_CTCF_Pos (7U)
+#define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
+#define SWPMI_ICR_CSRF_Pos (8U)
+#define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
+
+/******************* Bit definition for SWPMI_IER register ********************/
+#define SWPMI_IER_SRIE_Pos (8U)
+#define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
+#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
+#define SWPMI_IER_TCIE_Pos (7U)
+#define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
+#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
+#define SWPMI_IER_TIE_Pos (6U)
+#define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
+#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
+#define SWPMI_IER_RIE_Pos (5U)
+#define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
+#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
+#define SWPMI_IER_TXUNRIE_Pos (4U)
+#define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
+#define SWPMI_IER_RXOVRIE_Pos (3U)
+#define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
+#define SWPMI_IER_RXBERIE_Pos (2U)
+#define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
+#define SWPMI_IER_TXBEIE_Pos (1U)
+#define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
+#define SWPMI_IER_RXBFIE_Pos (0U)
+#define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
+
+/******************* Bit definition for SWPMI_RFL register ********************/
+#define SWPMI_RFL_RFL_Pos (0U)
+#define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
+#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos (0U)
+#define SWPMI_RFL_RFL_0_1_Msk (0x3U << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/******************* Bit definition for SWPMI_TDR register ********************/
+#define SWPMI_TDR_TD_Pos (0U)
+#define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
+
+/******************* Bit definition for SWPMI_RDR register ********************/
+#define SWPMI_RDR_RD_Pos (0U)
+#define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
+
+/******************* Bit definition for SWPMI_OR register ********************/
+#define SWPMI_OR_TBYP_Pos (0U)
+#define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
+#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos (1U)
+#define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
+#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/* */
+/* VREFBUF */
+/* */
+/******************************************************************************/
+/******************* Bit definition for VREFBUF_CSR register ****************/
+#define VREFBUF_CSR_ENVR_Pos (0U)
+#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos (1U)
+#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
+#define VREFBUF_CSR_VRS_Pos (2U)
+#define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
+#define VREFBUF_CSR_VRR_Pos (3U)
+#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
+
+/******************* Bit definition for VREFBUF_CCR register ******************/
+#define VREFBUF_CCR_TRIM_Pos (0U)
+#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB2FZ register ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
+
+/******************** Bit definition for USB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_DCDET_Pos (0U)
+#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos (1U)
+#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos (2U)
+#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos (19U)
+#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos (20U)
+#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
+
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+
+/******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
+#define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
+
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1) || \
+ ((INSTANCE) == DFSDM1_Filter2) || \
+ ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3) || \
+ ((INSTANCE) == DFSDM1_Channel4) || \
+ ((INSTANCE) == DFSDM1_Channel5) || \
+ ((INSTANCE) == DFSDM1_Channel6) || \
+ ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5) || \
+ ((INSTANCE) == DMA2_Channel6) || \
+ ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+ ((INSTANCE) == SAI1_Block_B) || \
+ ((INSTANCE) == SAI2_Block_A) || \
+ ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
+ ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn TIM8_UP_IRQn
+#define HASH_RNG_IRQn RNG_IRQn
+#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler RNG_IRQHandler
+#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L475xx_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l4xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx.h
+ * @author MCD Application Team
+ * @version V1.3.1
+ * @date 21-April-2017
+ * @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32L4xx device used in the target application
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheralâs registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l4xx
+ * @{
+ */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+ application
+ */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+ !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+ !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+ !defined (STM32L496xx) && !defined (STM32L4A6xx)
+ /* #define STM32L431xx */ /*!< STM32L431xx Devices */
+ /* #define STM32L432xx */ /*!< STM32L432xx Devices */
+ /* #define STM32L433xx */ /*!< STM32L433xx Devices */
+ /* #define STM32L442xx */ /*!< STM32L442xx Devices */
+ /* #define STM32L443xx */ /*!< STM32L443xx Devices */
+ /* #define STM32L451xx */ /*!< STM32L451xx Devices */
+ /* #define STM32L452xx */ /*!< STM32L452xx Devices */
+ /* #define STM32L462xx */ /*!< STM32L462xx Devices */
+ #define STM32L471xx /*!< STM32L471xx Devices */
+ /* #define STM32L475xx */ /*!< STM32L475xx Devices */
+ /* #define STM32L476xx */ /*!< STM32L476xx Devices */
+ /* #define STM32L485xx */ /*!< STM32L485xx Devices */
+ /* #define STM32L486xx */ /*!< STM32L486xx Devices */
+ /* #define STM32L496xx */ /*!< STM32L496xx Devices */
+ /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V1.3.1
+ */
+#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32L431xx)
+ #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+ #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+ #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+ #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+ #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+ #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+ #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+ #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+ #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+ #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+ #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+ #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+ #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+ #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+ #include "stm32l4a6xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/system_stm32l4xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,127 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l4xx.h
+ * @author MCD Application Team
+ * @version V1.3.1
+ * @date 21-April-2017
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/us_ticker_data.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/mtqn_low_power.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,476 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, MultiTech Systems
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of MultiTech nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "mtqn_low_power.h"
+
+#include "stdio.h"
+#include "mbed_debug.h"
+
+static uint32_t portA[6];
+static uint32_t portB[6];
+static uint32_t portC[6];
+static uint32_t portD[6];
+static uint32_t portE[6];
+static uint32_t portF[6];
+static uint32_t portG[6];
+static uint32_t portH[6];
+
+void mtqn_disable_systick_int() {
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+void mtqn_enable_systick_int() {
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+void mtqn_save_gpio_state() {
+ portA[0] = GPIOA->MODER;
+ portA[1] = GPIOA->OTYPER;
+ portA[2] = GPIOA->OSPEEDR;
+ portA[3] = GPIOA->PUPDR;
+ portA[4] = GPIOA->AFR[0];
+ portA[5] = GPIOA->AFR[1];
+
+ portB[0] = GPIOB->MODER;
+ portB[1] = GPIOB->OTYPER;
+ portB[2] = GPIOB->OSPEEDR;
+ portB[3] = GPIOB->PUPDR;
+ portB[4] = GPIOB->AFR[0];
+ portB[5] = GPIOB->AFR[1];
+
+ portC[0] = GPIOC->MODER;
+ portC[1] = GPIOC->OTYPER;
+ portC[2] = GPIOC->OSPEEDR;
+ portC[3] = GPIOC->PUPDR;
+ portC[4] = GPIOC->AFR[0];
+ portC[5] = GPIOC->AFR[1];
+
+ portD[0] = GPIOD->MODER;
+ portD[1] = GPIOD->OTYPER;
+ portD[2] = GPIOD->OSPEEDR;
+ portD[3] = GPIOD->PUPDR;
+ portD[4] = GPIOD->AFR[0];
+ portD[5] = GPIOD->AFR[1];
+
+ portD[0] = GPIOD->MODER;
+ portD[1] = GPIOD->OTYPER;
+ portD[2] = GPIOD->OSPEEDR;
+ portD[3] = GPIOD->PUPDR;
+ portD[4] = GPIOD->AFR[0];
+ portD[5] = GPIOD->AFR[1];
+
+ portE[0] = GPIOE->MODER;
+ portE[1] = GPIOE->OTYPER;
+ portE[2] = GPIOE->OSPEEDR;
+ portE[3] = GPIOE->PUPDR;
+ portE[4] = GPIOE->AFR[0];
+ portE[5] = GPIOE->AFR[1];
+
+ portF[0] = GPIOF->MODER;
+ portF[1] = GPIOF->OTYPER;
+ portF[2] = GPIOF->OSPEEDR;
+ portF[3] = GPIOF->PUPDR;
+ portF[4] = GPIOF->AFR[0];
+ portF[5] = GPIOF->AFR[1];
+
+ portG[0] = GPIOG->MODER;
+ portG[1] = GPIOG->OTYPER;
+ portG[2] = GPIOG->OSPEEDR;
+ portG[3] = GPIOG->PUPDR;
+ portG[4] = GPIOG->AFR[0];
+ portG[5] = GPIOG->AFR[1];
+
+ portH[0] = GPIOH->MODER;
+ portH[1] = GPIOH->OTYPER;
+ portH[2] = GPIOH->OSPEEDR;
+ portH[3] = GPIOH->PUPDR;
+ portH[4] = GPIOH->AFR[0];
+ portH[5] = GPIOH->AFR[1];
+}
+
+void mtqn_restore_gpio_state() {
+ GPIOA->MODER = portA[0];
+ GPIOA->OTYPER = portA[1];
+ GPIOA->OSPEEDR = portA[2];
+ GPIOA->PUPDR = portA[3];
+ GPIOA->AFR[0] = portA[4];
+ GPIOA->AFR[1] = portA[5];
+
+ GPIOB->MODER = portB[0];
+ GPIOB->OTYPER = portB[1];
+ GPIOB->OSPEEDR = portB[2];
+ GPIOB->PUPDR = portB[3];
+ GPIOB->AFR[0] = portB[4];
+ GPIOB->AFR[1] = portB[5];
+
+ GPIOC->MODER = portC[0];
+ GPIOC->OTYPER = portC[1];
+ GPIOC->OSPEEDR = portC[2];
+ GPIOC->PUPDR = portC[3];
+ GPIOC->AFR[0] = portC[4];
+ GPIOC->AFR[1] = portC[5];
+
+ GPIOD->MODER = portD[0];
+ GPIOD->OTYPER = portD[1];
+ GPIOD->OSPEEDR = portD[2];
+ GPIOD->PUPDR = portD[3];
+ GPIOD->AFR[0] = portD[4];
+ GPIOD->AFR[1] = portD[5];
+
+ GPIOE->MODER = portE[0];
+ GPIOE->OTYPER = portE[1];
+ GPIOE->OSPEEDR = portE[2];
+ GPIOE->PUPDR = portE[3];
+ GPIOE->AFR[0] = portE[4];
+ GPIOE->AFR[1] = portE[5];
+
+ GPIOF->MODER = portF[0];
+ GPIOF->OTYPER = portF[1];
+ GPIOF->OSPEEDR = portF[2];
+ GPIOF->PUPDR = portF[3];
+ GPIOF->AFR[0] = portF[4];
+ GPIOF->AFR[1] = portF[5];
+
+ GPIOG->MODER = portG[0];
+ GPIOG->OTYPER = portG[1];
+ GPIOG->OSPEEDR = portG[2];
+ GPIOG->PUPDR = portG[3];
+ GPIOG->AFR[0] = portG[4];
+ GPIOG->AFR[1] = portG[5];
+
+ GPIOH->MODER = portH[0];
+ GPIOH->OTYPER = portH[1];
+ GPIOH->OSPEEDR = portH[2];
+ GPIOH->PUPDR = portH[3];
+ GPIOH->AFR[0] = portH[4];
+ GPIOH->AFR[1] = portH[5];
+}
+
+/**
+ * @brief System Clock Speed decrease
+ * The system Clock source is shifted from HSI to MSI
+ * while at the same time, MSI range is set to RCC_MSIRANGE_0
+ * to go down to 100 KHz
+ * @param None
+ * @retval None
+ */
+int SystemClock_Decrease(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+ /* MSI is enabled in range 0 (100Khz) */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ /* Initialization Error */
+ return -1;
+ }
+
+ /* Select MSI as system clock source and keep HCLK, PCLK1 and PCLK2 clocks dividers as before */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ /* Initialization Error */
+ return -1;
+ }
+
+ /* Disable HSI to reduce power consumption since MSI is used from that point */
+ __HAL_RCC_HSI_DISABLE();
+ __HAL_RCC_LSI_DISABLE();
+
+ return 0;
+}
+
+void mtqn_pull_up_pins(){
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ HAL_PWREx_EnablePullUpPullDownConfig();
+
+ /* Enable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* Disable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_DISABLE();
+ __HAL_RCC_GPIOB_CLK_DISABLE();
+ __HAL_RCC_GPIOC_CLK_DISABLE();
+ __HAL_RCC_GPIOD_CLK_DISABLE();
+ __HAL_RCC_GPIOH_CLK_DISABLE();
+ __HAL_RCC_GPIOE_CLK_DISABLE();
+ __HAL_RCC_GPIOF_CLK_DISABLE();
+ __HAL_RCC_GPIOG_CLK_DISABLE();
+}
+
+void mtqn_pull_down_pins(){
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ HAL_PWREx_EnablePullUpPullDownConfig();
+
+ /* Enable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All ;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* Disable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_DISABLE();
+ __HAL_RCC_GPIOB_CLK_DISABLE();
+ __HAL_RCC_GPIOC_CLK_DISABLE();
+ __HAL_RCC_GPIOD_CLK_DISABLE();
+ __HAL_RCC_GPIOH_CLK_DISABLE();
+ __HAL_RCC_GPIOE_CLK_DISABLE();
+ __HAL_RCC_GPIOF_CLK_DISABLE();
+ __HAL_RCC_GPIOG_CLK_DISABLE();
+}
+
+
+ void mtqn_float_pins(){
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ HAL_PWREx_EnablePullUpPullDownConfig();
+
+ /* Enable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_All;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* Disable GPIOs clock */
+ __HAL_RCC_GPIOA_CLK_DISABLE();
+ __HAL_RCC_GPIOB_CLK_DISABLE();
+ __HAL_RCC_GPIOC_CLK_DISABLE();
+ __HAL_RCC_GPIOD_CLK_DISABLE();
+ __HAL_RCC_GPIOH_CLK_DISABLE();
+ __HAL_RCC_GPIOE_CLK_DISABLE();
+ __HAL_RCC_GPIOF_CLK_DISABLE();
+ __HAL_RCC_GPIOG_CLK_DISABLE();
+}
+
+void mtqn_enter_stop_mode() {
+
+ mtqn_save_gpio_state();
+ mtqn_float_pins();
+
+ SystemClock_Decrease();
+ /* Suspend Tick increment for power consumption purposes */
+ HAL_SuspendTick();
+ __HAL_RCC_TIM5_CLK_DISABLE();
+
+ // make sure wakeup flag is cleared
+ __HAL_PWR_CLEAR_FLAG(
+ PWR_FLAG_WUF1 | PWR_FLAG_WUF2 | PWR_FLAG_WUF3 | PWR_FLAG_WUF4
+ | PWR_FLAG_WUF5 | PWR_FLAG_WUFI);
+ __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
+
+ HAL_PWREx_EnableInternalWakeUpLine();
+ HAL_PWREx_EnableLowPowerRunMode();
+
+
+ /* Enable Power Clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Ensure that MSI is wake-up system clock */
+ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
+
+ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+ HAL_PWREx_DisableLowPowerRunMode();
+
+ SetSysClock();
+ SystemCoreClockUpdate();
+
+ /* Resume Tick interrupt if disabled prior to Low Power Run mode entry */
+ HAL_ResumeTick();
+ __HAL_RCC_TIM5_CLK_ENABLE();
+
+ mtqn_restore_gpio_state();
+
+}
+
+void mtqn_enter_standby_mode() {
+ //mtqn_float_pins();
+ //mtqn_pull_down_pins();
+
+ /* Enable Power Clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Disable all used wakeup sources: WKUP pin */
+ HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN2);
+
+
+ /* Clear wake up Flag */
+ __HAL_PWR_CLEAR_FLAG(
+ PWR_FLAG_WUF1 | PWR_FLAG_WUF2 | PWR_FLAG_WUF3 | PWR_FLAG_WUF4
+ | PWR_FLAG_WUF5 | PWR_FLAG_WUFI);
+
+ /* Enable wakeup pin WKUP2 */
+ HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN2_LOW);
+
+ /* Set RTC back-up register RTC_BKP31R to indicate
+ later on that system has entered shutdown mode */
+ WRITE_REG( RTC->BKP31R, 0x1 );
+ /* Enter shutdown mode */
+
+ HAL_PWREx_EnterSHUTDOWNMode();
+}
+
+void mtqn_enable_standby_wake_pin() {
+ HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
+}
+
+void mtqn_disable_standby_wake_pin() {
+ HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/mtqn_low_power.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, MultiTech Systems
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of MultiTech nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef __MTQN_LOW_POWER_H__
+#define __MTQN_LOW_POWER_H__
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* mtqn_disable_systick_int
+ * disable the systick interrupt
+ * call this before mtqn_enter_stop_mode so systick interrupt doesn't wake up the processor
+ * only necessary if RTOS is used
+ */
+void mtqn_disable_systick_int();
+
+/* mtqn_enable_systick_int
+ * enable the systick interrupt
+ * call this after mtqn_enter_stop_mode so RTOS can function again
+ * only necessary if RTOS is used
+ */
+void mtqn_enable_systick_int();
+
+/* mtqn_save_gpio_state
+ * save current state of all GPIOs
+ * call this before mtqn_enter_stop_mode
+ * to achieve the lowest possible power consumption possible all GPIO pins must be configured for
+ * analog mode with no pull resistors enabled before entering STOP mode
+ * the mtqn_enter_stop_mode function does this for USBTX/RX and all internal pins
+ * after calling mtqn_save_gpio_state, the user application must do the same for WAKE, GPIO*,
+ * UART1_*, I2C_*, and SPI_* pins
+ * the user application should make a call to mtqn_restore_gpio_state after waking from STOP mode
+ * in order to restore GPIO functionality
+ */
+void mtqn_save_gpio_state();
+
+/* mtqn_restore_gpio_state
+ * restore all GPIOs to the state they were in when mtqn_save_gpio_state was called
+ * call this after exiting from STOP mode
+ */
+void mtqn_restore_gpio_state();
+
+/* mtqn_enter_stop_mode
+ * put the processor into STOP mode
+ * RAM and peripheral state is retained
+ * can be woken up by a number of interrupt sources including GPIOs and internal interrupts
+ * program execution resumes after this function when the device wakes up
+ */
+void mtqn_enter_stop_mode();
+
+/* mtqn_enter_standby_mode
+ * put the processor into STANDBY mode
+ * RAM and peripheral state is lost
+ * can be woken up by the RTC alarm and rising edge on WAKE pin (WAKE pin must be configured first)
+ * program execution starts from the beginning of the application when the device wakes up
+ */
+void mtqn_enter_standby_mode();
+
+/* mtqn_enable_standby_wake_pin
+ * configure the WAKE pin as a wakeup source from standby mode
+ * after this call, a rising edge on the WAKE pin will wake the processor up from standby mode
+ * this function should be called immediately before mtqn_enter_standby_mode
+ */
+void mtqn_enable_standby_wake_pin();
+
+/* mtqn_disnable_standby_wake_pin
+ * should be called after waking up from standby mode
+ */
+void mtqn_disable_standby_wake_pin();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRAGONFLY_LOW_POWER_H__ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/onboard_modem_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "onboard_modem_api.h"
+#include "gpio_api.h"
+#include "platform/mbed_wait_api.h"
+#include "PinNames.h"
+
+#if MODEM_ON_BOARD
+
+// Note microseconds not milliseconds
+static void press_power_button(int time_us)
+{
+ gpio_t gpio;
+ gpio_init_out_ex(&gpio, MDMPWRON, 1);
+ wait_us(time_us);
+ gpio_write(&gpio, 0);
+}
+
+void onboard_modem_init()
+{
+ gpio_t gpio;
+
+ // Take us out of reset
+ gpio_init_inout(&gpio, RADIO_PWR, PIN_OUTPUT, PushPullNoPull, 1);
+ gpio_init_inout(&gpio, BUF_EN, PIN_OUTPUT, OpenDrainNoPull, 0);
+ gpio_init_out_ex(&gpio, MDMRST, 0);
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+ gpio_init_inout(&gpio, RADIO_DTR, PIN_OUTPUT, OpenDrainNoPull, 0);
+}
+
+void onboard_modem_deinit()
+{
+ onboard_modem_power_down();
+ gpio_t gpio;
+
+ // Back into reset
+ gpio_init_out_ex(&gpio, MDMRST, 1);
+ gpio_init_out_ex(&gpio, MDMPWRON, 1);
+ gpio_init_inout(&gpio, BUF_EN, PIN_OUTPUT, OpenDrainNoPull, 1);
+ gpio_init_inout(&gpio, RADIO_PWR, PIN_OUTPUT, PushPullNoPull, 0);
+ gpio_init_inout(&gpio, RADIO_DTR, PIN_OUTPUT, OpenDrainNoPull, 1);
+}
+
+void onboard_modem_power_up()
+{
+ onboard_modem_init();
+
+ gpio_t gpio;
+ gpio_init_in(&gpio, MON_1V8);
+
+ if(gpio_is_connected(&gpio) && !gpio_read(&gpio)) {
+ unsigned int i = 0;
+ while(i < 3)
+ {
+ press_power_button(150000);
+ wait_ms(250);
+
+ if(gpio_read(&gpio))
+ {
+ break;
+ }
+ i++;
+ }
+ }
+}
+
+void onboard_modem_power_down()
+{
+ /* Activate PWR_ON for 1.5s to switch off */
+ press_power_button(1500000);
+ // check for 1.8v low if not, take reset low for 10s
+}
+
+#endif //MODEM_ON_BOARD
+#endif //MBED_CONF_NSAPI_PRESENT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 80
+ * AHBCLK (MHz) | 80
+ * APB1CLK (MHz) | 80
+ * APB2CLK (MHz) | 80
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+#define USE_PLL_MSI 0x1 // Use MSI internal clock
+
+#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR |= RCC_CR_MSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON , HSION, and PLLON bits */
+ RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x00001000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI()==0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+ /* 4- If fail start with MSI clock */
+ if (SetSysClock_PLL_MSI() == 0)
+#endif
+ {
+ while(1) {
+ MBED_ASSERT(1);
+ }
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+ // Used to gain time after DeepSleep in case HSI is used
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+ return 0;
+ }
+
+ // Select MSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+ RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+ RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Disable MSI Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+ // Select MSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
+ RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+ RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Disable MSI Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/* PLL (clocked by MSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ // Enable LSE Oscillator to automatically calibrate the MSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ }
+
+ HAL_RCCEx_DisableLSECSS();
+ /* Enable MSI Oscillator and activate PLL with MSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
+ RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
+ RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
+ RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
+ RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+ /* Enable MSI Auto-calibration through LSE */
+ HAL_RCCEx_EnableMSIPLLMode();
+ /* Select MSI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/ublox_low_level_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ublox_low_level_api.h"
+
+#include <stdbool.h>
+#include "gpio_api.h"
+
+void ublox_board_init(void) {
+ gpio_t gpio;
+
+ // Enable power to 3V3
+ gpio_init_inout(&gpio, RADIO_PWR, PIN_OUTPUT, PushPullNoPull, 1);
+ gpio_init_inout(&gpio, VUSB_EN, PIN_OUTPUT, OpenDrainNoPull, 0);
+
+ // start with modem disabled
+ gpio_init_out_ex(&gpio, MDMRST, 1);
+ gpio_init_out_ex(&gpio, MDMPWRON, 0);
+}
+
+// End Of File
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/ublox_low_level_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,14 @@
+#ifndef UBLOX_LOW_LEVEL_API_H
+#define UBLOX_LOW_LEVEL_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ublox_board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // UBLOX_LOW_LEVEL_H
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -71,6 +71,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -204,3 +204,24 @@
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -159,6 +159,15 @@
SYS_WKUP1 = PA_0,
SYS_WKUP4 = PA_2,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PB_1,
+ QSPI1_IO1 = PB_0,
+ QSPI1_IO2 = PA_7,
+ QSPI1_IO3 = PA_6,
+ QSPI1_SCK = PA_3,
+ QSPI1_CSN = PA_2,
+
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -322,15 +322,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -349,8 +353,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -114,7 +114,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -123,12 +123,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -9,7 +9,7 @@ /* [RAM = 48kb + 16kb = 0x10000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 98 x 4) */ define symbol __region_SRAM1_start__ = 0x20000188; define symbol __region_SRAM1_end__ = 0x2000FFFF;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -76,6 +76,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -259,3 +259,27 @@
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to SMPS_PG [ADP5301ACBZ_OUTOK]
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to SMPS_SW [TS3A44159PWR_IN1_2]
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+// {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to STDIO_UART_RX
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -236,6 +236,14 @@
SYS_WKUP2 = PC_13,
SYS_WKUP4 = PA_2,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PB_1,
+ QSPI1_IO1 = PB_0,
+ QSPI1_IO2 = PA_7,
+ QSPI1_IO3 = PA_6,
+ QSPI1_SCK = PB_10,
+ QSPI1_CSN = PB_11,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -322,15 +322,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -349,8 +353,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -92,13 +92,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -106,7 +106,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -114,7 +114,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -123,12 +123,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -9,7 +9,7 @@ /* [RAM = 48kb + 16kb = 0x10000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 98 x 4) */ define symbol __region_SRAM1_start__ = 0x20000188; define symbol __region_SRAM1_end__ = 0x2000FFFF;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -322,15 +322,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -349,8 +353,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/stm32l443xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/stm32l443xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -49,8 +49,8 @@
.ANY (+RW +ZI)
}
- ; Total: 99 vectors = 396 bytes (0x18C) to be reserved in RAM
- RW_IRAM2 (0x10000000+0x18C) (0x04000-0x18C) { ; RW data 16k L4-ECC-SRAM2 retained in standby
+ ; Total: 99 vectors = 396 bytes (0x18C+0x4) to be reserved in RAM
+ RW_IRAM2 (0x10000000+0x190) (0x04000-0x190) { ; RW data 16k L4-ECC-SRAM2 retained in standby
.ANY (+RW +ZI)
}
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/STM32L443XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/STM32L443XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -7,10 +7,11 @@
#endif
/* Linker script to configure memory regions. */
+/* 0x18C resevered for vectors; 8-byte aligned = 0x190 (0x18C + 0x4)*/
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- SRAM2 (rwx) : ORIGIN = 0x1000018C, LENGTH = 16k - 0x18C
+ SRAM2 (rwx) : ORIGIN = 0x10000190, LENGTH = 16k - (0x18C+0x4)
SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 48k
}
@@ -93,13 +94,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +108,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +116,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +125,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/stm32l443xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/stm32l443xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,9 +7,9 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 48kb + 16kb = 0xC000] */ -/* Vector table dynamic copy: Total: 99 vectors = 396 bytes (0x18C) to be reserved in RAM */ +/* Vector table dynamic copy: Total: 99 vectors * 4 = 396 bytes (0x18C) to be reserved in RAM */ define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x1000018F; /* Aligned on 8 bytes (400 = 50 x 8) */ +define symbol __NVIC_end__ = 0x1000018F; /* Add 4 more bytes to be aligned on 8 bytes */ define symbol __region_SRAM2_start__ = 0x10000190; define symbol __region_SRAM2_end__ = 0x10003FFF; define symbol __region_SRAM1_start__ = 0x20000000;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -83,6 +83,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -340,3 +340,29 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to PMOD_SPI2_SCK
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D12 [SPI1_MISO]
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D11 [SPI1_MOSI]
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARD_D3 [INT_EXT10]
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARD_D6 [ADC1_IN6]
+ {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to OQUADSPI_BK1_IO0 [MX25R6435F_IO0]
+ {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QUADSPI_BK1_IO1 [MX25R6435F_IO1]
+ {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QUAD_SPI_BK1_IO2 [MX25R6435F_IO2]
+ {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QUAD_SPI_BK1_IO3 [MX25R6435F_IO3]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL]
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QUADSPI_CLK [MX25R6435F_SCLK]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA]
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to QUADSPI_NCS [MX25R6435F_SCLK]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -274,6 +274,14 @@
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PE_12,
+ QSPI_FLASH1_IO1 = PE_13,
+ QSPI_FLASH1_IO2 = PE_14,
+ QSPI_FLASH1_IO3 = PE_15,
+ QSPI_FLASH1_SCK = PE_10,
+ QSPI_FLASH1_CSN = PE_11,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,15 +309,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -336,8 +340,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -93,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,9 +7,9 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 96kb + 32kb = 0x20000] */ -/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +/* Vector table dynamic copy: Total: 98 vectors * 4 = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __NVIC_end__ = 0x10000187; define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; define symbol __region_SRAM1_start__ = 0x20000000;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -58,6 +58,16 @@
RNG_HandleTypeDef handle;
};
+struct qspi_s {
+ QSPI_HandleTypeDef handle;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -83,6 +83,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -340,3 +340,29 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to MEMS_SCK [L3GD20_SCL/SPC]
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to SEG23 [GH08172T_SEG23]
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to SEG0 [GH08172T_SEG0]
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SEG21 [GH08172T_SEG21]
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SEG2 [GH08172T_SEG2]
+ {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
+ {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1]
+ {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
+ {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK [N25Q128A13EF840E_C]
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to QSPI_CS [N25Q128A13EF840E_S\#]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -258,6 +258,22 @@
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PE_12,
+ QSPI1_IO1 = PE_13,
+ QSPI1_IO2 = PE_14,
+ QSPI1_IO3 = PE_15,
+ QSPI1_SCK = PE_10,
+ QSPI1_CSN = PE_11,
+
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = QSPI1_IO0,
+ QSPI_FLASH1_IO1 = QSPI1_IO1,
+ QSPI_FLASH1_IO2 = QSPI1_IO2,
+ QSPI_FLASH1_IO3 = QSPI1_IO3,
+ QSPI_FLASH1_SCK = QSPI1_SCK,
+ QSPI_FLASH1_CSN = QSPI1_CSN,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,15 +309,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -336,8 +340,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -83,6 +83,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_BASE
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -305,3 +305,23 @@
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,15 +309,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -336,8 +340,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,15 +309,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -336,8 +340,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -93,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/stm32l476xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/stm32l476xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,9 +7,9 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 96kb + 32kb = 0x20000] */ -/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +/* Vector table dynamic copy: Total: 98 vectors * 4 = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __NVIC_end__ = 0x10000187; define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; define symbol __region_SRAM1_start__ = 0x20000000;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -58,6 +58,16 @@
RNG_HandleTypeDef handle;
};
+struct qspi_s {
+ QSPI_HandleTypeDef handle;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -321,15 +321,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -348,8 +352,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -83,6 +83,10 @@
CAN_1 = (int)CAN1_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_BASE
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -305,3 +305,23 @@
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -309,15 +309,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -336,8 +340,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -93,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -115,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -124,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/stm32l486xx.icf Thu Nov 08 11:46:34 2018 +0000 @@ -7,9 +7,9 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 96kb + 32kb = 0x20000] */ -/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +/* Vector table dynamic copy: Total: 98 vectors * 4 = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __NVIC_end__ = 0x10000187; define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; define symbol __region_SRAM1_start__ = 0x20000000;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -421,3 +421,49 @@
{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D9
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [MX25R6435FM2IL0_SIO3]
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [MX25R6435FM2IL0_SIO2]
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [MX25R6435FM2IL0_SIO1]
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [MX25R6435FM2IL0_SIO0]
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS]
+ {PC_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to ADCx_IN2
+ {PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to DF_CKOUT
+ {PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to ARD_A2
+ {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to ARD_A0
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to OE [OE_IS66WV51216EBLL]
+ {PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to WE [WE_IS66WV51216EBLL]
+// {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to STDIO_UART_RX
+// {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to STDIO_UART_RX
+ {PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to LCD_NE
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to D8 [D8_IS66WV51216EBLL]
+ {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to D9 [D9_IS66WV51216EBLL]
+ {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to D10 [D10_IS66WV51216EBLL]
+ {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to D11 [D11_IS66WV51216EBLL]
+ {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to D12 [D12_IS66WV51216EBLL]
+ {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to STMOD_INT
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK [MX25R6435FM2IL0_SCLK]
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to SAI1_SCK_A
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to D7 [D7_IS66WV51216EBLL]
+ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // QUADSPI_CLK // Connected to ARD_A3
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS]
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to D8 [D8_IS66WV51216EBLL]
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -341,6 +341,14 @@
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
+ /**** QSPI FLASH pins ****/
+ QSPI_FLASH1_IO0 = PB_1,
+ QSPI_FLASH1_IO1 = PB_0,
+ QSPI_FLASH1_IO2 = PA_7,
+ QSPI_FLASH1_IO3 = PA_6,
+ QSPI_FLASH1_SCK = PB_11,
+ QSPI_FLASH1_CSN = PA_3,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -323,15 +323,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -349,8 +353,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -85,6 +85,10 @@
CAN_2 = (int)CAN2_BASE
} CANName;
+typedef enum {
+ QSPI_1 = (int)QSPI_BASE
+} QSPIName;
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -409,3 +409,52 @@
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+ {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P
+ {PC_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+ {PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0
+ {PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_IO1
+ {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2
+ {PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
+ {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
+ {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
+ {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+ {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
+ {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // QUADSPI_CLK
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+ {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P
+ {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS
+ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
+ {NC, NC, 0}
+};
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -317,6 +317,14 @@
SYS_WKUP4 = PA_2,
SYS_WKUP5 = PC_5,
+ /**** QSPI pins ****/
+ QSPI1_IO0 = PE_12,
+ QSPI1_IO1 = PB_0,
+ QSPI1_IO2 = PE_14,
+ QSPI1_IO3 = PE_15,
+ QSPI1_SCK = PB_10,
+ QSPI1_CSN = PA_2,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -323,15 +323,19 @@
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+#if MBED_CONF_TARGET_LSE_AVAILABLE
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
}
+ /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
HAL_RCCEx_DisableLSECSS();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -349,8 +353,12 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
+
+#if MBED_CONF_TARGET_LSE_AVAILABLE
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
+#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
+
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2018, STMicroelectronics
@@ -27,17 +28,25 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
; 1MB FLASH (0x100000) + 320KB SRAM (0x50000)
-LR_IROM1 0x08000000 0x100000 { ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
- ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x50000-0x1AC) { ; RW data 320k L4-SRAM1
+ ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x50000-0x1B0) { ; RW data 320k L4-SRAM1
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -1,3 +1,4 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2018, STMicroelectronics
@@ -27,17 +28,25 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
; 1MB FLASH (0x100000) + 320KB SRAM (0x50000)
-LR_IROM1 0x08000000 0x100000 { ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
- ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
- ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x1AC) (0x50000-0x1AC) { ; RW data 320k L4-SRAM1
+ ; Total: 107 vectors = 428 bytes (0x1AC); 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1B0) (0x50000-0x1B0) { ; RW data 320k L4-SRAM1
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld Thu Nov 08 11:46:34 2018 +0000
@@ -1,8 +1,17 @@
/* Linker script to configure memory regions. */
+/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
MEMORY
{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
- SRAM1 (rwx) : ORIGIN = 0x200001AC, LENGTH = 320k - 0x1AC
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ SRAM1 (rwx) : ORIGIN = 0x200001B0, LENGTH = 320k - (0x1AC +0x4)
}
/* Linker script to place sections and symbol values. Should be used together
@@ -84,13 +93,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -98,7 +107,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -106,7 +115,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
_edata = .;
@@ -115,12 +124,12 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
_ebss = .;
} > SRAM1
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -1,13 +1,16 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
/* [ROM = 1024kb = 0x100000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x08000000 + 0x100000 - 1;
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 0x50000] */
-/* Vector table dynamic copy: Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM */
+/* Vector table dynamic copy: Total: 107 vectors * 4 = 428 bytes (0x1AC) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200001AC - 1;
-define symbol __region_SRAM1_start__ = 0x200001AC; /* Aligned on 8 bytes (428 = 53 x 8) */
+define symbol __NVIC_end__ = 0x200001AF; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_SRAM1_start__ = 0x200001B0;
define symbol __region_SRAM1_end__ = 0x2004FFFF;
/* Memory regions */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,378 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+ {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+ {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]
+ {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, // Connected to LD2 [Blue]
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_11_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+ {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LD3 [Red]
+ {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)},
+ {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+// {PG_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_RX
+ {PG_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+ {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+// {PG_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_TX
+ {PG_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 (i.e. PWM_5) cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]
+ {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to LD2 [Blue]
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]
+ {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to LD3 [Red]
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+// {PF_6, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+// {PF_7, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+// {PF_8, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PF_9, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PF_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PF_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PG_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PG_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PG_11, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX
+ {PG_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+ {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID
+ {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]
+ {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX
+ {PG_8, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX
+ {PG_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
+ {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]
+ {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_OverCurrent [STMPS2151STR_FAULT]
+ {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
+ {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD2 [Blue]
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PG_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DP
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},
+ {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DM
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)}, // Connected to USB_VBUS
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
+ {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_9, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PG_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
+ {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,331 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200,
+ ALT2 = 0x300,
+ ALT3 = 0x400
+} ALTx;
+
+typedef enum {
+
+ PA_0 = 0x00,
+ PA_0_ALT0 = PA_0 | ALT0,
+ PA_1 = 0x01,
+ PA_1_ALT0 = PA_1 | ALT0,
+ PA_1_ALT1 = PA_1 | ALT1,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2 | ALT0,
+ PA_2_ALT1 = PA_2 | ALT1,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3 | ALT0,
+ PA_3_ALT1 = PA_3 | ALT1,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4 | ALT0,
+ PA_5 = 0x05,
+ PA_5_ALT0 = PA_5 | ALT0,
+ PA_6 = 0x06,
+ PA_6_ALT0 = PA_6 | ALT0,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7 | ALT0,
+ PA_7_ALT1 = PA_7 | ALT1,
+ PA_7_ALT2 = PA_7 | ALT2,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15 | ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0 | ALT0,
+ PB_0_ALT1 = PB_0 | ALT1,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1 | ALT0,
+ PB_1_ALT1 = PB_1 | ALT1,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3 | ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4 | ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5 | ALT0,
+ PB_6 = 0x16,
+ PB_6_ALT0 = PB_6 | ALT0,
+ PB_7 = 0x17,
+ PB_7_ALT0 = PB_7 | ALT0,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8 | ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9 | ALT0,
+ PB_10 = 0x1A,
+ PB_10_ALT0 = PB_10 | ALT0,
+ PB_11 = 0x1B,
+ PB_11_ALT0 = PB_11 | ALT0,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_13_ALT0 = PB_13 | ALT0,
+ PB_14 = 0x1E,
+ PB_14_ALT0 = PB_14 | ALT0,
+ PB_14_ALT1 = PB_14 | ALT1,
+ PB_15 = 0x1F,
+ PB_15_ALT0 = PB_15 | ALT0,
+ PB_15_ALT1 = PB_15 | ALT1,
+
+ PC_0 = 0x20,
+ PC_0_ALT0 = PC_0 | ALT0,
+ PC_0_ALT1 = PC_0 | ALT1,
+ PC_1 = 0x21,
+ PC_1_ALT0 = PC_1 | ALT0,
+ PC_1_ALT1 = PC_1 | ALT1,
+ PC_2 = 0x22,
+ PC_2_ALT0 = PC_2 | ALT0,
+ PC_2_ALT1 = PC_2 | ALT1,
+ PC_3 = 0x23,
+ PC_3_ALT0 = PC_3 | ALT0,
+ PC_3_ALT1 = PC_3 | ALT1,
+ PC_4 = 0x24,
+ PC_4_ALT0 = PC_4 | ALT0,
+ PC_5 = 0x25,
+ PC_5_ALT0 = PC_5 | ALT0,
+ PC_6 = 0x26,
+ PC_6_ALT0 = PC_6 | ALT0,
+ PC_7 = 0x27,
+ PC_7_ALT0 = PC_7 | ALT0,
+ PC_8 = 0x28,
+ PC_8_ALT0 = PC_8 | ALT0,
+ PC_9 = 0x29,
+ PC_9_ALT0 = PC_9 | ALT0,
+ PC_10 = 0x2A,
+ PC_10_ALT0 = PC_10 | ALT0,
+ PC_11 = 0x2B,
+ PC_11_ALT0 = PC_11 | ALT0,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_9_ALT0 = PF_9 | ALT0,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // Arduino J3 connector namings
+ A0 = PA_3,
+ A1 = PC_0,
+ A2 = PC_3,
+ A3 = PC_1,
+ A4 = PC_4,
+ A5 = PC_5,
+ D0 = PD_9,
+ D1 = PD_8,
+ D2 = PF_15,
+ D3 = PE_13,
+ D4 = PF_14,
+ D5 = PE_11,
+ D6 = PE_9,
+ D7 = PF_13,
+ D8 = PF_12,
+ D9 = PD_15,
+ D10 = PD_14,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PG_7,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PG_8,
+#endif
+
+ // Generic signals namings
+ LED1 = PC_7, // Green
+ LED2 = PB_7, // Blue
+ LED3 = PB_14, // Red
+ LED4 = LED1,
+ LED_RED = LED3,
+ USER_BUTTON = PC_13,
+
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX, // Virtual Com Port
+ SERIAL_RX = STDIO_UART_RX, // Virtual Com Port
+ USBTX = STDIO_UART_TX, // Virtual Com Port
+ USBRX = STDIO_UART_RX, // Virtual Com Port
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ PWM_OUT = D9,
+
+/**** USB pins ****/
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_NOE = PC_9,
+ USB_OTG_FS_NOE_ALT0 = PA_13,
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_SOF_ALT0 = PA_14,
+ USB_OTG_FS_VBUS = PA_9,
+
+/**** OSCILLATOR pins ****/
+ RCC_OSC32_IN = PC_14,
+ RCC_OSC32_OUT = PC_15,
+ RCC_OSC_IN = PH_0,
+ RCC_OSC_OUT = PH_1,
+
+/**** DEBUG pins ****/
+ SYS_JTCK_SWCLK = PA_14,
+ SYS_JTDI = PA_15,
+ SYS_JTDO_SWO = PB_3,
+ SYS_JTMS_SWDIO = PA_13,
+ SYS_JTRST = PB_4,
+ SYS_PVD_IN = PB_7,
+ SYS_TRACECLK = PE_2,
+ SYS_TRACED0 = PE_3,
+ SYS_TRACED0_ALT0 = PC_1,
+ SYS_TRACED0_ALT1 = PC_9,
+ SYS_TRACED1 = PE_4,
+ SYS_TRACED1_ALT0 = PC_10,
+ SYS_TRACED2 = PE_5,
+ SYS_TRACED2_ALT0 = PD_2,
+ SYS_TRACED3 = PE_6,
+ SYS_TRACED3_ALT0 = PC_12,
+ SYS_WKUP1 = PA_0,
+ SYS_WKUP2 = PC_13,
+ SYS_WKUP3 = PE_6,
+ SYS_WKUP4 = PA_2,
+ SYS_WKUP5 = PC_5,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,383 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 80
+ * AHBCLK (MHz) | 80
+ * APB1CLK (MHz) | 80
+ * APB2CLK (MHz) | 80
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+#define USE_PLL_MSI 0x1 // Use MSI internal clock
+
+#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR |= RCC_CR_MSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON , HSION, and PLLON bits */
+ RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x00001000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+ /* 4- If fail start with MSI clock */
+ if (SetSysClock_PLL_MSI() == 0)
+#endif
+ {
+ while (1) {
+ MBED_ASSERT(1);
+ }
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+ // Used to gain time after DeepSleep in case HSI is used
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+ return 0;
+ }
+
+ // Select MSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+ RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+ RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Disable MSI Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ /* Select HSI as clock source for LPUART1 */
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+ if (bypass == 0) {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ } else {
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ }
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+ // Select MSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
+ RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+ RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+ RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Disable MSI Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ /* Select HSI as clock source for LPUART1 */
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/* PLL (clocked by MSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ // Enable LSE Oscillator to automatically calibrate the MSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+ }
+
+ HAL_RCCEx_DisableLSECSS();
+ /* Enable MSI Oscillator and activate PLL with MSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
+ RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
+ RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
+ RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
+ RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+ /* Enable MSI Auto-calibration through LSE */
+ HAL_RCCEx_EnableMSIPLLMode();
+ /* Select MSI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select LSE as clock source for LPUART1 */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32l4r5xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,432 @@ +;********************** COPYRIGHT(c) 2017 STMicroelectronics ****************** +;* File Name : startup_stm32l4r5xx.s +;* Author : MCD Application Team +;* Description : STM32L4R5xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x200A0000 ; Top of RAM (640KB) + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler) + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD 0 ; Reserved + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD OCTOSPI2_IRQHandler ; OctoSPI2 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS global interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D global interrupt + DCD LTDC_IRQHandler ; LTDC global interrupt + DCD LTDC_ER_IRQHandler ; LTDC error global interrupt + DCD GFXMMU_IRQHandler ; GFXMMU global interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 overrun global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +OCTOSPI1_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +OCTOSPI2_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_ER_IRQHandler +I2C4_EV_IRQHandler +DCMI_IRQHandler +DMA2D_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +GFXMMU_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/stm32l4r5xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,52 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2018, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; 2MB FLASH (0x200000) + 640KB SRAM (0xA0000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 111 vectors = 444 bytes (0x1BC) (+ 4 bytes for 8-byte alignment) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C0) (0xA0000-0x1C0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/startup_stm32l4r5xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,415 @@ +;********************** COPYRIGHT(c) 2017 STMicroelectronics ****************** +;* File Name : startup_stm32l4r5xx.s +;* Author : MCD Application Team +;* Description : STM32L4R5xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + +__initial_sp EQU 0x200A0000 ; Top of RAM (640KB) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD 0 ; Reserved + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD OCTOSPI2_IRQHandler ; OctoSPI2 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS global interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D global interrupt + DCD LTDC_IRQHandler ; LTDC global interrupt + DCD LTDC_ER_IRQHandler ; LTDC error global interrupt + DCD GFXMMU_IRQHandler ; GFXMMU global interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 overrun global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +OCTOSPI1_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +OCTOSPI2_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_ER_IRQHandler +I2C4_EV_IRQHandler +DCMI_IRQHandler +DMA2D_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +GFXMMU_IRQHandler +DMAMUX1_OVR_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/stm32l4r5xx.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,52 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2018, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+; 2MB FLASH (0x200000) + 640KB SRAM (0xA0000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 111 vectors = 444 bytes (0x1BC) (+ 4 bytes for 8-byte alignment) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1C0) (0xA0000-0x1C0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/startup_stm32l4r5xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,560 @@ +/** + ****************************************************************************** + * @file startup_stm32l4r5xx.s + * @author MCD Application Team + * @brief STM32L4R5xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM1_FLT3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word 0 + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word DFSDM1_FLT2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word OCTOSPI1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word OCTOSPI2_IRQHandler + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + .word I2C4_ER_IRQHandler + .word I2C4_EV_IRQHandler + .word DCMI_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word DMA2D_IRQHandler + .word LTDC_IRQHandler + .word LTDC_ER_IRQHandler + .word GFXMMU_IRQHandler + .word DMAMUX1_OVR_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/stm32l4r5xx.ld Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,162 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 2048K
+#endif
+
+/* Linker script to configure memory regions. */
+/* Total: 111 vectors = 444 bytes (0x1BC) (+ 4 bytes for 8-byte alignment) to be reserved in RAM */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ SRAM1 (rwx) : ORIGIN = 0x200001C0, LENGTH = 640k - 0x1C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > SRAM1
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > SRAM1
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > SRAM1
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM1
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/startup_stm32l4r5xx.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,683 @@ +;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l4r5xx.s +;* Author : MCD Application Team +;* Description : STM32L4R5xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD 0 ; Reserved + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD OCTOSPI2_IRQHandler ; OctoSPI2 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D global interrupt + DCD LTDC_IRQHandler ; LTDC global interrupt + DCD LTDC_ER_IRQHandler ; LTDC error global interrupt + DCD GFXMMU_IRQHandler ; GFXMMU global interrupt + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 overrun global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/stm32l4r5xx.icf Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,35 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
+
+/* [ROM = 2MB = 0x200000] */
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 640KB = 0xA0000] */
+/* Vector table dynamic copy */
+/* Total: 111 vectors = 444 bytes (0x1BC) (+ 4 bytes for 8-byte alignment) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000000 + 0x1C0 - 1;
+define symbol __region_SRAM1_start__ = 0x20000000 + 0x1C0;
+define symbol __region_SRAM1_end__ = 0x20000000 + 0xA0000 - 1;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x400; /* 1KB */
+define symbol __size_heap__ = 0x20000; /* 128KB */
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in SRAM1_region { readwrite, block STACKHEAP };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/cmsis.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,22 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/cmsis_nvic.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,25 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 95 vectors = 380 bytes from 0x40 to 0x1BB +// Total: 111 vectors = 444 bytes (0x1BC) to be reserved in RAM +#define NVIC_NUM_VECTORS 111 +#define NVIC_RAM_VECTOR_ADDRESS 0X20000000 // Vectors positioned at start of SRAM + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+ RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4r5xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,20158 @@
+/**
+ ******************************************************************************
+ * @file stm32l4r5xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32L4R5xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32l4r5xx
+ * @{
+ */
+
+#ifndef __STM32L4R5xx_H
+#define __STM32L4R5xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
+ LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
+ LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
+ OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
+ SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
+ OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */
+ TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
+ RNG_IRQn = 80, /*!< RNG global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ CRS_IRQn = 82, /*!< CRS global interrupt */
+ I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */
+ I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
+ DCMI_IRQn = 85, /*!< DCMI global interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
+ DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x1C */
+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x2C */
+ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, 0x48 */
+ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
+ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+ __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA Multiplexer
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
+ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
+ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
+ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
+ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+ * @brief Firewall
+ */
+
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
+ __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
+ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
+ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
+ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
+ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
+ uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
+ __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+ __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
+ __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
+ __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
+ uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */
+ __IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+
+} GPIO_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
+ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
+ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
+ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
+ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
+ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
+ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
+ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
+ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
+ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
+ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+ __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */
+ __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
+ uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */
+ __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
+} PWR_TypeDef;
+
+
+/**
+ * @brief OCTO Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
+ __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
+ __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
+ __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
+ uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */
+ __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
+ __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
+ __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
+ __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
+ __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
+ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
+ __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
+ __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
+ __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
+ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
+ __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
+ __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
+ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
+ __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
+ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
+ __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
+ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
+ __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
+ uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */
+ __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
+ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */
+ __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */
+ __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
+ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */
+ __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
+ uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
+ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
+} OCTOSPI_TypeDef;
+
+/**
+ * @brief OCTO Serial Peripheral Interface IO Manager
+ */
+
+typedef struct
+{
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */
+ __IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */
+} OCTOSPIM_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
+ __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
+ __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
+ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
+ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
+ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
+ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
+ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
+ __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
+ __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
+ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
+ __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
+ __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
+ uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
+} SDMMC_TypeDef;
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
+ __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
+ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
+ __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */
+} SYSCFG_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
+ __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+ * @brief VREFBUF
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
+ __IO uint32_t GHWCFG1; /* User HW config1 044h*/
+ __IO uint32_t GHWCFG2; /* User HW config2 048h*/
+ __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
+ uint32_t Reserved6; /* Reserved 050h*/
+ __IO uint32_t GLPMCFG; /* LPM Register 054h*/
+ __IO uint32_t GPWRDN; /* Power Down Register 058h*/
+ __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
+ __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
+ uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address */
+#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 192 KB) base address */
+#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */
+#define SRAM3_BASE ((uint32_t)0x20040000U) /*!< SRAM3(384 KB) base address */
+#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
+#define OCTOSPI1_BASE ((uint32_t)0x90000000U) /*!< OCTOSPI1 memories accessible over AHB base address */
+#define OCTOSPI2_BASE ((uint32_t)0x70000000U) /*!< OCTOSPI2 memories accessible over AHB base address */
+
+#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
+#define OCTOSPI1_R_BASE ((uint32_t)0xA0001000U) /*!< OCTOSPI1 control registers base address */
+#define OCTOSPI2_R_BASE ((uint32_t)0xA0001400U) /*!< OCTOSPI2 control registers base address */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX ((uint32_t)0x00030000U) /*!< maximum SRAM1 size (up to 192 KBytes) */
+#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */
+#define SRAM3_SIZE ((uint32_t)0x00060000U) /*!< SRAM3 size (384 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1 FMC_BASE
+#define FMC_BANK1_1 FMC_BANK1
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3 (FMC_BASE + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
+#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
+
+
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
+
+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004)
+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008)
+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C)
+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010)
+#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014)
+#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018)
+#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C)
+#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020)
+#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024)
+#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028)
+#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002C)
+#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030)
+#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034)
+
+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100)
+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104)
+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108)
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010C)
+
+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080)
+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U)
+
+#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
+
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U)
+
+#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
+
+#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00U)
+#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400U)
+
+/*!< FMC Banks registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
+#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0 DFSDM1_Channel0
+#define DFSDM_Channel1 DFSDM1_Channel1
+#define DFSDM_Channel2 DFSDM1_Channel2
+#define DFSDM_Channel3 DFSDM1_Channel3
+#define DFSDM_Channel4 DFSDM1_Channel4
+#define DFSDM_Channel5 DFSDM1_Channel5
+#define DFSDM_Channel6 DFSDM1_Channel6
+#define DFSDM_Channel7 DFSDM1_Channel7
+#define DFSDM_Filter0 DFSDM1_Filter0
+#define DFSDM_Filter1 DFSDM1_Filter1
+#define DFSDM_Filter2 DFSDM1_Filter2
+#define DFSDM_Filter3 DFSDM1_Filter3
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
+
+
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+
+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+
+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+
+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
+#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
+#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+
+/******************** Bit definition for ADC_ISR register *******************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
+
+/******************** Bit definition for ADC_IER register *******************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC (ADC_IER_EOCIE)
+#define ADC_IER_EOS (ADC_IER_EOSIE)
+#define ADC_IER_OVR (ADC_IER_OVRIE)
+#define ADC_IER_JEOC (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos (30U)
+#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+
+/******************** Bit definition for ADC_CFGR register ******************/
+#define ADC_CFGR_DMAEN_Pos (0U)
+#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos (1U)
+#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_DFSDMCFG_Pos (2U)
+#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
+#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
+
+#define ADC_CFGR_RES_Pos (3U)
+#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
+#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos (5U)
+#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos (6U)
+#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos (10U)
+#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos (12U)
+#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos (13U)
+#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos (14U)
+#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos (16U)
+#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos (17U)
+#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos (20U)
+#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos (21U)
+#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos (22U)
+#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos (23U)
+#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos (24U)
+#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos (25U)
+#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos (26U)
+#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos (31U)
+#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
+
+/******************** Bit definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/******************** Bit definition for ADC_SMPR1 register *****************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+#define ADC_SMPR1_SMPPLUS_Pos (31U)
+#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
+#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
+
+/******************** Bit definition for ADC_SMPR2 register *****************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for ADC_TR1 register *******************/
+#define ADC_TR1_LT1_Pos (0U)
+#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
+#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
+#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
+#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
+#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
+#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
+#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
+#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
+#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
+#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
+#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
+#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos (16U)
+#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
+#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
+#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
+#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
+#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
+#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
+#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
+#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
+#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
+#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
+#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
+#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_TR2 register *******************/
+#define ADC_TR2_LT2_Pos (0U)
+#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
+#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
+#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
+#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
+#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
+#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
+#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
+#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos (16U)
+#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
+#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
+#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
+#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
+#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
+#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
+#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
+#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_TR3 register *******************/
+#define ADC_TR3_LT3_Pos (0U)
+#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
+#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
+#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
+#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
+#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
+#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
+#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
+#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos (16U)
+#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
+#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
+#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
+#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
+#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
+#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
+#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
+#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_SQR1 register ******************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ******************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ******************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ******************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
+#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
+#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
+#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
+#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
+#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
+#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
+#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
+#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
+#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
+#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
+#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
+#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
+#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
+#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
+#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JSQR register ******************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos (6U)
+#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos (8U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos (14U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos (20U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos (26U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_OFR1 register ******************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos (31U)
+#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ******************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos (31U)
+#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ******************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos (31U)
+#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ******************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos (31U)
+#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR2 register ******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR3 register ******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR4 register ******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_AWD2CR register ****************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_AWD3CR register ****************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_DIFSEL register ****************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_CALFACT register ***************/
+#define ADC_CALFACT_CALFACT_S_Pos (0U)
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos (16U)
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CCR register *******************/
+#define ADC_CCR_CKMODE_Pos (16U)
+#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos (1U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (2U)
+#define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN1_Pos (14U)
+#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_HFSEL_Pos (15U)
+#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
+#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
+
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos (17U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (18U)
+#define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN2_Pos (30U)
+#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos (14U)
+#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos (15U)
+#define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
+#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos (30U)
+#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos (31U)
+#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
+#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
+
+/******************* Bit definition for DAC_CCR register ********************/
+#define DAC_CCR_OTRIM1_Pos (0U)
+#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos (16U)
+#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
+
+/******************* Bit definition for DAC_MCR register *******************/
+#define DAC_MCR_MODE1_Pos (0U)
+#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
+#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos (16U)
+#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
+#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for DAC_SHSR1 register ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
+
+/****************** Bit definition for DAC_SHSR2 register ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
+
+/****************** Bit definition for DAC_SHHR register ******************/
+#define DAC_SHHR_THOLD1_Pos (0U)
+#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos (16U)
+#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
+
+/****************** Bit definition for DAC_SHRR register ******************/
+#define DAC_SHRR_TREFRESH1_Pos (0U)
+#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos (16U)
+#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk /*!< DCMI Capture enable */
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk /*!< DCMI Capture mode */
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk /*!< DCMI Crop feature */
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk /*!< DCMI JPEG format */
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk /*!< DCMI Embedded synchronization select */
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk /*!< DCMI Pixel clock polarity */
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk /*!< DCMI Horizontal synchronization polarity */
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk /*!< DCMI Vertical synchronization polarity */
+#define DCMI_CR_FCRC_Pos (8U)
+#define DCMI_CR_FCRC_Msk (0x3U << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */
+#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0 (0x1U << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1 (0x2U << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos (10U)
+#define DCMI_CR_EDM_Msk (0x3U << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */
+#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0 (0x1U << DCMI_CR_EDM_Pos) /*!< 0x00000400 */
+#define DCMI_CR_EDM_1 (0x2U << DCMI_CR_EDM_Pos) /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk /*!< DCMI DCMI enable */
+#define DCMI_CR_BSM_Pos (16U)
+#define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
+#define DCMI_CR_BSM DCMI_CR_BSM_Msk /*!< DCMI Byte Select mode BSM[1:0] */
+#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
+#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos (18U)
+#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk /*!< DCMI Odd/Even Byte Select (Byte Select Start) */
+#define DCMI_CR_LSM_Pos (19U)
+#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk /*!< DCMI Line Select mode */
+#define DCMI_CR_OELS_Pos (20U)
+#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk /*!< DCMI Odd/Even Line Select (Line Select Start) */
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk /*!< DCMI FIFO not empty */
+
+/******************** Bits definition for DCMI_RISR register ****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk /*!< DCMI Capture complete raw interrupt status */
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk /*!< DCMI Overrun raw interrupt status */
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk /*!< DCMI Synchronization error raw interrupt status */
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk /*!< DCMI VSYNC raw interrupt status */
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /*!< DCMI Line raw interrupt status */
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk /*!< DCMI Capture complete interrupt enable */
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk /*!< DCMI Overrun interrupt enable */
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk /*!< DCMI Synchronization error interrupt enable */
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk /*!< DCMI VSYNC interrupt enable */
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /*!< DCMI Line interrupt enable */
+#define DCMI_IER_INT_IE_Pos (0U)
+#define DCMI_IER_INT_IE_Msk (0x1FU << DCMI_IER_INT_IE_Pos) /*!< 0x0000001F */
+#define DCMI_IER_INT_IE DCMI_IER_INT_IE_Msk
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk /*!< DCMI Capture complete masked interrupt status */
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk /*!< DCMI Overrun masked interrupt status */
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk /*!< DCMI Synchronization error masked interrupt status */
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk /*!< DCMI VSYNC masked interrupt status */
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /*!< DCMI Line masked interrupt status */
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk /*!< DCMI Capture complete interrupt status clear */
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk /*!< DCMI Overrun interrupt status clear */
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk /*!< DCMI Synchronization error interrupt status clear */
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk /*!< DCMI Vertical synch interrupt status clear */
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /*!< DCMI line interrupt status clear */
+
+/******************** Bits definition for DCMI_ESCR register ****************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk /*!< DCMI Frame start delimiter code FSC[7:0] */
+#define DCMI_ESCR_FSC_0 (0x01U << DCMI_ESCR_FSC_Pos) /*!< 0x00000001 */
+#define DCMI_ESCR_FSC_1 (0x02U << DCMI_ESCR_FSC_Pos) /*!< 0x00000002 */
+#define DCMI_ESCR_FSC_2 (0x04U << DCMI_ESCR_FSC_Pos) /*!< 0x00000004 */
+#define DCMI_ESCR_FSC_3 (0x08U << DCMI_ESCR_FSC_Pos) /*!< 0x00000008 */
+#define DCMI_ESCR_FSC_4 (0x10U << DCMI_ESCR_FSC_Pos) /*!< 0x00000010 */
+#define DCMI_ESCR_FSC_5 (0x20U << DCMI_ESCR_FSC_Pos) /*!< 0x00000020 */
+#define DCMI_ESCR_FSC_6 (0x40U << DCMI_ESCR_FSC_Pos) /*!< 0x00000040 */
+#define DCMI_ESCR_FSC_7 (0x80U << DCMI_ESCR_FSC_Pos) /*!< 0x00000080 */
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk /*!< DCMI Line start delimiter code LSC[7:0] */
+#define DCMI_ESCR_LSC_0 (0x01U << DCMI_ESCR_LSC_Pos) /*!< 0x00000100 */
+#define DCMI_ESCR_LSC_1 (0x02U << DCMI_ESCR_LSC_Pos) /*!< 0x00000200 */
+#define DCMI_ESCR_LSC_2 (0x04U << DCMI_ESCR_LSC_Pos) /*!< 0x00000400 */
+#define DCMI_ESCR_LSC_3 (0x08U << DCMI_ESCR_LSC_Pos) /*!< 0x00000800 */
+#define DCMI_ESCR_LSC_4 (0x10U << DCMI_ESCR_LSC_Pos) /*!< 0x00001000 */
+#define DCMI_ESCR_LSC_5 (0x20U << DCMI_ESCR_LSC_Pos) /*!< 0x00002000 */
+#define DCMI_ESCR_LSC_6 (0x40U << DCMI_ESCR_LSC_Pos) /*!< 0x00004000 */
+#define DCMI_ESCR_LSC_7 (0x80U << DCMI_ESCR_LSC_Pos) /*!< 0x00008000 */
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk /*!< DCMI Line end delimiter code LEC[7:0] */
+#define DCMI_ESCR_LEC_0 (0x01U << DCMI_ESCR_LEC_Pos) /*!< 0x00010000 */
+#define DCMI_ESCR_LEC_1 (0x02U << DCMI_ESCR_LEC_Pos) /*!< 0x00020000 */
+#define DCMI_ESCR_LEC_2 (0x04U << DCMI_ESCR_LEC_Pos) /*!< 0x00040000 */
+#define DCMI_ESCR_LEC_3 (0x08U << DCMI_ESCR_LEC_Pos) /*!< 0x00080000 */
+#define DCMI_ESCR_LEC_4 (0x10U << DCMI_ESCR_LEC_Pos) /*!< 0x00100000 */
+#define DCMI_ESCR_LEC_5 (0x20U << DCMI_ESCR_LEC_Pos) /*!< 0x00200000 */
+#define DCMI_ESCR_LEC_6 (0x40U << DCMI_ESCR_LEC_Pos) /*!< 0x00400000 */
+#define DCMI_ESCR_LEC_7 (0x80U << DCMI_ESCR_LEC_Pos) /*!< 0x00800000 */
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /*!< DCMI Frame end delimiter code FEC[7:0] */
+#define DCMI_ESCR_FEC_0 (0x01U << DCMI_ESCR_FEC_Pos) /*!< 0x01000000 */
+#define DCMI_ESCR_FEC_1 (0x02U << DCMI_ESCR_FEC_Pos) /*!< 0x02000000 */
+#define DCMI_ESCR_FEC_2 (0x04U << DCMI_ESCR_FEC_Pos) /*!< 0x04000000 */
+#define DCMI_ESCR_FEC_3 (0x08U << DCMI_ESCR_FEC_Pos) /*!< 0x08000000 */
+#define DCMI_ESCR_FEC_4 (0x10U << DCMI_ESCR_FEC_Pos) /*!< 0x10000000 */
+#define DCMI_ESCR_FEC_5 (0x20U << DCMI_ESCR_FEC_Pos) /*!< 0x20000000 */
+#define DCMI_ESCR_FEC_6 (0x40U << DCMI_ESCR_FEC_Pos) /*!< 0x40000000 */
+#define DCMI_ESCR_FEC_7 (0x80U << DCMI_ESCR_FEC_Pos) /*!< 0x80000000 */
+
+/******************** Bits definition for DCMI_ESUR register ****************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk /*!< DCMI Frame start delimiter unmask FSU[7:0] */
+#define DCMI_ESUR_FSU_0 (0x01U << DCMI_ESUR_FSU_Pos) /*!< 0x00000001 */
+#define DCMI_ESUR_FSU_1 (0x02U << DCMI_ESUR_FSU_Pos) /*!< 0x00000002 */
+#define DCMI_ESUR_FSU_2 (0x04U << DCMI_ESUR_FSU_Pos) /*!< 0x00000004 */
+#define DCMI_ESUR_FSU_3 (0x08U << DCMI_ESUR_FSU_Pos) /*!< 0x00000008 */
+#define DCMI_ESUR_FSU_4 (0x10U << DCMI_ESUR_FSU_Pos) /*!< 0x00000010 */
+#define DCMI_ESUR_FSU_5 (0x20U << DCMI_ESUR_FSU_Pos) /*!< 0x00000020 */
+#define DCMI_ESUR_FSU_6 (0x40U << DCMI_ESUR_FSU_Pos) /*!< 0x00000040 */
+#define DCMI_ESUR_FSU_7 (0x80U << DCMI_ESUR_FSU_Pos) /*!< 0x00000080 */
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk /*!< DCMI Line start delimiter unmask LSU[7:0] */
+#define DCMI_ESUR_LSU_0 (0x01U << DCMI_ESUR_LSU_Pos) /*!< 0x00000100 */
+#define DCMI_ESUR_LSU_1 (0x02U << DCMI_ESUR_LSU_Pos) /*!< 0x00000200 */
+#define DCMI_ESUR_LSU_2 (0x04U << DCMI_ESUR_LSU_Pos) /*!< 0x00000400 */
+#define DCMI_ESUR_LSU_3 (0x08U << DCMI_ESUR_LSU_Pos) /*!< 0x00000800 */
+#define DCMI_ESUR_LSU_4 (0x10U << DCMI_ESUR_LSU_Pos) /*!< 0x00001000 */
+#define DCMI_ESUR_LSU_5 (0x20U << DCMI_ESUR_LSU_Pos) /*!< 0x00002000 */
+#define DCMI_ESUR_LSU_6 (0x40U << DCMI_ESUR_LSU_Pos) /*!< 0x00004000 */
+#define DCMI_ESUR_LSU_7 (0x80U << DCMI_ESUR_LSU_Pos) /*!< 0x00008000 */
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk /*!< DCMI Line end delimiter unmask LEU[7:0] */
+#define DCMI_ESUR_LEU_0 (0x01U << DCMI_ESUR_LEU_Pos) /*!< 0x00010000 */
+#define DCMI_ESUR_LEU_1 (0x02U << DCMI_ESUR_LEU_Pos) /*!< 0x00020000 */
+#define DCMI_ESUR_LEU_2 (0x04U << DCMI_ESUR_LEU_Pos) /*!< 0x00040000 */
+#define DCMI_ESUR_LEU_3 (0x08U << DCMI_ESUR_LEU_Pos) /*!< 0x00080000 */
+#define DCMI_ESUR_LEU_4 (0x10U << DCMI_ESUR_LEU_Pos) /*!< 0x00100000 */
+#define DCMI_ESUR_LEU_5 (0x20U << DCMI_ESUR_LEU_Pos) /*!< 0x00200000 */
+#define DCMI_ESUR_LEU_6 (0x40U << DCMI_ESUR_LEU_Pos) /*!< 0x00400000 */
+#define DCMI_ESUR_LEU_7 (0x80U << DCMI_ESUR_LEU_Pos) /*!< 0x00800000 */
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /*!< DCMI Frame end delimiter unmask FEU[7:0] */
+#define DCMI_ESUR_FEU_0 (0x01U << DCMI_ESUR_FEU_Pos) /*!< 0x01000000 */
+#define DCMI_ESUR_FEU_1 (0x02U << DCMI_ESUR_FEU_Pos) /*!< 0x02000000 */
+#define DCMI_ESUR_FEU_2 (0x04U << DCMI_ESUR_FEU_Pos) /*!< 0x04000000 */
+#define DCMI_ESUR_FEU_3 (0x08U << DCMI_ESUR_FEU_Pos) /*!< 0x08000000 */
+#define DCMI_ESUR_FEU_4 (0x10U << DCMI_ESUR_FEU_Pos) /*!< 0x10000000 */
+#define DCMI_ESUR_FEU_5 (0x20U << DCMI_ESUR_FEU_Pos) /*!< 0x20000000 */
+#define DCMI_ESUR_FEU_6 (0x40U << DCMI_ESUR_FEU_Pos) /*!< 0x40000000 */
+#define DCMI_ESUR_FEU_7 (0x80U << DCMI_ESUR_FEU_Pos) /*!< 0x80000000 */
+
+/******************** Bits definition for DCMI_CWSTRT register **************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk /*!< DCMI Horizontal offset count HOFFCNT[13:0] */
+#define DCMI_CWSTRT_HOFFCNT_0 (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000001 */
+#define DCMI_CWSTRT_HOFFCNT_1 (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000002 */
+#define DCMI_CWSTRT_HOFFCNT_2 (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000004 */
+#define DCMI_CWSTRT_HOFFCNT_3 (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000008 */
+#define DCMI_CWSTRT_HOFFCNT_4 (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000010 */
+#define DCMI_CWSTRT_HOFFCNT_5 (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000020 */
+#define DCMI_CWSTRT_HOFFCNT_6 (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000040 */
+#define DCMI_CWSTRT_HOFFCNT_7 (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000080 */
+#define DCMI_CWSTRT_HOFFCNT_8 (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000100 */
+#define DCMI_CWSTRT_HOFFCNT_9 (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000200 */
+#define DCMI_CWSTRT_HOFFCNT_10 (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000400 */
+#define DCMI_CWSTRT_HOFFCNT_11 (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000800 */
+#define DCMI_CWSTRT_HOFFCNT_12 (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00001000 */
+#define DCMI_CWSTRT_HOFFCNT_13 (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00002000 */
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /*!< DCMI Vertical start line count VST[12:0] */
+#define DCMI_CWSTRT_VST_0 (0x0001U << DCMI_CWSTRT_VST_Pos) /*!< 0x00010000 */
+#define DCMI_CWSTRT_VST_1 (0x0002U << DCMI_CWSTRT_VST_Pos) /*!< 0x00020000 */
+#define DCMI_CWSTRT_VST_2 (0x0004U << DCMI_CWSTRT_VST_Pos) /*!< 0x00040000 */
+#define DCMI_CWSTRT_VST_3 (0x0008U << DCMI_CWSTRT_VST_Pos) /*!< 0x00080000 */
+#define DCMI_CWSTRT_VST_4 (0x0010U << DCMI_CWSTRT_VST_Pos) /*!< 0x00100000 */
+#define DCMI_CWSTRT_VST_5 (0x0020U << DCMI_CWSTRT_VST_Pos) /*!< 0x00200000 */
+#define DCMI_CWSTRT_VST_6 (0x0040U << DCMI_CWSTRT_VST_Pos) /*!< 0x00400000 */
+#define DCMI_CWSTRT_VST_7 (0x0080U << DCMI_CWSTRT_VST_Pos) /*!< 0x00800000 */
+#define DCMI_CWSTRT_VST_8 (0x0100U << DCMI_CWSTRT_VST_Pos) /*!< 0x01000000 */
+#define DCMI_CWSTRT_VST_9 (0x0200U << DCMI_CWSTRT_VST_Pos) /*!< 0x02000000 */
+#define DCMI_CWSTRT_VST_10 (0x0400U << DCMI_CWSTRT_VST_Pos) /*!< 0x04000000 */
+#define DCMI_CWSTRT_VST_11 (0x0800U << DCMI_CWSTRT_VST_Pos) /*!< 0x08000000 */
+#define DCMI_CWSTRT_VST_12 (0x1000U << DCMI_CWSTRT_VST_Pos) /*!< 0x10000000 */
+
+/******************** Bits definition for DCMI_CWSIZE register **************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk /*!< DCMI Capture count CAPCNT[13:0] */
+#define DCMI_CWSIZE_CAPCNT_0 (0x0001U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000001 */
+#define DCMI_CWSIZE_CAPCNT_1 (0x0002U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000002 */
+#define DCMI_CWSIZE_CAPCNT_2 (0x0004U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000004 */
+#define DCMI_CWSIZE_CAPCNT_3 (0x0008U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000008 */
+#define DCMI_CWSIZE_CAPCNT_4 (0x0010U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000010 */
+#define DCMI_CWSIZE_CAPCNT_5 (0x0020U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000020 */
+#define DCMI_CWSIZE_CAPCNT_6 (0x0040U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000040 */
+#define DCMI_CWSIZE_CAPCNT_7 (0x0080U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000080 */
+#define DCMI_CWSIZE_CAPCNT_8 (0x0100U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000100 */
+#define DCMI_CWSIZE_CAPCNT_9 (0x0200U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000200 */
+#define DCMI_CWSIZE_CAPCNT_10 (0x0400U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000400 */
+#define DCMI_CWSIZE_CAPCNT_11 (0x0800U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000800 */
+#define DCMI_CWSIZE_CAPCNT_12 (0x1000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00001000 */
+#define DCMI_CWSIZE_CAPCNT_13 (0x2000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00002000 */
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /*!< DCMI Vertical line count VLINE[13:0] */
+#define DCMI_CWSIZE_VLINE_0 (0x0001U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00010000 */
+#define DCMI_CWSIZE_VLINE_1 (0x0002U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00020000 */
+#define DCMI_CWSIZE_VLINE_2 (0x0004U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00040000 */
+#define DCMI_CWSIZE_VLINE_3 (0x0008U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00080000 */
+#define DCMI_CWSIZE_VLINE_4 (0x0010U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00100000 */
+#define DCMI_CWSIZE_VLINE_5 (0x0020U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00200000 */
+#define DCMI_CWSIZE_VLINE_6 (0x0040U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00400000 */
+#define DCMI_CWSIZE_VLINE_7 (0x0080U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00800000 */
+#define DCMI_CWSIZE_VLINE_8 (0x0100U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x01000000 */
+#define DCMI_CWSIZE_VLINE_9 (0x0200U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x02000000 */
+#define DCMI_CWSIZE_VLINE_10 (0x0400U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x04000000 */
+#define DCMI_CWSIZE_VLINE_11 (0x0800U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x08000000 */
+#define DCMI_CWSIZE_VLINE_12 (0x1000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x10000000 */
+#define DCMI_CWSIZE_VLINE_13 (0x2000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x20000000 */
+
+/******************** Bits definition for DCMI_DR register **************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk /*!< DCMI Data byte 0 Byte0[7:0] */
+#define DCMI_DR_BYTE0_0 (0x01U << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
+#define DCMI_DR_BYTE0_1 (0x02U << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
+#define DCMI_DR_BYTE0_2 (0x04U << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
+#define DCMI_DR_BYTE0_3 (0x08U << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
+#define DCMI_DR_BYTE0_4 (0x10U << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
+#define DCMI_DR_BYTE0_5 (0x20U << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
+#define DCMI_DR_BYTE0_6 (0x40U << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
+#define DCMI_DR_BYTE0_7 (0x80U << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk /*!< DCMI Data byte 1 Byte1[7:0] */
+#define DCMI_DR_BYTE1_0 (0x01U << DCMI_DR_BYTE1_Pos) /*!< 0x00000100 */
+#define DCMI_DR_BYTE1_1 (0x02U << DCMI_DR_BYTE1_Pos) /*!< 0x00000200 */
+#define DCMI_DR_BYTE1_2 (0x04U << DCMI_DR_BYTE1_Pos) /*!< 0x00000400 */
+#define DCMI_DR_BYTE1_3 (0x08U << DCMI_DR_BYTE1_Pos) /*!< 0x00000800 */
+#define DCMI_DR_BYTE1_4 (0x10U << DCMI_DR_BYTE1_Pos) /*!< 0x00001000 */
+#define DCMI_DR_BYTE1_5 (0x20U << DCMI_DR_BYTE1_Pos) /*!< 0x00002000 */
+#define DCMI_DR_BYTE1_6 (0x40U << DCMI_DR_BYTE1_Pos) /*!< 0x00004000 */
+#define DCMI_DR_BYTE1_7 (0x80U << DCMI_DR_BYTE1_Pos) /*!< 0x00008000 */
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk /*!< DCMI Data byte 2 Byte2[7:0] */
+#define DCMI_DR_BYTE2_0 (0x01U << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
+#define DCMI_DR_BYTE2_1 (0x02U << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
+#define DCMI_DR_BYTE2_2 (0x04U << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
+#define DCMI_DR_BYTE2_3 (0x08U << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
+#define DCMI_DR_BYTE2_4 (0x10U << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
+#define DCMI_DR_BYTE2_5 (0x20U << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
+#define DCMI_DR_BYTE2_6 (0x40U << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
+#define DCMI_DR_BYTE2_7 (0x80U << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /*!< DCMI Data byte 3 Byte3[7:0] */
+#define DCMI_DR_BYTE3_0 (0x01U << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
+#define DCMI_DR_BYTE3_1 (0x02U << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
+#define DCMI_DR_BYTE3_2 (0x04U << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
+#define DCMI_DR_BYTE3_3 (0x08U << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
+#define DCMI_DR_BYTE3_4 (0x10U << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
+#define DCMI_DR_BYTE3_5 (0x20U << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
+#define DCMI_DR_BYTE3_6 (0x40U << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
+#define DCMI_DR_BYTE3_7 (0x80U << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos (0U)
+#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos (0U)
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
+
+/**************** Bit definition for DFSDM_CHDLYR register *******************/
+#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
+#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FU << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
+#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos (29U)
+#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos (24U)
+#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos (18U)
+#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
+#define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos (0U)
+#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos (8U)
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos (24U)
+#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos (16U)
+#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos (14U)
+#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos (13U)
+#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos (4U)
+#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos (3U)
+#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos (2U)
+#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos (1U)
+#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos (0U)
+#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
+#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos (29U)
+#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos (16U)
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos (0U)
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+
+/******************************************************************************/
+/* */
+/* DMAMUX Controller */
+/* */
+/******************************************************************************/
+
+/******************** Bits definition for DMAMUX_CxCR register **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
+
+#define DMAMUX_CxCR_SOIE_Pos (8U)
+#define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
+
+#define DMAMUX_CxCR_EGE_Pos (9U)
+#define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
+
+#define DMAMUX_CxCR_SE_Pos (16U)
+#define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
+
+#define DMAMUX_CxCR_SPOL_Pos (17U)
+#define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
+#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
+
+#define DMAMUX_CxCR_NBREQ_Pos (19U)
+#define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
+#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
+
+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
+#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
+
+/******************** Bits definition for DMAMUX_CSR register ****************/
+#define DMAMUX_CSR_SOF0_Pos (0U)
+#define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
+#define DMAMUX_CSR_SOF1_Pos (1U)
+#define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
+#define DMAMUX_CSR_SOF2_Pos (2U)
+#define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
+#define DMAMUX_CSR_SOF3_Pos (3U)
+#define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
+#define DMAMUX_CSR_SOF4_Pos (4U)
+#define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
+#define DMAMUX_CSR_SOF5_Pos (5U)
+#define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
+#define DMAMUX_CSR_SOF6_Pos (6U)
+#define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
+#define DMAMUX_CSR_SOF7_Pos (7U)
+#define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
+#define DMAMUX_CSR_SOF8_Pos (8U)
+#define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
+#define DMAMUX_CSR_SOF9_Pos (9U)
+#define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
+#define DMAMUX_CSR_SOF10_Pos (10U)
+#define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
+#define DMAMUX_CSR_SOF11_Pos (11U)
+#define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
+#define DMAMUX_CSR_SOF12_Pos (12U)
+#define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
+#define DMAMUX_CSR_SOF13_Pos (13U)
+#define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
+
+/******************** Bits definition for DMAMUX_CFR register ****************/
+
+#define DMAMUX_CFR_CSOF0_Pos (0U)
+#define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
+#define DMAMUX_CFR_CSOF1_Pos (1U)
+#define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
+#define DMAMUX_CFR_CSOF2_Pos (2U)
+#define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
+#define DMAMUX_CFR_CSOF3_Pos (3U)
+#define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
+#define DMAMUX_CFR_CSOF4_Pos (4U)
+#define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
+#define DMAMUX_CFR_CSOF5_Pos (5U)
+#define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
+#define DMAMUX_CFR_CSOF6_Pos (6U)
+#define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
+#define DMAMUX_CFR_CSOF7_Pos (7U)
+#define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
+#define DMAMUX_CFR_CSOF8_Pos (8U)
+#define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
+#define DMAMUX_CFR_CSOF9_Pos (9U)
+#define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
+#define DMAMUX_CFR_CSOF10_Pos (10U)
+#define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
+#define DMAMUX_CFR_CSOF11_Pos (11U)
+#define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
+#define DMAMUX_CFR_CSOF12_Pos (12U)
+#define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
+#define DMAMUX_CFR_CSOF13_Pos (13U)
+#define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
+
+/******************** Bits definition for DMAMUX_RGxCR register ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
+#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
+
+#define DMAMUX_RGxCR_OIE_Pos (8U)
+#define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
+
+#define DMAMUX_RGxCR_GE_Pos (16U)
+#define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
+
+#define DMAMUX_RGxCR_GPOL_Pos (17U)
+#define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
+#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
+
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
+#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
+
+/******************** Bits definition for DMAMUX_RGSR register **************/
+#define DMAMUX_RGSR_OF0_Pos (0U)
+#define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
+#define DMAMUX_RGSR_OF1_Pos (1U)
+#define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
+#define DMAMUX_RGSR_OF2_Pos (2U)
+#define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
+#define DMAMUX_RGSR_OF3_Pos (3U)
+#define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
+
+/******************** Bits definition for DMAMUX_RGCFR register ************/
+#define DMAMUX_RGCFR_COF0_Pos (0U)
+#define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
+#define DMAMUX_RGCFR_COF1_Pos (1U)
+#define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
+#define DMAMUX_RGCFR_COF2_Pos (2U)
+#define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
+#define DMAMUX_RGCFR_COF3_Pos (3U)
+#define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define DMA2D_LINE_OFFSET_MODE_SUPPORT
+#define DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT
+#define DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_Pos (0U)
+#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos (1U)
+#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos (2U)
+#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
+#define DMA2D_CR_LOM_Pos (6U)
+#define DMA2D_CR_LOM_Msk (0x1U << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
+#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
+#define DMA2D_CR_TEIE_Pos (8U)
+#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos (9U)
+#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos (10U)
+#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos (11U)
+#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos (12U)
+#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos (13U)
+#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos (16U)
+#define DMA2D_CR_MODE_Msk (0x7U << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
+#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2 (0x4U << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_Pos (0U)
+#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos (1U)
+#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos (2U)
+#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos (3U)
+#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos (4U)
+#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos (5U)
+#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos (0U)
+#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos (1U)
+#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos (2U)
+#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos (3U)
+#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
+#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos (5U)
+#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_Pos (0U)
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_Pos (0U)
+#define DMA2D_FGOR_LO_Msk (0xFFFFU << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_Pos (0U)
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_Pos (0U)
+#define DMA2D_BGOR_LO_Msk (0xFFFFU << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_Pos (0U)
+#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
+#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos (5U)
+#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos (8U)
+#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos (16U)
+#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_AI_Pos (20U)
+#define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos (21U)
+#define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos (16U)
+#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_Pos (0U)
+#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3 (0x8U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
+#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos (5U)
+#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos (8U)
+#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos (16U)
+#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos (20U)
+#define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos (21U)
+#define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos (0U)
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos (8U)
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos (16U)
+#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_Pos (0U)
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_Pos (0U)
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_Pos (0U)
+#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos (8U)
+#define DMA2D_OPFCCR_SB_Msk (0x1U << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos (20U)
+#define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos (21U)
+#define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Red Blue Swap */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 (0x000000FFU) /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1 (0x0000FF00U) /*!< Green Value */
+#define DMA2D_OCOLR_RED_1 (0x00FF0000U) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 (0xFF000000U) /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 (0x0000001FU) /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2 (0x000007E0U) /*!< Green Value */
+#define DMA2D_OCOLR_RED_2 (0x0000F800U) /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 (0x0000001FU) /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3 (0x000003E0U) /*!< Green Value */
+#define DMA2D_OCOLR_RED_3 (0x00007C00U) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 (0x00008000U) /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 (0x0000000FU) /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4 (0x000000F0U) /*!< Green Value */
+#define DMA2D_OCOLR_RED_4 (0x00000F00U) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 (0x0000F000U) /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_Pos (0U)
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_Pos (0U)
+#define DMA2D_OOR_LO_Msk (0xFFFFU << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_Pos (0U)
+#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos (16U)
+#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_Pos (0U)
+#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_Pos (0U)
+#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos (8U)
+#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR1 register ******************/
+#define EXTI_IMR1_IM0_Pos (0U)
+#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos (1U)
+#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos (2U)
+#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos (3U)
+#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos (4U)
+#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos (5U)
+#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos (6U)
+#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos (7U)
+#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos (8U)
+#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos (9U)
+#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos (10U)
+#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos (11U)
+#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos (12U)
+#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos (13U)
+#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos (14U)
+#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos (15U)
+#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos (16U)
+#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos (17U)
+#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos (18U)
+#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos (19U)
+#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos (20U)
+#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos (21U)
+#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos (22U)
+#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos (23U)
+#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos (24U)
+#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos (25U)
+#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos (26U)
+#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos (27U)
+#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
+#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos (28U)
+#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos (29U)
+#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos (30U)
+#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos (31U)
+#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos (0U)
+#define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
+
+/******************* Bit definition for EXTI_EMR1 register ******************/
+#define EXTI_EMR1_EM0_Pos (0U)
+#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos (1U)
+#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos (2U)
+#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos (3U)
+#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos (4U)
+#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos (5U)
+#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos (6U)
+#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos (7U)
+#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos (8U)
+#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos (9U)
+#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos (10U)
+#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos (11U)
+#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos (12U)
+#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos (13U)
+#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos (14U)
+#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos (15U)
+#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos (16U)
+#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos (17U)
+#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos (18U)
+#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos (19U)
+#define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos (20U)
+#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos (21U)
+#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos (22U)
+#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos (23U)
+#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos (24U)
+#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos (25U)
+#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos (26U)
+#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos (27U)
+#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
+#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos (28U)
+#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos (29U)
+#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos (30U)
+#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
+#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos (31U)
+#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
+
+/****************** Bit definition for EXTI_RTSR1 register ******************/
+#define EXTI_RTSR1_RT0_Pos (0U)
+#define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos (1U)
+#define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos (2U)
+#define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos (3U)
+#define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos (4U)
+#define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos (5U)
+#define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos (6U)
+#define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos (7U)
+#define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos (8U)
+#define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos (9U)
+#define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos (10U)
+#define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos (11U)
+#define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos (12U)
+#define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos (13U)
+#define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos (14U)
+#define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos (15U)
+#define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos (16U)
+#define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos (18U)
+#define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos (19U)
+#define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos (20U)
+#define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos (21U)
+#define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos (22U)
+#define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR1 register ******************/
+#define EXTI_FTSR1_FT0_Pos (0U)
+#define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos (1U)
+#define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos (2U)
+#define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos (3U)
+#define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos (4U)
+#define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos (5U)
+#define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos (6U)
+#define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos (7U)
+#define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos (8U)
+#define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos (9U)
+#define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos (10U)
+#define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos (11U)
+#define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos (12U)
+#define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos (13U)
+#define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos (14U)
+#define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos (15U)
+#define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos (16U)
+#define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos (18U)
+#define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos (19U)
+#define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos (20U)
+#define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos (21U)
+#define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos (22U)
+#define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER1 register *****************/
+#define EXTI_SWIER1_SWI0_Pos (0U)
+#define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos (1U)
+#define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos (2U)
+#define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos (3U)
+#define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos (4U)
+#define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos (5U)
+#define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos (6U)
+#define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos (7U)
+#define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos (8U)
+#define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos (9U)
+#define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos (10U)
+#define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos (11U)
+#define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos (12U)
+#define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos (13U)
+#define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos (14U)
+#define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos (15U)
+#define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos (16U)
+#define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos (18U)
+#define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos (19U)
+#define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos (20U)
+#define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos (21U)
+#define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos (22U)
+#define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR1 register *******************/
+#define EXTI_PR1_PIF0_Pos (0U)
+#define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos (1U)
+#define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos (2U)
+#define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos (3U)
+#define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos (4U)
+#define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos (5U)
+#define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos (6U)
+#define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos (7U)
+#define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos (8U)
+#define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos (9U)
+#define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos (10U)
+#define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos (11U)
+#define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos (12U)
+#define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos (13U)
+#define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos (14U)
+#define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos (15U)
+#define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos (16U)
+#define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos (18U)
+#define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
+#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos (19U)
+#define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos (20U)
+#define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos (21U)
+#define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos (22U)
+#define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_IM32_Pos (0U)
+#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
+#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos (1U)
+#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
+#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM35_Pos (3U)
+#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
+#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos (4U)
+#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos (5U)
+#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos (6U)
+#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM40_Pos (8U)
+#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
+#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM_Pos (0U)
+#define EXTI_IMR2_IM_Msk (0x17BU << EXTI_IMR2_IM_Pos) /*!< 0x0000017B */
+#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
+
+/******************* Bit definition for EXTI_EMR2 register ******************/
+#define EXTI_EMR2_EM32_Pos (0U)
+#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
+#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos (1U)
+#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
+#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM35_Pos (3U)
+#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
+#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos (4U)
+#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
+#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos (5U)
+#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
+#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos (6U)
+#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
+#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM40_Pos (8U)
+#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
+#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM_Pos (0U)
+#define EXTI_EMR2_EM_Msk (0x17BU << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */
+#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
+
+/****************** Bit definition for EXTI_RTSR2 register ******************/
+#define EXTI_RTSR2_RT35_Pos (3U)
+#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos (4U)
+#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos (5U)
+#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos (6U)
+#define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_FT35_Pos (3U)
+#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos (4U)
+#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos (5U)
+#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos (6U)
+#define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWI35_Pos (3U)
+#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos (4U)
+#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos (5U)
+#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos (6U)
+#define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PIF35_Pos (3U)
+#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
+#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos (4U)
+#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
+#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos (5U)
+#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
+#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos (6U)
+#define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
+#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS (0x00000004U)
+#define FLASH_ACR_LATENCY_5WS (0x00000005U)
+#define FLASH_ACR_LATENCY_6WS (0x00000006U)
+#define FLASH_ACR_LATENCY_7WS (0x00000007U)
+#define FLASH_ACR_LATENCY_8WS (0x00000008U)
+#define FLASH_ACR_LATENCY_9WS (0x00000009U)
+#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
+#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
+#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
+#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
+#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
+#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
+#define FLASH_ACR_PRFTEN_Pos (8U)
+#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
+#define FLASH_ACR_ICEN_Pos (9U)
+#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
+#define FLASH_ACR_DCEN_Pos (10U)
+#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
+#define FLASH_ACR_ICRST_Pos (11U)
+#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
+#define FLASH_ACR_DCRST_Pos (12U)
+#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
+#define FLASH_ACR_RUN_PD_Pos (13U)
+#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos (14U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP_Pos (0U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
+#define FLASH_SR_OPERR_Pos (1U)
+#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
+#define FLASH_SR_PROGERR_Pos (3U)
+#define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
+#define FLASH_SR_WRPERR_Pos (4U)
+#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
+#define FLASH_SR_PGAERR_Pos (5U)
+#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
+#define FLASH_SR_SIZERR_Pos (6U)
+#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
+#define FLASH_SR_PGSERR_Pos (7U)
+#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
+#define FLASH_SR_MISERR_Pos (8U)
+#define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
+#define FLASH_SR_FASTERR_Pos (9U)
+#define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
+#define FLASH_SR_RDERR_Pos (14U)
+#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
+#define FLASH_SR_OPTVERR_Pos (15U)
+#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
+#define FLASH_SR_BSY_Pos (16U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
+#define FLASH_SR_PEMPTY_Pos (17U)
+#define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
+#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk
+#define FLASH_CR_MER1_Pos (2U)
+#define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
+#define FLASH_CR_PNB_Pos (3U)
+#define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
+#define FLASH_CR_PNB FLASH_CR_PNB_Msk
+#define FLASH_CR_BKER_Pos (11U)
+#define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
+#define FLASH_CR_BKER FLASH_CR_BKER_Msk
+#define FLASH_CR_MER2_Pos (15U)
+#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
+#define FLASH_CR_STRT_Pos (16U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
+#define FLASH_CR_OPTSTRT_Pos (17U)
+#define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
+#define FLASH_CR_FSTPG_Pos (18U)
+#define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
+#define FLASH_CR_EOPIE_Pos (24U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
+#define FLASH_CR_ERRIE_Pos (25U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
+#define FLASH_CR_RDERRIE_Pos (26U)
+#define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
+#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
+#define FLASH_CR_OPTLOCK_Pos (30U)
+#define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
+#define FLASH_CR_LOCK_Pos (31U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
+
+/******************* Bits definition for FLASH_ECCR register ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
+#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
+#define FLASH_ECCR_BK_ECC_Pos (21U)
+#define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
+#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
+#define FLASH_ECCR_SYSF_ECC_Pos (22U)
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
+#define FLASH_ECCR_ECCIE_Pos (24U)
+#define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
+#define FLASH_ECCR_ECCC2_Pos (28U)
+#define FLASH_ECCR_ECCC2_Msk (0x1U << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
+#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
+#define FLASH_ECCR_ECCD2_Pos (29U)
+#define FLASH_ECCR_ECCD2_Msk (0x1U << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
+#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
+#define FLASH_ECCR_ECCC_Pos (30U)
+#define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
+#define FLASH_ECCR_ECCD_Pos (31U)
+#define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
+
+/******************* Bits definition for FLASH_OPTR register ***************/
+#define FLASH_OPTR_RDP_Pos (0U)
+#define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
+#define FLASH_OPTR_BOR_LEV_Pos (8U)
+#define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
+#define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos (12U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
+#define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
+#define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
+#define FLASH_OPTR_BFB2_Pos (20U)
+#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
+#define FLASH_OPTR_DB1M_Pos (21U)
+#define FLASH_OPTR_DB1M_Msk (0x1U << FLASH_OPTR_DB1M_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_DB1M FLASH_OPTR_DB1M_Msk
+#define FLASH_OPTR_DBANK_Pos (22U)
+#define FLASH_OPTR_DBANK_Msk (0x1U << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
+#define FLASH_OPTR_nBOOT1_Pos (23U)
+#define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
+#define FLASH_OPTR_SRAM2_PE_Pos (24U)
+#define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
+#define FLASH_OPTR_SRAM2_RST_Pos (25U)
+#define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
+#define FLASH_OPTR_nSWBOOT0_Pos (26U)
+#define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
+#define FLASH_OPTR_nBOOT0_Pos (27U)
+#define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
+
+/****************** Bits definition for FLASH_PCROP1SR register **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x1FFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0001FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
+
+/****************** Bits definition for FLASH_PCROP1ER register ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
+#define FLASH_PCROP1ER_PCROP1_END_Msk (0x1FFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0001FFFF */
+#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
+#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
+#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
+
+/****************** Bits definition for FLASH_WRP1AR register ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
+#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
+
+/****************** Bits definition for FLASH_WRPB1R register ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
+#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
+
+/****************** Bits definition for FLASH_PCROP2SR register **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x1FFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0001FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
+
+/****************** Bits definition for FLASH_PCROP2ER register ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
+#define FLASH_PCROP2ER_PCROP2_END_Msk (0x1FFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0001FFFF */
+#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
+
+/****************** Bits definition for FLASH_WRP2AR register ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
+#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
+#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
+#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
+
+/****************** Bits definition for FLASH_WRP2BR register ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
+#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
+#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
+#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
+
+/****************** Bits definition for FLASH_CFGR register *****************/
+#define FLASH_CFGR_LVEN_Pos (0U)
+#define FLASH_CFGR_LVEN_Msk (0x1U << FLASH_CFGR_LVEN_Pos) /*!< 0x00000001 */
+#define FLASH_CFGR_LVEN FLASH_CFGR_LVEN_Msk /*!< Flash low voltage enable */
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS_Pos (21U)
+#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
+#define FMC_BCRx_MBKEN_Pos (0U)
+#define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos (1U)
+#define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCRx_MTYP_Pos (2U)
+#define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos (4U)
+#define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos (6U)
+#define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos (8U)
+#define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos (9U)
+#define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos (11U)
+#define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCRx_WREN_Pos (12U)
+#define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
+#define FMC_BCRx_WAITEN_Pos (13U)
+#define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos (14U)
+#define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCRx_CPSIZE_Pos (16U)
+#define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
+#define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos (19U)
+#define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
+
+#define FMC_BCRx_NBLSET_Pos (22U)
+#define FMC_BCRx_NBLSET_Msk (0x3U << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
+#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
+#define FMC_BCRx_NBLSET_0 (0x1U << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
+#define FMC_BCRx_NBLSET_1 (0x2U << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
+#define FMC_BTRx_ADDSET_Pos (0U)
+#define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos (4U)
+#define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos (8U)
+#define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos (16U)
+#define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos (20U)
+#define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos (24U)
+#define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos (28U)
+#define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BTRx_DATAHLD_Pos (30U)
+#define FMC_BTRx_DATAHLD_Msk (0x3U << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
+#define FMC_BTRx_DATAHLD_0 (0x1U << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BTRx_DATAHLD_1 (0x2U << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
+#define FMC_BWTRx_ADDSET_Pos (0U)
+#define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos (4U)
+#define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos (8U)
+#define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos (16U)
+#define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos (28U)
+#define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BWTRx_DATAHLD_Pos (30U)
+#define FMC_BWTRx_DATAHLD_Msk (0x3U << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
+#define FMC_BWTRx_DATAHLD_0 (0x1U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BWTRx_DATAHLD_1 (0x2U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PCR register ********************/
+#define FMC_PCR_PWAITEN_Pos (1U)
+#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos (2U)
+#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos (3U)
+#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
+
+#define FMC_PCR_PWID_Pos (4U)
+#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos (6U)
+#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR_Pos (9U)
+#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos (13U)
+#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos (17U)
+#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FMC_SR register ********************/
+#define FMC_SR_IRS_Pos (0U)
+#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS_Pos (1U)
+#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
+#define FMC_SR_IFS_Pos (2U)
+#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN_Pos (3U)
+#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN_Pos (4U)
+#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN_Pos (5U)
+#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos (6U)
+#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET_Pos (0U)
+#define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos (8U)
+#define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos (16U)
+#define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos (24U)
+#define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT register *******************/
+#define FMC_PATT_ATTSET_Pos (0U)
+#define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
+#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos (8U)
+#define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos (16U)
+#define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos (24U)
+#define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_ECCR register *******************/
+#define FMC_ECCR_ECC_Pos (0U)
+#define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0 GPIO_BRR_BR0
+#define GPIO_BRR_BR_1 GPIO_BRR_BR1
+#define GPIO_BRR_BR_2 GPIO_BRR_BR2
+#define GPIO_BRR_BR_3 GPIO_BRR_BR3
+#define GPIO_BRR_BR_4 GPIO_BRR_BR4
+#define GPIO_BRR_BR_5 GPIO_BRR_BR5
+#define GPIO_BRR_BR_6 GPIO_BRR_BR6
+#define GPIO_BRR_BR_7 GPIO_BRR_BR7
+#define GPIO_BRR_BR_8 GPIO_BRR_BR8
+#define GPIO_BRR_BR_9 GPIO_BRR_BR9
+#define GPIO_BRR_BR_10 GPIO_BRR_BR10
+#define GPIO_BRR_BR_11 GPIO_BRR_BR11
+#define GPIO_BRR_BR_12 GPIO_BRR_BR12
+#define GPIO_BRR_BR_13 GPIO_BRR_BR13
+#define GPIO_BRR_BR_14 GPIO_BRR_BR14
+#define GPIO_BRR_BR_15 GPIO_BRR_BR15
+
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos (13U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0xFFFU << FW_VDSSA_ADD_Pos) /*!< 0x0003FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0xFFFU << FW_VDSL_LENG_Pos) /*!< 0x0003FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR1 register ********************/
+
+#define PWR_CR1_LPR_Pos (14U)
+#define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
+#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos (9U)
+#define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
+#define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos (8U)
+#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
+#define PWR_CR1_RRSTP_Pos (4U)
+#define PWR_CR1_RRSTP_Msk (0x1U << PWR_CR1_RRSTP_Pos) /*!< 0x00000010 */
+#define PWR_CR1_RRSTP PWR_CR1_RRSTP_Msk /*!< SRAM3 Retention in Stop 2 mode */
+#define PWR_CR1_LPMS_Pos (0U)
+#define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
+#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos (0U)
+#define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos (1U)
+#define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos (0U)
+#define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
+#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
+
+
+/******************** Bit definition for PWR_CR2 register ********************/
+#define PWR_CR2_USV_Pos (10U)
+#define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
+#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos (9U)
+#define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
+#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos (4U)
+#define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
+#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos (7U)
+#define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
+#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos (6U)
+#define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
+#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos (5U)
+#define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
+#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos (4U)
+#define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
+#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos (1U)
+#define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
+#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos (1U)
+#define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos (2U)
+#define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos (1U)
+#define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos (3U)
+#define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos (1U)
+#define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos (2U)
+#define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos (1U)
+#define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos (0U)
+#define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
+#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+/******************** Bit definition for PWR_CR3 register ********************/
+#define PWR_CR3_EIWUL_Pos (15U)
+#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
+#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
+#define PWR_CR3_DSIPDEN_Pos (12U)
+#define PWR_CR3_DSIPDEN_Msk (0x1U << PWR_CR3_DSIPDEN_Pos) /*!< 0x00001000 */
+#define PWR_CR3_DSIPDEN PWR_CR3_DSIPDEN_Msk /*!< Disable DSI pads pull-down */
+#define PWR_CR3_APC_Pos (10U)
+#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
+#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos (8U)
+#define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
+#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos (4U)
+#define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
+#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos (3U)
+#define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
+#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos (2U)
+#define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
+#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos (1U)
+#define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
+#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos (0U)
+#define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
+#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos (0U)
+#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
+#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
+
+/* Legacy defines */
+#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
+#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
+#define PWR_CR3_EIWF PWR_CR3_EIWUL
+
+
+/******************** Bit definition for PWR_CR4 register ********************/
+#define PWR_CR4_VBRS_Pos (9U)
+#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
+#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos (8U)
+#define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
+#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
+#define PWR_CR4_WP5_Pos (4U)
+#define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
+#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos (3U)
+#define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
+#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos (2U)
+#define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
+#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos (1U)
+#define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
+#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos (0U)
+#define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
+#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
+
+/******************** Bit definition for PWR_SR1 register ********************/
+#define PWR_SR1_WUFI_Pos (15U)
+#define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
+#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos (8U)
+#define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
+#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos (0U)
+#define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
+#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos (4U)
+#define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
+#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos (3U)
+#define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
+#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos (2U)
+#define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
+#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos (1U)
+#define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
+#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos (0U)
+#define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
+#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
+
+/******************** Bit definition for PWR_SR2 register ********************/
+#define PWR_SR2_PVMO4_Pos (15U)
+#define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
+#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos (14U)
+#define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
+#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos (13U)
+#define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
+#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos (12U)
+#define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
+#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos (11U)
+#define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
+#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos (10U)
+#define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
+#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos (9U)
+#define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
+#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos (8U)
+#define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
+#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
+
+/******************** Bit definition for PWR_SCR register ********************/
+#define PWR_SCR_CSBF_Pos (8U)
+#define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
+#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos (0U)
+#define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
+#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
+#define PWR_SCR_CWUF5_Pos (4U)
+#define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
+#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos (3U)
+#define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
+#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos (2U)
+#define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
+#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos (1U)
+#define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
+#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos (0U)
+#define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
+#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
+
+/******************** Bit definition for PWR_PUCRA register ********************/
+#define PWR_PUCRA_PA15_Pos (15U)
+#define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos (13U)
+#define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos (12U)
+#define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos (11U)
+#define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos (10U)
+#define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos (9U)
+#define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
+#define PWR_PUCRA_PA8_Pos (8U)
+#define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
+#define PWR_PUCRA_PA7_Pos (7U)
+#define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
+#define PWR_PUCRA_PA6_Pos (6U)
+#define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
+#define PWR_PUCRA_PA5_Pos (5U)
+#define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
+#define PWR_PUCRA_PA4_Pos (4U)
+#define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
+#define PWR_PUCRA_PA3_Pos (3U)
+#define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
+#define PWR_PUCRA_PA2_Pos (2U)
+#define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
+#define PWR_PUCRA_PA1_Pos (1U)
+#define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
+#define PWR_PUCRA_PA0_Pos (0U)
+#define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRA register ********************/
+#define PWR_PDCRA_PA14_Pos (14U)
+#define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos (12U)
+#define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos (11U)
+#define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos (10U)
+#define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos (9U)
+#define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
+#define PWR_PDCRA_PA8_Pos (8U)
+#define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
+#define PWR_PDCRA_PA7_Pos (7U)
+#define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
+#define PWR_PDCRA_PA6_Pos (6U)
+#define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
+#define PWR_PDCRA_PA5_Pos (5U)
+#define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
+#define PWR_PDCRA_PA4_Pos (4U)
+#define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
+#define PWR_PDCRA_PA3_Pos (3U)
+#define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
+#define PWR_PDCRA_PA2_Pos (2U)
+#define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
+#define PWR_PDCRA_PA1_Pos (1U)
+#define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
+#define PWR_PDCRA_PA0_Pos (0U)
+#define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRB register ********************/
+#define PWR_PUCRB_PB15_Pos (15U)
+#define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos (14U)
+#define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos (13U)
+#define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos (12U)
+#define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos (11U)
+#define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos (10U)
+#define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos (9U)
+#define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
+#define PWR_PUCRB_PB8_Pos (8U)
+#define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
+#define PWR_PUCRB_PB7_Pos (7U)
+#define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
+#define PWR_PUCRB_PB6_Pos (6U)
+#define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
+#define PWR_PUCRB_PB5_Pos (5U)
+#define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
+#define PWR_PUCRB_PB4_Pos (4U)
+#define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
+#define PWR_PUCRB_PB3_Pos (3U)
+#define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
+#define PWR_PUCRB_PB2_Pos (2U)
+#define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
+#define PWR_PUCRB_PB1_Pos (1U)
+#define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
+#define PWR_PUCRB_PB0_Pos (0U)
+#define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRB register ********************/
+#define PWR_PDCRB_PB15_Pos (15U)
+#define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos (14U)
+#define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos (13U)
+#define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos (12U)
+#define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos (11U)
+#define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos (10U)
+#define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos (9U)
+#define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
+#define PWR_PDCRB_PB8_Pos (8U)
+#define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
+#define PWR_PDCRB_PB7_Pos (7U)
+#define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
+#define PWR_PDCRB_PB6_Pos (6U)
+#define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
+#define PWR_PDCRB_PB5_Pos (5U)
+#define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
+#define PWR_PDCRB_PB3_Pos (3U)
+#define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
+#define PWR_PDCRB_PB2_Pos (2U)
+#define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
+#define PWR_PDCRB_PB1_Pos (1U)
+#define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
+#define PWR_PDCRB_PB0_Pos (0U)
+#define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRC register ********************/
+#define PWR_PUCRC_PC15_Pos (15U)
+#define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos (14U)
+#define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos (13U)
+#define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos (12U)
+#define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos (11U)
+#define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos (10U)
+#define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos (9U)
+#define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
+#define PWR_PUCRC_PC8_Pos (8U)
+#define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
+#define PWR_PUCRC_PC7_Pos (7U)
+#define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
+#define PWR_PUCRC_PC6_Pos (6U)
+#define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
+#define PWR_PUCRC_PC5_Pos (5U)
+#define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
+#define PWR_PUCRC_PC4_Pos (4U)
+#define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
+#define PWR_PUCRC_PC3_Pos (3U)
+#define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
+#define PWR_PUCRC_PC2_Pos (2U)
+#define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
+#define PWR_PUCRC_PC1_Pos (1U)
+#define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
+#define PWR_PUCRC_PC0_Pos (0U)
+#define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRC register ********************/
+#define PWR_PDCRC_PC15_Pos (15U)
+#define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos (14U)
+#define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos (13U)
+#define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos (12U)
+#define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos (11U)
+#define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos (10U)
+#define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos (9U)
+#define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
+#define PWR_PDCRC_PC8_Pos (8U)
+#define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
+#define PWR_PDCRC_PC7_Pos (7U)
+#define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
+#define PWR_PDCRC_PC6_Pos (6U)
+#define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
+#define PWR_PDCRC_PC5_Pos (5U)
+#define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
+#define PWR_PDCRC_PC4_Pos (4U)
+#define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
+#define PWR_PDCRC_PC3_Pos (3U)
+#define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
+#define PWR_PDCRC_PC2_Pos (2U)
+#define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
+#define PWR_PDCRC_PC1_Pos (1U)
+#define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
+#define PWR_PDCRC_PC0_Pos (0U)
+#define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRD register ********************/
+#define PWR_PUCRD_PD15_Pos (15U)
+#define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos (14U)
+#define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos (13U)
+#define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos (12U)
+#define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos (11U)
+#define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos (10U)
+#define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos (9U)
+#define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
+#define PWR_PUCRD_PD8_Pos (8U)
+#define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
+#define PWR_PUCRD_PD7_Pos (7U)
+#define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
+#define PWR_PUCRD_PD6_Pos (6U)
+#define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
+#define PWR_PUCRD_PD5_Pos (5U)
+#define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
+#define PWR_PUCRD_PD4_Pos (4U)
+#define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
+#define PWR_PUCRD_PD3_Pos (3U)
+#define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
+#define PWR_PUCRD_PD2_Pos (2U)
+#define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
+#define PWR_PUCRD_PD1_Pos (1U)
+#define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
+#define PWR_PUCRD_PD0_Pos (0U)
+#define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRD register ********************/
+#define PWR_PDCRD_PD15_Pos (15U)
+#define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos (14U)
+#define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos (13U)
+#define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos (12U)
+#define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos (11U)
+#define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos (10U)
+#define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos (9U)
+#define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
+#define PWR_PDCRD_PD8_Pos (8U)
+#define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
+#define PWR_PDCRD_PD7_Pos (7U)
+#define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
+#define PWR_PDCRD_PD6_Pos (6U)
+#define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
+#define PWR_PDCRD_PD5_Pos (5U)
+#define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
+#define PWR_PDCRD_PD4_Pos (4U)
+#define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
+#define PWR_PDCRD_PD3_Pos (3U)
+#define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
+#define PWR_PDCRD_PD2_Pos (2U)
+#define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
+#define PWR_PDCRD_PD1_Pos (1U)
+#define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
+#define PWR_PDCRD_PD0_Pos (0U)
+#define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRE register ********************/
+#define PWR_PUCRE_PE15_Pos (15U)
+#define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos (14U)
+#define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos (13U)
+#define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos (12U)
+#define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos (11U)
+#define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos (10U)
+#define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos (9U)
+#define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
+#define PWR_PUCRE_PE8_Pos (8U)
+#define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
+#define PWR_PUCRE_PE7_Pos (7U)
+#define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
+#define PWR_PUCRE_PE6_Pos (6U)
+#define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
+#define PWR_PUCRE_PE5_Pos (5U)
+#define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
+#define PWR_PUCRE_PE4_Pos (4U)
+#define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
+#define PWR_PUCRE_PE3_Pos (3U)
+#define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
+#define PWR_PUCRE_PE2_Pos (2U)
+#define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
+#define PWR_PUCRE_PE1_Pos (1U)
+#define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
+#define PWR_PUCRE_PE0_Pos (0U)
+#define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRE register ********************/
+#define PWR_PDCRE_PE15_Pos (15U)
+#define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos (14U)
+#define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos (13U)
+#define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos (12U)
+#define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos (11U)
+#define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos (10U)
+#define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos (9U)
+#define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
+#define PWR_PDCRE_PE8_Pos (8U)
+#define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
+#define PWR_PDCRE_PE7_Pos (7U)
+#define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
+#define PWR_PDCRE_PE6_Pos (6U)
+#define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
+#define PWR_PDCRE_PE5_Pos (5U)
+#define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
+#define PWR_PDCRE_PE4_Pos (4U)
+#define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
+#define PWR_PDCRE_PE3_Pos (3U)
+#define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
+#define PWR_PDCRE_PE2_Pos (2U)
+#define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
+#define PWR_PDCRE_PE1_Pos (1U)
+#define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
+#define PWR_PDCRE_PE0_Pos (0U)
+#define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRF register ********************/
+#define PWR_PUCRF_PF15_Pos (15U)
+#define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos (14U)
+#define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos (13U)
+#define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos (12U)
+#define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos (11U)
+#define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos (10U)
+#define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos (9U)
+#define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
+#define PWR_PUCRF_PF8_Pos (8U)
+#define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
+#define PWR_PUCRF_PF7_Pos (7U)
+#define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
+#define PWR_PUCRF_PF6_Pos (6U)
+#define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
+#define PWR_PUCRF_PF5_Pos (5U)
+#define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
+#define PWR_PUCRF_PF4_Pos (4U)
+#define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
+#define PWR_PUCRF_PF3_Pos (3U)
+#define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
+#define PWR_PUCRF_PF2_Pos (2U)
+#define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
+#define PWR_PUCRF_PF1_Pos (1U)
+#define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
+#define PWR_PUCRF_PF0_Pos (0U)
+#define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRF register ********************/
+#define PWR_PDCRF_PF15_Pos (15U)
+#define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos (14U)
+#define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos (13U)
+#define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos (12U)
+#define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos (11U)
+#define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos (10U)
+#define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos (9U)
+#define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
+#define PWR_PDCRF_PF8_Pos (8U)
+#define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
+#define PWR_PDCRF_PF7_Pos (7U)
+#define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
+#define PWR_PDCRF_PF6_Pos (6U)
+#define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
+#define PWR_PDCRF_PF5_Pos (5U)
+#define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
+#define PWR_PDCRF_PF4_Pos (4U)
+#define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
+#define PWR_PDCRF_PF3_Pos (3U)
+#define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
+#define PWR_PDCRF_PF2_Pos (2U)
+#define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
+#define PWR_PDCRF_PF1_Pos (1U)
+#define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
+#define PWR_PDCRF_PF0_Pos (0U)
+#define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRG register ********************/
+#define PWR_PUCRG_PG15_Pos (15U)
+#define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos (14U)
+#define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos (13U)
+#define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos (12U)
+#define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos (11U)
+#define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos (10U)
+#define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos (9U)
+#define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
+#define PWR_PUCRG_PG8_Pos (8U)
+#define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
+#define PWR_PUCRG_PG7_Pos (7U)
+#define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
+#define PWR_PUCRG_PG6_Pos (6U)
+#define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
+#define PWR_PUCRG_PG5_Pos (5U)
+#define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
+#define PWR_PUCRG_PG4_Pos (4U)
+#define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
+#define PWR_PUCRG_PG3_Pos (3U)
+#define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
+#define PWR_PUCRG_PG2_Pos (2U)
+#define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
+#define PWR_PUCRG_PG1_Pos (1U)
+#define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
+#define PWR_PUCRG_PG0_Pos (0U)
+#define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRG register ********************/
+#define PWR_PDCRG_PG15_Pos (15U)
+#define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos (14U)
+#define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos (13U)
+#define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos (12U)
+#define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos (11U)
+#define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos (10U)
+#define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos (9U)
+#define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
+#define PWR_PDCRG_PG8_Pos (8U)
+#define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
+#define PWR_PDCRG_PG7_Pos (7U)
+#define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
+#define PWR_PDCRG_PG6_Pos (6U)
+#define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
+#define PWR_PDCRG_PG5_Pos (5U)
+#define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
+#define PWR_PDCRG_PG4_Pos (4U)
+#define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
+#define PWR_PDCRG_PG3_Pos (3U)
+#define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
+#define PWR_PDCRG_PG2_Pos (2U)
+#define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
+#define PWR_PDCRG_PG1_Pos (1U)
+#define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
+#define PWR_PDCRG_PG0_Pos (0U)
+#define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRH register ********************/
+#define PWR_PUCRH_PH15_Pos (15U)
+#define PWR_PUCRH_PH15_Msk (0x1U << PWR_PUCRH_PH15_Pos) /*!< 0x00008000 */
+#define PWR_PUCRH_PH15 PWR_PUCRH_PH15_Msk /*!< Port PH15 Pull-Up set */
+#define PWR_PUCRH_PH14_Pos (14U)
+#define PWR_PUCRH_PH14_Msk (0x1U << PWR_PUCRH_PH14_Pos) /*!< 0x00004000 */
+#define PWR_PUCRH_PH14 PWR_PUCRH_PH14_Msk /*!< Port PH14 Pull-Up set */
+#define PWR_PUCRH_PH13_Pos (13U)
+#define PWR_PUCRH_PH13_Msk (0x1U << PWR_PUCRH_PH13_Pos) /*!< 0x00002000 */
+#define PWR_PUCRH_PH13 PWR_PUCRH_PH13_Msk /*!< Port PH13 Pull-Up set */
+#define PWR_PUCRH_PH12_Pos (12U)
+#define PWR_PUCRH_PH12_Msk (0x1U << PWR_PUCRH_PH12_Pos) /*!< 0x00001000 */
+#define PWR_PUCRH_PH12 PWR_PUCRH_PH12_Msk /*!< Port PH12 Pull-Up set */
+#define PWR_PUCRH_PH11_Pos (11U)
+#define PWR_PUCRH_PH11_Msk (0x1U << PWR_PUCRH_PH11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRH_PH11 PWR_PUCRH_PH11_Msk /*!< Port PH11 Pull-Up set */
+#define PWR_PUCRH_PH10_Pos (10U)
+#define PWR_PUCRH_PH10_Msk (0x1U << PWR_PUCRH_PH10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRH_PH10 PWR_PUCRH_PH10_Msk /*!< Port PH10 Pull-Up set */
+#define PWR_PUCRH_PH9_Pos (9U)
+#define PWR_PUCRH_PH9_Msk (0x1U << PWR_PUCRH_PH9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRH_PH9 PWR_PUCRH_PH9_Msk /*!< Port PH9 Pull-Up set */
+#define PWR_PUCRH_PH8_Pos (8U)
+#define PWR_PUCRH_PH8_Msk (0x1U << PWR_PUCRH_PH8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRH_PH8 PWR_PUCRH_PH8_Msk /*!< Port PH8 Pull-Up set */
+#define PWR_PUCRH_PH7_Pos (7U)
+#define PWR_PUCRH_PH7_Msk (0x1U << PWR_PUCRH_PH7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRH_PH7 PWR_PUCRH_PH7_Msk /*!< Port PH7 Pull-Up set */
+#define PWR_PUCRH_PH6_Pos (6U)
+#define PWR_PUCRH_PH6_Msk (0x1U << PWR_PUCRH_PH6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRH_PH6 PWR_PUCRH_PH6_Msk /*!< Port PH6 Pull-Up set */
+#define PWR_PUCRH_PH5_Pos (5U)
+#define PWR_PUCRH_PH5_Msk (0x1U << PWR_PUCRH_PH5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRH_PH5 PWR_PUCRH_PH5_Msk /*!< Port PH5 Pull-Up set */
+#define PWR_PUCRH_PH4_Pos (4U)
+#define PWR_PUCRH_PH4_Msk (0x1U << PWR_PUCRH_PH4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRH_PH4 PWR_PUCRH_PH4_Msk /*!< Port PH4 Pull-Up set */
+#define PWR_PUCRH_PH3_Pos (3U)
+#define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */
+#define PWR_PUCRH_PH2_Pos (2U)
+#define PWR_PUCRH_PH2_Msk (0x1U << PWR_PUCRH_PH2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRH_PH2 PWR_PUCRH_PH2_Msk /*!< Port PH2 Pull-Up set */
+#define PWR_PUCRH_PH1_Pos (1U)
+#define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
+#define PWR_PUCRH_PH0_Pos (0U)
+#define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRH register ********************/
+#define PWR_PDCRH_PH15_Pos (15U)
+#define PWR_PDCRH_PH15_Msk (0x1U << PWR_PDCRH_PH15_Pos) /*!< 0x00008000 */
+#define PWR_PDCRH_PH15 PWR_PDCRH_PH15_Msk /*!< Port PH15 Pull-Down set */
+#define PWR_PDCRH_PH14_Pos (14U)
+#define PWR_PDCRH_PH14_Msk (0x1U << PWR_PDCRH_PH14_Pos) /*!< 0x00004000 */
+#define PWR_PDCRH_PH14 PWR_PDCRH_PH14_Msk /*!< Port PH14 Pull-Down set */
+#define PWR_PDCRH_PH13_Pos (13U)
+#define PWR_PDCRH_PH13_Msk (0x1U << PWR_PDCRH_PH13_Pos) /*!< 0x00002000 */
+#define PWR_PDCRH_PH13 PWR_PDCRH_PH13_Msk /*!< Port PH13 Pull-Down set */
+#define PWR_PDCRH_PH12_Pos (12U)
+#define PWR_PDCRH_PH12_Msk (0x1U << PWR_PDCRH_PH12_Pos) /*!< 0x00001000 */
+#define PWR_PDCRH_PH12 PWR_PDCRH_PH12_Msk /*!< Port PH12 Pull-Down set */
+#define PWR_PDCRH_PH11_Pos (11U)
+#define PWR_PDCRH_PH11_Msk (0x1U << PWR_PDCRH_PH11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRH_PH11 PWR_PDCRH_PH11_Msk /*!< Port PH11 Pull-Down set */
+#define PWR_PDCRH_PH10_Pos (10U)
+#define PWR_PDCRH_PH10_Msk (0x1U << PWR_PDCRH_PH10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRH_PH10 PWR_PDCRH_PH10_Msk /*!< Port PH10 Pull-Down set */
+#define PWR_PDCRH_PH9_Pos (9U)
+#define PWR_PDCRH_PH9_Msk (0x1U << PWR_PDCRH_PH9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRH_PH9 PWR_PDCRH_PH9_Msk /*!< Port PH9 Pull-Down set */
+#define PWR_PDCRH_PH8_Pos (8U)
+#define PWR_PDCRH_PH8_Msk (0x1U << PWR_PDCRH_PH8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRH_PH8 PWR_PDCRH_PH8_Msk /*!< Port PH8 Pull-Down set */
+#define PWR_PDCRH_PH7_Pos (7U)
+#define PWR_PDCRH_PH7_Msk (0x1U << PWR_PDCRH_PH7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRH_PH7 PWR_PDCRH_PH7_Msk /*!< Port PH7 Pull-Down set */
+#define PWR_PDCRH_PH6_Pos (6U)
+#define PWR_PDCRH_PH6_Msk (0x1U << PWR_PDCRH_PH6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRH_PH6 PWR_PDCRH_PH6_Msk /*!< Port PH6 Pull-Down set */
+#define PWR_PDCRH_PH5_Pos (5U)
+#define PWR_PDCRH_PH5_Msk (0x1U << PWR_PDCRH_PH5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRH_PH5 PWR_PDCRH_PH5_Msk /*!< Port PH5 Pull-Down set */
+#define PWR_PDCRH_PH4_Pos (4U)
+#define PWR_PDCRH_PH4_Msk (0x1U << PWR_PDCRH_PH4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRH_PH4 PWR_PDCRH_PH4_Msk /*!< Port PH4 Pull-Down set */
+#define PWR_PDCRH_PH3_Pos (3U)
+#define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
+#define PWR_PDCRH_PH2_Pos (2U)
+#define PWR_PDCRH_PH2_Msk (0x1U << PWR_PDCRH_PH2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRH_PH2 PWR_PDCRH_PH2_Msk /*!< Port PH1 Pull-Down set */
+#define PWR_PDCRH_PH1_Pos (1U)
+#define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
+#define PWR_PDCRH_PH0_Pos (0U)
+#define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
+
+/******************** Bit definition for PWR_PUCRI register ********************/
+#define PWR_PUCRI_PI11_Pos (11U)
+#define PWR_PUCRI_PI11_Msk (0x1U << PWR_PUCRI_PI11_Pos) /*!< 0x00000800 */
+#define PWR_PUCRI_PI11 PWR_PUCRI_PI11_Msk /*!< Port PI11 Pull-Up set */
+#define PWR_PUCRI_PI10_Pos (10U)
+#define PWR_PUCRI_PI10_Msk (0x1U << PWR_PUCRI_PI10_Pos) /*!< 0x00000400 */
+#define PWR_PUCRI_PI10 PWR_PUCRI_PI10_Msk /*!< Port PI10 Pull-Up set */
+#define PWR_PUCRI_PI9_Pos (9U)
+#define PWR_PUCRI_PI9_Msk (0x1U << PWR_PUCRI_PI9_Pos) /*!< 0x00000200 */
+#define PWR_PUCRI_PI9 PWR_PUCRI_PI9_Msk /*!< Port PI9 Pull-Up set */
+#define PWR_PUCRI_PI8_Pos (8U)
+#define PWR_PUCRI_PI8_Msk (0x1U << PWR_PUCRI_PI8_Pos) /*!< 0x00000100 */
+#define PWR_PUCRI_PI8 PWR_PUCRI_PI8_Msk /*!< Port PI8 Pull-Up set */
+#define PWR_PUCRI_PI7_Pos (7U)
+#define PWR_PUCRI_PI7_Msk (0x1U << PWR_PUCRI_PI7_Pos) /*!< 0x00000080 */
+#define PWR_PUCRI_PI7 PWR_PUCRI_PI7_Msk /*!< Port PI7 Pull-Up set */
+#define PWR_PUCRI_PI6_Pos (6U)
+#define PWR_PUCRI_PI6_Msk (0x1U << PWR_PUCRI_PI6_Pos) /*!< 0x00000040 */
+#define PWR_PUCRI_PI6 PWR_PUCRI_PI6_Msk /*!< Port PI6 Pull-Up set */
+#define PWR_PUCRI_PI5_Pos (5U)
+#define PWR_PUCRI_PI5_Msk (0x1U << PWR_PUCRI_PI5_Pos) /*!< 0x00000020 */
+#define PWR_PUCRI_PI5 PWR_PUCRI_PI5_Msk /*!< Port PI5 Pull-Up set */
+#define PWR_PUCRI_PI4_Pos (4U)
+#define PWR_PUCRI_PI4_Msk (0x1U << PWR_PUCRI_PI4_Pos) /*!< 0x00000010 */
+#define PWR_PUCRI_PI4 PWR_PUCRI_PI4_Msk /*!< Port PI4 Pull-Up set */
+#define PWR_PUCRI_PI3_Pos (3U)
+#define PWR_PUCRI_PI3_Msk (0x1U << PWR_PUCRI_PI3_Pos) /*!< 0x00000008 */
+#define PWR_PUCRI_PI3 PWR_PUCRI_PI3_Msk /*!< Port PI3 Pull-Up set */
+#define PWR_PUCRI_PI2_Pos (2U)
+#define PWR_PUCRI_PI2_Msk (0x1U << PWR_PUCRI_PI2_Pos) /*!< 0x00000004 */
+#define PWR_PUCRI_PI2 PWR_PUCRI_PI2_Msk /*!< Port PI2 Pull-Up set */
+#define PWR_PUCRI_PI1_Pos (1U)
+#define PWR_PUCRI_PI1_Msk (0x1U << PWR_PUCRI_PI1_Pos) /*!< 0x00000002 */
+#define PWR_PUCRI_PI1 PWR_PUCRI_PI1_Msk /*!< Port PI1 Pull-Up set */
+#define PWR_PUCRI_PI0_Pos (0U)
+#define PWR_PUCRI_PI0_Msk (0x1U << PWR_PUCRI_PI0_Pos) /*!< 0x00000001 */
+#define PWR_PUCRI_PI0 PWR_PUCRI_PI0_Msk /*!< Port PI0 Pull-Up set */
+
+/******************** Bit definition for PWR_PDCRI register ********************/
+#define PWR_PDCRI_PI11_Pos (11U)
+#define PWR_PDCRI_PI11_Msk (0x1U << PWR_PDCRI_PI11_Pos) /*!< 0x00000800 */
+#define PWR_PDCRI_PI11 PWR_PDCRI_PI11_Msk /*!< Port PI11 Pull-Down set */
+#define PWR_PDCRI_PI10_Pos (10U)
+#define PWR_PDCRI_PI10_Msk (0x1U << PWR_PDCRI_PI10_Pos) /*!< 0x00000400 */
+#define PWR_PDCRI_PI10 PWR_PDCRI_PI10_Msk /*!< Port PI10 Pull-Down set */
+#define PWR_PDCRI_PI9_Pos (9U)
+#define PWR_PDCRI_PI9_Msk (0x1U << PWR_PDCRI_PI9_Pos) /*!< 0x00000200 */
+#define PWR_PDCRI_PI9 PWR_PDCRI_PI9_Msk /*!< Port PI9 Pull-Down set */
+#define PWR_PDCRI_PI8_Pos (8U)
+#define PWR_PDCRI_PI8_Msk (0x1U << PWR_PDCRI_PI8_Pos) /*!< 0x00000100 */
+#define PWR_PDCRI_PI8 PWR_PDCRI_PI8_Msk /*!< Port PI8 Pull-Down set */
+#define PWR_PDCRI_PI7_Pos (7U)
+#define PWR_PDCRI_PI7_Msk (0x1U << PWR_PDCRI_PI7_Pos) /*!< 0x00000080 */
+#define PWR_PDCRI_PI7 PWR_PDCRI_PI7_Msk /*!< Port PI7 Pull-Down set */
+#define PWR_PDCRI_PI6_Pos (6U)
+#define PWR_PDCRI_PI6_Msk (0x1U << PWR_PDCRI_PI6_Pos) /*!< 0x00000040 */
+#define PWR_PDCRI_PI6 PWR_PDCRI_PI6_Msk /*!< Port PI6 Pull-Down set */
+#define PWR_PDCRI_PI5_Pos (5U)
+#define PWR_PDCRI_PI5_Msk (0x1U << PWR_PDCRI_PI5_Pos) /*!< 0x00000020 */
+#define PWR_PDCRI_PI5 PWR_PDCRI_PI5_Msk /*!< Port PI5 Pull-Down set */
+#define PWR_PDCRI_PI4_Pos (4U)
+#define PWR_PDCRI_PI4_Msk (0x1U << PWR_PDCRI_PI4_Pos) /*!< 0x00000010 */
+#define PWR_PDCRI_PI4 PWR_PDCRI_PI4_Msk /*!< Port PI4 Pull-Down set */
+#define PWR_PDCRI_PI3_Pos (3U)
+#define PWR_PDCRI_PI3_Msk (0x1U << PWR_PDCRI_PI3_Pos) /*!< 0x00000008 */
+#define PWR_PDCRI_PI3 PWR_PDCRI_PI3_Msk /*!< Port PI3 Pull-Down set */
+#define PWR_PDCRI_PI2_Pos (2U)
+#define PWR_PDCRI_PI2_Msk (0x1U << PWR_PDCRI_PI2_Pos) /*!< 0x00000004 */
+#define PWR_PDCRI_PI2 PWR_PDCRI_PI2_Msk /*!< Port PI2 Pull-Down set */
+#define PWR_PDCRI_PI1_Pos (1U)
+#define PWR_PDCRI_PI1_Msk (0x1U << PWR_PDCRI_PI1_Pos) /*!< 0x00000002 */
+#define PWR_PDCRI_PI1 PWR_PDCRI_PI1_Msk /*!< Port PI1 Pull-Down set */
+#define PWR_PDCRI_PI0_Pos (0U)
+#define PWR_PDCRI_PI0_Msk (0x1U << PWR_PDCRI_PI0_Pos) /*!< 0x00000001 */
+#define PWR_PDCRI_PI0 PWR_PDCRI_PI0_Msk /*!< Port PI0 Pull-Down set */
+
+/******************** Bit definition for PWR_CR5 register ********************/
+#define PWR_CR5_R1MODE_Pos (8U)
+#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
+#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< Range 1 normal mode */
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_HSI48_SUPPORT
+#define RCC_PLLM_DIV_1_16_SUPPORT
+#define RCC_PLLP_DIV_2_31_SUPPORT
+#define RCC_PLLSAI1M_DIV_1_16_SUPPORT
+#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
+#define RCC_PLLSAI2_SUPPORT
+#define RCC_PLLSAI2M_DIV_1_16_SUPPORT
+#define RCC_PLLSAI2P_DIV_2_31_SUPPORT
+#define RCC_PLLSAI2Q_DIV_SUPPORT
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_MSION_Pos (0U)
+#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos (1U)
+#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos (2U)
+#define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos (3U)
+#define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos (4U)
+#define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos (8U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos (9U)
+#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (10U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos (11U)
+#define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
+#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos (26U)
+#define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos (27U)
+#define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos (28U)
+#define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos (29U)
+#define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
+
+/******************** Bit definition for RCC_ICSCR register ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos (0U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos (8U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos (16U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos (24U)
+#define RCC_ICSCR_HSITRIM_Msk (0x7FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
+#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_ICSCR_HSITRIM_6 (0x40U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos (4U)
+#define RCC_PLLCFGR_PLLM_Msk (0xFU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
+#define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLM_3 (0x8U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
+
+#define RCC_PLLCFGR_PLLN_Pos (8U)
+#define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
+#define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos (16U)
+#define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
+#define RCC_PLLCFGR_PLLP_Pos (17U)
+#define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
+#define RCC_PLLCFGR_PLLQEN_Pos (20U)
+#define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
+
+#define RCC_PLLCFGR_PLLQ_Pos (21U)
+#define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
+#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos (24U)
+#define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
+#define RCC_PLLCFGR_PLLR_Pos (25U)
+#define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
+#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
+#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
+#define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1M_Pos (4U)
+#define RCC_PLLSAI1CFGR_PLLSAI1M_Msk (0xFU << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x000000F0 */
+#define RCC_PLLSAI1CFGR_PLLSAI1M RCC_PLLSAI1CFGR_PLLSAI1M_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1M_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000010 */
+#define RCC_PLLSAI1CFGR_PLLSAI1M_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000020 */
+#define RCC_PLLSAI1CFGR_PLLSAI1M_2 (0x4U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAI1CFGR_PLLSAI1M_3 (0x8U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000080 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2M_Pos (4U)
+#define RCC_PLLSAI2CFGR_PLLSAI2M_Msk (0xFU << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x000000F0 */
+#define RCC_PLLSAI2CFGR_PLLSAI2M RCC_PLLSAI2CFGR_PLLSAI2M_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2M_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000010 */
+#define RCC_PLLSAI2CFGR_PLLSAI2M_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000020 */
+#define RCC_PLLSAI2CFGR_PLLSAI2M_2 (0x4U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAI2CFGR_PLLSAI2M_3 (0x8U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000080 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
+
+#define RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos (20U)
+#define RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2QEN RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2Q_Pos (21U)
+#define RCC_PLLSAI2CFGR_PLLSAI2Q_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2Q RCC_PLLSAI2CFGR_PLLSAI2Q_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2Q_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2Q_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos (27U)
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for RCC_CIER register ******************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_MSIRDYIE_Pos (2U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos (3U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos (4U)
+#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_PLLRDYIE_Pos (5U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
+#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
+#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
+#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
+#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos (9U)
+#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos (10U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
+
+/******************** Bit definition for RCC_CIFR register ******************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_MSIRDYF_Pos (2U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos (3U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos (4U)
+#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos (5U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
+#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
+#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
+#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
+#define RCC_CIFR_CSSF_Pos (8U)
+#define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
+#define RCC_CIFR_LSECSSF_Pos (9U)
+#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos (10U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
+
+/******************** Bit definition for RCC_CICR register ******************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_MSIRDYC_Pos (2U)
+#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos (3U)
+#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos (4U)
+#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos (5U)
+#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
+#define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
+#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
+#define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
+#define RCC_CICR_CSSC_Pos (8U)
+#define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
+#define RCC_CICR_LSECSSC_Pos (9U)
+#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSI48RDYC_Pos (10U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
+#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1U << RCC_AHB1RSTR_DMAMUX1RST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
+#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
+#define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
+#define RCC_AHB1RSTR_TSCRST_Pos (16U)
+#define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
+#define RCC_AHB1RSTR_DMA2DRST_Pos (17U)
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
+#define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
+#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
+#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
+#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
+#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
+#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
+#define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
+#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
+#define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
+#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
+#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
+#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
+#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
+#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
+#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
+#define RCC_AHB2RSTR_GPIOIRST_Pos (8U)
+#define RCC_AHB2RSTR_GPIOIRST_Msk (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB2RSTR_GPIOIRST RCC_AHB2RSTR_GPIOIRST_Msk
+#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
+#define RCC_AHB2RSTR_ADCRST_Pos (13U)
+#define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
+#define RCC_AHB2RSTR_DCMIRST_Pos (14U)
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos (18U)
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_OSPIMRST_Pos (20U)
+#define RCC_AHB2RSTR_OSPIMRST_Msk (0x1U << RCC_AHB2RSTR_OSPIMRST_Pos) /*!< 0x00100000 */
+#define RCC_AHB2RSTR_OSPIMRST RCC_AHB2RSTR_OSPIMRST_Msk
+#define RCC_AHB2RSTR_SDMMC1RST_Pos (22U)
+#define RCC_AHB2RSTR_SDMMC1RST_Msk (0x1U << RCC_AHB2RSTR_SDMMC1RST_Pos) /*!< 0x00400000 */
+#define RCC_AHB2RSTR_SDMMC1RST RCC_AHB2RSTR_SDMMC1RST_Msk
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_OSPI1RST_Pos (8U)
+#define RCC_AHB3RSTR_OSPI1RST_Msk (0x1U << RCC_AHB3RSTR_OSPI1RST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
+#define RCC_AHB3RSTR_OSPI2RST_Pos (9U)
+#define RCC_AHB3RSTR_OSPI2RST_Msk (0x1U << RCC_AHB3RSTR_OSPI2RST_Pos) /*!< 0x00000200 */
+#define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
+
+/******************** Bit definition for RCC_APB1RSTR1 register **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
+#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
+#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
+#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
+#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
+#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
+#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
+#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
+#define RCC_APB1RSTR1_USART2RST_Pos (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
+#define RCC_APB1RSTR1_USART3RST_Pos (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
+#define RCC_APB1RSTR1_UART4RST_Pos (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
+#define RCC_APB1RSTR1_UART5RST_Pos (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
+#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
+#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
+#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
+#define RCC_APB1RSTR1_CRSRST_Pos (24U)
+#define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
+#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
+#define RCC_APB1RSTR1_PWRRST_Pos (28U)
+#define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
+#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
+#define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
+#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
+#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
+#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
+
+/******************** Bit definition for RCC_APB1RSTR2 register **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
+#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
+#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
+#define RCC_APB1RSTR2_I2C4RST_Msk (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
+#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
+#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos (13U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
+#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1U << RCC_AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
+#define RCC_AHB1ENR_FLASHEN_Pos (8U)
+#define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
+#define RCC_AHB1ENR_CRCEN_Pos (12U)
+#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
+#define RCC_AHB1ENR_TSCEN_Pos (16U)
+#define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
+#define RCC_AHB1ENR_DMA2DEN_Pos (17U)
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
+#define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
+#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
+#define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
+#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
+#define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
+#define RCC_AHB2ENR_GPIODEN_Pos (3U)
+#define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
+#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
+#define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
+#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
+#define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
+#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
+#define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
+#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
+#define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
+#define RCC_AHB2ENR_GPIOIEN_Pos (8U)
+#define RCC_AHB2ENR_GPIOIEN_Msk (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2ENR_GPIOIEN RCC_AHB2ENR_GPIOIEN_Msk
+#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
+#define RCC_AHB2ENR_ADCEN_Pos (13U)
+#define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
+#define RCC_AHB2ENR_DCMIEN_Pos (14U)
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos (18U)
+#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_OSPIMEN_Pos (20U)
+#define RCC_AHB2ENR_OSPIMEN_Msk (0x1U << RCC_AHB2ENR_OSPIMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB2ENR_OSPIMEN RCC_AHB2ENR_OSPIMEN_Msk
+#define RCC_AHB2ENR_SDMMC1EN_Pos (22U)
+#define RCC_AHB2ENR_SDMMC1EN_Msk (0x1U << RCC_AHB2ENR_SDMMC1EN_Pos) /*!< 0x00400000 */
+#define RCC_AHB2ENR_SDMMC1EN RCC_AHB2ENR_SDMMC1EN_Msk
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN_Pos (0U)
+#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_OSPI1EN_Pos (8U)
+#define RCC_AHB3ENR_OSPI1EN_Msk (0x1U << RCC_AHB3ENR_OSPI1EN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
+#define RCC_AHB3ENR_OSPI2EN_Pos (9U)
+#define RCC_AHB3ENR_OSPI2EN_Msk (0x1U << RCC_AHB3ENR_OSPI2EN_Pos) /*!< 0x00000200 */
+#define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
+
+/******************** Bit definition for RCC_APB1ENR1 register ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
+#define RCC_APB1ENR1_TIM3EN_Pos (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
+#define RCC_APB1ENR1_TIM4EN_Pos (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
+#define RCC_APB1ENR1_TIM5EN_Pos (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
+#define RCC_APB1ENR1_TIM6EN_Pos (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
+#define RCC_APB1ENR1_TIM7EN_Pos (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
+#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
+#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
+#define RCC_APB1ENR1_WWDGEN_Pos (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
+#define RCC_APB1ENR1_SPI2EN_Pos (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
+#define RCC_APB1ENR1_SPI3EN_Pos (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
+#define RCC_APB1ENR1_USART2EN_Pos (17U)
+#define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
+#define RCC_APB1ENR1_USART3EN_Pos (18U)
+#define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
+#define RCC_APB1ENR1_UART4EN_Pos (19U)
+#define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
+#define RCC_APB1ENR1_UART5EN_Pos (20U)
+#define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
+#define RCC_APB1ENR1_I2C1EN_Pos (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
+#define RCC_APB1ENR1_I2C2EN_Pos (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
+#define RCC_APB1ENR1_I2C3EN_Pos (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
+#define RCC_APB1ENR1_CRSEN_Pos (24U)
+#define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
+#define RCC_APB1ENR1_CAN1EN_Pos (25U)
+#define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
+#define RCC_APB1ENR1_PWREN_Pos (28U)
+#define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
+#define RCC_APB1ENR1_DAC1EN_Pos (29U)
+#define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
+#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
+#define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
+#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
+
+/******************** Bit definition for RCC_APB1RSTR2 register **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
+#define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
+#define RCC_APB1ENR2_I2C4EN_Pos (1U)
+#define RCC_APB1ENR2_I2C4EN_Msk (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
+#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
+#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos (13U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos (16U)
+#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos (17U)
+#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos (18U)
+#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos (21U)
+#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos (22U)
+#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
+
+/******************** Bit definition for RCC_AHB1SMENR register ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
+#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
+#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
+#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
+#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
+#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
+#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
+#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
+#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
+#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
+#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
+#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
+#define RCC_AHB1SMENR_DMA2DSMEN_Pos (17U)
+#define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk
+
+/******************** Bit definition for RCC_AHB2SMENR register *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
+#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
+#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
+#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
+#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
+#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
+#define RCC_AHB2SMENR_GPIOISMEN_Pos (8U)
+#define RCC_AHB2SMENR_GPIOISMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2SMENR_GPIOISMEN RCC_AHB2SMENR_GPIOISMEN_Msk
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
+#define RCC_AHB2SMENR_SRAM3SMEN_Pos (10U)
+#define RCC_AHB2SMENR_SRAM3SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM3SMEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB2SMENR_SRAM3SMEN RCC_AHB2SMENR_SRAM3SMEN_Msk
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
+#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
+#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
+#define RCC_AHB2SMENR_DCMISMEN_Pos (14U)
+#define RCC_AHB2SMENR_DCMISMEN_Msk (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB2SMENR_DCMISMEN RCC_AHB2SMENR_DCMISMEN_Msk
+#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
+#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
+#define RCC_AHB2SMENR_OSPIMSMEN_Pos (20U)
+#define RCC_AHB2SMENR_OSPIMSMEN_Msk (0x1U << RCC_AHB2SMENR_OSPIMSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB2SMENR_OSPIMSMEN RCC_AHB2SMENR_OSPIMSMEN_Msk
+#define RCC_AHB2SMENR_SDMMC1SMEN_Pos (22U)
+#define RCC_AHB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_AHB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB2SMENR_SDMMC1SMEN RCC_AHB2SMENR_SDMMC1SMEN_Msk
+
+/******************** Bit definition for RCC_AHB3SMENR register *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
+#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
+#define RCC_AHB3SMENR_OSPI1SMEN_Pos (8U)
+#define RCC_AHB3SMENR_OSPI1SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI1SMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_OSPI1SMEN RCC_AHB3SMENR_OSPI1SMEN_Msk
+#define RCC_AHB3SMENR_OSPI2SMEN_Pos (9U)
+#define RCC_AHB3SMENR_OSPI2SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB3SMENR_OSPI2SMEN RCC_AHB3SMENR_OSPI2SMEN_Msk
+
+/******************** Bit definition for RCC_APB1SMENR1 register *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
+#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
+#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
+#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
+#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
+#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
+#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
+#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
+#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
+#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
+#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
+#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
+#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
+#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
+#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
+#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
+#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
+#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
+#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
+#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
+#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
+#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
+#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
+#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
+#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
+#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
+#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
+#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
+#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
+#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
+#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
+#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
+#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
+#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
+
+/******************** Bit definition for RCC_APB1SMENR2 register *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
+#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
+#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
+
+/******************** Bit definition for RCC_APB2SMENR register *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
+#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
+#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
+#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
+#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
+#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
+#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
+#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
+#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
+#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
+#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
+#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
+#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
+#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
+#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
+
+/******************** Bit definition for RCC_CCIPR register ******************/
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
+#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
+#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos (4U)
+#define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
+#define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos (6U)
+#define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
+#define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos (8U)
+#define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
+#define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
+#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
+#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos (14U)
+#define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
+#define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos (16U)
+#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
+#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
+#define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
+#define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos (26U)
+#define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
+#define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos (28U)
+#define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
+#define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos (3U)
+#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos (5U)
+#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos (6U)
+#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
+#define RCC_BDCR_LSCOEN_Pos (24U)
+#define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
+#define RCC_BDCR_LSCOSEL_Pos (25U)
+#define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
+
+#define RCC_CSR_MSISRANGE_Pos (8U)
+#define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
+#define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_BORRSTF_Pos (27U)
+#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos (7U)
+#define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
+#define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+#define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
+#define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
+#define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
+#define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
+#define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
+#define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for RCC_CCIPR2 register ******************/
+#define RCC_CCIPR2_I2C4SEL_Pos (0U)
+#define RCC_CCIPR2_I2C4SEL_Msk (0x3U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
+#define RCC_CCIPR2_I2C4SEL_0 (0x1U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR2_I2C4SEL_1 (0x2U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR2_DFSDM1SEL_Pos (2U)
+#define RCC_CCIPR2_DFSDM1SEL_Msk (0x1U << RCC_CCIPR2_DFSDM1SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR2_DFSDM1SEL RCC_CCIPR2_DFSDM1SEL_Msk
+
+#define RCC_CCIPR2_ADFSDM1SEL_Pos (3U)
+#define RCC_CCIPR2_ADFSDM1SEL_Msk (0x3U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000018 */
+#define RCC_CCIPR2_ADFSDM1SEL RCC_CCIPR2_ADFSDM1SEL_Msk
+#define RCC_CCIPR2_ADFSDM1SEL_0 (0x1U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000008 */
+#define RCC_CCIPR2_ADFSDM1SEL_1 (0x2U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000010 */
+
+#define RCC_CCIPR2_SAI1SEL_Pos (5U)
+#define RCC_CCIPR2_SAI1SEL_Msk (0x7U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
+#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk
+#define RCC_CCIPR2_SAI1SEL_0 (0x1U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
+#define RCC_CCIPR2_SAI1SEL_1 (0x2U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
+#define RCC_CCIPR2_SAI1SEL_2 (0x4U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
+
+#define RCC_CCIPR2_SAI2SEL_Pos (8U)
+#define RCC_CCIPR2_SAI2SEL_Msk (0x7U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */
+#define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk
+#define RCC_CCIPR2_SAI2SEL_0 (0x1U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */
+#define RCC_CCIPR2_SAI2SEL_1 (0x2U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */
+#define RCC_CCIPR2_SAI2SEL_2 (0x4U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */
+
+#define RCC_CCIPR2_SDMMCSEL_Pos (14U)
+#define RCC_CCIPR2_SDMMCSEL_Msk (0x1U << RCC_CCIPR2_SDMMCSEL_Pos) /*!< 0x00004000 */
+#define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk
+
+#define RCC_CCIPR2_PLLSAI2DIVR_Pos (16U)
+#define RCC_CCIPR2_PLLSAI2DIVR_Msk (0x3U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR2_PLLSAI2DIVR RCC_CCIPR2_PLLSAI2DIVR_Msk
+#define RCC_CCIPR2_PLLSAI2DIVR_0 (0x1U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR2_PLLSAI2DIVR_1 (0x2U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_CCIPR2_OSPISEL_Pos (20U)
+#define RCC_CCIPR2_OSPISEL_Msk (0x3U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR2_OSPISEL RCC_CCIPR2_OSPISEL_Msk
+#define RCC_CCIPR2_OSPISEL_0 (0x1U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR2_OSPISEL_1 (0x2U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos (5U)
+#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
+#define RNG_CR_CED RNG_CR_CED_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_ITSE_Pos (24U)
+#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define RTC_CR_BCK RTC_CR_BKP
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_ITSF_Pos (17U)
+#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_TAMPCR register ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_0R register *******************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
+
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R_Pos (0U)
+#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP5R RTC_BKP5R_Msk
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R_Pos (0U)
+#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP6R RTC_BKP6R_Msk
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R_Pos (0U)
+#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP7R RTC_BKP7R_Msk
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R_Pos (0U)
+#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP8R RTC_BKP8R_Msk
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R_Pos (0U)
+#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP9R RTC_BKP9R_Msk
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R_Pos (0U)
+#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP10R RTC_BKP10R_Msk
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R_Pos (0U)
+#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP11R RTC_BKP11R_Msk
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R_Pos (0U)
+#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP12R RTC_BKP12R_Msk
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R_Pos (0U)
+#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP13R RTC_BKP13R_Msk
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R_Pos (0U)
+#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP14R RTC_BKP14R_Msk
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R_Pos (0U)
+#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP15R RTC_BKP15R_Msk
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R_Pos (0U)
+#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP16R RTC_BKP16R_Msk
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R_Pos (0U)
+#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP17R RTC_BKP17R_Msk
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R_Pos (0U)
+#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP18R RTC_BKP18R_Msk
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R_Pos (0U)
+#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP19R RTC_BKP19R_Msk
+
+/******************** Bits definition for RTC_BKP20R register ***************/
+#define RTC_BKP20R_Pos (0U)
+#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP20R RTC_BKP20R_Msk
+
+/******************** Bits definition for RTC_BKP21R register ***************/
+#define RTC_BKP21R_Pos (0U)
+#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP21R RTC_BKP21R_Msk
+
+/******************** Bits definition for RTC_BKP22R register ***************/
+#define RTC_BKP22R_Pos (0U)
+#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP22R RTC_BKP22R_Msk
+
+/******************** Bits definition for RTC_BKP23R register ***************/
+#define RTC_BKP23R_Pos (0U)
+#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP23R RTC_BKP23R_Msk
+
+/******************** Bits definition for RTC_BKP24R register ***************/
+#define RTC_BKP24R_Pos (0U)
+#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP24R RTC_BKP24R_Msk
+
+/******************** Bits definition for RTC_BKP25R register ***************/
+#define RTC_BKP25R_Pos (0U)
+#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP25R RTC_BKP25R_Msk
+
+/******************** Bits definition for RTC_BKP26R register ***************/
+#define RTC_BKP26R_Pos (0U)
+#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP26R RTC_BKP26R_Msk
+
+/******************** Bits definition for RTC_BKP27R register ***************/
+#define RTC_BKP27R_Pos (0U)
+#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP27R RTC_BKP27R_Msk
+
+/******************** Bits definition for RTC_BKP28R register ***************/
+#define RTC_BKP28R_Pos (0U)
+#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP28R RTC_BKP28R_Msk
+
+/******************** Bits definition for RTC_BKP29R register ***************/
+#define RTC_BKP29R_Pos (0U)
+#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP29R RTC_BKP29R_Msk
+
+/******************** Bits definition for RTC_BKP30R register ***************/
+#define RTC_BKP30R_Pos (0U)
+#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP30R RTC_BKP30R_Msk
+
+/******************** Bits definition for RTC_BKP31R register ***************/
+#define RTC_BKP31R_Pos (0U)
+#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP31R RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 32U
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NOMCK_Pos (19U)
+#define SAI_xCR1_NOMCK_Msk (0x1U << SAI_xCR1_NOMCK_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NOMCK SAI_xCR1_NOMCK_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0x3FU << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
+#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
+#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
+
+#define SAI_xCR1_OSR_Pos (26U)
+#define SAI_xCR1_OSR_Msk (0x1U << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
+#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+/****************** Bit definition for SAI_PDMCR register *******************/
+#define SAI_PDMCR_PDMEN_Pos (0U)
+#define SAI_PDMCR_PDMEN_Msk (0x1U << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
+
+#define SAI_PDMCR_MICNBR_Pos (4U)
+#define SAI_PDMCR_MICNBR_Msk (0x3U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0 (0x1U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1 (0x2U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos (8U)
+#define SAI_PDMCR_CKEN1_Msk (0x1U << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos (9U)
+#define SAI_PDMCR_CKEN2_Msk (0x1U << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos (10U)
+#define SAI_PDMCR_CKEN3_Msk (0x1U << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos (11U)
+#define SAI_PDMCR_CKEN4_Msk (0x1U << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
+
+/****************** Bit definition for SAI_PDMDLY register ******************/
+#define SAI_PDMDLY_DLYM1L_Pos (0U)
+#define SAI_PDMDLY_DLYM1L_Msk (0x7U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0 (0x1U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1 (0x2U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2 (0x4U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos (4U)
+#define SAI_PDMDLY_DLYM1R_Msk (0x7U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0 (0x1U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1 (0x2U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2 (0x4U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos (8U)
+#define SAI_PDMDLY_DLYM2L_Msk (0x7U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0 (0x1U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1 (0x2U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2 (0x4U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos (12U)
+#define SAI_PDMDLY_DLYM2R_Msk (0x7U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0 (0x1U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1 (0x2U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2 (0x4U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos (16U)
+#define SAI_PDMDLY_DLYM3L_Msk (0x7U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0 (0x1U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1 (0x2U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2 (0x4U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos (20U)
+#define SAI_PDMDLY_DLYM3R_Msk (0x7U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0 (0x1U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1 (0x2U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2 (0x4U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos (24U)
+#define SAI_PDMDLY_DLYM4L_Msk (0x7U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0 (0x1U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1 (0x2U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2 (0x4U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos (28U)
+#define SAI_PDMDLY_DLYM4R_Msk (0x7U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0 (0x1U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1 (0x2U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2 (0x4U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
+
+/******************************************************************************/
+/* */
+/* SDMMC Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDMMC_POWER register ******************/
+#define SDMMC_POWER_PWRCTRL_Pos (0U)
+#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos (2U)
+#define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Pos /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Pos /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos (4U)
+#define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Pos /*!<Data and Command direction signals polarity selection */
+
+/****************** Bit definition for SDMMC_CLKCR register ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDMMC_CLKCR_PWRSAV_Pos (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+#define SDMMC_CLKCR_DDR_Pos (18U)
+#define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
+#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
+
+#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00030000 */
+#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00010000 */
+#define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for SDMMC_ARG register *******************/
+#define SDMMC_ARG_CMDARG_Pos (0U)
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDMMC_CMD register *******************/
+#define SDMMC_CMD_CMDINDEX_Pos (0U)
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
+#define SDMMC_CMD_CMDTRANS_Pos (6U)
+#define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
+#define SDMMC_CMD_CMDSTOP_Pos (7U)
+#define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
+
+#define SDMMC_CMD_WAITRESP_Pos (8U)
+#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos (10U)
+#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDMMC_CMD_WAITPEND_Pos (11U)
+#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos (12U)
+#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDMMC_CMD_DTHOLD_Pos (13U)
+#define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
+#define SDMMC_CMD_BOOTMODE_Pos (14U)
+#define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
+#define SDMMC_CMD_BOOTEN_Pos (15U)
+#define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
+#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM treats command as a Suspend or Resume command */
+
+/***************** Bit definition for SDMMC_RESPCMD register *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDMMC_RESP1 register ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP2 register ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP3 register ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP4 register ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_DTIMER register *****************/
+#define SDMMC_DTIMER_DATATIME_Pos (0U)
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDMMC_DLEN register *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDMMC_DCTRL register ******************/
+#define SDMMC_DCTRL_DTEN_Pos (0U)
+#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDMMC_DCTRL_DTDIR_Pos (1U)
+#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+
+#define SDMMC_DCTRL_DTMODE_Pos (2U)
+#define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos (8U)
+#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDMMC_DCTRL_RWSTOP_Pos (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDMMC_DCTRL_RWMOD_Pos (10U)
+#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDMMC_DCTRL_SDIOEN_Pos (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Data transfer mode selection */
+#define SDMMC_DCTRL_FIFORST_Pos (13U)
+#define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
+
+/****************** Bit definition for SDMMC_DCOUNT register *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDMMC_STA register ********************/
+#define SDMMC_STA_CCRCFAIL_Pos (0U)
+#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDMMC_STA_DCRCFAIL_Pos (1U)
+#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDMMC_STA_CTIMEOUT_Pos (2U)
+#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDMMC_STA_DTIMEOUT_Pos (3U)
+#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDMMC_STA_TXUNDERR_Pos (4U)
+#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDMMC_STA_RXOVERR_Pos (5U)
+#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDMMC_STA_CMDREND_Pos (6U)
+#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDMMC_STA_CMDSENT_Pos (7U)
+#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDMMC_STA_DATAEND_Pos (8U)
+#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDMMC_STA_DHOLD_Pos (9U)
+#define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
+#define SDMMC_STA_DBCKEND_Pos (10U)
+#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDMMC_STA_DABORT_Pos (11U)
+#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
+#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
+#define SDMMC_STA_DPSMACT_Pos (12U)
+#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
+#define SDMMC_STA_CPSMACT_Pos (13U)
+#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
+#define SDMMC_STA_TXFIFOHE_Pos (14U)
+#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos (15U)
+#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos (16U)
+#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDMMC_STA_RXFIFOF_Pos (17U)
+#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDMMC_STA_TXFIFOE_Pos (18U)
+#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDMMC_STA_RXFIFOE_Pos (19U)
+#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDMMC_STA_BUSYD0_Pos (20U)
+#define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
+#define SDMMC_STA_BUSYD0END_Pos (21U)
+#define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
+#define SDMMC_STA_SDIOIT_Pos (22U)
+#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDMMC_STA_ACKFAIL_Pos (23U)
+#define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
+#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
+#define SDMMC_STA_VSWEND_Pos (25U)
+#define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
+#define SDMMC_STA_CKSTOP_Pos (26U)
+#define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
+#define SDMMC_STA_IDMATE_Pos (27U)
+#define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
+#define SDMMC_STA_IDMABTC_Pos (28U)
+#define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
+
+/******************* Bit definition for SDMMC_ICR register *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos (5U)
+#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDMMC_ICR_CMDRENDC_Pos (6U)
+#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDMMC_ICR_CMDSENTC_Pos (7U)
+#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDMMC_ICR_DATAENDC_Pos (8U)
+#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDMMC_ICR_DHOLDC_Pos (9U)
+#define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos (10U)
+#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDMMC_ICR_DABORTC_Pos (11U)
+#define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
+#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
+#define SDMMC_ICR_SDIOITC_Pos (22U)
+#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDMMC_ICR_ACKFAILC_Pos (23U)
+#define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos (25U)
+#define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
+#define SDMMC_ICR_CKSTOPC_Pos (26U)
+#define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
+#define SDMMC_ICR_IDMATEC_Pos (27U)
+#define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
+#define SDMMC_ICR_IDMABTCC_Pos (28U)
+#define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
+
+/****************** Bit definition for SDMMC_MASK register *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDMMC_MASK_RXOVERRIE_Pos (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDMMC_MASK_CMDRENDIE_Pos (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDMMC_MASK_DATAENDIE_Pos (8U)
+#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDMMC_MASK_DHOLDIE_Pos (9U)
+#define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
+#define SDMMC_MASK_DBCKENDIE_Pos (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDMMC_MASK_DABORTIE_Pos (11U)
+#define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted Interrupt Enable */
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos (22U)
+#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos (25U)
+#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
+#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDMMC_FIFO register *******************/
+#define SDMMC_FIFO_FIFODATA_Pos (0U)
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/****************** Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos (0U)
+#define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos (2U)
+#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
+#define SPI_CR1_CRCL_Pos (11U)
+#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos (3U)
+#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos (8U)
+#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
+#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
+#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
+#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos (12U)
+#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos (13U)
+#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos (14U)
+#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos (9U)
+#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos (11U)
+#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* OCTOSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for OCTOSPI_CR register *******************/
+#define OCTOSPI_CR_EN_Pos (0U)
+#define OCTOSPI_CR_EN_Msk (0x1U << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
+#define OCTOSPI_CR_ABORT_Pos (1U)
+#define OCTOSPI_CR_ABORT_Msk (0x1U << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
+#define OCTOSPI_CR_DMAEN_Pos (2U)
+#define OCTOSPI_CR_DMAEN_Msk (0x1U << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define OCTOSPI_CR_TCEN_Pos (3U)
+#define OCTOSPI_CR_TCEN_Msk (0x1U << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define OCTOSPI_CR_DQM_Pos (6U)
+#define OCTOSPI_CR_DQM_Msk (0x1U << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
+#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
+#define OCTOSPI_CR_FSEL_Pos (7U)
+#define OCTOSPI_CR_FSEL_Msk (0x1U << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
+#define OCTOSPI_CR_FTHRES_Pos (8U)
+#define OCTOSPI_CR_FTHRES_Msk (0x1FU << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
+#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
+#define OCTOSPI_CR_TEIE_Pos (16U)
+#define OCTOSPI_CR_TEIE_Msk (0x1U << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define OCTOSPI_CR_TCIE_Pos (17U)
+#define OCTOSPI_CR_TCIE_Msk (0x1U << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define OCTOSPI_CR_FTIE_Pos (18U)
+#define OCTOSPI_CR_FTIE_Msk (0x1U << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define OCTOSPI_CR_SMIE_Pos (19U)
+#define OCTOSPI_CR_SMIE_Msk (0x1U << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define OCTOSPI_CR_TOIE_Pos (20U)
+#define OCTOSPI_CR_TOIE_Msk (0x1U << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define OCTOSPI_CR_APMS_Pos (22U)
+#define OCTOSPI_CR_APMS_Msk (0x1U << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
+#define OCTOSPI_CR_PMM_Pos (23U)
+#define OCTOSPI_CR_PMM_Msk (0x1U << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define OCTOSPI_CR_FMODE_Pos (28U)
+#define OCTOSPI_CR_FMODE_Msk (0x3U << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
+#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
+#define OCTOSPI_CR_FMODE_0 (0x1U << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
+#define OCTOSPI_CR_FMODE_1 (0x2U << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
+
+/**************** Bit definition for OCTOSPI_DCR1 register ******************/
+#define OCTOSPI_DCR1_CKMODE_Pos (0U)
+#define OCTOSPI_DCR1_CKMODE_Msk (0x1U << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
+#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define OCTOSPI_DCR1_FRCK_Pos (1U)
+#define OCTOSPI_DCR1_FRCK_Msk (0x1U << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
+#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
+#define OCTOSPI_DCR1_CSHT_Pos (8U)
+#define OCTOSPI_DCR1_CSHT_Msk (0x7U << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
+#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
+#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
+#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FU << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
+#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
+#define OCTOSPI_DCR1_MTYP_Pos (24U)
+#define OCTOSPI_DCR1_MTYP_Msk (0x7U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
+#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
+#define OCTOSPI_DCR1_MTYP_0 (0x1U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
+#define OCTOSPI_DCR1_MTYP_1 (0x2U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
+#define OCTOSPI_DCR1_MTYP_2 (0x4U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+
+/**************** Bit definition for OCTOSPI_DCR2 register ******************/
+#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
+#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFU << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
+#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
+#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
+#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
+#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
+#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
+#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
+#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
+
+/**************** Bit definition for OCTOSPI_DCR3 register ******************/
+#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
+#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FU << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
+#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */
+
+/***************** Bit definition for OCTOSPI_SR register *******************/
+#define OCTOSPI_SR_TEF_Pos (0U)
+#define OCTOSPI_SR_TEF_Msk (0x1U << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define OCTOSPI_SR_TCF_Pos (1U)
+#define OCTOSPI_SR_TCF_Msk (0x1U << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define OCTOSPI_SR_FTF_Pos (2U)
+#define OCTOSPI_SR_FTF_Msk (0x1U << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
+#define OCTOSPI_SR_SMF_Pos (3U)
+#define OCTOSPI_SR_SMF_Msk (0x1U << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define OCTOSPI_SR_TOF_Pos (4U)
+#define OCTOSPI_SR_TOF_Msk (0x1U << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define OCTOSPI_SR_BUSY_Pos (5U)
+#define OCTOSPI_SR_BUSY_Msk (0x1U << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
+#define OCTOSPI_SR_FLEVEL_Pos (8U)
+#define OCTOSPI_SR_FLEVEL_Msk (0x3FU << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
+#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
+
+/**************** Bit definition for OCTOSPI_FCR register *******************/
+#define OCTOSPI_FCR_CTEF_Pos (0U)
+#define OCTOSPI_FCR_CTEF_Msk (0x1U << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define OCTOSPI_FCR_CTCF_Pos (1U)
+#define OCTOSPI_FCR_CTCF_Msk (0x1U << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define OCTOSPI_FCR_CSMF_Pos (3U)
+#define OCTOSPI_FCR_CSMF_Msk (0x1U << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define OCTOSPI_FCR_TOF_Pos (8U)
+#define OCTOSPI_FCR_TOF_Msk (0x1U << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */
+#define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */
+
+/**************** Bit definition for OCTOSPI_DLR register *******************/
+#define OCTOSPI_DLR_DL_Pos (0U)
+#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFU << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
+
+/***************** Bit definition for OCTOSPI_AR register *******************/
+#define OCTOSPI_AR_ADDRESS_Pos (0U)
+#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
+
+/***************** Bit definition for OCTOSPI_DR register *******************/
+#define OCTOSPI_DR_DATA_Pos (0U)
+#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFU << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
+
+/*************** Bit definition for OCTOSPI_PSMKR register ******************/
+#define OCTOSPI_PSMKR_MASK_Pos (0U)
+#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
+
+/*************** Bit definition for OCTOSPI_PSMAR register ******************/
+#define OCTOSPI_PSMAR_MATCH_Pos (0U)
+#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
+
+/**************** Bit definition for OCTOSPI_PIR register *******************/
+#define OCTOSPI_PIR_INTERVAL_Pos (0U)
+#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFU << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
+
+/**************** Bit definition for OCTOSPI_CCR register *******************/
+#define OCTOSPI_CCR_IMODE_Pos (0U)
+#define OCTOSPI_CCR_IMODE_Msk (0x7U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
+#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
+#define OCTOSPI_CCR_IMODE_0 (0x1U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
+#define OCTOSPI_CCR_IMODE_1 (0x2U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
+#define OCTOSPI_CCR_IMODE_2 (0x4U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
+#define OCTOSPI_CCR_IDTR_Pos (3U)
+#define OCTOSPI_CCR_IDTR_Msk (0x1U << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
+#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
+#define OCTOSPI_CCR_ISIZE_Pos (4U)
+#define OCTOSPI_CCR_ISIZE_Msk (0x3U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
+#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
+#define OCTOSPI_CCR_ISIZE_0 (0x1U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
+#define OCTOSPI_CCR_ISIZE_1 (0x2U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
+#define OCTOSPI_CCR_ADMODE_Pos (8U)
+#define OCTOSPI_CCR_ADMODE_Msk (0x7U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
+#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
+#define OCTOSPI_CCR_ADMODE_0 (0x1U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
+#define OCTOSPI_CCR_ADMODE_1 (0x2U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
+#define OCTOSPI_CCR_ADMODE_2 (0x4U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define OCTOSPI_CCR_ADDTR_Pos (11U)
+#define OCTOSPI_CCR_ADDTR_Msk (0x1U << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
+#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
+#define OCTOSPI_CCR_ADSIZE_Pos (12U)
+#define OCTOSPI_CCR_ADSIZE_Msk (0x3U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
+#define OCTOSPI_CCR_ADSIZE_0 (0x1U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define OCTOSPI_CCR_ADSIZE_1 (0x2U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define OCTOSPI_CCR_ABMODE_Pos (16U)
+#define OCTOSPI_CCR_ABMODE_Msk (0x7U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
+#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
+#define OCTOSPI_CCR_ABMODE_0 (0x1U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
+#define OCTOSPI_CCR_ABMODE_1 (0x2U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
+#define OCTOSPI_CCR_ABMODE_2 (0x4U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
+#define OCTOSPI_CCR_ABDTR_Pos (19U)
+#define OCTOSPI_CCR_ABDTR_Msk (0x1U << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
+#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
+#define OCTOSPI_CCR_ABSIZE_Pos (20U)
+#define OCTOSPI_CCR_ABSIZE_Msk (0x3U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
+#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
+#define OCTOSPI_CCR_ABSIZE_0 (0x1U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
+#define OCTOSPI_CCR_ABSIZE_1 (0x2U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
+#define OCTOSPI_CCR_DMODE_Pos (24U)
+#define OCTOSPI_CCR_DMODE_Msk (0x7U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
+#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
+#define OCTOSPI_CCR_DMODE_0 (0x1U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define OCTOSPI_CCR_DMODE_1 (0x2U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define OCTOSPI_CCR_DMODE_2 (0x4U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
+#define OCTOSPI_CCR_DDTR_Pos (27U)
+#define OCTOSPI_CCR_DDTR_Msk (0x1U << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
+#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
+#define OCTOSPI_CCR_DQSE_Pos (29U)
+#define OCTOSPI_CCR_DQSE_Msk (0x1U << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
+#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
+#define OCTOSPI_CCR_SIOO_Pos (31U)
+#define OCTOSPI_CCR_SIOO_Msk (0x1U << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
+#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
+
+/**************** Bit definition for OCTOSPI_TCR register *******************/
+#define OCTOSPI_TCR_DCYC_Pos (0U)
+#define OCTOSPI_TCR_DCYC_Msk (0x1FU << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
+#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
+#define OCTOSPI_TCR_DHQC_Pos (28U)
+#define OCTOSPI_TCR_DHQC_Msk (0x1U << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
+#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
+#define OCTOSPI_TCR_SSHIFT_Pos (30U)
+#define OCTOSPI_TCR_SSHIFT_Msk (0x1U << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
+#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
+
+/***************** Bit definition for OCTOSPI_IR register *******************/
+#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
+#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
+
+/**************** Bit definition for OCTOSPI_ABR register *******************/
+#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
+#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
+
+/**************** Bit definition for OCTOSPI_LPTR register ******************/
+#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
+#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFU << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
+
+/**************** Bit definition for OCTOSPI_WCCR register ******************/
+#define OCTOSPI_WCCR_IMODE_Pos (0U)
+#define OCTOSPI_WCCR_IMODE_Msk (0x7U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
+#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
+#define OCTOSPI_WCCR_IMODE_0 (0x1U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
+#define OCTOSPI_WCCR_IMODE_1 (0x2U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
+#define OCTOSPI_WCCR_IMODE_2 (0x4U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
+#define OCTOSPI_WCCR_IDTR_Pos (3U)
+#define OCTOSPI_WCCR_IDTR_Msk (0x1U << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
+#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
+#define OCTOSPI_WCCR_ISIZE_Pos (4U)
+#define OCTOSPI_WCCR_ISIZE_Msk (0x3U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
+#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
+#define OCTOSPI_WCCR_ISIZE_0 (0x1U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
+#define OCTOSPI_WCCR_ISIZE_1 (0x2U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
+#define OCTOSPI_WCCR_ADMODE_Pos (8U)
+#define OCTOSPI_WCCR_ADMODE_Msk (0x7U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
+#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
+#define OCTOSPI_WCCR_ADMODE_0 (0x1U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
+#define OCTOSPI_WCCR_ADMODE_1 (0x2U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
+#define OCTOSPI_WCCR_ADMODE_2 (0x4U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
+#define OCTOSPI_WCCR_ADDTR_Pos (11U)
+#define OCTOSPI_WCCR_ADDTR_Msk (0x1U << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
+#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
+#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
+#define OCTOSPI_WCCR_ADSIZE_Msk (0x3U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
+#define OCTOSPI_WCCR_ADSIZE_0 (0x1U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define OCTOSPI_WCCR_ADSIZE_1 (0x2U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define OCTOSPI_WCCR_ABMODE_Pos (16U)
+#define OCTOSPI_WCCR_ABMODE_Msk (0x7U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
+#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
+#define OCTOSPI_WCCR_ABMODE_0 (0x1U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
+#define OCTOSPI_WCCR_ABMODE_1 (0x2U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
+#define OCTOSPI_WCCR_ABMODE_2 (0x4U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
+#define OCTOSPI_WCCR_ABDTR_Pos (19U)
+#define OCTOSPI_WCCR_ABDTR_Msk (0x1U << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
+#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
+#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
+#define OCTOSPI_WCCR_ABSIZE_Msk (0x3U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
+#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
+#define OCTOSPI_WCCR_ABSIZE_0 (0x1U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
+#define OCTOSPI_WCCR_ABSIZE_1 (0x2U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
+#define OCTOSPI_WCCR_DMODE_Pos (24U)
+#define OCTOSPI_WCCR_DMODE_Msk (0x7U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
+#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
+#define OCTOSPI_WCCR_DMODE_0 (0x1U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
+#define OCTOSPI_WCCR_DMODE_1 (0x2U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
+#define OCTOSPI_WCCR_DMODE_2 (0x4U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
+#define OCTOSPI_WCCR_DDTR_Pos (27U)
+#define OCTOSPI_WCCR_DDTR_Msk (0x1U << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
+#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
+#define OCTOSPI_WCCR_DQSE_Pos (29U)
+#define OCTOSPI_WCCR_DQSE_Msk (0x1U << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
+#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
+#define OCTOSPI_WCCR_SIOO_Pos (31U)
+#define OCTOSPI_WCCR_SIOO_Msk (0x1U << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */
+#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
+
+/**************** Bit definition for OCTOSPI_WTCR register ******************/
+#define OCTOSPI_WTCR_DCYC_Pos (0U)
+#define OCTOSPI_WTCR_DCYC_Msk (0x1FU << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
+#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
+
+/**************** Bit definition for OCTOSPI_WIR register *******************/
+#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
+#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
+
+/**************** Bit definition for OCTOSPI_WABR register ******************/
+#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
+#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
+
+/**************** Bit definition for OCTOSPI_HLCR register ******************/
+#define OCTOSPI_HLCR_LM_Pos (0U)
+#define OCTOSPI_HLCR_LM_Msk (0x1U << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
+#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
+#define OCTOSPI_HLCR_WZL_Pos (1U)
+#define OCTOSPI_HLCR_WZL_Msk (0x1U << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
+#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
+#define OCTOSPI_HLCR_TACC_Pos (8U)
+#define OCTOSPI_HLCR_TACC_Msk (0xFFU << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
+#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
+#define OCTOSPI_HLCR_TRWR_Pos (16U)
+#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
+#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
+
+/******************************************************************************/
+/* */
+/* OCTOSPIM */
+/* */
+/******************************************************************************/
+/*************** Bit definition for OCTOSPIM_PCR register *******************/
+#define OCTOSPIM_PCR_CLKEN_Pos (0U)
+#define OCTOSPIM_PCR_CLKEN_Msk (0x1U << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
+#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
+#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
+#define OCTOSPIM_PCR_CLKSRC_Msk (0x1U << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
+#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
+#define OCTOSPIM_PCR_DQSEN_Pos (4U)
+#define OCTOSPIM_PCR_DQSEN_Msk (0x1U << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
+#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
+#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
+#define OCTOSPIM_PCR_DQSSRC_Msk (0x1U << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
+#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
+#define OCTOSPIM_PCR_NCSEN_Pos (8U)
+#define OCTOSPIM_PCR_NCSEN_Msk (0x1U << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
+#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
+#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
+#define OCTOSPIM_PCR_NCSSRC_Msk (0x1U << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
+#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
+#define OCTOSPIM_PCR_IOLEN_Pos (16U)
+#define OCTOSPIM_PCR_IOLEN_Msk (0x1U << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
+#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
+#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
+#define OCTOSPIM_PCR_IOLSRC_Msk (0x3U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
+#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
+#define OCTOSPIM_PCR_IOLSRC_0 (0x1U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
+#define OCTOSPIM_PCR_IOLSRC_1 (0x2U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
+#define OCTOSPIM_PCR_IOHEN_Pos (24U)
+#define OCTOSPIM_PCR_IOHEN_Msk (0x1U << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
+#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
+#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
+#define OCTOSPIM_PCR_IOHSRC_Msk (0x3U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
+#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
+#define OCTOSPIM_PCR_IOHSRC_0 (0x1U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
+#define OCTOSPIM_PCR_IOHSRC_1 (0x2U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
+#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
+
+/****************** Bit definition for SYSCFG_CFGR1 register ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos (0U)
+#define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
+#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
+#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
+#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
+#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
+#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
+#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_SCSR register ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
+#define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
+#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
+
+/****************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_CLL_Pos (0U)
+#define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos (1U)
+#define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos (2U)
+#define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos (3U)
+#define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos (8U)
+#define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
+
+/****************** Bit definition for SYSCFG_SWPR register ****************/
+#define SYSCFG_SWPR_PAGE0_Pos (0U)
+#define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos (1U)
+#define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos (2U)
+#define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos (3U)
+#define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos (4U)
+#define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos (5U)
+#define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos (6U)
+#define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos (7U)
+#define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos (8U)
+#define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos (9U)
+#define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos (10U)
+#define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos (11U)
+#define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos (12U)
+#define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos (13U)
+#define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos (14U)
+#define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos (15U)
+#define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos (16U)
+#define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos (17U)
+#define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos (18U)
+#define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos (19U)
+#define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos (20U)
+#define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos (21U)
+#define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos (22U)
+#define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos (23U)
+#define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos (24U)
+#define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos (25U)
+#define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos (26U)
+#define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos (27U)
+#define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos (28U)
+#define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos (29U)
+#define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos (30U)
+#define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos (31U)
+#define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
+
+/****************** Bit definition for SYSCFG_SWPR2 register ***************/
+#define SYSCFG_SWPR2_PAGE32_Pos (0U)
+#define SYSCFG_SWPR2_PAGE32_Msk (0x1U << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2 Write protection page 32*/
+#define SYSCFG_SWPR2_PAGE33_Pos (1U)
+#define SYSCFG_SWPR2_PAGE33_Msk (0x1U << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2 Write protection page 33*/
+#define SYSCFG_SWPR2_PAGE34_Pos (2U)
+#define SYSCFG_SWPR2_PAGE34_Msk (0x1U << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2 Write protection page 34*/
+#define SYSCFG_SWPR2_PAGE35_Pos (3U)
+#define SYSCFG_SWPR2_PAGE35_Msk (0x1U << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2 Write protection page 35*/
+#define SYSCFG_SWPR2_PAGE36_Pos (4U)
+#define SYSCFG_SWPR2_PAGE36_Msk (0x1U << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2 Write protection page 36*/
+#define SYSCFG_SWPR2_PAGE37_Pos (5U)
+#define SYSCFG_SWPR2_PAGE37_Msk (0x1U << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2 Write protection page 37*/
+#define SYSCFG_SWPR2_PAGE38_Pos (6U)
+#define SYSCFG_SWPR2_PAGE38_Msk (0x1U << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2 Write protection page 38*/
+#define SYSCFG_SWPR2_PAGE39_Pos (7U)
+#define SYSCFG_SWPR2_PAGE39_Msk (0x1U << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2 Write protection page 39*/
+#define SYSCFG_SWPR2_PAGE40_Pos (8U)
+#define SYSCFG_SWPR2_PAGE40_Msk (0x1U << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2 Write protection page 40*/
+#define SYSCFG_SWPR2_PAGE41_Pos (9U)
+#define SYSCFG_SWPR2_PAGE41_Msk (0x1U << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2 Write protection page 41*/
+#define SYSCFG_SWPR2_PAGE42_Pos (10U)
+#define SYSCFG_SWPR2_PAGE42_Msk (0x1U << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2 Write protection page 42*/
+#define SYSCFG_SWPR2_PAGE43_Pos (11U)
+#define SYSCFG_SWPR2_PAGE43_Msk (0x1U << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2 Write protection page 43*/
+#define SYSCFG_SWPR2_PAGE44_Pos (12U)
+#define SYSCFG_SWPR2_PAGE44_Msk (0x1U << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2 Write protection page 44*/
+#define SYSCFG_SWPR2_PAGE45_Pos (13U)
+#define SYSCFG_SWPR2_PAGE45_Msk (0x1U << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2 Write protection page 45*/
+#define SYSCFG_SWPR2_PAGE46_Pos (14U)
+#define SYSCFG_SWPR2_PAGE46_Msk (0x1U << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2 Write protection page 46*/
+#define SYSCFG_SWPR2_PAGE47_Pos (15U)
+#define SYSCFG_SWPR2_PAGE47_Msk (0x1U << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2 Write protection page 47*/
+#define SYSCFG_SWPR2_PAGE48_Pos (16U)
+#define SYSCFG_SWPR2_PAGE48_Msk (0x1U << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2 Write protection page 48*/
+#define SYSCFG_SWPR2_PAGE49_Pos (17U)
+#define SYSCFG_SWPR2_PAGE49_Msk (0x1U << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2 Write protection page 49*/
+#define SYSCFG_SWPR2_PAGE50_Pos (18U)
+#define SYSCFG_SWPR2_PAGE50_Msk (0x1U << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2 Write protection page 50*/
+#define SYSCFG_SWPR2_PAGE51_Pos (19U)
+#define SYSCFG_SWPR2_PAGE51_Msk (0x1U << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2 Write protection page 51*/
+#define SYSCFG_SWPR2_PAGE52_Pos (20U)
+#define SYSCFG_SWPR2_PAGE52_Msk (0x1U << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2 Write protection page 52*/
+#define SYSCFG_SWPR2_PAGE53_Pos (21U)
+#define SYSCFG_SWPR2_PAGE53_Msk (0x1U << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2 Write protection page 53*/
+#define SYSCFG_SWPR2_PAGE54_Pos (22U)
+#define SYSCFG_SWPR2_PAGE54_Msk (0x1U << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2 Write protection page 54*/
+#define SYSCFG_SWPR2_PAGE55_Pos (23U)
+#define SYSCFG_SWPR2_PAGE55_Msk (0x1U << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2 Write protection page 55*/
+#define SYSCFG_SWPR2_PAGE56_Pos (24U)
+#define SYSCFG_SWPR2_PAGE56_Msk (0x1U << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2 Write protection page 56*/
+#define SYSCFG_SWPR2_PAGE57_Pos (25U)
+#define SYSCFG_SWPR2_PAGE57_Msk (0x1U << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2 Write protection page 57*/
+#define SYSCFG_SWPR2_PAGE58_Pos (26U)
+#define SYSCFG_SWPR2_PAGE58_Msk (0x1U << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2 Write protection page 58*/
+#define SYSCFG_SWPR2_PAGE59_Pos (27U)
+#define SYSCFG_SWPR2_PAGE59_Msk (0x1U << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2 Write protection page 59*/
+#define SYSCFG_SWPR2_PAGE60_Pos (28U)
+#define SYSCFG_SWPR2_PAGE60_Msk (0x1U << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2 Write protection page 60*/
+#define SYSCFG_SWPR2_PAGE61_Pos (29U)
+#define SYSCFG_SWPR2_PAGE61_Msk (0x1U << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2 Write protection page 61*/
+#define SYSCFG_SWPR2_PAGE62_Pos (30U)
+#define SYSCFG_SWPR2_PAGE62_Msk (0x1U << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2 Write protection page 62*/
+#define SYSCFG_SWPR2_PAGE63_Pos (31U)
+#define SYSCFG_SWPR2_PAGE63_Msk (0x1U << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2 Write protection page 63*/
+
+/****************** Bit definition for SYSCFG_SKR register ****************/
+#define SYSCFG_SKR_KEY_Pos (0U)
+#define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
+
+
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos (11U)
+#define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos (16U)
+#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos (18U)
+#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos (20U)
+#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos (8U)
+#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos (13U)
+#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos (16U)
+#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos (17U)
+#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
+
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+#define TIM_EGR_B2G_Pos (8U)
+#define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
+
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE_Pos (2U)
+#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos (3U)
+#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos (4U)
+#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos (7U)
+#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos (10U)
+#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos (11U)
+#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos (12U)
+#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos (15U)
+#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos (16U)
+#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos (17U)
+#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos (20U)
+#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos (21U)
+#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos (31U)
+#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5_Pos (0U)
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos (29U)
+#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos (30U)
+#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos (31U)
+#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6_Pos (0U)
+#define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos (16U)
+#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos (20U)
+#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos (24U)
+#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos (25U)
+#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM1_OR1 register *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
+#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
+
+#define TIM1_OR1_TI1_RMP_Pos (4U)
+#define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
+
+/******************* Bit definition for TIM1_OR2 register *******************/
+#define TIM1_OR2_BKINE_Pos (0U)
+#define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos (1U)
+#define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos (2U)
+#define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos (8U)
+#define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos (9U)
+#define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos (10U)
+#define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos (11U)
+#define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos (14U)
+#define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM1_OR3 register *******************/
+#define TIM1_OR3_BK2INE_Pos (0U)
+#define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos (1U)
+#define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos (2U)
+#define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
+#define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos (9U)
+#define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos (10U)
+#define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos (11U)
+#define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
+
+/******************* Bit definition for TIM8_OR1 register *******************/
+#define TIM8_OR1_TI1_RMP_Pos (4U)
+#define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
+
+/******************* Bit definition for TIM8_OR2 register *******************/
+#define TIM8_OR2_BKINE_Pos (0U)
+#define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos (1U)
+#define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos (2U)
+#define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos (8U)
+#define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos (9U)
+#define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos (10U)
+#define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos (11U)
+#define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos (14U)
+#define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM8_OR3 register *******************/
+#define TIM8_OR3_BK2INE_Pos (0U)
+#define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos (1U)
+#define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos (2U)
+#define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
+#define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos (9U)
+#define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos (10U)
+#define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos (11U)
+#define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
+
+/******************* Bit definition for TIM2_OR1 register *******************/
+#define TIM2_OR1_ITR1_RMP_Pos (0U)
+#define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos (1U)
+#define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos (2U)
+#define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
+
+/******************* Bit definition for TIM2_OR2 register *******************/
+#define TIM2_OR2_ETRSEL_Pos (14U)
+#define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM3_OR1 register *******************/
+#define TIM3_OR1_TI1_RMP_Pos (0U)
+#define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM3_OR2 register *******************/
+#define TIM3_OR2_ETRSEL_Pos (14U)
+#define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
+
+/******************* Bit definition for TIM15_OR1 register ******************/
+#define TIM15_OR1_TI1_RMP_Pos (0U)
+#define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos (1U)
+#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for TIM15_OR2 register ******************/
+#define TIM15_OR2_BKINE_Pos (0U)
+#define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos (1U)
+#define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos (2U)
+#define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos (8U)
+#define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos (9U)
+#define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos (10U)
+#define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos (11U)
+#define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************* Bit definition for TIM16_OR1 register ******************/
+#define TIM16_OR1_TI1_RMP_Pos (0U)
+#define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM16_OR2 register ******************/
+#define TIM16_OR2_BKINE_Pos (0U)
+#define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos (1U)
+#define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos (2U)
+#define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos (8U)
+#define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos (9U)
+#define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos (10U)
+#define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos (11U)
+#define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************* Bit definition for TIM17_OR1 register ******************/
+#define TIM17_OR1_TI1_RMP_Pos (0U)
+#define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
+
+/******************* Bit definition for TIM17_OR2 register ******************/
+#define TIM17_OR2_BKINE_Pos (0U)
+#define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
+#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos (1U)
+#define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos (2U)
+#define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos (8U)
+#define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos (9U)
+#define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
+#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos (10U)
+#define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos (11U)
+#define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register ********************/
+#define LPTIM_OR_OR_Pos (0U)
+#define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
+#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
+#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_EN_Pos (0U)
+#define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos (2U)
+#define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos (4U)
+#define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos (7U)
+#define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
+#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos (9U)
+#define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
+#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+#define COMP_CSR_POLARITY_Pos (15U)
+#define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos (16U)
+#define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
+#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
+#define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos (18U)
+#define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos (22U)
+#define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
+#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos (23U)
+#define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
+#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos (30U)
+#define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos (31U)
+#define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos (1U)
+#define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos (2U)
+#define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos (4U)
+#define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos (8U)
+#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos (10U)
+#define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos (12U)
+#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos (13U)
+#define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos (14U)
+#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos (15U)
+#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
+
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAEN_Pos (0U)
+#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos (1U)
+#define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos (2U)
+#define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos (4U)
+#define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos (8U)
+#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos (10U)
+#define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos (12U)
+#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos (13U)
+#define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos (14U)
+#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos (15U)
+#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos (31U)
+#define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAEN_Pos (0U)
+#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos (1U)
+#define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos (2U)
+#define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos (4U)
+#define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos (8U)
+#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos (10U)
+#define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos (12U)
+#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos (13U)
+#define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos (14U)
+#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos (15U)
+#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
+
+/******************* Bit definition for OPAMP_OTR register ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_OTR register ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_OTR register ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP_LPOTR register ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_LPOTR register ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_LPOTR register ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define USART_TCBGT_SUPPORT
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1U << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
+// MBED
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1U << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
+// MBED
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos (29U)
+#define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
+#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos (30U)
+#define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
+#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos (31U)
+#define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
+#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_SLVEN_Pos (0U)
+#define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
+#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos (3U)
+#define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+/* MBED */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+/* MBED */
+#define USART_CR3_TXFTIE_Pos (23U)
+#define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x02000000 */
+#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos (24U)
+#define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos (25U)
+#define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG[2:0] bits (RXFIFO threshold configuration) */
+#define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos (28U)
+#define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x02000000 */
+#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos (29U)
+#define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFTCFG[2:0] bits (TXFIFO threshold configuration) */
+#define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos (5U)
+#define USART_ISR_RXNE_RXFNE_Msk (0x1U << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos (7U)
+#define USART_ISR_TXE_TXFNF_Msk (0x1U << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos (13U)
+#define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */
+#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos (23U)
+#define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
+#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
+#define USART_ISR_RXFF_Pos (24U)
+#define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x00800000 */
+#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos (25U)
+#define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
+#define USART_ISR_RXFT_Pos (26U)
+#define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
+#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
+#define USART_ISR_TXFT_Pos (27U)
+#define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
+#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos (2U)
+#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos (5U)
+#define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
+#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos (7U)
+#define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos (13U)
+#define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
+#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Legacy defines */
+#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
+#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
+#define USART_ICR_NCF USART_ICR_NECF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************* Bit definition for USART_PRESC register ******************/
+#define USART_PRESC_PRESCALER_Pos (0U)
+#define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
+
+/******************************************************************************/
+/* */
+/* VREFBUF */
+/* */
+/******************************************************************************/
+/******************* Bit definition for VREFBUF_CSR register ****************/
+#define VREFBUF_CSR_ENVR_Pos (0U)
+#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos (1U)
+#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
+#define VREFBUF_CSR_VRS_Pos (2U)
+#define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
+#define VREFBUF_CSR_VRR_Pos (3U)
+#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
+
+/******************* Bit definition for VREFBUF_CCR register ******************/
+#define VREFBUF_CCR_TRIM_Pos (0U)
+#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
+
+/******************** Bit definition for DBGMCU_APB2FZ register ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
+
+/******************** Bit definition for USB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_DCDET_Pos (0U)
+#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos (1U)
+#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos (2U)
+#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos (19U)
+#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos (20U)
+#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
+
+/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+
+/******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
+#define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
+
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1) || \
+ ((INSTANCE) == DFSDM1_Filter2) || \
+ ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3) || \
+ ((INSTANCE) == DFSDM1_Channel4) || \
+ ((INSTANCE) == DFSDM1_Channel5) || \
+ ((INSTANCE) == DFSDM1_Channel6) || \
+ ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5) || \
+ ((INSTANCE) == DMA2_Channel6) || \
+ ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3) || \
+ ((INSTANCE) == I2C4))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* OSPI Instances *******************************/
+#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1) || \
+ ((INSTANCE) == OCTOSPI2))
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+ ((INSTANCE) == SAI1_Block_B) || \
+ ((INSTANCE) == SAI2_Block_A) || \
+ ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3) || \
+ ((INSTANCE) == I2C4))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
+ ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/*********************** UART Instances : FIFO mode ***************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn TIM8_UP_IRQn
+#define HASH_RNG_IRQn RNG_IRQn
+#define HASH_CRS_IRQn CRS_IRQn
+#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler RNG_IRQHandler
+#define HASH_CRS_IRQHandler CRS_IRQHandler
+#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4R5xx_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,257 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32L4xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l4xx
+ * @{
+ */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+ application
+ */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+ !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+ !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+ !defined (STM32L496xx) && !defined (STM32L4A6xx) && \
+ !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
+ /* #define STM32L431xx */ /*!< STM32L431xx Devices */
+ /* #define STM32L432xx */ /*!< STM32L432xx Devices */
+ /* #define STM32L433xx */ /*!< STM32L433xx Devices */
+ /* #define STM32L442xx */ /*!< STM32L442xx Devices */
+ /* #define STM32L443xx */ /*!< STM32L443xx Devices */
+ /* #define STM32L451xx */ /*!< STM32L451xx Devices */
+ /* #define STM32L452xx */ /*!< STM32L452xx Devices */
+ /* #define STM32L462xx */ /*!< STM32L462xx Devices */
+ /* #define STM32L471xx */ /*!< STM32L471xx Devices */
+ /* #define STM32L475xx */ /*!< STM32L475xx Devices */
+ /* #define STM32L476xx */ /*!< STM32L476xx Devices */
+ /* #define STM32L485xx */ /*!< STM32L485xx Devices */
+ /* #define STM32L486xx */ /*!< STM32L486xx Devices */
+ /* #define STM32L496xx */ /*!< STM32L496xx Devices */
+ /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
+ #define STM32L4R5xx /*!< STM32L4R5xx Devices */
+ /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
+ /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
+ /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
+ /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
+ /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number
+ */
+#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32L431xx)
+ #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+ #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+ #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+ #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+ #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+ #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+ #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+ #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+ #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+ #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+ #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+ #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+ #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+ #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+ #include "stm32l4a6xx.h"
+#elif defined(STM32L4R5xx)
+ #include "stm32l4r5xx.h"
+#elif defined(STM32L4R7xx)
+ #include "stm32l4r7xx.h"
+#elif defined(STM32L4R9xx)
+ #include "stm32l4r9xx.h"
+#elif defined(STM32L4S5xx)
+ #include "stm32l4s5xx.h"
+#elif defined(STM32L4S7xx)
+ #include "stm32l4s7xx.h"
+#elif defined(STM32L4S9xx)
+ #include "stm32l4s9xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/system_stm32l4xx.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,125 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l4xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/us_ticker_data.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __US_TICKER_DATA_H
+#define __US_TICKER_DATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_BIT_WIDTH 32 // 16 or 32
+
+#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __US_TICKER_DATA_H
--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c Thu Nov 08 11:46:34 2018 +0000
@@ -82,13 +82,27 @@
obj->handle.Init.DMAContinuousRequests = DISABLE;
obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun
obj->handle.Init.OversamplingMode = DISABLE; // No oversampling
+#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
+ obj->handle.Init.DFSDMConfig = 0;
+#endif
+
+#if defined(TARGET_DISCO_L496AG)
+ /* VREF+ is not connected to VDDA by default */
+ /* Use 2.5V as reference (instead of 3.3V) for internal channels calculation */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ HAL_SYSCFG_VREFBUF_VoltageScalingConfig(SYSCFG_VREFBUF_VOLTAGE_SCALE1); /* VREF_OUT2 = 2.5 V */
+ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
+ if (HAL_SYSCFG_EnableVREFBUF() != HAL_OK) {
+ error("HAL_SYSCFG_EnableVREFBUF issue\n");
+ }
+#endif /* TARGET_DISCO_L496AG */
// Enable ADC clock
__HAL_RCC_ADC_CLK_ENABLE();
__HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
- error("Cannot initialize ADC");
+ error("Cannot initialize ADC\n");
}
// ADC calibration is done only once
--- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Thu Nov 08 11:46:34 2018 +0000 @@ -143,8 +143,4 @@ }; #endif -/* STM32L4 HAL doesn't provide this API called in rtc_api.c */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) - #endif -
--- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -137,8 +137,9 @@
return -1;
}
- /* Clear OPTVERR bit set on virgin samples */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+
/* Get the 1st page to erase */
FirstPage = GetPage(address);
/* MBED HAL erases 1 page / sector at a time */
@@ -194,6 +195,9 @@
return -1;
}
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+
/* Program the user Flash area word by word */
StartAddress = address;
--- a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c Thu Nov 08 11:46:34 2018 +0000
@@ -38,8 +38,6 @@
extern uint32_t __mbed_sbrk_start;
extern uint32_t __mbed_krbs_start;
-#define STM32L4_HEAP_ALIGN 32
-#define STM32L4_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1))
/**
* The default implementation of _sbrk() (in platform/mbed_retarget.cpp) for GCC_ARM requires one-region model (heap and
* stack share one region), which doesn't fit two-region model (heap and stack are two distinct regions), for example,
@@ -50,10 +48,10 @@
void *__wrap__sbrk(int incr)
{
static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
- uint32_t heap_ind_old = STM32L4_ALIGN_UP(heap_ind, STM32L4_HEAP_ALIGN);
- uint32_t heap_ind_new = STM32L4_ALIGN_UP(heap_ind_old + incr, STM32L4_HEAP_ALIGN);
+ uint32_t heap_ind_old = heap_ind;
+ uint32_t heap_ind_new = heap_ind_old + incr;
- if (heap_ind_new > &__mbed_krbs_start) {
+ if (heap_ind_new > (uint32_t)&__mbed_krbs_start) {
errno = ENOMEM;
return (void *) - 1;
}
--- a/targets/TARGET_STM/gpio_irq_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/gpio_irq_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
-#include <stddef.h>
+#include <stdbool.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "pinmap.h"
@@ -268,11 +268,11 @@
uint32_t gpio_idx = pin_lines_desc[STM_PIN(obj->pin)].gpio_idx;
gpio_channel_t *gpio_channel = &channels[obj->irq_index];
- gpio_irq_disable(obj);
gpio_channel->pin_mask &= ~(1 << gpio_idx);
gpio_channel->channel_ids[gpio_idx] = 0;
gpio_channel->channel_gpio[gpio_idx] = 0;
gpio_channel->channel_pin[gpio_idx] = 0;
+ gpio_irq_disable(obj);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
@@ -325,10 +325,20 @@
void gpio_irq_disable(gpio_irq_t *obj)
{
+ const uint32_t pin_index = STM_PIN(obj->pin);
+ const uint32_t gpio_idx = pin_lines_desc[pin_index].gpio_idx;
+ const uint32_t pin_mask = 1 << gpio_idx;
+ const uint32_t irq_index = pin_lines_desc[pin_index].irq_index;
+ const gpio_channel_t *const gpio_channel = &channels[irq_index];
+
/* Clear EXTI line configuration */
- LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
- LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
- LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
- NVIC_DisableIRQ(obj->irq_n);
- NVIC_ClearPendingIRQ(obj->irq_n);
+ LL_EXTI_DisableRisingTrig_0_31(1 << pin_index);
+ LL_EXTI_DisableFallingTrig_0_31(1 << pin_index);
+ LL_EXTI_DisableIT_0_31(1 << pin_index);
+
+ const bool no_more_pins_on_vector = (gpio_channel->pin_mask & ~pin_mask) == 0;
+ if (no_more_pins_on_vector) {
+ NVIC_DisableIRQ(obj->irq_n);
+ NVIC_ClearPendingIRQ(obj->irq_n);
+ }
}
--- a/targets/TARGET_STM/i2c_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/i2c_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -590,6 +590,17 @@
#endif
// Disable reload mode
handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
+
+ // Ensure the transmission is started before sending a stop
+ if ((handle->Instance->CR2 & (uint32_t)I2C_CR2_RD_WRN) == 0) {
+ timeout = FLAG_TIMEOUT;
+ while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXIS)) {
+ if ((timeout--) == 0) {
+ return I2C_ERROR_BUS_BUSY;
+ }
+ }
+ }
+
// Generate the STOP condition
handle->Instance->CR2 |= I2C_CR2_STOP;
--- a/targets/TARGET_STM/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -145,9 +145,6 @@
__HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM);
HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF);
-
- /* Need to write a compare value in order to get LPTIM_FLAG_CMPOK in set_interrupt */
- __HAL_LPTIM_COMPARE_SET(&LptimHandle, 0);
}
static void LPTIM1_IRQHandler(void)
@@ -194,14 +191,14 @@
LptimHandle.Instance = LPTIM1;
irq_handler = (void (*)(void))lp_ticker_irq_handler;
+ __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK);
+ __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp);
/* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */
/* Any successive write before the CMPOK flag be set, will lead to unpredictable results */
while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) {
}
- __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK);
- __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
- __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp);
+ lp_ticker_clear_interrupt();
NVIC_EnableIRQ(LPTIM1_IRQn);
}
@@ -209,6 +206,7 @@
void lp_ticker_fire_interrupt(void)
{
lp_Fired = 1;
+ irq_handler = (void (*)(void))lp_ticker_irq_handler;
NVIC_SetPendingIRQ(LPTIM1_IRQn);
NVIC_EnableIRQ(LPTIM1_IRQn);
}
@@ -217,9 +215,6 @@
{
NVIC_DisableIRQ(LPTIM1_IRQn);
LptimHandle.Instance = LPTIM1;
- /* Waiting last write operation completion */
- while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) {
- }
}
void lp_ticker_clear_interrupt(void)
@@ -229,7 +224,10 @@
NVIC_ClearPendingIRQ(LPTIM1_IRQn);
}
-
+void lp_ticker_free(void)
+{
+ lp_ticker_disable_interrupt();
+}
/*****************************************************************/
/* lpticker_lptim config is 0 or not defined in json config file */
@@ -260,7 +258,6 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- lp_ticker_disable_interrupt();
rtc_set_wake_up_timer(timestamp);
}
@@ -276,7 +273,12 @@
void lp_ticker_clear_interrupt(void)
{
- NVIC_DisableIRQ(RTC_WKUP_IRQn);
+ lp_ticker_disable_interrupt();
+}
+
+void lp_ticker_free(void)
+{
+ lp_ticker_disable_interrupt();
}
#endif /* MBED_CONF_TARGET_LPTICKER_LPTIM */
--- a/targets/TARGET_STM/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/mbed_overrides.c Thu Nov 08 11:46:34 2018 +0000
@@ -54,5 +54,21 @@
SetSysClock();
SystemCoreClockUpdate();
+ /* Start LSI clock for RTC */
+#if DEVICE_RTC
+#if !MBED_CONF_TARGET_LSE_AVAILABLE
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+ if (__HAL_RCC_GET_RTC_SOURCE() != RCC_RTCCLKSOURCE_NO_CLK) {
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("Init : cannot initialize LSI\n");
+ }
+ }
+#endif /* ! MBED_CONF_TARGET_LSE_AVAILABLE */
+#endif /* DEVICE_RTC */
+
mbed_sdk_inited = 1;
}
--- a/targets/TARGET_STM/mbed_rtx.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000
@@ -25,7 +25,8 @@
defined(TARGET_STM32L476RG) ||\
defined(TARGET_STM32L476JG) ||\
defined(TARGET_STM32L476VG) ||\
- defined(TARGET_STM32L486RG))
+ defined(TARGET_STM32L486RG) ||\
+ defined(TARGET_STM32L471QG))
/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */
#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\
defined(__IAR_SYSTEMS_ICC__ )) &&\
@@ -36,10 +37,10 @@
#endif /* toolchains */
#elif (defined(TARGET_STM32F051R8) ||\
- defined(TARGET_STM32F100RB) ||\
- defined(TARGET_STM32L031K6) ||\
- defined(TARGET_STM32L053C8) ||\
- defined(TARGET_STM32L053R8))
+ defined(TARGET_STM32F100RB) ||\
+ defined(TARGET_STM32L031K6) ||\
+ defined(TARGET_STM32L053C8) ||\
+ defined(TARGET_STM32L053R8))
#define INITIAL_SP (0x20002000UL)
#elif (defined(TARGET_STM32F303K8) ||\
@@ -73,13 +74,11 @@
#elif defined(TARGET_STM32L443RC)
#define INITIAL_SP (0x2000C000UL)
-#elif defined(TARGET_STM32L432KC) ||\
- defined (TARGET_STM32L433RC)
-#define INITIAL_SP (0x20010000UL)
-
#elif (defined(TARGET_STM32F303RE) ||\
defined(TARGET_STM32F303ZE) ||\
- defined(TARGET_STM32F401VC))
+ defined(TARGET_STM32F401VC) ||\
+ defined(TARGET_STM32L432KC) ||\
+ defined(TARGET_STM32L433RC))
#define INITIAL_SP (0x20010000UL)
#elif defined(TARGET_STM32L152RE)
@@ -120,6 +119,9 @@
defined(TARGET_STM32F769NI))
#define INITIAL_SP (0x20080000UL)
+#elif defined(TARGET_STM32L4R5ZI)
+#define INITIAL_SP (0x200A0000UL)
+
#else
#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file"
#endif
@@ -136,4 +138,23 @@
#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
#endif
+#if (defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB))
+#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION))
+extern uint32_t __StackLimit;
+extern uint32_t __StackTop;
+extern uint32_t __end__;
+extern uint32_t __HeapLimit;
+#define HEAP_START ((unsigned char*) &__end__)
+#define HEAP_SIZE ((uint32_t)((uint32_t) &__HeapLimit - (uint32_t) HEAP_START))
+#define ISR_STACK_START ((unsigned char*) &__StackLimit)
+#define ISR_STACK_SIZE ((uint32_t)((uint32_t) &__StackTop - (uint32_t) &__StackLimit))
+#endif
+
+#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
+#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE
+#endif
+#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072
+
+#endif
+
#endif // MBED_MBED_RTX_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/qspi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,321 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if DEVICE_QSPI
+
+#include "qspi_api.h"
+#include "mbed_error.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+/* Max amount of flash size is 4Gbytes */
+/* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 1<<31 */
+#define QSPI_FLASH_SIZE_DEFAULT 0x80000000
+
+void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command)
+{
+ // TODO: shift these around to get more dynamic mapping
+ switch (command->instruction.bus_width) {
+ case QSPI_CFG_BUS_SINGLE:
+ st_command->InstructionMode = QSPI_INSTRUCTION_1_LINE;
+ break;
+ case QSPI_CFG_BUS_DUAL:
+ st_command->InstructionMode = QSPI_INSTRUCTION_2_LINES;
+ break;
+ case QSPI_CFG_BUS_QUAD:
+ st_command->InstructionMode = QSPI_INSTRUCTION_4_LINES;
+ break;
+ default:
+ st_command->InstructionMode = QSPI_INSTRUCTION_NONE;
+ break;
+ }
+
+ st_command->Instruction = command->instruction.value;
+ st_command->DummyCycles = command->dummy_count,
+ // these are target specific settings, use default values
+ st_command->SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
+ st_command->DdrMode = QSPI_DDR_MODE_DISABLE;
+ st_command->DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
+
+ switch (command->address.bus_width) {
+ case QSPI_CFG_BUS_SINGLE:
+ st_command->AddressMode = QSPI_ADDRESS_1_LINE;
+ break;
+ case QSPI_CFG_BUS_DUAL:
+ st_command->AddressMode = QSPI_ADDRESS_2_LINES;
+ break;
+ case QSPI_CFG_BUS_QUAD:
+ st_command->AddressMode = QSPI_ADDRESS_4_LINES;
+ break;
+ default:
+ st_command->AddressMode = QSPI_ADDRESS_NONE;
+ break;
+ }
+
+ if (command->address.disabled == true) {
+ st_command->AddressMode = QSPI_ADDRESS_NONE;
+ st_command->AddressSize = 0;
+ } else {
+ st_command->Address = command->address.value;
+ /* command->address.size needs to be shifted by QUADSPI_CCR_ADSIZE_Pos */
+ st_command->AddressSize = (command->address.size << QUADSPI_CCR_ADSIZE_Pos) & QUADSPI_CCR_ADSIZE_Msk;
+ }
+
+ switch (command->alt.bus_width) {
+ case QSPI_CFG_BUS_SINGLE:
+ st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_1_LINE;
+ break;
+ case QSPI_CFG_BUS_DUAL:
+ st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_2_LINES;
+ break;
+ case QSPI_CFG_BUS_QUAD:
+ st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES;
+ break;
+ default:
+ st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+ break;
+ }
+
+ if (command->alt.disabled == true) {
+ st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+ st_command->AlternateBytesSize = 0;
+ } else {
+ st_command->AlternateBytes = command->alt.value;
+ /* command->AlternateBytesSize needs to be shifted by QUADSPI_CCR_ABSIZE_Pos */
+ st_command->AlternateBytesSize = (command->alt.size << QUADSPI_CCR_ABSIZE_Pos) & QUADSPI_CCR_ABSIZE_Msk;
+ st_command->AlternateBytesSize = command->alt.size;
+ }
+
+ switch (command->data.bus_width) {
+ case QSPI_CFG_BUS_SINGLE:
+ st_command->DataMode = QSPI_DATA_1_LINE;
+ break;
+ case QSPI_CFG_BUS_DUAL:
+ st_command->DataMode = QSPI_DATA_2_LINES;
+ break;
+ case QSPI_CFG_BUS_QUAD:
+ st_command->DataMode = QSPI_DATA_4_LINES;
+ break;
+ default:
+ st_command->DataMode = QSPI_DATA_NONE;
+ break;
+ }
+
+ st_command->NbData = 0;
+}
+
+
+qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
+{
+ // Enable interface clock for QSPI
+ __HAL_RCC_QSPI_CLK_ENABLE();
+
+ // Reset QSPI
+ __HAL_RCC_QSPI_FORCE_RESET();
+ __HAL_RCC_QSPI_RELEASE_RESET();
+
+ // Reset handle internal state
+ obj->handle.State = HAL_QSPI_STATE_RESET;
+ obj->handle.Lock = HAL_UNLOCKED;
+
+ // Set default QSPI handle values
+ obj->handle.Init.ClockPrescaler = 1;
+ obj->handle.Init.FifoThreshold = 1;
+ obj->handle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+ obj->handle.Init.FlashSize = POSITION_VAL(QSPI_FLASH_SIZE_DEFAULT) - 1;
+ obj->handle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
+ obj->handle.Init.ClockMode = QSPI_CLOCK_MODE_0;
+#ifdef QSPI_DUALFLASH_ENABLE
+ obj->handle.Init.FlashID = QSPI_FLASH_ID_1;
+ obj->handle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
+#endif
+
+ obj->handle.Init.ClockMode = mode == 0 ? QSPI_CLOCK_MODE_0 : QSPI_CLOCK_MODE_3;
+
+ QSPIName qspiio0name = (QSPIName)pinmap_peripheral(io0, PinMap_QSPI_DATA);
+ QSPIName qspiio1name = (QSPIName)pinmap_peripheral(io1, PinMap_QSPI_DATA);
+ QSPIName qspiio2name = (QSPIName)pinmap_peripheral(io2, PinMap_QSPI_DATA);
+ QSPIName qspiio3name = (QSPIName)pinmap_peripheral(io3, PinMap_QSPI_DATA);
+ QSPIName qspiclkname = (QSPIName)pinmap_peripheral(sclk, PinMap_QSPI_SCLK);
+ QSPIName qspisselname = (QSPIName)pinmap_peripheral(ssel, PinMap_QSPI_SSEL);
+
+ QSPIName qspi_data_first = (QSPIName)pinmap_merge(qspiio0name, qspiio1name);
+ QSPIName qspi_data_second = (QSPIName)pinmap_merge(qspiio2name, qspiio3name);
+ QSPIName qspi_data_third = (QSPIName)pinmap_merge(qspiclkname, qspisselname);
+
+ if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
+ qspi_data_first != qspi_data_third) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ // tested all combinations, take first
+ obj->handle.Instance = (QUADSPI_TypeDef *)qspi_data_first;
+
+ // pinmap for pins (enable clock)
+ obj->io0 = io0;
+ pinmap_pinout(io0, PinMap_QSPI_DATA);
+ obj->io1 = io1;
+ pinmap_pinout(io1, PinMap_QSPI_DATA);
+ obj->io2 = io2;
+ pinmap_pinout(io2, PinMap_QSPI_DATA);
+ obj->io3 = io3;
+ pinmap_pinout(io3, PinMap_QSPI_DATA);
+
+ obj->sclk = sclk;
+ pinmap_pinout(sclk, PinMap_QSPI_SCLK);
+ obj->ssel = ssel;
+ pinmap_pinout(ssel, PinMap_QSPI_SSEL);
+
+ if (HAL_QSPI_Init(&obj->handle) != HAL_OK) {
+ return QSPI_STATUS_ERROR;
+ }
+ qspi_frequency(obj, hz);
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_free(qspi_t *obj)
+{
+ if(HAL_QSPI_DeInit(&obj->handle) != HAL_OK) {
+ return QSPI_STATUS_ERROR;
+ }
+
+ // Reset QSPI
+ __HAL_RCC_QSPI_FORCE_RESET();
+ __HAL_RCC_QSPI_RELEASE_RESET();
+
+ // Disable interface clock for QSPI
+ __HAL_RCC_QSPI_CLK_DISABLE();
+
+ // Configure GPIOs
+ pin_function(obj->io0, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->io1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->io2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->io3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ (void)(obj);
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_frequency(qspi_t *obj, int hz)
+{
+ qspi_status_t status = QSPI_STATUS_OK;
+
+ // HCLK drives QSPI
+ int div = HAL_RCC_GetHCLKFreq() / hz;
+ if (div > 256 || div < 1) {
+ status = QSPI_STATUS_INVALID_PARAMETER;
+ return status;
+ }
+
+ obj->handle.Init.ClockPrescaler = div - 1;
+
+ if (HAL_QSPI_Init(&obj->handle) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ }
+ return status;
+}
+
+qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
+{
+ QSPI_CommandTypeDef st_command;
+ qspi_prepare_command(command, &st_command);
+
+ st_command.NbData = *length;
+ qspi_status_t status = QSPI_STATUS_OK;
+
+ if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ return status;
+ }
+
+ if (HAL_QSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ }
+
+ return status;
+}
+
+qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
+{
+ QSPI_CommandTypeDef st_command;
+ qspi_prepare_command(command, &st_command);
+
+ st_command.NbData = *length;
+ qspi_status_t status = QSPI_STATUS_OK;
+
+ if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ return status;
+ }
+
+ if (HAL_QSPI_Receive(&obj->handle, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ }
+
+ return status;
+}
+
+qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
+{
+ qspi_status_t status = QSPI_STATUS_OK;
+
+ if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) {
+ // only command, no rx or tx
+ QSPI_CommandTypeDef st_command;
+ qspi_prepare_command(command, &st_command);
+
+ st_command.NbData = 1;
+ st_command.DataMode = QSPI_DATA_NONE; /* Instruction only */
+ if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+ status = QSPI_STATUS_ERROR;
+ return status;
+ }
+ } else {
+ // often just read a register, check if we need to transmit anything prior reading
+ if (tx_data != NULL && tx_size) {
+ size_t tx_length = tx_size;
+ status = qspi_write(obj, command, tx_data, &tx_length);
+ if (status != QSPI_STATUS_OK) {
+ return status;
+ }
+ }
+
+ if (rx_data != NULL && rx_size) {
+ size_t rx_length = rx_size;
+ status = qspi_read(obj, command, rx_data, &rx_length);
+ }
+ }
+ return status;
+}
+
+#endif
+
+/** @}*/
--- a/targets/TARGET_STM/rtc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/rtc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -36,8 +36,8 @@
#include "mbed_critical.h"
#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
-volatile uint32_t LP_continuous_time = 0;
-volatile uint32_t LP_last_RTC_time = 0;
+volatile uint32_t LPTICKER_counter = 0;
+volatile uint32_t LPTICKER_RTC_time = 0;
#endif
static int RTC_inited = 0;
@@ -60,14 +60,12 @@
#if MBED_CONF_TARGET_LSE_AVAILABLE
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
error("Cannot initialize RTC with LSE\n");
}
- __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
@@ -76,19 +74,13 @@
error("PeriphClkInitStruct RTC failed with LSE\n");
}
#else /* MBED_CONF_TARGET_LSE_AVAILABLE */
- // Reset Backup domain
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
-
- // Enable LSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
error("Cannot initialize RTC with LSI\n");
}
- __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
@@ -116,14 +108,14 @@
#endif /* TARGET_STM32F1 */
if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
- error("RTC initialization failed");
+ error("RTC initialization failed\n");
}
#if !(TARGET_STM32F1) && !(TARGET_STM32F2)
/* STM32F1 : there are no shadow registers */
/* STM32F2 : shadow registers can not be bypassed */
if (HAL_RTCEx_EnableBypassShadow(&RtcHandle) != HAL_OK) {
- error("EnableBypassShadow error");
+ error("EnableBypassShadow error\n");
}
#endif /* TARGET_STM32F1 || TARGET_STM32F2 */
}
@@ -149,51 +141,15 @@
For date, there is no specific register, only a software structure.
It is then not a problem to not use shifts.
*/
-#if TARGET_STM32F1
time_t rtc_read(void)
{
- RTC_DateTypeDef dateStruct = {0};
- RTC_TimeTypeDef timeStruct = {0};
- struct tm timeinfo;
+#if TARGET_STM32F1
RtcHandle.Instance = RTC;
-
- // Read actual date and time
- // Warning: the time must be read first!
- HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
- HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
-
- /* date information is null before first write procedure */
- /* set 01/01/1970 as default values */
- if (dateStruct.Year == 0) {
- dateStruct.Year = 2 ;
- dateStruct.Month = 1 ;
- dateStruct.Date = 1 ;
- }
-
- // Setup a tm structure based on the RTC
- /* tm_wday information is ignored by _rtc_maketime */
- /* tm_isdst information is ignored by _rtc_maketime */
- timeinfo.tm_mon = dateStruct.Month - 1;
- timeinfo.tm_mday = dateStruct.Date;
- timeinfo.tm_year = dateStruct.Year + 68;
- timeinfo.tm_hour = timeStruct.Hours;
- timeinfo.tm_min = timeStruct.Minutes;
- timeinfo.tm_sec = timeStruct.Seconds;
-
- // Convert to timestamp
- time_t t;
- if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
- return 0;
- }
-
- return t;
-}
+ return RTC_ReadTimeCounter(&RtcHandle);
#else /* TARGET_STM32F1 */
-time_t rtc_read(void)
-{
struct tm timeinfo;
/* Since the shadow registers are bypassed we have to read the time twice and compare them until both times are the same */
@@ -231,12 +187,23 @@
}
return t;
+
+#endif /* TARGET_STM32F1 */
}
-#endif /* TARGET_STM32F1 */
+
void rtc_write(time_t t)
{
+#if TARGET_STM32F1
+
+ RtcHandle.Instance = RTC;
+ if (RTC_WriteTimeCounter(&RtcHandle, t) != HAL_OK) {
+ error("RTC_WriteTimeCounter error\n");
+ }
+
+#else /* TARGET_STM32F1 */
+
RTC_DateTypeDef dateStruct = {0};
RTC_TimeTypeDef timeStruct = {0};
@@ -261,22 +228,19 @@
timeStruct.Hours = timeinfo.tm_hour;
timeStruct.Minutes = timeinfo.tm_min;
timeStruct.Seconds = timeinfo.tm_sec;
-
-#if !(TARGET_STM32F1)
timeStruct.TimeFormat = RTC_HOURFORMAT_24;
timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
-#endif /* TARGET_STM32F1 */
#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
- /* Need to update LP_continuous_time value before new RTC time */
+ /* Before setting the new time, we need to update the LPTICKER_counter value */
+ /* rtc_read_lp function is then called */
rtc_read_lp();
- /* LP_last_RTC_time value is updated with the new RTC time */
- LP_last_RTC_time = timeStruct.Seconds + timeStruct.Minutes * 60 + timeStruct.Hours * 60 * 60;
-
- /* Save current SSR */
- uint32_t Read_SubSeconds = (uint32_t)(RTC->SSR);
+ /* In rtc_read_lp, LPTICKER_RTC_time value has been updated with the current time */
+ /* We need now to overwrite the value with the new RTC time */
+ /* Note that when a new RTC time is set by HW, the RTC SubSeconds counter is reset to PREDIV_S_VALUE */
+ LPTICKER_RTC_time = (timeStruct.Seconds + timeStruct.Minutes * 60 + timeStruct.Hours * 60 * 60) * PREDIV_S_VALUE;
#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
// Change the RTC current date/time
@@ -287,12 +251,8 @@
error("HAL_RTC_SetTime error\n");
}
-#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
- while (Read_SubSeconds != (RTC->SSR)) {
- }
-#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
-
core_util_critical_section_exit();
+#endif /* TARGET_STM32F1 */
}
int rtc_isenabled(void)
@@ -341,11 +301,18 @@
uint32_t rtc_read_lp(void)
{
+ /* RTC_time_tick is the addition of the RTC time register (in second) and the RTC sub-second register
+ * This time value is breaking each 24h (= 86400s = 0x15180)
+ * In order to get a U32 continuous time information, we use an internal counter : LPTICKER_counter
+ * This counter is the addition of each spent time since last function call
+ * Current RTC time is saved into LPTICKER_RTC_time
+ * NB: rtc_read_lp() output is not the time in us, but the LPTICKER_counter (frequency LSE/4 = 8kHz => 122us)
+ */
+ core_util_critical_section_enter();
struct tm timeinfo;
/* Since the shadow registers are bypassed we have to read the time twice and compare them until both times are the same */
/* We don't have to read date as we bypass shadow registers */
- uint32_t Read_SecondFraction = (uint32_t)(RTC->PRER & RTC_PRER_PREDIV_S);
uint32_t Read_time = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
uint32_t Read_SubSeconds = (uint32_t)(RTC->SSR);
@@ -358,17 +325,18 @@
timeinfo.tm_min = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_MNT | RTC_TR_MNU)) >> 8));
timeinfo.tm_sec = RTC_Bcd2ToByte((uint8_t)((Read_time & (RTC_TR_ST | RTC_TR_SU)) >> 0));
- uint32_t RTC_time_s = timeinfo.tm_sec + timeinfo.tm_min * 60 + timeinfo.tm_hour * 60 * 60; // Max 0x0001-517F => * 8191 + 8191 = 0x2A2E-AE80
+ uint32_t RTC_time_tick = (timeinfo.tm_sec + timeinfo.tm_min * 60 + timeinfo.tm_hour * 60 * 60) * PREDIV_S_VALUE + PREDIV_S_VALUE - Read_SubSeconds; // Max 0x0001-517F * 8191 + 8191 = 0x2A2E-AE80
- if (LP_last_RTC_time <= RTC_time_s) {
- LP_continuous_time += (RTC_time_s - LP_last_RTC_time);
+ if (LPTICKER_RTC_time <= RTC_time_tick) {
+ LPTICKER_counter += (RTC_time_tick - LPTICKER_RTC_time);
} else {
- /* Add 24h */
- LP_continuous_time += (24 * 60 * 60 + RTC_time_s - LP_last_RTC_time);
+ /* When RTC time is 0h00.01 and was 11H59.59, difference is "current time + 24h - previous time" */
+ LPTICKER_counter += (RTC_time_tick + 24 * 60 * 60 * PREDIV_S_VALUE - LPTICKER_RTC_time);
}
- LP_last_RTC_time = RTC_time_s;
+ LPTICKER_RTC_time = RTC_time_tick;
- return LP_continuous_time * PREDIV_S_VALUE + Read_SecondFraction - Read_SubSeconds;
+ core_util_critical_section_exit();
+ return LPTICKER_counter;
}
void rtc_set_wake_up_timer(timestamp_t timestamp)
@@ -388,7 +356,9 @@
WakeUpCounter = 0xFFFF;
}
+ core_util_critical_section_enter();
RtcHandle.Instance = RTC;
+ HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle);
if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, WakeUpCounter, RTC_WAKEUPCLOCK_RTCCLK_DIV4) != HAL_OK) {
error("rtc_set_wake_up_timer init error\n");
}
@@ -396,6 +366,7 @@
NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)RTC_IRQHandler);
irq_handler = (void (*)(void))lp_ticker_irq_handler;
NVIC_EnableIRQ(RTC_WKUP_IRQn);
+ core_util_critical_section_exit();
}
void rtc_fire_interrupt(void)
@@ -410,10 +381,7 @@
void rtc_deactivate_wake_up_timer(void)
{
RtcHandle.Instance = RTC;
- __HAL_RTC_WRITEPROTECTION_DISABLE(&RtcHandle);
- __HAL_RTC_WAKEUPTIMER_DISABLE(&RtcHandle);
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&RtcHandle, RTC_IT_WUT);
- __HAL_RTC_WRITEPROTECTION_ENABLE(&RtcHandle);
+ HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle);
NVIC_DisableIRQ(RTC_WKUP_IRQn);
}
--- a/targets/TARGET_STM/rtc_api_hal.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_STM/rtc_api_hal.h Thu Nov 08 11:46:34 2018 +0000 @@ -81,7 +81,7 @@ /* PREDIV_S : 15-bit synchronous prescaler */ /* PREDIV_S is set in order to get a 1 Hz clock */ -#define PREDIV_S_VALUE RTC_CLOCK / (PREDIV_A_VALUE + 1) - 1 +#define PREDIV_S_VALUE (RTC_CLOCK / (PREDIV_A_VALUE + 1) - 1) /** Synchronise the RTC shadow registers. *
--- a/targets/TARGET_STM/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -354,7 +354,7 @@
if (!__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.HSIState = RCC_LSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
}
@@ -536,7 +536,9 @@
#if defined(LPUART1_BASE)
if (huart->Instance == LPUART1) {
if (obj_s->baudrate <= 9600) {
+#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_LSE)
HAL_UARTEx_EnableClockStopMode(huart);
+#endif
HAL_UARTEx_EnableStopMode(huart);
} else {
HAL_UARTEx_DisableClockStopMode(huart);
@@ -660,10 +662,10 @@
return -1;
}
-/* Function to protect deep sleep while a seral Tx is ongoing on not complete
- * yet. Returns 1 if there is at least 1 serial instance with ongoing ransfer
- * 0 otherwise.
- */
+/* Function used to protect deep sleep while a serial transmission is on-going.
+.* Returns 1 if there is at least 1 serial instance with an on-going transfer
+ * and 0 otherwise.
+*/
int serial_is_tx_ongoing(void) {
int TxOngoing = 0;
@@ -757,8 +759,13 @@
}
#endif
- /* If Tx is ongoing, then transfer is */
return TxOngoing;
}
+#else
+
+int serial_is_tx_ongoing(void) {
+ return 0;
+}
+
#endif /* DEVICE_SERIAL */
--- a/targets/TARGET_STM/sleep.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -52,7 +52,7 @@
// On L4 platforms we've seen unstable PLL CLK configuraiton
-// when DEEP SLEEP exits just few µs after being entered
+// when DEEP SLEEP exits just few µs after being entered
// So we need to force MSI usage before setting clocks again
static void ForcePeriphOutofDeepSleep(void)
{
@@ -151,13 +151,32 @@
core_util_critical_section_enter();
// Request to enter SLEEP mode
+#if TARGET_STM32L4
+ // State Transitions (see 5.3 Low-power modes, Fig. 13):
+ // * (opt): Low Power Run (LPR) Mode -> Run Mode
+ // * Run Mode -> Sleep
+ // --- Wait for Interrupt --
+ // * Sleep -> Run Mode
+ // * (opt): Run Mode -> Low Power Run Mode
+
+ // [5.4.1 Power control register 1 (PWR_CR1)]
+ // LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).
+ int lowPowerMode = PWR->CR1 & PWR_CR1_LPR;
+ if (lowPowerMode) {
+ HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+ } else {
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+ }
+#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
// Enable IRQs
core_util_critical_section_exit();
}
extern int serial_is_tx_ongoing(void);
+extern int mbed_sdk_inited;
void hal_deepsleep(void)
{
@@ -200,6 +219,10 @@
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
#endif /* TARGET_STM32L4 */
+ /* Prevent HAL_GetTick() from using ticker_read_us() to read the
+ * us_ticker timestamp until the us_ticker context is restored. */
+ mbed_sdk_inited = 0;
+
// Verify Clock Out of Deep Sleep
ForceClockOutofDeepSleep();
@@ -214,6 +237,10 @@
restore_timer_ctx();
+ /* us_ticker context restored, allow HAL_GetTick() to read the us_ticker
+ * timestamp via ticker_read_us() again. */
+ mbed_sdk_inited = 1;
+
// Enable IRQs
core_util_critical_section_exit();
}
--- a/targets/TARGET_STM/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_STM/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -206,6 +206,7 @@
{
// Timer is already initialized in HAL_InitTick()
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
}
uint32_t us_ticker_read()
@@ -256,3 +257,10 @@
__HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, timer_ccr1_reg);
TIM_MST->DIER = timer_dier_reg;
}
+
+void us_ticker_free(void)
+{
+ HAL_TIM_OC_Stop(&TimMasterHandle, TIM_CHANNEL_1);
+ us_ticker_disable_interrupt();
+}
+
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -136,6 +136,14 @@
} UARTName;
#endif
+#if DEVICE_QSPI
+typedef enum {
+#ifdef QSPI0_BASE
+ QSPI_0 = QSPI0_BASE,
+#endif
+} QSPIName;
+#endif
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralPins.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralPins.h Thu Nov 08 11:46:34 2018 +0000 @@ -68,5 +68,15 @@ extern const PinMap PinMap_CAN_RX[]; #endif +#if DEVICE_QSPI +/************QSPI**************/ +extern const PinMap PinMap_QSPI_DQ0[]; +extern const PinMap PinMap_QSPI_DQ1[]; +extern const PinMap PinMap_QSPI_DQ2[]; +extern const PinMap PinMap_QSPI_DQ3[]; +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_CS0[]; #endif +#endif +
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_MICRO/efm32gg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data
+ RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_ARM_STD/efm32gg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x200000DC 0x0001FF24 { ; RW data
+ RW_IRAM1 0x200000E0 0x0001FF20 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -13,10 +13,6 @@
* the stack where main runs is determined via the RTOS. */
STACK_SIZE = 0x400;
-/* This is the guaranteed minimum available heap size for an application. When
- * uVisor is enabled, this is also the maximum available heap size. The
- * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
- * heap and the page heap in uVisor applications. */
HEAP_SIZE = 0x6000;
#if !defined(MBED_APP_START)
@@ -34,8 +30,8 @@
}
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG */
-__vector_size = 0xDC;
+ * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 4(8-byte aligned) bytes for EFM32GG */
+__vector_size = 0xE0;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -73,10 +69,6 @@
SECTIONS
{
- /* Note: The uVisor expects the text section at a fixed location, as specified
- by the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_FLASH_OFFSET = 0x100;
- __UVISOR_FLASH_START = ORIGIN(FLASH) + __UVISOR_FLASH_OFFSET;
.text :
{
KEEP(*(.vectors))
@@ -84,12 +76,6 @@
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
- /* uVisor code and data */
- . = __UVISOR_FLASH_OFFSET;
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
*(.text*)
@@ -133,7 +119,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -151,7 +137,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -161,48 +147,6 @@
} > FLASH
*/
- /* uVisor own memory and private box memories
- /* If uVisor shares the SRAM with the OS/app, ensure that this section is
- * the first one after the VTOR relocation section. */
- /* Note: The uVisor expects this section at a fixed location, as specified
- by the porting process configuration parameter: SRAM_OFFSET. */
- __UVISOR_SRAM_OFFSET = 0x0;
- __UVISOR_SRAM_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* Protected uVisor own BSS section */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* Protected uVisor boxes' static memories */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- . = ALIGN(32);
- __uvisor_bss_end = .;
- } > RAM
-
- /* Heap space for the page allocator
- /* If uVisor shares the SRAM with the OS/app, ensure that this section is
- * the first one after the uVisor BSS section. Otherwise, ensure it is the
- * first one after the VTOR relocation section. */
- .page_heap (NOLOAD) :
- {
- . = ALIGN(32);
- __uvisor_page_start = .;
- KEEP(*(.keep.uvisor.page_heap))
- . = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) / 8);
- __uvisor_page_end = .;
- } > RAM
.data :
{
@@ -216,23 +160,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -240,43 +184,12 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
- /* uVisor configuration section
- * This section must be located after all other flash regions. */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uVisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* Pointers to the uVisor secure boxes configuration tables */
- /* Note: Do not add any further alignment here, as uVisor will need to
- have access to the exact list of pointers. */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* Pointers to all boxes register gateways. These are grouped here to
- allow discoverability and firmware verification. */
- __uvisor_register_gateway_ptr_start = .;
- KEEP(*(.keep.uvisor.register_gateway_ptr))
- __uvisor_register_gateway_ptr_end = .;
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } > FLASH
/* Uninitialized data section
* This region is not initialized by the C/C++ library and can be used to
@@ -293,24 +206,22 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
.heap (NOLOAD):
{
- __uvisor_heap_start = .;
__HeapBase = .;
__end__ = .;
end = __end__;
_end = __end__;
. += HEAP_SIZE;
__HeapLimit = .;
- __uvisor_heap_end = .;
} > RAM
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
@@ -319,11 +230,4 @@
ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(FLASH);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM);
- __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
- __uvisor_public_sram_start = __uvisor_sram_start;
- __uvisor_public_sram_end = __uvisor_sram_end;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/startup_efm32gg.S Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/startup_efm32gg.S Thu Nov 08 11:46:34 2018 +0000
@@ -127,10 +127,6 @@
blx r0
#endif
-#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
- ldr r0, =uvisor_init
- blx r0
-#endif /* defined(FEATURE_UVISOR) && defined(UVISOR_SUPPORTED) */
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_IAR/efm32gg990f1024.icf Thu Nov 08 11:46:34 2018 +0000 @@ -11,8 +11,8 @@ define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000DB; -define symbol __ICFEDIT_region_RAM_start__ = 0x200000DC; +define symbol __NVIC_end__ = 0x200000DF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000E0; define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c Thu Nov 08 11:46:34 2018 +0000
@@ -579,3 +579,53 @@
#endif
};
#endif
+
+#if DEVICE_QSPI
+MBED_WEAK const PinMap PinMap_QSPI_DQ0[] = {
+#ifdef QSPI0_BASE
+ {PD9, QSPI_0, 0},
+ {PA2, QSPI_0, 1},
+ {PG1, QSPI_0, 2},
+#endif
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DQ1[] = {
+#ifdef QSPI0_BASE
+ {PD10, QSPI_0, 0},
+ {PA3, QSPI_0, 1},
+ {PG2, QSPI_0, 2},
+#endif
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DQ2[] = {
+#ifdef QSPI0_BASE
+ {PD11, QSPI_0, 0},
+ {PA4, QSPI_0, 1},
+ {PG3, QSPI_0, 2},
+#endif
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DQ3[] = {
+#ifdef QSPI0_BASE
+ {PD12, QSPI_0, 0},
+ {PA5, QSPI_0, 1},
+ {PG4, QSPI_0, 2},
+#endif
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+#ifdef QSPI0_BASE
+ {PF6, QSPI_0, 0},
+ {PE14, QSPI_0, 1},
+ {PG0, QSPI_0, 2},
+#endif
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_CS0[] = {
+#ifdef QSPI0_BASE
+ {PF7, QSPI_0, 0},
+ {PA0, QSPI_0, 1},
+ {PG9, QSPI_0, 2},
+#endif
+};
+#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/TARGET_EFM32GG11_STK3701/PinNames.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/TARGET_EFM32GG11_STK3701/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -76,7 +76,16 @@
/* Board Controller */
STDIO_UART_TX = USBTX,
- STDIO_UART_RX = USBRX
+ STDIO_UART_RX = USBRX,
+
+ /* On-board MX25R3235F */
+ QSPI_FLASH1_IO0 = PG1,
+ QSPI_FLASH1_IO1 = PG2,
+ QSPI_FLASH1_IO2 = PG3,
+ QSPI_FLASH1_IO3 = PG4,
+ QSPI_FLASH1_SCK = PG0,
+ QSPI_FLASH1_CSN = PG9,
+
} PinName;
#ifdef __cplusplus
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/TOOLCHAIN_GCC_ARM/efm32gg11.ld Thu Nov 08 11:46:34 2018 +0000
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -151,23 +151,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_ARM_MICRO/efm32hg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000094 0x00001F6C { ; RW data
+ RW_IRAM1 0x20000098 0x00001F68 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_GCC_ARM/efm32hg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,8 +25,8 @@
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+21) * sizeof(uint32_t) = 148 bytes for EFM32HG */
-__vector_size = 0x94;
+ * 0x20000000. We need (16+21) * sizeof(uint32_t) = 148+4(8-byte aligned) bytes for EFM32HG */
+__vector_size = 0x98;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -152,23 +152,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -176,7 +176,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -184,11 +184,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/efm32hg322f64.icf Thu Nov 08 11:46:34 2018 +0000 @@ -11,8 +11,8 @@ define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000093; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000094; +define symbol __NVIC_end__ = 0x20000097; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000098; define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32lg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -112,7 +112,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -130,7 +130,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -151,23 +151,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32pg1b.ld Thu Nov 08 11:46:34 2018 +0000
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -151,23 +151,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data
+ RW_IRAM1 0x20000110 0x0003FEF0 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,8 +25,8 @@
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */
-__vector_size = 0x10C;
+ * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 + 4 (8-byte aligned) bytes for EFM32PG */
+__vector_size = 0x110;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -154,20 +154,20 @@
. = ALIGN (4);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf Thu Nov 08 11:46:34 2018 +0000 @@ -12,8 +12,8 @@ define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000010B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __NVIC_end__ = 0x2000010F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000110; define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00040000-1); /*-Sizes-*/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_GCC_ARM/efm32wg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -152,23 +152,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -176,7 +176,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -184,11 +184,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_ARM_MICRO/efm32zg.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x2000008C 0x00000F74 { ; RW data
+ RW_IRAM1 0x20000090 0x00000F70 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_GCC_ARM/efm32zg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,8 +25,8 @@
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+19) * sizeof(uint32_t) = 140 bytes for EFM32ZG */
-__vector_size = 0x8C;
+ * 0x20000000. We need (16+19) * sizeof(uint32_t) = 140 + 4(8-byte aligned) bytes for EFM32ZG */
+__vector_size = 0x90;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -152,23 +152,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -176,7 +176,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -184,11 +184,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/efm32zg222f32.icf Thu Nov 08 11:46:34 2018 +0000 @@ -11,8 +11,8 @@ define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000008B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000008C; +define symbol __NVIC_end__ = 0x2000008F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000090; define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/efr32mg1p.ld Thu Nov 08 11:46:34 2018 +0000
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -151,23 +151,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct Thu Nov 08 11:46:34 2018 +0000
@@ -17,7 +17,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data
+ RW_IRAM1 0x20000110 0x0003FEF0 { ; RW data
.ANY (+RW +ZI)
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld Thu Nov 08 11:46:34 2018 +0000
@@ -25,8 +25,8 @@
/* MBED: mbed needs to be able to dynamically set the interrupt vector table.
* We make room for the table at the very beginning of RAM, i.e. at
- * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */
-__vector_size = 0x10C;
+ * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 + 4(8-byte aligned) bytes for EFM32PG */
+__vector_size = 0x110;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -113,7 +113,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -131,7 +131,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -151,23 +151,23 @@
PROVIDE( __end_vector_table__ = .);
*(vtable)
*(.data*)
- . = ALIGN (4);
+ . = ALIGN (8);
*(.ram)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -175,7 +175,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -183,11 +183,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf Thu Nov 08 11:46:34 2018 +0000 @@ -11,8 +11,8 @@ define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x2000010B; -define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; +define symbol __NVIC_end__ = 0x2000010F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000110; define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -154,6 +154,18 @@
};
#endif
+#if DEVICE_QSPI
+struct qspi_s {
+ QSPI_TypeDef *instance;
+ PinName io0;
+ PinName io1;
+ PinName io2;
+ PinName io3;
+ PinName sclk;
+ PinName ssel;
+};
+#endif
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/crc_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/crc_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -34,6 +34,7 @@
#include "em_gpcrc.h"
static bool revOutput = false;
+static bool enableWordInput = false;
static uint32_t final_xor;
bool hal_crc_is_supported(const crc_mbed_config_t *config)
@@ -75,21 +76,24 @@
// defined by the mbed API. Emlib does the reversal on the poly, but
// not on the initial value.
if (config->width == 16) {
+ enableWordInput = false;
crc_init.initValue = __RBIT(config->initial_xor) >> 16;
} else {
+ enableWordInput = true;
crc_init.initValue = __RBIT(config->initial_xor);
}
// GPCRC operates on bit-reversed inputs and outputs vs the standard
// defined by the mbed API, so reflect_in/out needs to be negated.
if (config->reflect_in) {
- crc_init.reverseByteOrder = false;
crc_init.reverseBits = false;
} else {
- crc_init.reverseByteOrder = true;
crc_init.reverseBits = true;
}
+ // Input is little-endian
+ crc_init.reverseByteOrder = false;
+
// Disable byte mode to be able to run a faster U32 input version
crc_init.enableByteMode = false;
@@ -109,19 +113,30 @@
return;
}
- if (((uint32_t)data & 0x3) != 0 || size < 4) {
- // Unaligned or very small input, run a bytewise CRC
+ if (!enableWordInput || size < sizeof(uint32_t)) {
+ // Input to a non-word-sized poly, or too small data size for a word input
for (size_t i = 0; i < size; i++) {
GPCRC_InputU8(GPCRC, data[i]);
}
} else {
- // Aligned input, run 32-bit inputs as long as possible to make go faster.
size_t i = 0;
- for (; i < (size & (~0x3)); i+=4) {
+
+ // If input is unaligned, take off as many bytes as needed to align
+ while (((uint32_t)(data + i) & 0x3) != 0) {
+ GPCRC_InputU8(GPCRC, data[i]);
+ i++;
+ }
+
+ // If enough input remaining to do word-sized writes, do so
+ while ((size - i) >= sizeof(uint32_t)) {
GPCRC_InputU32(GPCRC, *((uint32_t*)(&data[i])));
+ i += sizeof(uint32_t);
}
- for (; i < size; i++) {
+
+ // Do byte input to pick off the last remaining bytes
+ while (i < size) {
GPCRC_InputU8(GPCRC, data[i]);
+ i++;
}
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c Thu Nov 08 11:46:34 2018 +0000 @@ -33,7 +33,6 @@ #include "em_system.h" #include "em_assert.h" #include <stddef.h> -#include "core_cmSecureAccess.h" /***************************************************************************//** * @addtogroup emlib @@ -62,24 +61,19 @@ EFM_ASSERT(rev); - uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); - uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); - uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); - uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); - /* CHIP FAMILY bit [5:2] */ - tmp = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ - tmp |= ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ - rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; + rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; /* CHIP MINOR bit [7:4] */ - tmp = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ - tmp |= ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; }
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -302,7 +302,7 @@
}
//Check if anything changed
- if(((PWM_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) == (pwm_prescaler_div << _TIMER_CTRL_PRESC_SHIFT)) && (TIMER_TopGet(PWM_TIMER) == cycles)) return;
+ if(((PWM_TIMER->CTRL & _TIMER_CTRL_PRESC_MASK) == (pwm_prescaler_div << _TIMER_CTRL_PRESC_SHIFT)) && (TIMER_TopGet(PWM_TIMER) == cycles)) return;
//Save previous period for recalculation of duty cycles
uint32_t previous_period_cycles = PWM_TIMER->TOPB;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,366 @@
+/***************************************************************************//**
+ * @file rtc_rtcc.c
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2018 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#include "device.h"
+#if DEVICE_QSPI && defined(QSPI_PRESENT)
+
+#include "stddef.h"
+#include "qspi_api.h"
+#include "mbed_error.h"
+#include "em_cmu.h"
+#include "em_qspi.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "pinmap_function.h"
+
+qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
+{
+
+#if defined(QSPI_FLASH_EN)
+ pin_mode(QSPI_FLASH_EN, PushPull);
+ GPIO_PinOutSet((GPIO_Port_TypeDef)(QSPI_FLASH_EN >> 4 & 0xF), QSPI_FLASH_EN & 0xF);
+#endif
+
+ // There's only one QSPI per chip for now
+ obj->instance = QSPI0;
+ obj->io0 = io0;
+ obj->io1 = io1;
+ obj->io2 = io2;
+ obj->io3 = io3;
+ obj->ssel = ssel;
+ obj->sclk = sclk;
+
+ CMU_ClockEnable(cmuClock_GPIO, true);
+
+#if (CORE_CLOCK_SOURCE == HFXO)
+ CMU_ClockSelectSet(cmuClock_QSPI0REF, cmuSelect_HFXO);
+#endif
+
+ CMU_ClockEnable(cmuClock_QSPI0, true);
+ CMU_ClockEnable(cmuClock_QSPI0REF, true);
+
+ qspi_frequency(obj, hz);
+
+ if (mode) {
+ obj->instance->CONFIG |= QSPI_CONFIG_SELCLKPOL | QSPI_CONFIG_SELCLKPHASE;
+ } else {
+ obj->instance->CONFIG &= ~(QSPI_CONFIG_SELCLKPOL | QSPI_CONFIG_SELCLKPHASE);
+ }
+
+ uint32_t loc = pin_location(io0, PinMap_QSPI_DQ0);
+ if (loc != pin_location(io1, PinMap_QSPI_DQ1) ||
+ loc != pin_location(io2, PinMap_QSPI_DQ2) ||
+ loc != pin_location(io3, PinMap_QSPI_DQ3) ||
+ loc != pin_location(sclk, PinMap_QSPI_SCLK) ||
+ loc != pin_location(ssel, PinMap_QSPI_CS0)) {
+ // All pins need to be on the same location number
+ qspi_free(obj);
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ // Configure QSPI pins
+ GPIO_PinOutClear((GPIO_Port_TypeDef)(io0 >> 4 & 0xF), io0 & 0xF);
+ pin_mode(io0, PushPull);
+
+ GPIO_PinOutClear((GPIO_Port_TypeDef)(io1 >> 4 & 0xF), io1 & 0xF);
+ pin_mode(io1, PushPull);
+
+ GPIO_PinOutClear((GPIO_Port_TypeDef)(io2 >> 4 & 0xF), io2 & 0xF);
+ pin_mode(io2, PushPull);
+
+ GPIO_PinOutClear((GPIO_Port_TypeDef)(io3 >> 4 & 0xF), io3 & 0xF);
+ pin_mode(io3, PushPull);
+
+ GPIO_PinOutClear((GPIO_Port_TypeDef)(sclk >> 4 & 0xF), sclk & 0xF);
+ pin_mode(sclk, PushPull);
+
+ GPIO_PinOutSet((GPIO_Port_TypeDef)(ssel >> 4 & 0xF), ssel & 0xF);
+ pin_mode(ssel, PushPull);
+
+
+ // Configure QSPI routing to GPIO
+ obj->instance->ROUTELOC0 = loc;
+ obj->instance->ROUTEPEN = QSPI_ROUTEPEN_SCLKPEN
+ | QSPI_ROUTEPEN_CS0PEN
+ | QSPI_ROUTEPEN_DQ0PEN
+ | QSPI_ROUTEPEN_DQ1PEN
+ | QSPI_ROUTEPEN_DQ2PEN
+ | QSPI_ROUTEPEN_DQ3PEN;
+
+ // Configure direct read
+ QSPI_ReadConfig_TypeDef readConfig = QSPI_READCONFIG_DEFAULT;
+ QSPI_ReadConfig(obj->instance, &readConfig);
+
+ // Configure direct write
+ QSPI_WriteConfig_TypeDef writeConfig = QSPI_WRITECONFIG_DEFAULT;
+ QSPI_WriteConfig(obj->instance, &writeConfig);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_free(qspi_t *obj)
+{
+ pin_mode(obj->io0, Disabled);
+ pin_mode(obj->io1, Disabled);
+ pin_mode(obj->io2, Disabled);
+ pin_mode(obj->io3, Disabled);
+ pin_mode(obj->ssel, Disabled);
+ pin_mode(obj->sclk, Disabled);
+
+ obj->instance->ROUTEPEN = 0;
+
+ QSPI_Enable(obj->instance, false);
+ CMU_ClockEnable(cmuClock_QSPI0REF, false);
+ CMU_ClockEnable(cmuClock_QSPI0, false);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_frequency(qspi_t *obj, int hz)
+{
+ if (hz <= 0) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ QSPI_Enable(obj->instance, false);
+
+ // Need at least a DIV4 for non-PHY mode and SDR transfers
+ uint32_t basefreq = CMU_ClockFreqGet(cmuClock_QSPI0REF);
+ uint32_t basediv = 4;
+ if ((uint32_t)hz < (basefreq / basediv)) {
+ basediv = (basefreq / hz) + 1;
+ }
+
+ QSPI_Init_TypeDef initQspi = QSPI_INIT_DEFAULT;
+ initQspi.divisor = basediv;
+ QSPI_Init(obj->instance, &initQspi);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
+{
+ QSPI_WriteConfig_TypeDef cfg = QSPI_WRITECONFIG_DEFAULT;
+ uint32_t to_write = *length;
+
+ // Enforce word-sized access
+ if ((to_write & 0x3) != 0) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ cfg.dummyCycles = command->dummy_count;
+
+ if (command->instruction.disabled) {
+ cfg.opCode = 0x02;
+ } else {
+ cfg.opCode = command->instruction.value;
+ }
+
+ if (command->address.disabled) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ if (command->address.bus_width == QSPI_CFG_BUS_SINGLE) {
+ cfg.addrTransfer = qspiTransferSingle;
+ } else if (command->address.bus_width == QSPI_CFG_BUS_DUAL) {
+ cfg.addrTransfer = qspiTransferDual;
+ } else if (command->address.bus_width == QSPI_CFG_BUS_QUAD) {
+ cfg.addrTransfer = qspiTransferQuad;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ if (command->data.bus_width == QSPI_CFG_BUS_SINGLE) {
+ cfg.dataTransfer = qspiTransferSingle;
+ } else if (command->data.bus_width == QSPI_CFG_BUS_DUAL) {
+ cfg.dataTransfer = qspiTransferDual;
+ } else if (command->data.bus_width == QSPI_CFG_BUS_QUAD) {
+ cfg.dataTransfer = qspiTransferQuad;
+ }
+
+ QSPI_WriteConfig(obj->instance, &cfg);
+
+ if (!command->alt.disabled) {
+ // Do not support alt mode in write mode
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ // Do an indirect write
+ obj->instance->INDAHBADDRTRIGGER = QSPI0_MEM_BASE;
+ obj->instance->INDIRECTWRITEXFERSTART = command->address.value;
+ obj->instance->INDIRECTWRITEXFERNUMBYTES = to_write;
+ obj->instance->INDIRECTWRITEXFERCTRL = QSPI_INDIRECTWRITEXFERCTRL_START;
+
+ // For the size of the transfer, poll the SRAM and fetch words from the SRAM
+ for (uint32_t i = 0; i < to_write; i+=4) {
+ // Wait for the QSPI in case we're writing too fast
+ while (((obj->instance->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK) >> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT) >= 126);
+
+ // Unaligned access is fine on CM3/CM4 provided we stick to LDR/STR
+ // With the line below, the compiler can't really do anything else anyways
+ *((uint32_t*)QSPI0_MEM_BASE) = ((uint32_t*)data)[i/4];
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
+{
+ QSPI_StigCmd_TypeDef cfg;
+
+ if (tx_size > 8 || rx_size > 8) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ cfg.writeDataSize = tx_size;
+ cfg.writeBuffer = (void*)tx_data;
+
+ cfg.readDataSize = rx_size;
+ cfg.readBuffer = rx_data;
+
+ if (command->address.disabled) {
+ cfg.addrSize = 0;
+ cfg.address = 0;
+ } else {
+ if (command->address.size == QSPI_CFG_ADDR_SIZE_8) {
+ cfg.addrSize = 1;
+ } else if (command->address.size == QSPI_CFG_ADDR_SIZE_16) {
+ cfg.addrSize = 2;
+ } else if (command->address.size == QSPI_CFG_ADDR_SIZE_24) {
+ cfg.addrSize = 3;
+ } else if (command->address.size == QSPI_CFG_ADDR_SIZE_32) {
+ cfg.addrSize = 4;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ cfg.address = command->address.value;
+ }
+
+ if (command->instruction.disabled) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ cfg.cmdOpcode = command->instruction.value;
+ }
+
+ cfg.dummyCycles = command->dummy_count;
+
+ if (!command->alt.disabled) {
+ cfg.modeBitEnable = true;
+ obj->instance->MODEBITCONFIG = command->alt.value & _QSPI_MODEBITCONFIG_MODE_MASK;
+
+ if(command->alt.size != QSPI_CFG_ALT_SIZE_8) {
+ //do not support 'alt' bigger than 8 bit
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ } else {
+ cfg.modeBitEnable = false;
+ }
+
+ QSPI_ExecStigCmd(obj->instance, &cfg);
+
+ return QSPI_STATUS_OK;
+}
+
+qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
+{
+ QSPI_ReadConfig_TypeDef cfg = QSPI_READCONFIG_DEFAULT;
+ uint32_t to_read = *length;
+
+ // Enforce word-sized access
+ if ((to_read & 0x3) != 0) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+
+ cfg.dummyCycles = command->dummy_count;
+
+ if (command->instruction.disabled) {
+ cfg.opCode = 0x03;
+ cfg.instTransfer = qspiTransferSingle;
+ } else {
+ cfg.opCode = command->instruction.value;
+ if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE) {
+ cfg.instTransfer = qspiTransferSingle;
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_DUAL) {
+ cfg.instTransfer = qspiTransferDual;
+ } else if (command->instruction.bus_width == QSPI_CFG_BUS_QUAD) {
+ cfg.instTransfer = qspiTransferQuad;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ if (command->address.disabled) {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ } else {
+ if (command->address.bus_width == QSPI_CFG_BUS_SINGLE) {
+ cfg.addrTransfer = qspiTransferSingle;
+ } else if (command->address.bus_width == QSPI_CFG_BUS_DUAL) {
+ cfg.addrTransfer = qspiTransferDual;
+ } else if (command->address.bus_width == QSPI_CFG_BUS_QUAD) {
+ cfg.addrTransfer = qspiTransferQuad;
+ } else {
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ if (command->data.bus_width == QSPI_CFG_BUS_SINGLE) {
+ cfg.dataTransfer = qspiTransferSingle;
+ } else if (command->data.bus_width == QSPI_CFG_BUS_DUAL) {
+ cfg.dataTransfer = qspiTransferDual;
+ } else if (command->data.bus_width == QSPI_CFG_BUS_QUAD) {
+ cfg.dataTransfer = qspiTransferQuad;
+ }
+
+ QSPI_ReadConfig(obj->instance, &cfg);
+
+ if (!command->alt.disabled) {
+ // Need to set up alt mode manually, called 'mode bits' in EFM32GG11 refman
+ obj->instance->DEVINSTRRDCONFIG |= QSPI_DEVINSTRRDCONFIG_MODEBITENABLE;
+ obj->instance->MODEBITCONFIG = command->alt.value & _QSPI_MODEBITCONFIG_MODE_MASK;
+
+ if(command->alt.size != QSPI_CFG_ALT_SIZE_8) {
+ // Do not support 'alt' bigger than 8 bit
+ return QSPI_STATUS_INVALID_PARAMETER;
+ }
+ }
+
+ // Do an indirect read
+ obj->instance->INDAHBADDRTRIGGER = QSPI0_MEM_BASE;
+ obj->instance->INDIRECTREADXFERSTART = command->address.value;
+ obj->instance->INDIRECTREADXFERNUMBYTES = to_read;
+ obj->instance->INDIRECTREADXFERCTRL = QSPI_INDIRECTREADXFERCTRL_START;
+
+ // For the size of the transfer, poll the SRAM and fetch words from the SRAM
+ for (uint32_t i = 0; i < to_read; i+=4) {
+ // Wait for the FIFO in case we're reading too fast
+ while ((obj->instance->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK) >> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT == 0);
+
+ // Unaligned access is fine on CM3/CM4 provided we stick to LDR/STR
+ // With the line below, the compiler can't really do anything else anyways
+ ((uint32_t*)data)[i/4] = *((uint32_t*)QSPI0_MEM_BASE);
+ }
+
+ return QSPI_STATUS_OK;
+}
+
+#endif /* DEVICE_QSPI && QSPI_PRESENT */
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,14 +99,14 @@
PROVIDE (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf Thu Nov 08 11:46:34 2018 +0000 @@ -9,8 +9,8 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x200; -define symbol __ICFEDIT_size_heap__ = 0x1400; +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,5 +1,5 @@
/* mbed Microcontroller Library
- * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -13,51 +13,57 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
+#include <stdbool.h>
#include "us_ticker_api.h"
-#include "mbed_critical.h"
-
-#define TMR16A_100US 0x960 // fsys = fc = 24MHz, Ttmra = 1/24us, 100us*24us = 2400 = 0x960
-#define TMR16A_SYSCK ((uint32_t)0x00000001)
-#define TMR16A_RUN ((uint32_t)0x00000001)
-#define TMR16A_STOP ((uint32_t)0x00000000)
-#define OVERFLOW_32BIT (0xFFFFFFFF / 0x64)
+#include "tmpm066_tmrb.h"
+#include "tmpm066_intifsd.h"
-static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
-static volatile uint32_t ticker_int_counter = 0; // Amount of overflows until user interrupt
-static volatile uint32_t us_ticker = 0; // timer counter
+#define MAX_TICK_16_BIT 0xFFFF
-void INT16A0_IRQHandler(void)
+static bool us_ticker_inited = false; // Is ticker initialized yet?
+
+void INTTB7_IRQHandler(void)
{
- us_ticker++;
-
- if (us_ticker > OVERFLOW_32BIT) {
- us_ticker = 0;
- }
+ us_ticker_irq_handler();
}
-void INT16A1_IRQHandler(void)
+const ticker_info_t* us_ticker_get_info()
{
- us_ticker_irq_handler();
+ static const ticker_info_t info = {
+ 3000000, // 3MHz,
+ 16 // 16 bit counter
+ };
+ return &info;
}
// initialize us_ticker
void us_ticker_init(void)
{
- // Enable clock supply to TA0
- CG_SetFcPeriphA(CG_FC_PERIPH_TMR16A, ENABLE);
+ TMRB_InitTypeDef m_tmrb0;
+
if (us_ticker_inited) {
+ us_ticker_disable_interrupt();
return;
}
- us_ticker_inited = 1;
+ us_ticker_inited = true;
+ // TSB_TB7 using free-run
+ m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
+ m_tmrb0.ClkDiv = TMRB_CLK_DIV_8;
+ m_tmrb0.UpCntCtrl = TMRB_FREE_RUN;
+ m_tmrb0.TrailingTiming = MAX_TICK_16_BIT;
+ m_tmrb0.LeadingTiming = MAX_TICK_16_BIT;
+
+ // Enable channel 0
+ TMRB_Enable(TSB_TB7);
// Stops and clear count operation
- TSB_T16A0->RUN = TMR16A_STOP;
- TSB_T16A0->CR = TMR16A_SYSCK;
- // Permits INTTA0 interrupt
- NVIC_EnableIRQ(INT16A0_IRQn);
- // Match counter set to max value
- TSB_T16A0->RG = TMR16A_100US;
- TSB_T16A0->RUN = TMR16A_RUN;
+ TMRB_SetRunState(TSB_TB7, TMRB_STOP);
+ // Mask All interrupts
+ TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
+ // Initialize timer
+ TMRB_Init(TSB_TB7, &m_tmrb0);
+ // Starts TSB_TB7
+ TMRB_SetRunState(TSB_TB7, TMRB_RUN);
}
uint32_t us_ticker_read(void)
@@ -68,42 +74,47 @@
us_ticker_init();
}
- uint32_t tickerbefore = 0;
- do {
- tickerbefore = us_ticker;
- ret_val = (us_ticker * 100);
- } while (tickerbefore != us_ticker);
+ ret_val = (uint32_t)TMRB_GetUpCntValue(TSB_TB7);
return ret_val;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = 0;
-
- // Stops and clear count operation
- TSB_T16A1->RUN = TMR16A_STOP;
- TSB_T16A1->CR = TMR16A_SYSCK;
- // Set the compare register
- delta = (timestamp - us_ticker_read());
- TSB_T16A1->RG = delta;
- // Set Interrupt
- NVIC_EnableIRQ(INT16A1_IRQn);
- // Start TMR_TA1 timer
- TSB_T16A1->RUN = TMR16A_RUN;
+ NVIC_DisableIRQ(INTTB7_IRQn);
+ NVIC_ClearPendingIRQ(INTTB7_IRQn);
+ TMRB_ChangeTrailingTiming(TSB_TB7, timestamp);
+ //Mask all Interrupts except trailing edge interrupt
+ TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
+ NVIC_EnableIRQ(INTTB7_IRQn);
}
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(INT16A1_IRQn);
+ NVIC_SetPendingIRQ(INTTB7_IRQn);
+ NVIC_EnableIRQ(INTTB7_IRQn);
}
void us_ticker_disable_interrupt(void)
{
- NVIC_DisableIRQ(INT16A1_IRQn);
+ // Mask All interrupts
+ TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
+ // Also clear and disable interrupts by NVIC
+ NVIC_ClearPendingIRQ(INTTB7_IRQn);
+ NVIC_DisableIRQ(INTTB7_IRQn);
}
void us_ticker_clear_interrupt(void)
{
- //no flags to clear
+ INTIFSD_ClearINTReq(INTIFSD_INT_SRC_TMRB_7_MDOVF);
+ NVIC_ClearPendingIRQ(INTTB7_IRQn);
}
+
+void us_ticker_free(void)
+{
+ TMRB_SetINTMask(TSB_TB7, TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT);
+ NVIC_ClearPendingIRQ(INTTB7_IRQn);
+ NVIC_DisableIRQ(INTTB7_IRQn);
+ TMRB_SetRunState(TSB_TB7, TMRB_STOP);
+ TMRB_Disable(TSB_TB7);
+}
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_GCC_ARM/tmpm3h6fwfg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -96,13 +96,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -110,7 +110,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -118,7 +118,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -126,11 +126,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/device/TOOLCHAIN_IAR/tmpm3h6fwfg.icf Thu Nov 08 11:46:34 2018 +0000 @@ -8,9 +8,9 @@ define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000218; /* 8_byte_aligned(117 + 16 vect * 4 bytes) */ define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/* Heap 1/4 of ram and stack 1/8 */ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x1200; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -120,77 +120,77 @@
switch (port) {
case PortA:
- if (mode == OpenDrain) TSB_PA->OD = val;
- else if (mode == PullUp) TSB_PA->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN = val;
+ if (mode == OpenDrain) TSB_PA->OD |= val;
+ else if (mode == PullUp) TSB_PA->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val;
break;
case PortB:
- if (mode == OpenDrain) TSB_PB->OD = val;
- else if (mode == PullUp) TSB_PB->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN = val;
+ if (mode == OpenDrain) TSB_PB->OD |= val;
+ else if (mode == PullUp) TSB_PB->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val;
break;
case PortC:
- if (mode == OpenDrain) TSB_PC->OD = val;
- else if (mode == PullUp) TSB_PC->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN = val;
+ if (mode == OpenDrain) TSB_PC->OD |= val;
+ else if (mode == PullUp) TSB_PC->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val;
break;
case PortD:
- if (mode == OpenDrain) TSB_PD->OD = val;
- else if (mode == PullUp) TSB_PD->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN = val;
+ if (mode == OpenDrain) TSB_PD->OD |= val;
+ else if (mode == PullUp) TSB_PD->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val;
break;
case PortE:
- if (mode == OpenDrain) TSB_PE->OD = val;
- else if (mode == PullUp) TSB_PE->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN = val;
+ if (mode == OpenDrain) TSB_PE->OD |= val;
+ else if (mode == PullUp) TSB_PE->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val;
break;
case PortF:
- if (mode == OpenDrain) TSB_PF->OD = val;
- else if (mode == PullUp) TSB_PF->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN = val;
+ if (mode == OpenDrain) TSB_PF->OD |= val;
+ else if (mode == PullUp) TSB_PF->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val;
break;
case PortG:
- if (mode == OpenDrain) TSB_PG->OD = val;
- else if (mode == PullUp) TSB_PG->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN = val;
+ if (mode == OpenDrain) TSB_PG->OD |= val;
+ else if (mode == PullUp) TSB_PG->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val;
break;
case PortH:
- if (mode == PullDown) TSB_PH->PDN = val;
+ if (mode == PullDown) TSB_PH->PDN |= val;
break;
case PortJ:
- if (mode == OpenDrain) TSB_PJ->OD = val;
- else if (mode == PullUp) TSB_PJ->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN = val;
+ if (mode == OpenDrain) TSB_PJ->OD |= val;
+ else if (mode == PullUp) TSB_PJ->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val;
break;
case PortK:
- if (mode == OpenDrain) TSB_PK->OD = val;
- else if (mode == PullUp) TSB_PK->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN = val;
+ if (mode == OpenDrain) TSB_PK->OD |= val;
+ else if (mode == PullUp) TSB_PK->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val;
break;
case PortL:
- if (mode == OpenDrain) TSB_PL->OD = val;
- else if (mode == PullUp) TSB_PL->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN = val;
+ if (mode == OpenDrain) TSB_PL->OD |= val;
+ else if (mode == PullUp) TSB_PL->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val;
break;
case PortM:
- if (mode == OpenDrain) TSB_PM->OD = val;
- else if (mode == PullUp) TSB_PM->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN = val;
+ if (mode == OpenDrain) TSB_PM->OD |= val;
+ else if (mode == PullUp) TSB_PM->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val;
break;
case PortN:
- if (mode == OpenDrain) TSB_PN->OD = val;
- else if (mode == PullUp) TSB_PN->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN = val;
+ if (mode == OpenDrain) TSB_PN->OD |= val;
+ else if (mode == PullUp) TSB_PN->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val;
break;
case PortP:
- if (mode == OpenDrain) TSB_PP->OD = val;
- else if (mode == PullUp) TSB_PP->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN = val;
+ if (mode == OpenDrain) TSB_PP->OD |= val;
+ else if (mode == PullUp) TSB_PP->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val;
break;
case PortR:
- if (mode == OpenDrain) TSB_PR->OD = val;
- else if (mode == PullUp) TSB_PR->PUP = val;
- else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN = val;
+ if (mode == OpenDrain) TSB_PR->OD |= val;
+ else if (mode == PullUp) TSB_PR->PUP |= val;
+ else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val;
break;
default:
break;
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM3H6/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -18,7 +18,7 @@
static bool us_ticker_inited = false; // Is ticker initialized yet?
-const ticker_info_t* us_ticker_get_info()
+const ticker_info_t* us_ticker_get_info(void)
{
static const ticker_info_t info = {
1248125, // (39.94 MHz / 32 )
@@ -83,3 +83,14 @@
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
}
+
+void us_ticker_free(void)
+{
+ TSB_CG_FSYSENA_IPENA26 = TXZ_DISABLE;
+ us_ticker_inited = false;
+ TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
+ // Disable and clear interrupts in NVIC
+ TSB_T32A0->STC = T32A_INT_MASK;
+ NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
+ NVIC_DisableIRQ(INTT32A00C_IRQn);
+}
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_GCC_ARM/tmpm46bf10fg.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_GCC_ARM/tmpm46bf10fg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -105,7 +105,7 @@
/*
.copy.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
@@ -123,7 +123,7 @@
/*
.zero.table :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
@@ -141,13 +141,13 @@
*(vtable)
*(.data*)
*(.ram_func*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -155,7 +155,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -163,7 +163,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -171,11 +171,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/pwmout_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/pwmout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -37,7 +37,7 @@
2, 8, 32, 64, 128, 256, 512
};
-#define CLOCK_FREQUENCY (48000000) // Input source clock
+#define CLOCK_FREQUENCY (SystemCoreClock) // Input source clock
void pwmout_init(pwmout_t *obj, PinName pin)
{
@@ -108,8 +108,8 @@
}
TMRB_SetFlipFlop(obj->channel, &FFStruct);
- if (obj->period > 0.7) {
- value = 1; //TMPM46B duty cycle should be < 700ms, above 700ms fixed 50% duty cycle
+ if (obj->period > 0.560) {
+ value = 1; // TMPM46B duty cycle should be < 560ms, above 560ms fixed 50% duty cycle
}
// Store the new leading_timing value
obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value);
@@ -148,7 +148,7 @@
seconds = (float)((us) / 1000000.0f);
obj->period = seconds;
- if (obj->period > 0.7) {
+ if (obj->period > 0.560) {
clk_freq = (CLOCK_FREQUENCY / 2);
} else {
clk_freq = CLOCK_FREQUENCY;
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -230,18 +230,23 @@
case SERIAL_2:
case SERIAL_3:
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
- obj->uart_config.DataBits = data_bits;
- obj->uart_config.StopBits = stop_bits;
- obj->uart_config.Parity = parity;
+ obj->uart_config.DataBits = ((data_bits == 7) ? UART_DATA_BITS_7:
+ ((data_bits == 8) ? UART_DATA_BITS_8 : UART_DATA_BITS_9));
+ obj->uart_config.StopBits = ((stop_bits == 1) ? UART_STOP_BITS_1 : UART_STOP_BITS_2);
+ obj->uart_config.Parity = ((parity == ParityOdd) ? UART_ODD_PARITY :
+ ((parity == ParityEven) ? UART_EVEN_PARITY : UART_NO_PARITY));
UART_Init(obj->UARTx,&obj->uart_config);
break;
case SERIAL_4:
case SERIAL_5:
FUART_Disable(obj->FUART);
- MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits
- obj->fuart_config.DataBits = data_bits;
- obj->fuart_config.StopBits = stop_bits;
- obj->fuart_config.Parity = parity;
+ MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits
+ obj->fuart_config.DataBits = ((data_bits == 7) ? FUART_DATA_BITS_7 : FUART_DATA_BITS_8);
+ obj->fuart_config.StopBits = ((stop_bits == 1) ? FUART_STOP_BITS_1 : FUART_STOP_BITS_2);
+ obj->fuart_config.Parity = ((parity == ParityOdd) ? FUART_ODD_PARITY :
+ ((parity == ParityEven) ? FUART_EVEN_PARITY :
+ ((parity == ParityForced1) ? FUART_1_PARITY :
+ ((parity == ParityForced0) ? FUART_0_PARITY : FUART_NO_PARITY))));
FUART_Init(obj->FUART,&obj->fuart_config);
FUART_Enable(obj->FUART);
break;
@@ -497,11 +502,20 @@
// Set flow control, Just support CTS
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
- UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+ UARTName uart_cts;
+
+ // SERIAL_5 & SERIAL_3 have same CTS pin (PA7), only function register is different (4 & 2).
+ // pinmap_peripheral() will always return first match from the map.
+ // But, if SERIAL_5 is used, then pinmap_peripheral() should return SERIAL_5 (function register 2 to be set).
+ if (obj->index == SERIAL_5) {
+ uart_cts = (UARTName)pinmap_peripheral(txflow, &PinMap_UART_CTS[5]);
+ } else {
+ uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+ }
UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
- switch (obj->index) {
+ switch (uart_name) {
case SERIAL_0:
case SERIAL_1:
case SERIAL_2:
@@ -529,7 +543,11 @@
obj->FUART->CR |= FUART_CTS_FLOW_CTRL;
// Enable the pin for CTS and RTS function
- pinmap_pinout(txflow, PinMap_UART_CTS);
+ if (uart_name == SERIAL_5) {
+ pinmap_pinout(txflow, &PinMap_UART_CTS[5]);
+ } else {
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ }
} else if (type == FlowControlRTS) {
MBED_ASSERT(uart_rts != (UARTName) NC);
@@ -545,7 +563,11 @@
obj->FUART->CR |= FUART_CTS_FLOW_CTRL | FUART_RTS_FLOW_CTRL;
// Enable the pin for CTS and RTS function
- pinmap_pinout(txflow, PinMap_UART_CTS);
+ if (uart_name == SERIAL_5) {
+ pinmap_pinout(txflow, &PinMap_UART_CTS[5]);
+ } else {
+ pinmap_pinout(txflow, PinMap_UART_CTS);
+ }
pinmap_pinout(rxflow, PinMap_UART_RTS);
} else {
// Disable CTS and RTS hardware flow control
--- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -1,5 +1,5 @@
/* mbed Microcontroller Library
- * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -13,14 +13,14 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
+#include <stdbool.h>
#include "us_ticker_api.h"
#include "tmpm46b_tmrb.h"
-#define TMR16A_100US 0xFFFF
-#define TMRB_CLK_DIV 0x3
+#define MAX_TICK_16_BIT 0xFFFF
+#define TMRB_CLK_DIV 0x3
-static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
-static volatile uint32_t us_ticker = 0; // timer counter
+static bool us_ticker_inited = false; // Is ticker initialized yet?
const ticker_info_t* us_ticker_get_info()
{
@@ -35,34 +35,32 @@
void us_ticker_init(void)
{
TMRB_InitTypeDef m_tmrb0;
- TMRB_FFOutputTypeDef FFStruct;
if (us_ticker_inited) {
+ us_ticker_disable_interrupt();
return;
}
- us_ticker_inited = 1;
+ us_ticker_inited = true;
+
+ // TSB_TB0 using free-run
+ m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
+ m_tmrb0.ClkDiv = TMRB_CLK_DIV;
+ m_tmrb0.UpCntCtrl = TMRB_FREE_RUN;
+ m_tmrb0.TrailingTiming = MAX_TICK_16_BIT;
+ m_tmrb0.LeadingTiming = MAX_TICK_16_BIT;
// Enable channel 0
TMRB_Enable(TSB_TB0);
// Stops and clear count operation
TMRB_SetRunState(TSB_TB0, TMRB_STOP);
- // Disable to TBxFF0 reverse trigger
- FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
- FFStruct.FlipflopReverseTrg =TMRB_DISABLE_FLIPFLOP;
- TMRB_SetFlipFlop(TSB_TB0, &FFStruct);
-
- // TSB_TB0 using free-run
- m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
- m_tmrb0.ClkDiv = TMRB_CLK_DIV;
- m_tmrb0.UpCntCtrl = TMRB_AUTO_CLEAR;
- m_tmrb0.TrailingTiming = TMR16A_100US;
- m_tmrb0.LeadingTiming = TMR16A_100US;
+ // Mask All interrupts
+ TMRB_SetINTMask(TSB_TB0, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT);
TMRB_Init(TSB_TB0, &m_tmrb0);
-
// Enable TMRB when system is in idle mode
TMRB_SetIdleMode(TSB_TB0, ENABLE);
// Starts TSB_TB0
TMRB_SetRunState(TSB_TB0, TMRB_RUN);
+ NVIC_SetVector(INTTB0_IRQn, (uint32_t)us_ticker_irq_handler);
}
uint32_t us_ticker_read(void)
@@ -80,54 +78,40 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- TMRB_InitTypeDef m_tmrb1;
- TMRB_FFOutputTypeDef FFStruct;
-
- const uint32_t now_ticks = us_ticker_read();
- uint32_t delta_ticks =
- timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFF - now_ticks);
-
- if (delta_ticks == 0) {
- /* The requested delay is less than the minimum resolution of this counter. */
- delta_ticks = 1;
- }
-
- // Ticker interrupt handle
- TMRB_Enable(TSB_TB1);
- TMRB_SetRunState(TSB_TB1, TMRB_STOP);
- NVIC_SetVector(INTTB1_IRQn, (uint32_t)us_ticker_irq_handler);
- NVIC_EnableIRQ(INTTB1_IRQn);
-
- // Split delta for preventing the Multiply overflowing
- FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
- FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
- TMRB_SetFlipFlop(TSB_TB1, &FFStruct);
-
- // TSB_TB0 using free-run
- m_tmrb1.Mode = TMRB_INTERVAL_TIMER;
- m_tmrb1.ClkDiv = TMRB_CLK_DIV;
- m_tmrb1.UpCntCtrl = TMRB_AUTO_CLEAR;
- m_tmrb1.TrailingTiming = delta_ticks;
- m_tmrb1.LeadingTiming = delta_ticks;
- TMRB_Init(TSB_TB1, &m_tmrb1);
- TMRB_SetINTMask(TSB_TB1,TMRB_MASK_OVERFLOW_INT | TMRB_MASK_MATCH_LEADING_INT);
- // Enable TMRB when system is in idle mode
- TMRB_SetIdleMode(TSB_TB1, ENABLE);
- TMRB_SetRunState(TSB_TB1, TMRB_RUN);
+ NVIC_DisableIRQ(INTTB0_IRQn);
+ NVIC_ClearPendingIRQ(INTTB0_IRQn);
+ TMRB_ChangeTrailingTiming(TSB_TB0, timestamp);
+ // Mask all Interrupts except trailing edge interrupt
+ TMRB_SetINTMask(TSB_TB0, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_OVERFLOW_INT);
+ NVIC_EnableIRQ(INTTB0_IRQn);
}
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(INTTB1_IRQn);
+ NVIC_SetPendingIRQ(INTTB0_IRQn);
+ NVIC_EnableIRQ(INTTB0_IRQn);
}
void us_ticker_disable_interrupt(void)
{
- // Also disable interrupts by NVIC
- NVIC_DisableIRQ(INTTB1_IRQn);
+ // Mask All interrupts
+ TMRB_SetINTMask(TSB_TB0, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT);
+ // Also clear and disable interrupts by NVIC
+ NVIC_ClearPendingIRQ(INTTB0_IRQn);
+ NVIC_DisableIRQ(INTTB0_IRQn);
}
void us_ticker_clear_interrupt(void)
{
- // No flag to clear
+ NVIC_ClearPendingIRQ(INTTB0_IRQn);
}
+
+void us_ticker_free(void)
+{
+ TMRB_SetINTMask(TSB_TB0, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT);
+ NVIC_ClearPendingIRQ(INTTB0_IRQn);
+ NVIC_DisableIRQ(INTTB0_IRQn);
+ TMRB_SetRunState(TSB_TB0, TMRB_STOP);
+ TMRB_Disable(TSB_TB0);
+ us_ticker_inited = false;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/adc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,499 @@
+/**
+ *******************************************************************************
+ * @file adc.h
+ * @brief This file provides all the functions prototypes for ADC driver.
+ * @version V1.0.0.0
+ * $Date:: 2017-09-12 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __ADC_H
+#define __ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+#include "adc_ch.h"
+/**
+ * @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/**
+ * @defgroup ADC ADC
+ * @brief ADC Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_define ADC Exported Define
+ * @{
+ */
+
+/**
+ * @defgroup ADC_ChannelMax Channel Num Max
+ * @brief Max Num of channel.
+ * @{
+ */
+
+ #define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */
+/**
+ * @}
+ */ /* End of group ADC_ChannelMax */
+/**
+ * @}
+ */ /* End of group ADC_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ @defgroup ADC_Exported_define ADC Exported Define
+ @{
+ */
+/** @enum adc_sampling_period0_t
+ @brief Outside AIN sampling period.
+ */
+typedef enum
+{
+ ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */
+ ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */
+ ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */
+ ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */
+ ADC_SAMPLING_PERIOD0_X16N = 0x28, /*!< SCLK Period (1/SCLK)x16N */
+ ADC_SAMPLING_PERIOD0_X64N = 0x38, /*!< SCLK Period (1/SCLK)x64N */
+}adc_sampling_period0_t;
+/** @enum adc_sampling_period1_t
+ @brief Outside AIN sampling period.
+ */
+typedef enum
+{
+ ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */
+ ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */
+ ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */
+ ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */
+ ADC_SAMPLING_PERIOD1_X16N = 0x500, /*!< SCLK Period (1/SCLK)x16N */
+ ADC_SAMPLING_PERIOD1_X64N = 0x700, /*!< SCLK Period (1/SCLK)x64N */
+}adc_sampling_period1_t;
+
+/*! @enum adc_sclk_t
+ @brief Select AD prescaler output (SCLK).
+ */
+typedef enum
+{
+ ADC_SCLK_1 = (0x00000000U), /*!< ADCLK/1 */
+ ADC_SCLK_2 = (0x00000001U), /*!< ADCLK/2 */
+ ADC_SCLK_4 = (0x00000002U), /*!< ADCLK/4 */
+ ADC_SCLK_8 = (0x00000003U), /*!< ADCLK/8 */
+ ADC_SCLK_16 = (0x00000004U), /*!< ADCLK/16 */
+}adc_sclk_t;
+
+/*! @enum adc_mod1_t
+ @brief Select SCLK Frequency Band (MOD1).
+ */
+typedef enum
+{
+ ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 40MHz > */
+ ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 40MHz < SCLK =< 50MHz > */
+ ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 50MHz < SCLK =< 60MHz > */
+ ADC_MOD1_SCLK_4 = (0x00106011U), /*!< 60MHz < SCLK =< 80MHz > */
+}adc_mod1_t;
+
+/*! @enum adc_mod2_t
+ @brief Select ADC Product Setting Value (MOD2).
+ */
+typedef enum
+{
+ ADC_MOD2_TMPM4G9 = (0x00000000U), /*!< TMPM4G9 */
+ ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */
+}adc_mod2_t;
+
+/*! @enum adc_int_t
+ @brief Select Interrupt Enable/Disable.
+ */
+typedef enum
+{
+ ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */
+ ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */
+}adc_int_t;
+
+/*! @enum adc_conversion_t
+ @brief Select conversion method.
+ */
+typedef enum
+{
+ ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */
+ ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */
+ ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */
+ ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */
+ ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */
+}adc_conversion_t;
+
+/*! @enum adc_dma_int_t
+ @brief Select DMA interrupt method.
+ */
+typedef enum
+{
+ ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */
+ ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */
+ ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */
+ ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */
+ ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */
+ ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */
+ ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */
+ ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */
+ ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */
+ ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */
+}adc_dma_int_t;
+
+/*! @enum adc_ain_range_t
+ @brief Range of AIN Macro Definisiton.
+ Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)".
+ */
+typedef enum
+{
+ ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */
+ ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */
+}adc_ain_range_t;
+
+/*! @enum adc_status_t
+ @brief AD Running Status.
+ */
+typedef enum
+{
+ ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */
+ ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
+ ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */
+}adc_status_t;
+
+/*! @enum adc_cnt_status_t
+ @brief Continuity Conversion Running Status.
+ */
+typedef enum
+{
+ ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */
+ ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
+ ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */
+}adc_cnt_status_t;
+
+/*! @enum adc_sgl_status_t
+ @brief Single Conversion Running Status.
+ */
+typedef enum
+{
+ ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */
+ ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
+ ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */
+}adc_sgl_status_t;
+
+/*! @enum adc_trg_status_t
+ @brief Trigger Conversion Running Status.
+ */
+typedef enum
+{
+ ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */
+ ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
+ ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */
+}adc_trg_status_t;
+
+/*! @enum adc_hpri_status_t
+ @brief Trigger Conversion Running Status.
+ */
+typedef enum
+{
+ ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */
+ ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */
+ ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */
+}adc_hpri_status_t;
+
+/*! @enum adcmpxen_t
+ @brief Select Enable, Disable setting(ADxCMPEN).
+ */
+typedef enum
+{
+ ADCMP3EN_DISABLE = (0x00000000U), /*!< Disable. */
+ ADCMP3EN_ENABLE = (0x00000008U), /*!< Enable. */
+ ADCMP2EN_DISABLE = (0x00000000U), /*!< Disable. */
+ ADCMP2EN_ENABLE = (0x00000004U), /*!< Enable. */
+ ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */
+ ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */
+ ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */
+ ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */
+}adcmpxen_t;
+
+/*! @enum adcmpcnt_t
+ @brief Select Compare count num.
+ */
+typedef enum
+{
+ ADCMPCNT_1 = (0x00000000U), /*!< 1 time */
+ ADCMPCNT_2 = (0x00000100U), /*!< 2 times */
+ ADCMPCNT_3 = (0x00000200U), /*!< 3 times */
+ ADCMPCNT_4 = (0x00000300U), /*!< 4 times */
+ ADCMPCNT_5 = (0x00000400U), /*!< 5 times */
+ ADCMPCNT_6 = (0x00000500U), /*!< 6 times */
+ ADCMPCNT_7 = (0x00000600U), /*!< 7 times */
+ ADCMPCNT_8 = (0x00000700U), /*!< 8 times */
+ ADCMPCNT_9 = (0x00000800U), /*!< 9 times */
+ ADCMPCNT_10 = (0x00000900U), /*!< 10 times */
+ ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */
+ ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */
+ ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */
+ ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */
+ ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */
+ ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */
+}adcmpcnt_t;
+
+/*! @enum adcmpcond_t
+ @brief Compare condition
+ */
+typedef enum
+{
+ ADCMPCond_CNT = (0x00000000U), /*!< Continuous */
+ ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */
+}adcmpcond_t;
+
+/*! @enum adcmpbigsml_t
+ @brief Compare Big, Small condition
+ */
+typedef enum
+{
+ ADCMPBigSml_Big = (0x00000000U), /*!< Big */
+ ADCMPBigSml_Sml = (0x00000020U), /*!< Small */
+}adcmpbigsml_t;
+
+/*! @enum adcmpstr_t
+ @brief Select Compare Store register
+ */
+typedef enum
+{
+ ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */
+ ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */
+ ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */
+ ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */
+ ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */
+ ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */
+ ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */
+ ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */
+ ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */
+ ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */
+ ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */
+ ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */
+ ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */
+ ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */
+ ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */
+ ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */
+ ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */
+ ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */
+ ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */
+ ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */
+ ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */
+ ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */
+ ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */
+ ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */
+}adcmpstr_t;
+/*! @enum adcexazain_t
+ @brief Select AIN no.
+ */
+
+typedef enum
+{
+ ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */
+ ADCEXAZSEL_AIN1, /*!< AIN1 */
+ ADCEXAZSEL_AIN2, /*!< AIN2 */
+ ADCEXAZSEL_AIN3, /*!< AIN3 */
+ ADCEXAZSEL_AIN4, /*!< AIN4 */
+ ADCEXAZSEL_AIN5, /*!< AIN5 */
+ ADCEXAZSEL_AIN6, /*!< AIN6 */
+ ADCEXAZSEL_AIN7, /*!< AIN7 */
+ ADCEXAZSEL_AIN8, /*!< AIN8 */
+ ADCEXAZSEL_AIN9, /*!< AIN9 */
+ ADCEXAZSEL_AIN10, /*!< AIN10 */
+ ADCEXAZSEL_AIN11, /*!< AIN11 */
+ ADCEXAZSEL_AIN12, /*!< AIN12 */
+ ADCEXAZSEL_AIN13, /*!< AIN13 */
+ ADCEXAZSEL_AIN14, /*!< AIN14 */
+ ADCEXAZSEL_AIN15, /*!< AIN15 */
+ ADCEXAZSEL_AIN16, /*!< AIN16 */
+ ADCEXAZSEL_AIN17, /*!< AIN17 */
+ ADCEXAZSEL_AIN18, /*!< AIN18 */
+ ADCEXAZSEL_AIN19, /*!< AIN19 */
+ ADCEXAZSEL_AIN20, /*!< AIN20 */
+ ADCEXAZSEL_AIN21, /*!< AIN21 */
+ ADCEXAZSEL_AIN22, /*!< AIN22 */
+ ADCEXAZSEL_AIN23, /*!< AIN23 */
+}adcexazain_t;
+/*! @enum adcexazsel_t
+ @brief Select sampling period, EXAS0 or EXAS1.
+ */
+typedef enum
+{
+ ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */
+ ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */
+}adcexazsel_t;
+
+/*!
+ @}
+ */ /* End of group ADC_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/*!
+ @defgroup ADC_Exported_typedef ADC Exported Typedef
+ @{
+ */
+
+/*----------------------------------*/
+/*! @struct adc_clock_t
+ @brief Clock information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period.
+ : Use @ref adc_sampling_period0_t. */
+ adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period.
+ : Use @ref adc_sampling_period1_t. */
+ adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK).
+ : Use @ref adc_sclk_t. */
+ uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */
+} adc_clock_t;
+
+/*----------------------------------*/
+/*! @struct adc_cmpx_t
+ @brief Clock information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t CMPEN; /*!< Enable Register status */
+ uint32_t CMPCNT; /*!< Compare count num. */
+ uint32_t CMPCond; /*!< Compare condition */
+ uint32_t CMPBigSml; /*!< Compare Big/Small condition */
+ uint32_t StrReg; /*!< Compare Store register */
+ uint32_t ADComp; /*!< ADxCMP0 register data */
+ void (*handle)(uint32_t id, TXZ_Result result); /*!< Notity Compare Done. */
+} adc_cmpx_t;
+
+/*----------------------------------*/
+/*! @struct adc_initial_setting_t
+ @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t id; /*!< ID: User value. */
+ adc_clock_t clk; /*!< Clock setting.
+ : Use @ref adc_clock_t. */
+ uint32_t mod1; /*!< AVDD3 voltage band setting.
+ : Use @ref adc_mod1_t. */
+ uint32_t mod2; /*!< Product info setting.
+ : Use @ref adc_mod2_t. */
+ adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */
+
+
+} adc_initial_setting_t;
+
+/*----------------------------------*/
+/*! @struct adc_channel_setting_t
+ @brief Channel Setting. \n
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t interrupt; /*!< Interrupt Enable/Disable.
+ : Use @ref adc_dma_int_t. */
+ uint32_t type; /*!< Conversion Type.
+ : Use @ref adc_conversion_t. */
+ uint32_t ain; /*!< AIN. */
+} adc_channel_setting_t;
+
+/*----------------------------------*/
+/*! @struct adc_internal_info_t
+ @brief Driver internal information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */
+} adc_internal_info_t;
+
+/*----------------------------------*/
+/*! @struct adc_t
+ @brief ADC handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_AD_TypeDef *p_instance; /*!< Registers base address. */
+ adc_initial_setting_t init; /*!< Initial setting. */
+ adc_internal_info_t info; /*!< Driver internal information. */
+ struct
+ {
+ void (*single)(uint32_t id, TXZ_Result result); /*!< Notity Single Conversion Done. */
+ void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notity Continuity Conversion Done. */
+ void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notity Trigger Conversion Done. */
+ void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notity HighPriority Conversion Done. */
+ } handler; /*!< Handler structure. */
+} adc_t;
+
+/**
+ * @}
+ */ /* End of group ADC_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_functions ADC Exported Functions
+ * @{
+ */
+TXZ_Result adc_init(adc_t *p_obj);
+TXZ_Result adc_deinit(adc_t *p_obj);
+TXZ_Result adc_mode1_setting(void);
+TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting);
+TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch);
+TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t);
+TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t);
+TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value);
+TXZ_Result adc_start(adc_t *p_obj);
+TXZ_Result adc_stop(adc_t *p_obj);
+TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status);
+TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout);
+void adc_compa_irq_handler( void );
+void adc_compb_irq_handler( void );
+void adc_single_irq_handler( void );
+void adc_continuity_irq_handler( void );
+void adc_trigger_irq_handler( void );
+/**
+ * @}
+ */ /* End of group ADC_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group ADC */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ADC_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/adc_ch.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,135 @@
+/**
+ *******************************************************************************
+ * @file adc_ch.h
+ * @brief This file provides all the functions prototypes for ADC driver. \n
+ * Channel Class.
+ * @version V1.0.0.0
+ * $Date:: 2017-09-07 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __ADC_CH_H
+#define __ADC_CH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/**
+ * @defgroup ADC ADC
+ * @brief ADC Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_define ADC Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_define ADC Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_typedef ADC Exported Typedef
+ * @{
+ */
+
+/*----------------------------------*/
+/*! @struct adc_ch_initial_setting_t
+ * @brief Initialize Setting.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t interrupt; /*!< Interrupt Enable/Disable.
+ : Use @ref adc_dma_int_t. */
+ uint32_t type; /*!< Conversion Type.
+ : Use @ref adc_conversion_t. */
+ uint32_t ain; /*!< AIN. */
+} adc_ch_initial_setting_t;
+
+/*----------------------------------*/
+/*! @struct adc_ch_t
+ * @brief ADC handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ __IO uint32_t *p_tset; /*!< ADxTSETn Address. */
+ __I uint32_t *p_reg; /*!< ADxREGx Address. */
+ adc_ch_initial_setting_t init; /*!< Initial setting. */
+} adc_ch_t;
+
+/**
+ * @}
+ */ /* End of group ADC_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Exported_functions ADC Exported Functions
+ * @{
+ */
+uint32_t get_conversion_data(uint32_t reg);
+TXZ_Result adc_ch_init(adc_ch_t *p_obj);
+TXZ_Result adc_ch_deinit(adc_ch_t *p_obj);
+TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj);
+TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj);
+TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value);
+/**
+ * @}
+ */ /* End of group ADC_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group ADC */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ADC_CH_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/adc_include.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,349 @@
+/**
+ *******************************************************************************
+ * @file adc_include.h
+ * @brief This file provides internal common definition.
+ * @version V1.0.0.0
+ * $Date:: 2017-09-07 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __ADC_INCLUDE_H
+#define __ADC_INCLUDE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+#include "txz_hal.h"
+
+/**
+ * @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/**
+ * @defgroup ADC ADC
+ * @brief ADC Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+/**
+ * @defgroup NULL_Pointer NULL Pointer
+ * @brief NULL Pointer.
+ * @{
+ */
+#define ADC_NULL ((void *)0) /*!< NULL Pointer. */
+/**
+ * @}
+ */ /* End of group NULL_Pointer */
+
+/**
+ * @defgroup Parameter_Result Parameter Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of group Parameter_Result */
+
+/**
+ * @defgroup ADxCR0 ADxCR0
+ * @brief ADxCR0 Register.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-8 | - |
+ * | 7 | ADEN |
+ * | 6-3 | - |
+ * | 2 | HPSGL |
+ * | 1 | SGL |
+ * | 0 | CNT |
+ * @{
+ */
+/* ADEN */
+#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */
+#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */
+/* HPSGL */
+#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */
+/* SGL */
+#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */
+/* CNT */
+#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */
+#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */
+#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */
+/**
+ * @}
+ */ /* End of group ADxCR0 */
+
+/**
+ * @defgroup ADxCR1 ADxCR1
+ * @brief ADxCR1 Register.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-8 | - |
+ * | 7 | HPDMEN |
+ * | 6 | CNTDMEN |
+ * | 5 | SGLDMEN |
+ * | 4 | TRGDMEN |
+ * | 3:2 | - |
+ * | 1 | HPTRGEN |
+ * | 0 | TRGEN |
+ * @{
+ */
+/* HPDMEN */
+#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */
+#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */
+/* CNTDMEN */
+#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */
+#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */
+/* SGLDMEN */
+#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */
+#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */
+/* TRGDMEN */
+#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */
+#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */
+/* HPTRGEN */
+#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */
+#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */
+/* TRGEN */
+#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */
+#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */
+/**
+ * @}
+ */ /* End of group ADxCR1 */
+
+/**
+ * @defgroup ADxST ADxST
+ * @brief ADxST Register.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-8 | - |
+ * | 7 | ADBF |
+ * | 6-4 | - |
+ * | 3 | CNTF |
+ * | 2 | SNGF |
+ * | 1 | TRGF |
+ * | 0 | HPF |
+ * @{
+ */
+/* ADBF */
+#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */
+#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */
+#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */
+/* CNTF */
+#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */
+#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */
+#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */
+/* SNGF */
+#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */
+#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */
+#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */
+/* TRGF */
+#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */
+#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */
+#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */
+/* PMDF */
+#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */
+#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */
+#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */
+/**
+ * @}
+ */ /* End of group ADxST */
+
+/**
+ * @defgroup ADxMOD0 ADxMOD0.
+ * @brief ADxMOD0 Register.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-2 | - |
+ * | 1 | RCUT |
+ * | 0 | DACON |
+ * @{
+ */
+/* RCUT */
+#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */
+#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */
+/* DACON */
+#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */
+#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */
+/**
+ * @}
+ */ /* End of group ADxMOD0 */
+
+/**
+ * @name ADxCMPEN Macro Definition.
+ * @brief ADxCMPEN Register Macro Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-4 | - |
+ * | 3 | CMP3EN |
+ * | 2 | CMP2EN |
+ * | 1 | CMP1EN |
+ * | 0 | CMP0EN |
+ * @{
+ */
+/* CMP3EN */
+#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */
+#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */
+/* CMP2EN */
+#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */
+#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */
+/* CMP1EN */
+#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */
+#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */
+/* CMP0EN */
+#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */
+#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */
+/**
+ * @}
+ */ /* End of name ADxCMPEN Macro Definition */
+
+/**
+ * @name ADxTSETn Macro Definition.
+ * @brief ADxTSETn Register Macro Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-8 | - |
+ * | 7 | ENINT0 |
+ * | 6-5 | TRGS0[1:0] |
+ * | 4-0 | AINST0[4:0]|
+ * @{
+ */
+/* ENINT0 */
+#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */
+#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */
+#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */
+/* TRGS0[1:0] */
+#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */
+#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */
+#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */
+#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */
+#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */
+/**
+ * @}
+ */ /* End of name ADxTSETn Macro Definition */
+
+/**
+ * @name ADxREGn Macro Definition.
+ * @brief ADxREGn Register Macro Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-30 | - |
+ * | 29 | ADOVRF_Mn |
+ * | 28 | ADRF_Mn |
+ * | 27-16 | ADR_Mn[11:0] |
+ * | 15-4 | ADRn[11:0] |
+ * | 3-2 | - |
+ * | 1 | ADOVRFn |
+ * | 0 | ADRFn |
+ * @{
+ */
+/* ADOVRF_Mn */
+#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */
+#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
+#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */
+/* ADRF_Mn */
+#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */
+#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */
+#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */
+/* ADR_Mn */
+#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */
+/* ADRn */
+#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */
+/* ADOVRFn */
+#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */
+#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
+#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */
+/* ADRFn */
+#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */
+#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */
+#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */
+/**
+ * @}
+ */ /* End of name ADxREGn Macro Definition */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_typedef ADC Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Inline Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_fuctions ADC Private Fuctions
+ * @{
+ */
+/* no define */
+/**
+ * @}
+ */ /* End of group ADC_Private_functions */
+
+/**
+ * @}
+ */ /* End of group ADC */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ADC_INCLUDE_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/tmpm4g9_fc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,137 @@
+/**
+ *******************************************************************************
+ * @file fc.h
+ * @brief Flash_Userboot Sample Application.
+ * @version V1.0.0.0
+ * $date:: $
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FC_H
+#define __FC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+#if defined(__FC_H)
+/** @addtogroup Periph driver
+ * @{
+ */
+
+/** @defgroup fc
+ * @brief fc
+ * @{
+ */
+
+
+/** @defgroup FlashApi_Exported_Types
+ * @{
+ */
+
+/**
+ * @enum fc_sr0_t
+ * @brief Enumerated type definition of the FCSR0 register.
+ */
+typedef enum {
+ FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */
+} fc_sr0_t;
+
+/*----------------------------------*/
+/**
+ * @enum fc_erase_kind_t
+ * @brief FC Erase Flash Kind structure definenition.
+*/
+/*----------------------------------*/
+typedef enum {
+ FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */
+ FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */
+} fc_erase_kind_t;
+
+typedef enum {
+ FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */
+ FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */
+ FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */
+ FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */
+ FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */
+ FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */
+ FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */
+ FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */
+ FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */
+ FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */
+ FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */
+ FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */
+ FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */
+ FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */
+ FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */
+ FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */
+ FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */
+ FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */
+ FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */
+ FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */
+ FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */
+ FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */
+ FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */
+ FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */
+ FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */
+ FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */
+ FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */
+ FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */
+ FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */
+ FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */
+ FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */
+ FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */
+} fc_code_flash_page_number_t;
+
+/** @} */
+/* End of group FlashApi_Exported_Types */
+
+/** @defgroup FlashApi_Exported_Constants
+ * @{
+ */
+
+//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */
+//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */
+#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */
+//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */
+#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */
+//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */
+#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */
+
+/** @} */
+/* End of group FlashApi_Exported_Constants */
+
+
+
+/** @weakgroup FlashApi_Exported_FunctionPrototypes
+ * @{
+ */
+TXZ_WorkState fc_get_status(fc_sr0_t status);
+TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
+TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages);
+TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page);
+TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr);
+
+/** @} */
+/* End of group FlashApi_Exported_FunctionPrototypes */
+
+
+/** @} */
+/* End of group fc */
+
+/** @} */
+/* End of group Periph_driver */
+
+#endif /* defined(__FC_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __FC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/tmpm4g9_rtc.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,386 @@
+/**
+ *******************************************************************************
+ * @file bsp_rtc.h
+ * @brief This file provides all the functions prototypes for RTC Class.
+ * @version V1.0.0.1
+ * $Date:: 2017-09-01 08:26:38 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __BSP_RTC_H
+#define __BSP_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+//#include "txz_sample_def.h"
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @addtogroup BSP_UTILITIES
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup BSP_UTILITIES_Exported_macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup BSP_UTILITIES_Exported_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup BSP_UTILITIES_Exported_define
+ * @{
+ */
+
+/**
+ * @defgroup RTC_RangeSec Range Second
+ * @brief Range of Second.
+ * @brief Range of Second "(RTC_RANGE_SEC_MIN <= Value <= RTC_RANGE_SEC_MAX)".
+ * @{
+ */
+#define RTC_RANGE_SEC_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 sec */
+#define RTC_RANGE_SEC_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 sec */
+/**
+ * @}
+ */ /* End of group RTC_RangeSec */
+
+/**
+ * @defgroup RTC_RangeMin Range Minute
+ * @brief Range of Minute.
+ * @brief Range of Minute "(RTC_RANGE_MIN_MIN <= Value <= RTC_RANGE_MIN_MAX)".
+ * @{
+ */
+#define RTC_RANGE_MIN_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 min */
+#define RTC_RANGE_MIN_MAX ((uint8_t)0x3B) /*!< Maximum Value :59 min */
+/**
+ * @}
+ */ /* End of group RTC_RangeMin */
+
+/**
+ * @defgroup RTC_AlarmMin Alarm Minute
+ * @brief Compare/No Compare minute.
+ * @{
+ */
+#define RTC_ALARM_MIN_OFF ((uint8_t)0x7F) /*!< No compare. */
+#define RTC_ALARM_MIN_ON ((uint8_t)0x00) /*!< Compare. */
+/**
+ * @}
+ */ /* End of group RTC_AlarmMin */
+
+/**
+ * @defgroup RTC_Range24Hour Range 24 Hour
+ * @brief Range of 24 Hour.
+ * @brief Range of 24 Hour "(RTC_RANGE_24_HOUR_MIN <= Value <= RTC_RANGE_24_HOUR_MAX)".
+ * @{
+ */
+#define RTC_RANGE_24_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */
+#define RTC_RANGE_24_HOUR_MAX ((uint8_t)0x17) /*!< Maximum Value :23 hour */
+/**
+ * @}
+ */ /* End of group RTC_Range24Hour */
+
+/**
+ * @defgroup RTC_Range12Hour Range 12 Hour
+ * @brief Range of 12 Hour.
+ * @brief Range of 12 Hour "(RTC_RANGE_12_HOUR_MIN <= Value <= RTC_RANGE_12_HOUR_MAX)".
+ * @{
+ */
+#define RTC_RANGE_12_HOUR_MIN ((uint8_t)0x00) /*!< Minimum Value : 0 hour */
+#define RTC_RANGE_12_HOUR_MAX ((uint8_t)0x0B) /*!< Maximum Value :11 hour */
+/**
+ * @}
+ */ /* End of group RTC_Range12Hour */
+
+/**
+ * @defgroup RTC_Meridiem Meridiem
+ * @brief AM/PM.
+ * @{
+ */
+#define RTC_MERIDIEM_AM ((uint8_t)0x00) /*!< A.M. */
+#define RTC_MERIDIEM_PM ((uint8_t)0x20) /*!< P.M. */
+/**
+ * @}
+ */ /* End of group RTC_Meridiem */
+
+/**
+ * @defgroup RTC_AlarmHour Alarm Hour
+ * @brief Compare/No Compare hour.
+ * @{
+ */
+#define RTC_ALARM_HOUR_OFF ((uint8_t)0x3F) /*!< No compare. */
+#define RTC_ALARM_HOUR_ON ((uint8_t)0x00) /*!< Compare. */
+/**
+ * @}
+ */ /* End of group RTC_AlarmHour */
+
+/**
+ * @defgroup RTC_Day Day Of Week
+ * @brief Day of week.
+ * @{
+ */
+#define RTC_DAY_SUNDAY ((uint8_t)0x00) /*!< Sunday. */
+#define RTC_DAY_MONDAY ((uint8_t)0x01) /*!< Monday. */
+#define RTC_DAY_TUESDAY ((uint8_t)0x02) /*!< Tuesday. */
+#define RTC_DAY_WEDNESDAY ((uint8_t)0x03) /*!< Wednesday. */
+#define RTC_DAY_THURSDAY ((uint8_t)0x04) /*!< Thursday. */
+#define RTC_DAY_FRIDAY ((uint8_t)0x05) /*!< Friday. */
+#define RTC_DAY_SATURDAY ((uint8_t)0x06) /*!< Saturday. */
+/**
+ * @}
+ */ /* End of group RTC_Day */
+
+/**
+ * @defgroup RTC_AlarmDay Alarm Day
+ * @brief Compare/No Compare day.
+ * @{
+ */
+#define RTC_ALARM_DAY_OFF ((uint8_t)0x03) /*!< No compare. */
+#define RTC_ALARM_DAY_ON ((uint8_t)0x00) /*!< Compare. */
+/**
+ * @}
+ */ /* End of group RTC_AlarmDay */
+
+/**
+ * @defgroup RTC_RangeDate Range Date
+ * @brief Range of Date.
+ * @brief Range of Date "(RTC_RANGE_DATE_MIN <= Value <= RTC_RANGE_DATE_MAX)".
+ * @{
+ */
+#define RTC_RANGE_DATE_MIN ((uint8_t)0x00) /*!< Minimum Value :date 00 */
+#define RTC_RANGE_DATE_MAX ((uint8_t)0x1F) /*!< Maximum Value :date 31 */
+/**
+ * @}
+ */ /* End of group RTC_RangeDate */
+
+/**
+ * @defgroup RTC_AlarmDate Alarm Date
+ * @brief Compare/No Compare date.
+ * @{
+ */
+#define RTC_ALARM_DATE_OFF ((uint8_t)0x3F) /*!< No compare. */
+#define RTC_ALARM_DATE_ON ((uint8_t)0x00) /*!< Compare. */
+/**
+ * @}
+ */ /* End of group RTC_AlarmDate */
+
+/**
+ * @defgroup RTC_Month Month
+ * @brief Month.
+ * @{
+ */
+#define RTC_MONTH_JAN ((uint8_t)0x01) /*!< January. */
+#define RTC_MONTH_FEB ((uint8_t)0x02) /*!< February. */
+#define RTC_MONTH_MAR ((uint8_t)0x03) /*!< March. */
+#define RTC_MONTH_APR ((uint8_t)0x04) /*!< April. */
+#define RTC_MONTH_MAY ((uint8_t)0x05) /*!< May. */
+#define RTC_MONTH_JUN ((uint8_t)0x06) /*!< June. */
+#define RTC_MONTH_JUL ((uint8_t)0x07) /*!< July. */
+#define RTC_MONTH_AUG ((uint8_t)0x08) /*!< August. */
+#define RTC_MONTH_SEP ((uint8_t)0x09) /*!< September. */
+#define RTC_MONTH_OCT ((uint8_t)0x10) /*!< October. */
+#define RTC_MONTH_NOV ((uint8_t)0x11) /*!< November. */
+#define RTC_MONTH_DEC ((uint8_t)0x12) /*!< December. */
+/**
+ * @}
+ */ /* End of group RTC_Month */
+
+/**
+ * @defgroup BSP_RTC_HourNotation Hour Notation
+ * @brief 24/12 Hour Notation.
+ * @{
+ */
+#define RTC_HOUR_NOTATION_12 ((uint8_t)0x00) /*!< 12-hour notation. */
+#define RTC_HOUR_NOTATION_24 ((uint8_t)0x01) /*!< 24-hour notation. */
+/**
+ * @}
+ */ /* End of group BSP_RTC_HourNotation */
+
+/**
+ * @defgroup RTC_RangeYear Range Year
+ * @brief Range of Year.
+ * @brief Range of Year "(RTC_RANGE_YEAR_MIN <= Value <= RTC_RANGE_YEAR_MAX)".
+ * @{
+ */
+#define RTC_RANGE_YEAR_MIN ((uint8_t)0x00) /*!< Minimum Value :year 00 */
+#define RTC_RANGE_YEAR_MAX ((uint8_t)0x63) /*!< Maximum Value :year 99 */
+/**
+ * @}
+ */ /* End of group RTC_RangeYear */
+
+/**
+ * @defgroup RTC_LeapYear Leap Year
+ * @brief Leap Year.
+ * @{
+ */
+#define RTC_LEAP_YEAR_0 ((uint8_t)0x00) /*!< Leap year. */
+#define RTC_LEAP_YEAR_1 ((uint8_t)0x01) /*!< 1 year since leap year. */
+#define RTC_LEAP_YEAR_2 ((uint8_t)0x02) /*!< 2 years since leap year. */
+#define RTC_LEAP_YEAR_3 ((uint8_t)0x03) /*!< 3 years since leap year. */
+/**
+ * @}
+ */ /* End of group RTC_LeapYear */
+
+/**
+ * @defgroup RTC_IntSource Interrupt Source Signal
+ * @brief Interrupt Source Signal.
+ * @{
+ */
+#define RTC_INT_SRC_1HZ ((uint8_t)0x47) /*!< 1 Hz. */
+#define RTC_INT_SRC_2HZ ((uint8_t)0xC3) /*!< 2 Hz. */
+#define RTC_INT_SRC_4HZ ((uint8_t)0xC5) /*!< 4 Hz. */
+#define RTC_INT_SRC_8HZ ((uint8_t)0x01) /*!< 8 Hz. */
+#define RTC_INT_SRC_16HZ ((uint8_t)0xC6) /*!< 16 Hz. */
+#define RTC_INT_SRC_ALARM ((uint8_t)0xC7) /*!< Alarm. */
+/**
+ * @}
+ */ /* End of group RTC_IntSource */
+
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup BSP_UTILITIES_Exported_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup BSP_UTILITIES_Exported_typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief RTC handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct uart_handle
+{
+ TSB_RTC_TypeDef *p_instance; /*!< Registers base address. */
+} rtc_t;
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup BSP_UTILITIES_Exported_functions
+ * @{
+ */
+TXZ_Result m4g9_rtc_init(rtc_t *p_obj);
+TXZ_Result rtc_deinit(rtc_t *p_obj);
+TXZ_Result rtc_enable_int(rtc_t *p_obj);
+TXZ_Result rtc_disable_int(rtc_t *p_obj);
+TXZ_Result rtc_set_int_source(rtc_t *p_obj, uint8_t src);
+TXZ_Result rtc_set_hour_notation(rtc_t *p_obj, uint8_t notation);
+TXZ_Result rtc_get_hour_notation(rtc_t *p_obj, uint8_t *p_notation);
+/* clock */
+TXZ_Result rtc_clock_enable(rtc_t *p_obj);
+TXZ_Result rtc_clock_disable(rtc_t *p_obj);
+TXZ_Result rtc_clock_reset_counter(rtc_t *p_obj);
+TXZ_Result rtc_clock_set_sec(rtc_t *p_obj, uint8_t sec);
+TXZ_Result rtc_clock_get_sec(rtc_t *p_obj, uint8_t *p_sec);
+TXZ_Result rtc_clock_set_min(rtc_t *p_obj, uint8_t min);
+TXZ_Result rtc_clock_get_min(rtc_t *p_obj, uint8_t *p_min);
+TXZ_Result rtc_clock_set_hour_24(rtc_t *p_obj, uint8_t hour);
+TXZ_Result rtc_clock_get_hour_24(rtc_t *p_obj, uint8_t *p_hour);
+TXZ_Result rtc_clock_set_hour_12(rtc_t *p_obj, uint8_t meridiem, uint8_t hour);
+TXZ_Result rtc_clock_get_hour_12(rtc_t *p_obj, uint8_t *p_meridiem, uint8_t *p_hour);
+TXZ_Result rtc_clock_set_day(rtc_t *p_obj, uint8_t day);
+TXZ_Result rtc_clock_get_day(rtc_t *p_obj, uint8_t *p_day);
+TXZ_Result rtc_clock_set_date(rtc_t *p_obj, uint8_t date);
+TXZ_Result rtc_clock_get_date(rtc_t *p_obj, uint8_t *p_date);
+TXZ_Result rtc_clock_set_month(rtc_t *p_obj, uint8_t month);
+TXZ_Result rtc_clock_get_month(rtc_t *p_obj, uint8_t *p_month);
+TXZ_Result rtc_clock_set_year(rtc_t *p_obj, uint8_t year);
+TXZ_Result rtc_clock_get_year(rtc_t *p_obj, uint8_t *p_year);
+TXZ_Result rtc_clock_set_leap(rtc_t *p_obj, uint8_t leap);
+TXZ_Result rtc_clock_get_leap(rtc_t *p_obj, uint8_t *p_leap);
+/* alarm */
+TXZ_Result rtc_alarm_enable(rtc_t *p_obj);
+TXZ_Result rtc_alarm_disable(rtc_t *p_obj);
+TXZ_Result rtc_alarm_reset(rtc_t *p_obj);
+TXZ_Result rtc_alarm_set_min(rtc_t *p_obj, uint8_t compare, uint8_t min);
+TXZ_Result rtc_alarm_get_min(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_min);
+TXZ_Result rtc_alarm_set_hour_24(rtc_t *p_obj, uint8_t compare, uint8_t hour);
+TXZ_Result rtc_alarm_get_hour_24(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_hour);
+TXZ_Result rtc_alarm_set_hour_12(rtc_t *p_obj, uint8_t compare, uint8_t meridiem, uint8_t hour);
+TXZ_Result rtc_alarm_get_hour_12(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_meridiem, uint8_t *p_hour);
+TXZ_Result rtc_alarm_set_day(rtc_t *p_obj, uint8_t compare, uint8_t day);
+TXZ_Result rtc_alarm_get_day(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_day);
+TXZ_Result rtc_alarm_set_date(rtc_t *p_obj, uint8_t compare, uint8_t date);
+TXZ_Result rtc_alarm_get_date(rtc_t *p_obj, uint8_t *p_compare, uint8_t *p_date);
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group BSP_UTILITIES */
+
+/**
+ * @}
+ */ /* End of group Sample_Appli */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __BSP_RTC_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_cg.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,113 @@
+/**
+ *******************************************************************************
+ * @file txz_cg.h
+ * @brief This file provides all the functions prototypes for CG driver.
+ * @version V1.0.0.0
+ * $Date:: 2018-04-02 19:31:41 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __CG_H
+#define __CG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup CG CG
+ * @brief CG Driver.
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Exported_define CG Exported Define
+ * @{
+ */
+/* no define */
+/**
+ * @}
+ */ /* End of group CG_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Exported_define CG Exported Define
+ * @{
+ */
+/* no define */
+/**
+ * @}
+ */ /* End of group CG_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Exported_typedef CG Exported Typedef
+ * @{
+ */
+/**
+ * @brief CG member.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_CG_TypeDef *p_instance; /*!< Registers base address. */
+} cg_t;
+
+/**
+ * @}
+ */ /* End of group CG_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Exported_functions CG Exported Functions
+ * @{
+ */
+uint32_t cg_get_fsysm(cg_t *p_obj);
+uint32_t cg_get_phyt0(cg_t *p_obj);
+uint32_t cg_get_mphyt0(cg_t *p_obj);
+TXZ_Result cg_ihosc_enable(cg_t *p_obj);
+TXZ_Result cg_ihosc_disable(cg_t *p_obj);
+/**
+ * @}
+ */ /* End of group CG_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group CG */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __CG_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_driver_def.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,96 @@
+/**
+ *******************************************************************************
+ * @file txz_driver_def.h
+ * @brief All common macro and definition for TXZ peripheral drivers
+ * @version V1.0.0.0
+ * $Date:: 2017-07-21 15:39:36 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TXZ_DRIVER_DEF_H
+#define __TXZ_DRIVER_DEF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF
+ * @brief All common macro and definition for TXZ peripheral drivers
+ * @{
+ */
+
+/** @defgroup Device_Header_Included Device Header Included
+ * @brief Include the Device header file of a Target.
+ * @{
+ */
+#include "TMPM4G9.h" /*!< TMPM4Gx Group Header file. */
+/**
+ * @}
+ */ /* End of group Device_Header */
+
+
+/** @defgroup TXZ_Exported_typedef TXZ Exported typedef
+ * @{
+ */
+typedef enum {
+ TXZ_SUCCESS = 0U,
+ TXZ_ERROR = 1U
+} TXZ_Result;
+
+typedef enum {
+ TXZ_BUSY = 0U,
+ TXZ_DONE = 1U
+} TXZ_WorkState;
+
+typedef enum {
+ TXZ_DISABLE = 0U,
+ TXZ_ENABLE = 1U
+} TXZ_FunctionalState;
+/**
+ * @}
+ */ /* End of group TXZ_Exported_typedef */
+
+/** @defgroup TXZ_Exported_macro TXZ Exported macro
+ * @{
+ */
+#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0)
+
+/**
+ * @brief To report the name of the source file and source line number where the
+ * assert_param error has occurred, "DEBUG" must be defined. And detailed
+ * definition of assert_failed() is needed to be implemented, which can be
+ * done, for example, in the main.c file.
+ */
+#ifdef DEBUG
+void assert_failed(char *file, int32_t line);
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
+#else
+#define assert_param(expr)
+#endif /* DEBUG */
+/**
+ * @}
+ */ /* End of group TXZ_Exported_macro */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+/**
+ * @}
+ */ /* End of group TXZ_DRIVER_DEF */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __TXZ_DRIVER_DEF_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_fuart.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,552 @@
+/**
+ *******************************************************************************
+ * @file txz_fuart.h
+ * @brief This file provides all the functions prototypes for FUART driver.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-06 10:43:01 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __FUART_H
+#define __FUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup FUART FUART
+ * @brief FUART Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Exported_define FUART Exported Define
+ * @{
+ */
+
+/**
+ * @defgroup FUART_FifoMax Max Num of FIFO
+ * @brief Max Num of Tx/Rx Fifo.
+ * @{
+ */
+#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */
+#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */
+/**
+ * @}
+ */ /* End of group UART_FifoMax */
+
+/**
+ * @defgroup FUART_CTSHandshake CTS Handshake
+ * @brief Available CTS Handshake Macro Definisiton.
+ * @{
+ */
+#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */
+/**
+ * @}
+ */ /* End of group FUART_CTSHandshake */
+
+
+/**
+ * @defgroup FUART_RTSHandshake RTS Handshake
+ * @brief Available RTS Handshake Macro Definisiton.
+ * @{
+ */
+#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */
+/**
+ * @}
+ */ /* End of group FUART_RTSHandshake */
+
+/**
+ * @defgroup FUART_FIFO FIFO Enable
+ * @brief FIFO Enable Bit Macro Definisiton.
+ * @{
+ */
+#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */
+#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */
+/**
+ * @}
+ */ /* End of group FUART_FIFO */
+
+
+/**
+ * @defgroup FUART_StopBit Stop Bit
+ * @brief Stop Bit Macro Definisiton.
+ * @{
+ */
+#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */
+#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */
+/**
+ * @}
+ */ /* End of group FUART_StopBit */
+
+
+/**
+ * @defgroup FUART_ParityBit Parity Bit
+ * @brief Parity Bit Macro Definisiton.
+ * @{
+ */
+#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
+#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */
+/**
+ * @}
+ */ /* End of group FUART_ParityBit */
+
+
+/**
+ * @defgroup FUART_ParityEnable Parity Enable
+ * @brief Enable/Disable Parity Macro Definisiton.
+ * @{
+ */
+#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_ParityEnable */
+
+/**
+ * @defgroup FUART_StaticParityEnable Static Parity Enable
+ * @brief Enable/Disable Static Parity Macro Definisiton.
+ * @{
+ */
+#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_ParityEnable */
+
+/**
+ * @defgroup FUART_DataLength Data Length
+ * @brief Data Length Macro Definisiton.
+ * @{
+ */
+#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */
+#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */
+#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */
+#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */
+/**
+ * @}
+ */ /* End of group FUART_DataLength */
+
+/**
+ * @defgroup FUART_FIFO_Level FIFO Level
+ * @brief FIFO Level Macro Definisiton.
+ * @{
+ */
+#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */
+#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */
+#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */
+#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */
+#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */
+
+/**
+ * @}
+ */ /* End of group FUART_DataLength */
+
+/**
+ * @defgroup FUART_TxInterrupt Tx Interrpt
+ * @brief Available Transmit Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */
+/**
+ * @}
+ */ /* End of group FUART_TxInterrupt */
+
+
+/**
+ * @defgroup FUART_RxInterrupt Rx Interrpt
+ * @brief Available Receive Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */
+/**
+ * @}
+ */ /* End of group FUART_RxInterrupt */
+
+
+/**
+ * @defgroup FUART_ErrorInterrupt Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+/**
+ * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_OVER_RUN_ErrorInterrupt */
+
+/**
+ * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_BREAK_ErrorInterrupt */
+
+/**
+ * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_PARITY_ErrorInterrupt */
+
+/**
+ * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_FRAMING_ErrorInterrupt */
+
+/**
+ * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */
+/**
+ * @}
+ */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */
+/**
+ * @}
+ */ /* End of group FUART_ErrorInterrupt */
+
+
+/**
+ * @defgroup FUART_RangeK Range K
+ * @brief Range of K Macro Definisiton.
+ * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)".
+ * @{
+ */
+#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */
+#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */
+/**
+ * @}
+ */ /* End of group FUART_RangeK */
+
+
+/**
+ * @defgroup FUART_RangeN Range N
+ * @brief Range of N Macro Definisiton.
+ * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)".
+ * @{
+ */
+#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */
+#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */
+/**
+ * @}
+ */ /* End of group FUART_RangeN */
+
+
+/**
+ * @defgroup FUART_OverrunErr Overrun Error
+ * @brief Overrun Error Macro Definisiton.
+ * @{
+ */
+#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */
+/**
+ * @}
+ */ /* End of group FUART_OverrunErr */
+
+
+/**
+ * @defgroup FUART_BreakErr Break Error
+ * @brief Break Error Macro Definisiton.
+ * @{
+ */
+#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */
+/**
+ * @}
+ */ /* End of group FUART_BreakErr */
+
+
+/**
+ * @defgroup FUART_ParityErr Parity Error
+ * @brief Parity Error Macro Definisiton.
+ * @{
+ */
+#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */
+/**
+ * @}
+ */ /* End of group FUART_ParityErr */
+
+
+/**
+ * @defgroup FUART_FramingErr Framing Error
+ * @brief Framing Error Macro Definisiton.
+ * @{
+ */
+#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */
+/**
+ * @}
+ */ /* End of group FUART_FramingErr */
+
+/**
+ * @defgroup FUARTxFR FUARTxFR Register
+ * @brief FUARTxFR Register Definition.
+ * @{
+ */
+/* FR */
+#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */
+#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */
+#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */
+#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */
+#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */
+#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */
+
+#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */
+#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */
+#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */
+#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */
+#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */
+#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */
+
+#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */
+#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */
+#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */
+#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */
+#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */
+#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */
+/**
+ * @}
+ */ /* End of group FUARTxFR */
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Exported_define FUART Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Exported_typedef FUART Exported Typedef
+ * @{
+ */
+
+/*----------------------------------*/
+/**
+ * @brief Receive event information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} fuart_receive_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit data information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to transmit data. */
+ uint32_t num; /*!< The number of transmit data. */
+} fuart_transmit_t;
+
+/*----------------------------------*/
+/**
+ * @brief Boudrate setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t brk; /*!< Division Value K.
+ : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */
+ uint32_t brn; /*!< Division Value N.
+ : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */
+} fuart_boudrate_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit FIFO setting.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t inttx; /*!< Available Transmit Interrupt.
+ : Use @ref FUART_TxInterrupt */
+ uint32_t level; /*!< Transmit Fill Level.
+ : Use @ref FUART_FIFO_Level */
+} fuart_tx_int_t;
+
+/*----------------------------------*/
+/**
+ * @brief Receive FIFO setting.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t intrx; /*!< Available Receive Interrupt.
+ : Use @ref FUART_RxInterrupt */
+ uint32_t level; /*!< Receive Fill Level.
+ : Use @ref FUART_FIFO_Level */
+} fuart_rx_int_t;
+
+/*----------------------------------*/
+/**
+ * @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t id; /*!< ID: User value. */
+ fuart_boudrate_t boudrate; /*!< Boudrate setting.
+ : Use @ref fuart_boudrate_t */
+ uint32_t interr; /*!< Available Error Interrupt.
+ : Use @ref FUART_ErrorInterrupt */
+ fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting.
+ : Use @ref fuart_tx_int_t */
+ fuart_rx_int_t rx_int; /*!< Receive Interrupt setting.
+ : Use @ref fuart_rx_int_t */
+ uint32_t ctse; /*!< Available CTS Handshake.
+ : Use @ref FUART_CTSHandshake */
+ uint32_t rtse; /*!< Available RTS Handshake.
+ : Use @ref FUART_RTSHandshake */
+ uint32_t stpa; /*!< Enable/Disable Static Parity.
+ : Use @ref FUART_StaticParityEnable */
+ uint32_t sm; /*!< Data Length.
+ : Use @ref FUART_DataLength */
+ uint32_t fifo; /*!< Available FIFO.
+ : Use @ref FUART_FIFO */
+ uint32_t sblen; /*!< Stop Bit.
+ : Use @ref FUART_StopBit */
+ uint32_t even; /*!< Odd/Even Parity Bit.
+ : Use @ref FUART_ParityBit */
+ uint32_t pe; /*!< Enable/Disable Parity Bit.
+ : Use @ref FUART_ParityEnable */
+} fuart_initial_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief FUART handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */
+ fuart_initial_setting_t init; /*!< Initial setting. */
+ /*------------------------------------------*/
+ /*!
+ @brief Transmit Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ uint32_t rp; /*!< Num of transmited data. */
+ fuart_transmit_t info; /*!< Transmit Data Information. */
+ void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
+ } transmit;
+ /*------------------------------------------*/
+ /*!
+ @brief Receive Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ uint32_t wp; /*!< Num of received data. */
+ fuart_receive_t info; /*!< Receive Data Information. */
+ void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */
+ } receive;
+} fuart_t;
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Exported_functions FUART Exported Functions
+ * @{
+ */
+TXZ_Result fuart_init(fuart_t *p_obj);
+TXZ_Result fuart_deinit(fuart_t *p_obj);
+TXZ_Result fuart_discard_transmit(fuart_t *p_obj);
+TXZ_Result fuart_discard_receive(fuart_t *p_obj);
+TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info);
+TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info);
+void fuart_transmit_irq_handler(fuart_t *p_obj);
+void fuart_receive_irq_handler(fuart_t *p_obj);
+void fuart_error_irq_handler(fuart_t *p_obj);
+void fuart_irq_handler(fuart_t *p_obj);
+TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status);
+TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error);
+TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting);
+/**
+ * @}
+ */ /* End of group FUART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group FUART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __UART_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_fuart_ex.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,110 @@
+/**
+ *******************************************************************************
+ * @file txz_fuart_ex.h
+ * @brief This file provides all the functions prototypes for FUART driver.
+ * @brief Extended functionality.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-06 10:43:01 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __FUART_EX_H
+#define __FUART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+#include "txz_fuart.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup FUART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_functions
+ * @{
+ */
+TXZ_Result fuart_send_break(fuart_t *p_obj);
+TXZ_Result fuart_stop_break(fuart_t *p_obj);
+/**
+ * @}
+ */ /* End of group FUART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group FUART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __FUART_EX_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_fuart_include.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,390 @@
+/**
+ *******************************************************************************
+ * @file txz_fuart_include.h
+ * @brief This file provides internal common definition.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-06 10:43:01 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __FUART_INCLUDE_H
+#define __FUART_INCLUDE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup FUART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_define
+ * @{
+ */
+
+/**
+ * @defgroup FUART_NullPointer Null Pointer
+ * @brief Null Pointer.
+ * @{
+ */
+#define FUART_NULL ((void *)0) /*!< Null Pointer. */
+/**
+ * @}
+ */ /* End of group FUART_NullPointer */
+
+/**
+ * @defgroup FUART_ParameterResult Parameter Check Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of group FUART_ParameterResult */
+
+/**
+ * @defgroup FUARTxDR FUARTxDR Register
+ * @brief FUARTxDR Register Definition.
+ * @{
+ */
+/* DR */
+#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
+/**
+ * @}
+ */ /* End of group FUARTxDR */
+
+/**
+ * @defgroup FUARTxCR FUARTxCR Register
+ * @brief FUARTxCR Register Definition.
+ * @{
+ */
+#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */
+#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */
+#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */
+#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */
+#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */
+
+#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */
+#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */
+#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */
+#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */
+#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */
+
+#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */
+#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */
+#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */
+#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */
+#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */
+/**
+ * @}
+ */ /* End of group FUARTxRSR */
+
+/**
+ * @defgroup FUARTxRSR FUARTxRSR Register
+ * @brief FUARTxRSR Register Definition.
+ * @{
+ */
+#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */
+#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */
+#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */
+#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */
+
+#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */
+#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */
+#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */
+#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */
+/**
+ * @}
+ */ /* End of group FUARTxRSR */
+
+/**
+ * @defgroup FUARTxECR FUARTxECR Register
+ * @brief FUARTxECR Register Definition.
+ * @{
+ */
+/* ECR */
+#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */
+#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */
+#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */
+#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */
+
+#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */
+#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */
+#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */
+#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */
+
+/**
+ * @}
+ */ /* End of group FUARTxECR */
+
+/**
+ * @defgroup FUARTxLCR_H FUARTxRSR Register
+ * @brief FUARTxLCR_H Register Definition.
+ * @{
+ */
+#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */
+
+#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */
+#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */
+/**
+ * @}
+ */ /* End of group FUARTxLCR_H */
+
+/**
+ * @defgroup FUARTxRIS FUARTxRIS Register
+ * @brief FUARTxRIS Register Definition.
+ * @{
+ */
+#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */
+#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */
+#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */
+#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */
+#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */
+#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */
+#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */
+
+#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */
+#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */
+#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */
+#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */
+#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */
+#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */
+#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */
+
+/**
+ * @}
+ */ /* End of group FUARTxRIS */
+
+/**
+ * @defgroup FUARTxMIS FUARTxMIS Register
+ * @brief FUARTxMIS Register Definition.
+ * @{
+ */
+#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */
+#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */
+#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */
+#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */
+#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */
+#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */
+#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */
+
+#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */
+#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */
+#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */
+#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */
+#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */
+#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */
+#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */
+
+/**
+ * @}
+ */ /* End of group FUARTxMIS */
+
+/**
+ * @defgroup FUARTxICR FUARTxICR Register
+ * @brief FUARTxICR Register Definition.
+ * @{
+ */
+#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */
+#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */
+#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */
+#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */
+#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */
+#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */
+#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */
+
+#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */
+#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */
+#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */
+#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */
+#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */
+#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */
+#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */
+
+/**
+ * @}
+ */ /* End of group FUARTxICR */
+
+/**
+ * @defgroup FUARTxDMACR FUARTxDMACR Register
+ * @brief FUARTxDMACR Register Definition.
+ * @{
+ */
+#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */
+#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */
+
+#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */
+#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */
+
+#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */
+#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */
+/**
+ * @}
+ */ /* End of group FUARTxDMACR */
+
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Inline Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_fuctions
+ * @{
+ */
+__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance);
+__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance);
+__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance);
+__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance);
+/*--------------------------------------------------*/
+/**
+ * @brief Disable FUARTxCR TXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 0;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable FUARTxCR TXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,8))) = 1;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disable FUARTxCR RXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 0;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable FUARTxCR RXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR,9))) = 1;
+#endif
+}
+
+
+/**
+ * @}
+ */ /* End of group FUART_Private_functions */
+
+/**
+ * @}
+ */ /* End of group FUART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __UART_EX_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_gpio.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2406 @@
+/**
+ *******************************************************************************
+ * @file txz_gpio.h
+ * @brief This file provides all the functions prototypes for GPIO driver.
+ * @version V1.0.0.
+ * $Date:: 2017-11-09 16:44:27 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __GPIO_H
+#define __GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define TMPM4G9
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup GPIO GPIO
+ * @brief GPIO Driver.
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Exported_define GPIO Exported Define
+ * @{
+ */
+
+
+/**
+ * @defgroup GPIO_Result Result
+ * @brief GPIO Result Macro Definition.
+ * @{
+ */
+#define GPIO_RESULT_SUCCESS (0) /*!< Success */
+#define GPIO_RESULT_FAILURE (-1) /*!< Failure */
+#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */
+/**
+ * @}
+ */ /* End of group GPIO_Result */
+
+/**
+ * @}
+ */ /* End of group GPIO_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef
+ * @{
+ */
+
+/**
+ * @enum gpio_pinstate_t
+ * @brief Pin State Reset/Set Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0, /*!< 0: Clear */
+ GPIO_PIN_SET, /*!< 1: Set */
+}gpio_pinstate_t;
+
+/**
+ * @enum gpio_pininout_t
+ * @brief Pin Input/Output Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PIN_INPUT = 0, /*!< 0: Input */
+ GPIO_PIN_OUTPUT, /*!< 1: Output */
+ GPIO_PIN_INOUT, /*!< 2: Input/Output */
+ GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */
+}gpio_pininout_t;
+
+/**
+ * @enum gpio_gr_t
+ * @brief Port Group Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PORT_A = 0x0, /*!< 0: PA */
+ GPIO_PORT_B, /*!< 1: PB */
+ GPIO_PORT_C, /*!< 2: PC */
+ GPIO_PORT_D, /*!< 3: PD */
+ GPIO_PORT_E, /*!< 4: PE */
+ GPIO_PORT_F, /*!< 5: PF */
+ GPIO_PORT_G, /*!< 6: PG */
+ GPIO_PORT_H, /*!< 7: PH */
+ GPIO_PORT_J, /*!< 8: PJ */
+ GPIO_PORT_K, /*!< 9: PK */
+ GPIO_PORT_L, /*!< 10:PL */
+ GPIO_PORT_M, /*!< 11: PM */
+ GPIO_PORT_N, /*!< 12: PN */
+ GPIO_PORT_P, /*!< 13: PP */
+ GPIO_PORT_R, /*!< 14: PR */
+ GPIO_PORT_T, /*!< 15: PT */
+ GPIO_PORT_U, /*!< 16: PU */
+ GPIO_PORT_V, /*!< 17: PV */
+ GPIO_PORT_W, /*!< 18: PW */
+ GPIO_PORT_Y, /*!< 19: PY */
+ GPIO_GROUP_Max /*!< Max Number */
+}gpio_gr_t;
+
+/**
+ * @enum gpio_num_t
+ * @brief Port Number Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PORT_0 = 0x0, /*!< 0: Port0 */
+ GPIO_PORT_1, /*!< 1: Port1 */
+ GPIO_PORT_2, /*!< 2: Port2 */
+ GPIO_PORT_3, /*!< 3: Port3 */
+ GPIO_PORT_4, /*!< 4: Port4 */
+ GPIO_PORT_5, /*!< 5: Port5 */
+ GPIO_PORT_6, /*!< 6: Port6 */
+ GPIO_PORT_7, /*!< 7: Port7 */
+ GPIO_PORT_Max /*!< Max Number */
+}gpio_num_t;
+
+/**
+ * @enum gpio_fr_t
+ * @brief Port Function Number Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_FR_1 = 1, /*!< 1: PxFR1 */
+ GPIO_FR_2, /*!< 2: PxFR2 */
+ GPIO_FR_3, /*!< 3: PxFR3 */
+ GPIO_FR_4, /*!< 4: PxFR4 */
+ GPIO_FR_5, /*!< 5: PxFR5 */
+ GPIO_FR_6, /*!< 6: PxFR6 */
+ GPIO_FR_7, /*!< 7: PxFR7 */
+ GPIO_FR_NA, /*!< 8: N/A */
+ GPIO_FR_Max, /*!< Max Number */
+}gpio_fr_t;
+
+/**
+ * @enum gpio_mode_t
+ * @brief Port Mode Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */
+ GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */
+ GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */
+ GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */
+ GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */
+ GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */
+ GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */
+ GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */
+ GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */
+ GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */
+ GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */
+ GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */
+ GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */
+}gpio_mode_t;
+
+/**
+ * @enum gpio_pa0_func_t
+ * @brief PortA0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA0_INT02a = 0, /*!< 0: INT02a */
+ GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */
+ GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */
+ GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */
+ GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */
+ GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */
+ GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */
+}gpio_pa0_func_t;
+
+/**
+ * @enum gpio_pa1_func_t
+ * @brief PortA1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */
+ GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */
+ GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */
+ GPIO_PA1_TSPI0CLK = GPIO_FR_7, /*!< PAFR7: TSPI0CLK */
+}gpio_pa1_func_t;
+
+/**
+ * @enum gpio_pa2_func_t
+ * @brief PortA2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */
+ GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */
+ GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */
+}gpio_pa2_func_t;
+
+ /**
+ * @enum gpio_pa3_func_t
+ * @brief PortA3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */
+ GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */
+ GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */
+ GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */
+ GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */
+ GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR6: TSPI2CS1 */
+}gpio_pa3_func_t;
+
+ /**
+ * @enum gpio_pa4_func_t
+ * @brief PortA4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */
+ GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */
+ GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */
+ GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */
+ GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */
+ GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */
+}gpio_pa4_func_t;
+
+/**
+ * @enum gpio_pa5_func_t
+ * @brief PortA5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */
+ GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */
+ GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */
+ GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */
+ GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */
+}gpio_pa5_func_t;
+
+/**
+ * @enum gpio_pa6_func_t
+ * @brief PortA6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */
+ GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */
+ GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */
+ GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */
+}gpio_pa6_func_t;
+
+
+/**
+ * @enum gpio_pa7_func_t
+ * @brief PortA6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PA7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PA7_INT03a = 0, /*!< 0: INT03a */
+ GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */
+ GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */
+ GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */
+ GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */
+ GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */
+ GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */
+}gpio_pa7_func_t;
+
+
+
+/**
+ * @enum gpio_pb0_func_t
+ * @brief PortB0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB0_INT04a = 0, /*!< 0: INT04a */
+ GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */
+ GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */
+ GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */
+ GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */
+}gpio_pb0_func_t;
+
+/**
+ * @enum gpio_pb1_func_t
+ * @brief PortB1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB1_INT05a = 0, /*!< 0: INT05a */
+ GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */
+ GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */
+ GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */
+ GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */
+ GPIO_PB1_HDMAREQB = GPIO_FR_6, /*!< PBFR6: HDMAREQB */
+}gpio_pb1_func_t;
+
+/**
+ * @enum gpio_pb2_func_t
+ * @brief PortB2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */
+ GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */
+ GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */
+}gpio_pb2_func_t;
+
+ /**
+ * @enum gpio_pb3_func_t
+ * @brief PortB3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */
+ GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */
+}gpio_pb3_func_t;
+
+ /**
+ * @enum gpio_pb4_func_t
+ * @brief PortB4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB4_EA12 = GPIO_FR_1, /*!< PBFR1: EA12 */
+ GPIO_PB4_T32A03OUTA = GPIO_FR_3, /*!< PBFR3: T32A03OUTA */
+ GPIO_PB4_T32A03OUTC = GPIO_FR_5, /*!< PBFR5: T32A03OUTC */
+}gpio_pb4_func_t;
+
+/**
+ * @enum gpio_pb5_func_t
+ * @brief PortB5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB5_EA13 = GPIO_FR_1, /*!< PBFR1: EA13 */
+ GPIO_PB5_T32A03OUTB = GPIO_FR_3, /*!< PBFR3: T32A03OUTB */
+}gpio_pb5_func_t;
+
+/**
+ * @enum gpio_pb6_func_t
+ * @brief PortB6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB6_INT06a = 0, /*!< 0: INT06a */
+ GPIO_PB6_EA14 = GPIO_FR_1, /*!< PBFR1: EA14 */
+ GPIO_PB6_T32A03INB1 = GPIO_FR_2, /*!< PBFR2: T32A03INB1 */
+ GPIO_PB6_T32A03INA0 = GPIO_FR_3, /*!< PBFR3: T32A03INA0 */
+ GPIO_PB6_T32A03INC0 = GPIO_FR_5, /*!< PBFR5: T32A03INC0 */
+}gpio_pb6_func_t;
+
+/**
+ * @enum gpio_pb7_func_t
+ * @brief PortB7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PB7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PB7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PB7_INT07a = 0, /*!< 0: INT07a */
+ GPIO_PB7_EA15 = GPIO_FR_1, /*!< PBFR1: EA15 */
+ GPIO_PB7_T32A03INA1 = GPIO_FR_2, /*!< PBFR2: T32A03INA1 */
+ GPIO_PB7_T32A03INB0 = GPIO_FR_3, /*!< PBFR3: T32A03INB0 */
+ GPIO_PB7_T32A03INC1 = GPIO_FR_5, /*!< PBFR5: T32A03INC1 */
+}gpio_pb7_func_t;
+
+
+/**
+ * @enum gpio_pc0_func_t
+ * @brief PortC0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC0_INT12a = 0, /*!< 0: INT12a */
+ GPIO_PC0_EA16 = GPIO_FR_1, /*!< PCFR1: EA16 */
+ GPIO_PC0_T32A08INA0 = GPIO_FR_3, /*!< PCFR3: T32A08INA0 */
+ GPIO_PC0_T32A08INC0 = GPIO_FR_5, /*!< PCFR5: T32A08INC0 */
+}gpio_pc0_func_t;
+
+/**
+ * @enum gpio_pc1_func_t
+ * @brief PortC1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC1_INT13a = 0, /*!< 0: INT13a */
+ GPIO_PC1_EA17 = GPIO_FR_1, /*!< PCFR1: EA17 */
+ GPIO_PC1_T32A08INB0 = GPIO_FR_3, /*!< PCFR3: T32A08INB0 */
+ GPIO_PC1_T32A08INC1 = GPIO_FR_5, /*!< PCFR5: T32A08INC1 */
+}gpio_pc1_func_t;
+
+/**
+ * @enum gpio_pc2_func_t
+ * @brief PortC2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC2_EA18 = GPIO_FR_1, /*!< PCFR1: UT4TXDB */
+ GPIO_PC2_T32A08OUTA = GPIO_FR_3, /*!< PCFR3: T32A08OUTA */
+ GPIO_PC2_T32A08OUTC = GPIO_FR_5, /*!< PCFR5: T32A08OUTC */
+}gpio_pc2_func_t;
+
+ /**
+ * @enum gpio_pc3_func_t
+ * @brief PortC3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC3_EA19 = GPIO_FR_1, /*!< PCFR1: EA19 */
+ GPIO_PC3_T32A08OUTB = GPIO_FR_3, /*!< PCFR3: T32A08OUTB */
+}gpio_pc3_func_t;
+
+ /**
+ * @enum gpio_pc4_func_t
+ * @brief PortC4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */
+ GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */
+ GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */
+}gpio_pc4_func_t;
+
+/**
+ * @enum gpio_pc5_func_t
+ * @brief PortC5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */
+ GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */
+}gpio_pc5_func_t;
+
+/**
+ * @enum gpio_pc6_func_t
+ * @brief PortC6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC6_INT14a = 0, /*!< 0: INT14a */
+ GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */
+}gpio_pc6_func_t;
+
+/**
+ * @enum gpio_pc7_func_t
+ * @brief PortC7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PC7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PC7_INT15a = 0, /*!< 0: INT15a */
+ GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */
+}gpio_pc7_func_t;
+
+/**
+ * @enum gpio_pd0_func_t
+ * @brief PortD0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */
+ GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */
+ GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */
+ GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */
+ GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */
+ GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */
+ GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */
+}gpio_pd0_func_t;
+
+/**
+ * @enum gpio_pd1_func_t
+ * @brief PortD1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */
+ GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */
+ GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */
+ GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */
+ GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */
+ GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */
+}gpio_pd1_func_t;
+
+/**
+ * @enum gpio_pd2_func_t
+ * @brief PortD2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */
+ GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */
+ GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */
+ GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */
+ GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */
+}gpio_pd2_func_t;
+
+ /**
+ * @enum gpio_pd3_func_t
+ * @brief PortD3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */
+ GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */
+ GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */
+ GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */
+}gpio_pd3_func_t;
+
+/**
+ * @enum gpio_pd4_func_t
+ * @brief PortD4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */
+ GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */
+ GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */
+ GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */
+}gpio_pd4_func_t;
+
+/**
+ * @enum gpio_pd5_func_t
+ * @brief PortD5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */
+ GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */
+ GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */
+}gpio_pd5_func_t;
+
+/**
+ * @enum gpio_pd6_func_t
+ * @brief PortD6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */
+ GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */
+ GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */
+ GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */
+ GPIO_PD6_EMG_N = GPIO_FR_7, /*!< PCFR7: EMG_N */
+}gpio_pd6_func_t;
+
+/**
+ * @enum gpio_pd7_func_t
+ * @brief PortD7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PD7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */
+ GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */
+ GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */
+ GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */
+ GPIO_PD7_OVV0_N = GPIO_FR_7, /*!< PCFR7: OVV0_N */
+}gpio_pd7_func_t;
+
+/**
+ * @enum gpio_pe0_func_t
+ * @brief PortE0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */
+ GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */
+ GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */
+ GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */
+ GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */
+ GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */
+}gpio_pe0_func_t;
+
+/**
+ * @enum gpio_pe1_func_t
+ * @brief PortE1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */
+ GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */
+ GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */
+ GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */
+ GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */
+}gpio_pe1_func_t;
+
+/**
+ * @enum gpio_pe2_func_t
+ * @brief PortE2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */
+ GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */
+ GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */
+ GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */
+ GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */
+}gpio_pe2_func_t;
+
+ /**
+ * @enum gpio_pe3_func_t
+ * @brief PortE3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */
+ GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */
+ GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */
+ GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */
+ GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */
+}gpio_pe3_func_t;
+
+ /**
+ * @enum gpio_pe4_func_t
+ * @brief PortE4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */
+ GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */
+ GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */
+ GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */
+ GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */
+}gpio_pe4_func_t;
+
+/**
+ * @enum gpio_pe5_func_t
+ * @brief PortE5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */
+ GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */
+ GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */
+ GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */
+ GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */
+}gpio_pe5_func_t;
+
+/**
+ * @enum gpio_pe6_func_t
+ * @brief PortE6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */
+ GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */
+ GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */
+ GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */
+ GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */
+}gpio_pe6_func_t;
+
+/**
+ * @enum gpio_pe7_func_t
+ * @brief PortE7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PE7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */
+ GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */
+ GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */
+ GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */
+ GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */
+ GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */
+}gpio_pe7_func_t;
+
+/**
+ * @enum gpio_pf0_func_t
+ * @brief PortF0 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF0_INT04b = 0, /*!< 0: INT04b */
+ GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */
+}gpio_pf0_func_t;
+
+/**
+ * @enum gpio_pf1_func_t
+ * @brief PortF1 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */
+}gpio_pf1_func_t;
+
+/**
+ * @enum gpio_pf2_func_t
+ * @brief PortF2 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */
+}gpio_pf2_func_t;
+
+ /**
+ * @enum gpio_pf3_func_t
+ * @brief PortF3 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */
+}gpio_pf3_func_t;
+
+ /**
+ * @enum gpio_pf4_func_t
+ * @brief PortF4 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */
+}gpio_pf4_func_t;
+
+ /**
+ * @enum gpio_pf5_func_t
+ * @brief PortF5 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */
+}gpio_pf5_func_t;
+
+ /**
+ * @enum gpio_pf6_func_t
+ * @brief PortF6 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */
+}gpio_pf6_func_t;
+
+ /**
+ * @enum gpio_pf7_func_t
+ * @brief PortF7 Function Enumerated TyPF Definition.
+ */
+typedef enum
+{
+ GPIO_PF7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PF7_INT05b = 0, /*!< 0: INT05b */
+ GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */
+}gpio_pf7_func_t;
+
+/**
+ * @enum gpio_pg0_func_t
+ * @brief PortG0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG0_INT08a = 0, /*!< 0: INT08a */
+ GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */
+ GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */
+ GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */
+}gpio_pg0_func_t;
+
+/**
+ * @enum gpio_pg1_func_t
+ * @brief PortG1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG1_INT09a = 0, /*!< 0: INT09a */
+ GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */
+ GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */
+ GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */
+}gpio_pg1_func_t;
+
+/**
+ * @enum gpio_pg2_func_t
+ * @brief PortG2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */
+ GPIO_PG2_RTCALARM = GPIO_FR_4, /*!< PCFR4: RTCALARM */
+ GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */
+ GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */
+}gpio_pg2_func_t;
+
+/**
+ * @enum gpio_pg3_func_t
+ * @brief PortG3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */
+ GPIO_PG3_TRGIN = GPIO_FR_4, /*!< PCFR4: TRGIN */
+ GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */
+ GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */
+}gpio_pg3_func_t;
+
+/**
+ * @enum gpio_pg4_func_t
+ * @brief PortG4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */
+ GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */
+ GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */
+ GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */
+}gpio_pg4_func_t;
+
+/**
+ * @enum gpio_pg5_func_t
+ * @brief PortG5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */
+ GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */
+ GPIO_PG5_FUT0SI_SIRIN = GPIO_FR_4, /*!< PCFR4: FUT0SI_SIRIN */
+ GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */
+ GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */
+}gpio_pg5_func_t;
+
+/**
+ * @enum gpio_pg6_func_t
+ * @brief PortG6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */
+ GPIO_PG6_NBD0CLK = GPIO_FR_4, /*!< PCFR4: NBD0CLK */
+ GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */
+}gpio_pg6_func_t;
+
+/**
+ * @enum gpio_pg7_func_t
+ * @brief PortG7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PG7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */
+ GPIO_PG7_NBD0DATA0 = GPIO_FR_4, /*!< PCFR4: NBD0DATA0 */
+ GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */
+}gpio_pg7_func_t;
+
+/**
+ * @enum gpio_ph0_func_t
+ * @brief PortH0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */
+ GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */
+ GPIO_PH0_NBD0DATA1 = GPIO_FR_4, /*!< PCFR4: NBD0DATA1 */
+ GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */
+}gpio_ph0_func_t;
+
+/**
+ * @enum gpio_ph1_func_t
+ * @brief PortH1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */
+ GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */
+ GPIO_PH1_NBD0DATA2 = GPIO_FR_4, /*!< PCFR4: NBD0DATA2 */
+ GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */
+}gpio_ph1_func_t;
+
+/**
+ * @enum gpio_ph2_func_t
+ * @brief PortH2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */
+ GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */
+ GPIO_PH2_NBD0DATA3 = GPIO_FR_4, /*!< PCFR4: NBD0DATA3 */
+ GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */
+}gpio_ph2_func_t;
+
+ /**
+ * @enum gpio_ph3_func_t
+ * @brief PortH3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */
+ GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */
+ GPIO_PH3_NBD0SYNC = GPIO_FR_4, /*!< PCFR4: NBD0SYNC */
+ GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */
+}gpio_ph3_func_t;
+
+ /**
+ * @enum gpio_ph4_func_t
+ * @brief PortH4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */
+ GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */
+ GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */
+}gpio_ph4_func_t;
+
+ /**
+ * @enum gpio_ph5_func_t
+ * @brief PortH5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */
+ GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */
+ GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */
+}gpio_ph5_func_t;
+
+ /**
+ * @enum gpio_ph6_func_t
+ * @brief PortH6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */
+ GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */
+ GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */
+}gpio_ph6_func_t;
+
+ /**
+ * @enum gpio_ph7_func_t
+ * @brief PortH7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PH7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */
+ GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */
+ GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */
+}gpio_ph7_func_t;
+
+/**
+ * @enum gpio_pj0_func_t
+ * @brief PortJ0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */
+ GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */
+}gpio_pj0_func_t;
+
+/**
+ * @enum gpio_pj1_func_t
+ * @brief PortJ1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */
+ GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */
+}gpio_pj1_func_t;
+
+/**
+ * @enum gpio_pj2_func_t
+ * @brief PortJ2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */
+ GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */
+ GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */
+}gpio_pj2_func_t;
+
+ /**
+ * @enum gpio_pj3_func_t
+ * @brief PortJ3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */
+ GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */
+ GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */
+}gpio_pj3_func_t;
+
+ /**
+ * @enum gpio_pj4_func_t
+ * @brief PortJ4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */
+ GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */
+ GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */
+}gpio_pj4_func_t;
+
+/**
+ * @enum gpio_pj5_func_t
+ * @brief PortJ5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */
+ GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */
+ GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */
+}gpio_pj5_func_t;
+
+/**
+ * @enum gpio_pj6_func_t
+ * @brief PortJ6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */
+ GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */
+}gpio_pj6_func_t;
+
+/**
+ * @enum gpio_pj7_func_t
+ * @brief PortJ7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */
+ GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */
+}gpio_pj7_func_t;
+
+/**
+ * @enum gpio_pk0_func_t
+ * @brief PortK0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK0_INT10a = 0, /*!< 0: INT10a */
+ GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */
+ GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */
+ GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */
+ GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */
+}gpio_pk0_func_t;
+
+/**
+ * @enum gpio_pk1_func_t
+ * @brief PortK1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK1_INT11a = 0, /*!< 0: INT11a */
+ GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */
+ GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */
+ GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */
+ GPIO_PK1_HDMAREQA = GPIO_FR_4, /*!< PKFR4: HDMAREQA */
+}gpio_pk1_func_t;
+
+/**
+ * @enum gpio_pk2_func_t
+ * @brief PortK2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */
+ GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */
+}gpio_pk2_func_t;
+
+ /**
+ * @enum gpio_pk3_func_t
+ * @brief PortK3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */
+ GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */
+}gpio_pk3_func_t;
+
+ /**
+ * @enum gpio_pk4_func_t
+ * @brief PortK4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */
+ GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */
+ GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */
+}gpio_pk4_func_t;
+
+/**
+ * @enum gpio_pk5_func_t
+ * @brief PortK5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */
+ GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */
+ GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */
+}gpio_pk5_func_t;
+
+/**
+ * @enum gpio_pk6_func_t
+ * @brief PortK6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */
+ GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */
+ GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */
+ GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */
+ GPIO_PK6_SMI0SCK = GPIO_FR_6, /*!< PKFR6: SMI0SCK */
+}gpio_pk6_func_t;
+
+/**
+ * @enum gpio_pk7_func_t
+ * @brief PortK7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PK7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PK7_INT00a = 0, /*!< 0: INT00a */
+ GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */
+ GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */
+ GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */
+ GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */
+ GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */
+}gpio_pk7_func_t;
+
+/**
+ * @enum gpio_pl0_func_t
+ * @brief PortL0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL0_INT01a = 0, /*!< 0: INT01a */
+ GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */
+ GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */
+ GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */
+ GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */
+}gpio_pl0_func_t;
+
+/**
+ * @enum gpio_pl1_func_t
+ * @brief PortL1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL1_TPI1SCK = GPIO_FR_7, /*!< PLFR7: TPI1SCK */
+}gpio_pl1_func_t;
+
+/**
+ * @enum gpio_pl2_func_t
+ * @brief PortL2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */
+}gpio_pl2_func_t;
+
+ /**
+ * @enum gpio_pl3_func_t
+ * @brief PortL3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */
+ GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */
+ GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */
+ GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */
+}gpio_pl3_func_t;
+
+ /**
+ * @enum gpio_pl4_func_t
+ * @brief PortL4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL4_INT12b = 0, /*!< 0: IN112b */
+ GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */
+ GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */
+}gpio_pl4_func_t;
+
+/**
+ * @enum gpio_pl5_func_t
+ * @brief PortL5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL5_INT13b = 0, /*!< 0: INT13b */
+ GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */
+}gpio_pl5_func_t;
+
+/**
+ * @enum gpio_pl6_func_t
+ * @brief PortL6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL6_INT03b = 0, /*!< 0: INT03b */
+ GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */
+ GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */
+}gpio_pl6_func_t;
+
+/**
+ * @enum gpio_pl7_func_t
+ * @brief PortL7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PL7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PL7_TRGIN = GPIO_FR_1, /*!< PLFR1: TRGIN */
+ GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */
+}gpio_pl7_func_t;
+
+/**
+ * @enum gpio_pm0_func_t
+ * @brief PortM0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */
+ GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */
+ GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */
+ GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */
+}gpio_pm0_func_t;
+
+/**
+ * @enum gpio_pm1_func_t
+ * @brief PortM1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */
+ GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */
+ GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */
+ GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */
+}gpio_pm1_func_t;
+
+/**
+ * @enum gpio_pm2_func_t
+ * @brief PortM2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */
+ GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */
+ GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */
+ GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */
+ GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */
+}gpio_pm2_func_t;
+
+ /**
+ * @enum gpio_pm3_func_t
+ * @brief PortM3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM3_INT14b = 0, /*!< 0: INT14b */
+ GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */
+ GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */
+ GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */
+ GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */
+ GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */
+}gpio_pm3_func_t;
+
+ /**
+ * @enum gpio_pm4_func_t
+ * @brief PortM4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM4_INT15b = 0, /*!< 0: INT15b */
+ GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */
+ GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */
+ GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */
+ GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */
+}gpio_pm4_func_t;
+
+/**
+ * @enum gpio_pm5_func_t
+ * @brief PortM5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */
+ GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */
+ GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */
+ GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */
+}gpio_pm5_func_t;
+
+/**
+ * @enum gpio_pm6_func_t
+ * @brief PortM6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */
+ GPIO_PM6_T32A76OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */
+ GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */
+ GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */
+ GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */
+ GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */
+}gpio_pm6_func_t;
+
+/**
+ * @enum gpio_pm7_func_t
+ * @brief PortM7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PM7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */
+ GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */
+ GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */
+ GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */
+ GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */
+}gpio_pm7_func_t;
+
+/**
+ * @enum gpio_pn0_func_t
+ * @brief PortN0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */
+}gpio_pn0_func_t;
+
+/**
+ * @enum gpio_pn1_func_t
+ * @brief PortN1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */
+}gpio_pn1_func_t;
+
+/**
+ * @enum gpio_pn2_func_t
+ * @brief PortN2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */
+}gpio_pn2_func_t;
+
+/**
+ * @enum gpio_pn3_func_t
+ * @brief PortN3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */
+}gpio_pn3_func_t;
+
+ /**
+ * @enum gpio_pn4_func_t
+ * @brief PortN4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */
+}gpio_pn4_func_t;
+
+/**
+ * @enum gpio_pn5_func_t
+ * @brief PortN5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */
+}gpio_pn5_func_t;
+
+/**
+ * @enum gpio_pn6_func_t
+ * @brief PortN6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */
+}gpio_pn6_func_t;
+
+/**
+ * @enum gpio_pn7_func_t
+ * @brief PortN7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */
+}gpio_pn7_func_t;
+
+/**
+ * @enum gpio_pp0_func_t
+ * @brief PortP0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */
+ GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */
+ GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */
+ GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */
+}gpio_pp0_func_t;
+
+/**
+ * @enum gpio_pp1_func_t
+ * @brief PortP1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */
+ GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */
+ GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */
+ GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */
+}gpio_pp1_func_t;
+
+/**
+ * @enum gpio_pp2_func_t
+ * @brief PortP2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */
+ GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */
+ GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */
+ GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */
+}gpio_pp2_func_t;
+
+ /**
+ * @enum gpio_pp3_func_t
+ * @brief PortP3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */
+ GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */
+ GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */
+ GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */
+}gpio_pp3_func_t;
+
+ /**
+ * @enum gpio_pp4_func_t
+ * @brief PortP4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */
+ GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */
+ GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */
+ GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */
+}gpio_pp4_func_t;
+
+ /**
+ * @enum gpio_pp5_func_t
+ * @brief PortP5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */
+ GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */
+ GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */
+ GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */
+}gpio_pp5_func_t;
+
+/**
+ * @enum gpio_pp6_func_t
+ * @brief PortP6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */
+ GPIO_PP6_INT10b = 0, /*!< 0: INT10b */
+ GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */
+ GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */
+ GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */
+}gpio_pp6_func_t;
+
+ /**
+ * @enum gpio_pp7_func_t
+ * @brief PortP7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PP7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */
+ GPIO_PP7_INT11b = 0, /*!< 0: INT11b */
+ GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */
+ GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */
+ GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */
+}gpio_pp7_func_t;
+
+/**
+ * @enum gpio_pr0_func_t
+ * @brief PortR0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */
+ GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */
+ GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */
+}gpio_pr0_func_t;
+
+/**
+ * @enum gpio_pr1_func_t
+ * @brief PortR1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */
+ GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */
+ GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */
+}gpio_pr1_func_t;
+
+/**
+ * @enum gpio_pr2_func_t
+ * @brief PortR2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */
+ GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */
+ GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */
+}gpio_pr2_func_t;
+
+/**
+ * @enum gpio_pr3_func_t
+ * @brief PortR3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */
+ GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */
+ GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */
+}gpio_pr3_func_t;
+
+/**
+ * @enum gpio_pr4_func_t
+ * @brief PortR4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */
+ GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */
+ GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */
+}gpio_pr4_func_t;
+
+/**
+ * @enum gpio_pr5_func_t
+ * @brief PortR5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */
+ GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */
+ GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */
+}gpio_pr5_func_t;
+
+/**
+ * @enum gpio_pr6_func_t
+ * @brief PortR6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */
+ GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */
+ GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */
+}gpio_pr6_func_t;
+
+/**
+ * @enum gpio_pr7_func_t
+ * @brief PortR7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PR7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */
+ GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */
+ GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */
+}gpio_pr7_func_t;
+
+
+/**
+ * @enum gpio_pt0_func_t
+ * @brief PortT0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */
+}gpio_pt0_func_t;
+
+/**
+ * @enum gpio_pt1_func_t
+ * @brief PortT1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */
+ GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */
+}gpio_pt1_func_t;
+
+/**
+ * @enum gpio_pt2_func_t
+ * @brief PortT2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */
+}gpio_pt2_func_t;
+
+/**
+ * @enum gpio_pt3_func_t
+ * @brief PortT3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PT3_INT00b = 0, /*!< 0: INT00b */
+ GPIO_PT3_RTCCLK = GPIO_FR_1, /*!< PTFR1: RTCCLK */
+ GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */
+ GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */
+ GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */
+ GPIO_PT3_MDMAREQA = GPIO_FR_6, /*!< PTFR6: MDMAREQA */
+}gpio_pt3_func_t;
+
+/**
+ * @enum gpio_pt4_func_t
+ * @brief PortT4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PT4_INT01b = 0, /*!< 0: INT01b */
+ GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */
+}gpio_pt4_func_t;
+
+/**
+ * @enum gpio_pt5_func_t
+ * @brief PortT5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PT5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PT5_INT02b = 0, /*!< 0: INT02b */
+ GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */
+}gpio_pt5_func_t;
+
+/**
+ * @enum gpio_pu0_func_t
+ * @brief PortU0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */
+ GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */
+ GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */
+}gpio_pu0_func_t;
+
+/**
+ * @enum gpio_pu1_func_t
+ * @brief PortU1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU1_T32A12OUTB = GPIO_FR_2, /*!< PUFR2: T32A12OUTB */
+ GPIO_PU1_UT4RXD = GPIO_FR_7, /*!< PUFR7: UT4RXD */
+}gpio_pu1_func_t;
+
+/**
+ * @enum gpio_pu2_func_t
+ * @brief PortU2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU2_INT06b = 0, /*!< 0: INT06b */
+ GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */
+ GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */
+ GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */
+}gpio_pu2_func_t;
+
+/**
+ * @enum gpio_pu3_func_t
+ * @brief PortU3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU3_INT07b = 0, /*!< 0: INT07b */
+ GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */
+ GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */
+ GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */
+}gpio_pu3_func_t;
+
+/**
+ * @enum gpio_pu4_func_t
+ * @brief PortU4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU4_INT08b = 0, /*!< 0: INT08b */
+ GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */
+ GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */
+ GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */
+}gpio_pu4_func_t;
+
+/**
+ * @enum gpio_pu5_func_t
+ * @brief PortU5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU5_INT09b = 0, /*!< 0: INT09b */
+ GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */
+ GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */
+ GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */
+}gpio_pu5_func_t;
+
+/**
+ * @enum gpio_pu6_func_t
+ * @brief PortU6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */
+ GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */
+ GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */
+}gpio_pu6_func_t;
+
+/**
+ * @enum gpio_pu7_func_t
+ * @brief PortU7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PU7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */
+ GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */
+}gpio_pu7_func_t;
+
+/**
+ * @enum gpio_pv0_func_t
+ * @brief PortV0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */
+ GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */
+ GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */
+ GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */
+ GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */
+ GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */
+}gpio_pv0_func_t;
+
+/**
+ * @enum gpio_pv1_func_t
+ * @brief PortV1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */
+ GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */
+ GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */
+ GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */
+ GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */
+ GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */
+}gpio_pv1_func_t;
+
+/**
+ * @enum gpio_pv2_func_t
+ * @brief PortV2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */
+ GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */
+ GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */
+ GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */
+ GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */
+ GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */
+}gpio_pv2_func_t;
+
+/**
+ * @enum gpio_pv3_func_t
+ * @brief PortV3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */
+ GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */
+ GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */
+ GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */
+ GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */
+}gpio_pv3_func_t;
+
+/**
+ * @enum gpio_pv4_func_t
+ * @brief PortV4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */
+ GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */
+ GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */
+ GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */
+ GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */
+}gpio_pv4_func_t;
+
+/**
+ * @enum gpio_pv5_func_t
+ * @brief PortV5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */
+ GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */
+ GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */
+ GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */
+ GPIO_PV5_I2CSDA = GPIO_FR_6, /*!< PVFR6: I2CSDA */
+ GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */
+}gpio_pv5_func_t;
+
+/**
+ * @enum gpio_pv6_func_t
+ * @brief PortV6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */
+ GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */
+ GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */
+ GPIO_PV6_EMG0_N = GPIO_FR_5, /*!< PVFR5: EMG0_N */
+ GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */
+}gpio_pv6_func_t;
+
+/**
+ * @enum gpio_pv7_func_t
+ * @brief PortV7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PV7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */
+ GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */
+ GPIO_PV7_OVV0_N = GPIO_FR_5, /*!< PVFR5: OVV0_N */
+ GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */
+ GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */
+}gpio_pv7_func_t;
+
+/**
+ * @enum gpio_pw0_func_t
+ * @brief PortW0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW0_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */
+ GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */
+ GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */
+}gpio_pw0_func_t;
+
+/**
+ * @enum gpio_pw1_func_t
+ * @brief PortW1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW1_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */
+ GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */
+ GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */
+}gpio_pw1_func_t;
+
+/**
+ * @enum gpio_pw2_func_t
+ * @brief PortW2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW2_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */
+ GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */
+ GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */
+}gpio_pw2_func_t;
+
+/**
+ * @enum gpio_pw3_func_t
+ * @brief PortW3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW3_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */
+ GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */
+}gpio_pw3_func_t;
+
+/**
+ * @enum gpio_pw4_func_t
+ * @brief PortW4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */
+ GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */
+ GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */
+ GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */
+}gpio_pw4_func_t;
+
+/**
+ * @enum gpio_pw5_func_t
+ * @brief PortW5 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW5_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */
+ GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */
+ GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */
+}gpio_pw5_func_t;
+
+/**
+ * @enum gpio_pw6_func_t
+ * @brief PortW6 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW6_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */
+ GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */
+ GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */
+}gpio_pw6_func_t;
+
+/**
+ * @enum gpio_pw7_func_t
+ * @brief PortW7 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PW7_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */
+ GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */
+ GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */
+ GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */
+}gpio_pw7_func_t;
+
+/**
+ * @enum gpio_py0_func_t
+ * @brief PortY0 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */
+}gpio_py0_func_t;
+
+/**
+ * @enum gpio_py1_func_t
+ * @brief PortY1 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */
+}gpio_py1_func_t;
+
+/**
+ * @enum gpio_py2_func_t
+ * @brief PortY2 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */
+}gpio_py2_func_t;
+
+/**
+ * @enum gpio_py3_func_t
+ * @brief PortY3 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */
+ GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */
+}gpio_py3_func_t;
+
+/**
+ * @enum gpio_py4_func_t
+ * @brief PortY4 Function Enumerated Type Definition.
+ */
+typedef enum
+{
+ GPIO_PY4_INPUT = 0, /*!< 0: Input Port */
+ GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */
+ GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */
+ GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */
+}gpio_py4_func_t;
+
+/**
+ * @}
+ */ /* End of group GPIO_Exported_Typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief GPIO handle structure definenition.
+*/
+/*----------------------------------*/
+#if defined(TMPM4G6)
+typedef struct gpio_pa_handle
+{
+ TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */
+ TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */
+ TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */
+ TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */
+ TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */
+ TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */
+ TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */
+ TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */
+ TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */
+ TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */
+ TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */
+ TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */
+ TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */
+} _gpio_t;
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+typedef struct gpio_pa_handle
+{
+ TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */
+ TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */
+ TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */
+ TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */
+ TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */
+ TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */
+ TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */
+ TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */
+ TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */
+ TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */
+ TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */
+ TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */
+ TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */
+ TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */
+ TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */
+ TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */
+} _gpio_t;
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+typedef struct gpio_pa_handle
+{
+ TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */
+ TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */
+ TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */
+ TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */
+ TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */
+ TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */
+ TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */
+ TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */
+ TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */
+ TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */
+ TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */
+ TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */
+ TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */
+ TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */
+ TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */
+ TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */
+ TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */
+} _gpio_t;
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+typedef struct gpio_pa_handle
+{
+ TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */
+ TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */
+ TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */
+ TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */
+ TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */
+ TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */
+ TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */
+ TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */
+ TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */
+ TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */
+ TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */
+ TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */
+ TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */
+ TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */
+ TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */
+ TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */
+ TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */
+ TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */
+ TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */
+ TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */
+} _gpio_t;
+#endif /* TMPM4G9 */
+
+/**
+ * @}
+ */ /* End of group GPIO_Exported_Typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Exported_functions GPIO Exported Functions
+ * @{
+ */
+TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group);
+TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group);
+TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val);
+TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val);
+TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout);
+TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
+TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
+TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val);
+TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val);
+TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate);
+
+/**
+ * @}
+ */ /* End of group GPIO_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group GPIO */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __GPIO_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_hal.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,126 @@
+/**
+ *******************************************************************************
+ * @file txz_hal.h
+ * @brief This file provides all the functions prototypes for driver common part.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-09 11:01:04 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __HAL_H
+#define __HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup HAL HAL
+ * @brief HAL Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Exported_macro HAL Exported Macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Exported_define HAL Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Exported_define HAL Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Exported_typedef HAL Exported Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Exported_functions HAL Exported Functions
+ * @{
+ */
+
+void hal_inc_tick(void);
+uint32_t hal_get_tick(void);
+
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group HAL */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __HAL_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_i2c.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,843 @@
+/**
+ *******************************************************************************
+ * @file txz_i2c.h
+ * @brief This file provides all the functions prototypes for I2C Class.
+ * @version V1.0.0.4
+ * $Date:: 2016-11-24 00:00:00 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __I2C_H
+#define __I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @addtogroup UTILITIES
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+#ifdef DEBUG
+/**
+ * @name I2C_NULL Pointer
+ * @brief NULL Pointer.
+ * @{
+ */
+#define I2C_NULL ((void *)0)
+/**
+ * @}
+ */ /* End of name I2C_NULL Pointer */
+#endif
+
+/**
+ * @name I2CxST Macro Definition.
+ * @brief I2CxST Register Macro Definition.
+ * @{
+ */
+#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */
+#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */
+#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */
+#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */
+#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */
+/**
+ * @}
+ */ /* End of name I2CxST Macro Definition */
+
+/**
+ * @name I2CxCR1 Macro Definition.
+ * @brief I2CxCR1 Register Macro Definition.
+ * @{
+ */
+#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */
+#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */
+#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */
+
+/**
+ * @}
+ */ /* End of name I2CxCR1 Macro Definition */
+
+/**
+ * @name I2CxDBR Macro Definition.
+ * @brief I2CxDBR Register Macro Definition.
+ * @{
+ */
+#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */
+/**
+ * @}
+ */ /* End of name I2CxDBR Macro Definition */
+
+
+/**
+ * @name I2CxCR2 Macro Definition.
+ * @brief I2CxCR2 Register Macro Definition.
+ * @{
+ */
+#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */
+#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */
+#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */
+#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */
+#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */
+#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */
+#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */
+#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */
+
+/**
+ * @}
+ */ /* End of name I2CxCR2 Macro Definition */
+
+/**
+ * @name I2CxSR Macro Definition.
+ * @brief I2CxSR Register Macro Definition.
+ * @{
+ */
+#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */
+#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */
+#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */
+#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */
+#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */
+#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */
+#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */
+#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */
+/**
+ * @}
+ */ /* End of name I2CxSR Macro Definition */
+
+/**
+ * @name I2CxPRS Macro Definition.
+ * @brief I2CxPRS Register Macro Definition.
+ * @{
+ */
+#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */
+/**
+ * @}
+ */ /* End of name I2CxPRS Macro Definition */
+
+/**
+ * @name I2CxIE Macro Definition.
+ * @brief I2CxIE Register Macro Definition.
+ * @{
+ */
+#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */
+#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */
+#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */
+#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */
+#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */
+
+/**
+ * @}
+ */ /* End of name I2CxIE Macro Definition */
+
+
+/**
+ * @name I2CxOP Macro Definition.
+ * @brief I2CxOP Register Macro Definition.
+ * @{
+ */
+#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */
+#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */
+#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */
+#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */
+#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */
+#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */
+#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */
+#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */
+#ifndef I2C_MULTI_MASTER
+ #define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */
+#else
+ #define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */
+#endif
+#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */
+/**
+ * @}
+ */ /* End of name I2CxOP Macro Definition */
+
+/**
+ * @name I2CxAR Macro Definition.
+ * @brief I2CxAR Register Macro Definition.
+ * @{
+ */
+#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */
+#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
+#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
+
+/**
+ * @}
+ */ /* End of name I2CxAR Macro Definition */
+
+
+/**
+ * @name I2CxPM Macro Definition.
+ * @brief I2CxPM Register Macro Definition.
+ * @{
+ */
+#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */
+/**
+ * @}
+ */ /* End of name I2CxPM Macro Definition */
+
+/**
+ * @name I2CxWUPCR_INT Macro Definition.
+ * @brief I2CxWUPCR_INT Register Macro Definition.
+ * @{
+ */
+#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */
+#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */
+/**
+ * @}
+ */ /* End of name I2CxWUPCR_INT Macro Definition */
+
+/**
+ * @name I2CxWUPCR_RST Macro Definition.
+ * @brief I2CxWUPCR_RST Register Macro Definition.
+ * @{
+ */
+#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */
+#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */
+/**
+ * @}
+ */ /* End of name I2CxWUPCR_RST Macro Definition */
+
+
+/**
+ * @name I2CxWUPCR_ACK Macro Definition.
+ * @brief I2CxWUPCR_ACK Register Macro Definition.
+ * @{
+ */
+#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */
+#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */
+/**
+ * @}
+ */ /* End of name I2CxWUPCR_RST Macro Definition */
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_typedef
+ * @{
+ */
+
+/*----------------------------------*/
+/**
+ * @brief Clock setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t sck; /*!< Select internal SCL output clock frequency. */
+ uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */
+} I2C_clock_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief Wakeup Control setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t sgcdi; /*!< Select general call detect ON/OFF. */
+ uint32_t ack; /*!< Select ACK output. */
+ uint32_t reset; /*!< I2C BUS Rest. */
+ uint32_t intend; /*!< Interrupt release. */
+} I2CS_wup_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ I2C_clock_setting_t clock; /*!< Serial clock setting. */
+} I2C_initial_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */
+} I2CS_initial_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief I2C handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */
+ I2C_initial_setting_t init; /*!< Initial setting. */
+} I2C_t;
+#if defined(I2CSxWUP_EN)
+/*----------------------------------*/
+/**
+ * @brief I2CS handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */
+ I2CS_initial_setting_t init; /*!< Initial setting. */
+} I2CS_t;
+#endif
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Inline Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_functions
+ * @{
+ */
+__STATIC_INLINE void I2C_reset(I2C_t *p_obj);
+__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj);
+__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj);
+__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj);
+__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data);
+__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj);
+__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack);
+__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj);
+__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj);
+__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj);
+__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj);
+__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj);
+__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj);
+__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj);
+__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx);
+__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj);
+__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr);
+__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj);
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C software reset.
+ * @param p_obj :I2C object.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_reset(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
+ p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
+ }
+#else
+ p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
+ p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C bus port high
+ * @param p_obj :I2C object.
+ * @retval true :SDA and SCL Port High.
+ * @retval false :Bus Error.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
+ }
+ return (0);
+#else
+ return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Generate stop condition.
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
+ }
+#else
+ p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Read from Data buffer
+ * @param p_obj :I2C object.
+ * @retval result :Read data.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
+ }
+ return (0);
+#else
+ return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Write to Data buffer.
+ * @param p_obj :I2C object.
+ * @param data :Write data.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
+ }
+#else
+ p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return restart condition
+ * @param p_obj :I2C object.
+ * @retval true :Restart Detected.
+ * @retval false :Restart Non-Detected.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ __IO uint32_t opreg = p_obj->p_instance->OP;
+ p_obj->p_instance->OP &= ~I2CxOP_RSTA;
+ return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
+ }
+ return (0);
+#else
+ __IO uint32_t opreg = p_obj->p_instance->OP;
+ p_obj->p_instance->OP &= ~I2CxOP_RSTA;
+ return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Ack condition
+ * @param p_obj :I2C object.
+ * @param nack :1 NACK, 0 ACK.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ if (nack)
+ {
+ p_obj->p_instance->OP |= I2CxOP_MFACK;
+ }
+ else
+ {
+ p_obj->p_instance->OP &= ~I2CxOP_MFACK;
+ }
+ }
+#else
+ if (nack)
+ {
+ p_obj->p_instance->OP |= I2CxOP_MFACK;
+ }
+ else
+ {
+ p_obj->p_instance->OP &= ~I2CxOP_MFACK;
+ }
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return received Ack condition
+ * @param p_obj :I2C object.
+ * @retval true :NACK Received.
+ * @retval false :ACK Received.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return Busy condition
+ * @param p_obj :I2C object.
+ * @retval true :I2C bus busy.
+ * @retval false :I2C bus free.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return The Master status
+ * @param p_obj :I2C object.
+ * @retval true :Master mode.
+ * @retval false :Slave mode.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return The Transmitter
+ * @param p_obj :I2C object.
+ * @retval true :Transmitter.
+ * @retval false :Receiver.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Interrupt Status
+ * @param p_obj :I2C object.
+ * @retval true :Interruput Occured.
+ * @retval false :No Interruput Occured.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Interrupt Status Clear
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->ST = I2CxST_CLEAR;
+ }
+#else
+ p_obj->p_instance->ST = I2CxST_CLEAR;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable Interrupt setting.
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->IE = I2CxIE_I2C;
+ }
+#else
+ p_obj->p_instance->IE = I2CxIE_I2C;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable Interrupt setting.
+ * @param p_obj :I2C object.
+ * @param tx :Direction of transfer(1=tx 0=rx).
+ * @retval -
+ * @note For DMA transfer.
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ if (tx)
+ {
+ p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
+ }
+ else
+ {
+ p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
+ }
+ }
+#else
+ if (tx)
+ {
+ p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
+ }
+ else
+ {
+ p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
+ }
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disable Interrupt setting.
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->IE = I2CxIE_CLEAR;
+ }
+#else
+ p_obj->p_instance->IE = I2CxIE_CLEAR;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set slave address.
+ * @param p_obj :I2C object.
+ * @param addr :slave address.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
+ p_obj->p_instance->AR2 = I2CxAR2_INIT;
+ }
+#else
+ p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
+ p_obj->p_instance->AR2 = I2CxAR2_INIT;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Detecting Slave Address
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
+ && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
+ }
+ return (0);
+#else
+ return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
+ && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
+#endif
+}
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_functions
+ * @{
+ */
+void I2C_init(I2C_t *p_obj);
+void I2C_start_condition(I2C_t *p_obj, uint32_t data);
+uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting);
+void I2C_slave_init(I2C_t *p_obj);
+#if defined(I2CSxWUP_EN)
+void I2CS_init(I2CS_t *p_obj);
+void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
+void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
+#endif
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_functions */
+
+/**
+ * @}
+ */ /* End of group UTILITIES */
+
+/**
+ * @}
+ */ /* End of group Example */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __I2C_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_i2c_api.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,311 @@
+/**
+ *******************************************************************************
+ * @file bsp_i2c.h
+ * @brief This file provides all the functions prototypes for I2C Driver.
+ * @version V1.0.0.2
+ * $Date:: 2017-10-03 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __BSP_I2C_H
+#define __BSP_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_i2c.h"
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @addtogroup UTILITIES
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_define
+ * @{
+ */
+/**
+ * @defgroup I2C_NullPointer Null Pointer
+ * @brief I2C NULL Pointer.
+ * @{
+ */
+#define I2C_NULL ((void *)0)
+/**
+ * @}
+ */ /* End of group I2C_NullPointer */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_define
+ * @{
+ */
+
+/**
+ * @defgroup I2C_ACK I2C ACK Macros
+ * @brief I2C Type of Acknowledge.
+ * @{
+ */
+#define I2C_NACK (0) /*!< NACK Received. */
+#define I2C_ACK (1) /*!< ACK Received. */
+/**
+ * @}
+ */ /* End of group I2C_ACK */
+
+
+/**
+ * @defgroup I2C_ERROR I2C ERROR Macros
+ * @brief I2C Error definitions.
+ * @{
+ */
+#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */
+#if 0
+#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */
+#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */
+#endif
+#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */
+#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */
+#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */
+/**
+ * @}
+ */ /* End of group I2C_ERROR */
+
+
+/**
+ * @defgroup I2C_Events I2C Events Macros
+ * @brief I2C Asynch Events.
+ * @{
+ */
+#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */
+#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */
+#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */
+#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+/**
+ * @}
+ */ /* End of group I2C_Events */
+
+/**
+ * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros
+ * @brief I2C Received Contents of Slave.
+ * @{
+ */
+#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */
+#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */
+#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */
+#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */
+/**
+ * @}
+ */ /* End of group I2C_SlaveReceive */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_define
+ * @{
+ */
+
+/*----------------------------------*/
+/**
+ * @brief i2c Port Enumerated Type Definition.
+*/
+/*----------------------------------*/
+typedef enum {
+ I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */
+ I2C_PORT_PG3, /*!< 1: PG3 I2C0 */
+ I2C_PORT_PF2, /*!< 2: PF2 I2C1 */
+ I2C_PORT_PF3, /*!< 3: PF3 I2C1 */
+ I2C_PORT_PG4, /*!< 4: PG4 I2C2 */
+ I2C_PORT_PG5, /*!< 5: PG5 I2C2 */
+ I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */
+ I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */
+ I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */
+ I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */}
+i2c_port_t;
+
+/*----------------------*/
+/* I2C Setting */
+/*----------------------*/
+/* #define I2C_CHANNEL0 */
+#define I2C_CHANNEL3
+/* #define I2C_CHANNEL2 */
+/* #define I2C_CHANNEL3 */
+/* #define I2C_CHANNEL4 */
+#if defined(I2C_CHANNEL0)
+ #define I2Cx_TEXT "I2C0"
+ #define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */
+ #define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */
+#elif defined(I2C_CHANNEL1)
+ #define I2Cx_TEXT "I2C1"
+ #define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */
+ #define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */
+#elif defined(I2C_CHANNEL2)
+ #define I2Cx_TEXT "I2C2"
+ #define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */
+ #define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */
+#elif defined(I2C_CHANNEL3)
+ #define I2Cx_TEXT "I2C3"
+ #define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */
+ #define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */
+#elif defined(I2C_CHANNEL4)
+ #define I2Cx_TEXT "I2C4"
+ #define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */
+ #define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */
+#else
+ #error "target channel is non-select."
+#endif
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief I2C internal information structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t bus_free; /*!< Bus free information. */
+ uint8_t start; /*!< Start condition information. */
+ uint32_t irqn; /*!< IRQ number table pointer. */
+ struct
+ {
+ uint32_t address; /*!< Slave address. */
+ uint32_t stop; /*!< Stop control */
+ uint32_t event; /*!< I2C Event information. */
+ uint32_t state; /*!< Transfer State. */
+ } asynch;
+} i2c_internal_info_t;
+
+/*----------------------------------*/
+/**
+ * @brief I2C buffer structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_buffer; /*!< Buffer address. */
+ uint32_t length; /*!< Buffer length. */
+ uint32_t pos; /*!< Buffer pointer. */
+} i2c_buffer_t;
+
+/*----------------------------------*/
+/**
+ * @brief I2C handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ I2C_t i2c; /*!< I2C class structure. */
+ i2c_internal_info_t info; /*!< Internal Information. */
+ i2c_buffer_t tx_buff; /*!< Tx buffer structure. */
+ i2c_buffer_t rx_buff; /*!< Rx buffer structure. */
+} _i2c_t;
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_functions
+ * @{
+ */
+TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl);
+TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz);
+void i2c_reset_t(_i2c_t *p_obj);
+TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj);
+TXZ_Result i2c_start_t(_i2c_t *p_obj);
+TXZ_Result i2c_stop_t(_i2c_t *p_obj);
+int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
+int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
+int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last);
+int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data);
+uint8_t i2c_active_t(_i2c_t *p_obj);
+TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop);
+uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj);
+void i2c_abort_asynch_t(_i2c_t *p_obj);
+
+/* For slave */
+void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave);
+int32_t i2c_slave_receive_t(_i2c_t *p_obj);
+int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
+int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
+void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address);
+TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length);
+uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj);
+void i2c_slave_abort_asynch_t(_i2c_t *p_obj);
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group UTILITIES */
+
+/**
+ * @}
+ */ /* End of group Example */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __BSP_I2C_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_sample_def.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,30 @@ +/** + ******************************************************************************* + * @file txz_sample_def.h + * @brief This file includes header files for sample application. + * @version V1.0.0.3 + * $Date:: 2017-10-26 13:33:43 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_SAMPLE_DEF_H +#define __TXZ_SAMPLE_DEF_H + +#include "txz_driver_def.h" +#include "txz_hal.h" +#if defined(TMPM4G9) + #include "txz_cg.h" + #include "txz_gpio.h" +#else + #include "txz_cg.h" + #include "txz_gpio.h" + #include "txz_dma.h" +#endif +#include "txz_uart.h" +#include "txz_t32a.h" +#endif /* __TXZ_SAMPLE_DEF_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_t32a.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1024 @@
+/**
+ *******************************************************************************
+ * @file txz_t32a.h
+ * @brief This file provides all the functions prototypes for T32A driver.
+ * @version V1.0.0.7
+ * $Date:: 2017-11-30 17:34:52 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __T32A_H
+#define __T32A_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup T32A T32A
+ * @brief T32A Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Exported_define T32A Exported Define
+ * @{
+ */
+
+/**
+ * @defgroup T32A_Result Result
+ * @brief T32A Result Macro Definition.
+ * @{
+ */
+#define T32A_RESULT_SUCCESS (0) /*!< Success */
+#define T32A_RESULT_FAILURE (-1) /*!< Failure */
+#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */
+/**
+ * @}
+ */ /* End of group T32A_Result */
+
+/**
+ * @defgroup T32A_NullPointer Null Pointer
+ * @brief Null Pointer.
+ * @{
+ */
+#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */
+/**
+ * @}
+ */ /* End of group T32A_NullPointer */
+
+ /**
+ * @defgroup T32A_HALT T32A Debug HALT Control
+ * @brief Debug HALT Control Run/Stop HALT Macro Definition.
+ * @{
+ */
+#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */
+#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */
+/**
+ * @}
+ */ /* End of group T32A_HALT */
+
+ /**
+ * @defgroup T32A_MODE32 T32A 16bit/32bit MODE
+ * @brief T32A 16bit/32bit MODE MODE32 Macro Definition.
+ * @{
+ */
+#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */
+#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */
+/**
+ * @}
+ */ /* End of group T32A_MODE32 */
+
+ /**
+ * @defgroup T32A_RUNFLGx T32A RUNFLG Control
+ * @brief Run/Stop RUNFLGx Macro Definition.
+ * @{
+ */
+#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */
+#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */
+/**
+ * @}
+ */ /* End of group T32A_RUNFLGx */
+
+/**
+ * @defgroup T32A_SFTSTPx T32A SW STOP Control
+ * @brief T32A SW STOPx SFTSTPx Macro Definition.
+ * @{
+ */
+#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */
+#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */
+/**
+ * @}
+ */ /* End of group T32A_SFTSTPx */
+
+/**
+ * @defgroup T32A_SFTSTAx T32A SW START Control
+ * @brief T32A SW STARTx SFTSTAx Macro Definition.
+ * @{
+ */
+#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */
+#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */
+/**
+ * @}
+ */ /* End of group T32A_SFTSTAx */
+
+/**
+ * @defgroup T32A_RUNx T32A RUN Disable/Enable Control
+ * @brief RUN Disable/Enable RUNx Macro Definition.
+ * @{
+ */
+#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */
+/**
+ * @}
+ */ /* End of group T32A_RUNx */
+
+
+/**
+ * @defgroup T32A_PRSCLx T32A PRESCALER Control
+ * @brief PRESCALER Control PRSCLx Macro Definition.
+ * @{
+ */
+#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */
+#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */
+#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */
+#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */
+#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */
+#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */
+#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */
+#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */
+/**
+ * @}
+ */ /* End of group T32A_PRSCLx */
+
+/**
+ * @defgroup T32A_CLKx T32A COLCK Control
+ * @brief CLOCK Control CLKA Macro Definition.
+ * @{
+ */
+#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */
+#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */
+#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */
+#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */
+#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */
+#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */
+/**
+ * @}
+ */ /* End of group T32A_CLKx */
+
+/**
+ * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control
+ * @brief Double Buffer Disable/Enable WBFx Macro Definition.
+ * @{
+ */
+#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */
+/**
+ * @}
+ */ /* End of group T32A_WBFx */
+
+ /**
+ * @defgroup T32A_UPDNx T32A Counter Up/Down Control
+ * @brief Counter Up/Down Control UPDNx Macro Definition.
+ * @{
+ */
+#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */
+#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */
+#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */
+#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */
+/**
+ * @}
+ */ /* End of group T32A_UPDNx */
+
+ /**
+ * @defgroup T32A_RELDx T32A Counter Reload Control
+ * @brief Counter Reload Control RELDx Macro Definition.
+ * @{
+ */
+#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */
+#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */
+#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */
+#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */
+#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */
+#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */
+#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */
+#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */
+/**
+ * @}
+ */ /* End of group T32A_RELDx */
+
+ /**
+ * @defgroup T32A_STOPx T32A Counter Stop Control
+ * @brief Counter Stop Control STOPx Macro Definition.
+ * @{
+ */
+#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */
+#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */
+#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */
+#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */
+#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */
+#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */
+#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */
+#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */
+/**
+ * @}
+ */ /* End of group T32A_STOPx */
+
+
+ /**
+ * @defgroup T32A_STARTx T32A Counter Start Control
+ * @brief Counter Start Control STARTx Macro Definition.
+ * @{
+ */
+#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */
+#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */
+#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */
+#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */
+#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */
+#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */
+#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */
+#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */
+/**
+ * @}
+ */ /* End of group T32A_STARTx */
+
+/**
+ * @defgroup T32A_OCRx T32AxOUTA Control
+ * @brief T32AxOUTA Control OCRx Macro Definition.
+ * @{
+ */
+#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothig */
+#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */
+#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */
+#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */
+/**
+ * @}
+ */ /* End of group T32A_OCRx */
+
+/**
+ * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1
+ * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition.
+ * @{
+ */
+#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */
+#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */
+#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */
+#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */
+/**
+ * @}
+ */ /* End of group T32A_OCRCAPx1 */
+
+/**
+ * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value
+ * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition.
+ * @{
+ */
+#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */
+#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */
+#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */
+#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */
+/**
+ * @}
+ */ /* End of group T32A_OCRCAPx0 */
+
+/**
+ * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value
+ * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition.
+ * @{
+ */
+#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */
+#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */
+#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */
+#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */
+/**
+ * @}
+ */ /* End of group T32A_OCRCMPx1 */
+
+/**
+ * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value
+ * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition.
+ * @{
+ */
+#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */
+#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */
+#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */
+#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */
+/**
+ * @}
+ */ /* End of group T32A_OCRCMPx0 */
+
+/**
+ * @defgroup T32A_RGx0 T32A Timer Register x0 MASK
+ * @brief T32A Timer Register A0 MASK RGx0 Macro Definition.
+ * @{
+ */
+#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_RGx0 */
+
+/**
+ * @defgroup T32A_RGx1 T32A Timer Register x1 MASK
+ * @brief T32A Timer Register A1 MASK RGx1 Macro Definition.
+ * @{
+ */
+#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_RGx0 */
+
+/**
+ * @defgroup T32A_TMRx T32A Counter Capture Register x MASK
+ * @brief T32A Counter Capture Register x MASK TMRx Macro Definition.
+ * @{
+ */
+#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_TMRx */
+
+/**
+ * @defgroup T32A_RELD T32A Counter Reload Register x MASK
+ * @brief T32A Counter Reload Register x MASK TMRx Macro Definition.
+ * @{
+ */
+#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_RELD */
+
+ /**
+ * @defgroup T32A_CAPMx1 T32A Capture Control Register x1
+ * @brief Capture Control Register A1 CAPMx1 Macro Definition.
+ * @{
+ */
+#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */
+#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */
+#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */
+#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */
+#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */
+#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */
+#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */
+#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */
+/**
+ * @}
+ */ /* End of group T32A_CAPMx1 */
+
+ /**
+ * @defgroup T32A_CAPMx0 T32A Capture Control Register x0
+ * @brief Capture Control Register x0 CAPMx0 Macro Definition.
+ * @{
+ */
+#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */
+#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */
+#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */
+#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */
+#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */
+#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */
+#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */
+#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */
+/**
+ * @}
+ */ /* End of group T32A_CAPMx0 */
+
+/**
+ * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK
+ * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition.
+ * @{
+ */
+#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_CAPx0 */
+
+/**
+ * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK
+ * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition.
+ * @{
+ */
+#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */
+#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */
+/**
+ * @}
+ */ /* End of group T32A_CAPx1 */
+
+/**
+ * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK
+ * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition.
+ * @{
+ */
+#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000)
+#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010)
+/**
+ * @}
+ */ /* End of group T32A_IMSTERR */
+
+/**
+ * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK
+ * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition.
+ * @{
+ */
+#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */
+#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */
+/**
+ * @}
+ */ /* End of group T32A_IMUFx */
+
+/**
+ * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK
+ * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition.
+ * @{
+ */
+#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */
+#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */
+/**
+ * @}
+ */ /* End of group T32A_IMOFx */
+
+/**
+ * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK
+ * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition.
+ * @{
+ */
+#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */
+#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */
+/**
+ * @}
+ */ /* End of group T32A_IMx1 */
+
+/**
+ * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK
+ * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition.
+ * @{
+ */
+#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */
+#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */
+/**
+ * @}
+ */ /* End of group T32A_IMx0 */
+
+/**
+ * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status
+ * @brief T32A Statuserr Flag Status INTSTERR Macro Definition.
+ * @{
+ */
+#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010)
+#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010)
+/**
+ * @}
+ */ /* End of group T32A_INTSTERR */
+
+/**
+ * @defgroup T32A_INTUFA T32A Underflow Flag Status
+ * @brief T32A Underflow Flag Status INTUFA Macro Definition.
+ * @{
+ */
+#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */
+#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */
+/**
+ * @}
+ */ /* End of group T32A_INTUFA */
+
+/**
+ * @defgroup T32A_INTOFA T32A Overflow Flag Status
+ * @brief T32A Overflow Flag Status INTOFA Macro Definition.
+ * @{
+ */
+#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */
+#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */
+/**
+ * @}
+ */ /* End of group T32A_INTOFA */
+
+/**
+ * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status
+ * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition.
+ * @{
+ */
+#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */
+#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */
+/**
+ * @}
+ */ /* End of group T32A_INTA1 */
+
+/**
+ * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status
+ * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition.
+ * @{
+ */
+#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */
+#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */
+/**
+ * @}
+ */ /* End of group T32A_INTA0 */
+
+/**
+ * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control
+ * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition.
+ * @{
+ */
+#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */
+#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */
+/**
+ * @}
+ */ /* End of group T32A_DMAENx2 */
+
+/**
+ * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control
+ * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition.
+ * @{
+ */
+#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */
+#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */
+/**
+ * @}
+ */ /* End of group T32A_DMAENx1 */
+
+/**
+ * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control
+ * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition.
+ * @{
+ */
+#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */
+#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */
+/**
+ * @}
+ */ /* End of group T32A_DMAENx0 */
+
+ /**
+ * @defgroup T32A_PDN T32A Pulse Mode Count Down Control
+ * @brief Pulse Mode Count Down Control PDN Macro Definition.
+ * @{
+ */
+#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */
+#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */
+#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */
+#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */
+#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */
+#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */
+#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */
+#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */
+/**
+ * @}
+ */ /* End of group T32A_PDN */
+
+ /**
+ * @defgroup T32A_PUP T32A Pulse Mode Count UP Control
+ * @brief Pulse Mode Count UP Control PUP Macro Definition.
+ * @{
+ */
+#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */
+#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */
+#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */
+#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */
+#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */
+#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */
+#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */
+#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */
+/**
+ * @}
+ */ /* End of group T32A_PUP */
+
+ /**
+ * @defgroup T32A_NF T32A Noise Filter control
+ * @brief Noise Filter control NF Macro Definition.
+ * @{
+ */
+#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */
+#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/ÓT0 */
+#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/ÓT0 */
+#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/ÓT0 */
+/**
+ * @}
+ */ /* End of group T32A_NF */
+
+/**
+ * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control
+ * @brief Phase 2 Pulse Direction control PDIR Macro Definition.
+ * @{
+ */
+#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */
+#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */
+/**
+ * @}
+ */ /* End of group T32A_PDIR */
+
+/**
+ * @defgroup T32A_PMODE T32A Pulse Count Mode control
+ * @brief Pulse Count Mode control PDIR Macro Definition.
+ * @{
+ */
+#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */
+#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */
+/**
+ * @}
+ */ /* End of group T32A_PMODE */
+
+/**
+ * @}
+ */ /* End of group T32A_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/** @defgroup T32A_Exported_Typedef T32A Exported Typedef
+ * @{
+ */
+
+/**
+ * @enum t32_type_t
+ * @brief Use of Timer register.
+ */
+typedef enum
+{
+ T32A_TIMERA = 0, /*!< 0: Timer A */
+ T32A_TIMERB, /*!< 1: Timer B */
+ T32A_TIMERC, /*!< 2: Timer C */
+ T32A_TIMERMAX,
+}t32_type_t;
+
+/**
+ * @enum t32_regnum_t
+ * @brief Use of Timer register number.
+ */
+typedef enum
+{
+ T32A_REG0 = 0, /*!< 0: Register 0 */
+ T32A_REG1, /*!< 1: Register 1 */
+ T32A_RELOAD, /*!< 2: Reload Register */
+}t32_regnum_t;
+/**
+ * @enum t32_mode_t
+ * @brief Use of Timer register.
+ */
+typedef enum
+{
+ T32A_MATCH = 0, /*!< 0: compare match detection 0 */
+ T32A_OVERFLOW, /*!< 1: Overfloe detection */
+ T32A_UNDERFLOW, /*!< 2: Underflow detection */
+ T32A_CAPTURE0, /*!< 3: Capture 0 */
+ T32A_CAPTURE1, /*!< 4: Capture 0 */
+}t32_mode_t;
+
+/**
+ * @enum t32_triger_t
+ * @brief Use of Timer register.
+ */
+typedef enum
+{
+ T32A_INTRG = 0, /*!< 0: internal triger */
+ T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */
+ T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */
+ T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */
+ T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */
+}t32_triger_t;
+/**
+ * @}
+ */ /* End of group T32A_Exported_Typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup T32A_Exported_Typedef T32A Exported Typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @struct t32a_mode_t
+ * @brief TimerA Mode Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t halt; /*!< T32A Debug HALT Control.
+ : Use @ref T32A_HALT */
+ uint32_t mode; /*!< T32A 16bit/32bit MODE .
+ : Use @ref T32A_MODE32 */
+} t32a_mode_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_runx_t
+ * @brief TimerA Run Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t runflg; /*!< TimerA Run Control Flag.
+ : Use @ref T32A_RUNFLGx */
+ uint32_t sftstp; /*!< SW Counter STOP Control.
+ : Use @ref T32A_SFTSTPx */
+ uint32_t sftsta; /*!< SW Counter START Control.
+ : Use @ref T32A_SFTSTAx */
+ uint32_t run; /*!< TimerA Run Control.
+ : Use @ref T32A_RUNx */
+} t32a_runx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_crx_t
+ * @brief Counter Register Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t prscl; /*!< T32A PRESCALER Control.
+ : Use @ref T32A_PRSCLx */
+ uint32_t clk; /*!< T32A COLCK Control.
+ : Use @ref T32A_CLKx */
+ uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control.
+ : Use @ref T32A_WBFx */
+ uint32_t updn; /*!< T32A Counter Up/Down Control.
+ : Use @ref T32A_UPDNx */
+ uint32_t reld; /*!< T32A Counter Reload Control.
+ : Use @ref T32A_RELDx */
+ uint32_t stop; /*!< T32A Counter Stop Control.
+ : Use @ref T32A_STOPx */
+ uint32_t start; /*!< T32A Counter Start Controlc.
+ : Use @ref T32A_STARTx */
+} t32a_crx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_outcrx0_t
+ * @brief TimerA Output Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t ocr; /*!< T32AxOUTA Control.
+ : Use @ref T32A_OCRx */
+} t32a_outcrx0_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_outcrx1_t
+ * @brief T32AxOUTA Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1.
+ : Use @ref T32A_OCRCAPx1 */
+ uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1.
+ : Use @ref T32A_OCRCAPx0 */
+ uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value
+ : Use @ref T32A_OCRCMPx1 */
+ uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value
+ : Use @ref T32A_OCRCMPx0 */
+} t32a_outcrx1_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_capcrx_t
+ * @brief Capture Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t capmx1; /*!< T32A Capture Control Register x1.
+ : Use @ref T32A_CAPMx1 */
+ uint32_t capmx0; /*!< T32A Capture Control Register A0.
+ : Use @ref T32A_CAPMx0 */
+} t32a_capcrx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_rgx0_t
+ * @brief T32A Timer Register x0 Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t rgx0; /*!< T32A Timer Register x0.
+ : Use @ref T32A_RGx0 */
+} t32a_rgx0_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_rgx1_t
+ * @brief T32A Timer Register x1 Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t rgx1; /*!< T32A Timer Register x1.
+ : Use @ref T32A_RGx1 */
+} t32a_rgx1_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_tmrx_t
+ * @brief T32A Counter Capture Register A Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t tmrx; /*!< T32A Counter Capture Register x.
+ : Use @ref T32A_TMRx */
+} t32a_tmrx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_reldx_t
+ * @brief T32A Counter Reload Register Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t reld; /*!< T32A Counter Reload Register.
+ : Use @ref T32A_RELD */
+} t32a_reldx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_capx0_t
+ * @brief T32A Capture Register x0 Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t capx0; /*!< T32A Capture Register x0.
+ : Use @ref T32A_CAPx0 */
+} t32a_capx0_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_capx1_t
+ * @brief T32A Capture Register x0 Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t capx1; /*!< T32A Capture Register x1.
+ : Use @ref T32A_CAPx1 */
+} t32a_capx1_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_imx_t
+ * @brief Interrupt mask register Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C).
+ : Use @ref T32A_IMSTERR */
+ uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK.
+ : Use @ref T32A_IMUFx */
+ uint32_t imof; /*!< T32A Underflow Interrupt Request MASK.
+ : Use @ref T32A_IMOFx */
+ uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK.
+ : Use @ref T32A_IMx1 */
+ uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK.
+ : Use @ref T32A_IMx0 */
+} t32a_imx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_stx_t
+ * @brief Status register structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C).
+ : Use @ref T32A_INTSTERR */
+ uint32_t intuf; /*!< T32A Underflow Flag Status.
+ : Use @ref T32A_INTUFA */
+ uint32_t intof; /*!< T32A Overflow Flag Status.
+ : Use @ref T32A_INTOFA */
+ uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status.
+ : Use @ref T32A_INTA1 */
+ uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status.
+ : Use @ref T32A_INTA0 */
+} t32a_stx_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_dma_req_t
+ * @brief DMA Request register setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control.
+ : Use @ref T32A_DMAENx2 */
+ uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control.
+ : Use @ref T32A_DMAENx1 */
+ uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control.
+ : Use @ref T32A_DMAENx0 */
+} t32a_dma_req_t;
+
+/*----------------------------------*/
+/**
+ * @struct t32a_pulse_cr_t
+ * @brief Pulse Count Control register setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t pdn; /*!< Pulse Mode Count Down Control.
+ : Use @ref T32A_PDN */
+ uint32_t pup; /*!< Pulse Mode Count UP Control.
+ : Use @ref T32A_PUP */
+ uint32_t nf; /*!< Noise Filter control.
+ : Use @ref T32A_NF */
+ uint32_t pdir; /*!< Phase 2 Pulse Direction control.
+ : Use @ref T32A_PDIR */
+ uint32_t pmode; /*!< Pulse Count Mode control.
+ : Use @ref T32A_PMODE */
+} t32a_pulse_cr_t;
+
+/**
+ * @struct t32a_initial_setting_t
+ * @brief Initial Timer setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t id; /*!< ID: User value. */
+ t32a_runx_t runx; /*!< Timer Run Control Setting */
+ t32a_crx_t crx; /*!< Counter Register Control Setting */
+ t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */
+ t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */
+ t32a_capcrx_t capcrx; /*!< Capture Control Setting */
+ t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */
+ t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */
+ t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */
+ t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */
+ t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */
+ t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */
+ t32a_imx_t imx; /*!< Interrupt mask register Setting */
+ t32a_dma_req_t dma_req; /*!< DMA Request register Setting */
+ t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */
+ void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */
+ void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */
+ void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */
+} t32a_initial_setting_t;
+
+/**
+ * @struct t32a_initial_mode_t
+ * @brief Initial Mode setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ t32a_mode_t mode; /*!< Timer Mode Setting */
+} t32a_initial_mode_t;
+
+
+/*----------------------------------*/
+/**
+ * @brief T32A handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct t32a_handle
+{
+ TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */
+ t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */
+ t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */
+}t32a_t;
+
+/** @} */
+/* End of group T32A_Exported_Types */
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Exported_functions T32A Exported Functions
+ * @{
+ */
+TXZ_Result t32a_mode_init(t32a_t *p_obj);
+TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type);
+TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value);
+TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val);
+TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type);
+void t32a_timer_IRQHandler(t32a_t *p_obj);
+void t32a_timer_cap0_IRQHandler(t32a_t *p_obj);
+void t32a_timer_cap1_IRQHandler(t32a_t *p_obj);
+TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl);
+/**
+ * @}
+ */ /* End of group T32A_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group T32A */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __T32A_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_tspi.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1322 @@
+/**
+ *******************************************************************************
+ * @file txz_tspi.h
+ * @brief This file provides all the functions prototypes for TSPI driver.
+ * @version V1.0.0.3
+ * $Date:: 2018-02-28 13:37:55 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __TSPI_H
+#define __TSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup TSPI TSPI
+ * @brief TSPI Driver.
+ * @{
+ */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Exported_define TSPI Exported Define
+ * @{
+ */
+/**
+ * @defgroup TSPI_NullPointer Null Pointer
+ * @brief Null Pointer.
+ * @{
+ */
+#define TSPI_NULL ((void *)0)
+/**
+ * @}
+ */ /* End of group TSPI_NullPointer */
+
+/**
+ * @defgroup TSPI_ParameterResult Parameter Check Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of group TSPI_ParameterResult */
+
+
+/**
+ * @defgroup TSPI_Result Result
+ * @brief TSPI Result Macro Definition.
+ * @{
+ */
+#define TSPI_RESULT_SUCCESS (0) /*!< Success */
+#define TSPI_RESULT_FAILURE (-1) /*!< Failure */
+/**
+ * @}
+ */ /* End of group TSPI_Result */
+
+/**
+ * @defgroup TSPI_SW_Reset SW Reset
+ * @brief Software Rest Macro Definition.
+ * @{
+ */
+#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */
+#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */
+/**
+ * @}
+ */ /* End of group TSPI_SW_Reset */
+
+
+/**
+ * @defgroup TSPI_Enable TSPI Enable/Disable Control
+ * @brief Enable/Disable TSPIE Macro Definition.
+ * @{
+ */
+#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_Enable */
+
+/**
+ * @defgroup TSPI_Triger_Control Triger Control
+ * @brief Enable/Disable TRGEN Macro Definition.
+ * @{
+ */
+#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_Transmission_Control */
+
+/**
+ * @defgroup TSPI_Transmission_Control Transmission Control
+ * @brief Enable/Disable TRXE Macro Definition.
+ * @{
+ */
+#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */
+#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/
+/**
+ * @}
+ */ /* End of group TSPI_Transmission_Control */
+
+/**
+ * @defgroup TSPI_Transmission_Mode Transmission Mode
+ * @brief TSPIIMS Mode Macro Definisiton.
+ * @{
+ */
+#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */
+#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */
+/**
+ * @}
+ */ /* End of group TSPI_Transmission_Mode */
+
+
+/**
+ * @defgroup TSPI_Operation_Select Operation Select
+ * @brief Master/Slave MSTR Operation Macro Definisiton.
+ * @{
+ */
+#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /*!< MASTER MODE */
+#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */
+/**
+ * @}
+ */ /* End of group TSPI_Operation_Select */
+
+
+/**
+ * @defgroup TSPI_Transfer_Mode Transfer Mode
+ * @brief Transfer Mode TMMD Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */
+#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */
+#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */
+#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */
+/**
+ * @}
+ */ /* End of group TSPI_Transfer_Mode */
+
+
+/**
+ * @defgroup TSPI_CSSEL_Select CSSEL Select
+ * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton.
+ * @{
+ */
+#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */
+#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */
+#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */
+#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */
+/**
+ * @}
+ */ /* End of group TSPI_CSSEL_Select */
+
+/**
+ * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range
+ * @brief Transfer Frame Range Macro Definisiton.
+ * @{
+ */
+#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /*!< Single Transfer Frame :0 */
+#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */
+/**
+ * @}
+ */ /* End of group TSPI_Transfer_Frame_Range */
+/**
+ * @defgroup TSPI_IDLE_Output_value IDLE Output Value
+ * @brief IDLE time Output Value TIDLE Macro Definisiton.
+ * @{
+ */
+#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */
+#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */
+#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */
+#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */
+/**
+ * @}
+ */ /* End of group TSPI_IDLE_Output_value */
+
+/**
+ * @defgroup TSPI_RXDLY_value RXDLY Value
+ * @brief IDLE time Output Value TIDLE Macro Definisiton.
+ * @{
+ */
+#define TSPI_RXDLY_SET ((uint32_t)0x00010000) /*!< RXDLY SET */
+/**
+ * @}
+ */ /* End of group TSPI_RXDLY_value*/
+
+
+ /**
+ * @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value
+ * @brief In case of Under Run Output Value TXDEMP Macro Definisiton.
+ * @{
+ */
+#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */
+#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */
+/**
+ * @}
+ */ /* End of group TSPI_Underrun_Output_value */
+
+
+/**
+ * @defgroup TSPI_TxFillLevel Tx Fill Level
+ * @brief Transmit Fill Level Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */
+#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */
+#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */
+#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */
+#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */
+#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */
+#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */
+#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */
+#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */
+/*!
+ * @}
+ */ /* End of group TSPI_TxFillLevel */
+
+
+/**
+ * @defgroup TSPI_RxFillLevel Rx Fill Level
+ * @brief Receive Fill Level Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */
+#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */
+#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */
+#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */
+#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */
+#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */
+#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */
+#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */
+#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */
+/**
+ * @}
+ */ /* End of group TSPI_RxFillLevel */
+
+
+/**
+ * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt
+ * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_TxFIFOInterrupt */
+
+
+/**
+ * @defgroup TSPI_TxInterrupt Tx Interrpt
+ * @brief Enable/Disable Transmit Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_TxInterrupt */
+
+
+/**
+ * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt
+ * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_RxFIFOInterrupt */
+
+
+/**
+ * @defgroup TSPI_RxInterrupt Rx Interrpt
+ * @brief Enable/Disable Receive Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_RxInterrupt */
+
+
+/**
+ * @defgroup TSPI_ErrorInterrupt Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_ErrorInterrupt */
+
+
+/**
+ * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt
+ * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */
+#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_TxDMAInterrupt */
+
+
+/**
+ * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt
+ * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */
+#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_RxDMAInterrupt */
+
+
+/**
+ * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear
+ * @brief Tx Buffer Clear Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */
+/**
+ * @}
+ */ /* End of group TSPI_Tx_Buffer_Clear */
+
+
+/**
+ * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear
+ * @brief Rx Buffer Clear Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */
+/**
+ * @}
+ */ /* End of group TSPI_Rx_Buffer_Clear */
+
+
+/**
+ * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock
+ * @brief Baudrate Input Clock Macro Definisiton.
+ * @{
+ */
+#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */
+#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */
+#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */
+#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */
+#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */
+#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */
+#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */
+#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */
+#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */
+#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */
+/**
+ * @}
+ */ /* End of group TSPI_Baudrate_Clock */
+
+
+/**
+ * @defgroup TSPI_Baudrate_Divider Baudrate Divider
+ * @brief Baudrate IDivider Macro Definisiton.
+ * @{
+ */
+#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */
+#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */
+#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */
+#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */
+#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */
+#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */
+#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */
+#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */
+#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */
+#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */
+#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */
+#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */
+#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */
+#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */
+#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */
+#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */
+/**
+ * @}
+ */ /* End of group TSPI_Baudrate_Divider */
+
+
+/**
+ * @defgroup TSPI_DataDirection Data Direction
+ * @brief Data Direction Macro Definisiton.
+ * @{
+ */
+#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */
+#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */
+/*!
+ * @}
+ */ /* End of group TSPI_DataDirection */
+
+
+/**
+ * @defgroup TSPI_DataLength Data Length
+ * @brief Data Length Macro Definisiton.
+ * @{
+ */
+#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */
+#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */
+#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */
+#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */
+#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */
+#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */
+#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */
+#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */
+#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */
+#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */
+#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */
+#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */
+#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */
+#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */
+#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */
+#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */
+#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */
+#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */
+#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */
+#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */
+#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */
+#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */
+#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */
+#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */
+#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */
+#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */
+/**
+ * @}
+ */ /* End of group TSPI_DataLength */
+
+
+/**
+ * @defgroup TSPI_Frame_Interval_Time Frame Interval time
+ * @brief Frame Interval time Macro Definisiton.
+ * @{
+ */
+#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */
+#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */
+#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */
+/**
+ * @}
+ */ /* End of group TSPI_Frame_Interval_Time */
+
+
+/**
+ * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity
+ * @brief TSPIxCS3 Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */
+#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */
+/**
+ * @}
+ */ /* End of group TSPI_TSPIxCS3_Polarity */
+
+
+/**
+ * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity
+ * @brief TSPIxCS2 Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */
+#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */
+/**
+ * @}
+ */ /* End of group TSPI_TSPIxCS2_Polarity */
+
+
+/**
+ * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity
+ * @brief TSPIxCS1 Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */
+#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */
+/**
+ * @}
+ */ /* End of group TSPI_TSPIxCS1_Polarity */
+
+
+/**
+ * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity
+ * @brief TSPIxCS0 Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */
+#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */
+/**
+ * @}
+ */ /* End of group TSPI_TSPIxCS0_Polarity */
+
+
+/**
+ * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity
+ * @brief Serial Clock Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */
+#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */
+/**
+ * @}
+ */ /* End of group Serial Clock Polarity */
+
+
+/**
+ * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity
+ * @brief Serial Clock IDLE Polarity Macro Definisiton.
+ * @{
+ */
+#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */
+#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */
+/**
+ * @}
+ */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */
+
+
+/**
+ * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time
+ * @brief Minimum IDLE Time Macro Definisiton.
+ * @{
+ */
+#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */
+#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */
+/**
+ * @}
+ */ /* End of group TSPI_Minimum_IDLE_Time */
+
+
+/**
+ * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay
+ * @brief Serial Clock Delay Macro Definisiton.
+ * @{
+ */
+#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */
+#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */
+/**
+ * @}
+ */ /* End of group TSPI_Serial_Clock_Delay */
+
+
+/**
+ * @defgroup TSPI_Negate_Delay Negate Delay
+ * @brief Negate Delay Macro Definisiton.
+ * @{
+ */
+#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */
+#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */
+#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */
+#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */
+#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */
+#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */
+#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */
+#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */
+#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */
+#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */
+#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */
+#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */
+#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */
+#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */
+#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */
+#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */
+/**
+ * @}
+ */ /* End of group TSPI_Negate_Delay */
+
+
+/**
+ * @defgroup TSPI_ParityEnable Parity Enable
+ * @brief Enable/Disable Parity Macro Definisiton.
+ * @{
+ */
+#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */
+/**
+ * @}
+ */ /* End of group TSPI_ParityEnable */
+
+
+/**
+ * @defgroup TSPI_ParityBit Parity Bit
+ * @brief Parity Bit Macro Definisiton.
+ * @{
+ */
+#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
+#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */
+/**
+ * @}
+ */ /* End of group TSPI_ParityBit */
+
+
+/**
+ * @defgroup TSPI_Status_Setting_flag Status Setting Flag
+ * @brief Enable/Disable Status Setting Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */
+#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */
+/**
+ * @}
+ */ /* End of group TSPI_Status_Setting_flag */
+
+
+/**
+ * @defgroup TSPI_TxState Transmitting State Flag
+ * @brief Transmitting State Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */
+#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */
+#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */
+/**
+ * @}
+ */ /* End of group TSPI_TxState */
+
+
+/**
+ * @defgroup TSPI_TxDone Transmitting Complete Flag
+ * @brief Transmitting Complete Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */
+#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */
+#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */
+/**
+ * @}
+ */ /* End of group TSPI_TxDone */
+
+
+/**
+ * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag
+ * @brief Transmitting FIFO Interrpt Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */
+#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */
+#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */
+/**
+ * @}
+ */ /* End of group TSPI_TxFIFOInterruptFlag */
+
+/**
+ * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag
+ * @brief Transmitting FIFO Empty Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */
+#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */
+/**
+ * @}
+ */ /* End of group TSPI_TxFIFOEmptyFlag */
+
+/**
+ * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level
+ * @brief Current Transmitting FIFO Level Macro Definisiton.
+ * @{
+ */
+#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */
+#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */
+#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */
+#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */
+#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */
+#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */
+#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */
+#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */
+#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */
+/**
+ * @}
+ */ /* End of group TSPI_TxReachFillLevel */
+
+
+/**
+ * @defgroup TSPI_RxState Receive State Flag
+ * @brief Receive State Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */
+#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */
+#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */
+/**
+ * @}
+ */ /* End of group TSPI_RxState */
+
+
+/**
+ * @defgroup TSPI_RxDone Receive Complete Flag
+ * @brief Receive Complete Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */
+#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */
+#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */
+/**
+ * @}
+ */ /* End of group TSPI_RxDone */
+
+
+/**
+ * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag
+ * @brief Rx FIFO Interrpt Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */
+#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */
+#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */
+/**
+ * @}
+ */ /* End of group TSPI_RxFIFOInterruptFlag */
+
+/**
+ * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag
+ * @brief Receiving FIFO Full Flag Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */
+#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */
+/**
+ * @}
+ */ /* End of group TSPI_RxFIFOFullFlag */
+
+
+/**
+ * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level
+ * @brief Current Receive FIFO Level Macro Definisiton.
+ * @{
+ */
+#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */
+#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */
+#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */
+#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */
+#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */
+#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */
+#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */
+#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */
+#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */
+/**
+ * @}
+ */ /* End of group TSPI_RxReachFillLevel */
+
+
+/**
+ * @defgroup TSPI_TRGErr Triger Error
+ * @brief Triger Error Macro Definisiton.
+ * @{
+ */
+#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */
+#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */
+/**
+ * @}
+ */ /* End of group TSPI_TRGErr */
+
+/**
+ * @defgroup TSPI_UnderrunErr Underrun Error
+ * @brief Underrun Error Macro Definisiton.
+ * @{
+ */
+#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */
+#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */
+/**
+ * @}
+ */ /* End of group TSPI_UnderrunErr */
+
+/**
+ * @defgroup TSPI_OverrunErr Overrun Error
+ * @brief Overrun Error Macro Definisiton.
+ * @{
+ */
+#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */
+#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */
+/**
+ * @}
+ */ /* End of group TSPI_OverrunErr */
+
+
+/**
+ * @defgroup TSPI_ParityErr Parity Error
+ * @brief Parity Error Macro Definisiton.
+ * @{
+ */
+#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */
+#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */
+/**
+ * @}
+ */ /* End of group TSPI_ParityErr */
+
+ /**
+ * @defgroup TSPI_Data_allign Data allign
+ * @brief Data allign Macro Definisiton.
+ * @{
+ */
+#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */
+#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */
+#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */
+/**
+ * @}
+ */ /* End of group TSPI_Data_allign */
+
+ /**
+ * @defgroup TSPI_FifoMax FIFO MAX
+ * @brief FIFO MAX LEVEL
+ * @{
+ */
+#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */
+/**
+ * @}
+ */ /* End of group TSPI_FifoMax */
+
+ /**
+ * @defgroup TSPI_ErrCode Error Code
+ * @brief Error Code Macro Definisiton.
+ * @{
+ */
+#define NOERROR ((uint32_t)0x00000000) /*!< no error */
+#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */
+#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */
+#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */
+#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */
+#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */
+#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */
+#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */
+#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */
+#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */
+#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */
+/**
+* @}
+ */ /* End of group TSPI_ErrCode */
+
+ /**
+ * @defgroup TSPI_Buffer_Size Receive Buffer size
+ * @brief Error Code Macro Definisiton.
+ * @{
+ */
+#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */
+/**
+* @}
+ */ /* End of group TSPI_Buffer_Size */
+/**
+ * @}
+ */ /* End of group TSPI_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef
+ * @{
+ */
+/* No define */
+/**
+ * @}
+ */ /* End of group TSPI_Exported_Typedef */
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @struct tspi_receive8_t
+ * @brief Receive event information structure definenition.
+ * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} tspi_receive8_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_receive16_t
+ * @brief Receive event information structure definenition.
+ * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint16_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} tspi_receive16_t;
+
+/**
+ * @struct tspi_receive32_t
+ * @brief Receive event information structure definenition.
+ * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} tspi_receive32_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_receive_t
+ * @brief Receive event information structure definenition.
+*/
+/*----------------------------------*/
+typedef union
+{
+ tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */
+ tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */
+ tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */
+} tspi_receive_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_transmit8_t
+ * @brief Transmit data information structure definenition.
+ * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to transmit data. */
+ uint32_t num; /*!< The number of transmit data. */
+} tspi_transmit8_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_transmit16_t
+ * @brief Transmit data information structure definenition.
+ * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint16_t *p_data; /*!< The buffer to transmit data. */
+ uint32_t num; /*!< The number of transmit data. */
+} tspi_transmit16_t;
+/*----------------------------------*/
+/**
+ * @struct tspi_transmit32_t
+ * @brief Transmit data information structure definenition.
+ * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t *p_data; /*!< The buffer to transmit data. */
+ uint32_t num; /*!< The number of transmit data. */
+} tspi_transmit32_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_transmit_t
+ * @brief Transmit data information structure definenition.
+*/
+/*----------------------------------*/
+typedef union
+{
+ tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */
+ tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */
+ tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */
+} tspi_transmit_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_control1_t
+ * @brief Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t trgen; /*!< TRGEN Transmission Triger Control.
+ : Use @ref TSPI_Triger_Control */
+ uint32_t trxe; /*!< TRXE Transmission Control.
+ : Use @ref TSPI_Transmission_Control */
+ uint32_t tspims; /*!< TSPI/SIO Transmission Mode.
+ : Use @ref TSPI_Transmission_Mode */
+ uint32_t mstr; /*!< Master/Slave Operation Select.
+ : Use @ref TSPI_Operation_Select */
+ uint32_t tmmd; /*!< Transfer Mode Select.
+ : Use @ref TSPI_Transfer_Mode */
+ uint32_t cssel; /*!< CSSEL Select.
+ : Use @ref TSPI_CSSEL_Select */
+ uint32_t fc; /*!< Transfer Frame Value.
+ : Range ( TSPI_TRANS_RANGE_SINGLE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */
+} tspi_control1_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_control2_t
+ * @brief Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t tidle; /*!< IDLE Output Value.
+ : Use @ref TSPI_IDLE_Output_value */
+ uint32_t txdemp; /*!< Under Run Occur Output Value.
+ : Use @ref TSPI_IDLE_Output_value */
+ uint32_t rxdly; /*!< Fsys Select.
+ : Use @ref TSPI_RXDLY_value */
+ uint32_t til; /*!< Transmit Fill Level.
+ : Use @ref TSPI_TxFillLevel */
+ uint32_t ril; /*!< Receive Fill Level.
+ : Use @ref TSPI_RxFillLevel */
+ uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt.
+ : Use @ref TSPI_TxFIFOInterrupt */
+ uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt.
+ : Use @ref TSPI_TxInterrupt */
+ uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt.
+ : Use @ref TSPI_RxFIFOInterrupt */
+ uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt.
+ : Use @ref TSPI_RxInterrupt */
+ uint32_t interr; /*!< Enable/Disable Error Interrupt.
+ : Use @ref TSPI_ErrorInterrupt */
+ uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt.
+ : Use @ref TSPI_TxDMAInterrupt */
+ uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt.
+ : Use @ref TSPI_RxDMAInterrupt */
+} tspi_control2_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_control3_t
+ * @brief Control Setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t tfempclr; /*!< Transmit Buffer Clear.
+ : Use @ref TSPI_Tx_Buffer_Clear */
+ uint32_t rffllclr; /*!< Receive Buffer Clear.
+ : Use @ref TSPI_Rx_Buffer_Clear */
+} tspi_control3_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_baudrate_t
+ * @brief Clock setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t brck; /*!< Baudrate Input Clock.
+ : Use @ref TSPI_Baudrate_Clock */
+ uint32_t brs; /*!< Baudrate Divider.
+ : Use @ref TSPI_Baudrate_Divider */
+} tspi_baudrate_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_fmtr0_t
+ * @brief Format control0.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t dir; /*!< Data Direction.
+ : Use @ref TSPI_DataDirection */
+ uint32_t fl; /*!< Data Length.
+ : Use @ref TSPI_DataLength */
+ uint32_t fint; /*!< Frame Interval time.
+ : Use @ref TSPI_Frame_Interval_Time */
+ uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive.
+ : Use @ref TSPI_TSPIxCS3_Polarity */
+ uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive.
+ : Use @ref TSPI_TSPIxCS2_Polarity */
+ uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive.
+ : Use @ref TSPI_TSPIxCS1_Polarity */
+ uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive.
+ : Use @ref TSPI_TSPIxCS0_Polarity */
+ uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge.
+ : Use @ref TSPI_Serial_Clock_Polarity */
+ uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low.
+ : Use @ref TSPI_Serial_Clock_IDLE_Polarity */
+ uint32_t csint; /*!< Minimum IDLE Time.
+ : Use @ref TSPI_Minimum_IDLE_Time */
+ uint32_t cssckdl; /*!< Serial Clock Delay.
+ : Use @ref TSPI_Serial_Clock_Delay */
+ uint32_t sckcsdl; /*!< Negate Delay.
+ : Use @ref TSPI_Negate_Delay */
+} tspi_fmtr0_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_fmtr1_t
+ * @brief Format control1.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t reserved; /*!< SIO Slave MOde.
+ : */
+ uint32_t vpe; /*!< Enable/Disable Parity Function.
+ : Use @ref TSPI_ParityEnable */
+ uint32_t vpm; /*!< Odd/Even Parity Bit.
+ : Use @ref TSPI_ParityBit */
+} tspi_fmtr1_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_status_t
+ * @brief Status register.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t tspisue; /*!< Enable/Disable Status Setting Flag.
+ : Use @ref TSPI_Status_Setting_flag */
+ uint32_t txrun; /*!< Stop/Active Tx Active Flag.
+ : Use @ref TSPI_TxState */
+ uint32_t txend; /*!< Tx Data Send Complete Flag.
+ : Use @ref TSPI_TxDone */
+ uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag.
+ : Use @ref TSPI_TxFIFOInterruptFlag */
+ uint32_t tfemp; /*!< Tx FIFO Empty Flag.
+ : Use @ref TSPI_TxFIFOEmptyFlag */
+ uint32_t tlvll; /*!< Tx Reach Fill Level
+ : Use @ref TSPI_TxReachFillLevel */
+ uint32_t rxrun; /*!< Stop/Active Rx Active Flag.
+ : Use @ref TSPI_RxState */
+ uint32_t rxend; /*!< Rx Data Receive Complete Flag.
+ : Use @ref TSPI_RxDone */
+ uint32_t intrxff; /*!< Rx FIFO Interrpt Flag
+ : Use @ref TSPI_RxFIFOInterruptFlag */
+ uint32_t rffll; /*!< Rx FIFO Full Flag
+ : Use @ref TSPI_RxFIFOFullFlag */
+ uint32_t rlvl; /*!< Rx Reach Fill Level
+ : Use @ref TSPI_RxReachFillLevel */
+} tspi_status_t;
+
+/*----------------------------------*/
+/**
+ * @struct tspi_error_t
+ * @brief Error flag.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t udrerr; /*!< Underrun Error.
+ : Use @ref TSPI_UnderrunErr */
+ uint32_t ovrerr; /*!< Overrun Error.
+ : Use @ref TSPI_OverrunErr */
+ uint32_t perr; /*!< Parity Error.
+ : Use @ref TSPI_ParityErr */
+} tspi_error_t;
+
+
+/*----------------------------------*/
+/**
+ * @struct tspi_initial_setting_t
+ * @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t id; /*!< ID: User value. */
+ tspi_control1_t cnt1; /*!< Control1 setting.
+ : Use @ref tspi_control1_t */
+ tspi_control2_t cnt2; /*!< Control2 setting.
+ : Use @ref tspi_control2_t */
+ tspi_control3_t cnt3; /*!< Control2 setting.
+ : Use @ref tspi_control2_t */
+ tspi_baudrate_t brd; /*!< Baudrate setting.
+ : Use @ref tspi_baudrate_t */
+ tspi_fmtr0_t fmr0; /*!< Format control0 setting.
+ : Use @ref tspi_fmtr0_t */
+ tspi_fmtr1_t fmr1; /*!< Format control1 setting.
+ : Use @ref tspi_fmtr1_t */
+} tspi_initial_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief TSPI handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct tspi_handle
+{
+ TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */
+ tspi_initial_setting_t init; /*!< Initial setting. */
+ uint32_t errcode; /*!< ErrorCode */
+ /*------------------------------------------*/
+ /*!
+ @brief Transmit Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ uint32_t rp; /*!< Num of transmited data. */
+ tspi_transmit_t info; /*!< Transmit Data Information. */
+ uint8_t tx_allign; /*!< Transmit Data length Information. */
+ void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
+ } transmit;
+ /*------------------------------------------*/
+ /*!
+ @brief Receive Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ tspi_receive_t info; /*!< Receive Data Information. */
+ uint8_t rx_allign; /*!< Receive Data length Information. */
+ void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */
+ } receive;
+} tspi_t;
+/**
+ * @}
+ */ /* End of group TSPI_Exported_Typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Exported_functions TSPI Exported Functions
+ * @{
+ */
+TXZ_Result tspi_init(tspi_t *p_obj);
+TXZ_Result tspi_deinit(tspi_t *p_obj);
+TXZ_Result tspi_format(tspi_t *p_obj);
+TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout);
+TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout);
+TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info);
+TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info);
+TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info);
+TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info);
+void tspi_irq_handler_transmit(tspi_t *p_obj);
+void tspi_irq_handler_receive(tspi_t *p_obj);
+void tspi_error_irq_handler(tspi_t *p_obj);
+TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status);
+TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error);
+TXZ_Result tspi_error_clear(tspi_t *p_obj);
+TXZ_Result tspi_discard_transmit(tspi_t *p_obj);
+TXZ_Result tspi_discard_receive(tspi_t *p_obj);
+/**
+ * @}
+ */ /* End of group TSPI_Exported_functions */
+/**
+ * @}
+ */ /* End of group TSPI */
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __TSPI_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_uart.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,812 @@
+/**
+ *******************************************************************************
+ * @file txz_uart.h
+ * @brief This file provides all the functions prototypes for UART driver.
+ * @version V1.0.0.0
+ * $Date:: 2017-07-21 15:39:36 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __UART_H
+#define __UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @defgroup UART UART
+ * @brief UART Driver.
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Exported_define UART Exported Define
+ * @{
+ */
+
+/**
+ * @defgroup UART_FifoMax Max Num of FIFO
+ * @brief Max Num of Tx/Rx Fifo.
+ * @{
+ */
+#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */
+#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */
+/**
+ * @}
+ */ /* End of group UART_FifoMax */
+
+/**
+ * @defgroup UART_HalfClockSelect Half Clock Select
+ * @brief Output Terminal Select
+ * @{
+ */
+#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */
+#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */
+/**
+ * @}
+ */ /* End of group UART_HalfClockSelect */
+
+/**
+ * @defgroup UART_HalfClockMode Half Clock Mode
+ * @brief Half Clock Mode Setting.
+ * @{
+ */
+#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */
+#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */
+/**
+ * @}
+ */ /* End of group UART_HalfClockMode */
+
+/**
+ * @defgroup UART_HalfClockCTR Half Clock Mode Control
+ * @brief Half Clock Control.
+ * @{
+ */
+#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */
+#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */
+/**
+ * @}
+ */ /* End of group UART_HalfClockCTR */
+
+/**
+ * @defgroup UART_LoopBack Loop Back Function
+ * @brief Half Clock Control.
+ * @{
+ */
+#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */
+#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */
+/**
+ * @}
+ */ /* End of group UART_LoopBack */
+
+
+/**
+ * @defgroup UART_NoiseFilter Noise Filter
+ * @brief Noise Filter Setting.
+ * @{
+ */
+#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */
+#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */
+#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */
+#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */
+#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */
+#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */
+#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */
+#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */
+/**
+ * @}
+ */ /* End of group UART_NoiseFilter */
+
+
+/**
+ * @defgroup UART_CTSHandshake CTS Handshake
+ * @brief Available CTS Handshake Macro Definisiton.
+ * @{
+ */
+#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_CTSHandshake */
+
+
+/**
+ * @defgroup UART_RTSHandshake RTS Handshake
+ * @brief Available RTS Handshake Macro Definisiton.
+ * @{
+ */
+#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_RTSHandshake */
+
+
+/**
+ * @defgroup UART_DataComplementation Data Complementation
+ * @brief Enable/Disable Data Signal Complementation Macro Definisiton.
+ * @{
+ */
+#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */
+/**
+ * @}
+ */ /* End of group UART_DataComplementation */
+
+
+/**
+ * @defgroup UART_DataDirection Data Direction
+ * @brief Data Direction Macro Definisiton.
+ * @{
+ */
+#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */
+#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */
+/*!
+ * @}
+ */ /* End of group UART_DataDirection */
+
+
+/**
+ * @defgroup UART_StopBit Stop Bit
+ * @brief Stop Bit Macro Definisiton.
+ * @{
+ */
+#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */
+#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */
+/**
+ * @}
+ */ /* End of group UART_StopBit */
+
+
+/**
+ * @defgroup UART_ParityBit Parity Bit
+ * @brief Parity Bit Macro Definisiton.
+ * @{
+ */
+#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
+#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */
+/**
+ * @}
+ */ /* End of group UART_ParityBit */
+
+
+/**
+ * @defgroup UART_ParityEnable Parity Enable
+ * @brief Enable/Disable Parity Macro Definisiton.
+ * @{
+ */
+#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */
+/**
+ * @}
+ */ /* End of group UART_ParityEnable */
+
+
+/**
+ * @defgroup UART_DataLength Data Length
+ * @brief Data Length Macro Definisiton.
+ * @{
+ */
+#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */
+#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */
+#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */
+/**
+ * @}
+ */ /* End of group UART_DataLength */
+
+
+/**
+ * @defgroup UART_TxFillLevelRange Tx Fill Level Range
+ * @brief Transmit Fill Level Range Macro Definisiton.
+ * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)".
+ * @{
+ */
+#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */
+#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */
+/*!
+ * @}
+ */ /* End of group UART_TxFillLevelRange */
+
+
+/**
+ * @defgroup UART_RxFillLevelRange Rx Fill Level Range
+ * @brief Receive Fill Level Range Macro Definisiton.
+ * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)".
+ * @{
+ */
+#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */
+#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */
+/**
+ * @}
+ */ /* End of group UART_RxFillLevelRange */
+
+
+/**
+ * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt
+ * @brief Available Transmit FIFO Interrupt Macro Definisiton.
+ * @{
+ */
+#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_TxFIFOInterrupt */
+
+
+/**
+ * @defgroup UART_TxInterrupt Tx Interrpt
+ * @brief Available Transmit Interrupt Macro Definisiton.
+ * @{
+ */
+#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_TxInterrupt */
+
+
+/**
+ * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt
+ * @brief Available Receive FIFO Interrupt Macro Definisiton.
+ * @{
+ */
+#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_RxFIFOInterrupt */
+
+
+/**
+ * @defgroup UART_RxInterrupt Rx Interrpt
+ * @brief Available Receive Interrupt Macro Definisiton.
+ * @{
+ */
+#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
+#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */
+/**
+ * @}
+ */ /* End of group UART_RxInterrupt */
+
+
+/**
+ * @defgroup UART_ErrorInterrupt Error Interrupt
+ * @brief Enable/Disable Error Interrupt Macro Definisiton.
+ * @{
+ */
+#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */
+/**
+ * @}
+ */ /* End of group UART_ErrorInterrupt */
+
+
+/**
+ * @defgroup UART_Prescaler Prescaler
+ * @brief Prescaler Macro Definisiton.
+ * @{
+ */
+#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */
+#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */
+#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */
+#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */
+#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */
+#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */
+#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */
+#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */
+#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */
+#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */
+/**
+ * @}
+ */ /* End of group UART_Prescaler */
+
+
+/**
+ * @defgroup UART_Clock_Mask Clock Mask
+ * @brief Clock Mask Macro Definisiton.
+ * @{
+ */
+#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */
+/**
+ * @}
+ */ /* End of group UART_Clock_Mask */
+
+
+/**
+ * @defgroup UART_Division Division
+ * @brief Enable/Disable Division Macro Definisiton.
+ * @{
+ */
+#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
+#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */
+/**
+ * @}
+ */ /* End of group UART_Division */
+
+
+/**
+ * @defgroup UART_RangeK Range K
+ * @brief Range of K Macro Definisiton.
+ * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)".
+ * @{
+ */
+#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */
+#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */
+/**
+ * @}
+ */ /* End of group UART_RangeK */
+
+
+/**
+ * @defgroup UART_RangeN Range N
+ * @brief Range of N Macro Definisiton.
+ * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)".
+ * @{
+ */
+#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */
+#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */
+/**
+ * @}
+ */ /* End of group UART_RangeN */
+
+
+/**
+ * @defgroup UART_SettingEnable Setting Enable
+ * @brief Enable/Disable Setting Macro Definisiton.
+ * @{
+ */
+#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */
+#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */
+#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */
+/**
+ * @}
+ */ /* End of group UART_SettingEnable */
+
+
+/**
+ * @defgroup UART_TxState Tx State
+ * @brief Transmitting State Macro Definisiton.
+ * @{
+ */
+#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */
+#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
+#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */
+/**
+ * @}
+ */ /* End of group UART_TxState */
+
+
+/**
+ * @defgroup UART_TxDone Transmitting Done
+ * @brief Transmitting Done Macro Definisiton.
+ * @{
+ */
+#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */
+#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */
+/**
+ * @}
+ */ /* End of group UART_TxDone */
+
+
+/**
+ * @defgroup UART_TxReachFillLevel Tx Reach Fill Level
+ * @brief Reach Transmitting Fill Level Macro Definisiton.
+ * @{
+ */
+#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */
+#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */
+/**
+ * @}
+ */ /* End of group UART_TxReachFillLevel */
+
+
+/**
+ * @defgroup UART_TxFifoLevel Tx FIFO Fill Level
+ * @brief Transmitting FIFO Fill Level Macro Definisiton.
+ * @{
+ */
+#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */
+/**
+ * @}
+ */ /* End of group UART_TxFifoLevel */
+
+
+/**
+ * @defgroup UART_RxState Rx State
+ * @brief Receive State Macro Definisiton.
+ * @{
+ */
+#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */
+#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
+#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */
+/**
+ * @}
+ */ /* End of group UART_RxState */
+
+
+/**
+ * @defgroup UART_RxDone Rx Done
+ * @brief Receive Done Macro Definisiton.
+ * @{
+ */
+#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */
+#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */
+/**
+ * @}
+ */ /* End of group UART_RxDone */
+
+
+/**
+ * @defgroup UART_RxReachFillLevel Rx Reach Fill Level
+ * @brief Reach Receive Fill Level Macro Definisiton.
+ * @{
+ */
+#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */
+#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */
+/**
+ * @}
+ */ /* End of group UART_RxReachFillLevel */
+
+
+/**
+ * @defgroup UART_RxFifoLevel Rx FIFO Fill Level
+ * @brief Receive FIFO Fill Level Macro Definisiton.
+ * @{
+ */
+#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */
+/**
+ * @}
+ */ /* End of group UART_RxFifoLevel */
+
+
+/**
+ * @defgroup UART_TriggerErr Trigger Error
+ * @brief Trigger Error Macro Definisiton.
+ * @{
+ */
+#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */
+/**
+ * @}
+ */ /* End of group UART_TxTriggerErr */
+
+
+/**
+ * @defgroup UART_OverrunErr Overrun Error
+ * @brief Overrun Error Macro Definisiton.
+ * @{
+ */
+#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */
+/**
+ * @}
+ */ /* End of group UART_OverrunErr */
+
+
+/**
+ * @defgroup UART_ParityErr Parity Error
+ * @brief Parity Error Macro Definisiton.
+ * @{
+ */
+#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */
+/**
+ * @}
+ */ /* End of group UART_ParityErr */
+
+
+/**
+ * @defgroup UART_FramingErr Framing Error
+ * @brief Framing Error Macro Definisiton.
+ * @{
+ */
+#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */
+/**
+ * @}
+ */ /* End of group UART_FramingErr */
+
+
+/**
+ * @defgroup UART_BreakErr Break Error
+ * @brief Break Error Macro Definisiton.
+ * @{
+ */
+#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
+#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */
+/**
+ * @}
+ */ /* End of group UART_BreakErr */
+
+/**
+ * @}
+ */ /* End of group UART_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Exported_define UART Exported Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Exported_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Exported_typedef UART Exported Typedef
+ * @{
+ */
+
+/*----------------------------------*/
+/**
+ * @brief Receive event information structure definenition.
+ * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this.
+ * @attention "num" must be over FIFO max num.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} uart_receive8_t;
+
+/*----------------------------------*/
+/**
+ * @brief Receive event information structure definenition.
+ * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint16_t *p_data; /*!< The buffer to receive data. */
+ uint32_t num; /*!< The number of receive data. */
+} uart_receive16_t;
+
+/*----------------------------------*/
+/**
+ * @brief Receive event information structure definenition.
+*/
+/*----------------------------------*/
+typedef union
+{
+ uart_receive8_t rx8; /*!< @ref uart_receive8_t */
+ uart_receive16_t rx16; /*!< @ref uart_receive16_t */
+} uart_receive_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit data information structure definenition.
+ * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint8_t *p_data; /*!< The buffer to transmit data. */
+ uint32_t num; /*!< The number of transmit data. */
+} uart_transmit8_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit data information structure definenition.
+ * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint16_t *p_data; /*!< The buffer to transmit data.
+ Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */
+ uint32_t num; /*!< The number of transmit data. */
+} uart_transmit16_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit data information structure definenition.
+*/
+/*----------------------------------*/
+typedef union
+{
+ uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */
+ uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */
+} uart_transmit_t;
+
+/*----------------------------------*/
+/**
+ * @brief Clock setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t prsel; /*!< Prescaler.
+ : Use @ref UART_Prescaler */
+} uart_clock_t;
+
+/*----------------------------------*/
+/**
+ * @brief Boudrate setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t ken; /*!< Enable/Disable Division Definisiton.
+ : Use @ref UART_Division */
+ uint32_t brk; /*!< Division Value K.
+ : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */
+ uint32_t brn; /*!< Division Value N.
+ : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */
+} uart_boudrate_t;
+
+/*----------------------------------*/
+/**
+ * @brief Transmit FIFO setting.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t inttx; /*!< Available Transmit FIFO Interrupt.
+ : Use @ref UART_TxFIFOInterrupt */
+ uint32_t level; /*!< Transmit Fill Level.
+ : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */
+} uart_tx_fifo_t;
+
+/*----------------------------------*/
+/**
+ * @brief Receive FIFO setting.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t intrx; /*!< Available Receive FIFO Interrupt.
+ : Use @ref UART_RxFIFOInterrupt */
+ uint32_t level; /*!< Receive Fill Level.
+ : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */
+} uart_rx_fifo_t;
+
+/*----------------------------------*/
+/**
+ * @brief Initial setting structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ uint32_t id; /*!< ID: User value. */
+ uart_clock_t clock; /*!< Clock setting.
+ : Use @ref uart_clock_t */
+ uart_boudrate_t boudrate; /*!< Boudrate setting.
+ : Use @ref uart_boudrate_t */
+ uint32_t inttx; /*!< Available Transmit Interrupt.
+ : Use @ref UART_TxInterrupt */
+ uint32_t intrx; /*!< Available Receive Interrupt.
+ : Use @ref UART_RxInterrupt */
+ uint32_t interr; /*!< Available Error Interrupt.
+ : Use @ref UART_ErrorInterrupt */
+ uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting.
+ : Use @ref uart_tx_fifo_t */
+ uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting.
+ : Use @ref uart_rx_fifo_t */
+ uint32_t hct; /*!< Half Clock Terminal Select.
+ : Use @ref UART_HalfClockSelect */
+ uint32_t hcm; /*!< Half Clock Mode Select.
+ : Use @ref UART_HalfClockMode */
+ uint32_t hcc; /*!< Half Clock Control.
+ : Use @ref UART_HalfClockCTR */
+ uint32_t lbc; /*!< Loop Back Control.
+ : Use @ref UART_LoopBack */
+ uint32_t nf; /*!< UTxRXD Noise Filter.
+ : Use @ref UART_NoiseFilter */
+ uint32_t ctse; /*!< Available CTS Handshake.
+ : Use @ref UART_CTSHandshake */
+ uint32_t rtse; /*!< Available RTS Handshake.
+ : Use @ref UART_RTSHandshake */
+ uint32_t iv; /*!< Data Signal Complementation.
+ : Use @ref UART_DataComplementation */
+ uint32_t dir; /*!< Data Direction.
+ : Use @ref UART_DataDirection */
+ uint32_t sblen; /*!< Stop Bit.
+ : Use @ref UART_StopBit */
+ uint32_t even; /*!< Odd/Even Parity Bit.
+ : Use @ref UART_ParityBit */
+ uint32_t pe; /*!< Enable/Disable Parity Bit.
+ : Use @ref UART_ParityEnable */
+ uint32_t sm; /*!< Data Length.
+ : Use @ref UART_DataLength */
+} uart_initial_setting_t;
+
+/*----------------------------------*/
+/**
+ * @brief UART handle structure definenition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ TSB_UART_TypeDef *p_instance; /*!< Registers base address. */
+ uart_initial_setting_t init; /*!< Initial setting. */
+ /*------------------------------------------*/
+ /*!
+ @brief Transmit Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ uint32_t rp; /*!< Num of transmited data. */
+ uart_transmit_t info; /*!< Transmit Data Information. */
+ void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
+ } transmit;
+ /*------------------------------------------*/
+ /*!
+ @brief Receive Informatin.
+ */
+ /*------------------------------------------*/
+ struct
+ {
+ uart_receive_t info; /*!< Receive Data Information. */
+ void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */
+ } receive;
+} uart_t;
+
+/**
+ * @}
+ */ /* End of group UART_Exported_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Exported_functions UART Exported Functions
+ * @{
+ */
+TXZ_Result uart_init(uart_t *p_obj);
+TXZ_Result uart_deinit(uart_t *p_obj);
+TXZ_Result uart_discard_transmit(uart_t *p_obj);
+TXZ_Result uart_discard_receive(uart_t *p_obj);
+TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info);
+TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info);
+void uart_transmit_irq_handler(uart_t *p_obj);
+void uart_receive_irq_handler(uart_t *p_obj);
+void uart_error_irq_handler(uart_t *p_obj);
+TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status);
+TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error);
+TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting);
+/**
+ * @}
+ */ /* End of group UART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group UART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __UART_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/inc/txz_uart_include.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,476 @@
+/**
+ *******************************************************************************
+ * @file txz_uart_include.h
+ * @brief This file provides internal common definition.
+ * @version V1.0.0.0
+ * $Date:: 2017-07-21 15:39:36 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+/*------------------------------------------------------------------------------*/
+/* Define to prevent recursive inclusion */
+/*------------------------------------------------------------------------------*/
+#ifndef __UART_INCLUDE_H
+#define __UART_INCLUDE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_driver_def.h"
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup UART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UART_Private_define
+ * @{
+ */
+
+/**
+ * @defgroup UART_NullPointer Null Pointer
+ * @brief Null Pointer.
+ * @{
+ */
+#define UART_NULL ((void *)0)
+/**
+ * @}
+ */ /* End of group UART_NullPointer */
+
+/**
+ * @defgroup UART_ParameterResult Parameter Check Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of group UART_ParameterResult */
+
+/**
+ * @defgroup UARTxSWRST UARTxSWRST Register
+ * @brief UARTxSWRST Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-8 | - |
+ * | 7 | SWRSTF |
+ * | 6:2 | - |
+ * | 1:0 | SWRST |
+ * @{
+ */
+/* SWRSTF */
+#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */
+#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */
+#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */
+/* SWRST */
+#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */
+#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */
+/**
+ * @}
+ */ /* End of group UARTxSWRST */
+
+/**
+ * @defgroup UARTxCR0 UARTxCR0 Register
+ * @brief UARTxCR0 Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-19 | - |
+ * | 18 | HBSST |
+ * | 17 | HBSMD |
+ * | 16 | HBSEN |
+ * | 15 | LPB |
+ * | 14-12 | NF[2:0] |
+ * | 11 | - |
+ * | 10 | CTSE |
+ * | 9 | RTSE |
+ * | 8 | WU |
+ * | 7 | - |
+ * | 6 | IV |
+ * | 5 | DIR |
+ * | 4 | SBLEN |
+ * | 3 | EVEN |
+ * | 2 | PE |
+ * | 1-0 | SM[1:0] |
+ * @{
+ */
+/* HBSST */
+#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */
+/* HBSMD */
+#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */
+/* HBSEN */
+#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */
+#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */
+#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */
+/* LPB */
+#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */
+#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */
+#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */
+/* WU */
+#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */
+#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */
+#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */
+/**
+ * @}
+ */ /* End of group UARTxCR0 */
+
+/**
+ * @defgroup UARTxCR1 UARTxCR1 Register
+ * @brief UARTxCR1 Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-15 | - |
+ * | 14-12 | TIL[2:0] |
+ * | 11 | - |
+ * | 10-8 | RIL[2:0] |
+ * | 7 | INTTXFE |
+ * | 6 | INTTXWE |
+ * | 5 | INTRXFE |
+ * | 4 | INTRXWE |
+ * | 3 | - |
+ * | 2 | INTERR |
+ * | 1 | DMATE |
+ * | 0 | DMARE |
+ * @{
+ */
+/* RIL */
+#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */
+/* DMATE */
+#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */
+#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */
+#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */
+/* DMARE */
+#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */
+#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */
+#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */
+/**
+ * @}
+ */ /* End of group UARTxCR1 */
+
+/**
+ * @defgroup UARTxTRANS UARTxTRANS Register
+ * @brief UARTxTRANS Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-4 | - |
+ * | 3 | BK |
+ * | 2 | TXTRG |
+ * | 1 | TXE |
+ * | 0 | RXE |
+ * @{
+ */
+/* BK */
+#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */
+#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */
+#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */
+/* TXTRG */
+#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */
+#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */
+#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */
+/* TXE */
+#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */
+#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */
+#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */
+/* RXE */
+#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */
+#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */
+#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */
+/* TXE,RXE */
+#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */
+/**
+ * @}
+ */ /* End of group UARTxTRANS */
+
+/**
+ * @defgroup UARTxDR UARTxDR Register
+ * @brief UARTxDR Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-19 | - |
+ * | 18 | PERR |
+ * | 17 | FERR |
+ * | 16 | BERR |
+ * | 15:9 | - |
+ * | 8:0 | DR |
+ * @{
+ */
+/* DR */
+#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */
+#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
+#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */
+/**
+ * @}
+ */ /* End of group UARTxDR */
+
+/**
+ * @defgroup UARTxSR UARTxSR Register
+ * @brief UARTxSR Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31 | SUE |
+ * | 30:16 | - |
+ * | 15 | TXRUN |
+ * | 14 | TXEND |
+ * | 13 | TXFF |
+ * | 12 | - |
+ * | 11:8 | TLVL |
+ * | 7 | RXRUN |
+ * | 6 | RXEND |
+ * | 5 | RXFF |
+ * | 4 | - |
+ * | 3:0 | RLVL |
+ * @{
+ */
+/* SUE */
+#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */
+/* TXEND */
+#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */
+#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */
+#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */
+/* TXFF */
+#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */
+#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */
+#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */
+/* TLVL */
+#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */
+/* RXEND */
+#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */
+#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */
+#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */
+/* RXFF */
+#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */
+#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */
+#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */
+/* RLVL */
+#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */
+/**
+ * @}
+ */ /* End of group UARTxSR */
+
+/**
+ * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register
+ * @brief UARTxFIFOCLR Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-2 | - |
+ * | 1 | TFCLR |
+ * | 0 | RFCLR |
+ * @{
+ */
+/* TFCLR */
+#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */
+/* RFCLR */
+#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */
+/**
+ * @}
+ */ /* End of group UARTxFIFOCLR */
+
+/**
+ * @defgroup UARTxERR UARTxERR Register
+ * @brief UARTxERR Register Definition.
+ * @details Detail.
+ * | Bit | Bit Symbol |
+ * | :--- | :--- |
+ * | 31-5 | - |
+ * | 4 | TRGERR |
+ * | 3 | OVRERR |
+ * | 2 | PERR |
+ * | 1 | FERR |
+ * | 0 | BERR |
+ * @{
+ */
+/* TRGERR */
+#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */
+#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */
+#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */
+#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */
+/* OVRERR */
+#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */
+#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */
+#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */
+#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */
+/* PERR */
+#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */
+#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */
+#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */
+#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */
+/* FERR */
+#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */
+#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */
+#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */
+#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */
+/* BERR */
+#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */
+#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */
+#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */
+#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */
+/**
+ * @}
+ */ /* End of group UARTxERR */
+
+/**
+ * @}
+ */ /* End of group UART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UART_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UART_Private_typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Inline Functions */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UART_Private_fuctions
+ * @{
+ */
+__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
+__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
+__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
+__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
+/*--------------------------------------------------*/
+/**
+ * @brief Disable UARTxTRANS TXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 0;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable UARTxTRANS TXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,1))) = 1;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disable UARTxTRANS RXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 0;
+#endif
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable UARTxTRANS RXE.
+ * @param p_instance: Instance address.
+ * @retval -
+ * @note Bitband Access
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
+{
+#ifdef DEBUG
+ if ((uint32_t)p_instance >= (uint32_t)PERI_BASE)
+ {
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1;
+ }
+#else
+ (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS,0))) = 1;
+#endif
+}
+
+
+/**
+ * @}
+ */ /* End of group UART_Private_functions */
+
+/**
+ * @}
+ */ /* End of group UART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __UART_EX_H */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/adc.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1200 @@
+/**
+ *******************************************************************************
+ * @file adc.c
+ * @brief This file provides API functions for ADC driver.
+ * @version V1.0.0.0
+ * $Date:: 2017-09-07 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "adc_include.h"
+#include "adc_ch.h"
+#include "adc.h"
+
+#if defined(__ADC_H)
+/**
+ * @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/**
+ * @addtogroup ADC
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_macro ADC Private Macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_Enumeration ADC Private Enumeration
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_Enumeration */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_typedef ADC Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Variable Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_variable ADC Private Variable Definition
+ * @{
+ */
+static adc_t *p_AdcObj;
+/**
+ * @}
+ */ /* End of group ADC_Private_variable */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_fuctions ADC Private Fuctions
+ * @{
+ */
+static int32_t check_param_sampling_period0(adc_sampling_period0_t param);
+static int32_t check_param_sampling_period1(adc_sampling_period1_t param);
+static int32_t check_param_prescaler_output(adc_sclk_t param);
+static int32_t check_param_interrupt(adc_int_t param);
+static int32_t check_param_type(adc_conversion_t param);
+static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max);
+static void clear_ch_instance_info(adc_ch_t *p_ch);
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param)
+ * @brief Check the Sampling Period's parameter.
+ * @param[in] param :Sampling Period's parameter
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx".
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_sampling_period0(adc_sampling_period0_t param)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ switch (param)
+ {
+ case ADC_SAMPLING_PERIOD0_XN:
+ case ADC_SAMPLING_PERIOD0_X2N:
+ case ADC_SAMPLING_PERIOD0_X3N:
+ case ADC_SAMPLING_PERIOD0_X4N:
+ case ADC_SAMPLING_PERIOD0_X16N:
+ case ADC_SAMPLING_PERIOD0_X64N:
+ result = ADC_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param)
+ * @brief Check the Sampling Period's parameter.
+ * @param[in] param :Sampling Period's parameter
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx".
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_sampling_period1(adc_sampling_period1_t param)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ switch (param)
+ {
+ case ADC_SAMPLING_PERIOD1_XN:
+ case ADC_SAMPLING_PERIOD1_X2N:
+ case ADC_SAMPLING_PERIOD1_X3N:
+ case ADC_SAMPLING_PERIOD1_X4N:
+ case ADC_SAMPLING_PERIOD1_X16N:
+ case ADC_SAMPLING_PERIOD1_X64N:
+ result = ADC_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_prescaler_output(adc_sclk_t param)
+ * @brief Check the AD Prescaler Output's parameter.
+ * @param[in] param :AD Prescaler Output's parameter
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx".
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_prescaler_output(adc_sclk_t param)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ switch (param)
+ {
+ case ADC_SCLK_1:
+ case ADC_SCLK_2:
+ case ADC_SCLK_4:
+ case ADC_SCLK_8:
+ case ADC_SCLK_16:
+ result = ADC_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_interrupt(adc_int_t param)
+ * @brief Check the Interrupt's parameter.
+ * @param[in] param :Interrupt's parameter
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_interrupt(adc_int_t param)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ switch (param)
+ {
+ case ADC_INT_DISABLE:
+ case ADC_INT_ENABLE:
+ result = ADC_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_type(adc_conversion_t param)
+ * @brief Check the Conversion Type's parameter.
+ * @param[in] param :Conversion Type's parameter
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx".
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_type(adc_conversion_t param)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ switch (param)
+ {
+ case ADC_CONVERSION_DISABLE:
+ case ADC_CONVERSION_CNT:
+ case ADC_CONVERSION_SGL:
+ case ADC_CONVERSION_TRG:
+ case ADC_CONVERSION_HPTG:
+ result = ADC_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max)
+ * @brief Check the AIN Range's parameter.
+ * @param[in] ain :AIN Range's parameter
+ * @param[in] min :Range Min.
+ * @param[in] max :Range Max.
+ * @retval ADC_PARAM_OK :Success.
+ * @retval ADC_PARAM_NG :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max)
+{
+ int32_t result = ADC_PARAM_NG;
+
+ if (min == 0)
+ {
+ if (ain <= max)
+ {
+ result = ADC_PARAM_OK;
+ }
+ }
+ else
+ {
+ if ((min <= ain) && (ain <= max))
+ {
+ result = ADC_PARAM_OK;
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void clear_ch_instance_info(adc_ch_t *p_ch)
+ * @brief Channel Instance Information Clear.
+ * @param[in] p_ch :Channel Instance Address.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+static void clear_ch_instance_info(adc_ch_t *p_ch)
+{
+ p_ch->p_tset = ADC_NULL;
+ p_ch->p_reg = ADC_NULL;
+ p_ch->init.type = ADC_CONVERSION_DISABLE;
+}
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_compa_irq_handler( void )
+ * @brief IRQ Handler for Compare_A done.
+ * @param -
+ * @retval -
+ * @note Call by Compare_A Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_compa_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL))
+ {
+ p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_compb_irq_handler( void )
+ * @brief IRQ Handler for Compare_B done.
+ * @param -
+ * @retval -
+ * @note Call by Compare_B Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_compb_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL))
+ {
+ p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_single_irq_handler( void )
+ * @brief IRQ Handler for single conversion done.
+ * @param -
+ * @retval -
+ * @note Call by Single Conversion Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_single_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->handler.single != ADC_NULL))
+ {
+ p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_continuity_irq_handler( void )
+ * @brief IRQ Handler for continuity conversion done.
+ * @param -
+ * @retval -
+ * @note Call by Continuity Conversion Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_continuity_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->handler.continuity != ADC_NULL))
+ {
+ p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_trigger_irq_handler( void )
+ * @brief IRQ Handler for trigger conversion done.
+ * @param -
+ * @retval -
+ * @note Call by Trigger Conversion Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_trigger_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->handler.trigger != ADC_NULL))
+ {
+ p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn static void adc_highpriority_irq_handler( void )
+ * @brief IRQ Handler for highpriority conversion done.
+ * @param -
+ * @retval -
+ * @note Call by HigPriority Conversion Done IRQ Handler.
+ */
+/*--------------------------------------------------*/
+void adc_highpriority_irq_handler( void )
+{
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if ((p_AdcObj != ADC_NULL) &&
+ (p_AdcObj->handler.highpriority != ADC_NULL))
+ {
+ p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS);
+ }
+}
+
+/**
+ * @}
+ */ /* End of group ADC_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup ADC_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_init(adc_t *p_obj)
+ * @brief Initialize the ADC object.
+ * @param[in] p_obj :ADC object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_init(adc_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ p_AdcObj = p_obj;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ /* Check the parameter. */
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if ((void*)(p_obj->p_instance) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if (p_obj->init.clk.sampling_select > 0x0100000)
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if(result == TXZ_SUCCESS)
+ {
+ /*------------------------------*/
+ /* Init Variable */
+ /*------------------------------*/
+ uint32_t i;
+
+ for (i=0; i<ADC_NUM_MAX; i++)
+ {
+ clear_ch_instance_info(&p_obj->info.ch[i]);
+ }
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxCLK ---*/
+ p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld);
+ /*--- ADxEXAZSEL ---*/
+ p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select;
+ /*--- ADxMOD0 ---*/
+ p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON);
+ /*--- ADxMOD1 ---*/
+ p_obj->p_instance->MOD1 = p_obj->init.mod1;
+ /*--- ADxMOD2 ---*/
+ p_obj->p_instance->MOD2 = p_obj->init.mod2;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_deinit(adc_t *p_obj)
+ * @brief Release the ADC object.
+ * @param[in] p_obj :ADC object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_deinit(adc_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t i;
+ adc_ch_t *p_ch;
+ p_AdcObj = p_obj;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxCR0 ---*/
+ p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE);
+ /*------------------------------*/
+ /* Wait Stop */
+ /*------------------------------*/
+ /*--- ADxST ---*/
+ /* When all convetion stop, ADxST is set "0". */
+ while(p_obj->p_instance->ST != 0)
+ {
+ /* no processing */
+ }
+ /*------------------------------*/
+ /* Channel Class Destruct */
+ /*------------------------------*/
+ for (i=0; i<ADC_NUM_MAX; i++)
+ {
+ p_ch = &p_obj->info.ch[i];
+ if (p_ch->init.type == ADC_CONVERSION_DISABLE)
+ {
+ if (adc_ch_deinit(p_ch) == TXZ_SUCCESS)
+ {
+ clear_ch_instance_info(p_ch);
+ }
+ }
+ }
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxCMPEN ---*/
+ p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE);
+ /*--- ADxCR1 ---*/
+ p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
+ /*--- ADxMOD0 ---*/
+ p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF);
+ /*--- ADxMOD1 ---*/
+ p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3;
+ /*--- ADxMOD2 ---*/
+ p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting)
+ * @brief ADC Channel Setting
+ * @param[in] p_obj :ADC object.
+ * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX).
+ * @param[in] p_setting :Channel Setting Source Address.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ p_AdcObj = p_obj;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0) ||
+ ((void*)(p_setting) == (void*)0) ||
+ (ch >= ADC_NUM_MAX))
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ if(result == TXZ_SUCCESS)
+ {
+ /*------------------------------*/
+ /* Channel Class Construct */
+ /*------------------------------*/
+ adc_ch_t *p_ch = &p_obj->info.ch[ch];
+
+ p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch);
+ p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch);
+ p_ch->init.interrupt = p_setting->interrupt;
+ p_ch->init.type = p_setting->type;
+ p_ch->init.ain = p_setting->ain;
+ result = adc_ch_init(p_ch);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch)
+ * @brief ADC Channel Clear
+ * @param[in] p_obj :ADC object.
+ * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX).
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ p_AdcObj = p_obj;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ (ch >= ADC_NUM_MAX))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Channel Class Destruct */
+ /*------------------------------*/
+ adc_ch_t *p_ch = &p_obj->info.ch[ch];
+
+ result = adc_ch_deinit(p_ch);
+ /* Init Variable */
+ clear_ch_instance_info(p_ch);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t)
+ * @brief Initialize the ADC Compare register
+ * @param[in] p_obj :ADC object.
+ * @param[in] p_cmpx_t :Clock information structure.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ * @attention After initialization, 3us of stabilization time is needed.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ p_AdcObj = p_obj;
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_cmpx_t) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Init Variable */
+ /*------------------------------*/
+ if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE)
+ {
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE;
+ }
+ if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE)
+ {
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE;
+ }
+ if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE)
+ {
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE;
+ }
+ if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE)
+ {
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE;
+ }
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE)
+ {
+ p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN;
+ p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT;
+ p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond;
+ p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml;
+ p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg;
+ p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp;
+ p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle;
+ p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN;
+ p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg;
+ p_obj->p_instance->CMP0 = p_cmpx_t->ADComp;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE)
+ {
+ p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN;
+ p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT;
+ p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond;
+ p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml;
+ p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg;
+ p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp;
+ p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle;
+ p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN;
+ p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg;
+ p_obj->p_instance->CMP1 = p_cmpx_t->ADComp;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP2EN_ENABLE)
+ {
+ p_obj->init.CMPxEN[2].CMPEN = p_cmpx_t->CMPEN;
+ p_obj->init.CMPxEN[2].CMPCNT = p_cmpx_t->CMPCNT;
+ p_obj->init.CMPxEN[2].CMPCond = p_cmpx_t->CMPCond;
+ p_obj->init.CMPxEN[2].CMPBigSml = p_cmpx_t->CMPBigSml;
+ p_obj->init.CMPxEN[2].StrReg = p_cmpx_t->StrReg;
+ p_obj->init.CMPxEN[2].ADComp = p_cmpx_t->ADComp;
+ p_obj->init.CMPxEN[2].handle = p_cmpx_t->handle;
+ p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN;
+ p_obj->p_instance->CMPCR2 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg;
+ p_obj->p_instance->CMP2 = p_cmpx_t->ADComp;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP3EN_ENABLE)
+ {
+ p_obj->init.CMPxEN[3].CMPEN = p_cmpx_t->CMPEN;
+ p_obj->init.CMPxEN[3].CMPCNT = p_cmpx_t->CMPCNT;
+ p_obj->init.CMPxEN[3].CMPCond = p_cmpx_t->CMPCond;
+ p_obj->init.CMPxEN[3].CMPBigSml = p_cmpx_t->CMPBigSml;
+ p_obj->init.CMPxEN[3].StrReg = p_cmpx_t->StrReg;
+ p_obj->init.CMPxEN[3].ADComp = p_cmpx_t->ADComp;
+ p_obj->init.CMPxEN[3].handle = p_cmpx_t->handle;
+ p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN;
+ p_obj->p_instance->CMPCR3 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg;
+ p_obj->p_instance->CMP3 = p_cmpx_t->ADComp;
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t)
+ * @brief Release the ADC Compare register
+ * @param[in] p_obj :ADC object.
+ * @param[in] p_cmpx_t :Clock information structure.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ * @attention After initialization, 3us of stabilization time is needed.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ p_AdcObj = p_obj;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_cmpx_t) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE)
+ {
+ p_obj->init.CMPxEN[0].CMPEN = 0;
+ p_obj->init.CMPxEN[0].CMPCNT = 0;
+ p_obj->init.CMPxEN[0].CMPCond = 0;
+ p_obj->init.CMPxEN[0].CMPBigSml = 0;
+ p_obj->init.CMPxEN[0].StrReg = 0;
+ p_obj->init.CMPxEN[0].ADComp = 0;
+ p_obj->init.CMPxEN[0].handle = (void*)0;
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE;
+ p_obj->p_instance->CMPCR0 = 0;
+ p_obj->p_instance->CMP0 = 0;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE)
+ {
+ p_obj->init.CMPxEN[1].CMPEN = 0;
+ p_obj->init.CMPxEN[1].CMPCNT = 0;
+ p_obj->init.CMPxEN[1].CMPCond = 0;
+ p_obj->init.CMPxEN[1].CMPBigSml = 0;
+ p_obj->init.CMPxEN[1].StrReg = 0;
+ p_obj->init.CMPxEN[1].ADComp = 0;
+ p_obj->init.CMPxEN[1].handle = (void*)0;
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE;
+ p_obj->p_instance->CMPCR1 = 0;
+ p_obj->p_instance->CMP1 = 0;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP2EN_DISABLE)
+ {
+ p_obj->init.CMPxEN[2].CMPEN = 0;
+ p_obj->init.CMPxEN[2].CMPCNT = 0;
+ p_obj->init.CMPxEN[2].CMPCond = 0;
+ p_obj->init.CMPxEN[2].CMPBigSml = 0;
+ p_obj->init.CMPxEN[2].StrReg = 0;
+ p_obj->init.CMPxEN[2].ADComp = 0;
+ p_obj->init.CMPxEN[2].handle = (void*)0;
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP2EN_ENABLE;
+ p_obj->p_instance->CMPCR2 = 0;
+ p_obj->p_instance->CMP2 = 0;
+ }
+ else if (p_cmpx_t->CMPEN == ADCMP3EN_DISABLE)
+ {
+ p_obj->init.CMPxEN[3].CMPEN = 0;
+ p_obj->init.CMPxEN[3].CMPCNT = 0;
+ p_obj->init.CMPxEN[3].CMPCond = 0;
+ p_obj->init.CMPxEN[3].CMPBigSml = 0;
+ p_obj->init.CMPxEN[3].StrReg = 0;
+ p_obj->init.CMPxEN[3].ADComp = 0;
+ p_obj->init.CMPxEN[3].handle = (void*)0;
+ p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP3EN_ENABLE;
+ p_obj->p_instance->CMPCR3 = 0;
+ p_obj->p_instance->CMP3 = 0;
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value)
+ * @brief Get AD value
+ * @param[in] p_obj :ADC object.
+ * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX).
+ * @param p_value :AD value. Destination address.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value)
+{
+ TXZ_Result result = TXZ_ERROR;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0) ||
+ ((void*)(p_value) == (void*)0) ||
+ (ch >= ADC_NUM_MAX))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Get Value */
+ /*------------------------------*/
+ adc_ch_t *p_ch = &p_obj->info.ch[ch];
+
+ result = adc_ch_get_value(p_ch, p_value);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_start(adc_t *p_obj)
+ * @brief Start Conversion.
+ * @param[in] p_obj :ADC object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_start(adc_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Enable Conversion */
+ /*------------------------------*/
+ uint32_t i;
+ adc_ch_t *p_ch;
+ uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE);
+ uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
+
+ for (i=0; i<ADC_NUM_MAX; i++)
+ {
+ p_ch = &p_obj->info.ch[i];
+ switch (p_ch->init.type)
+ {
+ case ADC_CONVERSION_CNT:
+ cr0 |= ADxCR0_CNT_ENABLE;
+ break;
+ case ADC_CONVERSION_SGL:
+ cr0 |= ADxCR0_SGL_ENABLE;
+ break;
+ case ADC_CONVERSION_TRG:
+ cr1 |= ADxCR1_TRGEN_ENABLE;
+ break;
+ case ADC_CONVERSION_HPTG:
+ cr1 |= ADxCR1_HPTRGEN_ENABLE;
+ break;
+ default:
+ /* no processing */
+ break;
+ }
+ }
+ /*--- ADxCR1 ---*/
+ p_obj->p_instance->CR1 = cr1;
+ /*--- ADxCR0 ---*/
+ p_obj->p_instance->CR0 = cr0;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_stop(adc_t *p_obj)
+ * @brief Stop Conversion.
+ * @param[in] p_obj :ADC object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_stop(adc_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t i;
+ adc_ch_t *p_ch;
+ uint32_t value;
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Disable Conversion */
+ /*------------------------------*/
+ /*--- ADxCR0 ---*/
+ p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE);
+ /*------------------------------*/
+ /* Wait Stop */
+ /*------------------------------*/
+ /*--- ADxST ---*/
+ /* When all convetion stop, ADxST is set "0". */
+ while(p_obj->p_instance->ST != 0)
+ {
+ /* no processing */
+ }
+ /*------------------------------*/
+ /* Dummy Read */
+ /*------------------------------*/
+ /* Read is needed before the next convertion. */
+ for (i=0; i<ADC_NUM_MAX; i++)
+ {
+ p_ch = &p_obj->info.ch[i];
+ if (p_ch->init.type == ADC_CONVERSION_DISABLE)
+ {
+ if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ }
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout)
+ * @brief Wait for single conversion to be completed
+ * @param[in] p_obj :ADC object.
+ * @param[in] timeout :Timeout(tick).
+ * @retval TXZ_DONE :Success.
+ * @retval TXZ_BUSY :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout)
+{
+ TXZ_WorkState result = TXZ_BUSY;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ uint32_t base = hal_get_tick();
+ uint32_t current = 0;
+ uint32_t status;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0))
+ {
+ result = TXZ_DONE;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Check Status */
+ /*------------------------------*/
+ while(loopBreak == TXZ_BUSY)
+ {
+ /*--- Check Status ---*/
+ /* Read status. */
+ status = p_obj->p_instance->ST;
+ /* Check status. */
+ if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE)
+ {
+ result = TXZ_DONE;
+ loopBreak = TXZ_DONE;
+ }
+ else
+ {
+ /*--- Check Timeout ---*/
+ if (timeout == 0)
+ {
+ loopBreak = TXZ_DONE;
+ }
+ else
+ {
+ current = hal_get_tick();
+ if (current > base)
+ {
+ if ((current - base) >= timeout)
+ {
+ loopBreak = TXZ_DONE;
+ }
+ }
+ else
+ {
+ base = current;
+ }
+ }
+ }
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status)
+ * @brief Get Conversion Status.
+ * @details Status bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-8 | - | - |
+ * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. |
+ * | 6-4 | - | - |
+ * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. |
+ * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. |
+ * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. |
+ * | 0 | - | - |
+ *
+ * @param[in] p_obj :ADC object.
+ * @param[out] p_status :Conversion Status. Destination address.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((void*)(p_obj->p_instance) == (void*)0) ||
+ ((void*)(p_status) == (void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Read Register */
+ /*------------------------------*/
+ *p_status = p_obj->p_instance->ST;
+ }
+
+ return (result);
+}
+/**
+ * @}
+ */ /* End of group ADC_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group ADC */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__ADC_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/adc_ch.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,351 @@
+/**
+ *******************************************************************************
+ * @file adc_ch.c
+ * @brief This file provides API functions for ADC driver. \n
+ * Channel Class.
+ * @version V1.0.0.0
+ * $Date:: 2017-09-07 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "adc_include.h"
+#include "adc_ch.h"
+
+#if defined(__ADC_CH_H)
+/**
+ * @addtogroup Periph_Driver Peripheral Driver
+ * @{
+ */
+
+/**
+ * @addtogroup ADC
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_define ADC Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_typedef ADC Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group ADC_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup ADC_Private_fuctions ADC Private Fuctions
+ * @{
+ */
+#ifdef DEBUG
+ /* no define */
+#endif
+
+/**
+ * @}
+ */ /* End of group ADC_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup ADC_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/*!
+ * @fn static uint32_t get_conversion_data(uint32_t reg)
+ * @brief Get convertion data from ADxREGn.
+ * @param[in] reg :ADxREGn data.
+ * @retval Convertion data.
+ * @note -
+ */
+/*--------------------------------------------------*/
+uint32_t get_conversion_data(uint32_t reg)
+{
+ uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4);
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj)
+ * @brief Initialize the ADC Channel object.
+ * @param[in][out] p_obj :ADC Channel object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_ch_init(adc_ch_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((volatile void*)(p_obj->p_tset) == (volatile void*)0) ||
+ ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxREGx ---*/
+ /* Read is needed before the next convertion. */
+ {
+ volatile uint32_t reg;
+ reg = *p_obj->p_reg;
+ }
+ /*--- ADxTSET ---*/
+ *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj)
+ * @brief Release the ADC Channel object.
+ * @param[in][out] p_obj :ADC Channel object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_ch_deinit(adc_ch_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxTSET ---*/
+ *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0);
+ /*--- ADxREGx ---*/
+ /* Read is needed before the next convertion. */
+ {
+ volatile uint32_t reg;
+ reg = *p_obj->p_reg;
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj)
+ * @brief Enable Interrupt.
+ * @param[in][out] p_obj :ADC Channel object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((volatile void*)(p_obj->p_tset) == (volatile void*)0) ||
+ ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxTSET ---*/
+ {
+ uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
+
+ *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj)
+ * @brief Disable Interrupt.
+ * @param[in][out] p_obj :ADC Channel object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has stoped.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if (((void*)(p_obj) == (void*)0) ||
+ ((volatile void*)(p_obj->p_tset) == (volatile void*)0) ||
+ ((volatile const void*)(p_obj->p_reg) == (volatile const void*)0))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- ADxTSET ---*/
+ {
+ uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
+
+ *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value)
+ * @brief Get conversion value.
+ * @param p_obj :ADC Channel object.
+ * @param p_value :AD value. Destination address.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @pre Conversion has done.
+ */
+/*--------------------------------------------------*/
+TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value)
+{
+ TXZ_Result result = TXZ_ERROR;
+ uint32_t reg;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ reg = *p_obj->p_reg;
+ /*------------------------------*/
+ /* Check Result */
+ /*------------------------------*/
+ if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON)
+ {
+ *p_value = get_conversion_data(reg);
+ result = TXZ_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+/**
+ * @}
+ */ /* End of group ADC_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group ADC */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__ADC_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/tmpm4g9_fc.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,646 @@
+/**
+ *******************************************************************************
+ * @file fc.c
+ * @brief Flash_Userboot Sample Application.
+ * @version V1.0.1.0
+ * $Date:: 2017-06-23 13:52:12 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include <string.h>
+#include "tmpm4g9_fc.h"
+//#include "txz_sample_def.h"
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @defgroup Flash_Userboot Flash_Userboot Sample Appli
+ * @{
+ */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
+ * @{
+ */
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
+ * @{
+ */
+#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
+#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */
+#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */
+#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */
+#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */
+#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */
+
+/****************** Changed by TSIP *************************************/
+///* Area Selection All */
+#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL)
+#define FC_AREASEL_AREA0 (uint32_t)(0x00000777UL) //select Area 0,1 and 2
+#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0888UL) //mask Area 0,1 and 2
+#define FC_AREASEL_WRITE_MODE (uint32_t)(0x1C000000UL)
+
+static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = {
+ (0x5E000000UL), /*!< CODE FLASH Page0 */
+ (0x5E001000UL), /*!< CODE FLASH Page1 */
+ (0x5E002000UL), /*!< CODE FLASH Page2 */
+ (0x5E003000UL), /*!< CODE FLASH Page3 */
+ (0x5E004000UL), /*!< CODE FLASH Page4 */
+ (0x5E005000UL), /*!< CODE FLASH Page5 */
+ (0x5E006000UL), /*!< CODE FLASH Page6 */
+ (0x5E007000UL), /*!< CODE FLASH Page7 */
+ (0x5E008000UL), /*!< CODE FLASH Page8 */
+ (0x5E009000UL), /*!< CODE FLASH Page9 */
+ (0x5E00A000UL), /*!< CODE FLASH Page10 */
+ (0x5E00B000UL), /*!< CODE FLASH Page11 */
+ (0x5E00C000UL), /*!< CODE FLASH Page12 */
+ (0x5E00D000UL), /*!< CODE FLASH Page13 */
+ (0x5E00E000UL), /*!< CODE FLASH Page14 */
+ (0x5E00F000UL), /*!< CODE FLASH Page15 */
+ (0x5E010000UL), /*!< CODE FLASH Page16 */
+ (0x5E011000UL), /*!< CODE FLASH Page17 */
+ (0x5E012000UL), /*!< CODE FLASH Page18 */
+ (0x5E013000UL), /*!< CODE FLASH Page19 */
+ (0x5E014000UL), /*!< CODE FLASH Page20 */
+ (0x5E015000UL), /*!< CODE FLASH Page21 */
+ (0x5E016000UL), /*!< CODE FLASH Page22 */
+ (0x5E017000UL), /*!< CODE FLASH Page23 */
+ (0x5E018000UL), /*!< CODE FLASH Page24 */
+ (0x5E019000UL), /*!< CODE FLASH Page25 */
+ (0x5E01A000UL), /*!< CODE FLASH Page26 */
+ (0x5E01B000UL), /*!< CODE FLASH Page27 */
+ (0x5E01C000UL), /*!< CODE FLASH Page28 */
+ (0x5E01D000UL), /*!< CODE FLASH Page29 */
+ (0x5E01E000UL), /*!< CODE FLASH Page30 */
+ (0x5E01F000UL) /*!< CODE FLASH Page31 */
+};
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define
+ * @{
+ */
+/**
+ * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef
+ * @{
+ */
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Member */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables
+ * @{
+ */
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_variables */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions
+ * @{
+ */
+__STATIC_INLINE TXZ_Result fc_enable_areasel(void);
+__STATIC_INLINE TXZ_Result fc_disable_areasel(void);
+static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
+static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size);
+static TXZ_Result fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind);
+static TXZ_Result fc_blank_check(uint32_t* address, uint32_t size);
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enables the AREA0.
+ * @param -
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ * This function write the FCAREASEL regiset.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+__STATIC_INLINE TXZ_Result fc_enable_areasel(void)
+{
+ TXZ_Result retval = TXZ_ERROR;
+ /* Writes the FCKER register the KEYCODE. */
+ TSB_FC->KCR = FC_KCR_KEYCODE;
+
+ /* Selects the area0 */
+ {
+ uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
+ TSB_FC->AREASEL = reg | FC_AREASEL_AREA0;
+ }
+
+ /* Confirms the FCAREASEL register the SSF0 was set. */
+ while(1){
+ uint32_t i = TSB_FC->AREASEL;
+ if((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE){
+ retval = TXZ_SUCCESS;
+ break;
+ }
+ }
+
+ return(retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disables the AREA0.
+ * @param -
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ * This function write the FCAREASEL regiset.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+__STATIC_INLINE TXZ_Result fc_disable_areasel(void)
+{
+ TXZ_Result retval = TXZ_ERROR;
+
+ /* Writes the FCKER register the KEYCODE. */
+ TSB_FC->KCR = FC_KCR_KEYCODE;
+
+ /* Selects the area0 */
+ {
+ uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0;
+ TSB_FC->AREASEL = reg | FC_AREASEL_EXPECT_AREA0;
+ }
+
+ /* Confirms the SSF0 of the FCAREASEL register is not set. */
+ while(1){
+ uint32_t i = TSB_FC->AREASEL;
+ if((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE){
+ retval = TXZ_SUCCESS;
+ break;
+ }
+ }
+
+ return(retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Writes data of the Flash ROM.
+ * @param uint32_t* : src_address
+ * @param uint32_t* : dst_address
+ * @param uint32_t : size
+ * @return -
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+static void fc_write_command(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
+{
+ TXZ_Result retval;
+ /******** Changed/Added by TSIP next 12 lines *************/
+ volatile uint32_t* addr1;
+ volatile uint32_t* addr2;
+ if(dst_address <= (uint32_t *)0x0007FFFFUL) {
+ addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR);
+ addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR);
+ } else if(dst_address <= (uint32_t *)0x000FFFFF) {
+ addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x10000);
+ addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x10000);
+ } else {
+ addr1 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR + 0x100000);
+ addr2 = (uint32_t *) ((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR + 0x100000);
+ }
+ volatile uint32_t* addr3 = (uint32_t *) ((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP);
+ uint32_t* source = (uint32_t *) src_address;
+
+ /* Enables the AREA0. Write Mode. */
+ retval = fc_enable_areasel();
+
+ if(retval == TXZ_SUCCESS){
+ uint32_t i;
+
+ *addr1 = (0x000000AAUL); /* bus cycle 1 */
+ *addr2 = (0x00000055UL); /* bus cycle 2 */
+ *addr1 = (0x000000A0UL); /* bus cycle 3 */
+ for(i=(0UL); i<size; i+=(0x4UL)){
+ *addr3 = *source;
+ source++;
+ }
+
+ /* Confirmation of the works start of ROM. */
+ while(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
+ };
+
+ /* Waits for a finish of the works in the code Flash ROM. */
+ while(fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY){
+ };
+ }
+
+ /* Disables the AREA0. Read Mode. */
+ retval = fc_disable_areasel();
+ }
+
+/*--------------------------------------------------*/
+/**
+ * @brief Verifies data of the Flash ROM.
+ * @param uint32_t* : src_address
+ * @param uint32_t* : dst_address
+ * @param uint32_t : size
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+static TXZ_Result fc_verify_check(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
+{
+ TXZ_Result retval = TXZ_ERROR;
+ int res = memcmp(src_address, dst_address, size);
+ if(res == 0){
+ retval = TXZ_SUCCESS;
+ }
+
+ return(retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Auro page erase command of the flash ROM.
+ * @param uint32_t* flash_top_address : flash top address
+ * @param uint32_t* erase_top_address : erase top address
+ * @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc.
+ * @return -
+ * @note This function erases specified place of the flash ROM.
+ */
+/*--------------------------------------------------*/
+//TXZ_Result fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address)
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+static TXZ_Result fc_erase_command(uint32_t* flash_top_address, uint32_t* erase_top_address, fc_erase_kind_t kind)
+{
+ TXZ_Result retval;
+
+ /******** Changed/Added by TSIP next 12 lines *************/
+ volatile uint32_t *addr1;
+ volatile uint32_t *addr2;
+ if(erase_top_address <= (uint32_t *)0x5E07FFFFUL) {
+ addr1 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC1_ADDR);
+ addr2 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC2_ADDR);
+ } else if(erase_top_address <= (uint32_t *)0x5E0FFFFF) {
+ addr1 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC1_ADDR + 0x10000);
+ addr2 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC2_ADDR + 0x10000);
+ } else {
+ addr1 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC1_ADDR + 0x100000);
+ addr2 = (uint32_t *) ((uint32_t)flash_top_address + FC_CMD_BC2_ADDR + 0x100000);
+ }
+ volatile uint32_t *addr3 = (uint32_t *) erase_top_address;
+ /* Enables the AREA0. Write Mode. */
+ retval = fc_enable_areasel();
+ // printf("Areasel done\n\r");
+
+ if(retval == TXZ_SUCCESS){
+ *addr1 = (0x000000AAUL);
+ *addr2 = (0x00000055UL);
+ *addr1 = (0x00000080UL);
+ *addr1 = (0x000000AAUL);
+ *addr2 = (0x00000055UL);
+ *addr3 = kind;
+
+ /* Confirmation of the works start of ROM. */
+ while(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
+ };
+
+ /* Waits for a finish of the works in the code Flash ROM. */
+ while(fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY){
+ };
+ }
+
+ /* Disables the AREA0. Read Mode. */
+ retval = fc_disable_areasel();
+ return retval;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Checks a blank of the Flash ROM every 4bytes.
+ * @param uint32_t* : addrress
+ * @param uint32_t : size
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+static TXZ_Result fc_blank_check(uint32_t* address, uint32_t size)
+{
+ TXZ_Result retval = TXZ_SUCCESS;
+
+ uint32_t i;
+
+ for(i=0; i<(size/sizeof(uint32_t)); i++){
+ uint32_t* addr = &address[i];
+ if(*addr != FC_BRANK_VALUE){
+ retval = TXZ_ERROR;
+ break;
+ }
+ }
+
+ return (retval);
+}
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Private_fuctions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Get the status of the flash auto operation.
+ * @param fc_sr0_t : status
+ * @return Result.
+ * @retval TXZ_BUSY : Busy.
+ * @retval TXZ_DONE : Done.
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+TXZ_WorkState fc_get_status(fc_sr0_t status)
+{
+ TXZ_WorkState retval = TXZ_BUSY;
+ uint32_t work32;
+
+ /* Reads the FCSR0. Masks the other specfic status */
+ work32 = TSB_FC->SR0 & (uint32_t)status;
+
+ /* Confirms the specific status of the flash ROM */
+ if(work32 == (uint32_t)status){
+ retval = TXZ_DONE;
+ }
+
+ return (retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Auto write command of the code flash ROM.
+ * @param uint32_t* : src_address
+ * @param uint32_t* : dst_address
+ * @param uint32_t : size
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ * This function writes 16bytes data to the code Flash ROM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+TXZ_Result fc_write_code_flash(uint32_t* src_address, uint32_t* dst_address, uint32_t size)
+{
+ TXZ_Result retval = TXZ_SUCCESS;
+
+ /* Checks the code Flash ROM status */
+ if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
+
+ uint32_t i;
+ /* Checks the code Flash ROM status */
+ for(i=0;i<size;i+=(uint32_t)(0x10UL)){
+ /* Writes 16bytes data. */
+ fc_write_command((uint32_t*)((uint32_t)src_address+i), (uint32_t*)((uint32_t)dst_address+i), (uint32_t)(0x10UL));
+ }
+
+ /* Verifies user data and data of the Flash ROM. */
+ retval = fc_verify_check(src_address, dst_address, size);
+ }
+
+ return (retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Auro page erase command of the code flash ROM.
+ * @param first_page : The first page to erase
+ * @param num_of_pages : The number of pages to erase.
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ * This function erases specified page of the code Flash ROM and checks a blank.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages)
+{
+ TXZ_Result retval = TXZ_SUCCESS;
+
+ /* Checks the code Flash ROM status */
+ if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
+ /* Checks the number of maximum pages. */
+ if((first_page + num_of_pages) <= FC_MAX_PAGES){
+ uint8_t i;
+ for(i=0; i<num_of_pages ; i++){
+ /* Erases the specific page. */
+ fc_erase_command((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP,
+ (uint32_t*)fc_const_code_flash_address[first_page+i],
+ FC_ERASE_KIND_PAGE);
+ }
+ /* Checks a blank of the specific page. */
+ if(fc_blank_check((uint32_t*)fc_const_code_flash_address[first_page], FC_PAGE_SIZE*(uint32_t)num_of_pages) == TXZ_ERROR){
+ retval = TXZ_ERROR;
+ }
+ }
+ else{
+ retval = TXZ_ERROR;
+ }
+ }
+ else {
+ retval = TXZ_ERROR;
+ }
+
+ return (retval);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Checks a blank of the code Flash ROM of specified pages.
+ * @param first_page : The first page which checks a blank.
+ * @param last_page : The last page which checks a blank..
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page)
+{
+ TXZ_Result retval;
+
+ uint32_t* address = (uint32_t*)fc_const_code_flash_address[first_page];
+ uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE);
+
+ retval = fc_blank_check(address, size);
+
+ return (retval);
+}
+
+/*--------------------------------------------------*/
+/*************** written by TSIP ******************/
+/**
+ * @brief Erases the entire block of code Flash ROM of specified address.
+ * @param uint32_t *top_addr : top address of Flash ROM.
+ * @param uint32_t *blk_addr : start address of block to be erased.
+ * @return Result.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note It works in the inner RAM.
+ */
+/*--------------------------------------------------*/
+#if defined ( __GNUC__ ) /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+#if defined ( __ICCARM__ ) // IAR Compiler
+__ramfunc
+#endif
+TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr)
+{
+ TXZ_Result retval = TXZ_SUCCESS;
+ /* Checks the code Flash ROM status */
+ if(fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE){
+ /* Erases the specific block. */
+ fc_erase_command((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK);
+ /* Checks a blank of the specific block. */
+ if(fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR){
+ retval = TXZ_ERROR;
+ } else{
+ // do nothing
+ }
+ }
+ else {
+ retval = TXZ_ERROR;
+ }
+
+ return (retval);
+}
+
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group Flash_Userboot */
+
+/**
+ * @}
+ */ /* End of group Example */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_cg.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,492 @@
+/**
+ *******************************************************************************
+ * @file txz_cg.c
+ * @brief This file provides API functions for CG driver.
+ * @version V1.0.0.1
+ * $Date:: 2018-04-04 18:04:44 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_cg.h"
+
+#if defined(__CG_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup CG
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Private_define CG Private Define
+ * @{
+ */
+/* no define */
+/**
+ * @}
+ */ /* End of group CG_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Private_define CG Private Define
+ * @{
+ */
+#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */
+
+#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */
+#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */
+#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */
+#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */
+#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */
+
+#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */
+#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */
+#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */
+#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */
+#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */
+
+#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */
+
+#define CG_PRCK_1 ((uint32_t)0x00000000) /*!< CG ÓT0 fc register value */
+#define CG_PRCK_2 ((uint32_t)0x00000100) /*!< CG ÓT0 fc/2 register value */
+#define CG_PRCK_4 ((uint32_t)0x00000200) /*!< CG ÓT0 fc/4 register value */
+#define CG_PRCK_8 ((uint32_t)0x00000300) /*!< CG ÓT0 fc/8 register value */
+#define CG_PRCK_16 ((uint32_t)0x00000400) /*!< CG ÓT0 fc/16 register value */
+#define CG_PRCK_32 ((uint32_t)0x00000500) /*!< CG ÓT0 fc/32 register value */
+#define CG_PRCK_64 ((uint32_t)0x00000600) /*!< CG ÓT0 fc/64 register value */
+#define CG_PRCK_128 ((uint32_t)0x00000700) /*!< CG ÓT0 fc/128 register value */
+#define CG_PRCK_256 ((uint32_t)0x00000800) /*!< CG ÓT0 fc/256 register value */
+#define CG_PRCK_512 ((uint32_t)0x00000900) /*!< CG ÓT0 fc/512 register value */
+
+#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */
+
+#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG ÓT0 fc register status */
+#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG ÓT0 fc/2 register status */
+#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG ÓT0 fc/4 register status */
+#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG ÓT0 fc/8 register status */
+#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG ÓT0 fc/16 register status */
+#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG ÓT0 fc/32 register status */
+#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG ÓT0 fc/64 register status */
+#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG ÓT0 fc/128 register status */
+#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG ÓT0 fc/256 register status */
+#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG ÓT0 fc/512 register status */
+
+#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG ÓT0 fc division value */
+#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG ÓT0 fc/2 division value */
+#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG ÓT0 fc/4 division value */
+#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG ÓT0 fc/8 division value */
+#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG ÓT0 fc/16 division value */
+#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG ÓT0 fc/32 division value */
+#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG ÓT0 fc/64 division value */
+#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG ÓT0 fc/128 division value */
+#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG ÓT0 fc/256 division value */
+#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG ÓT0 fc/512 division value */
+
+
+#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */
+
+#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG ÓT0 fc/PRCK value */
+#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG ÓT0 fc/PRCK/2 value */
+#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG ÓT0 fc/PRCK/4 value */
+
+#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm ÓT0 division value */
+#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm ÓT0/2 division value */
+#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm ÓT0/4 division value */
+
+#define CG_IHOSC_DISABLE ((uint32_t)0x00000000) /*!< Internal high-speed oscillator disable */
+#define CG_IHOSC_ENABLE ((uint32_t)0x00000001) /*!< Internal high-speed oscillator enable */
+
+#define CG_IHOSC1EN ((uint32_t)0x00000000) /*!< CG OSCCR bit0 */
+
+#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */
+#define CG_MCKSELGST_1 ((uint32_t)0x00000000) /*!< CG fsysm fc/PRCK value */
+#define CG_MCKSELGST_2 ((uint32_t)0x00400000) /*!< CG fsysm fc/PRCK/2 value */
+#define CG_MCKSELGST_4 ((uint32_t)0x00800000) /*!< CG fsysm fc/PRCK/4 value */
+
+
+/**
+ * @}
+ */ /* End of group CG_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Private_define CG Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group CG_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Private_typedef CG Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group CG_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Private_fuctions CG Private Fuctions
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group CG_Private_functions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup CG_Exported_functions CG Exported Functions
+ * @{
+ */
+
+/*--------------------------------------------------*/
+/**
+ * @brief Update Middle PrescalerClock according register values.
+ * @param p_obj :CG object.
+ * @retval Middle PrescalerClock Frequency.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+uint32_t cg_get_fsysm(cg_t *p_obj)
+{
+ uint32_t result = 0U;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the CG_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /* System core clock update */
+ SystemCoreClockUpdate();
+
+ switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK)
+ {
+ case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */
+ result = SystemCoreClock / CG_FSYSM_1_DIV;
+ break;
+ case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */
+ result = SystemCoreClock / CG_FSYSM_2_DIV;
+ break;
+ case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */
+ result = SystemCoreClock / CG_FSYSM_4_DIV;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+ return (result);
+
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Update PrescalerClock according register values.
+ * @param p_obj :CG object.
+ * @retval PrescalerClock Frequency.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+uint32_t cg_get_phyt0(cg_t *p_obj)
+{
+ uint32_t result = 0U;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the CG_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /* System core clock update */
+ SystemCoreClockUpdate();
+
+ /* Get Gear status. */
+ switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK)
+ {
+ case CG_FSYS_1: /* Gear -> fc */
+ result = SystemCoreClock * CG_FSYS_1_MUL;
+ break;
+ case CG_FSYS_2: /* Gear -> fc/2 */
+ result = SystemCoreClock * CG_FSYS_2_MUL;
+ break;
+ case CG_FSYS_4: /* Gear -> fc/4 */
+ result = SystemCoreClock * CG_FSYS_4_MUL;
+ break;
+ case CG_FSYS_8: /* Gear -> fc/8 */
+ result = SystemCoreClock * CG_FSYS_8_MUL;
+ break;
+ case CG_FSYS_16: /* Gear -> fc/16 */
+ result = SystemCoreClock * CG_FSYS_16_MUL;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+
+ switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK)
+ {
+ case CG_PRCKST_1: /* ÓT0 -> fc */
+ result /= CG_PRCK_1_DIV;
+ break;
+ case CG_PRCKST_2: /* ÓT0 -> fc/2 */
+ result /= CG_PRCK_2_DIV;
+ break;
+ case CG_PRCKST_4: /* ÓT0 -> fc/4 */
+ result /= CG_PRCK_4_DIV;
+ break;
+ case CG_PRCKST_8: /* ÓT0 -> fc/8 */
+ result /= CG_PRCK_8_DIV;
+ break;
+ case CG_PRCKST_16: /* ÓT0 -> fc/16 */
+ result /= CG_PRCK_16_DIV;
+ break;
+ case CG_PRCKST_32: /* ÓT0 -> fc/32 */
+ result /= CG_PRCK_32_DIV;
+ break;
+ case CG_PRCKST_64: /* ÓT0 -> fc/64 */
+ result /= CG_PRCK_64_DIV;
+ break;
+ case CG_PRCKST_128: /* ÓT0 -> fc/128 */
+ result /= CG_PRCK_128_DIV;
+ break;
+ case CG_PRCKST_256: /* ÓT0 -> fc/256 */
+ result /= CG_PRCK_256_DIV;
+ break;
+ case CG_PRCKST_512: /* ÓT0 -> fc/512 */
+ result /= CG_PRCK_512_DIV;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Update Middle PrescalerClock according register values.
+ * @param p_obj :CG object.
+ * @retval Middle PrescalerClock Frequency.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+uint32_t cg_get_mphyt0(cg_t *p_obj)
+{
+ uint32_t result = 0U;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the CG_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /* System core clock update */
+ SystemCoreClockUpdate();
+
+ /* Get Gear status. */
+ switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK)
+ {
+ case CG_FSYS_1: /* Gear -> fc */
+ result = SystemCoreClock * CG_FSYS_1_MUL;
+ break;
+ case CG_FSYS_2: /* Gear -> fc/2 */
+ result = SystemCoreClock * CG_FSYS_2_MUL;
+ break;
+ case CG_FSYS_4: /* Gear -> fc/4 */
+ result = SystemCoreClock * CG_FSYS_4_MUL;
+ break;
+ case CG_FSYS_8: /* Gear -> fc/8 */
+ result = SystemCoreClock * CG_FSYS_8_MUL;
+ break;
+ case CG_FSYS_16: /* Gear -> fc/16 */
+ result = SystemCoreClock * CG_FSYS_16_MUL;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+ switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK)
+ {
+ case CG_PRCKST_1: /* ÓT0 -> fc */
+ result /= CG_PRCK_1_DIV;
+ break;
+ case CG_PRCKST_2: /* ÓT0 -> fc/2 */
+ result /= CG_PRCK_2_DIV;
+ break;
+ case CG_PRCKST_4: /* ÓT0 -> fc/4 */
+ result /= CG_PRCK_4_DIV;
+ break;
+ case CG_PRCKST_8: /* ÓT0 -> fc/8 */
+ result /= CG_PRCK_8_DIV;
+ break;
+ case CG_PRCKST_16: /* ÓT0 -> fc/16 */
+ result /= CG_PRCK_16_DIV;
+ break;
+ case CG_PRCKST_32: /* ÓT0 -> fc/32 */
+ result /= CG_PRCK_32_DIV;
+ break;
+ case CG_PRCKST_64: /* ÓT0 -> fc/64 */
+ result /= CG_PRCK_64_DIV;
+ break;
+ case CG_PRCKST_128: /* ÓT0 -> fc/128 */
+ result /= CG_PRCK_128_DIV;
+ break;
+ case CG_PRCKST_256: /* ÓT0 -> fc/256 */
+ result /= CG_PRCK_256_DIV;
+ break;
+ case CG_PRCKST_512: /* ÓT0 -> fc/512 */
+ result /= CG_PRCK_512_DIV;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+
+ switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK)
+ {
+ case CG_MCKSELPST_1: /* ÓT0 -> fc/PRCK */
+ result /= CG_FSYSM_1_DIV;
+ break;
+ case CG_MCKSELPST_2: /* ÓT0 -> fc/PRCK/2 */
+ result /= CG_FSYSM_2_DIV;
+ break;
+ case CG_MCKSELPST_4: /* ÓT0 -> fc/PRCK/4 */
+ result /= CG_FSYSM_4_DIV;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Internal high-speed oscillator enable.
+ * @param p_obj :CG object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result cg_ihosc_enable(cg_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the CG_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /* Internal high-speed oscillator is enable. */
+ (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_ENABLE;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Internal high-speed oscillator disable.
+ * @param p_obj :CG object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result cg_ihosc_disable(cg_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the CG_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /* Internal high-speed oscillator is disable. */
+ (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR,CG_IHOSC1EN))) = CG_IHOSC_DISABLE;
+
+ return (result);
+}
+/**
+ * @}
+ */ /* End of group CG_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group CG */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__CG_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_fuart.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1438 @@
+/**
+ *******************************************************************************
+ * @file txz_fuart.c
+ * @brief This file provides API functions for FUART driver.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-06 10:43:01 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_fuart_include.h"
+#include "txz_fuart.h"
+
+#if defined(__FUART_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup FUART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Private_define FUART Private Define
+ * @{
+ */
+
+/**
+ * @defgroup FUART_BourateConfig Bourate Setting Configuration
+ * @brief Bourate Setting Configuration.
+ * @{
+ */
+#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */
+#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */
+#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */
+
+#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */
+#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */
+#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */
+
+#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */
+#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */
+/**
+ * @}
+ */ /* End of group FUART_BourateConfig */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Private_define FUART Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Private_define FUART Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Private_typedef FUART Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup FUART_Private_fuctions FUART Private Fuctions
+ * @{
+ */
+#ifdef DEBUG
+ __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param);
+ __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param);
+ __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param);
+ __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param);
+ __STATIC_INLINE int32_t check_param_data_length(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_err_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rangeK(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rangeN(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param);
+#endif /* #ifdef DEBUG */
+#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE)
+ static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64);
+#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */
+
+#ifdef DEBUG
+/*--------------------------------------------------*/
+/**
+ * @brief Check the CTS Handshake's parameter.
+ * @param param :CTS Handshake's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_CTS_DISABLE:
+ case FUART_CTS_ENABLE:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the RTS Handshake's parameter.
+ * @param param :RTS Handshake's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_RTS_DISABLE:
+ case FUART_RTS_ENABLE:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Stop Bit's parameter.
+ * @param param :Stop Bit's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_STOP_BIT_1:
+ case FUART_STOP_BIT_2:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Bit's parameter.
+ * @param param :Parity Bit's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_PARITY_BIT_ODD:
+ case FUART_PARITY_BIT_EVEN:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Enable's parameter.
+ * @param param :Parity Enable's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_PARITY_DISABLE:
+ case FUART_PARITY_ENABLE:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Length's parameter.
+ * @param param :Data Length's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_data_length(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_DATA_LENGTH_5:
+ case FUART_DATA_LENGTH_6:
+ case FUART_DATA_LENGTH_7:
+ case FUART_DATA_LENGTH_8:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Fill Level Range's parameter.
+ * @param param :Tx Fill Level Range's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_FIFO_LEVEL_4:
+ case FUART_FIFO_LEVEL_8:
+ case FUART_FIFO_LEVEL_16:
+ case FUART_FIFO_LEVEL_24:
+ case FUART_FIFO_LEVEL_28:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Fill Level's parameter.
+ * @param param :Rx Fill Level's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_FIFO_LEVEL_4:
+ case FUART_FIFO_LEVEL_8:
+ case FUART_FIFO_LEVEL_16:
+ case FUART_FIFO_LEVEL_24:
+ case FUART_FIFO_LEVEL_28:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Interrpt's parameter.
+ * @param param :Tx Interrpt's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_int(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_TX_INT_DISABLE:
+ case FUART_TX_INT_ENABLE:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Interrpt's parameter.
+ * @param param :Rx Interrpt's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_int(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ switch (param)
+ {
+ case FUART_RX_INT_DISABLE:
+ case FUART_RX_INT_ENABLE:
+ result = FUART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Error Interrpt's parameter.
+ * @param param :Error Interrpt's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_err_int(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE);
+
+ if(param == 0){
+ result = FUART_PARAM_OK;
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Range K's parameter.
+ * @param param :Range K's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rangeK(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ /*--- Now, FUART_RANGE_K_MIN is 0. ---*/
+#if 0
+ if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX))
+#else
+ if (param <= FUART_RANGE_K_MAX)
+#endif
+ {
+ result = FUART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Range N's parameter.
+ * @param param :Range N's parameter
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rangeN(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX))
+ {
+ result = FUART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the num of buff for transmit.
+ * @param param :Num of buff.
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ if (param != 0)
+ {
+ result = FUART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the num of buff for receive.
+ * @param param :Num of buff.
+ * @retval FUART_PARAM_OK :Valid
+ * @retval FUART_PARAM_NG :Invalid
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param)
+{
+ int32_t result = FUART_PARAM_NG;
+
+ if (param != 0)
+ {
+ result = FUART_PARAM_OK;
+ }
+
+ return (result);
+}
+#endif /* #ifdef DEBUG */
+
+#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE)
+/*--------------------------------------------------*/
+/**
+ * @brief Check the within error margin.
+ * @param boudrate :Boudrate(bps).
+ * @param clock :Clock(hz).
+ * @param boudrate :Boudrate(bps).
+ * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX"
+ * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX"
+ * @param p_range64 :Error range(after fixed point bit shift).
+ * @retval TXZ_SUCCESS :Within error margin.
+ * @retval TXZ_ERROR :Without error margin.
+ * @note For N+(64-K)/64 division.
+ */
+/*--------------------------------------------------*/
+static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64)
+{
+ TXZ_Result result = TXZ_ERROR;
+ uint64_t boud64 = 0;
+ uint64_t tx64 = 0;
+ uint64_t work64 = 0;
+
+ /* phi T0 */
+ tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT+2));
+
+ /* Bourate */
+ boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT);
+ *p_range64 = ((boud64/100)*FUART_CFG_BOUDRATE_ERROR_RANGE);
+ /* BourateX */
+ work64 = (uint64_t)((uint64_t)n << 6);
+ work64 = (uint64_t)(work64 + (uint64_t)k);
+ work64 = (tx64 / work64);
+ if (boud64 >= *p_range64)
+ {
+ if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64)))
+ {
+ if( boud64 < work64 )
+ {
+ *p_range64 = (work64 - boud64);
+ }
+ else
+ {
+ *p_range64 = (boud64 - work64);
+ }
+ result = TXZ_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_functions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Initialize the FUART object.
+ * @param p_obj :FUART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_init(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(check_param_rangeK(p_obj->init.boudrate.brk));
+ assert_param(check_param_rangeN(p_obj->init.boudrate.brn));
+ assert_param(check_param_tx_int(p_obj->init.tx_int.inttx));
+ assert_param(check_param_rx_int(p_obj->init.rx_int.intrx));
+ assert_param(check_param_err_int(p_obj->init.interr));
+ assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level));
+ assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level));
+ assert_param(check_param_cts_handshake(p_obj->init.ctse));
+ assert_param(check_param_rts_handshake(p_obj->init.rtse));
+ assert_param(check_param_stop_bit(p_obj->init.sblen));
+ assert_param(check_param_parity_bit(p_obj->init.even));
+ assert_param(check_param_parity_enable(p_obj->init.pe));
+ assert_param(check_param_data_length(p_obj->init.sm));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable FUART */
+ /*------------------------------*/
+ p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE |
+ FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE);
+ /*------------------------------*/
+ /* Interrupt Disable */
+ /*------------------------------*/
+ p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE |
+ FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE |
+ FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE);
+ /*------------------------------*/
+ /* Interrupt Clear */
+ /*------------------------------*/
+ p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR |
+ FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR |
+ FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR);
+
+ /*------------------------------*/
+ /* FIFO Disable */
+ /*------------------------------*/
+ p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE);
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ p_obj->p_instance->BRD = p_obj->init.boudrate.brn;
+ p_obj->p_instance->FBRD = p_obj->init.boudrate.brk;
+ p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm |
+ p_obj->init.fifo | p_obj->init.sblen |
+ p_obj->init.even | p_obj->init.pe);
+ p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level);
+ p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx);
+ p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Release the FUART object.
+ * @param p_obj :FUART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_deinit(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable FUART */
+ /*------------------------------*/
+ p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE |
+ FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE);
+ /*------------------------------*/
+ /* Interrupt Disable */
+ /*------------------------------*/
+ p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE |
+ FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE |
+ FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE);
+ /*------------------------------*/
+ /* Interrupt Clear */
+ /*------------------------------*/
+ p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR |
+ FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR |
+ FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR);
+ /*------------------------------*/
+ /* FIFO Disable */
+ /*------------------------------*/
+ p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard transmit.
+ * @param p_obj :FUART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears transmit's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_discard_transmit(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ disable_FUARTxCR_TXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Interrupt Clear */
+ /*------------------------------*/
+ p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard receive.
+ * @param p_obj :FUART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears receive's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_discard_receive(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ disable_FUARTxCR_RXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Interrupt Clear */
+ /*------------------------------*/
+ p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Transmit data. Non-Blocking Communication.
+ * @param p_obj :FUART object.
+ * @param p_info :The information of transmit data.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Asynchronous Processing.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ assert_param(IS_POINTER_NOT_NULL(p_info->p_data));
+ assert_param(check_param_tx_buff_num(p_info->num));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- FUARTxCR ---*/
+ /* Write to TXE(=0). */
+ /* Bitband Access. */
+ disable_FUARTxCR_TXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ p_obj->transmit.rp = 0;
+ p_obj->transmit.info.p_data = p_info->p_data;
+ p_obj->transmit.info.num = p_info->num;
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ {
+ volatile uint32_t fr_reg;
+
+ fr_reg = p_obj->p_instance->FR;
+ while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET)
+ {
+ /*=== Transmit Continue ===*/
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ /*--- FUARTxDR ---*/
+ if (p_obj->transmit.info.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else{
+ break;
+ }
+ fr_reg = p_obj->p_instance->FR;
+ }
+ }
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- FUARTxCR ---*/
+ /* Write to TXE(=1). */
+ /* Bitband Access. */
+ enable_FUARTxCR_TXE(p_obj->p_instance);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Receive data. Non-Blocking Communication.
+ * @param p_obj :FUART object.
+ * @param p_info :The information of receive buffer.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Asynchronous Processing.
+ * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ volatile uint8_t dummy;
+ volatile uint32_t fr_reg;
+ uint32_t rx_count = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ assert_param(IS_POINTER_NOT_NULL(p_info->p_data));
+ assert_param(check_param_rx_buff_num(p_info->num));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /* Write to RXE(=0). */
+ /* Bitband Access. */
+ disable_FUARTxCR_RXE(p_obj->p_instance);
+ /* FIFO CLR */
+ fr_reg = p_obj->p_instance->FR;
+ while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR)
+ {
+ dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK);
+ if(p_obj->init.fifo == 1)
+ {
+ if(++rx_count > FUART_RX_FIFO_MAX)
+ {
+ break;
+ }
+ }
+ else{
+ if(++rx_count > 1)
+ {
+ break;
+ }
+ }
+ fr_reg = p_obj->p_instance->FR;
+ }
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ p_obj->receive.wp = 0;
+ p_obj->receive.info.p_data = p_info->p_data;
+ p_obj->receive.info.num = p_info->num;
+ /*------------------------------*/
+ /* Enable Receive */
+ /*------------------------------*/
+ /*--- FUARTxCR ---*/
+ /* Write to RXE(=1). */
+ /* Bitband Access. */
+ enable_FUARTxCR_RXE(p_obj->p_instance);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for transmit.
+ * @param p_obj :FUART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void fuart_transmit_irq_handler(fuart_t *p_obj)
+{
+ uint32_t cr_reg;
+ volatile uint32_t fr_reg;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current FUARTxCR */
+ cr_reg = p_obj->p_instance->CR;
+ /*------------------------------*/
+ /* Transmit Status Check */
+ /*------------------------------*/
+ if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE)
+ {
+ if (p_obj->transmit.info.num <= p_obj->transmit.rp)
+ {
+ /*=== Transmit Done!! ===*/
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- FUARTxCR ---*/
+ /* Write to TXE(=0). */
+ /* Bitband Access. */
+ /* disable_FUARTxCR_TXE(p_obj->p_instance); */
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->transmit.handler != FUART_NULL)
+ {
+ /* Call the transmit handler with TXZ_SUCCESS. */
+ p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS);
+ }
+ }
+ else
+ {
+ fr_reg = p_obj->p_instance->FR;
+ while((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET)
+ {
+ /*=== Transmit Continue ===*/
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ /*--- FUARTxDR ---*/
+ if (p_obj->transmit.info.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else{
+ break;
+ }
+ fr_reg = p_obj->p_instance->FR;
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for receive.
+ * @param p_obj :FUART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void fuart_receive_irq_handler(fuart_t *p_obj)
+{
+ uint32_t cr_reg;
+ volatile uint32_t fr_reg;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current FUARTxCR */
+ cr_reg = p_obj->p_instance->CR;
+ /*------------------------------*/
+ /* Receive Status Check */
+ /*------------------------------*/
+ if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE)
+ {
+ uint32_t rx_count = 0;
+
+ fr_reg = p_obj->p_instance->FR;
+ while((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR)
+ {
+ *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK);
+ p_obj->receive.wp += 1;
+ if(p_obj->receive.wp >= p_obj->receive.info.num)
+ {
+ break;
+ }
+ if(p_obj->init.fifo == 1)
+ {
+ if(++rx_count >= FUART_RX_FIFO_MAX)
+ {
+ break;
+ }
+ }
+ else{
+ break;
+ }
+ fr_reg = p_obj->p_instance->FR;
+ }
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if(p_obj->receive.wp >= p_obj->receive.info.num)
+ {
+ if(p_obj->receive.handler != FUART_NULL)
+ {
+ fuart_receive_t param;
+ param.p_data = p_obj->receive.info.p_data;
+ param.num = p_obj->receive.wp;
+ p_obj->receive.wp = 0;
+ /* Call the receive handler with TXZ_SUCCESS. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m);
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for error.
+ * @param p_obj :FUART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void fuart_error_irq_handler(fuart_t *p_obj)
+{
+ uint32_t cr_reg;
+ uint32_t error;
+ uint32_t ecr_reg = 0x00;
+ uint32_t icr_reg = 0x00;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current FUARTxCR */
+ cr_reg = p_obj->p_instance->CR;
+ /*------------------------------*/
+ /* Error Registar Control */
+ /*------------------------------*/
+ /* Read current FUARTxRSR. */
+ error = p_obj->p_instance->RSR;
+ /* Now, no clear the error flag. */
+ /*------------------------------*/
+ /* Error Check */
+ /*------------------------------*/
+ /*--- FUARTxRSR ---*/
+ /* Check the receive error. */
+ {
+ TXZ_Result err = TXZ_SUCCESS;
+ /* OVER RUN */
+ if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR)
+ {
+ volatile uint8_t dummy;
+
+ icr_reg |= FUARTxICR_OEIC_CLR;
+ ecr_reg |= FUARTxECR_OE_CLR;
+ dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK);
+ err = TXZ_ERROR;
+ }
+ /* BREAK */
+ if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR)
+ {
+ icr_reg |= FUARTxICR_BEIC_CLR;
+ ecr_reg |= FUARTxECR_BE_CLR;
+ err = TXZ_ERROR;
+ }
+ /* PARITY */
+ if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR)
+ {
+ icr_reg |= FUARTxICR_PEIC_CLR;
+ ecr_reg |= FUARTxECR_PE_CLR;
+ err = TXZ_ERROR;
+ }
+ /* FRAMING */
+ if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR)
+ {
+ icr_reg |= FUARTxICR_FEIC_CLR;
+ ecr_reg |= FUARTxECR_FE_CLR;
+ err = TXZ_ERROR;
+ }
+ if (err == TXZ_ERROR)
+ {
+ p_obj->p_instance->ICR = icr_reg;
+ p_obj->p_instance->ECR = ecr_reg;
+ /*------------------------------*/
+ /* Receive Check */
+ /*------------------------------*/
+ if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE)
+ {
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- FUARTxCR ---*/
+ /* Write to RXE(=0). */
+ /* Bitband Access. */
+ disable_FUARTxCR_RXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != FUART_NULL)
+ {
+ /* Call the receive handler with TXZ_ERROR. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL);
+ }
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for timeout error.
+ * @param p_obj :FUART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void fuart_timeout_error_irq_handler(fuart_t *p_obj)
+{
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != FUART_NULL)
+ {
+ /* Call the receive handler with TXZ_ERROR. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL);
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler .
+ * @param p_obj :FUART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void fuart_irq_handler(fuart_t *p_obj)
+{
+ uint32_t interrupt_status = p_obj->p_instance->MIS;
+ if((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ)
+ {
+ p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK;
+ fuart_receive_irq_handler(p_obj);
+ }
+ if((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ)
+ {
+ p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK;
+ fuart_transmit_irq_handler(p_obj);
+ }
+ if((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0)
+ {
+ p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK);
+ fuart_error_irq_handler(p_obj);
+ }
+ if((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0)
+ {
+ p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK;
+ fuart_timeout_error_irq_handler(p_obj);
+ }
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get status.
+ * @details Status bits.
+ * | Bit | Bit Symbol | Function |
+ * | 31-8 | - | - |
+ * | 7 | TXFE | Transmit FIFO Empty Flag. |
+ * | 6 | RXFF | Reach Receive Fill Level Flag. |
+ * | 5 | TXFF | Reach Transmit Fill Level Flag. | |
+ * | 4 | RXFE | Receive FIFO Empty Flag. |
+ * | 3 | BUSY | Transmit BUSY Flag. |
+ * | 2-1 | - | - |
+ * | 0 | CTS | FUTxCTS Flag. |
+ *
+ * @param p_obj :FUART object.
+ * @param p_status :Save area for status.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_status));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Status Read */
+ /*------------------------------*/
+ /*--- FUARTxFR ---*/
+ /* Read current FUARTxFR. */
+ *p_status = p_obj->p_instance->FR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get error information.
+ * @details Error bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-4 | - | - |
+ * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. |
+ * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. |
+ * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. |
+ * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. |
+ *
+ * @param p_obj :FUART object.
+ * @param p_error :Save area for error.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_error));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Error Read */
+ /*------------------------------*/
+ /*--- FUARTxRSR ---*/
+ /* Read current FUARTxRSR. */
+ *p_error = p_obj->p_instance->RSR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get the setting of boudrate.
+ * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B".
+ * @param boudrate :Boudrate(bps).
+ * @param p_brd :Save area for Division Setting.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Not support setting.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd)
+{
+ TXZ_Result result = TXZ_ERROR;
+#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE)
+ uint64_t tx = 0;
+ uint64_t work = 0;
+ uint64_t range64 = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_brd));
+ /* Check the parameter of FUARTxCLK. */
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Calculate Division Setting */
+ /*------------------------------*/
+ if ((clock > 0) && (boudrate > 0))
+ {
+ /*--- phi T0 ---*/
+ tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT);
+
+ /*--- N+(K/64) division ---*/
+ {
+ uint8_t k = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+
+ work = ((uint64_t)boudrate);
+ tx /= work;
+ tx >>= 4;
+ for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++)
+ {
+ work = tx - (uint64_t)k;
+ work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */
+ if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX))
+ {
+ uint64_t workRange = 0;
+ /* Verification */
+ if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS)
+ {
+#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL)
+ /* Compare the previous range. */
+ if (result == TXZ_SUCCESS)
+ {
+ if (range64 > workRange)
+ {
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ range64 = workRange;
+ }
+ }
+ else
+ {
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ range64 = workRange;
+ }
+ result = TXZ_SUCCESS;
+#else
+ /* Finish!! */
+ if (result == TXZ_SUCCESS)
+ {
+ if (range64 > workRange)
+ {
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ }
+ }
+ else
+ {
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ }
+ result = TXZ_SUCCESS;
+ loopBreak = TXZ_DONE;
+#endif
+ }
+ }
+ }
+ }
+ }
+#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */
+
+ return (result);
+}
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group FUART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__UART_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_fuart_ex.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,206 @@
+/**
+ *******************************************************************************
+ * @file txz_fuart_ex.c
+ * @brief This file provides API functions for FUART driver.
+ * @brief Extended functionality.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-06 10:43:01 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_fuart_include.h"
+#include "txz_fuart_ex.h"
+
+#if defined(__FUART_EX_H)
+
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup UART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Private_fuctions
+ * @{
+ */
+
+/**
+ * @}
+ */ /* End of group FUART_Private_functions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup FUART_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Send Break.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_send_break(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Set Break */
+ /*------------------------------*/
+ {
+ uint32_t trans = p_obj->p_instance->LCR_H;
+
+ trans &= ~FUARTxLCR_H_BRK_MASK;
+ trans |= FUARTxLCR_H_BRK_SEND;
+ p_obj->p_instance->LCR_H = trans;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Stop Break.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result fuart_stop_break(fuart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the FUART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Set Break */
+ /*------------------------------*/
+ {
+ uint32_t trans = p_obj->p_instance->LCR_H;
+
+ trans &= ~FUARTxLCR_H_BRK_MASK;
+ trans |= FUARTxLCR_H_BRK_STOP;
+ p_obj->p_instance->LCR_H = trans;
+ }
+
+ return (result);
+}
+
+
+/**
+ * @}
+ */ /* End of group FUART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group FUART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__UART_EX_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_gpio.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,4751 @@
+/**
+ *******************************************************************************
+ * @file txz_gpio.c
+ * @brief This file provides API functions for GPIO driver.
+ * @version V1.0.0.2
+ * $Date:: 2018-04-11 14:13:48 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_gpio.h"
+
+#if defined(__GPIO_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup GPIO
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Private_define GPIO Private Define
+ * @{
+ */
+/**
+ * @name Parameter Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of name Parameter Result */
+
+/**
+ * @name Bit Operation Macro
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */
+#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */
+#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */
+#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */
+#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */
+#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */
+#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)(0x0000001UL<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */
+/**
+ * @}
+ */ /* End of Bit Operation Macro */
+/**
+ * @}
+ */ /* End of group GPIO_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Private_define GPIO Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group GPIO_Private_define */
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Private_typedef GPIO Private Typedef
+ * @{
+ */
+/*!
+ * @brief Pin Exist Table
+ * @details Bit0 :GPIO_Mode_DATA
+ * @details Bit1 :GPIO_Mode_CR
+ * @details Bit2 :GPIO_Mode_FR1
+ * @details Bit3 :GPIO_Mode_FR2
+ * @details Bit4 :GPIO_Mode_FR3
+ * @details Bit5 :GPIO_Mode_FR4
+ * @details Bit6 :GPIO_Mode_FR5
+ * @details Bit7 :GPIO_Mode_FR6
+ * @details Bit8 :GPIO_Mode_FR7
+ * @details Bit9 :GPIO_Mode_OD
+ * @details Bit10 :GPIO_Mode_PUP
+ * @details Bit11 :GPIO_Mode_PDN
+ * @details Bit12 :GPIO_Mode_IE
+ */
+#if defined(TMPM4G6)
+static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] =
+{
+ /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */
+ { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */
+ { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */
+ { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */
+ { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */
+ { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x0000, 0x0000, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */
+ { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */
+ { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */
+ { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */
+ { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */
+ { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */
+ { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */
+ { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_T */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_V */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */
+ { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */
+};
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] =
+{
+ /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */
+ { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */
+ { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */
+ { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_C */
+ { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */
+ { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */
+ { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */
+ { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */
+ { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */
+ { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */
+ { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */
+ { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */
+ { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */
+ { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_R */
+ { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */
+ { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */
+ { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */
+};
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] =
+{
+ /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */
+ { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */
+ { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */
+ { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */
+ { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */
+ { 0x1F7F, 0x1E07, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */
+ { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */
+ { 0x1E57, 0x1E57, 0x1E03, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */
+ { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_J */
+ { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */
+ { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_L */
+ { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */
+ { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */
+ { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */
+ { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */
+ { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_U */
+ { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */
+ { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_W */
+ { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */
+};
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] =
+{
+ /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */
+ { 0x1FDF, 0x1F57, 0x1F17, 0x1FDF, 0x1FDF, 0x1FD7, 0x1F97, 0x1FDF }, /** GPIO_PORT_A */
+ { 0x1E5F, 0x1EDF, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E5F, 0x1E5F }, /** GPIO_PORT_B */
+ { 0x1E57, 0x1E57, 0x1E57, 0x1E17, 0x1E57, 0x1E17, 0x1E07, 0x1E07 }, /** GPIO_PORT_C */
+ { 0x1FFF, 0x1F7F, 0x1F77, 0x1F37, 0x1F57, 0x1F17, 0x1F5F, 0x1F5F }, /** GPIO_PORT_D */
+ { 0x1F7F, 0x1F47, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F77, 0x1F7F }, /** GPIO_PORT_E */
+ { 0x1E07, 0x1E07, 0x1F03, 0x1F03, 0x1E07, 0x1E07, 0x1E07, 0x1E07 }, /** GPIO_PORT_F */
+ { 0x1E57, 0x1E57, 0x1F13, 0x1F7B, 0x1F6B, 0x1F7B, 0x1E67, 0x1E67 }, /** GPIO_PORT_G */
+ { 0x1E77, 0x1E77, 0x1E73, 0x1E73, 0x1E57, 0x1E47, 0x1E47, 0x1E47 }, /** GPIO_PORT_H */
+ { 0x1E53, 0x1E53, 0x1F53, 0x1F53, 0x1E5B, 0x1E5B, 0x1F43, 0x1F43 }, /** GPIO_PORT_J */
+ { 0x1F9F, 0x1E3F, 0x1E8F, 0x1E8F, 0x1EA7, 0x1EA7, 0x1EBF, 0x1DBB }, /** GPIO_PORT_K */
+ { 0x1F9B, 0x1F03, 0x1F03, 0x1F9B, 0x1E1B, 0x1E0B, 0x1E1B, 0x1E0F }, /** GPIO_PORT_L */
+ { 0x1FE3, 0x1FE3, 0x1FDB, 0x1FEB, 0x1FAB, 0x1F9B, 0x1FFB, 0x1FEB }, /** GPIO_PORT_M */
+ { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_N */
+ { 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B, 0x1E5B }, /** GPIO_PORT_P */
+ { 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B, 0x1E1B }, /** GPIO_PORT_R */
+ { 0x1E03, 0x1E03, 0x1F03, 0x1EDF, 0x1E23, 0x1E0B, 0x0000, 0x0000 }, /** GPIO_PORT_T */
+ { 0x1F1B, 0x1F0B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F1B, 0x1F0B }, /** GPIO_PORT_U */
+ { 0x1FFB, 0x1FFB, 0x1FFB, 0x1FEB, 0x1FEB, 0x1FFB, 0x1F7B, 0x1FEB }, /** GPIO_PORT_V */
+ { 0x1EE3, 0x1F63, 0x1F63, 0x1E63, 0x1FD3, 0x1FC3, 0x1FC3, 0x1FD3 }, /** GPIO_PORT_W */
+ { 0x1C01, 0x1C01, 0x1C01, 0x1C01, 0x1E27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_Y */
+};
+#endif /* TMPM4G9 */
+
+/**
+ * @}
+ */ /* End of group GPIO_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup GPIO_Private_fuctions GPIO Private Fuctions
+ * @{
+ */
+
+static uint8_t change_mode_to_num( uint32_t mode );
+static uint8_t change_func_to_num( uint32_t mode );
+static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode);
+static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode);
+/*--------------------------------------------------*/
+/*!
+ * @fn static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode)
+ * @brief Check the Pin Exist.
+ * @param[in] p_obj :GPIO object.
+ * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ */
+/*--------------------------------------------------*/
+
+static uint8_t change_mode_to_num( uint32_t mode )
+{
+ uint8_t retVal = 0;
+
+ if (mode == GPIO_Mode_DATA) {retVal = 0;}
+ else if (mode == GPIO_Mode_CR) {retVal = 1;}
+ else if (mode == GPIO_Mode_FR1) {retVal = 2;}
+ else if (mode == GPIO_Mode_FR2) {retVal = 3;}
+ else if (mode == GPIO_Mode_FR3) {retVal = 4;}
+ else if (mode == GPIO_Mode_FR4) {retVal = 5;}
+ else if (mode == GPIO_Mode_FR5) {retVal = 6;}
+ else if (mode == GPIO_Mode_FR6) {retVal = 7;}
+ else if (mode == GPIO_Mode_FR7) {retVal = 8;}
+ else if (mode == GPIO_Mode_OD) {retVal = 9;}
+ else if (mode == GPIO_Mode_PUP) {retVal = 10;}
+ else if (mode == GPIO_Mode_PDN) {retVal = 11;}
+ else if (mode == GPIO_Mode_IE) {retVal = 12;}
+ else {retVal = 13;}
+
+ return retVal;
+}
+
+static uint8_t change_func_to_num( uint32_t mode )
+{
+ uint8_t retVal = 0;
+
+ if (mode == GPIO_FR_1) {retVal = 2;}
+ else if (mode == GPIO_FR_2) {retVal = 3;}
+ else if (mode == GPIO_FR_3) {retVal = 4;}
+ else if (mode == GPIO_FR_4) {retVal = 5;}
+ else if (mode == GPIO_FR_5) {retVal = 6;}
+ else if (mode == GPIO_FR_6) {retVal = 7;}
+ else if (mode == GPIO_FR_7) {retVal = 8;}
+ else if (mode == GPIO_FR_NA) {retVal = 1;}
+ else if (mode == 0) {retVal = 1;}
+ else {retVal = 13;}
+
+ return retVal;
+}
+
+static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode)
+{
+ int32_t result = PARAM_NG;
+ uint8_t chgmode;
+ uint16_t tmp;
+
+ chgmode = change_mode_to_num(mode);
+ if ((chgmode < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max))
+ {
+ tmp = (PinExistTbl[group][num] >> chgmode) & 0x01;
+ result = PARAM_OK;
+ if (tmp == 0){ result = PARAM_NG;}
+ }
+ else
+ {
+ result = PARAM_NG;
+ }
+
+ return (result);
+}
+static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode)
+{
+ int32_t result = PARAM_NG;
+ uint8_t chgfunc;
+ uint16_t tmp;
+
+ chgfunc = change_func_to_num(mode);
+ /* param check skip if func is INPUT or OUTPUT */
+ if(chgfunc == 1)
+ {
+ return (PARAM_OK);
+ }
+ if ((chgfunc < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max))
+ {
+ tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01;
+ result = PARAM_OK;
+ if (tmp == 0){ result = PARAM_NG;}
+ }
+ else
+ {
+ result = PARAM_NG;
+ }
+
+ return (result);
+}
+/**
+ * @}
+ */ /* End of group GPIO_Private_functions */
+
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup GPIO_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group)
+ * @brief Initialize the GPIO object.
+ * @param[in] p_obj :GPIO object.
+ * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /* Check the NULL of address. */
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ switch (group)
+ {
+#if defined(TMPM4G6)
+ case GPIO_PORT_A:
+ /* PA Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB02 = 1U;
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_B:
+ /* PB Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB03 = 1U;
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_D:
+ /* PD Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB05 = 1U;
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_E:
+ /* PE Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB06 = 1U;
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_F:
+ /* PF Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB07= 1U;
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_G:
+ /* PG Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB08 = 1U;
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_H:
+ /* PH Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB09 = 1U;
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF8;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ break;
+ case GPIO_PORT_K:
+ /* PK Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB11 = 1U;
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_L:
+ /* PL Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB12 = 1U;
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_N:
+ /* PN Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB14 = 1U;
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_P:
+ /* PP Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB15 = 1U;
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_T:
+ /* PT Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB16 = 1U;
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_Y:
+ /* PY Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB21 = 1U;
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ break;
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+ case GPIO_PORT_A:
+ /* PA Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB02 = 1U;
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_B:
+ /* PB Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB03 = 1U;
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_C:
+ /* PC Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB04 = 1U;
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_D:
+ /* PD Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB05 = 1U;
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_E:
+ /* PE Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB06 = 1U;
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_F:
+ /* PF Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB07= 1U;
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_G:
+ /* PG Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB08 = 1U;
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_H:
+ /* PH Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB09 = 1U;
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF8;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ break;
+ case GPIO_PORT_K:
+ /* PK Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB11 = 1U;
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_L:
+ /* PL Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB12 = 1U;
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_N:
+ /* PN Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB14 = 1U;
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_P:
+ /* PP Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB15 = 1U;
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_R:
+ /* PR Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB16 = 1U;
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_T:
+ /* PT Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB17 = 1U;
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_V:
+ /* PV Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB19 = 1U;
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_Y:
+ /* PY Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB21 = 1U;
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ break;
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+ case GPIO_PORT_A:
+ /* PA Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB02 = 1U;
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_B:
+ /* PB Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB03 = 1U;
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_C:
+ /* PC Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB04 = 1U;
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_D:
+ /* PD Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB05 = 1U;
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_E:
+ /* PE Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB06 = 1U;
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_F:
+ /* PF Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB07= 1U;
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_G:
+ /* PG Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB08 = 1U;
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_H:
+ /* PH Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB09 = 1U;
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF8;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ break;
+ case GPIO_PORT_K:
+ /* PK Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB11 = 1U;
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_L:
+ /* PL Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB12 = 1U;
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_M:
+ /* PM Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB13 = 1U;
+ p_obj->p_pm_instance->DATA = 0x00;
+ p_obj->p_pm_instance->CR = 0x00;
+ p_obj->p_pm_instance->FR2 = 0x00;
+ p_obj->p_pm_instance->FR3 = 0x00;
+ p_obj->p_pm_instance->FR4 = 0x00;
+ p_obj->p_pm_instance->FR5 = 0x00;
+ p_obj->p_pm_instance->FR6 = 0x00;
+ p_obj->p_pm_instance->FR7 = 0x00;
+ p_obj->p_pm_instance->OD = 0x00;
+ p_obj->p_pm_instance->PUP = 0x00;
+ p_obj->p_pm_instance->PDN = 0x00;
+ p_obj->p_pm_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_N:
+ /* PN Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB14 = 1U;
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_P:
+ /* PP Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB15 = 1U;
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_R:
+ /* PR Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB16 = 1U;
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_T:
+ /* PT Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB17 = 1U;
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_V:
+ /* PV Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB19 = 1U;
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_Y:
+ /* PY Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB21 = 1U;
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ break;
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+ case GPIO_PORT_A:
+ /* PA Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB02 = 1U;
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_B:
+ /* PB Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB03 = 1U;
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_C:
+ /* PC Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB04 = 1U;
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_D:
+ /* PD Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB05 = 1U;
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_E:
+ /* PE Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB06 = 1U;
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_F:
+ /* PF Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB07= 1U;
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_G:
+ /* PG Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB08 = 1U;
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_H:
+ /* PH Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB09 = 1U;
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF8;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ break;
+ case GPIO_PORT_J:
+ /* PJ Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB10 = 1U;
+ p_obj->p_pj_instance->DATA = 0x00;
+ p_obj->p_pj_instance->CR = 0x00;
+ p_obj->p_pj_instance->FR2 = 0x00;
+ p_obj->p_pj_instance->FR3 = 0x00;
+ p_obj->p_pj_instance->FR5 = 0x00;
+ p_obj->p_pj_instance->FR7 = 0x00;
+ p_obj->p_pj_instance->OD = 0x00;
+ p_obj->p_pj_instance->PUP = 0x00;
+ p_obj->p_pj_instance->PDN = 0x00;
+ p_obj->p_pj_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_K:
+ /* PK Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB11 = 1U;
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_L:
+ /* PL Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB12 = 1U;
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_M:
+ /* PM Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB13 = 1U;
+ p_obj->p_pm_instance->DATA = 0x00;
+ p_obj->p_pm_instance->CR = 0x00;
+ p_obj->p_pm_instance->FR2 = 0x00;
+ p_obj->p_pm_instance->FR3 = 0x00;
+ p_obj->p_pm_instance->FR4 = 0x00;
+ p_obj->p_pm_instance->FR5 = 0x00;
+ p_obj->p_pm_instance->FR6 = 0x00;
+ p_obj->p_pm_instance->FR7 = 0x00;
+ p_obj->p_pm_instance->OD = 0x00;
+ p_obj->p_pm_instance->PUP = 0x00;
+ p_obj->p_pm_instance->PDN = 0x00;
+ p_obj->p_pm_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_N:
+ /* PN Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB14 = 1U;
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_P:
+ /* PP Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB15 = 1U;
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_R:
+ /* PR Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB16 = 1U;
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_T:
+ /* PT Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB17 = 1U;
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_U:
+ /* PU Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB18 = 1U;
+ p_obj->p_pu_instance->DATA = 0x00;
+ p_obj->p_pu_instance->CR = 0x00;
+ p_obj->p_pu_instance->FR2 = 0x00;
+ p_obj->p_pu_instance->FR3 = 0x00;
+ p_obj->p_pu_instance->FR7 = 0x00;
+ p_obj->p_pu_instance->OD = 0x00;
+ p_obj->p_pu_instance->PUP = 0x00;
+ p_obj->p_pu_instance->PDN = 0x00;
+ p_obj->p_pu_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_V:
+ /* PV Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB19 = 1U;
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_W:
+ /* PW Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB20 = 1U;
+ p_obj->p_pw_instance->DATA = 0x00;
+ p_obj->p_pw_instance->CR = 0x00;
+ p_obj->p_pw_instance->FR3 = 0x00;
+ p_obj->p_pw_instance->FR4 = 0x00;
+ p_obj->p_pw_instance->FR5 = 0x00;
+ p_obj->p_pw_instance->FR6 = 0x00;
+ p_obj->p_pw_instance->FR7 = 0x00;
+ p_obj->p_pw_instance->OD = 0x00;
+ p_obj->p_pw_instance->PUP = 0x00;
+ p_obj->p_pw_instance->PDN = 0x00;
+ p_obj->p_pw_instance->IE = 0x00;
+ break;
+ case GPIO_PORT_Y:
+ /* PY Clock Enable */
+ TSB_CG_FSYSMENB_IPMENB21 = 1U;
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ break;
+#endif /* TMPM4G9 */
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group)
+ * @brief Release the GPIO object.
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group.: Use @ref gpio_gr_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /* Check the NULL of address. */
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ /* Disable the selected GPIO peripheral */
+ switch (group)
+ {
+#if defined(TMPM4G6)
+ case GPIO_PORT_A:
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ /* PA Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB02 = 0U;
+ break;
+ case GPIO_PORT_B:
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ /* PB Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB03 = 0U;
+ break;
+ case GPIO_PORT_D:
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ /* PD Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB05 = 0U;
+ break;
+ case GPIO_PORT_E:
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ /* PE Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB06 = 0U;
+ break;
+ case GPIO_PORT_F:
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ /* PF Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB07= 0U;
+ break;
+ case GPIO_PORT_G:
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ /* PG Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB08 = 0U;
+ break;
+ case GPIO_PORT_H:
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF0;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ /* PH Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB09 = 0U;
+ break;
+ case GPIO_PORT_K:
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ /* PK Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB11 = 0U;
+ break;
+ case GPIO_PORT_L:
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ /* PL Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB12 = 0U;
+ break;
+ case GPIO_PORT_N:
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ /* PN Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB14 = 0U;
+ break;
+ case GPIO_PORT_P:
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ /* PP Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB15 = 0U;
+ break;
+ case GPIO_PORT_T:
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ /* PT Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB16 = 0U;
+ break;
+ case GPIO_PORT_Y:
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ /* PY Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB21 = 0U;
+ break;
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+ case GPIO_PORT_A:
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ /* PA Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB02 = 0U;
+ break;
+ case GPIO_PORT_B:
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ /* PB Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB03 = 0U;
+ break;
+ case GPIO_PORT_C:
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ /* PC Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB04 = 0U;
+ break;
+ case GPIO_PORT_D:
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ /* PD Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB05 = 0U;
+ break;
+ case GPIO_PORT_E:
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ /* PE Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB06 = 0U;
+ break;
+ case GPIO_PORT_F:
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ /* PF Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB07= 0U;
+ break;
+ case GPIO_PORT_G:
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ /* PG Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB08 = 0U;
+ break;
+ case GPIO_PORT_H:
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF0;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ /* PH Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB09 = 0U;
+ break;
+ case GPIO_PORT_K:
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ /* PK Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB11 = 0U;
+ break;
+ case GPIO_PORT_L:
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ /* PL Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB12 = 0U;
+ break;
+ case GPIO_PORT_N:
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ /* PN Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB14 = 0U;
+ break;
+ case GPIO_PORT_P:
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ /* PP Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB15 = 0U;
+ break;
+ case GPIO_PORT_R:
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ /* PR Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB16 = 0U;
+ break;
+ case GPIO_PORT_T:
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ /* PT Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB17 = 0U;
+ break;
+ case GPIO_PORT_V:
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ /* PV Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB19 = 0U;
+ break;
+ case GPIO_PORT_Y:
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ /* PY Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB21 = 0U;
+ break;
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+ case GPIO_PORT_A:
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ /* PA Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB02 = 0U;
+ break;
+ case GPIO_PORT_B:
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ /* PB Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB03 = 0U;
+ break;
+ case GPIO_PORT_C:
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ /* PC Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB04 = 0U;
+ break;
+ case GPIO_PORT_D:
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ /* PD Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB05 = 0U;
+ break;
+ case GPIO_PORT_E:
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ /* PE Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB06 = 0U;
+ break;
+ case GPIO_PORT_F:
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ /* PF Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB07= 0U;
+ break;
+ case GPIO_PORT_G:
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ /* PG Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB08 = 0U;
+ break;
+ case GPIO_PORT_H:
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF0;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ /* PH Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB09 = 0U;
+ break;
+ case GPIO_PORT_K:
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ /* PK Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB11 = 0U;
+ break;
+ case GPIO_PORT_L:
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ /* PL Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB12 = 0U;
+ break;
+ case GPIO_PORT_M:
+ p_obj->p_pm_instance->DATA = 0x00;
+ p_obj->p_pm_instance->CR = 0x00;
+ p_obj->p_pm_instance->FR2 = 0x00;
+ p_obj->p_pm_instance->FR3 = 0x00;
+ p_obj->p_pm_instance->FR4 = 0x00;
+ p_obj->p_pm_instance->FR5 = 0x00;
+ p_obj->p_pm_instance->FR6 = 0x00;
+ p_obj->p_pm_instance->FR7 = 0x00;
+ p_obj->p_pm_instance->OD = 0x00;
+ p_obj->p_pm_instance->PUP = 0x00;
+ p_obj->p_pm_instance->PDN = 0x00;
+ p_obj->p_pm_instance->IE = 0x00;
+ /* PM Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB13 = 0U;
+ break;
+ case GPIO_PORT_N:
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ /* PN Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB14 = 0U;
+ break;
+ case GPIO_PORT_P:
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ /* PP Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB15 = 0U;
+ break;
+ case GPIO_PORT_R:
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ /* PR Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB16 = 0U;
+ break;
+ case GPIO_PORT_T:
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ /* PT Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB17 = 0U;
+ break;
+ case GPIO_PORT_V:
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ /* PV Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB19 = 0U;
+ break;
+ case GPIO_PORT_Y:
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ /* PY Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB21 = 0U;
+ break;
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+ case GPIO_PORT_A:
+ p_obj->p_pa_instance->DATA = 0x00;
+ p_obj->p_pa_instance->CR = 0x00;
+ p_obj->p_pa_instance->FR1 = 0x00;
+ p_obj->p_pa_instance->FR2 = 0x00;
+ p_obj->p_pa_instance->FR3 = 0x00;
+ p_obj->p_pa_instance->FR5 = 0x00;
+ p_obj->p_pa_instance->FR6 = 0x00;
+ p_obj->p_pa_instance->FR7 = 0x00;
+ p_obj->p_pa_instance->OD = 0x00;
+ p_obj->p_pa_instance->PUP = 0x00;
+ p_obj->p_pa_instance->PDN = 0x00;
+ p_obj->p_pa_instance->IE = 0x00;
+ /* PA Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB02 = 0U;
+ break;
+ case GPIO_PORT_B:
+ p_obj->p_pb_instance->DATA = 0x00;
+ p_obj->p_pb_instance->CR = 0x00;
+ p_obj->p_pb_instance->FR1 = 0x00;
+ p_obj->p_pb_instance->FR2 = 0x00;
+ p_obj->p_pb_instance->FR3 = 0x00;
+ p_obj->p_pb_instance->FR5 = 0x00;
+ p_obj->p_pb_instance->FR6 = 0x00;
+ p_obj->p_pb_instance->OD = 0x00;
+ p_obj->p_pb_instance->PUP = 0x00;
+ p_obj->p_pb_instance->PDN = 0x00;
+ p_obj->p_pb_instance->IE = 0x00;
+ /* PB Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB03 = 0U;
+ break;
+ case GPIO_PORT_C:
+ p_obj->p_pc_instance->DATA = 0x00;
+ p_obj->p_pc_instance->CR = 0x00;
+ p_obj->p_pc_instance->FR1 = 0x00;
+ p_obj->p_pc_instance->FR3 = 0x00;
+ p_obj->p_pc_instance->FR5 = 0x00;
+ p_obj->p_pc_instance->OD = 0x00;
+ p_obj->p_pc_instance->PUP = 0x00;
+ p_obj->p_pc_instance->PDN = 0x00;
+ p_obj->p_pc_instance->IE = 0x00;
+ /* PC Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB04 = 0U;
+ break;
+ case GPIO_PORT_D:
+ p_obj->p_pd_instance->DATA = 0x00;
+ p_obj->p_pd_instance->CR = 0x00;
+ p_obj->p_pd_instance->FR1 = 0x00;
+ p_obj->p_pd_instance->FR2 = 0x00;
+ p_obj->p_pd_instance->FR3 = 0x00;
+ p_obj->p_pd_instance->FR4 = 0x00;
+ p_obj->p_pd_instance->FR5 = 0x00;
+ p_obj->p_pd_instance->FR6 = 0x00;
+ p_obj->p_pd_instance->FR7 = 0x00;
+ p_obj->p_pd_instance->OD = 0x00;
+ p_obj->p_pd_instance->PUP = 0x00;
+ p_obj->p_pd_instance->PDN = 0x00;
+ p_obj->p_pd_instance->IE = 0x00;
+ /* PD Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB05 = 0U;
+ break;
+ case GPIO_PORT_E:
+ p_obj->p_pe_instance->DATA = 0x00;
+ p_obj->p_pe_instance->CR = 0x00;
+ p_obj->p_pe_instance->FR1 = 0x00;
+ p_obj->p_pe_instance->FR2 = 0x00;
+ p_obj->p_pe_instance->FR3 = 0x00;
+ p_obj->p_pe_instance->FR4 = 0x00;
+ p_obj->p_pe_instance->FR5 = 0x00;
+ p_obj->p_pe_instance->FR7 = 0x00;
+ p_obj->p_pe_instance->OD = 0x00;
+ p_obj->p_pe_instance->PUP = 0x00;
+ p_obj->p_pe_instance->PDN = 0x00;
+ p_obj->p_pe_instance->IE = 0x00;
+ /* PE Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB06 = 0U;
+ break;
+ case GPIO_PORT_F:
+ p_obj->p_pf_instance->DATA = 0x00;
+ p_obj->p_pf_instance->CR = 0x00;
+ p_obj->p_pf_instance->FR1 = 0x00;
+ p_obj->p_pf_instance->FR7 = 0x00;
+ p_obj->p_pf_instance->OD = 0x00;
+ p_obj->p_pf_instance->PUP = 0x00;
+ p_obj->p_pf_instance->PDN = 0x00;
+ p_obj->p_pf_instance->IE = 0x00;
+ /* PF Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB07= 0U;
+ break;
+ case GPIO_PORT_G:
+ p_obj->p_pg_instance->DATA = 0x00;
+ p_obj->p_pg_instance->CR = 0x00;
+ p_obj->p_pg_instance->FR1 = 0x00;
+ p_obj->p_pg_instance->FR2 = 0x00;
+ p_obj->p_pg_instance->FR3 = 0x00;
+ p_obj->p_pg_instance->FR4 = 0x00;
+ p_obj->p_pg_instance->FR5 = 0x00;
+ p_obj->p_pg_instance->FR7 = 0x00;
+ p_obj->p_pg_instance->OD = 0x00;
+ p_obj->p_pg_instance->PUP = 0x00;
+ p_obj->p_pg_instance->PDN = 0x00;
+ p_obj->p_pg_instance->IE = 0x00;
+ /* PG Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB08 = 0U;
+ break;
+ case GPIO_PORT_H:
+ p_obj->p_ph_instance->DATA = 0x00;
+ p_obj->p_ph_instance->CR = 0x50;
+ p_obj->p_ph_instance->FR1 = 0xF0;
+ p_obj->p_ph_instance->FR3 = 0x00;
+ p_obj->p_ph_instance->FR4 = 0x00;
+ p_obj->p_ph_instance->FR5 = 0x00;
+ p_obj->p_ph_instance->OD = 0x00;
+ p_obj->p_ph_instance->PUP = 0x98;
+ p_obj->p_ph_instance->PDN = 0x20;
+ p_obj->p_ph_instance->IE = 0xB8;
+ /* PH Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB09 = 0U;
+ break;
+ case GPIO_PORT_J:
+ p_obj->p_pj_instance->DATA = 0x00;
+ p_obj->p_pj_instance->CR = 0x00;
+ p_obj->p_pj_instance->FR2 = 0x00;
+ p_obj->p_pj_instance->FR3 = 0x00;
+ p_obj->p_pj_instance->FR5 = 0x00;
+ p_obj->p_pj_instance->FR7 = 0x00;
+ p_obj->p_pj_instance->OD = 0x00;
+ p_obj->p_pj_instance->PUP = 0x00;
+ p_obj->p_pj_instance->PDN = 0x00;
+ p_obj->p_pj_instance->IE = 0x00;
+ /* PJ Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB10 = 0U;
+ break;
+ case GPIO_PORT_K:
+ p_obj->p_pk_instance->DATA = 0x00;
+ p_obj->p_pk_instance->CR = 0x00;
+ p_obj->p_pk_instance->FR1 = 0x00;
+ p_obj->p_pk_instance->FR2 = 0x00;
+ p_obj->p_pk_instance->FR3 = 0x00;
+ p_obj->p_pk_instance->FR4 = 0x00;
+ p_obj->p_pk_instance->FR6 = 0x00;
+ p_obj->p_pk_instance->FR7 = 0x00;
+ p_obj->p_pk_instance->OD = 0x00;
+ p_obj->p_pk_instance->PUP = 0x00;
+ p_obj->p_pk_instance->PDN = 0x00;
+ p_obj->p_pk_instance->IE = 0x00;
+ /* PK Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB11 = 0U;
+ break;
+ case GPIO_PORT_L:
+ p_obj->p_pl_instance->DATA = 0x00;
+ p_obj->p_pl_instance->CR = 0x00;
+ p_obj->p_pl_instance->FR1 = 0x00;
+ p_obj->p_pl_instance->FR2 = 0x00;
+ p_obj->p_pl_instance->FR3 = 0x00;
+ p_obj->p_pl_instance->FR6 = 0x00;
+ p_obj->p_pl_instance->FR7 = 0x00;
+ p_obj->p_pl_instance->OD = 0x00;
+ p_obj->p_pl_instance->PUP = 0x00;
+ p_obj->p_pl_instance->PDN = 0x00;
+ p_obj->p_pl_instance->IE = 0x00;
+ /* PL Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB12 = 0U;
+ break;
+ case GPIO_PORT_M:
+ p_obj->p_pm_instance->DATA = 0x00;
+ p_obj->p_pm_instance->CR = 0x00;
+ p_obj->p_pm_instance->FR2 = 0x00;
+ p_obj->p_pm_instance->FR3 = 0x00;
+ p_obj->p_pm_instance->FR4 = 0x00;
+ p_obj->p_pm_instance->FR5 = 0x00;
+ p_obj->p_pm_instance->FR6 = 0x00;
+ p_obj->p_pm_instance->FR7 = 0x00;
+ p_obj->p_pm_instance->OD = 0x00;
+ p_obj->p_pm_instance->PUP = 0x00;
+ p_obj->p_pm_instance->PDN = 0x00;
+ p_obj->p_pm_instance->IE = 0x00;
+ /* PM Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB13 = 0U;
+ break;
+ case GPIO_PORT_N:
+ p_obj->p_pn_instance->DATA = 0x00;
+ p_obj->p_pn_instance->CR = 0x00;
+ p_obj->p_pn_instance->OD = 0x00;
+ p_obj->p_pn_instance->PUP = 0x00;
+ p_obj->p_pn_instance->PDN = 0x00;
+ p_obj->p_pn_instance->IE = 0x00;
+ /* PN Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB14 = 0U;
+ break;
+ case GPIO_PORT_P:
+ p_obj->p_pp_instance->DATA = 0x00;
+ p_obj->p_pp_instance->CR = 0x00;
+ p_obj->p_pp_instance->FR2 = 0x00;
+ p_obj->p_pp_instance->FR3 = 0x00;
+ p_obj->p_pp_instance->FR5 = 0x00;
+ p_obj->p_pp_instance->OD = 0x00;
+ p_obj->p_pp_instance->PUP = 0x00;
+ p_obj->p_pp_instance->PDN = 0x00;
+ p_obj->p_pp_instance->IE = 0x00;
+ /* PP Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB15 = 0U;
+ break;
+ case GPIO_PORT_R:
+ p_obj->p_pr_instance->DATA = 0x00;
+ p_obj->p_pr_instance->CR = 0x00;
+ p_obj->p_pr_instance->FR2 = 0x00;
+ p_obj->p_pr_instance->FR3 = 0x00;
+ p_obj->p_pr_instance->OD = 0x00;
+ p_obj->p_pr_instance->PUP = 0x00;
+ p_obj->p_pr_instance->PDN = 0x00;
+ p_obj->p_pr_instance->IE = 0x00;
+ /* PR Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB16 = 0U;
+ break;
+ case GPIO_PORT_T:
+ p_obj->p_pt_instance->DATA = 0x00;
+ p_obj->p_pt_instance->CR = 0x00;
+ p_obj->p_pt_instance->FR1 = 0x00;
+ p_obj->p_pt_instance->FR2 = 0x00;
+ p_obj->p_pt_instance->FR3 = 0x00;
+ p_obj->p_pt_instance->FR6 = 0x00;
+ p_obj->p_pt_instance->FR7 = 0x00;
+ p_obj->p_pt_instance->OD = 0x00;
+ p_obj->p_pt_instance->PUP = 0x00;
+ p_obj->p_pt_instance->PDN = 0x00;
+ p_obj->p_pt_instance->IE = 0x00;
+ /* PT Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB17 = 0U;
+ break;
+ case GPIO_PORT_U:
+ p_obj->p_pu_instance->DATA = 0x00;
+ p_obj->p_pu_instance->CR = 0x00;
+ p_obj->p_pu_instance->FR2 = 0x00;
+ p_obj->p_pu_instance->FR3 = 0x00;
+ p_obj->p_pu_instance->FR7 = 0x00;
+ p_obj->p_pu_instance->OD = 0x00;
+ p_obj->p_pu_instance->PUP = 0x00;
+ p_obj->p_pu_instance->PDN = 0x00;
+ p_obj->p_pu_instance->IE = 0x00;
+ /* PU Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB18 = 0U;
+ break;
+ case GPIO_PORT_V:
+ p_obj->p_pv_instance->DATA = 0x00;
+ p_obj->p_pv_instance->CR = 0x00;
+ p_obj->p_pv_instance->FR2 = 0x00;
+ p_obj->p_pv_instance->FR3 = 0x00;
+ p_obj->p_pv_instance->FR4 = 0x00;
+ p_obj->p_pv_instance->FR5 = 0x00;
+ p_obj->p_pv_instance->FR6 = 0x00;
+ p_obj->p_pv_instance->FR7 = 0x00;
+ p_obj->p_pv_instance->OD = 0x00;
+ p_obj->p_pv_instance->PUP = 0x00;
+ p_obj->p_pv_instance->PDN = 0x00;
+ p_obj->p_pv_instance->IE = 0x00;
+ /* PV Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB19 = 0U;
+ break;
+ case GPIO_PORT_W:
+ p_obj->p_pw_instance->DATA = 0x00;
+ p_obj->p_pw_instance->CR = 0x00;
+ p_obj->p_pw_instance->FR3 = 0x00;
+ p_obj->p_pw_instance->FR4 = 0x00;
+ p_obj->p_pw_instance->FR5 = 0x00;
+ p_obj->p_pw_instance->FR6 = 0x00;
+ p_obj->p_pw_instance->FR7 = 0x00;
+ p_obj->p_pw_instance->OD = 0x00;
+ p_obj->p_pw_instance->PUP = 0x00;
+ p_obj->p_pw_instance->PDN = 0x00;
+ p_obj->p_pw_instance->IE = 0x00;
+ /* PW Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB20 = 0U;
+ break;
+ case GPIO_PORT_Y:
+ p_obj->p_py_instance->DATA = 0x00;
+ p_obj->p_py_instance->CR = 0x00;
+ p_obj->p_py_instance->FR1 = 0x00;
+ p_obj->p_py_instance->FR4 = 0x00;
+ p_obj->p_py_instance->OD = 0x00;
+ p_obj->p_py_instance->PUP = 0x00;
+ p_obj->p_py_instance->PDN = 0x00;
+ p_obj->p_py_instance->IE = 0x00;
+ /* PY Clock Disable */
+ TSB_CG_FSYSMENB_IPMENB21 = 0U;
+ break;
+#endif /* TMPM4G9 */
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val)
+ * @brief Port Mode Write
+ * @param[in] p_obj :GPIO object.
+ * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t
+ * @param[in] val :value
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ int32_t i;
+ int32_t param_result = PARAM_NG;
+
+ /* Check the parameters, the NULL of address */
+ for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++)
+ {
+ param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode);
+ if(param_result == PARAM_OK)
+ {
+ break;
+ }
+ else
+ {
+ result = TXZ_ERROR;
+ }
+ }
+ if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ switch (group)
+ {
+#if defined(TMPM4G6)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;}
+ break;
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;}
+ break;
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;}
+ break;
+ case GPIO_PORT_M:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;}
+ break;
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pa_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pa_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pa_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pa_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pa_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pa_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pa_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pa_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pa_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pa_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pa_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pa_instance->IE = val;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pb_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pb_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pb_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pb_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pb_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pb_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pb_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pb_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pb_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pb_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pb_instance->IE = val;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pc_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pc_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pc_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pc_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pc_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pc_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pc_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pc_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pc_instance->IE = val;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pd_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pd_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pd_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pd_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pd_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pd_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pd_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pd_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pd_instance->IE = val;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pe_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pe_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pe_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pd_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pd_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pd_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pd_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pe_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pe_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pe_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pe_instance->IE = val;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pf_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pf_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pf_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pf_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pf_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pf_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pf_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pf_instance->IE = val;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pg_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pg_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pg_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pg_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pg_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pg_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pg_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pg_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pg_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pg_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pg_instance->IE = val;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_ph_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_ph_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_ph_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_ph_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_ph_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_ph_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_ph_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_ph_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_ph_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_ph_instance->IE = val;}
+ break;
+ case GPIO_PORT_J:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pj_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pj_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pj_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pj_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pj_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pj_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pj_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pj_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pj_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pj_instance->IE = val;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pk_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pk_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pk_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pk_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pk_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pk_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pk_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pk_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pk_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pk_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pk_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pk_instance->IE = val;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pl_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pl_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pl_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pl_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pl_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pl_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pl_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pl_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pl_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pl_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pl_instance->IE = val;}
+ break;
+ case GPIO_PORT_M:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pm_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pm_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pm_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pm_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pm_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pm_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pm_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pm_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pm_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pm_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pm_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pm_instance->IE = val;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pn_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pn_instance->CR = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pn_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pn_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pn_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pn_instance->IE = val;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pp_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pp_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pp_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pp_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pp_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pp_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pp_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pp_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pp_instance->IE = val;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pr_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pr_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pr_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pr_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pr_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pr_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pr_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pr_instance->IE = val;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pt_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pt_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_pt_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pt_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pt_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pt_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pt_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pt_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pt_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pt_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pt_instance->IE = val;}
+ break;
+ case GPIO_PORT_U:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pu_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pu_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pu_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pu_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pu_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pu_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pu_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pu_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pu_instance->IE = val;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pv_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pv_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR2) {p_obj->p_pv_instance->FR2 = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pv_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pv_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pv_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pv_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pv_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pv_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pv_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pv_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pv_instance->IE = val;}
+ break;
+ case GPIO_PORT_W:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_pw_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_pw_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR3) {p_obj->p_pw_instance->FR3 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_pw_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_FR5) {p_obj->p_pw_instance->FR5 = val;}
+ else if(mode == GPIO_Mode_FR6) {p_obj->p_pw_instance->FR6 = val;}
+ else if(mode == GPIO_Mode_FR7) {p_obj->p_pw_instance->FR7 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_pw_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_pw_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_pw_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_pw_instance->IE = val;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {p_obj->p_py_instance->DATA = val;}
+ else if(mode == GPIO_Mode_CR) {p_obj->p_py_instance->CR = val;}
+ else if(mode == GPIO_Mode_FR1) {p_obj->p_py_instance->FR1 = val;}
+ else if(mode == GPIO_Mode_FR4) {p_obj->p_py_instance->FR4 = val;}
+ else if(mode == GPIO_Mode_OD) {p_obj->p_py_instance->OD = val;}
+ else if(mode == GPIO_Mode_PUP) {p_obj->p_py_instance->PUP = val;}
+ else if(mode == GPIO_Mode_PDN) {p_obj->p_py_instance->PDN = val;}
+ else if(mode == GPIO_Mode_IE) {p_obj->p_py_instance->IE = val;}
+ break;
+#endif /* TMPM4G9 */
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val)
+ * @brief Port Mode Read
+ * @param[in] p_obj :GPIO object.
+ * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t
+ * @param[out] val :Store of value
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ int32_t param_result = PARAM_NG;
+ int32_t i;
+
+ /* Check the parameters, the NULL of address */
+ for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++ )
+ {
+ param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode);
+ if(param_result == PARAM_OK)
+ {
+ break;
+ }
+ else
+ {
+ result = TXZ_ERROR;
+ }
+ }
+ if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ switch (group)
+ {
+#if defined(TMPM4G6)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;}
+ break;
+#endif /* TMPM4G6 */
+#if defined(TMPM4G7)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;}
+ break;
+#endif /* TMPM4G7 */
+#if defined(TMPM4G8)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;}
+ break;
+ case GPIO_PORT_M:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;}
+ break;
+#endif /* TMPM4G8 */
+#if defined(TMPM4G9)
+ case GPIO_PORT_A:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pa_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pa_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pa_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pa_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pa_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pa_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pa_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pa_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pa_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pa_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pa_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pa_instance->IE;}
+ break;
+ case GPIO_PORT_B:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pb_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pb_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pb_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pb_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pb_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pb_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pb_instance->FR6;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pb_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pb_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pb_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pb_instance->IE;}
+ break;
+ case GPIO_PORT_C:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pc_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pc_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pc_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pc_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pc_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pc_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pc_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pc_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pc_instance->IE;}
+ break;
+ case GPIO_PORT_D:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pd_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pd_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pd_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pd_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pd_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pd_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pd_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pd_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pd_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pd_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pd_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pd_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pd_instance->IE;}
+ break;
+ case GPIO_PORT_E:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pe_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pe_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pe_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pe_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pe_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pe_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pe_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pe_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pe_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pe_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pe_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pe_instance->IE;}
+ break;
+ case GPIO_PORT_F:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pf_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pf_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pf_instance->FR1;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pf_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pf_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pf_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pf_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pf_instance->IE;}
+ break;
+ case GPIO_PORT_G:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pg_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pg_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pg_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pg_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pg_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pg_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pg_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pg_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pg_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pg_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pg_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pg_instance->IE;}
+ break;
+ case GPIO_PORT_H:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_ph_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_ph_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_ph_instance->FR1;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_ph_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_ph_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_ph_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_ph_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_ph_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_ph_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_ph_instance->IE;}
+ break;
+ case GPIO_PORT_J:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pj_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pj_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pj_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pj_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pj_instance->FR5;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pj_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pj_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pj_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pj_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pj_instance->IE;}
+ break;
+ case GPIO_PORT_K:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pk_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pk_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pk_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pk_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pk_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pk_instance->FR4;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pk_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pk_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pk_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pk_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pk_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pk_instance->IE;}
+ break;
+ case GPIO_PORT_L:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pl_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pl_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pl_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pl_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pl_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pl_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pl_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pl_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pl_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pl_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pl_instance->IE;}
+ break;
+ case GPIO_PORT_M:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pm_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pm_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pm_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pm_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pm_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pm_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pm_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pm_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pm_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pm_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pm_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pm_instance->IE;}
+ break;
+ case GPIO_PORT_N:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pn_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pn_instance->CR;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pn_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pn_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pn_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pn_instance->IE;}
+ break;
+ case GPIO_PORT_P:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pp_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pp_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pp_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pp_instance->FR3;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pp_instance->FR5;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pp_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pp_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pp_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pp_instance->IE;}
+ break;
+ case GPIO_PORT_R:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pr_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pr_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pr_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pr_instance->FR3;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pr_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pr_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pr_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pr_instance->IE;}
+ break;
+ case GPIO_PORT_T:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pt_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pt_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_pt_instance->FR1;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pt_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pt_instance->FR3;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pt_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pt_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pt_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pt_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pt_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pt_instance->IE;}
+ break;
+ case GPIO_PORT_U:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pu_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pu_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pu_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pu_instance->FR3;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pu_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pu_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pu_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pu_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pu_instance->IE;}
+ break;
+ case GPIO_PORT_V:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pv_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pv_instance->CR;}
+ else if(mode == GPIO_Mode_FR2) {*val = p_obj->p_pv_instance->FR2;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pv_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pv_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pv_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pv_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pv_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pv_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pv_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pv_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pv_instance->IE;}
+ break;
+ case GPIO_PORT_W:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_pw_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_pw_instance->CR;}
+ else if(mode == GPIO_Mode_FR3) {*val = p_obj->p_pw_instance->FR3;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_pw_instance->FR4;}
+ else if(mode == GPIO_Mode_FR5) {*val = p_obj->p_pw_instance->FR5;}
+ else if(mode == GPIO_Mode_FR6) {*val = p_obj->p_pw_instance->FR6;}
+ else if(mode == GPIO_Mode_FR7) {*val = p_obj->p_pw_instance->FR7;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_pw_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_pw_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_pw_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_pw_instance->IE;}
+ break;
+ case GPIO_PORT_Y:
+ if(mode == GPIO_Mode_DATA) {*val = p_obj->p_py_instance->DATA;}
+ else if(mode == GPIO_Mode_CR) {*val = p_obj->p_py_instance->CR;}
+ else if(mode == GPIO_Mode_FR1) {*val = p_obj->p_py_instance->FR1;}
+ else if(mode == GPIO_Mode_FR4) {*val = p_obj->p_py_instance->FR4;}
+ else if(mode == GPIO_Mode_OD) {*val = p_obj->p_py_instance->OD;}
+ else if(mode == GPIO_Mode_PUP) {*val = p_obj->p_py_instance->PUP;}
+ else if(mode == GPIO_Mode_PDN) {*val = p_obj->p_py_instance->PDN;}
+ else if(mode == GPIO_Mode_IE) {*val = p_obj->p_py_instance->IE;}
+ break;
+#endif /* TMPM4G9 */
+ default:
+ result = TXZ_ERROR;
+ }
+ }
+
+ return result;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Port Function switching
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t
+ * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t
+ * @retval GPIO_RESULT_SUCCESS :Success.
+ * @retval GPIO_RESULT_FAILURE :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t port_base;
+ uint32_t mode_base;
+ int32_t param_result = PARAM_NG;
+
+ /* Check the parameters, the NULL of address */
+ param_result = check_param_func_pin_exist(p_obj, group, num, func);
+ if (((void*)(p_obj) == (void*)0) || (param_result == PARAM_NG))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ switch (group)
+ {
+ #if defined(TMPM4G6)
+ case GPIO_PORT_A:
+ port_base = (uint32_t)p_obj->p_pa_instance;
+ break;
+ case GPIO_PORT_B:
+ port_base = (uint32_t)p_obj->p_pb_instance;
+ break;
+ case GPIO_PORT_D:
+ port_base = (uint32_t)p_obj->p_pd_instance;
+ break;
+ case GPIO_PORT_E:
+ port_base = (uint32_t)p_obj->p_pe_instance;
+ break;
+ case GPIO_PORT_F:
+ port_base = (uint32_t)p_obj->p_pf_instance;
+ break;
+ case GPIO_PORT_G:
+ port_base = (uint32_t)p_obj->p_pg_instance;
+ break;
+ case GPIO_PORT_H:
+ port_base = (uint32_t)p_obj->p_ph_instance;
+ break;
+ case GPIO_PORT_K:
+ port_base = (uint32_t)p_obj->p_pk_instance;
+ break;
+ case GPIO_PORT_L:
+ port_base = (uint32_t)p_obj->p_pl_instance;
+ break;
+ case GPIO_PORT_N:
+ port_base = (uint32_t)p_obj->p_pn_instance;
+ break;
+ case GPIO_PORT_P:
+ port_base = (uint32_t)p_obj->p_pp_instance;
+ break;
+ case GPIO_PORT_T:
+ port_base = (uint32_t)p_obj->p_pt_instance;
+ break;
+ case GPIO_PORT_Y:
+ port_base = (uint32_t)p_obj->p_py_instance;
+ break;
+ #endif /* TMPM4G6 */
+ #if defined(TMPM4G7)
+ case GPIO_PORT_A:
+ port_base = (uint32_t)p_obj->p_pa_instance;
+ break;
+ case GPIO_PORT_B:
+ port_base = (uint32_t)p_obj->p_pb_instance;
+ break;
+ case GPIO_PORT_C:
+ port_base = (uint32_t)p_obj->p_pc_instance;
+ break;
+ case GPIO_PORT_D:
+ port_base = (uint32_t)p_obj->p_pd_instance;
+ break;
+ case GPIO_PORT_E:
+ port_base = (uint32_t)p_obj->p_pe_instance;
+ break;
+ case GPIO_PORT_F:
+ port_base = (uint32_t)p_obj->p_pf_instance;
+ break;
+ case GPIO_PORT_G:
+ port_base = (uint32_t)p_obj->p_pg_instance;
+ break;
+ case GPIO_PORT_H:
+ port_base = (uint32_t)p_obj->p_ph_instance;
+ break;
+ case GPIO_PORT_K:
+ port_base = (uint32_t)p_obj->p_pk_instance;
+ break;
+ case GPIO_PORT_L:
+ port_base = (uint32_t)p_obj->p_pl_instance;
+ break;
+ case GPIO_PORT_N:
+ port_base = (uint32_t)p_obj->p_pn_instance;
+ break;
+ case GPIO_PORT_P:
+ port_base = (uint32_t)p_obj->p_pp_instance;
+ break;
+ case GPIO_PORT_R:
+ port_base = (uint32_t)p_obj->p_pr_instance;
+ break;
+ case GPIO_PORT_T:
+ port_base = (uint32_t)p_obj->p_pt_instance;
+ break;
+ case GPIO_PORT_V:
+ port_base = (uint32_t)p_obj->p_pv_instance;
+ break;
+ case GPIO_PORT_Y:
+ port_base = (uint32_t)p_obj->p_py_instance;
+ break;
+ #endif /* TMPM4G7 */
+ #if defined(TMPM4G8)
+ case GPIO_PORT_A:
+ port_base = (uint32_t)p_obj->p_pa_instance;
+ break;
+ case GPIO_PORT_B:
+ port_base = (uint32_t)p_obj->p_pb_instance;
+ break;
+ case GPIO_PORT_C:
+ port_base = (uint32_t)p_obj->p_pc_instance;
+ break;
+ case GPIO_PORT_D:
+ port_base = (uint32_t)p_obj->p_pd_instance;
+ break;
+ case GPIO_PORT_E:
+ port_base = (uint32_t)p_obj->p_pe_instance;
+ break;
+ case GPIO_PORT_F:
+ port_base = (uint32_t)p_obj->p_pf_instance;
+ break;
+ case GPIO_PORT_G:
+ port_base = (uint32_t)p_obj->p_pg_instance;
+ break;
+ case GPIO_PORT_H:
+ port_base = (uint32_t)p_obj->p_ph_instance;
+ break;
+ case GPIO_PORT_K:
+ port_base = (uint32_t)p_obj->p_pk_instance;
+ break;
+ case GPIO_PORT_L:
+ port_base = (uint32_t)p_obj->p_pl_instance;
+ break;
+ case GPIO_PORT_M:
+ port_base = (uint32_t)p_obj->p_pm_instance;
+ break;
+ case GPIO_PORT_N:
+ port_base = (uint32_t)p_obj->p_pn_instance;
+ break;
+ case GPIO_PORT_P:
+ port_base = (uint32_t)p_obj->p_pp_instance;
+ break;
+ case GPIO_PORT_R:
+ port_base = (uint32_t)p_obj->p_pr_instance;
+ break;
+ case GPIO_PORT_T:
+ port_base = (uint32_t)p_obj->p_pt_instance;
+ break;
+ case GPIO_PORT_V:
+ port_base = (uint32_t)p_obj->p_pv_instance;
+ break;
+ case GPIO_PORT_Y:
+ port_base = (uint32_t)p_obj->p_py_instance;
+ break;
+ #endif /* TMPM4G8 */
+ #if defined(TMPM4G9)
+ case GPIO_PORT_A:
+ port_base = (uint32_t)p_obj->p_pa_instance;
+ break;
+ case GPIO_PORT_B:
+ port_base = (uint32_t)p_obj->p_pb_instance;
+ break;
+ case GPIO_PORT_C:
+ port_base = (uint32_t)p_obj->p_pc_instance;
+ break;
+ case GPIO_PORT_D:
+ port_base = (uint32_t)p_obj->p_pd_instance;
+ break;
+ case GPIO_PORT_E:
+ port_base = (uint32_t)p_obj->p_pe_instance;
+ break;
+ case GPIO_PORT_F:
+ port_base = (uint32_t)p_obj->p_pf_instance;
+ break;
+ case GPIO_PORT_G:
+ port_base = (uint32_t)p_obj->p_pg_instance;
+ break;
+ case GPIO_PORT_H:
+ port_base = (uint32_t)p_obj->p_ph_instance;
+ break;
+ case GPIO_PORT_J:
+ port_base = (uint32_t)p_obj->p_pj_instance;
+ break;
+ case GPIO_PORT_K:
+ port_base = (uint32_t)p_obj->p_pk_instance;
+ break;
+ case GPIO_PORT_L:
+ port_base = (uint32_t)p_obj->p_pl_instance;
+ break;
+ case GPIO_PORT_M:
+ port_base = (uint32_t)p_obj->p_pm_instance;
+ break;
+ case GPIO_PORT_N:
+ port_base = (uint32_t)p_obj->p_pn_instance;
+ break;
+ case GPIO_PORT_P:
+ port_base = (uint32_t)p_obj->p_pp_instance;
+ break;
+ case GPIO_PORT_R:
+ port_base = (uint32_t)p_obj->p_pr_instance;
+ break;
+ case GPIO_PORT_T:
+ port_base = (uint32_t)p_obj->p_pt_instance;
+ break;
+ case GPIO_PORT_U:
+ port_base = (uint32_t)p_obj->p_pu_instance;
+ break;
+ case GPIO_PORT_V:
+ port_base = (uint32_t)p_obj->p_pv_instance;
+ break;
+ case GPIO_PORT_W:
+ port_base = (uint32_t)p_obj->p_pw_instance;
+ break;
+ case GPIO_PORT_Y:
+ port_base = (uint32_t)p_obj->p_py_instance;
+ break;
+ #endif /* TMPM4G9 */
+ default:
+ result = TXZ_ERROR;
+ }
+ if(result == TXZ_ERROR)
+ {
+ return (result);
+ }
+
+ /* Initialization PxFR OFF */
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7);
+ BITBAND_PORT_CLR(mode_base, num);
+
+ /* Initialize Input/Output */
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+
+ switch (func) {
+ case 0:
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_1:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_2:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_3:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_4:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_5:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }
+ break;
+ case GPIO_FR_6:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_7:
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7);
+ BITBAND_PORT_SET(mode_base, num);
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ case GPIO_FR_NA:
+ if(inout== GPIO_PIN_OUTPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_CLR(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_INPUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_CLR(mode_base, num);
+ }else if(inout== GPIO_PIN_INOUT){
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
+ BITBAND_PORT_SET(mode_base, num);
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
+ BITBAND_PORT_SET(mode_base, num);
+ }else if(inout== GPIO_PIN_NOTINOUT){
+ /* No Process */
+ }
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Pull up mode
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t port_base;
+ uint32_t mode_base;
+
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ port_base = BITBAND_PORT_BASE(group);
+
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP);
+ if (val == GPIO_PIN_SET)
+ {
+ BITBAND_PORT_SET(mode_base, num);
+ }
+ else if (val == GPIO_PIN_RESET)
+ {
+ BITBAND_PORT_CLR(mode_base, num);
+ }
+ else{ result = TXZ_ERROR;}
+ }
+
+ return result;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Pull down mode
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t port_base;
+ uint32_t mode_base;
+
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ port_base = BITBAND_PORT_BASE(group);
+
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN);
+ if (val == GPIO_PIN_SET)
+ {
+ BITBAND_PORT_SET(mode_base, num);
+ }
+ else if (val == GPIO_PIN_RESET)
+ {
+ BITBAND_PORT_CLR(mode_base, num);
+ }
+ else{ result = TXZ_ERROR;}
+ }
+
+ return result;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Set Open drain mode
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t port_base;
+ uint32_t mode_base;
+
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ port_base = BITBAND_PORT_BASE(group);
+
+ mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD);
+ if (val == GPIO_PIN_SET)
+ {
+ BITBAND_PORT_SET(mode_base, num);
+ }
+ else if (val == GPIO_PIN_RESET)
+ {
+ BITBAND_PORT_CLR(mode_base, num);
+ }
+ else{ result = TXZ_ERROR;}
+ }
+
+ return result;
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val)
+ * @brief Port Bit Write
+ * @param p_obj :GPIO object.
+ * @param group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t
+ * @param val :GPIO Pin Reset/Set.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t base;
+
+ /* Check the parameters */
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ base = BITBAND_PORT_BASE(group);
+ base = BITBAND_PORT_MODE_BASE(base, mode);
+ if (val == GPIO_PIN_SET){ BITBAND_PORT_SET(base, num);}
+ else if (val == GPIO_PIN_RESET){ BITBAND_PORT_CLR(base, num);}
+ else{ result = TXZ_ERROR;}
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/*!
+ * @fn TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate)
+ * @brief Port Bit Read
+ * @param[in] p_obj :GPIO object.
+ * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t
+ * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t
+ * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t
+ * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t
+ */
+/*--------------------------------------------------*/
+TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t base;
+ uint32_t val;
+
+ /* Check the parameters */
+ if ((void*)(p_obj) == (void*)0)
+ {
+ result = TXZ_ERROR;
+ }
+ else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG)
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ base = BITBAND_PORT_BASE(group);
+ base = BITBAND_PORT_MODE_BASE(base, mode);
+ BITBAND_PORT_READ(val, base, num);
+ if(val == GPIO_PIN_RESET){ *pinstate = GPIO_PIN_RESET;}
+ else if (val == GPIO_PIN_SET){ *pinstate = GPIO_PIN_SET;}
+ else{ result = TXZ_ERROR;}
+ }
+
+ return result;
+}
+
+/**
+ * @}
+ */ /* End of group GPIO_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group GPIO */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__GPIO_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_hal.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,175 @@
+/**
+ *******************************************************************************
+ * @file txz_hal.c
+ * @brief This file provides API functions for driver common part.
+ * @version V1.0.0.0
+ * $Date:: 2017-08-09 11:01:04 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_hal.h"
+
+#if defined(__HAL_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup HAL
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_macro HAL Private Macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Private_macro */
+
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_define HAL Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_define HAL Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_define HAL Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_typedef HAL Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group HAL_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup HAL_Private_fuctions HAL Private Fuctions
+ * @{
+ */
+
+static uint32_t tick;
+
+/**
+ * @}
+ */ /* End of group HAL_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup HAL_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Increment a tick value.
+ * @param -
+ * @retval -
+ * @note Please call by user.
+ * @note In the sample, this variable is incremented each 1ms timer interrupt.
+ */
+/*--------------------------------------------------*/
+void hal_inc_tick(void)
+{
+ tick++;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Provides a tick value.
+ * @param -
+ * @return Tick value.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+uint32_t hal_get_tick(void)
+{
+ return(tick);
+}
+
+/**
+ * @}
+ */ /* End of group HAL_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group HAL */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__HAL_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_i2c.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,415 @@
+/**
+ *******************************************************************************
+ * @file txz_i2c.c
+ * @brief This file provides API functions for I2C Class.
+ * @version V1.0.0.2
+ * $Date:: 2016-11-08 00:00:00 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_i2c.h"
+
+#if defined(__I2C_H)
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @addtogroup UTILITIES
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_macro */
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Member */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_variables
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_variables */
+
+/*------------------------------------------------------------------------------*/
+/* Const Table */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_const
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief SCK Divider value table.
+ * @details SCK = b000 - b111.
+ * @note NFSEL=0 (Digital Setting) Divider value.
+*/
+/*----------------------------------*/
+static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20,24,32,48,80,144,272,528 };
+static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 };
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_const */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_functions
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_functions
+ * @{
+ */
+
+/*--------------------------------------------------*/
+/**
+ * @brief Initializing I2C Regester
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2C_init(I2C_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE;
+ p_obj->p_instance->OP = I2CxOP_INIT;
+ p_obj->p_instance->CR1 = (I2CxCR1_ACK | /* I2CxCR1_NOACK | */ p_obj->init.clock.sck);
+ p_obj->p_instance->AR = I2CxAR_INIT;
+ p_obj->p_instance->AR2 = I2CxAR2_INIT;
+ p_obj->p_instance->CR2 = I2CxCR2_INIT;
+ p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
+ p_obj->p_instance->IE = I2CxIE_CLEAR;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Generate start condition
+ * @param p_obj :I2C object.
+ * @param data :Slave address.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2C_start_condition(I2C_t *p_obj, uint32_t data)
+{
+ __IO uint32_t opreg;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ opreg = p_obj->p_instance->OP;
+ opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
+ if(I2C_master(p_obj)){
+ if ((p_obj->p_instance->SR & I2CxSR_BB))
+ {
+ opreg |= I2CxOP_SREN;
+ }
+ }
+ p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck);
+ p_obj->p_instance->OP = opreg;
+ p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
+ p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION;
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Return the I2c clock setting
+ * @param p_obj :I2C object.
+ * @param frequency :Maximum frequency.
+ * @param fsys :SystemCoreClock.
+ * @param p_setting :Clock data pointer.
+ * @retval Non-zero :Scl frequency.
+ * @retval 0 :Error.
+ * @note -
+ */
+/*--------------------------------------------------*/
+uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting)
+{
+ uint32_t result = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_setting));
+#endif /* #ifdef DEBUG */
+
+ if (frequency <= 1000000)
+ {
+ uint64_t sck, tmp_sck;
+ uint64_t prsck, tmp_prsck;
+ uint64_t fscl, tmp_fscl;
+ uint64_t fx;
+ uint64_t max_fx, min_fx;
+ uint64_t low_width,low_width_min;
+
+ sck = tmp_sck = 0;
+ prsck = tmp_prsck = 1;
+ fscl = tmp_fscl = 0;
+
+ if(frequency <= 400000)
+ {
+ max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */
+ min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */
+ low_width_min = 1600;
+ }
+ else
+ {
+ max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */
+ min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */
+ low_width_min = 675;
+ }
+ for (prsck = 1; prsck <= 32; prsck++)
+ {
+ fx = ((uint64_t)fsys / prsck);
+
+ if ((fx < max_fx) && (fx >= min_fx))
+ {
+ for (sck = 0; sck <= 7; sck++)
+ {
+ low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys;
+ if(low_width < low_width_min)
+ {
+ continue;
+ }
+ fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
+
+ if ((fscl <= frequency) && (fscl > tmp_fscl))
+ {
+ tmp_fscl = fscl;
+ tmp_sck = sck;
+ tmp_prsck = (prsck < 32)? prsck: 0;
+ }
+ }
+ }
+ }
+ result = (uint32_t)tmp_fscl;
+ p_setting->sck = (uint32_t)tmp_sck;
+ p_setting->prsck = (tmp_prsck < 32)? (uint32_t)tmp_prsck: 0;
+ }
+ else
+ {
+ result = 0;
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Slave mode setting.
+ * @param p_obj :I2C object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2C_slave_init(I2C_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ p_obj->p_instance->OP = I2CxOP_SLAVE_INIT;
+ p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck);
+ p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
+ p_obj->p_instance->CR2 = I2CxCR2_INIT;
+ p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
+ p_obj->p_instance->IE = 1;
+}
+#if defined(I2CSxWUP_EN)
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Wakeup Control setting.
+ * @param p_obj :I2CS object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2CS_init(I2CS_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ p_obj->p_instance->WUPCR1 = (p-obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Primary Slave Address setting.
+ * @param p_obj :I2CS object.
+ * @param addr :Primary Slave Address.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ p_obj->p_instance->WUPCR2 = (0x0000000E & adr);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Secondary Slave Address setting.
+ * @param p_obj :I2CS object.
+ * @param addr :Secondary Slave Address.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ p_obj->p_instance->WUPCR3 = (0x0000000E & adr);
+ p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */
+}
+#endif
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_functions */
+
+/**
+ * @}
+ */ /* End of group UTILITIES */
+
+/**
+ * @}
+ */ /* End of group Example */
+
+#endif /* defined(__I2C_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_i2c_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1865 @@
+/**
+ *******************************************************************************
+ * @file bsp_i2c.c
+ * @brief This file provides API functions for BSP I2C driver.
+ * @version V1.0.0.1
+ * $Date:: 2017-10-03 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_i2c_api.h"
+
+#if defined(__BSP_I2C_H)
+
+/**
+ * @addtogroup Example
+ * @{
+ */
+
+/**
+ * @addtogroup UTILITIES
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Macro Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_macro
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_macro */
+
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+
+/**
+ * @name Parameter Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of name Parameter Result */
+
+/**
+ * @name timeout
+ * @brief This timeouts are not based on accurate values, this just guarantee that
+ the application will not remain stuck if the I2C communication is corrupted.
+ * @{
+ */
+#define I2C_TIMEOUT (100000) /*>! fail safe. */
+
+/**
+ * @}
+ */ /* End of name timeout */
+
+#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+#define I2C_CH0 (0) /*!< I2C Channel 0. */
+#define I2C_CH1 (1) /*!< I2C Channel 1. */
+#define I2C_CH2 (2) /*!< I2C Channel 2. */
+#define I2C_CH3 (3) /*!< I2C Channel 3. */
+#define I2C_CH4 (4) /*!< I2C Channel 3. */
+#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_define
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief Transfer State.
+*/
+/*----------------------------------*/
+enum {
+ I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */
+ I2C_TRANSFER_STATE_BUSY /*!< Busy. */
+} TransferState;
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_define */
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_typedef
+ * @{
+ */
+
+/*----------------------------------*/
+/**
+ * @brief For IRQn_Type number definition.
+*/
+/*----------------------------------*/
+typedef struct
+{
+ IRQn_Type i2c;
+ IRQn_Type al;
+ IRQn_Type bf;
+ IRQn_Type na;
+} i2c_irq_t;
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Member */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_variables
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_variables */
+
+/*------------------------------------------------------------------------------*/
+/* Const Table */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_const
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief Channel 0 IRQn_Type number table.
+*/
+/*----------------------------------*/
+static const i2c_irq_t I2C_CH0_IRQN_TBL[1] =
+{
+ { INTI2C0_IRQn, INTI2C0AL_IRQn, INTI2C0BF_IRQn, INTI2C0NACK_IRQn }
+};
+
+/*----------------------------------*/
+/**
+ * @brief Channel 1 IRQn_Type number table.
+*/
+/*----------------------------------*/
+static const i2c_irq_t I2C_CH1_IRQN_TBL[1] =
+{
+ { INTI2C1_IRQn, INTI2C1AL_IRQn, INTI2C1BF_IRQn, INTI2C1NACK_IRQn }
+};
+
+/*----------------------------------*/
+/**
+ * @brief Channel 2 IRQn_Type number table.
+*/
+/*----------------------------------*/
+static const i2c_irq_t I2C_CH2_IRQN_TBL[1] =
+{
+ { INTI2C2_IRQn, INTI2C2AL_IRQn, INTI2C2BF_IRQn, INTI2C2NACK_IRQn }
+};
+
+/*----------------------------------*/
+/**
+ * @brief Channel 3 IRQn_Type number table.
+*/
+/*----------------------------------*/
+static const i2c_irq_t I2C_CH3_IRQN_TBL[1] =
+{
+ { INTI2C3_IRQn, INTI2C3AL_IRQn, INTI2C3BF_IRQn, INTI2C3NACK_IRQn }
+};
+
+/*----------------------------------*/
+/**
+ * @brief Channel 4 IRQn_Type number table.
+*/
+/*----------------------------------*/
+static const i2c_irq_t I2C_CH4_IRQN_TBL[1] =
+{
+ { INTI2C4_IRQn, INTI2C4AL_IRQn, INTI2C4BF_IRQn, INTI2C4NACK_IRQn }
+};
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_const */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Private_functions
+ * @{
+ */
+#ifdef DEBUG
+__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn);
+__STATIC_INLINE int32_t check_param_address(int32_t address);
+#endif
+__STATIC_INLINE void enable_irq(uint32_t irqn);
+__STATIC_INLINE void disable_irq(uint32_t irqn);
+__STATIC_INLINE void clear_irq(uint32_t irqn);
+__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl);
+__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl);
+__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl);
+__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl);
+__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl);
+__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn);
+__STATIC_INLINE void reset_asynch(_i2c_t *p_obj);
+__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj);
+static void i2c_irq_handler(_i2c_t *p_obj);
+static void i2c_slave_irq_handler(_i2c_t *p_obj);
+
+#ifdef DEBUG
+/*--------------------------------------------------*/
+/**
+ * @brief Compare the IRQn's parameter.
+ * @param irqn :I2C IRQn List.
+ * @retval I2C_PARAM_OK :Available.
+ * @retval I2C_PARAM_NG :Not Available.
+ * @note -.
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn)
+{
+ int32_t result = I2C_PARAM_NG;
+
+ if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL)
+ {
+ result = I2C_PARAM_OK;
+ }
+ if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL)
+ {
+ result = I2C_PARAM_OK;
+ }
+ if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL)
+ {
+ result = I2C_PARAM_OK;
+ }
+ if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL)
+ {
+ result = I2C_PARAM_OK;
+ }
+ if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL)
+ {
+ result = I2C_PARAM_OK;
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Compare the Slave address's parameter.
+ * @param address :Address.
+ * @retval I2C_PARAM_OK :Available.
+ * @retval I2C_PARAM_NG :Not Available.
+ * @note Here, 10bit address has not supported.
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_address(int32_t address)
+{
+ int32_t result = I2C_PARAM_NG;
+
+ if ((address >= 0) && (address <= 255))
+ {
+ result = I2C_PARAM_OK;
+ }
+ return (result);
+}
+#endif
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable I2C IRQ
+ * @param irqn :I2C IRQn List.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void enable_irq(uint32_t irqn)
+{
+ i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(check_param_irqn(irqn));
+#endif /* #ifdef DEBUG */
+ NVIC_EnableIRQ(p_irqn->i2c);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disable I2C IRQ
+ * @param irqn :I2C IRQn List.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void disable_irq(uint32_t irqn)
+{
+ i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(check_param_irqn(irqn));
+#endif /* #ifdef DEBUG */
+ NVIC_DisableIRQ(p_irqn->i2c);
+ NVIC_DisableIRQ(p_irqn->al);
+ NVIC_DisableIRQ(p_irqn->bf);
+ NVIC_DisableIRQ(p_irqn->na);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief ClearPending I2C IRQ
+ * @param irqn :I2C IRQn List.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void clear_irq(uint32_t irqn)
+{
+ i2c_irq_t *p_irqn = (i2c_irq_t *)irqn;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(check_param_irqn(irqn));
+#endif /* #ifdef DEBUG */
+ NVIC_ClearPendingIRQ(p_irqn->i2c);
+ NVIC_ClearPendingIRQ(p_irqn->al);
+ NVIC_ClearPendingIRQ(p_irqn->bf);
+ NVIC_ClearPendingIRQ(p_irqn->na);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Port Setting (PG2, PG3)
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl)
+{
+ if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3))
+ {
+ /* Port G */
+
+ /* SCL */
+ TSB_PG_IE_PG3IE = 0; /* Input :Disable */
+ TSB_PG_CR_PG3C = 0; /* Output :Disable */
+ TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */
+ TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */
+ TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */
+ TSB_PG_DATA_PG3 = 0; /* Data :0 */
+ TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */
+ TSB_PG_IE_PG3IE = 1; /* Input :Enable */
+ TSB_PG_CR_PG3C = 1; /* Output :Enable */
+
+ /* SDA */
+ TSB_PG_IE_PG2IE = 0; /* Input :Disable */
+ TSB_PG_CR_PG2C = 0; /* Output :Disable */
+ TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */
+ TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */
+ TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */
+ TSB_PG_DATA_PG2 = 0; /* Data :0 */
+ TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */
+ TSB_PG_IE_PG2IE = 1; /* Input :Enable */
+ TSB_PG_CR_PG2C = 1; /* Output :Enable */
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Port Setting (PF2, PF3)
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl)
+{
+ if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3))
+ {
+ /* Port F */
+
+ /* SCL */
+ TSB_PF_IE_PF3IE = 0; /* Input :Disable */
+ TSB_PF_CR_PF3C = 0; /* Output :Disable */
+ TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */
+ TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */
+ TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */
+ TSB_PF_DATA_PF3 = 0; /* Data :0 */
+ TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */
+ TSB_PF_IE_PF3IE = 1; /* Input :Enable */
+ TSB_PF_CR_PF3C = 1; /* Output :Enable */
+
+ /* SDA */
+ TSB_PF_IE_PF2IE = 0; /* Input :Disable */
+ TSB_PF_CR_PF2C = 0; /* Output :Disable */
+ TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */
+ TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */
+ TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */
+ TSB_PF_DATA_PF2 = 0; /* Data :0 */
+ TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */
+ TSB_PF_IE_PF2IE = 1; /* Input :Enable */
+ TSB_PF_CR_PF2C = 1; /* Output :Enable */
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Port Setting (PG4, PG5)
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl)
+{
+ if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5))
+ {
+ /* Port G */
+
+ /* SCL */
+ TSB_PG_IE_PG5IE = 0; /* Input :Disable */
+ TSB_PG_CR_PG5C = 0; /* Output :Disable */
+ TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */
+ TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */
+ TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */
+ TSB_PG_DATA_PG5 = 0; /* Data :0 */
+ TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */
+ TSB_PG_IE_PG5IE = 1; /* Input :Enable */
+ TSB_PG_CR_PG5C = 1; /* Output :Enable */
+
+ /* SDA */
+ TSB_PG_IE_PG4IE = 0; /* Input :Disable */
+ TSB_PG_CR_PG4C = 0; /* Output :Disable */
+ TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */
+ TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */
+ TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */
+ TSB_PG_DATA_PG4 = 0; /* Data :0 */
+ TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */
+ TSB_PG_IE_PG4IE = 1; /* Input :Enable */
+ TSB_PG_CR_PG4C = 1; /* Output :Enable */
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Port Setting (PM0, PM1)
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl)
+{
+ if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7))
+ {
+ /* Port M */
+
+ /* SCL */
+ TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */
+ TSB_PJ_CR_PJ6C = 0; /* Output :Disable */
+ TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */
+ TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */
+ TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */
+ TSB_PJ_DATA_PJ6 = 0; /* Data :0 */
+ TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */
+ TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */
+ TSB_PJ_CR_PJ6C = 1; /* Output :Enable */
+
+ /* SDA */
+ TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */
+ TSB_PJ_CR_PJ7C = 0; /* Output :Disable */
+ TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */
+ TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */
+ TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */
+ TSB_PJ_DATA_PJ7 = 0; /* Data :0 */
+ TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */
+ TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */
+ TSB_PJ_CR_PJ7C = 1; /* Output :Enable */
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Port Setting (PM6, PM7)
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl)
+{
+ if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3))
+ {
+ /* Port M */
+
+ /* SCL */
+ TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */
+ TSB_PJ_CR_PJ2C = 0; /* Output :Disable */
+ TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */
+ TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */
+ TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */
+ TSB_PJ_DATA_PJ2 = 0; /* Data :0 */
+ TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */
+ TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */
+ TSB_PJ_CR_PJ2C = 1; /* Output :Enable */
+
+ /* SDA */
+ TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */
+ TSB_PJ_CR_PJ3C = 0; /* Output :Disable */
+ TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */
+ TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */
+ TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */
+ TSB_PJ_DATA_PJ3 = 0; /* Data :0 */
+ TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */
+ TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */
+ TSB_PJ_CR_PJ3C = 1; /* Output :Enable */
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Setting
+ * @param ch :I2C Channel.
+ * @param p_irqn :Destination Address of a I2C IRQn List.
+ * @retval non-zero :Instance Address.
+ * @retval zero :Channel not supported.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn)
+{
+ uint32_t instance = 0;
+
+ switch (ch)
+ {
+ case I2C_CH0:
+ instance = (uint32_t)TSB_I2C0;
+ *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL;
+ break;
+
+ case I2C_CH1:
+ instance = (uint32_t)TSB_I2C1;
+ *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL;
+ break;
+
+ case I2C_CH2:
+ instance = (uint32_t)TSB_I2C2;
+ *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL;
+ break;
+
+ case I2C_CH3:
+ instance = (uint32_t)TSB_I2C3;
+ *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL;
+ break;
+
+ case I2C_CH4:
+ instance = (uint32_t)TSB_I2C4;
+ *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL;
+ break;
+
+ default:
+ break;
+ }
+ return (instance);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Reset Asynch Transfer
+ * @param p_obj :i2c object
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE void reset_asynch(_i2c_t *p_obj)
+{
+ disable_irq(p_obj->info.irqn);
+ I2C_disable_interrupt(&p_obj->i2c);
+}
+
+__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj)
+{
+#ifdef DEBUG
+ if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL))
+ {
+ return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL);
+ }
+ return (0);
+#else
+ return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL);
+#endif
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Waiting i2c status
+ * @param p_obj :i2c object
+ * @retval 0 :Success.
+ * @retval -1 :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj)
+{
+ int32_t timeout;
+
+ timeout = I2C_TIMEOUT;
+ while (!I2C_int_status(&p_obj->i2c))
+ {
+ if (I2C_status_arbitration(&p_obj->i2c))
+ {
+ volatile uint32_t dummy = 0;
+ dummy = I2C_read_data(&p_obj->i2c);
+ return (-5);
+ }
+ if ((timeout--) == 0)
+ {
+ return (-1);
+ }
+ }
+ if (I2C_status_arbitration(&p_obj->i2c))
+ {
+ volatile uint32_t dummy = 0;
+ dummy = I2C_read_data(&p_obj->i2c);
+ return (-5);
+ }
+ return (0);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Transfer handler
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note Called by i2c_irq_handler_asynch_t.
+ */
+/*--------------------------------------------------*/
+static void i2c_irq_handler(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ I2C_clear_int_status(&p_obj->i2c);
+
+ if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY))
+ {
+ p_obj->info.asynch.event = I2C_EVENT_ERROR;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ else
+ {
+ if (I2C_transmitter(&p_obj->i2c))
+ {
+ int32_t start = I2C_restart(&p_obj->i2c);
+
+ if (!I2C_get_ack(&p_obj->i2c))
+ {
+ if (p_obj->tx_buff.pos < p_obj->tx_buff.length)
+ {
+ I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]);
+ }
+ else if (p_obj->rx_buff.length != 0)
+ {
+ I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U));
+ }
+ else
+ {
+ if (p_obj->info.asynch.stop)
+ {
+ I2C_stop_condition(&p_obj->i2c);
+ }
+ p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ else
+ {
+ if (p_obj->tx_buff.pos < p_obj->tx_buff.length)
+ {
+ if (p_obj->tx_buff.pos == 0)
+ {
+ p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE);
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ else
+ {
+ p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ else if (p_obj->rx_buff.length != 0)
+ {
+ if (p_obj->tx_buff.pos == 0)
+ {
+ p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE);
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ else
+ {
+ p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK);
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ else
+ {
+ if (p_obj->info.asynch.stop)
+ {
+ I2C_stop_condition(&p_obj->i2c);
+ }
+ p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ }
+ else
+ {
+ int32_t start = I2C_restart(&p_obj->i2c);
+
+ if (p_obj->rx_buff.pos < p_obj->rx_buff.length)
+ {
+ if (!start)
+ {
+ p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c);
+ }
+ }
+ if (p_obj->rx_buff.pos < p_obj->rx_buff.length)
+ {
+ I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1)));
+ I2C_write_data(&p_obj->i2c, 0);
+ }
+ else
+ {
+ if (p_obj->info.asynch.stop)
+ {
+ I2C_stop_condition(&p_obj->i2c);
+ }
+ p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ }
+ if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE)
+ {
+ reset_asynch(p_obj);
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief I2C Transfer handler
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note Called by i2c_slave_irq_handler_asynch_t.
+ */
+/*--------------------------------------------------*/
+static void i2c_slave_irq_handler(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ I2C_clear_int_status(&p_obj->i2c);
+
+ if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY))
+ {
+ p_obj->info.asynch.event = I2C_EVENT_ERROR;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ else
+ {
+ int32_t start = I2C_slave_detected(&p_obj->i2c);
+ if (start)
+ {
+ uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c);
+ }
+ if (I2C_transmitter(&p_obj->i2c))
+ {
+ if (!I2C_get_ack(&p_obj->i2c))
+ {
+ if (p_obj->tx_buff.pos < p_obj->tx_buff.length)
+ {
+ I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]);
+ }
+ else
+ { /* dummy, wait nack */
+ I2C_write_data(&p_obj->i2c, 0);
+ }
+ }
+ else
+ {
+ /* error event not be set */
+ p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ else
+ {
+ if (p_obj->rx_buff.pos < p_obj->rx_buff.length)
+ {
+ if (!start)
+ {
+ p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c);
+ }
+ }
+ if (p_obj->rx_buff.pos < p_obj->rx_buff.length)
+ {
+ I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1)? 0: 1)));
+ I2C_write_data(&p_obj->i2c, 0);
+ }
+ else
+ {
+ p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ }
+ }
+ }
+ if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE)
+ {
+ reset_asynch(p_obj);
+ I2C_slave_init(&p_obj->i2c);
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Enable I2C IRQ
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void i2c_enable_irq(_i2c_t *p_obj)
+{
+ enable_irq(p_obj->info.irqn);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Disable I2C IRQ
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void i2c_disable_irq(_i2c_t *p_obj)
+{
+ disable_irq(p_obj->info.irqn);
+}
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UTILITIES_Exported_functions
+ * @{
+ */
+
+/*--------------------------------------------------*/
+/**
+ * @brief Initialize the I2C Driver
+ * @param p_obj :i2c object.
+ * @param sda :SDA port.
+ * @param scl :SCL port.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl)
+{
+ TXZ_Result result = TXZ_ERROR;
+ uint32_t instance = 0;
+ uint32_t irqn = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ /* ch0 */
+ if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3))
+ {
+ set_port_ch0(sda, scl);
+ instance = set_i2c(I2C_CH0, &irqn);
+ }
+ /* ch1 */
+ if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3))
+ {
+ set_port_ch1(sda, scl);
+ instance = set_i2c(I2C_CH1, &irqn);
+ }
+ /* ch2 */
+ if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5))
+ {
+ set_port_ch2(sda, scl);
+ instance = set_i2c(I2C_CH2, &irqn);
+ }
+ /* ch3 */
+ if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7))
+ {
+ set_port_ch3(sda, scl);
+ instance = set_i2c(I2C_CH3, &irqn);
+ }
+ /* ch4 */
+ if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3))
+ {
+ set_port_ch4(sda, scl);
+ instance = set_i2c(I2C_CH3, &irqn);
+ }
+
+ if ((instance != 0) && (irqn != 0))
+ {
+ disable_irq(irqn);
+ clear_irq(irqn);
+
+ /* Set irqn table */
+ p_obj->info.irqn = irqn;
+
+ /* Set instance */
+ p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance;
+
+ /* I2C Reset */
+ i2c_reset_t(p_obj);
+
+ /* Set Frequency Default at 100KHz */
+ if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS)
+ {
+ result = TXZ_SUCCESS;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Reset I2C peripheral
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void i2c_reset_t(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ /* Software reset */
+ I2C_reset(&p_obj->i2c);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Configure the I2C frequency
+ * @param p_obj :i2c object.
+ * @param hz :frequency in Hz.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz)
+{
+ TXZ_Result result = TXZ_ERROR;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ if (I2C_port_high(&p_obj->i2c))
+ {
+ uint32_t fval;
+
+ SystemCoreClockUpdate();
+
+ fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock);
+ if (fval != 0)
+ {
+ //I2C_init(&p_obj->i2c);
+ p_obj->info.bus_free = 0;
+ p_obj->info.start = 0;
+ p_obj->info.asynch.address = 0;
+ p_obj->info.asynch.stop = 0;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ p_obj->info.asynch.event = 0;
+ p_obj->tx_buff.p_buffer = I2C_NULL;
+ p_obj->tx_buff.length = 0;
+ p_obj->tx_buff.pos = 0;
+ p_obj->rx_buff.p_buffer = I2C_NULL;
+ p_obj->rx_buff.length = 0;
+ p_obj->rx_buff.pos = 0;
+ result = TXZ_SUCCESS;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check bus free on the I2C bus.
+ * @param p_obj :i2c object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ p_obj->info.bus_free = 1;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Creates a start condition on the I2C bus.
+ * @param p_obj :i2c object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.(now, not use)
+ * @note Start condition is not generate yet, after this function returned.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_start_t(_i2c_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ p_obj->info.start = 1;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Creates a stop condition on the I2C bus.
+ * @param p_obj :i2c object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Master and blocking function.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_stop_t(_i2c_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ int32_t timeout;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ I2C_stop_condition(&p_obj->i2c);
+ p_obj->info.bus_free = 0;
+ p_obj->info.start = 0;
+
+ timeout = I2C_TIMEOUT;
+ while (i2c_active_t(p_obj))
+ {
+ if ((timeout--) == 0)
+ {
+ result = TXZ_ERROR;
+ break;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Blocking reading data
+ * @param p_obj :i2c object.
+ * @param address :Slave address(7-bit) and last bit is 0.
+ * @param p_data :Address of Read data.
+ * @param length :Number of the bytes to read.
+ * @param stop :Stop to be generated after the transfer is done.
+ * @retval Number of read bytes.
+ * @note Master and blocking function.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop)
+{
+ int32_t result = 0;
+ int32_t count = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_data));
+ assert_param(check_param_address(address));
+#endif /* #ifdef DEBUG */
+
+ if (length > 0)
+ {
+ /* Start Condition */
+ if (i2c_start_t(p_obj) == TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U));
+ if (result == I2C_ACK)
+ {
+ /* Read all bytes */
+ while (count < length)
+ {
+ int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1))? 0: 1));
+ if (data < 0)
+ {
+ result = data;
+ break;
+ }
+ p_data[count++] = (uint8_t)data;
+ }
+ result = count;
+ }
+ else if (result == I2C_ERROR_ARBITRATION)
+ {
+ }
+ else if (result == (-2)) //I2C_ERROR_BUS_BUSY
+ {
+ }
+ else
+ {
+ stop = 1;
+ result = (-1) ;//I2C_ERROR_NO_SLAVE;
+ }
+ /* Stop Condition */
+ if (stop)
+ {
+ if (i2c_stop_t(p_obj) == TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Blocking sending data
+ * @param p_obj :i2c object.
+ * @param address :Slave address(7-bit) and last bit is 0.
+ * @param p_data :Destination address of Write data.
+ * @param length :Number of the bytes to write.
+ * @param stop :Stop to be generated after the transfer is done.
+ * @retval Number of write bytes.
+ * @note Master and blocking function.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop)
+{
+ int32_t result = 0;
+ int32_t count = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_data));
+ assert_param(check_param_address(address));
+#endif /* #ifdef DEBUG */
+
+ /* Start Condition */
+ if (i2c_start_t(p_obj) == TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ result = i2c_byte_write_t(p_obj, address);
+ if (result == I2C_ACK)
+ {
+ /* Write all bytes */
+ while (count < length)
+ {
+ int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]);
+ if (data < I2C_ACK)
+ {
+ result = data;
+ break;
+ }
+ }
+ if(result >=0){
+ result = count;
+ }
+ }
+ else if (result == I2C_ERROR_ARBITRATION)
+ {
+ }
+ else if (result == (-2)) //I2C_ERROR_BUS_BUSY
+ {
+ }
+ else
+ {
+ stop = 1;
+ result = (-1); //I2C_ERROR_NO_SLAVE;
+ }
+ /* Stop Condition */
+ if (stop)
+ {
+ if (i2c_stop_t(p_obj) == TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Read one byte
+ * @param p_obj :i2c object.
+ * @param last :last acknowledge.
+ * @retval The read byte (but -1 is timout error).
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last)
+{
+ int32_t result;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ I2C_clear_int_status(&p_obj->i2c);
+ I2C_set_ack(&p_obj->i2c, last);
+ I2C_write_data(&p_obj->i2c, 0);
+ result = wait_status(p_obj);
+ if (result < 0)
+ {
+ // result = -1;
+ }
+ else
+ {
+ result = (int32_t)I2C_read_data(&p_obj->i2c);
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Write one byte
+ * @param p_obj :i2c object.
+ * @param data :Write data.
+ * @retval 0 :NACK was received.
+ * @retval 1 :ACK was received.
+ * @retval -1 :Timout error.
+ * @note Macro definition of return values is @ref I2C_ACK.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data)
+{
+ int32_t result;
+ int32_t timeout;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ I2C_clear_int_status(&p_obj->i2c);
+ if (p_obj->info.start == 1)
+ {
+ p_obj->info.start = 0;
+ if (p_obj->info.bus_free == 1)
+ {
+ timeout = I2C_TIMEOUT;
+ while (i2c_active_t(p_obj))
+ {
+ if ((timeout--) == 0)
+ {
+ p_obj->info.bus_free = 0;
+ return (-1);
+ }
+ }
+ }
+ /* Start Condition */
+ I2C_start_condition(&p_obj->i2c, (uint32_t)data);
+ if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c)))
+ {
+ p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
+ p_obj->info.bus_free = 0;
+ if (I2C_status_arbitration(&p_obj->i2c))
+ {
+ return (-5);
+ }
+ return (-2);
+ }
+ }
+ else
+ {
+ I2C_write_data(&p_obj->i2c, (uint32_t)data);
+ }
+ p_obj->info.bus_free = 0;
+ result = wait_status(p_obj);
+ if (result < 0)
+ {
+ return (result);
+ }
+ if (!I2C_get_ack(&p_obj->i2c))
+ {
+ result = 1;
+ }
+ else
+ {
+ result = 0;
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Attempts to determine if the I2C bus is already in use
+ * @param p_obj :i2c object.
+ * @retval 0 :Non-active.
+ * @retval 1 :Active.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+uint8_t i2c_active_t(_i2c_t *p_obj)
+{
+ uint8_t result;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ if (I2C_status_busy(&p_obj->i2c))
+ {
+ result = 1;
+ }
+ else
+ {
+ result = 0;
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Start I2C asynchronous transfer
+ * @param p_obj :i2c object.
+ * @param p_tx :Buffer of write data.
+ * @param tx_length :Length of write data.
+ * @param p_rx :Buffer of read data.
+ * @param rx_length :Length of read data.
+ * @param address :Slave address(7-bit) and last bit is 0.
+ * @param stop :Stop to be generated after the transfer is done.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Master and non-blocking function.
+ * @note Events of this function will be notified on i2c_irq_handler_asynch_t.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop)
+{
+ TXZ_Result result = TXZ_ERROR;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(check_param_address(address));
+#endif /* #ifdef DEBUG */
+
+ if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE)
+ {
+ if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0)))
+ {
+ reset_asynch(p_obj);
+ I2C_clear_int_status(&p_obj->i2c);
+ clear_irq(p_obj->info.irqn);
+ p_obj->info.asynch.address = (uint32_t)address;
+ p_obj->info.asynch.event = 0;
+ p_obj->info.asynch.stop = (uint32_t)stop;
+ p_obj->tx_buff.p_buffer = p_tx;
+ p_obj->tx_buff.length = (uint32_t)tx_length;
+ p_obj->tx_buff.pos = 0;
+ p_obj->rx_buff.p_buffer = p_rx;
+ p_obj->rx_buff.length = (uint32_t)rx_length;
+ p_obj->rx_buff.pos = 0;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY;
+ I2C_enable_interrupt(&p_obj->i2c);
+ if ((tx_length == 0) && (rx_length != 0))
+ {
+ I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U));
+ }
+ else
+ {
+ I2C_start_condition(&p_obj->i2c, (uint32_t)address);
+ }
+ p_obj->info.bus_free = 0;
+ p_obj->info.start = 0;
+ enable_irq(p_obj->info.irqn);
+ result = TXZ_SUCCESS;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief The asynchronous IRQ handler
+ * @param p_obj :i2c object.
+ * @retval zero :Transfer in progress.
+ * @retval non-zero :Event information.
+ * @note Macro definition of return values is @ref I2C_Events.
+ * @attention This function should be implement as INTI2Cx_IRQHandler.
+ */
+/*--------------------------------------------------*/
+uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ i2c_irq_handler(p_obj);
+
+ return (p_obj->info.asynch.event & I2C_EVENT_ALL);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Abort asynchronous transfer
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note After error event occurred on i2c_irq_handler_asynch_t,
+ * @note call this function and clear error status.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void i2c_abort_asynch_t(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ reset_asynch(p_obj);
+ if (i2c_stop_t(p_obj) == TXZ_SUCCESS)
+ {
+ /* no processing */
+ }
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ i2c_reset_t(p_obj);
+ I2C_init(&p_obj->i2c);
+ clear_irq(p_obj->info.irqn);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Configure I2C as slave or master.
+ * @param p_obj :i2c object.
+ * @param enable_slave :Enable slave mode.
+ * @retval -
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ disable_irq(p_obj->info.irqn);
+
+ if (enable_slave)
+ {
+ I2C_slave_init(&p_obj->i2c);
+ }
+ else
+ {
+ /* Slave Disable Settings. */
+ i2c_reset_t(p_obj);
+ I2C_init(&p_obj->i2c);
+ }
+ p_obj->info.bus_free = 0;
+ p_obj->info.start = 0;
+ I2C_clear_int_status(&p_obj->i2c);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check to see if the I2C slave has been addressed.
+ * @param p_obj :i2c object.
+ * @retval I2C_NO_DATA :The slave has not been addressed.
+ * @retval I2C_READ_ADDRESSED :Read addresses.
+ * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support).
+ * @retval I2C_WRITE_ADDRESSED :Write addressed.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_slave_receive_t(_i2c_t *p_obj)
+{
+ int32_t result = I2C_NO_DATA;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ if (I2C_slave_detected(&p_obj->i2c))
+ {
+ uint32_t sa = I2C_read_data(&p_obj->i2c);
+
+ if (!I2C_transmitter(&p_obj->i2c))
+ {
+ result = I2C_WRITE_ADDRESSED;
+ }
+ else
+ {
+ result = I2C_READ_ADDRESSED;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Blocking reading data.
+ * @param p_obj :i2c object.
+ * @param p_data :Destination address of read data.
+ * @param length :Number of bytes to read.
+ * @retval Number of read bytes.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length)
+{
+ int32_t count = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_data));
+#endif /* #ifdef DEBUG */
+
+ /* Read all bytes */
+ while (count < length)
+ {
+ I2C_clear_int_status(&p_obj->i2c);
+ I2C_set_ack(&p_obj->i2c, ((count < (length - 1))? 0: 1));
+ I2C_write_data(&p_obj->i2c, 0);
+ if (wait_status(p_obj) < 0)
+ {
+ break;
+ }
+ if (I2C_slave_detected(&p_obj->i2c))
+ {
+ return (count);
+ }
+ p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c);
+ }
+ I2C_slave_init(&p_obj->i2c);
+ return (count);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Blocking sending data.
+ * @param p_obj :i2c object.
+ * @param p_data :Source address of write data.
+ * @param length :Number of bytes to write.
+ * @retval Number of written bytes.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length)
+{
+ int32_t count = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_data));
+#endif /* #ifdef DEBUG */
+
+ /* Write all bytes */
+ while (count < length)
+ {
+ I2C_clear_int_status(&p_obj->i2c);
+ I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]);
+ if (wait_status(p_obj) < 0)
+ {
+ break;
+ }
+ if (!I2C_get_ack(&p_obj->i2c))
+ {
+ /* continue */
+ }
+ else
+ {
+ break;
+ }
+ }
+ I2C_slave_init(&p_obj->i2c);
+ return (count);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Configure I2C slave address.
+ * @param p_obj :i2c object.
+ * @param address :Address to be set.
+ * @retval -
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(check_param_address((int32_t)address));
+#endif /* #ifdef DEBUG */
+
+ I2C_set_address(&p_obj->i2c, address);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Start I2C asynchronous transfer
+ * @param p_obj :i2c object.
+ * @param p_tx :Buffer of write data.
+ * @param tx_length :Length of write data.
+ * @param p_rx :Buffer of read data.
+ * @param rx_length :Length of read data.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Slave and non-blocking function.
+ * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length)
+{
+ TXZ_Result result = TXZ_ERROR;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE)
+ {
+ if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0)))
+ {
+ reset_asynch(p_obj);
+ I2C_clear_int_status(&p_obj->i2c);
+ clear_irq(p_obj->info.irqn);
+ p_obj->info.asynch.address = 0;
+ p_obj->info.asynch.event = 0;
+ p_obj->info.asynch.stop = 0;
+ p_obj->tx_buff.p_buffer = p_tx;
+ p_obj->tx_buff.length = (uint32_t)tx_length;
+ p_obj->tx_buff.pos = 0;
+ p_obj->rx_buff.p_buffer = p_rx;
+ p_obj->rx_buff.length = (uint32_t)rx_length;
+ p_obj->rx_buff.pos = 0;
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY;
+ I2C_enable_interrupt(&p_obj->i2c);
+ enable_irq(p_obj->info.irqn);
+ result = TXZ_SUCCESS;
+ }
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief The asynchronous IRQ handler
+ * @param p_obj :i2c object.
+ * @retval zero :Transfer in progress.
+ * @retval non-zero :Event information.
+ * @note Macro definition of return values is @ref I2C_Events.
+ * @attention This function should be implement as INTI2Cx_IRQHandler.
+ */
+/*--------------------------------------------------*/
+uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ i2c_slave_irq_handler(p_obj);
+
+ return (p_obj->info.asynch.event & I2C_EVENT_ALL);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Abort asynchronous transfer
+ * @param p_obj :i2c object.
+ * @retval -
+ * @note For a non-blocking function.
+ * @note After error event occurred on i2c_slave_irq_handler_asynch_t,
+ * @note call this function and clear error status.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void i2c_slave_abort_asynch_t(_i2c_t *p_obj)
+{
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif /* #ifdef DEBUG */
+
+ reset_asynch(p_obj);
+ p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE;
+ I2C_slave_init(&p_obj->i2c);
+ I2C_clear_int_status(&p_obj->i2c);
+ clear_irq(p_obj->info.irqn);
+}
+
+/**
+ * @}
+ */ /* End of group UTILITIES_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group UTILITIES */
+
+/**
+ * @}
+ */ /* End of group Example */
+
+#endif /* defined(__BSP_I2C_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_t32a.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2034 @@
+ /**
+ *******************************************************************************
+ * @file txz_t32a.c
+ * @brief This file provides API functions for T32A driver.
+ * @version V1.0.0.7
+ * $Date:: 2018-03-30 13:56:50 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_t32a.h"
+
+#if defined(__T32A_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup T32A
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Private_define T32A Private Define
+ * @{
+ */
+/**
+ * @name Parameter Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of name Parameter Result */
+/**
+ * @}
+ */ /* End of group T32A_Private_typedef */
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Private_define T32A Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group T32A_Private_define */
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Private_typedef T32A Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group T32A_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Member */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup T32A_Private_member T32A Private Member
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group T32A_Private_member */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup T32A_Private_fuctions TSPI Private Fuctions
+ * @{
+ */
+#ifdef DEBUG
+ __INLINE static int32_t check_param_mode_halt(uint32_t param);
+ __INLINE static int32_t check_param_mode_mode32(uint32_t param);
+ __INLINE static int32_t check_param_runx_sftstpx(uint32_t param);
+ __INLINE static int32_t check_param_runx_sftstax(uint32_t param);
+ __INLINE static int32_t check_param_runx_runx(uint32_t param);
+ __INLINE static int32_t check_param_crx_prsclx(uint32_t param);
+ __INLINE static int32_t check_param_crx_clkx(uint32_t param);
+ __INLINE static int32_t check_param_crx_wbfx(uint32_t param);
+ __INLINE static int32_t check_param_crx_updnx(uint32_t param);
+ __INLINE static int32_t check_param_crx_reldx(uint32_t param);
+ __INLINE static int32_t check_param_crx_stopx(uint32_t param);
+ __INLINE static int32_t check_param_crx_startx(uint32_t param);
+ __INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param);
+ __INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param);
+ __INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param);
+ __INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param);
+ __INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param);
+ __INLINE static int32_t check_param_capcrx_capmx1(uint32_t param);
+ __INLINE static int32_t check_param_capcrx_capmx0(uint32_t param);
+ __INLINE static int32_t check_param_rgx0_rgx0(uint32_t param);
+ __INLINE static int32_t check_param_rgx1_rgx1(uint32_t param);
+ __INLINE static int32_t check_param_reldx_reld(uint32_t param);
+ __INLINE static int32_t check_param_imx_imsterr(uint32_t param);
+ __INLINE static int32_t check_param_imx_imufx(uint32_t param);
+ __INLINE static int32_t check_param_imx_imofx(uint32_t param);
+ __INLINE static int32_t check_param_imx_imx1(uint32_t param);
+ __INLINE static int32_t check_param_imx_imx0(uint32_t param);
+ __INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param);
+ __INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param);
+ __INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param);
+ __INLINE static int32_t check_param_pls_cr_pdn(uint32_t param);
+ __INLINE static int32_t check_param_pls_cr_pup(uint32_t param);
+ __INLINE static int32_t check_param_pls_cr_nf(uint32_t param);
+ __INLINE static int32_t check_param_pls_cr_pdir(uint32_t param);
+ __INLINE static int32_t check_param_pls_cr_pmode(uint32_t param);
+#endif
+
+#ifdef DEBUG
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Mode HALT's parameter.
+ * @param param :Mode HALT's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_HALT
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_mode_halt(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_DBG_HALT_RUN:
+ case T32A_DBG_HALT_STOP:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Mode mode32's parameter.
+ * @param param :Mode mode32's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_MODE32
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_mode_mode32(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_MODE_16:
+ case T32A_MODE_32:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the SW Counter STOP Control's parameter.
+ * @param param :SW Counter STOP Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_SFTSTPx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_runx_sftstpx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_COUNT_DONT_STOP:
+ case T32A_COUNT_STOP:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the SW START Control's parameter.
+ * @param param :SW START Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_SFTSTAx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_runx_sftstax(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_COUNT_DONT_START:
+ case T32A_COUNT_START:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A RUN Disable/Enable Control's parameter.
+ * @param param :T32A RUN Disable/Enable Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PRSCLx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_runx_runx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_RUN_DISABLE:
+ case T32A_RUN_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A PRESCALER Control's parameter.
+ * @param param :T32A PRESCALER Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PRSCLx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_prsclx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_PRSCLx_1:
+ case T32A_PRSCLx_2:
+ case T32A_PRSCLx_8:
+ case T32A_PRSCLx_32:
+ case T32A_PRSCLx_128:
+ case T32A_PRSCLx_256:
+ case T32A_PRSCLx_512:
+ case T32A_PRSCLx_1024:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A PRESCALER Control's parameter.
+ * @param param :T32A PRESCALER Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_CLKx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_clkx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_CLKx_PRSCLx:
+ case T32A_CLKx_INTRG:
+ case T32A_CLKx_TIM_RISING_EDGE:
+ case T32A_CLKx_TIM_TRAILING_EDGE:
+ case T32A_CLKx_EXTTRG_RISING_EDGE:
+ case T32A_CLKx_EXTTRG_TRAILING_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Double Buffer Disable/Enable Control's parameter.
+ * @param param :Double Buffer Disable/Enable Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_WBFx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_wbfx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_WBF_DISABLE:
+ case T32A_WBF_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Counter Up/Down Control's parameter.
+ * @param param :T32A Counter Up/Down Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_UPDNx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_updnx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_COUNT_UP:
+ case T32A_COUNT_DOWN:
+ case T32A_COUNT_UPDOWN:
+ case T32A_COUNT_PLS:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Counter Reload Control's parameter.
+ * @param param :T32A Counter Reload Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_RELDx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_reldx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_RELOAD_NON:
+ case T32A_RELOAD_INTRG:
+ case T32A_RELOAD_EXTTRG_RISING_EDGE:
+ case T32A_RELOAD_EXTTRG_TRAILING_EDGE:
+ case T32A_RELOAD_TIM_RISING_EDGE:
+ case T32A_RELOAD_TIM_TRAILING_EDGE:
+ case T32A_RELOAD_SYNC:
+ case T32A_RELOAD_TREGx:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Counter Stop Control's parameter.
+ * @param param :T32A Counter Stop Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_STOPx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_stopx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_STOP_NON:
+ case T32A_STOP_INTRG:
+ case T32A_STOP_EXTTRG_RISING_EDGE:
+ case T32A_STOP_EXTTRG_TRAILING_EDGE:
+ case T32A_STOP_TIM_RISING_EDGE:
+ case T32A_STOP_TIM_TRAILING_EDGE:
+ case T32A_STOP_SYNC:
+ case T32A_STOP_TREGx:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Counter Start Control's parameter.
+ * @param param :T32A Counter Start Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_STARTx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_crx_startx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_START_NON:
+ case T32A_START_INTRG:
+ case T32A_START_EXTTRG_RISING_EDGE:
+ case T32A_START_EXTTRG_TRAILING_EDGE:
+ case T32A_START_TIM_RISING_EDGE:
+ case T32A_START_TIM_TRAILING_EDGE:
+ case T32A_START_SYNC:
+ result = PARAM_OK;
+ break;
+ case T32A_START_Rsvd:
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32AxOUTA Control's parameter.
+ * @param param :T32AxOUTA Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_OCRx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_OCR_DISABLE:
+ case T32A_OCR_SET:
+ case T32A_OCR_CLR:
+ case T32A_OCR_INVERSION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter.
+ * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_OCRCAPx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_OCRCAPx1_DISABLE:
+ case T32A_OCRCAPx1_SET:
+ case T32A_OCRCAPx1_CLR:
+ case T32A_OCRCAPx1_INVERSION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter.
+ * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_OCRCAPx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_OCRCAPx0_DISABLE:
+ case T32A_OCRCAPx0_SET:
+ case T32A_OCRCAPx0_CLR:
+ case T32A_OCRCAPx0_INVERSION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter.
+ * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_OCRCMPx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_OCRCMPx1_DISABLE:
+ case T32A_OCRCMPx1_SET:
+ case T32A_OCRCMPx1_CLR:
+ case T32A_OCRCMPx1_INVERSION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter.
+ * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_OCRCMPx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_OCRCMPx0_DISABLE:
+ case T32A_OCRCMPx0_SET:
+ case T32A_OCRCMPx0_CLR:
+ case T32A_OCRCMPx0_INVERSION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Capture Control Register A1's parameter.
+ * @param param :T32A Capture Control Register A1's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_CAPMx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_CAPMx1_DISABLE:
+ case T32A_CAPMx1_INTRG:
+ case T32A_CAPMx1_INx0_RISING_EDGE:
+ case T32A_CAPMx1_INx0_TRAILING_EDGE:
+ case T32A_CAPMx1_INx1_RISING_EDGE:
+ case T32A_CAPMx1_INx1_TRAILING_EDGE:
+ case T32A_CAPMx1_TIM_RISING_EDGE:
+ case T32A_CAPMx1_TIM_TRAILING_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Capture Control Register A0's parameter.
+ * @param param :T32A Capture Control Register A0's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_CAPMx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_CAPMx0_DISABLE:
+ case T32A_CAPMx0_INTRG:
+ case T32A_CAPMx0_INx0_RISING_EDGE:
+ case T32A_CAPMx0_INx0_TRAILING_EDGE:
+ case T32A_CAPMx0_INx1_RISING_EDGE:
+ case T32A_CAPMx0_INx1_TRAILING_EDGE:
+ case T32A_CAPMx0_TIM_RISING_EDGE:
+ case T32A_CAPMx0_TIM_TRAILING_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Timer Register A0's parameter.
+ * @param param :T32A Timer Register A0's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_RGx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ if (param <= T32A_RGx0_MASK){
+ result = PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Timer Register A1's parameter.
+ * @param param :T32A Timer Register A1's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_RGx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ if (param <= T32A_RGx1_MASK){
+ result = PARAM_OK;
+ }
+
+ return (result);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Counter Reload Register A's parameter.
+ * @param param :T32A Counter Reload Register A's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_RELD
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_reldx_reld(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ if (param <= T32A_RELDx_MASK){
+ result = PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Statuserr Interrupt Request MASK's parameter.
+ * @param param :T32A Statuserr Interrupt Request MASK's parameter.
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_IMSTEER
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_imx_imsterr(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_IMSTERR_MASK_NOREQ:
+ case T32A_IMSTERR_MASK_REQ:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Overflow Interrupt Request MASK's parameter.
+ * @param param :T32A Overflow Interrupt Request MASK's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_IMUFx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_imx_imufx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_IMOFx_MASK_NOREQ:
+ case T32A_IMOFx_MASK_REQ:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Overflow Interrupt Request MASK's parameter.
+ * @param param :T32A Overflow Interrupt Request MASK's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_IMOFx
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_imx_imofx(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_IMOFx_MASK_NOREQ:
+ case T32A_IMOFx_MASK_REQ:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter.
+ * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_IMx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_imx_imx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_IMx1_MASK_NOREQ:
+ case T32A_IMx1_MASK_REQ:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter.
+ * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_IMx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_imx_imx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_IMx0_MASK_NOREQ:
+ case T32A_IMx0_MASK_REQ:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A DMA Converter1 Request control's parameter.
+ * @param param :T32A DMA Converter1 Request control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_DMAENx2
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_DMAENx2_DISABLE:
+ case T32A_DMAENx2_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A DMA InputCapture1 Request control's parameter.
+ * @param param :T32A DMA InputCapture1 Request control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_DMAENx1
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_DMAENx1_DISABLE:
+ case T32A_DMAENx1_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A DMA InputCapture0 Request control's parameter.
+ * @param param :T32A DMA InputCapture0 Request control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_DMAENx0
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_DMAENx0_DISABLE:
+ case T32A_DMAENx0_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Pulse Mode Count Down Control's parameter.
+ * @param param :T32A Pulse Mode Count Down Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PDN
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_PDN_NON0:
+ case T32A_PDN_NON1:
+ case T32A_PDN_INC0_RISING_EDGE:
+ case T32A_PDN_INC0_TRAILING_EDGE:
+ case T32A_PDN_INC1_RISING_EDGE:
+ case T32A_PDN_INC1_TRAILING_EDGE:
+ case T32A_PDN_INC0_BOTH_EDGE:
+ case T32A_PDN_INC1_BOTH_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Pulse Mode Count UP Control's parameter.
+ * @param param :T32A Pulse Mode Count UP Control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PUP
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_pls_cr_pup(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_PUP_NON0:
+ case T32A_PUP_NON1:
+ case T32A_PUP_INC0_RISING_EDGE:
+ case T32A_PUP_INC0_TRAILING_EDGE:
+ case T32A_PUP_INC1_RISING_EDGE:
+ case T32A_PUP_INC1_TRAILING_EDGE:
+ case T32A_PUP_INC0_BOTH_EDGE:
+ case T32A_PUP_INC1_BOTH_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Noise Filter control's parameter.
+ * @param param :T32A Noise Filter control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_NF
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_pls_cr_nf(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_NF_NON:
+ case T32A_NF_2:
+ case T32A_NF_4:
+ case T32A_NF_8:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Phase 2 Pulse Direction control's parameter.
+ * @param param :T32A Phase 2 Pulse Direction control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PDIR
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_PDIR_FORWARD:
+ case T32A_PDIR_BACKWARD:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the T32A Pulse Count Mode control's parameter.
+ * @param param :T32A Pulse Count Mode control's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref T32A_PMODE
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case T32A_PMODE_PHASE_2:
+ case T32A_PMODE_PHASE_1:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+
+
+
+#endif
+/**
+ * @}
+ */ /* End of group T32A_Private_functions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup T32A_Exported_functions
+
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Mode Initialize the T32A object.
+ * @param p_obj :T32A object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_mode_init(t32a_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ check_param_mode_halt(p_obj->init_mode.mode.halt);
+ check_param_mode_mode32(p_obj->init_mode.mode.mode);
+#endif /* DEBUG */
+ /* Timer Mode Set */
+ p_obj->p_instance->MOD = 0;
+ p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode);
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Initialize the T32A object.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_timer_init(t32a_t *p_obj,uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ /* Check the parameter of TimerA Mode Set */
+ check_param_mode_halt(p_obj->init_mode.mode.halt);
+ check_param_mode_mode32(p_obj->init_mode.mode.mode);
+ /* Check the parameter of TimerA Run Control Set */
+ check_param_runx_sftstpx(p_obj->init[type].runx.sftstp);
+ check_param_runx_sftstax(p_obj->init[type].runx.sftsta);
+ check_param_runx_runx(p_obj->init[type].runx.run);
+ /* Check the parameter of Counter Register Control Set */
+ check_param_crx_prsclx(p_obj->init[type].crx.prscl);
+ check_param_crx_clkx(p_obj->init[type].crx.clk);
+ check_param_crx_wbfx(p_obj->init[type].crx.wbf);
+ check_param_crx_updnx(p_obj->init[type].crx.updn);
+ check_param_crx_reldx(p_obj->init[type].crx.reld);
+ check_param_crx_stopx(p_obj->init[type].crx.stop);
+ check_param_crx_startx(p_obj->init[type].crx.start);
+ /* Check the parameter of TimerA Output Control Set */
+ check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr);
+ /* Check the parameter of T32AxOUTA Control Set */
+ check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1);
+ check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0);
+ check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1);
+ check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0);
+ /* Check the parameter of Capture Control Set */
+ check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1);
+ check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0);
+ /* Check the parameter of T32A Timer Register 0 Set */
+ check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0);
+ /* Check the parameter of T32A Timer Register 1 Set */
+ check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1);
+ /* Check the parameter of T32A Counter Reload Register Set */
+ check_param_reldx_reld(p_obj->init[type].reldx.reld);
+ /* Check the parameter of Interrupt mask register Set */
+ check_param_imx_imsterr(p_obj->init[type].imx.imsterr);
+ check_param_imx_imufx(p_obj->init[type].imx.imuf);
+ check_param_imx_imofx(p_obj->init[type].imx.imof);
+ check_param_imx_imx1(p_obj->init[type].imx.imx1);
+ check_param_imx_imx0(p_obj->init[type].imx.imx0);
+ /* Check the parameter of DMA Request register Set */
+ check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2);
+ check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1);
+ check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0);
+#endif
+
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A */
+ if(p_obj->init_mode.mode.mode != T32A_MODE_16) {
+ result = TXZ_ERROR;
+ return (result);
+ }
+ /* TimerA Run Control Disable */
+ p_obj->p_instance->RUNA = 0;
+ /* Counter Register Control Set */
+ p_obj->p_instance->CRA = 0;
+ p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \
+ p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start );
+ /* TimerA Output Control Set */
+ p_obj->p_instance->OUTCRA0 = 0;
+ p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr;
+ /* T32AxOUTA Control Set */
+ p_obj->p_instance->OUTCRA1 = 0;
+ p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \
+ p_obj->init[type].outcrx1.ocrcmp0 );
+ /* T32A Timer Register A0 Set */
+ p_obj->p_instance->RGA0 = 0;
+ p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0;
+ /* T32A Timer Register A1 Set */
+ p_obj->p_instance->RGA1 = 0;
+ p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1;
+ /* T32A Counter Reload Register Set */
+ p_obj->p_instance->RELDA = 0;
+ p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld;
+ /* TimerB Capture Control Set */
+ p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1);
+ /* Interrupt mask register Set */
+ p_obj->p_instance->IMA = 0;
+ p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \
+ p_obj->init[type].imx.imx0 );
+ /* DMA Request register Set */
+ p_obj->p_instance->DMAA = 0;
+ p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 );
+ /* TimerA Run Control Set */
+ p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run);
+ break;
+ case T32A_TIMERB:
+ /* Timer B */
+ if(p_obj->init_mode.mode.mode != T32A_MODE_16) {
+ result = TXZ_ERROR;
+ return (result);
+ }
+ /* TimerB Run Control Disable */
+ p_obj->p_instance->RUNB = 0;
+ /* Counter Register Control Set */
+ p_obj->p_instance->CRB = 0;
+ p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \
+ p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start );
+ /* TimerB Output Control Set */
+ p_obj->p_instance->OUTCRB0 = 0;
+ p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr;
+ /* T32AxOUTB Control Set */
+ p_obj->p_instance->OUTCRB1 = 0;
+ p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \
+ p_obj->init[type].outcrx1.ocrcmp0 );
+ /* T32A Timer Register B0 Set */
+ p_obj->p_instance->RGB0 = 0;
+ p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0;
+ /* T32A Timer Register B1 Set */
+ p_obj->p_instance->RGB1 = 0;
+ p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1;
+ /* T32A Counter Reload Register Set */
+ p_obj->p_instance->RELDB = 0;
+ p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld;
+ /* TimerB Capture Control Set */
+ p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1);
+ /* Interrupt mask register Set */
+ p_obj->p_instance->IMB = 0;
+ p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \
+ p_obj->init[type].imx.imx0 );
+ /* DMA Request register Set */
+ p_obj->p_instance->DMAB = 0;
+ p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 );
+ /* TimerB Run Control Set */
+ p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run);
+ break;
+ case T32A_TIMERC:
+ /* Timer C */
+ if(p_obj->init_mode.mode.mode != T32A_MODE_32) {
+ result = TXZ_ERROR;
+ return (result);
+ }
+ /* TimerC Run Control Disable */
+ p_obj->p_instance->RUNC = 0;
+ #ifdef DEBUG
+ /* Pulse Count Control register Set */
+ check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn);
+ check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup);
+ check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf);
+ check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir);
+ check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode);
+ #endif
+ /* Counter Register Control Set */
+ p_obj->p_instance->CRC = 0;
+ p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \
+ p_obj->init[type].crx.reld | p_obj->init[type].crx.stop |p_obj->init[type].crx.start );
+ /* TimerC Output Control Set */
+ p_obj->p_instance->OUTCRC0 = 0;
+ p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr;
+ /* T32AxOUTC Control Set */
+ p_obj->p_instance->OUTCRC1 = 0;
+ p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \
+ p_obj->init[type].outcrx1.ocrcmp0 );
+ /* T32A Timer Register C0 Set */
+ p_obj->p_instance->RGC0 = 0;
+ p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0;
+ /* T32A Timer Register C1 Set */
+ p_obj->p_instance->RGC1 = 0;
+ p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1;
+ /* T32A Counter Reload Register Set */
+ p_obj->p_instance->RELDC = 0;
+ p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld;
+ /* TimerC Capture Control Set */
+ p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1);
+ /* Interrupt mask register Set */
+ p_obj->p_instance->IMC = 0;
+ p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \
+ p_obj->init[type].imx.imx0 );
+ /* DMA Request register Set */
+ p_obj->p_instance->DMAC = 0;
+ p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0 );
+ /* Pulse Count Control register Set */
+ p_obj->p_instance->PLSCR = 0;
+ p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \
+ p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode);
+ /* TimerC Run Control Set */
+ p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run);
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Release the T32A object.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A */
+ /* Disable the selected T32A peripheral */
+ p_obj->p_instance->RUNA = T32A_RUN_DISABLE;
+ break;
+ case T32A_TIMERB:
+ /* Timer B */
+ /* Disable the selected T32A peripheral */
+ p_obj->p_instance->RUNB = T32A_RUN_DISABLE;
+ break;
+ case T32A_TIMERC:
+ /* Timer C */
+ /* Disable the selected T32A peripheral */
+ p_obj->p_instance->RUNC = T32A_RUN_DISABLE;
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Start in interrupt mode.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){
+ /* Timer A RUN */
+ p_obj->p_instance->RUNA |= T32A_RUN_ENABLE;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ case T32A_TIMERB:
+ if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){
+ /* Timer B RUN */
+ p_obj->p_instance->RUNB |= T32A_RUN_ENABLE;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ case T32A_TIMERC:
+ if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){
+ /* Timer C RUN */
+ p_obj->p_instance->RUNC |= T32A_RUN_ENABLE;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Stop in interrupt mode.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A Stop */
+ p_obj->p_instance->RUNA = T32A_RUN_DISABLE;
+ break;
+ case T32A_TIMERB:
+ /* Timer B Stop */
+ p_obj->p_instance->RUNB = T32A_RUN_DISABLE;
+ break;
+ case T32A_TIMERC:
+ /* SW Counter Stop & Timer C Stop */
+ p_obj->p_instance->RUNC = T32A_RUN_DISABLE;
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Start in interrupt mode.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ if(((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0){
+ /* Timer A SW Counter start */
+ p_obj->p_instance->RUNA |= T32A_COUNT_START;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ case T32A_TIMERB:
+ if(((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0){
+ /* Timer SW Counter start */
+ p_obj->p_instance->RUNB |= T32A_COUNT_START;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ case T32A_TIMERC:
+ if(((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0){
+ /* Timer C SW Counter start */
+ p_obj->p_instance->RUNC |= T32A_COUNT_START;
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Stop in interrupt mode.
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* TimerA SW Counter Stop */
+ p_obj->p_instance->RUNA = T32A_COUNT_STOP;
+ break;
+ case T32A_TIMERB:
+ /* Timer B SW Counter Stop */
+ p_obj->p_instance->RUNB = T32A_COUNT_STOP;
+ break;
+ case T32A_TIMERC:
+ /* Timer C SW Counter Stop */
+ p_obj->p_instance->RUNC = T32A_COUNT_STOP;
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Register Value Setting
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @param num :T32A Register Number. : Use @ref t32_regnum_t
+ * @param value :Setting Value.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A */
+ if(num == T32A_REG0) {p_obj->p_instance->RGA0 = value;}
+ else if(num == T32A_REG1) {p_obj->p_instance->RGA1 = value;}
+ else if(num == T32A_RELOAD) {p_obj->p_instance->RELDA = value;}
+ break;
+ case T32A_TIMERB:
+ /* Timer B */
+ if(num == T32A_REG0) {p_obj->p_instance->RGB0 = value;}
+ else if(num == T32A_REG1) {p_obj->p_instance->RGB1 = value;}
+ else if(num == T32A_RELOAD) {p_obj->p_instance->RELDB = value;}
+ break;
+ case T32A_TIMERC:
+ /* Timer C */
+ if(num == T32A_REG0) {p_obj->p_instance->RGC0 = value;}
+ else if(num == T32A_REG1) {p_obj->p_instance->RGC1 = value;}
+ else if(num == T32A_RELOAD) {p_obj->p_instance->RELDC = value;}
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Timer Register Value Read
+ * @param p_obj :T32A object.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @param p_val :Save area for register value.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A */
+ *p_val = p_obj->p_instance->TMRA;
+ break;
+ case T32A_TIMERB:
+ /* Timer B */
+ *p_val = p_obj->p_instance->TMRB;
+ break;
+ case T32A_TIMERC:
+ /* Timer C */
+ *p_val = p_obj->p_instance->TMRC;
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Get status.
+ * @details Status bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-4 | - | - |
+ * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. |
+ * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. |
+ * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. |
+ * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. |
+ *
+ * @param p_obj :T32A object.
+ * @param p_status :Save area for status.
+ * @param type :T32A Timer Type. : Use @ref t32_type_t
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_status));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Status Read */
+ /*------------------------------*/
+ switch (type)
+ {
+ case T32A_TIMERA:
+ /* Timer A */
+ *p_status = p_obj->p_instance->STA;
+ break;
+ case T32A_TIMERB:
+ /* Timer B */
+ *p_status = p_obj->p_instance->STB;
+ break;
+ case T32A_TIMERC:
+ /* Timer C */
+ *p_status = p_obj->p_instance->STC;
+ break;
+ default:
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for Timer interrupt.
+ * @param p_obj :T32A object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void t32a_timer_IRQHandler(t32a_t *p_obj)
+{
+ uint32_t status_a, status_b, status_c;
+ /*------------------------------*/
+ /* Get Status */
+ /*------------------------------*/
+ (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA);
+ (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB);
+ (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC);
+
+ if(status_a != 0){
+ /*------------------------------*/
+ /* Call Handler Timer A */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS);
+ }
+ }
+ if(status_b != 0){
+ /*------------------------------*/
+ /* Call Handler Timer B */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS);
+ }
+ }
+ if(status_c != 0){
+ /*------------------------------*/
+ /* Call Handler Timer C */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS);
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt.
+ * @param p_obj :T32A object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void t32a_timer_cap0_IRQHandler(t32a_t *p_obj)
+{
+ uint32_t status_a, status_b, status_c;
+ /*------------------------------*/
+ /* Get Status */
+ /*------------------------------*/
+ (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA);
+ (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB);
+ (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC);
+
+ if(status_a != 0){
+ /*------------------------------*/
+ /* Call Handler Timer A */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS);
+ }
+ }
+ if(status_b != 0){
+ /*------------------------------*/
+ /* Call Handler Timer B */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS);
+ }
+ }
+ if(status_c != 0){
+ /*------------------------------*/
+ /* Call Handler Timer C */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS);
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt.
+ * @param p_obj :T32A object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note An initial value of default is set at the
+ reset status value. If needed, please
+ rewrite and use an initial value.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+void t32a_timer_cap1_IRQHandler(t32a_t *p_obj)
+{
+ uint32_t status_a, status_b, status_c;
+ /*------------------------------*/
+ /* Get Status */
+ /*------------------------------*/
+ (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA);
+ (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB);
+ (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC);
+
+ if(status_a != 0){
+ /*------------------------------*/
+ /* Call Handler Timer A */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS);
+ }
+ }
+ if(status_b != 0){
+ /*------------------------------*/
+ /* Call Handler Timer B */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS);
+ }
+ }
+ if(status_c != 0){
+ /*------------------------------*/
+ /* Call Handler Timer C */
+ /*------------------------------*/
+ if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL)
+ {
+ /* Call the handler with Status Register Value & SUCCESS. */
+ p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c,TXZ_SUCCESS);
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Calculate timer value to set timer register.
+ * @param p_value: time value store pointer.
+ * @param time: The require period which the uint is us.
+ * @param prescaler: System Clock Freq
+ * @param prscl: Select the division for source clock @ref T32A_PRSCLx.
+ * @retval the value set to Tmrb timer register.
+ */
+/*--------------------------------------------------*/
+TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint64_t denominator;
+ uint64_t numerator;
+ uint32_t div;
+
+ /* div */
+ switch (prscl)
+ {
+ case T32A_PRSCLx_1:
+ div = 1;
+ break;
+ case T32A_PRSCLx_2:
+ div = 2;
+ break;
+ case T32A_PRSCLx_8:
+ div = 8;
+ break;
+ case T32A_PRSCLx_32:
+ div = 32;
+ break;
+ case T32A_PRSCLx_128:
+ div = 128;
+ break;
+ case T32A_PRSCLx_256:
+ div = 256;
+ break;
+ case T32A_PRSCLx_512:
+ div = 512;
+ break;
+ case T32A_PRSCLx_1024:
+ div = 1024;
+ break;
+ default:
+ div = 1;
+ break;
+ }
+ /*-----------------------------------------------*/
+ /* "1"counter (s) = 1 / fs */
+ /* "1"counter (s) = 1 / (prescaler / div) */
+ /* "1"counter (us) = (10^6) / (prescaler / div) */
+ /* "1"counter (us) = ((10^6) * div)/prescaler */
+ /* "x"counter (us) = time */
+ /*-----------------------------------------------*/
+ /* x : time = 1 : ((10^6) * div)/prescaler */
+ /*-----------------------------------------------*/
+ /* x = time / (((10^6) * div)/prescaler) */
+ /* = (prescaler * time) / ((10^6) * div) */
+ /*-----------------------------------------------*/
+ denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time));
+ numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div);
+ denominator = (uint64_t)(denominator / numerator);
+ /* result */
+ if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF)))
+ {
+ result = TXZ_ERROR;
+ }
+ else
+ {
+ *p_value = (uint32_t)denominator;
+ }
+
+ return (result);
+}
+
+/**
+ * @}
+ */ /* End of group T32A_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group T32A */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__T32A_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_tspi.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,2830 @@
+/**
+ *******************************************************************************
+ * @file txz_tspi.c
+ * @brief This file provides API functions for TSPI driver.
+ * @version V1.0.0.0
+ * $Date:: 2018-01-25 17:07:20 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_tspi.h"
+
+#if defined(__TSPI_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup TSPI
+ * @{
+ */
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Private_define TSPI Private Define
+ * @{
+ */
+/**
+ * @name TSPI NULL Pointer
+ * @brief Null Pointer for TSPI
+ * @{
+ */
+#define TSPI_NULL ((void *)0) /*!< NULL pointer. */
+/**
+ * @}
+ */ /* End of name TSPI NULL Pointer */
+
+/**
+ * @name Parameter Result
+ * @brief Whether the parameter is specified or not.
+ * @{
+ */
+#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
+#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
+/**
+ * @}
+ */ /* End of name Parameter Result */
+
+/**
+ * @name FIFO Max Num.
+ * @brief Transfer's/Receive's FIFO Max Num.
+ * @{
+ */
+#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */
+#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */
+/**
+ * @}
+ */ /* End of name FIFO Max Num */
+
+/**
+ * @name TSPIxDR_MASK Macro Definition.
+ * @brief TSPIxDR_MASK Macro Definition.
+ * @{
+ */
+/* DR */
+#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */
+#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */
+/**
+ * @}
+ */ /* End of name TSPIxDR_MASK Macro Definition */
+
+/**
+ * @name TSPI _DATA_LENGTH Macro Definition.
+ * @brief TSPI DATA LENGTH Macro Definition.
+ * @{
+ */
+#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */
+#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */
+#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */
+#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */
+#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */
+#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */
+#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */
+#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */
+#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */
+#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */
+#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */
+#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */
+#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */
+#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */
+#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */
+#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */
+#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */
+#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */
+#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */
+#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */
+#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */
+#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */
+#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */
+#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */
+#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */
+/**
+ * @}
+ */ /* End of name TSPI _DATA_LENGTH Macro Definition */
+/**
+ * @}
+ */ /* End of group TSPI_Private_typedef */
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Private_define TSPI Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group TSPI_Private_define */
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Private_typedef TSPI Private Typedef
+ * @{
+ */
+/*----------------------------------*/
+/**
+ * @brief TSPI mask array.
+*/
+/*----------------------------------*/
+static uint32_t mask[32] ={
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ TSPI_DR_8BIT_MASK,
+ TSPI_DR_9BIT_MASK,
+ TSPI_DR_10BIT_MASK,
+ TSPI_DR_11BIT_MASK,
+ TSPI_DR_12BIT_MASK,
+ TSPI_DR_13BIT_MASK,
+ TSPI_DR_14BIT_MASK,
+ TSPI_DR_15BIT_MASK,
+ TSPI_DR_16BIT_MASK,
+ TSPI_DR_17BIT_MASK,
+ TSPI_DR_18BIT_MASK,
+ TSPI_DR_19BIT_MASK,
+ TSPI_DR_20BIT_MASK,
+ TSPI_DR_21BIT_MASK,
+ TSPI_DR_22BIT_MASK,
+ TSPI_DR_23BIT_MASK,
+ TSPI_DR_24BIT_MASK,
+ TSPI_DR_25BIT_MASK,
+ TSPI_DR_26BIT_MASK,
+ TSPI_DR_27BIT_MASK,
+ TSPI_DR_28BIT_MASK,
+ TSPI_DR_29BIT_MASK,
+ TSPI_DR_30BIT_MASK,
+ TSPI_DR_31BIT_MASK
+};
+
+/**
+ * @}
+ */ /* End of group TSPI_Private_typedef */
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup TSPI_Private_fuctions TSPI Private Fuctions
+ * @{
+ */
+
+#ifdef DEBUG
+ __INLINE static int32_t check_param_transmit_enable(uint32_t param);
+ __INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param);
+ __INLINE static int32_t check_param_transmit_master(uint32_t param);
+ __INLINE static int32_t check_param_transmit_mode(uint32_t param);
+ __INLINE static int32_t check_param_transmit_sel_select(uint32_t param);
+ __INLINE static int32_t check_param_frame_range(uint32_t param);
+ __INLINE static int32_t check_param_idle_imp(uint32_t param);
+ __INLINE static int32_t check_param_underrun_imp(uint32_t param);
+ __INLINE static int32_t check_param_tx_fill_level(uint32_t param);
+ __INLINE static int32_t check_param_rx_fill_level(uint32_t param);
+ __INLINE static int32_t check_param_tx_fifo_int(uint32_t param);
+ __INLINE static int32_t check_param_rx_fifo_int(uint32_t param);
+ __INLINE static int32_t check_param_err_int(uint32_t param);
+ __INLINE static int32_t check_param_tx_dma_int(uint32_t param);
+ __INLINE static int32_t check_param_rx_dma_int(uint32_t param);
+ __INLINE static int32_t check_param_input_clock(uint32_t param);
+ __INLINE static int32_t check_param_input_divider(uint32_t param);
+ __INLINE static int32_t check_param_data_direction(uint32_t param);
+ __INLINE static int32_t check_param_frame_length(uint32_t param);
+ __INLINE static int32_t check_param_frame_interval(uint32_t param);
+ __INLINE static int32_t check_param_tspixcs3_imp(uint32_t param);
+ __INLINE static int32_t check_param_tspixcs2_imp(uint32_t param);
+ __INLINE static int32_t check_param_tspixcs1_imp(uint32_t param);
+ __INLINE static int32_t check_param_tspixcs0_imp(uint32_t param);
+ __INLINE static int32_t check_param_clock_edge_imp(uint32_t param);
+ __INLINE static int32_t check_param_clock_idle_imp(uint32_t param);
+ __INLINE static int32_t check_param_min_idle_time(uint32_t param);
+ __INLINE static int32_t check_param_clock_delay(uint32_t param);
+ __INLINE static int32_t check_param_negate_delay(uint32_t param);
+ __INLINE static int32_t check_param_parity_enable(uint32_t param);
+ __INLINE static int32_t check_param_parity_bit(uint32_t param);
+#endif
+
+#ifdef DEBUG
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transmit Enable's parameter.
+ * @param param :Transmit Enable's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Transmission_Control
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_transmit_enable(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TRXE_DISABLE:
+ case TSPI_TRXE_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transmit Mode's parameter.
+ * @param param :Transmit Mode's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Transmission_Mode
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_SPI_MODE:
+ case TSPI_SIO_MODE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transmit Master/Slave parameter.
+ * @param param :Transmit Master/Slave parameter (Only support Master mode)
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Operation_Select
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_transmit_master(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_MASTER_OPEARTION:
+ case TSPI_SLAVE_OPERATION:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transfer Mode's parameter.
+ * @param param :Transfer Mode's parameter (not support Two Way)
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Transfer_Mode
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_transmit_mode(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TWO_WAY:
+ case TSPI_TX_ONLY:
+ case TSPI_RX_ONLY:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transmit Sel Select's parameter.
+ * @param param :Transmit Sel Select's parameter (not support Two Way)
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_CSSEL_Select
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_transmit_sel_select(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TSPIxCS0_ENABLE:
+ case TSPI_TSPIxCS1_ENABLE:
+ case TSPI_TSPIxCS2_ENABLE:
+ case TSPI_TSPIxCS3_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Transmit Frame Range's parameter.
+ * @param param :TransmitFrame Range's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Transfer_Frame_Range
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_frame_range(uint32_t param)
+
+{
+ int32_t result = PARAM_NG;
+
+ if ((TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)){
+ result = PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the IDLE Output Value's parameter.
+ * @param param :IDLE Output Value's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_IDLE_Output_value
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_idle_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TIDLE_Hiz:
+ case TSPI_TIDLE_LAST_DATA:
+ case TSPI_TIDLE_LOW:
+ case TSPI_TIDLE_HI:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Underrun Occur Output Value's parameter.
+ * @param param :Underrun Occur Output Value's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Underrun_Output_value
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_underrun_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TXDEMP_LOW:
+ case TSPI_TXDEMP_HI:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Fill Level's parameter.
+ * @param param :Tx Fill Level's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TxFillLevel
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tx_fill_level(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TX_FILL_LEVEL_0:
+ case TSPI_TX_FILL_LEVEL_1:
+ case TSPI_TX_FILL_LEVEL_2:
+ case TSPI_TX_FILL_LEVEL_3:
+ case TSPI_TX_FILL_LEVEL_4:
+ case TSPI_TX_FILL_LEVEL_5:
+ case TSPI_TX_FILL_LEVEL_6:
+ case TSPI_TX_FILL_LEVEL_7:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Fill Level's parameter.
+ * @param param :Rx Fill Level's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_RxFillLevel
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rx_fill_level(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_RX_FILL_LEVEL_0:
+ case TSPI_RX_FILL_LEVEL_1:
+ case TSPI_RX_FILL_LEVEL_2:
+ case TSPI_RX_FILL_LEVEL_3:
+ case TSPI_RX_FILL_LEVEL_4:
+ case TSPI_RX_FILL_LEVEL_5:
+ case TSPI_RX_FILL_LEVEL_6:
+ case TSPI_RX_FILL_LEVEL_7:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx FIFO Interrpt's parameter.
+ * @param param :Tx FIFO Interrpt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TxInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tx_fifo_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TX_FIFO_INT_DISABLE:
+ case TSPI_TX_FIFO_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Interrpt's parameter.
+ * @param param :Tx Interrpt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TxInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tx_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TX_INT_DISABLE:
+ case TSPI_TX_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx FIFO Interrpt's parameter.
+ * @param param :Rx FIFO Interrpt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_RxFIFOInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rx_fifo_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_RX_FIFO_INT_DISABLE:
+ case TSPI_RX_FIFO_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Interrpt's parameter.
+ * @param param :Rx Interrpt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_RxInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rx_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_RX_INT_DISABLE:
+ case TSPI_RX_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Error Interrupt's parameter.
+ * @param param :Error Interrupt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_ErrorInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_err_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_ERR_INT_DISABLE:
+ case TSPI_ERR_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx DMA Interrupt's parameter.
+ * @param param :Tx DMA Interrupt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TxDMAInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tx_dma_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TX_DMA_INT_DISABLE:
+ case TSPI_TX_DMA_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx DMA Interrupt's parameter.
+ * @param param :Rx DMA Interrupt's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_RxDMAInterrupt
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_rx_dma_int(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_RX_DMA_INT_DISABLE:
+ case TSPI_RX_DMA_INT_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Input Clock's parameter.
+ * @param param :Input Clock's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Baudrate_Clock
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_input_clock(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_BR_CLOCK_0:
+ case TSPI_BR_CLOCK_1:
+ case TSPI_BR_CLOCK_2:
+ case TSPI_BR_CLOCK_4:
+ case TSPI_BR_CLOCK_8:
+ case TSPI_BR_CLOCK_16:
+ case TSPI_BR_CLOCK_32:
+ case TSPI_BR_CLOCK_64:
+ case TSPI_BR_CLOCK_128:
+ case TSPI_BR_CLOCK_256:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Baudrate Divider's parameter.
+ * @param param :Baudrate Divider's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Baudrate_Clock
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_input_divider(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_BR_DIVIDER_16:
+ case TSPI_BR_DIVIDER_1:
+ case TSPI_BR_DIVIDER_2:
+ case TSPI_BR_DIVIDER_3:
+ case TSPI_BR_DIVIDER_4:
+ case TSPI_BR_DIVIDER_5:
+ case TSPI_BR_DIVIDER_6:
+ case TSPI_BR_DIVIDER_7:
+ case TSPI_BR_DIVIDER_8:
+ case TSPI_BR_DIVIDER_9:
+ case TSPI_BR_DIVIDER_10:
+ case TSPI_BR_DIVIDER_11:
+ case TSPI_BR_DIVIDER_12:
+ case TSPI_BR_DIVIDER_13:
+ case TSPI_BR_DIVIDER_14:
+ case TSPI_BR_DIVIDER_15:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Direction's parameter.
+ * @param param :Data Direction's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx".
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_data_direction(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_DATA_DIRECTION_LSB:
+ case TSPI_DATA_DIRECTION_MSB:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Length's parameter.
+ * @param param :Data Length's parameter (Only support 8bit DATA)
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx".
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_frame_length(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_DATA_LENGTH_8:
+ case TSPI_DATA_LENGTH_9:
+ case TSPI_DATA_LENGTH_10:
+ case TSPI_DATA_LENGTH_11:
+ case TSPI_DATA_LENGTH_12:
+ case TSPI_DATA_LENGTH_13:
+ case TSPI_DATA_LENGTH_14:
+ case TSPI_DATA_LENGTH_15:
+ case TSPI_DATA_LENGTH_16:
+ case TSPI_DATA_LENGTH_17:
+ case TSPI_DATA_LENGTH_18:
+ case TSPI_DATA_LENGTH_19:
+ case TSPI_DATA_LENGTH_20:
+ case TSPI_DATA_LENGTH_21:
+ case TSPI_DATA_LENGTH_22:
+ case TSPI_DATA_LENGTH_23:
+ case TSPI_DATA_LENGTH_24:
+ case TSPI_DATA_LENGTH_25:
+ case TSPI_DATA_LENGTH_26:
+ case TSPI_DATA_LENGTH_27:
+ case TSPI_DATA_LENGTH_28:
+ case TSPI_DATA_LENGTH_29:
+ case TSPI_DATA_LENGTH_30:
+ case TSPI_DATA_LENGTH_31:
+ case TSPI_DATA_LENGTH_32:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Frame Interval's parameter.
+ * @param param :Frame Interval's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Frame_Interval_Time
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_frame_interval(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_INTERVAL_TIME_0:
+ case TSPI_INTERVAL_TIME_1:
+ case TSPI_INTERVAL_TIME_2:
+ case TSPI_INTERVAL_TIME_3:
+ case TSPI_INTERVAL_TIME_4:
+ case TSPI_INTERVAL_TIME_5:
+ case TSPI_INTERVAL_TIME_6:
+ case TSPI_INTERVAL_TIME_7:
+ case TSPI_INTERVAL_TIME_8:
+ case TSPI_INTERVAL_TIME_9:
+ case TSPI_INTERVAL_TIME_10:
+ case TSPI_INTERVAL_TIME_11:
+ case TSPI_INTERVAL_TIME_12:
+ case TSPI_INTERVAL_TIME_13:
+ case TSPI_INTERVAL_TIME_14:
+ case TSPI_INTERVAL_TIME_15:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the TTSPIxCS3 Polarity's parameter.
+ * @param param :TTSPIxCS3 Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity.
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TSPIxCS3_NEGATIVE:
+ case TSPI_TSPIxCS3_POSITIVE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the TTSPIxCS2 Polarity's parameter.
+ * @param param :TTSPIxCS2 Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity.
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TSPIxCS2_NEGATIVE:
+ case TSPI_TSPIxCS2_POSITIVE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the TTSPIxCS1 Polarity's parameter.
+ * @param param :TTSPIxCS1 Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity.
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TSPIxCS1_NEGATIVE:
+ case TSPI_TSPIxCS1_POSITIVE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the TTSPIxCS0 Polarity's parameter.
+ * @param param :TTSPIxCS0 Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity.
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_TSPIxCS0_NEGATIVE:
+ case TSPI_TSPIxCS0_POSITIVE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Serial Clock Polarity's parameter.
+ * @param param :Serial Clock Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Serial_Clock_Polarity
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_clock_edge_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_SERIAL_CK_1ST_EDGE:
+ case TSPI_SERIAL_CK_2ND_EDGE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Serial Clock IDLE Polarity's parameter.
+ * @param param :Serial Clock IDLE Polarity's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_clock_idle_imp(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_SERIAL_CK_IDLE_LOW:
+ case TSPI_SERIAL_CK_IDLE_HI:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Minimum IDLE Time's parameter.
+ * @param param :Minimum IDLE Time's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Minimum_IDLE_Time
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_min_idle_time(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_MIN_IDLE_TIME_1:
+ case TSPI_MIN_IDLE_TIME_2:
+ case TSPI_MIN_IDLE_TIME_3:
+ case TSPI_MIN_IDLE_TIME_4:
+ case TSPI_MIN_IDLE_TIME_5:
+ case TSPI_MIN_IDLE_TIME_6:
+ case TSPI_MIN_IDLE_TIME_7:
+ case TSPI_MIN_IDLE_TIME_8:
+ case TSPI_MIN_IDLE_TIME_9:
+ case TSPI_MIN_IDLE_TIME_10:
+ case TSPI_MIN_IDLE_TIME_11:
+ case TSPI_MIN_IDLE_TIME_12:
+ case TSPI_MIN_IDLE_TIME_13:
+ case TSPI_MIN_IDLE_TIME_14:
+ case TSPI_MIN_IDLE_TIME_15:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Serial Clock Delay's parameter.
+ * @param param :Serial Clock Delay's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Serial_Clock_Delay
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_clock_delay(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_SERIAL_CK_DELAY_1:
+ case TSPI_SERIAL_CK_DELAY_2:
+ case TSPI_SERIAL_CK_DELAY_3:
+ case TSPI_SERIAL_CK_DELAY_4:
+ case TSPI_SERIAL_CK_DELAY_5:
+ case TSPI_SERIAL_CK_DELAY_6:
+ case TSPI_SERIAL_CK_DELAY_7:
+ case TSPI_SERIAL_CK_DELAY_8:
+ case TSPI_SERIAL_CK_DELAY_9:
+ case TSPI_SERIAL_CK_DELAY_10:
+ case TSPI_SERIAL_CK_DELAY_11:
+ case TSPI_SERIAL_CK_DELAY_12:
+ case TSPI_SERIAL_CK_DELAY_13:
+ case TSPI_SERIAL_CK_DELAY_14:
+ case TSPI_SERIAL_CK_DELAY_15:
+ case TSPI_SERIAL_CK_DELAY_16:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Negate Delay's parameter.
+ * @param param :Negate Delay's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_Negate_Delay
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_negate_delay(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_NEGATE_1:
+ case TSPI_NEGATE_2:
+ case TSPI_NEGATE_3:
+ case TSPI_NEGATE_4:
+ case TSPI_NEGATE_5:
+ case TSPI_NEGATE_6:
+ case TSPI_NEGATE_7:
+ case TSPI_NEGATE_8:
+ case TSPI_NEGATE_9:
+ case TSPI_NEGATE_10:
+ case TSPI_NEGATE_11:
+ case TSPI_NEGATE_12:
+ case TSPI_NEGATE_13:
+ case TSPI_NEGATE_14:
+ case TSPI_NEGATE_15:
+ case TSPI_NEGATE_16:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Enable's parameter.
+ * @param param :Parity Enable's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx".
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_parity_enable(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_PARITY_DISABLE:
+ case TSPI_PARITY_ENABLE:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Bit's parameter.
+ * @param param :Parity Bit's parameter
+ * @retval PARAM_OK :Valid
+ * @retval PARAM_NG :Invalid
+ * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx".
+ */
+/*--------------------------------------------------*/
+__INLINE static int32_t check_param_parity_bit(uint32_t param)
+{
+ int32_t result = PARAM_NG;
+
+ switch (param)
+ {
+ case TSPI_PARITY_BIT_ODD:
+ case TSPI_PARITY_BIT_EVEN:
+ result = PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+#endif
+/**
+ * @}
+ */ /* End of group TSPI_Private_functions */
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup TSPI_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Initialize the TSPI object.
+ * @param p_obj :TSPI object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_init(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ /* Check the parameter of TTSPIxCR1. */
+ assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe));
+ assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims));
+ assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr));
+ assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd));
+ assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel));
+ assert_param(check_param_frame_range(p_obj->init.cnt1.fc));
+ /* Check the parameter of TTSPIxCR2 */
+ assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle));
+ assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp));
+ assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til));
+ assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril));
+ assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe));
+ assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe));
+ assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe));
+ assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe));
+ assert_param(check_param_err_int(p_obj->init.cnt2.interr));
+ assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate));
+ assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare));
+ /* Check the parameter of TTSPIxBR */
+ assert_param(check_param_input_clock(p_obj->init.brd.brck));
+ assert_param(check_param_input_divider(p_obj->init.brd.brs));
+ /* Check the parameter of TTSPIxFMTR0 */
+ assert_param(check_param_data_direction(p_obj->init.fmr0.dir));
+ assert_param(check_param_frame_length(p_obj->init.fmr0.fl));
+ assert_param(check_param_frame_interval(p_obj->init.fmr0.fint));
+ assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol));
+ assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol));
+ assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol));
+ assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol));
+ assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha));
+ assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol));
+ assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint));
+ assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl));
+ assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl));
+ /* Check the parameter of TTSPIxFMTR1 */
+ assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe));
+ assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm));
+#endif
+
+
+ /* TSPI Software Reset */
+ p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE);
+ p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);;
+
+ /* Wait for 2 clocks of reset completion */
+ __NOP();
+ __NOP();
+
+ /* Enable the selected TSPI peripheral (TSPIE)*/
+ p_obj->p_instance->CR0 = TSPI_ENABLE;
+
+ /* Control1 Register1 Set*/
+ p_obj->p_instance->CR1 = 0x00001C01U;
+ p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \
+ p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims| p_obj->init.cnt1.trgen);
+ /* Control2 Register Set */
+ p_obj->p_instance->CR2 = 0x00E10100U;
+ p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \
+ p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe |p_obj->init.cnt2.inttxwe | \
+ p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare );
+
+ /* Control3 Register is FIFO clear, do nothing */
+
+ /* Baudrate Register Set */
+ p_obj->p_instance->BR = 0U;
+ p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs);
+
+ /* Format control0 Register Set */
+ p_obj->p_instance->FMTR0 = 0x8800C400U;
+ p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \
+ p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \
+ p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl );
+
+ /* Format control1 Register Set*/
+ p_obj->p_instance->FMTR1 = 0U;
+ p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe);
+
+ /* not created */
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Release the TSPI object.
+ * @param p_obj :TSPI object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_deinit(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+
+ /* Disable the selected TSPI peripheral */
+ p_obj->p_instance->CR0 = TSPI_DISABLE;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Transmit data..
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of transmit data.
+ * @param timeout :Timeout duration.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note When p_info is NULL, "Failure" is returned.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t err=0;
+ uint32_t length = 0;
+
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+
+ p_obj->errcode = NOERROR;
+
+ /* Check the Transfer Mode setting */
+ if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) {
+ p_obj->errcode = TRANSMITMODEERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ /* Transmit data check*/
+ if((p_info->tx8.p_data == TSPI_NULL ) || (p_info->tx8.num == 0))
+ {
+ p_obj->errcode = DATABUFEMPERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ /* FIFO Cear */
+ p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE;
+ /* Check the Frame length setting */
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24);
+ /* Blocking Communication support frame length 8bit (1 byte) only */
+ if (length == (TSPI_DATA_LENGTH_8 >> 24)) {
+ p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8;
+ }else{
+ p_obj->errcode = DATALENGTHERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ /* Transmit Data write to D ata Register */
+ while (p_info->tx8.num > 0)
+ {
+ /* Check the current fill level */
+ if(((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7)
+ {
+ *((__IO uint8_t*)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK);
+ p_info->tx8.num--;
+ /* check complete transmit */
+ if((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE)
+ {
+ timeout--;
+ if(timeout == 0) {
+ p_obj->errcode = TIMEOUTERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+ else
+ {
+ /* Enable TSPI Transmission Control */
+ if(p_info->tx8.num==0){
+ p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE;
+ return (result);
+ }
+ else {
+ /* Next transmit data sending */
+ p_obj->p_instance->SR |= TSPI_TX_DONE_CLR;
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ }
+
+ }
+ }else{
+ p_obj->errcode = FIFOFULLERR;
+ timeout--;
+ if(timeout == 0) {
+ p_obj->errcode = TIMEOUTERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+
+ }
+ /* check complete transmit */
+ while((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE)
+ {
+ timeout--;
+ if(timeout == 0) {
+ p_obj->errcode = TIMEOUTERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+ /* Check Error Flag */
+ if((tspi_get_error(p_obj, &err)) != TXZ_ERROR)
+ {
+ if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;}
+ else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;}
+ else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;}
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+ if(p_obj->errcode == NOERROR) {
+ //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR;
+ p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE;
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ return (result);
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Receive data. Blocking Communication.
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of receive buffer.
+ * @param timeout :Timeout duration.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note When p_info is NULL, "Failure" is returned.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t err=0;
+ uint32_t length = 0;
+ uint32_t count = 0;
+ uint32_t index = 0;
+// uint32_t level = 0;
+
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+
+ p_obj->errcode = NOERROR;
+
+ /* Check the Transfer Mode setting */
+ if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) {
+ p_obj->errcode = TRANSMITMODEERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ if((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) {
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ }
+
+ /* Transmit data check*/
+ if((p_info->rx8.p_data == TSPI_NULL ) || (p_info->rx8.num == 0))
+ {
+ result = TXZ_ERROR;
+ return (result);
+ }
+ count = p_info->rx8.num;
+
+ /* Check the Frame length setting */
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ /* Blocking Communication support frame length 8bit (1 byte) only */
+ if (length == (TSPI_DATA_LENGTH_8 >> 24)) {
+ p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8;
+ }else{
+ p_obj->errcode = DATALENGTHERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ while (timeout > 0)
+ {
+ /* Wait until Receive Complete Flag is set to receive data */
+ if((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE)
+ {
+ while (count > 0) {
+ /* Check the remain data exist */
+ if((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0){
+ p_info->rx8.p_data[index] = (*((__IO uint8_t*)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK);
+ count--;
+ index++;
+ }else{
+ p_obj->errcode = FIFOFULLERR;
+ timeout--;
+ if(timeout == 0) {
+ p_obj->errcode = TIMEOUTERR;
+ result = TXZ_ERROR;
+ return (result);
+ }
+ }
+ }
+ /* Receive Complete Flag is clear */
+ p_obj->p_instance->SR |= TSPI_RX_DONE_CLR;
+ /* FIFO Cear */
+ p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE;
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ return (result);
+ }
+ else {timeout--;}
+ }
+ /* Timeout management */
+ p_obj->errcode = TIMEOUTERR;
+
+ /* Check Error Flag set */
+ if((tspi_get_error(p_obj, &err)) != TXZ_ERROR)
+ {
+ if(((err) & TSPI_UNDERRUN_ERR)== TSPI_UNDERRUN_ERR) {p_obj->errcode = UNDERRUNERR;}
+ else if(((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) {p_obj->errcode = OVERRUNERR;}
+ else if(((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) {p_obj->errcode = PARITYERR;}
+ }else{
+ result = TXZ_ERROR;
+ return (result);
+ }
+
+ result = TXZ_ERROR;
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Transmit data. Non-Blocking Communication.
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of transmit data.
+ * @retval SUCCESS :Success.
+ * @retval FAILURE :Failure.
+ * @note Asynchronous Processing.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t length = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data));
+ }
+ else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data));
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ p_obj->p_instance->SR |= TSPI_TX_DONE_CLR;
+ p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE;
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ p_obj->transmit.rp = 0;
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data;
+ p_obj->transmit.info.tx8.num = p_info->tx8.num;
+ p_obj->transmit.tx_allign = 8;
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data;
+ p_obj->transmit.info.tx16.num = p_info->tx16.num;
+ p_obj->transmit.tx_allign = 16;
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data;
+ p_obj->transmit.info.tx32.num = p_info->tx32.num;
+ p_obj->transmit.tx_allign = 32;
+ }
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ {
+ /* transmit data length set */
+
+ /*--- TSPIxSR ---*/
+ /* Read FIFO fill level. */
+ /* Read current TLVL. */
+ __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK);
+ tlvl >>= 8;
+ /* FIFO Max = TRANSFER_FIFO_MAX_NUM */
+ if (tlvl > TRANSFER_FIFO_MAX_NUM)
+ {
+ tlvl = TRANSFER_FIFO_MAX_NUM;
+ }
+ /* Empty FIFO Num */
+ {
+ __IO uint32_t work = tlvl;
+ tlvl = (TRANSFER_FIFO_MAX_NUM - work);
+ }
+ /*--- TSPIxDR ---*/
+ /* Only the empty number of FIFO is a transmission data set. */
+ {
+ uint32_t i = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ /* Set data to FIFO. */
+ for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++)
+ {
+ switch (p_obj->transmit.tx_allign)
+ {
+ case 8:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 16:
+ if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 32:
+ if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ }
+ }
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ return (result);
+}
+
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Receive data. Non-Blocking Communication.
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of receive buffer.
+ * @retval SUCCESS :Success.
+ * @retval FAILURE :Failure.
+ * @note Asynchronous Processing.
+ * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t length = 0;
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data));
+ }
+ else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data));
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->receive.info.rx8.p_data = p_info->rx8.p_data;
+ p_obj->receive.info.rx8.num = p_info->rx8.num;
+ p_obj->receive.rx_allign = 8;
+
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->receive.info.rx16.p_data = p_info->rx16.p_data;
+ p_obj->receive.info.rx16.num = p_info->rx16.num;
+ p_obj->receive.rx_allign = 16;
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->receive.info.rx32.p_data = p_info->rx32.p_data;
+ p_obj->receive.info.rx32.num = p_info->rx32.num;
+ p_obj->receive.rx_allign = 32;
+ }
+ /*------------------------------*/
+ /* Enable Receive */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Transmit data DMA. Non-Blocking Communication.
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of transmit data.
+ * @retval SUCCESS :Success.
+ * @retval FAILURE :Failure.
+ * @note Asynchronous Processing.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t length = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data));
+ }
+ else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data));
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ p_obj->p_instance->SR |= TSPI_TX_DONE_CLR;
+ p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE;
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ p_obj->transmit.rp = 0;
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data;
+ p_obj->transmit.info.tx8.num = p_info->tx8.num;
+ p_obj->transmit.tx_allign = 8;
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data;
+ p_obj->transmit.info.tx16.num = p_info->tx16.num;
+ p_obj->transmit.tx_allign = 16;
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data;
+ p_obj->transmit.info.tx32.num = p_info->tx32.num;
+ p_obj->transmit.tx_allign = 32;
+ }
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ {
+ /* transmit data length set */
+
+ /*--- TSPIxSR ---*/
+ /* Read FIFO fill level. */
+ /* Read current TLVL. */
+ __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK);
+ tlvl >>= 8;
+ /* FIFO Max = TRANSFER_FIFO_MAX_NUM */
+ if (tlvl > TRANSFER_FIFO_MAX_NUM)
+ {
+ tlvl = TRANSFER_FIFO_MAX_NUM;
+ }
+ /* Empty FIFO Num */
+ {
+ __IO uint32_t work = tlvl;
+ tlvl = (TRANSFER_FIFO_MAX_NUM - work);
+ }
+ /*--- TSPIxDR ---*/
+ /* Only the empty number of FIFO is a transmission data set. */
+ {
+ uint32_t i = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ /* Set data to FIFO. */
+ for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++)
+ {
+ switch (p_obj->transmit.tx_allign)
+ {
+ case 8:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 16:
+ if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 32:
+ if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ }
+ }
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /* Write to DMATE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE)
+ {
+ p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE;
+ }
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Receive data DMA. Non-Blocking Communication.
+ * @param p_obj :TSPI object.
+ * @param p_info :The information of receive buffer.
+ * @retval SUCCESS :Success.
+ * @retval FAILURE :Failure.
+ * @note Asynchronous Processing.
+ * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t length = 0;
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if(p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data));
+ }
+ else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data));
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->receive.info.rx8.p_data = p_info->rx8.p_data;
+ p_obj->receive.info.rx8.num = p_info->rx8.num;
+ p_obj->receive.rx_allign = 8;
+
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->receive.info.rx16.p_data = p_info->rx16.p_data;
+ p_obj->receive.info.rx16.num = p_info->rx16.num;
+ p_obj->receive.rx_allign = 16;
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->receive.info.rx32.p_data = p_info->rx32.p_data;
+ p_obj->receive.info.rx32.num = p_info->rx32.num;
+ p_obj->receive.rx_allign = 32;
+ }
+ /*------------------------------*/
+ /* Enable Receive */
+ /*------------------------------*/
+ /* Write to DMARE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE)
+ {
+ p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE;
+ }
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for transmit.
+ * @param p_obj :TSPI object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void tspi_irq_handler_transmit(tspi_t *p_obj)
+{
+ __IO uint32_t status;
+
+ uint32_t length;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Status Registar Control */
+ /*------------------------------*/
+ /* Read current TSPIxSR. */
+ status = p_obj->p_instance->SR;
+ /* Clear the transmit's end flag. */
+ /* Write to TXEND(=1), and TXFF(=1). */
+ //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR);
+ /*------------------------------*/
+ /* Data length setting */
+ /*------------------------------*/
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U);
+ /*------------------------------*/
+ /* Transmit Status Check */
+ /*------------------------------*/
+ /* Check the transmit's end flag. */
+ if (((status & TSPI_TX_DONE_FLAG ) == TSPI_TX_DONE) ||
+ ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til))
+ {
+ TXZ_WorkState txDone = TXZ_BUSY;
+ /* Read FIFO fill level. */
+ __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK);
+ tlvl >>= 8;
+ /* FIFO Max = TRANSFER_FIFO_MAX_NUM */
+ if (tlvl > TRANSFER_FIFO_MAX_NUM)
+ {
+ tlvl = TRANSFER_FIFO_MAX_NUM;
+ }
+ /* Get the empty num in FIFO. */
+ {
+ __IO uint32_t work = tlvl;
+ tlvl = (TRANSFER_FIFO_MAX_NUM - work);
+ }
+ if (tlvl == TRANSFER_FIFO_MAX_NUM)
+ {
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->transmit.tx_allign = 8;
+ if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp)
+ {
+ txDone = TXZ_DONE;
+ }
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->transmit.tx_allign = 16;
+ if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp)
+ {
+ txDone = TXZ_DONE;
+ }
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->transmit.tx_allign = 32;
+ if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp)
+ {
+ txDone = TXZ_DONE;
+ }
+ }
+ }
+ if (txDone == TXZ_DONE)
+ {
+ /*=== Transmit Done!! ===*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->transmit.handler != TSPI_NULL)
+ {
+ /* Call the transmit handler with SUCCESS. */
+ p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS);
+ }
+ }
+ else
+ {
+ /*=== Transmit Continue ===*/
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ /* Only the empty number of FIFO is a transmission data set. */
+ uint32_t i = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ /* Set data to FIFO. */
+ for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++)
+ {
+ switch (p_obj->transmit.tx_allign)
+ {
+ case 8:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 16:
+ if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case 32:
+ if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ #if 0
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+ #endif
+ }
+ }
+}
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for receive.
+ * @param p_obj :TSPI object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void tspi_irq_handler_receive(tspi_t *p_obj)
+{
+ __IO uint32_t status;
+
+ uint32_t length = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+
+ /*------------------------------*/
+ /* Status Registar Control */
+ /*------------------------------*/
+ /* Read current TSPIxSR. */
+ status = p_obj->p_instance->SR;
+ /* Clear the transmit's end flag. */
+ /* Write to RXEND(=1), and RXFF(=1). */
+ //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR);
+ /*------------------------------*/
+ /* Data length setting */
+ /*------------------------------*/
+ length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24);
+ if(length == DATA_LENGTH_8)
+ {
+ /* 8 bit */
+ p_obj->receive.rx_allign = 8;
+ }
+ else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17) )
+ {
+ /* 9 - 16 bit */
+ p_obj->receive.rx_allign = 16;
+ }
+ else
+ {
+ /* 17 - 32 bit */
+ p_obj->receive.rx_allign = 32;
+ }
+ /*------------------------------*/
+ /* Receive Status Check */
+ /*------------------------------*/
+ /* Check the receive's end flag. */
+ if (((status & TSPI_RX_DONE_FLAG ) == TSPI_RX_DONE) ||
+ ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril))
+ {
+ /* Read FIFO fill level. */
+ __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK);
+ //__IO uint32_t rlvl = 7;
+ /* FIFO Max = RECEIVE_FIFO_MAX_NUM */
+ if (rlvl > RECEIVE_FIFO_MAX_NUM)
+ {
+ rlvl = RECEIVE_FIFO_MAX_NUM;
+ }
+ /*------------------------------*/
+ /* Data Read */
+ /*------------------------------*/
+ /* Read FIFO data. */
+ if (rlvl != 0)
+ {
+ uint32_t i;
+ for (i=0; i<rlvl; i++)
+ {
+ switch (p_obj->receive.rx_allign)
+ {
+ case 8:
+ *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK);
+ break;
+ case 16:
+ *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]);
+ break;
+ case 32:
+ *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]);
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != TSPI_NULL)
+ {
+ tspi_receive_t param;
+
+ switch (p_obj->receive.rx_allign)
+ {
+ case 8:
+ param.rx8.p_data = p_obj->receive.info.rx8.p_data;
+ param.rx8.num = rlvl;
+ break;
+ case 16:
+ param.rx16.p_data = p_obj->receive.info.rx16.p_data;
+ param.rx16.num = rlvl;
+ break;
+ case 32:
+ param.rx32.p_data = p_obj->receive.info.rx32.p_data;
+ param.rx32.num = rlvl;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ /* Call the receive handler with SUCCESS. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m);
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for error.
+ * @param p_obj :TSPI object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void tspi_error_irq_handler(tspi_t *p_obj)
+{
+ __IO uint32_t error;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Error Registar Control */
+ /*------------------------------*/
+ /* Read current TSPIxERR. */
+ error = p_obj->p_instance->ERR;
+ /* Now, no clear the error flag. */
+ /*------------------------------*/
+ /* Error Check */
+ /*------------------------------*/
+ /*--- TSPIxERR ---*/
+ /* Check the transmit error. */
+ /* TRGERR */
+ if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR)
+ {
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->transmit.handler != TSPI_NULL)
+ {
+ /* Call the transmit handler with FAILURE. */
+ p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR);
+ }
+ }
+ /* Check the receive error. */
+ {
+ TXZ_Result err = TXZ_SUCCESS;
+ /* UNDERERR */
+ if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ /* OVRERR */
+ if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ /* PERR */
+ if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ if (err == TXZ_ERROR)
+ {
+ /*------------------------------*/
+ /* Receive Check */
+ /*------------------------------*/
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=0). */
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != TSPI_NULL)
+ {
+ /* Call the receive handler with FAILURE. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL);
+ }
+ }
+ }
+}
+
+
+/*--------------------------------------------------*/
+/**
+ * @brief Data Format setting
+ * @param p_obj :TSPI object.
+ * @retval -
+ * @note When p_obj is NULL, no processing.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_format(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ /* Check the parameter of TTSPIxFMTR0 */
+ assert_param(check_param_data_direction(p_obj->init.fmr0.dir));
+ assert_param(check_param_frame_length(p_obj->init.fmr0.fl));
+ assert_param(check_param_frame_interval(p_obj->init.fmr0.fint));
+ assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol));
+ assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol));
+ assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol));
+ assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol));
+ assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha));
+ assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol));
+ assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint));
+ assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl));
+ assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl));
+ /* Check the parameter of TTSPIxFMTR1 */
+ assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe));
+ assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm));
+#endif
+
+
+ /* Format control1 Register Set*/
+ p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe);
+ /* Format control0 Register Set */
+ p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \
+ p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \
+ p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl );
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get status.
+ * @details Status bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. |
+ * | 30-24 | - | - |
+ * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. |
+ * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. |
+ * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. |
+ * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. |
+ * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. |
+ * | 15-8 | - | - |
+ * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. |
+ * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. |
+ * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. |
+ * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag |
+ * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag |
+ *
+ * @param p_obj :TSPI object.
+ * @param p_status :Save area for status.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note When p_status is NULL, "Failure" is returned.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+
+ /* Return TSPI state */
+ *p_status = p_obj->p_instance->SR;
+ if(p_status != TSPI_NULL){ return (result);}
+ else {
+ result = TXZ_ERROR;
+ return (result);
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get error information.
+ * @details Error bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-3 | - | - |
+ * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. |
+ * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. |
+ * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. |
+ *
+ * @param p_obj :TSPI object.
+ * @param p_error :Save area for error.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note When p_error is NULL, "Failure" is returned.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+
+ /* Return TSPI ERROR */
+ *p_error = p_obj->p_instance->ERR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Error information clear.
+ * @details Error bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-3 | - | - |
+ * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. |
+ * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. |
+ * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. |
+ *
+ * @param p_obj :TSPI object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note When p_obj is NULL, "Failure" is returned.
+ * @note When p_error is NULL, "Failure" is returned.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_error_clear(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ /* Check the parameters */
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+#endif
+ p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR);
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard transmit.
+ * @param p_obj :TSPI object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears transmit's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_discard_transmit(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ /*--- TSPIxTRXE ---*/
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Refresh Setting */
+ /*------------------------------*/
+ /*--- TSPIxSR ---*/
+ /* Clear the transmit's end flag. */
+ /* Write to TXEND(=1), and TXFF(=1). */
+ p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
+ /*--- TSPIxFIFOCLR ---*/
+ /* Clear the transmit's FIFO. */
+ /* Write to TFCLR(=1). */
+ p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
+ /*--- TSPIxERR ---*/
+ /* Clear the trigger error flag. */
+ /* Write to TRGERR(=1). */
+ p_obj->p_instance->ERR = (TSPI_TRGERR_ERR );
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard receive.
+ * @param p_obj :TSPI object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears receive's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result tspi_discard_receive(tspi_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the TSPI_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ /*--- TSPIxTRXE ---*/
+ p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
+ /*------------------------------*/
+ /* Refresh Setting */
+ /*------------------------------*/
+ /*------------------------------*/
+ /* Refresh Setting */
+ /*------------------------------*/
+ /*--- TSPIxSR ---*/
+ /* Clear the transmit's end flag. */
+ /* Write to TXEND(=1), and TXFF(=1). */
+ p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR);
+ /*--- TSPIxFIFOCLR ---*/
+ /* Clear the transmit's FIFO. */
+ /* Write to TFCLR(=1). */
+ p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE);
+ /*--- TSPIxERR ---*/
+ /* Clear the trigger error flag. */
+ /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */
+ p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR |TSPI_OVERRUN_ERR | TSPI_PARITY_ERR );
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- TSPIxTRANS ---*/
+ /* Write to TRXE(=1). */
+ /* Check if the TSPI is already enabled */
+ if((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE)
+ {
+ p_obj->p_instance->CR0 |= TSPI_ENABLE;
+ }
+
+ /* Enable TSPI Transmission Control */
+ p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE;
+
+ return (result);
+}
+
+
+/**
+ * @}
+ */ /* End of group TSPI_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group TSPI */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__TSPI_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/Periph_Driver/src/txz_uart.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,1910 @@
+/**
+ *******************************************************************************
+ * @file txz_uart.c
+ * @brief This file provides API functions for UART driver.
+ * @version V1.0.0.1
+ * $Date:: 2018-04-02 19:31:41 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/* Includes */
+/*------------------------------------------------------------------------------*/
+#include "txz_uart_include.h"
+#include "txz_uart.h"
+
+#if defined(__UART_H)
+/**
+ * @addtogroup Periph_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup UART
+ * @{
+ */
+/*------------------------------------------------------------------------------*/
+/* Configuration */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Private_define UART Private Define
+ * @{
+ */
+
+/**
+ * @defgroup UART_BourateConfig Bourate Setting Configuration
+ * @brief Bourate Setting Configuration.
+ * @{
+ */
+#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */
+#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */
+#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */
+
+#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */
+#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */
+#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL
+
+#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */
+#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */
+/**
+ * @}
+ */ /* End of group UART_BourateConfig */
+
+/**
+ * @}
+ */ /* End of group UART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Private_define UART Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Enumerated Type Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Private_define UART Private Define
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Private_define */
+
+
+/*------------------------------------------------------------------------------*/
+/* Structure Definition */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Private_typedef UART Private Typedef
+ * @{
+ */
+
+/* no define */
+
+/**
+ * @}
+ */ /* End of group UART_Private_typedef */
+
+
+/*------------------------------------------------------------------------------*/
+/* Private Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @defgroup UART_Private_fuctions UART Private Fuctions
+ * @{
+ */
+#ifdef DEBUG
+ __STATIC_INLINE int32_t check_param_noize_filter(uint32_t param);
+ __STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param);
+ __STATIC_INLINE int32_t check_param_data_complemention(uint32_t param);
+ __STATIC_INLINE int32_t check_param_data_direction(uint32_t param);
+ __STATIC_INLINE int32_t check_param_stop_bit(uint32_t param);
+ __STATIC_INLINE int32_t check_param_parity_bit(uint32_t param);
+ __STATIC_INLINE int32_t check_param_parity_enable(uint32_t param);
+ __STATIC_INLINE int32_t check_param_data_length(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_err_int(uint32_t param);
+ __STATIC_INLINE int32_t check_param_prescaler(uint32_t param);
+ __STATIC_INLINE int32_t check_param_division(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rangeK(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rangeN(uint32_t param);
+ __STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param);
+ __STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param);
+#endif /* #ifdef DEBUG */
+__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level);
+__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level);
+#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE)
+ static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64);
+#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */
+
+#ifdef DEBUG
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Noize Fileter's parameter.
+ * @param param :Noize fileter's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_NOISE_FILTER_NON:
+ case UART_NOISE_FILTER_2_T0:
+ case UART_NOISE_FILTER_4_T0:
+ case UART_NOISE_FILTER_8_T0:
+ case UART_NOISE_FILTER_2_CLOCK:
+ case UART_NOISE_FILTER_3_CLOCK:
+ case UART_NOISE_FILTER_4_CLOCK:
+ case UART_NOISE_FILTER_5_CLOCK:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the CTS Handshake's parameter.
+ * @param param :CTS Handshake's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_CTS_DISABLE:
+ case UART_CTS_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the RTS Handshake's parameter.
+ * @param param :RTS Handshake's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_RTS_DISABLE:
+ case UART_RTS_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Complementation's parameter.
+ * @param param :Data Complementation's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_DATA_COMPLEMENTION_DISABLE:
+ case UART_DATA_COMPLEMENTION_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Direction's parameter.
+ * @param param :Data Direction's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_data_direction(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_DATA_DIRECTION_LSB:
+ case UART_DATA_DIRECTION_MSB:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Stop Bit's parameter.
+ * @param param :Stop Bit's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_STOP_BIT_1:
+ case UART_STOP_BIT_2:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Bit's parameter.
+ * @param param :Parity Bit's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_PARITY_BIT_ODD:
+ case UART_PARITY_BIT_EVEN:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Parity Enable's parameter.
+ * @param param :Parity Enable's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_PARITY_DISABLE:
+ case UART_PARITY_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Data Length's parameter.
+ * @param param :Data Length's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_data_length(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_DATA_LENGTH_7:
+ case UART_DATA_LENGTH_8:
+ case UART_DATA_LENGTH_9:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Fill Level Range's parameter.
+ * @param param :Tx Fill Level Range's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/
+#if 0
+ if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX))
+#else
+ if (param <= UART_TX_FILL_RANGE_MAX)
+#endif
+ {
+ result = UART_PARAM_OK;
+ }
+
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Fill Level's parameter.
+ * @param param :Rx Fill Level's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX))
+ {
+ result = UART_PARAM_OK;
+ }
+
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx FIFO Interrpt's parameter.
+ * @param param :Tx FIFO Interrpt's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_TX_FIFO_INT_DISABLE:
+ case UART_TX_FIFO_INT_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Tx Interrpt's parameter.
+ * @param param :Tx Interrpt's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_int(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_TX_INT_DISABLE:
+ case UART_TX_INT_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx FIFO Interrpt's parameter.
+ * @param param :Rx FIFO Interrpt's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_RX_FIFO_INT_DISABLE:
+ case UART_RX_FIFO_INT_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Rx Interrpt's parameter.
+ * @param param :Rx Interrpt's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_int(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_RX_INT_DISABLE:
+ case UART_RX_INT_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Error Interrupt's parameter.
+ * @param param :Error Interrupt's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_err_int(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_ERR_INT_DISABLE:
+ case UART_ERR_INT_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Prescaler's parameter.
+ * @param param :Prescaler's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_prescaler(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_PLESCALER_1:
+ case UART_PLESCALER_2:
+ case UART_PLESCALER_4:
+ case UART_PLESCALER_8:
+ case UART_PLESCALER_16:
+ case UART_PLESCALER_32:
+ case UART_PLESCALER_64:
+ case UART_PLESCALER_128:
+ case UART_PLESCALER_256:
+ case UART_PLESCALER_512:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Division's parameter.
+ * @param param :Division's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_division(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ switch (param)
+ {
+ case UART_DIVISION_DISABLE:
+ case UART_DIVISION_ENABLE:
+ result = UART_PARAM_OK;
+ break;
+ default:
+ /* no process */
+ break;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Range K's parameter.
+ * @param param :Range K's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rangeK(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ /*--- Now, UART_RANGE_K_MIN is 0. ---*/
+#if 0
+ if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX))
+#else
+ if (param <= UART_RANGE_K_MAX)
+#endif
+ {
+ result = UART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the Range N's parameter.
+ * @param param :Range N's parameter
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx".
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rangeN(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX))
+ {
+ result = UART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the num of buff for transmit.
+ * @param param :Num of buff.
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ if (param != 0)
+ {
+ result = UART_PARAM_OK;
+ }
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Check the num of buff for receive.
+ * @param param :Num of buff.
+ * @retval UART_PARAM_OK :Valid
+ * @retval UART_PARAM_NG :Invalid
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param)
+{
+ int32_t result = UART_PARAM_NG;
+
+ if (param >= 8)
+ {
+ result = UART_PARAM_OK;
+ }
+
+ return (result);
+}
+#endif /* #ifdef DEBUG */
+
+/*--------------------------------------------------*/
+/**
+ * @brief Convert Tx FIFO fill level to register.
+ * @param level :Fill Level.
+ * @retval Register value.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level)
+{
+ uint32_t result = (level << 12);
+
+ return(result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Convert Rx FIFO fill level to register.
+ * @param level :Fill Level.
+ * @retval Register value.
+ * @note -
+ */
+/*--------------------------------------------------*/
+__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level)
+{
+ uint32_t result;
+
+ if (level < 8)
+ {
+ result = (level << 8);
+ }
+ else
+ {
+ result = 0;
+ }
+
+ return(result);
+}
+
+#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE)
+/*--------------------------------------------------*/
+/**
+ * @brief Check the within error margin.
+ * @param boudrate :Boudrate(bps).
+ * @param clock :Clock(hz).
+ * @param p_clk :Select Clock Setting.
+ * @param boudrate :Boudrate(bps).
+ * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX"
+ * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX"
+ * @param p_range64 :Error range(after fixed point bit shift).
+ * @retval TXZ_SUCCESS :Within error margin.
+ * @retval TXZ_ERROR :Without error margin.
+ * @note For N+(64-K)/64 division.
+ */
+/*--------------------------------------------------*/
+static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64)
+{
+ TXZ_Result result = TXZ_ERROR;
+ uint64_t boud64 = 0;
+ uint64_t tx64 = 0;
+ uint64_t work64 = 0;
+
+ /* phi Tx */
+ uint32_t prescaler = (p_clk->prsel >> 4);
+
+ work64 = (uint64_t)((uint64_t)1 << prescaler);
+ tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT+2));
+ tx64 /= work64;
+
+ /* Bourate */
+ boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT);
+ *p_range64 = ((boud64/100)*UART_CFG_BOUDRATE_ERROR_RANGE);
+ /* BourateX */
+ work64 = (uint64_t)((uint64_t)n << 6);
+ work64 = (uint64_t)(work64 + (64-(uint64_t)k));
+ work64 = (tx64 / work64);
+ if (boud64 >= *p_range64)
+ {
+ if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64)))
+ {
+ if( boud64 < work64 )
+ {
+ *p_range64 = (work64 - boud64);
+ }
+ else
+ {
+ *p_range64 = (boud64 - work64);
+ }
+ result = TXZ_SUCCESS;
+ }
+ }
+
+ return (result);
+}
+#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */
+
+/**
+ * @}
+ */ /* End of group UART_Private_functions */
+
+
+/*------------------------------------------------------------------------------*/
+/* Public Function */
+/*------------------------------------------------------------------------------*/
+/**
+ * @addtogroup UART_Exported_functions
+ * @{
+ */
+/*--------------------------------------------------*/
+/**
+ * @brief Initialize the UART object.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_init(uart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(check_param_prescaler(p_obj->init.clock.prsel));
+ assert_param(check_param_division(p_obj->init.boudrate.ken));
+ assert_param(check_param_rangeK(p_obj->init.boudrate.brk));
+ assert_param(check_param_rangeN(p_obj->init.boudrate.brn));
+ assert_param(check_param_tx_int(p_obj->init.inttx));
+ assert_param(check_param_rx_int(p_obj->init.intrx));
+ assert_param(check_param_err_int(p_obj->init.interr));
+ assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx));
+ assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level));
+ assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx));
+ assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level));
+ assert_param(check_param_noize_filter(p_obj->init.nf));
+ assert_param(check_param_cts_handshake(p_obj->init.ctse));
+ assert_param(check_param_rts_handshake(p_obj->init.rtse));
+ assert_param(check_param_data_complemention(p_obj->init.iv));
+ assert_param(check_param_data_direction(p_obj->init.dir));
+ assert_param(check_param_stop_bit(p_obj->init.sblen));
+ assert_param(check_param_parity_bit(p_obj->init.even));
+ assert_param(check_param_parity_enable(p_obj->init.pe));
+ assert_param(check_param_data_length(p_obj->init.sm));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* SW Reset */
+ /*------------------------------*/
+ /*--- UARTxSWRST ---*/
+ /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */
+ /* Wait to "SWRSTF = 0". */
+ while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN)
+ {
+ /* no process */
+ }
+ /* Write to SWRST(=10). */
+ p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10;
+ /* Write to SWRST(=01). */
+ p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01;
+ /* Wait to "SWRSTF = 0". */
+ while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN)
+ {
+ /* no process */
+ }
+ /*------------------------------*/
+ /* FIFO Clear */
+ /*------------------------------*/
+ /*--- UARTxFIFOCLR ---*/
+ /* Write to TFCLR(=1), and RFCLR(=1) */
+ p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR);
+ /*------------------------------*/
+ /* Register Setting */
+ /*------------------------------*/
+ /*--- UARTxCLK ---*/
+ /* Reflecting "p_obj->init.clk" */
+ p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK);
+ /*--- UARTxBRD ---*/
+ /* Reflecting "p_obj->init.brd" */
+ /* Be careful, BRK needs to bit shit. */
+ {
+ uint32_t brk = (p_obj->init.boudrate.brk << 16);
+ p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn);
+ }
+ /*--- UARTxCR0 ---*/
+ /* Reflecting "p_obj->init.cnt0" */
+ p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm |
+ p_obj->init.hcc | p_obj->init.lbc |
+ p_obj->init.nf | p_obj->init.ctse |
+ p_obj->init.rtse | p_obj->init.iv |
+ p_obj->init.dir | p_obj->init.sblen |
+ p_obj->init.even | p_obj->init.pe |
+ p_obj->init.sm);
+ /*--- UARTxCR1 ---*/
+ /* Reflecting "p_obj->init.cnt1" */
+ /* Fixed: "DMATE=0", "DMARE=0". */
+ /* Be careful, "TIL", "RIL" need to bit shit. */
+ p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) |
+ convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) |
+ p_obj->init.txfifo.inttx | p_obj->init.inttx |
+ p_obj->init.rxfifo.intrx | p_obj->init.intrx |
+ p_obj->init.interr);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Release the UART object.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_deinit(uart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */
+ p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE |
+ UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE);
+ /*--- UARTxCR1 ---*/
+ p_obj->p_instance->CR1 = 0;
+ /*--- UARTxCR0 ---*/
+ p_obj->p_instance->CR0 = 0;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard transmit.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears transmit's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_discard_transmit(uart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t trans = 0;
+ uint32_t count = 10000000;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Read current UARTxTRANS value. */
+ trans = p_obj->p_instance->TRANS;
+ /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */
+ p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE |
+ UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE);
+ /*------------------------------*/
+ /* Refresh Setting */
+ /*------------------------------*/
+ /*--- UARTxSR ---*/
+ /* Clear the transmit's end flag. */
+ /* Write to TXEND(=1), and TXFF(=1). */
+ p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR);
+ while((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN)
+ {
+ if(--count == 0)
+ {
+ break;
+ }
+ }
+ /*--- UARTxFIFOCLR ---*/
+ /* Clear the transmit's FIFO. */
+ /* Write to TFCLR(=1). */
+ p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR);
+ /*--- UARTxERR ---*/
+ /* Clear the trigger error flag. */
+ /* Write to TRGERR(=1). */
+ p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR);
+ /*------------------------------*/
+ /* Enable Receive */
+ /*------------------------------*/
+ /* Return RXE setting to UARTxTRANS */
+ p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Discard receive.
+ * @param p_obj :UART object.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note This function clears receive's fifo, end flag and error info.
+ * @attention This function is not available in interrupt.
+ * @attention Use after interrupt is disabled.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_discard_receive(uart_t *p_obj)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+ uint32_t trans = 0;
+ uint32_t count = 10000000;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transfer */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Read current UARTxTRANS value. */
+ trans = p_obj->p_instance->TRANS;
+ /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */
+ p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE |
+ UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE);
+ /*------------------------------*/
+ /* Refresh Setting */
+ /*------------------------------*/
+ /*--- UARTxSR ---*/
+ /* Clear the receive's end flag. */
+ /* Write to RXEND(=1), and RXFF(=1). */
+ p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR);
+ while((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN)
+ {
+ if(--count == 0)
+ {
+ break;
+ }
+ }
+ /*--- UARTxFIFOCLR ---*/
+ /* Clear the transmit's FIFO. */
+ /* Write to RFCLR(=1). */
+ p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_RFCLR_CLEAR);
+ /*--- UARTxERR ---*/
+ /* Clear the trigger error flag. */
+ /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */
+ p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR |
+ UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR);
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /* Return TXE setting to UARTxTRANS */
+ p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK));
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Transmit data. Non-Blocking Communication.
+ * @param p_obj :UART object.
+ * @param p_info :The information of transmit data.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Asynchronous Processing.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if (p_obj->init.sm == UART_DATA_LENGTH_9 )
+ {
+ /* 9 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data));
+ assert_param(check_param_tx_buff_num(p_info->tx16.num));
+ }
+ else
+ {
+ /* 7/8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data));
+ assert_param(check_param_tx_buff_num(p_info->tx8.num));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to TXE(=0). */
+ /* Bitband Access. */
+ disable_UARTxTRANS_TXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ p_obj->transmit.rp = 0;
+ if (p_obj->init.sm == UART_DATA_LENGTH_9)
+ {
+ /* 9 bit */
+ p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data;
+ p_obj->transmit.info.tx16.num = p_info->tx16.num;
+ }
+ else
+ {
+ /* 7/8 bit */
+ p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data;
+ p_obj->transmit.info.tx8.num = p_info->tx8.num;
+ }
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ {
+ /*--- UARTxSR ---*/
+ /* Read FIFO fill level. */
+ /* Read current TLVL. */
+ uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK);
+ tlvl >>= 8;
+ /* FIFO Max = UART_TX_FIFO_MAX */
+ if (tlvl > UART_TX_FIFO_MAX)
+ {
+ tlvl = UART_TX_FIFO_MAX;
+ }
+ /* Empty FIFO Num */
+ {
+ uint32_t work = tlvl;
+ tlvl = (UART_TX_FIFO_MAX - work);
+ }
+ /*--- UARTxDR ---*/
+ /* Only the empty number of FIFO is a transmission data set. */
+ {
+ uint32_t i = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ /* Set data to FIFO. */
+ for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++)
+ {
+ switch (p_obj->init.sm)
+ {
+ case UART_DATA_LENGTH_9:
+ if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case UART_DATA_LENGTH_8:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case UART_DATA_LENGTH_7:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = ((uint32_t)*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ }
+ }
+ /*------------------------------*/
+ /* Enable Transmit */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to TXE(=1). */
+ /* Bitband Access. */
+ enable_UARTxTRANS_TXE(p_obj->p_instance);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Receive data. Non-Blocking Communication.
+ * @param p_obj :UART object.
+ * @param p_info :The information of receive buffer.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note Asynchronous Processing.
+ * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num.
+ * @attention This function is not available in interrupt.
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_info));
+ /* Check the parameter of transmit. */
+ if (p_obj->init.sm == UART_DATA_LENGTH_9 )
+ {
+ /* 9 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data));
+ assert_param(check_param_rx_buff_num(p_info->rx16.num));
+ }
+ else
+ {
+ /* 7/8 bit */
+ assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data));
+ assert_param(check_param_rx_buff_num(p_info->rx8.num));
+ }
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /* Write to RXE(=0). */
+ /* Bitband Access. */
+ disable_UARTxTRANS_RXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Information Setting */
+ /*------------------------------*/
+ if (p_obj->init.sm == UART_DATA_LENGTH_9 )
+ {
+ /* 9 bit */
+ p_obj->receive.info.rx16.p_data = p_info->rx16.p_data;
+ p_obj->receive.info.rx16.num = p_info->rx16.num;
+ }
+ else
+ {
+ /* 7/8 bit */
+ p_obj->receive.info.rx8.p_data = p_info->rx8.p_data;
+ p_obj->receive.info.rx8.num = p_info->rx8.num;
+ }
+ /*------------------------------*/
+ /* Enable Receive */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to RXE(=1). */
+ /* Bitband Access. */
+ enable_UARTxTRANS_RXE(p_obj->p_instance);
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for transmit.
+ * @param p_obj :UART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void uart_transmit_irq_handler(uart_t *p_obj)
+{
+ uint32_t trans;
+ uint32_t status;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current UARTxTRANS */
+ trans = p_obj->p_instance->TRANS;
+ /*------------------------------*/
+ /* Status Registar Control */
+ /*------------------------------*/
+ /* Read current UARTxSR. */
+ status = p_obj->p_instance->SR;
+ /* Clear the transmit's end flag. */
+ /* Write to TXEND(=1), and TXFF(=1). */
+ p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR);
+ /*------------------------------*/
+ /* Transmit Status Check */
+ /*------------------------------*/
+ if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE)
+ {
+ /*---- UARTxSR ---*/
+ /* Check the transmit's end flag. */
+ if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) ||
+ ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED))
+ {
+ TXZ_WorkState txDone = TXZ_BUSY;
+ /* Read FIFO fill level. */
+ uint32_t tlvl = (status & UARTxSR_TLVL_MASK);
+ tlvl >>= 8;
+ /* FIFO Max = UART_TX_FIFO_MAX */
+ if (tlvl > UART_TX_FIFO_MAX)
+ {
+ tlvl = UART_TX_FIFO_MAX;
+ }
+ /* Get the empty num in FIFO. */
+ {
+ uint32_t work = tlvl;
+ tlvl = (UART_TX_FIFO_MAX - work);
+ }
+ if (tlvl == UART_TX_FIFO_MAX)
+ {
+ switch (p_obj->init.sm)
+ {
+ case UART_DATA_LENGTH_9:
+ if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp)
+ {
+ txDone = TXZ_DONE;
+ }
+ break;
+ default:
+ if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp)
+ {
+ txDone = TXZ_DONE;
+ }
+ break;
+ }
+ }
+ if (txDone == TXZ_DONE)
+ {
+ /*=== Transmit Done!! ===*/
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to TXE(=0). */
+ /* Bitband Access. */
+ disable_UARTxTRANS_TXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->transmit.handler != UART_NULL)
+ {
+ /* Call the transmit handler with TXZ_SUCCESS. */
+ p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS);
+ }
+ }
+ else
+ {
+ /*=== Transmit Continue ===*/
+ /*------------------------------*/
+ /* Data Setting */
+ /*------------------------------*/
+ /*--- UARTxDR ---*/
+ /* Only the empty number of FIFO is a transmission data set. */
+ uint32_t i = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+ /* Set data to FIFO. */
+ for (i=0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++)
+ {
+ switch (p_obj->init.sm)
+ {
+ case UART_DATA_LENGTH_9:
+ if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case UART_DATA_LENGTH_8:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ case UART_DATA_LENGTH_7:
+ if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp)
+ {
+ p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK);
+ p_obj->transmit.rp += 1;
+ }
+ else
+ {
+ loopBreak = TXZ_DONE;
+ }
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for receive.
+ * @param p_obj :UART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void uart_receive_irq_handler(uart_t *p_obj)
+{
+ uint32_t trans;
+ uint32_t status;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current UARTxTRANS */
+ trans = p_obj->p_instance->TRANS;
+ /*------------------------------*/
+ /* Status Registar Control */
+ /*------------------------------*/
+ /* Read current UARTxSR. */
+ status = p_obj->p_instance->SR;
+ /* Clear the transmit's end flag. */
+ /* Write to RXEND(=1), and RXFF(=1). */
+ p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR);
+ /*------------------------------*/
+ /* Receive Status Check */
+ /*------------------------------*/
+ if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE)
+ {
+ /* Check the receive's end flag. */
+ if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) ||
+ ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED))
+ {
+ /* Read FIFO fill level. */
+ uint32_t rlvl = (status & UARTxSR_RLVL_MASK);
+ /* FIFO Max = UART_RX_FIFO_MAX */
+ if (rlvl > UART_RX_FIFO_MAX)
+ {
+ rlvl = UART_RX_FIFO_MAX;
+ }
+ /*------------------------------*/
+ /* Data Read */
+ /*------------------------------*/
+ /* Read FIFO data. */
+ if (rlvl != 0)
+ {
+ uint32_t i;
+ for (i=0; i<rlvl; i++)
+ {
+ switch (p_obj->init.sm)
+ {
+ case UART_DATA_LENGTH_9:
+ *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK);
+ break;
+ case UART_DATA_LENGTH_8:
+ *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK);
+ break;
+ case UART_DATA_LENGTH_7:
+ *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK);
+ break;
+ default:
+ /* no process */
+ break;
+ }
+ }
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != UART_NULL)
+ {
+ uart_receive_t param;
+
+ if (p_obj->init.sm == UART_DATA_LENGTH_9)
+ {
+ param.rx16.p_data = p_obj->receive.info.rx16.p_data;
+ param.rx16.num = rlvl;
+ }
+ else
+ {
+ param.rx8.p_data = p_obj->receive.info.rx8.p_data;
+ param.rx8.num = rlvl;
+ }
+ /* Call the receive handler with TXZ_SUCCESS. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m);
+ }
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief IRQ Handler for error.
+ * @param p_obj :UART object.
+ * @retval -
+ * @note -
+ */
+/*--------------------------------------------------*/
+void uart_error_irq_handler(uart_t *p_obj)
+{
+ uint32_t trans;
+ uint32_t error;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Trans Registar */
+ /*------------------------------*/
+ /* Read current UARTxTRANS */
+ trans = p_obj->p_instance->TRANS;
+ /*------------------------------*/
+ /* Error Registar Control */
+ /*------------------------------*/
+ /* Read current UARTxERR. */
+ error = p_obj->p_instance->ERR;
+ /* Now, no clear the error flag. */
+ /*------------------------------*/
+ /* Error Check */
+ /*------------------------------*/
+ /*--- UARTxERR ---*/
+ /* Check the transmit error. */
+ /* TRGERR */
+ if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR)
+ {
+ /*------------------------------*/
+ /* Transmit Check */
+ /*------------------------------*/
+ if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE)
+ {
+ /*------------------------------*/
+ /* Disable Transmit */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to TXE(=0). */
+ /* Bitband Access. */
+ disable_UARTxTRANS_TXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->transmit.handler != UART_NULL)
+ {
+ /* Call the transmit handler with TXZ_ERROR. */
+ p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR);
+ }
+ }
+ }
+ /* Check the receive error. */
+ {
+ TXZ_Result err = TXZ_SUCCESS;
+ /* OVRERR */
+ if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ /* PERR */
+ if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ /* FERR */
+ if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ /* BERR */
+ if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR)
+ {
+ err = TXZ_ERROR;
+ }
+ if (err == TXZ_ERROR)
+ {
+ /*------------------------------*/
+ /* Receive Check */
+ /*------------------------------*/
+ if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE)
+ {
+ /*------------------------------*/
+ /* Disable Receive */
+ /*------------------------------*/
+ /*--- UARTxTRANS ---*/
+ /* Write to RXE(=0). */
+ /* Bitband Access. */
+ disable_UARTxTRANS_RXE(p_obj->p_instance);
+ /*------------------------------*/
+ /* Call Handler */
+ /*------------------------------*/
+ if (p_obj->receive.handler != UART_NULL)
+ {
+ /* Call the receive handler with TXZ_ERROR. */
+ p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL);
+ }
+ }
+ }
+ }
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get status.
+ * @details Status bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. |
+ * | 30-16 | - | - |
+ * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. |
+ * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. |
+ * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. |
+ * | 12 | - | - |
+ * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel |
+ * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. |
+ * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. |
+ * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel |
+ * | 4 | - | - |
+ * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel |
+ *
+ * @param p_obj :UART object.
+ * @param p_status :Save area for status.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_status));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Status Read */
+ /*------------------------------*/
+ /*--- UARTxSR ---*/
+ /* Read current UARTxSR. */
+ *p_status = p_obj->p_instance->SR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get error information.
+ * @details Error bits.
+ * | Bit | Bit Symbol | Function |
+ * | :--- | :--- | :--- |
+ * | 31-5 | - | - |
+ * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. |
+ * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. |
+ * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. |
+ * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. |
+ * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. |
+ *
+ * @param p_obj :UART object.
+ * @param p_error :Save area for error.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Failure.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error)
+{
+ TXZ_Result result = TXZ_SUCCESS;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the UART_NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_obj));
+ assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
+ assert_param(IS_POINTER_NOT_NULL(p_error));
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Error Read */
+ /*------------------------------*/
+ /*--- UARTxERR ---*/
+ /* Read current UARTxERR. */
+ *p_error = p_obj->p_instance->ERR;
+
+ return (result);
+}
+
+/*--------------------------------------------------*/
+/**
+ * @brief Get the setting of boudrate.
+ * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B".
+ * @param p_clk :Select Clock Setting.
+ * @param boudrate :Boudrate(bps).
+ * @param p_brd :Save area for Division Setting.
+ * @retval TXZ_SUCCESS :Success.
+ * @retval TXZ_ERROR :Not support setting.
+ * @note -
+ */
+/*--------------------------------------------------*/
+TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd)
+{
+ TXZ_Result result = TXZ_ERROR;
+#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE)
+ uint64_t tx = 0;
+ uint64_t work = 0;
+ uint64_t range64 = 0;
+
+ /*------------------------------*/
+ /* Parameter Check */
+ /*------------------------------*/
+#ifdef DEBUG
+ /* Check the NULL of address. */
+ assert_param(IS_POINTER_NOT_NULL(p_clk));
+ assert_param(IS_POINTER_NOT_NULL(p_brd));
+ /* Check the parameter of UARTxCLK. */
+#endif /* #ifdef DEBUG */
+ /*------------------------------*/
+ /* Calculate Division Setting */
+ /*------------------------------*/
+ if ((clock > 0) && (boudrate > 0))
+ {
+ /*--- phi Tx ---*/
+ uint32_t prescaler = (p_clk->prsel >> 4);
+
+ work = (uint64_t)((uint64_t)1 << prescaler);
+ tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT);
+ tx /= work;
+
+ /*--- N+(64-K)/64 division ---*/
+ {
+ uint8_t k = 0;
+ TXZ_WorkState loopBreak = TXZ_BUSY;
+
+ work = ((uint64_t)boudrate);
+ tx /= work;
+ tx >>= 4;
+ for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++)
+ {
+ work = tx + (uint64_t)k;
+ if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT))
+ {
+ work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT);
+ work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */
+ if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX))
+ {
+ uint64_t workRange = 0;
+
+ /* Verification */
+ if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS)
+ {
+#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL)
+ /* Compare the previous range. */
+ if (result == TXZ_SUCCESS)
+ {
+ if (range64 > workRange)
+ {
+ p_brd->ken = UART_DIVISION_ENABLE;
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ range64 = workRange;
+ }
+ }
+ else
+ {
+ p_brd->ken = UART_DIVISION_ENABLE;
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ range64 = workRange;
+ }
+ result = TXZ_SUCCESS;
+#else
+ /* Finish!! */
+ if (result == TXZ_SUCCESS)
+ {
+ if (range64 > workRange)
+ {
+ p_brd->ken = UART_DIVISION_ENABLE;
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ }
+ }
+ else
+ {
+ p_brd->ken = UART_DIVISION_ENABLE;
+ p_brd->brk = (uint32_t)k;
+ p_brd->brn = (uint32_t)work;
+ }
+ result = TXZ_SUCCESS;
+ loopBreak = TXZ_DONE;
+#endif
+ }
+ }
+ }
+ }
+ }
+ }
+#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */
+
+ return (result);
+}
+
+/**
+ * @}
+ */ /* End of group UART_Exported_functions */
+
+/**
+ * @}
+ */ /* End of group UART */
+
+/**
+ * @}
+ */ /* End of group Periph_Driver */
+
+#endif /* defined(__UART_H) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/PeripheralNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,192 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ SERIAL_0 = 0,
+ SERIAL_1,
+ SERIAL_2,
+ SERIAL_3,
+ SERIAL_4,
+ SERIAL_5,
+ SERIAL_6,
+ SERIAL_7,
+ INVALID_SERIAL = (int)NC
+} UARTName;
+
+typedef enum {
+ DAC_0 = 0,
+ DAC_1,
+ INVALID_DAC = (int)NC
+} DACName;
+
+typedef enum {
+ PWM_0 = 0,
+ PWM_1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11,
+ PWM_12,
+ INVALID_PWM = (int)NC
+} PWMName;
+
+typedef enum {
+ ADC_A0 = 0,
+ ADC_A1,
+ ADC_A2,
+ ADC_A3,
+ ADC_A4,
+ ADC_A5,
+ ADC_A6,
+ ADC_A7,
+ ADC_A8,
+ ADC_A9,
+ ADC_A10,
+ ADC_A11,
+ ADC_A12,
+ ADC_A13,
+ ADC_A14,
+ ADC_A15,
+ ADC_A16,
+ ADC_A17,
+ ADC_A18,
+ ADC_A19,
+ ADC_A20,
+ ADC_A21,
+ ADC_A22,
+ ADC_A23,
+ INVALID_ADC = (int)NC
+} ADCName;
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1,
+ I2C_2,
+ I2C_3,
+ I2C_4,
+ INVALID_I2C = (int)NC
+} I2CName;
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1,
+ SPI_2,
+ SPI_3,
+ SPI_4,
+ SPI_5,
+ SPI_6,
+ SPI_7,
+ SPI_8,
+ INVALID_SPI = (int)NC
+} SPIName;
+
+typedef enum {
+ GPIO_IRQ_0 = 0,
+ GPIO_IRQ_1,
+ GPIO_IRQ_2,
+ GPIO_IRQ_3,
+ GPIO_IRQ_4,
+ GPIO_IRQ_5,
+ GPIO_IRQ_6,
+ GPIO_IRQ_7,
+ GPIO_IRQ_8,
+ GPIO_IRQ_9,
+ GPIO_IRQ_A,
+ GPIO_IRQ_B,
+ GPIO_IRQ_C,
+ GPIO_IRQ_D,
+ GPIO_IRQ_E,
+ GPIO_IRQ_F,
+ INVALID_GPIO_IRQ = (int)NC
+} GPIO_IRQName;
+
+// DAP UART
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+
+#define SERIAL_TX PU0
+#define SERIAL_RX PU1
+
+#define STDIO_UART SERIAL_4
+
+// TxD RxD
+#define MBED_UART0 PE3, PE2
+#define MBED_UART1 PH1, PH0
+#define MBED_UART2 PG1, PG0
+#define MBED_UART3 PU7, PU6
+#define MBED_UART4 PM1, PM0
+#define MBED_UART5 PJ1, PJ0
+#define MBED_UART6 PG4, PG5
+#define MBED_UART7 PJ6, PJ7
+#define MBED_UARTUSB USBTX, USBRX
+
+// SDA SCK
+#define MBED_I2C0 PG2, PG3
+#define MBED_I2C1 PF2, PF3
+#define MBED_I2C2 PG4, PG5
+#define MBED_I2C3 PJ6, PJ7
+#define MBED_I2C4 PJ3, PJ2
+
+// MOSI, MISO, SCLK SS
+#define MBED_SPI0 PA3, PA2, PA1, PA0
+#define MBED_SPI1 PL3, PL2, PL1, PL0
+#define MBED_SPI2 PA4, PA5, PA6, PA7
+#define MBED_SPI3 PK4, PK5, PK6, PK7
+#define MBED_SPI4 PD3, PD2, PD1, PD0
+#define MBED_SPI5 PV5, PV4, PV6, PV7
+#define MBED_SPI6 PM0, PM1, PM2, PM3
+#define MBED_SPI7 PM7, PM6, PM5, PM4
+#define MBED_SPI8 PW3, PW2, PW1, PW0
+
+#define MBED_ANALOGIN0 A0
+#define MBED_ANALOGIN1 A1
+#define MBED_ANALOGIN2 A2
+#define MBED_ANALOGIN3 A3
+#define MBED_ANALOGIN4 A4
+#define MBED_ANALOGIN5 A5
+
+#define MBED_PWMOUT0 PA5
+#define MBED_PWMOUT1 PB2
+#define MBED_PWMOUT2 PB4
+#define MBED_PWMOUT3 PD2
+#define MBED_PWMOUT4 PD4
+#define MBED_PWMOUT5 PE1
+#define MBED_PWMOUT6 PE6
+#define MBED_PWMOUT7 PC2
+#define MBED_PWMOUT8 PL6
+#define MBED_PWMOUT9 PC4
+#define MBED_PWMOUT10 PM2
+#define MBED_PWMOUT11 PU0
+#define MBED_PWMOUT12 PU6
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/PinNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF)
+#define PIN_POS(X) ((uint32_t)(X) & 0x7)
+
+// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
+#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
+#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16)
+#define PIN_DIR(X) ((X) & 0xffff)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT,
+ PIN_INOUT
+} PinDirection;
+
+typedef enum {
+ // TMPM4G9 Pin Names
+ PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+ PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+ PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
+ PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7,
+ PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+ PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+ PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
+ PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
+ PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7,
+ PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7,
+ PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7,
+ PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7,
+ PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7,
+ PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7,
+ PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7,
+ PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5,
+ PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7,
+ PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7,
+ PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7,
+ PY0 = 19 << 3, PY1, PY2, PY3, PY4,
+
+ // Other mbed Pin Names
+ LED1 = PE4,
+ LED2 = PE5,
+ LED3 = PE6,
+ LED4 = PE7,
+
+ // External data bus Pin Names
+ D0 = PJ0,
+ D1 = PJ1,
+ D2 = PF4,
+ D3 = PB2,
+ D4 = PF5,
+ D5 = PB4,
+ D6 = PC2,
+ D7 = PF6,
+ D8 = PA4,
+ D9 = PC4,
+ D10 = PA0,
+ D11 = PA3,
+ D12 = PA2,
+ D13 = PA1,
+ D14 = PG2,
+ D15 = PG3,
+
+ // Analogue in pins
+ A0 = PN0,
+ A1 = PN1,
+ A2 = PN2,
+ A3 = PN3,
+ A4 = PN4,
+ A5 = PN5,
+
+ // USB2_UART
+ USBTX = PU0,
+ USBRX = PU1,
+ MBEDIF_TXD = USBTX,
+ MBEDIF_RXD = USBRX,
+
+ MBED_CONF_APP_UART0_TX = PE3,
+ MBED_CONF_APP_UART0_RX = PE2,
+
+ // Switches
+ SW1 = PL4,
+ SW2 = PL5,
+ SW3 = PV0,
+ SW4 = PV1,
+
+ // I2C pins
+ SDA = PG2,
+ SCL = PG3,
+ I2C_SDA = SDA,
+ I2C_SCL = SCL,
+
+ // Analogue out
+ DAC0 = PT0,
+ DAC1 = PT1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown,
+ PullNone,
+ OpenDrain,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/PortNames.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB,
+ PortC,
+ PortD,
+ PortE,
+ PortF,
+ PortG,
+ PortH,
+ PortJ,
+ PortK,
+ PortL,
+ PortM,
+ PortN,
+ PortP,
+ PortR,
+ PortT,
+ PortU,
+ PortV,
+ PortW,
+ PortY
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/analogin_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_wait_api.h"
+#include "mbed_error.h"
+#include "adc_include.h"
+
+#define ADC_12BIT_RANGE 0xFFF
+#define CONVERSION_FLAG 0x4
+
+static const PinMap PinMap_ADC[] = {
+ {PN0, ADC_A0, PIN_DATA(0, 0)},
+ {PN1, ADC_A1, PIN_DATA(0, 0)},
+ {PN2, ADC_A2, PIN_DATA(0, 0)},
+ {PN3, ADC_A3, PIN_DATA(0, 0)},
+ {PN4, ADC_A4, PIN_DATA(0, 0)},
+ {PN5, ADC_A5, PIN_DATA(0, 0)},
+ {PN6, ADC_A6, PIN_DATA(0, 0)},
+ {PN7, ADC_A7, PIN_DATA(0, 0)},
+ {PP0, ADC_A8, PIN_DATA(0, 0)},
+ {PP1, ADC_A9, PIN_DATA(0, 0)},
+ {PP2, ADC_A10, PIN_DATA(0, 0)},
+ {PP3, ADC_A11, PIN_DATA(0, 0)},
+ {PP4, ADC_A12, PIN_DATA(0, 0)},
+ {PP5, ADC_A13, PIN_DATA(0, 0)},
+ {PP6, ADC_A14, PIN_DATA(0, 0)},
+ {PP7, ADC_A15, PIN_DATA(0, 0)},
+ {PR0, ADC_A16, PIN_DATA(0, 0)},
+ {PR1, ADC_A17, PIN_DATA(0, 0)},
+ {PR2, ADC_A18, PIN_DATA(0, 0)},
+ {PR3, ADC_A19, PIN_DATA(0, 0)},
+ {PR4, ADC_A20, PIN_DATA(0, 0)},
+ {PR5, ADC_A21, PIN_DATA(0, 0)},
+ {PR6, ADC_A22, PIN_DATA(0, 0)},
+ {PR7, ADC_A23, PIN_DATA(0, 0)},
+ {NC, NC, 0}
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ // Check that pin belong to ADC module
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ // Enable ADC clock supply
+ TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE;
+ TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE;
+ TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE;
+
+ // Enable clock for GPIO
+ if (obj->adc <= ADC_A7) {
+ TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE;
+ } else if (obj->adc <= ADC_A15) {
+ TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE;
+ } else {
+ TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE;
+ }
+
+ // Set pin function as ADC
+ pinmap_pinout(pin, PinMap_ADC);
+
+ // Initialize
+ obj->p_adc.p_instance = TSB_ADA;
+ obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN;
+ obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN;
+ obj->p_adc.init.clk.vadcld = ADC_SCLK_1;
+ obj->p_adc.init.clk.sampling_select = 0;
+ obj->p_adc.init.mod1 = ADC_MOD1_SCLK_3;
+ obj->p_adc.init.mod2 = ADC_MOD2_TMPM4G9;
+ obj->p_adc.handler.single = NULL;
+ obj->p_adc.handler.continuity = NULL;
+ obj->p_adc.handler.trigger = NULL;
+ obj->p_adc.handler.highpriority = NULL;
+
+ if (adc_init(&obj->p_adc) != TXZ_SUCCESS) {
+ error("Failed : ADC Initialization");
+ }
+
+ // ADC channel setting
+ obj->param.interrupt = ADC_INT_DISABLE;
+ obj->param.type = ADC_CONVERSION_SGL;
+ obj->param.ain = obj->adc;
+
+ if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) {
+ error("Failed : ADC channel setting");
+ }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint32_t adc_result = 0;
+
+ // Assert that ADC channel is valid
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ if (adc_start(&obj->p_adc) == TXZ_SUCCESS) {
+ // adc started
+ }
+
+ // Wait for Continuous conversion program flag clear.
+ while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) {
+ // Do nothing
+ }
+
+ if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) {
+ error("Failed : To read ADC converted result");
+ }
+
+ if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) {
+ error("Failed : To Stop ADC Conversion");
+ }
+
+ return (uint16_t)adc_result;
+}
+
+float analogin_read(analogin_t *obj)
+{
+ uint16_t value = 0;
+
+ value = analogin_read_u16(obj);
+
+ return (float)(value * (1.0f / (float)ADC_12BIT_RANGE));
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/analogout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "analogout_api.h"
+#include "pinmap.h"
+
+#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable.
+#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable.
+#define DAC_RANGE (0xFF) // 8 bits
+#define DAC_NB_BITS (8)
+#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out
+#define DAC1_CLR_IN_CLR_OUT (2)
+#define MAX_ANALOG_VAL (1.0f)
+#define MIN_ANALOG_VAL (0.0f)
+#define MAX_DIGITAL_VAL (0xFF)
+#define MIN_DIGITAL_VAL (0x00)
+
+static const PinMap PinMap_DAC[] = {
+ {PT0, DAC_0, PIN_DATA(0, 1)},
+ {PT1, DAC_1, PIN_DATA(0, 1)},
+ {NC, NC, 0}
+};
+
+static inline void dac_write(dac_t *obj,int val)
+{
+ // Set the DAC output
+ obj->DACx->REG = (val &= DAC_RANGE);
+}
+
+static inline int dac_read(dac_t *obj)
+{
+ return ((obj->DACx->REG) & DAC_RANGE);
+}
+
+void analogout_init(dac_t *obj, PinName pin)
+{
+ DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+
+ MBED_ASSERT(dac_name != (DACName)NC);
+
+ obj->dac = dac_name;
+ switch (dac_name) {
+ case DAC_0:
+ obj->DACx = TSB_DA0;
+ // Enable clock for DAC0 and Port T
+ TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE;
+ break;
+ case DAC_1:
+ obj->DACx = TSB_DA1;
+ // Enable clock for DAC1 and Port T
+ TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE;
+ break;
+ default:
+ break;
+ }
+
+ // Pinout the chosen DAC
+ pinmap_pinout(pin, PinMap_DAC);
+
+ // DAC pins as neither input and nor output
+ if (dac_name == DAC_0) {
+ TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT);
+ TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT);
+ } else if (dac_name == DAC_1) {
+ TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT);
+ TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT);
+ } else {
+ return;
+ }
+
+ // Enable DAC
+ obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE;
+ analogout_write_u16(obj, MIN_DIGITAL_VAL);
+}
+
+void analogout_free(dac_t *obj)
+{
+ obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE;
+ obj->dac = (DACName)NC;
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+ if (value < MIN_ANALOG_VAL) {
+ dac_write(obj, MIN_DIGITAL_VAL);
+ } else if (value > MAX_ANALOG_VAL) {
+ dac_write(obj,DAC_RANGE);
+ } else {
+ dac_write(obj, value * (float)DAC_RANGE);
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+ // Writing higher 8-bits to Data Register
+ dac_write(obj, (value >> (16 - DAC_NB_BITS)));
+}
+
+float analogout_read(dac_t *obj)
+{
+ uint32_t value = 0;
+
+ value = dac_read(obj);
+
+ return (float)value * (MAX_ANALOG_VAL / (float)DAC_RANGE);
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+ uint32_t value = 0;
+
+ value = dac_read(obj);
+ // Upper and lower byte stored with read value
+ return ((value << (16 - DAC_NB_BITS)) | value);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 32 + +#include <stddef.h> +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TMPM4G9.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,6129 @@
+/**
+ *******************************************************************************
+ * @file TMPM4G9.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the
+ * TOSHIBA 'TMPM4G9' Device Series
+ * @version V1.0.9.0
+ * $Date:: 2018-04-02 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER
+ * @{
+ */
+
+/** @addtogroup TMPM4G9
+ * @{
+ */
+
+#ifndef __TMPM4G9_H__
+#define __TMPM4G9_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** TMPM4G9 Specific Interrupt Numbers *******************************************************************/
+ INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */
+ INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */
+ INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */
+ INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */
+ INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */
+ INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */
+ INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */
+ INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */
+ INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */
+ INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */
+ INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */
+ INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */
+ INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */
+ INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */
+ INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */
+ INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */
+ INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */
+ INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */
+ INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */
+ INTISDA_IRQn = 19, /*!< Interval Sensing Detector Interrupt (Unit A) */
+ INTISDB_IRQn = 20, /*!< Interval Sensing Detector Interrupt (Unit B) */
+ INTISDC_IRQn = 21, /*!< Interval Sensing Detector Interrupt (Unit C) */
+ INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */
+ INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */
+ INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */
+ INTHDMAATC_IRQn = 25, /*!< HDMA Complete of transfer(Unit A) */
+ INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */
+ INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */
+ INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */
+ INTMDMAATC_IRQn = 29, /*!< MDMA Complete of transfer(Unit A) */
+ INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA All Interrupt/Timer Interrupt C */
+ INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C*/
+ INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */
+ INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */
+ INTPWM0_IRQn = 60, /*!< PMD0 interrupt */
+ INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) */
+ INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) */
+ INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) */
+ INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) */
+ INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) */
+ INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) */
+ INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) */
+ INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) */
+ INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) */
+ INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) */
+ INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) */
+ INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) */
+ INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) */
+ INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) */
+ INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) */
+ INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) */
+ INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) */
+ INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) */
+ INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) */
+ INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) */
+ INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) */
+ INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) */
+ INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) */
+ INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) */
+ INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) */
+ INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) */
+ INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) */
+ INTSMI0_IRQn = 88, /*!< Serial Memory Interface Interrupt */
+ INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) */
+ INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) */
+ INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) */
+ INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) */
+ INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) */
+ INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) */
+ INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) */
+ INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) */
+ INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) */
+ INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) */
+ INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) */
+ INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) */
+ INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) */
+ INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) */
+ INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) */
+ INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) */
+ INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) */
+ INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) */
+ INTFUART0_IRQn = 107, /*!< FUART Interrupt(channel 0) */
+ INTFUART1_IRQn = 108, /*!< FUART Interrupt(channel 1) */
+ INTI2C0_IRQn = 109, /*!< I2C0 transmission and reception interrupt */
+ INTI2C0AL_IRQn = 110, /*!< I2C0 arbitration lost interrupt */
+ INTI2C0BF_IRQn = 111, /*!< I2C0 bus free interrupt */
+ INTI2C0NACK_IRQn = 112, /*!< I2C0 no ack interrupt */
+ INTI2C1_IRQn = 113, /*!< I2C1 transmission and reception interrupt */
+ INTI2C1AL_IRQn = 114, /*!< I2C1 arbitration lost interrupt */
+ INTI2C1BF_IRQn = 115, /*!< I2C1 bus free interrupt */
+ INTI2C1NACK_IRQn = 116, /*!< I2C1 no ack interrupt */
+ INTI2C2_IRQn = 117, /*!< I2C2 transmission and reception interrupt */
+ INTI2C2AL_IRQn = 118, /*!< I2C2 arbitration lost interrupt */
+ INTI2C2BF_IRQn = 119, /*!< I2C2 bus free interrupt */
+ INTI2C2NACK_IRQn = 120, /*!< I2C2 no ack interrupt */
+ INTI2C3_IRQn = 121, /*!< I2C3 transmission and reception interrupt */
+ INTI2C3AL_IRQn = 122, /*!< I2C3 arbitration lost interrupt */
+ INTI2C3BF_IRQn = 123, /*!< I2C3 bus free interrupt */
+ INTI2C3NACK_IRQn = 124, /*!< I2C3 no ack interrupt */
+ INTI2C4_IRQn = 125, /*!< I2C4 transmission and reception interrupt */
+ INTI2C4AL_IRQn = 126, /*!< I2C4 arbitration lost interrupt */
+ INTI2C4BF_IRQn = 127, /*!< I2C4 bus free interrupt */
+ INTI2C4NACK_IRQn = 128, /*!< I2C4 no ack interrupt */
+ INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */
+ INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */
+ INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */
+ INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */
+ INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */
+ INTADAHP_IRQn = 134, /*!< ADC High Priority AD conversion interrupt */
+ INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */
+ INTFLCRDY0_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */
+ INTFLCRDY1_IRQn = 137, /*!< Code FLASH Area2 Ready interrupt */
+ INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) */
+ INTMDMAADERR_IRQn = 140 /*!< MDMA descriptor error(Unit A) */
+} IRQn_Type;
+
+/** Processor and Core Peripheral Section */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_TMPM4G9.h" /* TMPM4G9 System */
+
+/** @addtogroup Device_Peripheral_registers
+ * @{
+ */
+
+/** Device Specific Peripheral registers structures */
+
+/**
+ * @brief DMA Controller
+ */
+typedef struct
+{
+ __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */
+ __I uint32_t INTTCSTATUS; /*!< DMAC Interrupt Terminal Count Status Register*/
+ __O uint32_t INTTCCLEAR; /*!< DMAC Interrupt Terminal Count Clear Register */
+ __I uint32_t INTERRORSTATUS; /*!< DMAC Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /*!< DMAC Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Interrupt Terminal Count Status Register*/
+ __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /*!< DMAC Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Request Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */
+ uint32_t RESERVED1[51];
+ __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Source Address Register */
+ __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Destination Address Register */
+ __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */
+ __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */
+ __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */
+ uint32_t RESERVED2[3];
+ __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Source Address Register */
+ __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Destination Address Register */
+ __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */
+ __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */
+ __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */
+} TSB_DMAC_TypeDef;
+
+/**
+ * @brief
+ */
+typedef struct
+{
+ __IO uint32_t MAP0; /*!< SMIF Flash Memory Map0 Register */
+ __IO uint32_t MAP1; /*!< SMIF Flash Memory Map1 Register */
+ __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */
+ __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */
+ __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */
+ __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */
+ uint32_t RESERVED0[250];
+ __IO uint32_t RACR0; /*!< SMIF Program Register Access Control Register 0*/
+ __IO uint32_t RACR1; /*!< SMIF Program Register Access Control Register 1*/
+ __IO uint32_t INT; /*!< SMIF Program Register Access Interrupt Enable Register*/
+ __IO uint32_t STAT; /*!< SMIF Program Register Access Status Register */
+ uint32_t RESERVED1[60];
+ __IO uint32_t PBUF0; /*!< SMIF Program Register Primary Buffer Data Register 0*/
+ __IO uint32_t PBUF1; /*!< SMIF Program Register Primary Buffer Data Register 1*/
+ uint32_t RESERVED2[62];
+ __IO uint32_t SBUF00; /*!< SMIF Program Register Secondary Buffer Data Register 00*/
+ __IO uint32_t SBUF01; /*!< SMIF Program Register Secondary Buffer Data Register 01*/
+ __IO uint32_t SBUF02; /*!< SMIF Program Register Secondary Buffer Data Register 02*/
+ __IO uint32_t SBUF03; /*!< SMIF Program Register Secondary Buffer Data Register 03*/
+ __IO uint32_t SBUF04; /*!< SMIF Program Register Secondary Buffer Data Register 04*/
+ __IO uint32_t SBUF05; /*!< SMIF Program Register Secondary Buffer Data Register 05*/
+ __IO uint32_t SBUF06; /*!< SMIF Program Register Secondary Buffer Data Register 06*/
+ __IO uint32_t SBUF07; /*!< SMIF Program Register Secondary Buffer Data Register 07*/
+ __IO uint32_t SBUF08; /*!< SMIF Program Register Secondary Buffer Data Register 08*/
+ __IO uint32_t SBUF09; /*!< SMIF Program Register Secondary Buffer Data Register 09*/
+ __IO uint32_t SBUF10; /*!< SMIF Program Register Secondary Buffer Data Register 10*/
+ __IO uint32_t SBUF11; /*!< SMIF Program Register Secondary Buffer Data Register 11*/
+ __IO uint32_t SBUF12; /*!< SMIF Program Register Secondary Buffer Data Register 12*/
+ __IO uint32_t SBUF13; /*!< SMIF Program Register Secondary Buffer Data Register 13*/
+ __IO uint32_t SBUF14; /*!< SMIF Program Register Secondary Buffer Data Register 14*/
+ __IO uint32_t SBUF15; /*!< SMIF Program Register Secondary Buffer Data Register 15*/
+ __IO uint32_t SBUF16; /*!< SMIF Program Register Secondary Buffer Data Register 16*/
+ __IO uint32_t SBUF17; /*!< SMIF Program Register Secondary Buffer Data Register 17*/
+ __IO uint32_t SBUF18; /*!< SMIF Program Register Secondary Buffer Data Register 18*/
+ __IO uint32_t SBUF19; /*!< SMIF Program Register Secondary Buffer Data Register 19*/
+ __IO uint32_t SBUF20; /*!< SMIF Program Register Secondary Buffer Data Register 20*/
+ __IO uint32_t SBUF21; /*!< SMIF Program Register Secondary Buffer Data Register 21*/
+ __IO uint32_t SBUF22; /*!< SMIF Program Register Secondary Buffer Data Register 22*/
+ __IO uint32_t SBUF23; /*!< SMIF Program Register Secondary Buffer Data Register 23*/
+ __IO uint32_t SBUF24; /*!< SMIF Program Register Secondary Buffer Data Register 24*/
+ __IO uint32_t SBUF25; /*!< SMIF Program Register Secondary Buffer Data Register 25*/
+ __IO uint32_t SBUF26; /*!< SMIF Program Register Secondary Buffer Data Register 26*/
+ __IO uint32_t SBUF27; /*!< SMIF Program Register Secondary Buffer Data Register 27*/
+ __IO uint32_t SBUF28; /*!< SMIF Program Register Secondary Buffer Data Register 28*/
+ __IO uint32_t SBUF29; /*!< SMIF Program Register Secondary Buffer Data Register 29*/
+ __IO uint32_t SBUF30; /*!< SMIF Program Register Secondary Buffer Data Register 30*/
+ __IO uint32_t SBUF31; /*!< SMIF Program Register Secondary Buffer Data Register 31*/
+ __IO uint32_t SBUF32; /*!< SMIF Program Register Secondary Buffer Data Register 32*/
+ __IO uint32_t SBUF33; /*!< SMIF Program Register Secondary Buffer Data Register 33*/
+ __IO uint32_t SBUF34; /*!< SMIF Program Register Secondary Buffer Data Register 34*/
+ __IO uint32_t SBUF35; /*!< SMIF Program Register Secondary Buffer Data Register 35*/
+ __IO uint32_t SBUF36; /*!< SMIF Program Register Secondary Buffer Data Register 36*/
+ __IO uint32_t SBUF37; /*!< SMIF Program Register Secondary Buffer Data Register 37*/
+ __IO uint32_t SBUF38; /*!< SMIF Program Register Secondary Buffer Data Register 38*/
+ __IO uint32_t SBUF39; /*!< SMIF Program Register Secondary Buffer Data Register 39*/
+ __IO uint32_t SBUF40; /*!< SMIF Program Register Secondary Buffer Data Register 40*/
+ __IO uint32_t SBUF41; /*!< SMIF Program Register Secondary Buffer Data Register 41*/
+ __IO uint32_t SBUF42; /*!< SMIF Program Register Secondary Buffer Data Register 42*/
+ __IO uint32_t SBUF43; /*!< SMIF Program Register Secondary Buffer Data Register 43*/
+ __IO uint32_t SBUF44; /*!< SMIF Program Register Secondary Buffer Data Register 44*/
+ __IO uint32_t SBUF45; /*!< SMIF Program Register Secondary Buffer Data Register 45*/
+ __IO uint32_t SBUF46; /*!< SMIF Program Register Secondary Buffer Data Register 46*/
+ __IO uint32_t SBUF47; /*!< SMIF Program Register Secondary Buffer Data Register 47*/
+ __IO uint32_t SBUF48; /*!< SMIF Program Register Secondary Buffer Data Register 48*/
+ __IO uint32_t SBUF49; /*!< SMIF Program Register Secondary Buffer Data Register 49*/
+ __IO uint32_t SBUF50; /*!< SMIF Program Register Secondary Buffer Data Register 50*/
+ __IO uint32_t SBUF51; /*!< SMIF Program Register Secondary Buffer Data Register 51*/
+ __IO uint32_t SBUF52; /*!< SMIF Program Register Secondary Buffer Data Register 52*/
+ __IO uint32_t SBUF53; /*!< SMIF Program Register Secondary Buffer Data Register 53*/
+ __IO uint32_t SBUF54; /*!< SMIF Program Register Secondary Buffer Data Register 54*/
+ __IO uint32_t SBUF55; /*!< SMIF Program Register Secondary Buffer Data Register 55*/
+ __IO uint32_t SBUF56; /*!< SMIF Program Register Secondary Buffer Data Register 56*/
+ __IO uint32_t SBUF57; /*!< SMIF Program Register Secondary Buffer Data Register 57*/
+ __IO uint32_t SBUF58; /*!< SMIF Program Register Secondary Buffer Data Register 58*/
+ __IO uint32_t SBUF59; /*!< SMIF Program Register Secondary Buffer Data Register 59*/
+ __IO uint32_t SBUF60; /*!< SMIF Program Register Secondary Buffer Data Register 60*/
+ __IO uint32_t SBUF61; /*!< SMIF Program Register Secondary Buffer Data Register 61*/
+ __IO uint32_t SBUF62; /*!< SMIF Program Register Secondary Buffer Data Register 62*/
+ __IO uint32_t SBUF63; /*!< SMIF Program Register Secondary Buffer Data Register 63*/
+} TSB_SMI_TypeDef;
+
+/**
+ * @brief Interrupt control A Register
+ */
+typedef struct
+{
+ __IO uint8_t NIC00; /*!< Non Maskable interrupt Mode Control Register A 00*/
+ uint8_t RESERVED0[31];
+ __IO uint8_t IMC00; /*!< interrupt Mode Control Register A 00 */
+ __IO uint8_t IMC01; /*!< interrupt Mode Control Register A 01 */
+ __IO uint8_t IMC02; /*!< interrupt Mode Control Register A 02 */
+ __IO uint8_t IMC03; /*!< interrupt Mode Control Register A 03 */
+ __IO uint8_t IMC04; /*!< interrupt Mode Control Register A 04 */
+ __IO uint8_t IMC05; /*!< interrupt Mode Control Register A 05 */
+ __IO uint8_t IMC06; /*!< interrupt Mode Control Register A 06 */
+ __IO uint8_t IMC07; /*!< interrupt Mode Control Register A 07 */
+ __IO uint8_t IMC08; /*!< interrupt Mode Control Register A 08 */
+ __IO uint8_t IMC09; /*!< interrupt Mode Control Register A 09 */
+ __IO uint8_t IMC10; /*!< interrupt Mode Control Register A 10 */
+ __IO uint8_t IMC11; /*!< interrupt Mode Control Register A 11 */
+ __IO uint8_t IMC12; /*!< interrupt Mode Control Register A 12 */
+ __IO uint8_t IMC13; /*!< interrupt Mode Control Register A 13 */
+ __IO uint8_t IMC14; /*!< interrupt Mode Control Register A 14 */
+ __IO uint8_t IMC15; /*!< interrupt Mode Control Register A 15 */
+ __IO uint8_t IMC16; /*!< interrupt Mode Control Register A 16 */
+ __IO uint8_t IMC17; /*!< interrupt Mode Control Register A 17 */
+ __IO uint8_t IMC18; /*!< interrupt Mode Control Register A 18 */
+ __IO uint8_t IMC19; /*!< interrupt Mode Control Register A 19 */
+ __IO uint8_t IMC20; /*!< interrupt Mode Control Register A 20 */
+ __IO uint8_t IMC21; /*!< interrupt Mode Control Register A 21 */
+ __IO uint8_t IMC22; /*!< interrupt Mode Control Register A 22 */
+ __IO uint8_t IMC23; /*!< interrupt Mode Control Register A 23 */
+ __IO uint8_t IMC24; /*!< interrupt Mode Control Register A 24 */
+ __IO uint8_t IMC25; /*!< interrupt Mode Control Register A 25 */
+ __IO uint8_t IMC26; /*!< interrupt Mode Control Register A 26 */
+ __IO uint8_t IMC27; /*!< interrupt Mode Control Register A 27 */
+ __IO uint8_t IMC28; /*!< interrupt Mode Control Register A 28 */
+ __IO uint8_t IMC29; /*!< interrupt Mode Control Register A 29 */
+ __IO uint8_t IMC30; /*!< interrupt Mode Control Register A 30 */
+ __IO uint8_t IMC31; /*!< interrupt Mode Control Register A 31 */
+ uint8_t RESERVED1[17];
+ __IO uint8_t IMC49; /*!< interrupt Mode Control Register A 49 */
+ __IO uint8_t IMC50; /*!< interrupt Mode Control Register A 50 */
+ __IO uint8_t IMC51; /*!< interrupt Mode Control Register A 51 */
+ __IO uint8_t IMC52; /*!< interrupt Mode Control Register A 52 */
+ __IO uint8_t IMC53; /*!< interrupt Mode Control Register A 53 */
+ __IO uint8_t IMC54; /*!< interrupt Mode Control Register A 54 */
+ __IO uint8_t IMC55; /*!< interrupt Mode Control Register A 55 */
+ __IO uint8_t IMC56; /*!< interrupt Mode Control Register A 56 */
+ __IO uint8_t IMC57; /*!< interrupt Mode Control Register A 57 */
+} TSB_IA_TypeDef;
+
+/**
+ * @brief Reset Low power Management Register
+ */
+typedef struct
+{
+ __IO uint8_t LOSCCR; /*!< Low OSC and IHOSC2 clock supply Control Register*/
+ __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */
+ __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */
+ __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */
+ uint8_t RESERVED0[11];
+ __IO uint8_t PROTECT; /*!< Protect Register */
+} TSB_RLM_TypeDef;
+
+/**
+ * @brief LVD0
+ */
+typedef struct
+{
+ __IO uint8_t CR1; /*!< LVD Control register1 */
+ __IO uint8_t CR2; /*!< LVD Control register2 */
+ __IO uint8_t LVL1; /*!< LVD detection voltage select register 1 */
+ __IO uint8_t LVL2; /*!< LVD detection voltage select register 2 */
+ __I uint8_t SR; /*!< LVD status register */
+} TSB_LVD_TypeDef;
+
+/**
+ * @brief TRGSEL
+ */
+typedef struct
+{
+ __IO uint32_t CR0; /*!< TRGSEL Control register 0 */
+ __IO uint32_t CR1; /*!< TRGSEL Control register 1 */
+ __IO uint32_t CR2; /*!< TSEL Control register 2 */
+ __IO uint32_t CR3; /*!< TRGSEL Control register 3 */
+ __IO uint32_t CR4; /*!< TRGSEL Control register 4 */
+ __IO uint32_t CR5; /*!< TRGSEL Control register 5 */
+ __IO uint32_t CR6; /*!< TRGSEL Control register 6 */
+ __IO uint32_t CR7; /*!< TRGSEL Control register 7 */
+ __IO uint32_t CR8; /*!< TRGSEL Control register 8 */
+ __IO uint32_t CR9; /*!< TRGSEL Control register 9 */
+ __IO uint32_t CR10; /*!< TRGSEL Control register 10 */
+ __IO uint32_t CR11; /*!< TRGSEL Control register 11 */
+ __IO uint32_t CR12; /*!< TRGSEL Control register 12 */
+ __IO uint32_t CR13; /*!< TRGSEL Control register 13 */
+} TSB_TSEL_TypeDef;
+
+/**
+ * @brief Long Term Timer(LTTMR)
+ */
+typedef struct
+{
+ __IO uint8_t CR0; /*!< Long Term Control Register */
+ __IO uint8_t VALL; /*!< Long Term Setting Register */
+ __IO uint8_t VALH; /*!< Long Term Setting Register */
+} TSB_LTT_TypeDef;
+
+/**
+ * @brief Serial Interface (TSPI)
+ */
+typedef struct
+{
+ __IO uint32_t CR0; /*!< TSPI Control Register 0 */
+ __IO uint32_t CR1; /*!< TSPI Control Register 1 */
+ __IO uint32_t CR2; /*!< TSPI Control Register 2 */
+ __IO uint32_t CR3; /*!< TSPI Control Register 3 */
+ __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */
+ __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */
+ __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */
+ uint32_t RESERVED0[57];
+ __IO uint32_t DR; /*!< TSPI Data Register */
+ uint32_t RESERVED1[63];
+ __IO uint32_t SR; /*!< TSPI Status Register */
+ __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */
+} TSB_TSPI_TypeDef;
+
+/**
+ * @brief External Bus Interface(EXB)
+ */
+typedef struct
+{
+ __IO uint32_t MOD; /*!< External Bus Mode Control Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t AS0; /*!< External Bus Base Address and CS Space setting Register 0*/
+ __IO uint32_t AS1; /*!< External Bus Base Address and CS Space setting Register 1 */
+ __IO uint32_t AS2; /*!< External Bus Base Address and CS Space setting Register 2*/
+ __IO uint32_t AS3; /*!< External Bus Base Address and CS Space setting Register 3*/
+ uint32_t RESERVED1[8];
+ __IO uint32_t CS0; /*!< Chip Select and Wait Controller Register 0 */
+ __IO uint32_t CS1; /*!< Chip Select and Wait Controller Register 1 */
+ __IO uint32_t CS2; /*!< Chip Select and Wait Controller Register 2 */
+ __IO uint32_t CS3; /*!< Chip Select and Wait Controller Register 3 */
+ uint32_t RESERVED2[4];
+ __IO uint32_t CLKCTL; /*!< Clock output controlRegister */
+} TSB_EXB_TypeDef;
+
+/**
+ * @brief Clock Generator (CG)
+ */
+typedef struct
+{
+ __IO uint32_t PROTECT; /*!< Protect Register */
+ __IO uint32_t OSCCR; /*!< Oscillation Control Register */
+ __IO uint32_t SYSCR; /*!< System Clock Control Register */
+ __IO uint32_t STBYCR; /*!< Standby Control Register */
+ uint32_t RESERVED0[4];
+ __IO uint32_t PLL0SEL; /*!< PLL Selection Register 0 */
+ uint32_t RESERVED1[3];
+ __IO uint32_t WUPHCR; /*!< High OSC Warming-up Register */
+ __IO uint32_t WUPLCR; /*!< Low OSC Warming-up Register */
+ uint32_t RESERVED2[4];
+ __IO uint32_t FSYSMENA; /*!< Middle fsys Supply Stop Register A */
+ __IO uint32_t FSYSMENB; /*!< Middle fsys Supply Stop Register A */
+ __IO uint32_t FSYSENA; /*!< High fsys Supply Stop Register A */
+ uint32_t RESERVED3;
+ __IO uint32_t FCEN; /*!< FC Supply Stop Register */
+ __IO uint32_t SPCLKEN; /*!< ADC TRACE Clock Supply Stop Register */
+ uint32_t RESERVED4[2];
+ __IO uint32_t EXTEND2; /*!< Extend for MDMAC Register */
+} TSB_CG_TypeDef;
+
+/**
+ * @brief Interrupt Control B Register
+ */
+typedef struct
+{
+ uint8_t RESERVED0[16];
+ __IO uint8_t NIC00; /*!< Non maskable interrupt Control Register 00 */
+ uint8_t RESERVED1[79];
+ __IO uint8_t IMC000; /*!< interrupt Mode Control Register 000 */
+ __IO uint8_t IMC001; /*!< interrupt Mode Control Register 001 */
+ __IO uint8_t IMC002; /*!< interrupt Mode Control Register 002 */
+ __IO uint8_t IMC003; /*!< interrupt Mode Control Register 003 */
+ __IO uint8_t IMC004; /*!< interrupt Mode Control Register 004 */
+ __IO uint8_t IMC005; /*!< interrupt Mode Control Register 005 */
+ __IO uint8_t IMC006; /*!< interrupt Mode Control Register 006 */
+ __IO uint8_t IMC007; /*!< interrupt Mode Control Register 007 */
+ __IO uint8_t IMC008; /*!< interrupt Mode Control Register 008 */
+ __IO uint8_t IMC009; /*!< interrupt Mode Control Register 009 */
+ __IO uint8_t IMC010; /*!< interrupt Mode Control Register 010 */
+ __IO uint8_t IMC011; /*!< interrupt Mode Control Register 011 */
+ __IO uint8_t IMC012; /*!< interrupt Mode Control Register 012 */
+ __IO uint8_t IMC013; /*!< interrupt Mode Control Register 013 */
+ __IO uint8_t IMC014; /*!< interrupt Mode Control Register 014 */
+ __IO uint8_t IMC015; /*!< interrupt Mode Control Register 015 */
+ __IO uint8_t IMC016; /*!< interrupt Mode Control Register 016 */
+ __IO uint8_t IMC017; /*!< interrupt Mode Control Register 017 */
+ __IO uint8_t IMC018; /*!< interrupt Mode Control Register 018 */
+ __IO uint8_t IMC019; /*!< interrupt Mode Control Register 019 */
+ __IO uint8_t IMC020; /*!< interrupt Mode Control Register 020 */
+ __IO uint8_t IMC021; /*!< interrupt Mode Control Register 021 */
+ __IO uint8_t IMC022; /*!< interrupt Mode Control Register 022 */
+ __IO uint8_t IMC023; /*!< interrupt Mode Control Register 023 */
+ __IO uint8_t IMC024; /*!< interrupt Mode Control Register 024 */
+ __IO uint8_t IMC025; /*!< interrupt Mode Control Register 025 */
+ __IO uint8_t IMC026; /*!< interrupt Mode Control Register 026 */
+ __IO uint8_t IMC027; /*!< interrupt Mode Control Register 027 */
+ __IO uint8_t IMC028; /*!< interrupt Mode Control Register 028 */
+ __IO uint8_t IMC029; /*!< interrupt Mode Control Register 029 */
+ __IO uint8_t IMC030; /*!< interrupt Mode Control Register 030 */
+ __IO uint8_t IMC031; /*!< interrupt Mode Control Register 031 */
+ __IO uint8_t IMC032; /*!< interrupt Mode Control Register 032 */
+ __IO uint8_t IMC033; /*!< interrupt Mode Control Register 033 */
+ __IO uint8_t IMC034; /*!< interrupt Mode Control Register 034 */
+ __IO uint8_t IMC035; /*!< interrupt Mode Control Register 035 */
+ __IO uint8_t IMC036; /*!< interrupt Mode Control Register 036 */
+ __IO uint8_t IMC037; /*!< interrupt Mode Control Register 037 */
+ __IO uint8_t IMC038; /*!< interrupt Mode Control Register 038 */
+ __IO uint8_t IMC039; /*!< interrupt Mode Control Register 039 */
+ __IO uint8_t IMC040; /*!< interrupt Mode Control Register 040 */
+ __IO uint8_t IMC041; /*!< interrupt Mode Control Register 041 */
+ __IO uint8_t IMC042; /*!< interrupt Mode Control Register 042 */
+ __IO uint8_t IMC043; /*!< interrupt Mode Control Register 043 */
+ __IO uint8_t IMC044; /*!< interrupt Mode Control Register 044 */
+ __IO uint8_t IMC045; /*!< interrupt Mode Control Register 045 */
+ __IO uint8_t IMC046; /*!< interrupt Mode Control Register 046 */
+ __IO uint8_t IMC047; /*!< interrupt Mode Control Register 047 */
+ __IO uint8_t IMC048; /*!< interrupt Mode Control Register 048 */
+ __IO uint8_t IMC049; /*!< interrupt Mode Control Register 049 */
+ __IO uint8_t IMC050; /*!< interrupt Mode Control Register 050 */
+ __IO uint8_t IMC051; /*!< interrupt Mode Control Register 051 */
+ __IO uint8_t IMC052; /*!< interrupt Mode Control Register 052 */
+ __IO uint8_t IMC053; /*!< interrupt Mode Control Register 053 */
+ __IO uint8_t IMC054; /*!< interrupt Mode Control Register 054 */
+ __IO uint8_t IMC055; /*!< interrupt Mode Control Register 055 */
+ __IO uint8_t IMC056; /*!< interrupt Mode Control Register 056 */
+ __IO uint8_t IMC057; /*!< interrupt Mode Control Register 057 */
+ __IO uint8_t IMC058; /*!< interrupt Mode Control Register 058 */
+ __IO uint8_t IMC059; /*!< interrupt Mode Control Register 059 */
+ __IO uint8_t IMC060; /*!< interrupt Mode Control Register 060 */
+ __IO uint8_t IMC061; /*!< interrupt Mode Control Register 061 */
+ __IO uint8_t IMC062; /*!< interrupt Mode Control Register 062 */
+ __IO uint8_t IMC063; /*!< interrupt Mode Control Register 063 */
+ __IO uint8_t IMC064; /*!< interrupt Mode Control Register 064 */
+ __IO uint8_t IMC065; /*!< interrupt Mode Control Register 065 */
+ __IO uint8_t IMC066; /*!< interrupt Mode Control Register 066 */
+ __IO uint8_t IMC067; /*!< interrupt Mode Control Register 067 */
+ __IO uint8_t IMC068; /*!< interrupt Mode Control Register 068 */
+ __IO uint8_t IMC069; /*!< interrupt Mode Control Register 069 */
+ __IO uint8_t IMC070; /*!< interrupt Mode Control Register 070 */
+ __IO uint8_t IMC071; /*!< interrupt Mode Control Register 071 */
+ __IO uint8_t IMC072; /*!< interrupt Mode Control Register 072 */
+ __IO uint8_t IMC073; /*!< interrupt Mode Control Register 073 */
+ __IO uint8_t IMC074; /*!< interrupt Mode Control Register 074 */
+ __IO uint8_t IMC075; /*!< interrupt Mode Control Register 075 */
+ __IO uint8_t IMC076; /*!< interrupt Mode Control Register 076 */
+ __IO uint8_t IMC077; /*!< interrupt Mode Control Register 077 */
+ __IO uint8_t IMC078; /*!< interrupt Mode Control Register 078 */
+ __IO uint8_t IMC079; /*!< interrupt Mode Control Register 079 */
+ __IO uint8_t IMC080; /*!< interrupt Mode Control Register 080 */
+ __IO uint8_t IMC081; /*!< interrupt Mode Control Register 081 */
+ __IO uint8_t IMC082; /*!< interrupt Mode Control Register 082 */
+ __IO uint8_t IMC083; /*!< interrupt Mode Control Register 083 */
+ __IO uint8_t IMC084; /*!< interrupt Mode Control Register 084 */
+ __IO uint8_t IMC085; /*!< interrupt Mode Control Register 085 */
+ __IO uint8_t IMC086; /*!< interrupt Mode Control Register 086 */
+ __IO uint8_t IMC087; /*!< interrupt Mode Control Register 087 */
+ __IO uint8_t IMC088; /*!< interrupt Mode Control Register 088 */
+ __IO uint8_t IMC089; /*!< interrupt Mode Control Register 089 */
+ __IO uint8_t IMC090; /*!< interrupt Mode Control Register 090 */
+ __IO uint8_t IMC091; /*!< interrupt Mode Control Register 091 */
+ __IO uint8_t IMC092; /*!< interrupt Mode Control Register 092 */
+ __IO uint8_t IMC093; /*!< interrupt Mode Control Register 093 */
+ __IO uint8_t IMC094; /*!< interrupt Mode Control Register 094 */
+ __IO uint8_t IMC095; /*!< interrupt Mode Control Register 095 */
+ __IO uint8_t IMC096; /*!< interrupt Mode Control Register 096 */
+ __IO uint8_t IMC097; /*!< interrupt Mode Control Register 097 */
+ __IO uint8_t IMC098; /*!< interrupt Mode Control Register 098 */
+ __IO uint8_t IMC099; /*!< interrupt Mode Control Register 099 */
+ __IO uint8_t IMC100; /*!< interrupt Mode Control Register 100 */
+ __IO uint8_t IMC101; /*!< interrupt Mode Control Register 101 */
+ __IO uint8_t IMC102; /*!< interrupt Mode Control Register 102 */
+ __IO uint8_t IMC103; /*!< interrupt Mode Control Register 103 */
+ __IO uint8_t IMC104; /*!< interrupt Mode Control Register 104 */
+ __IO uint8_t IMC105; /*!< interrupt Mode Control Register 105 */
+ __IO uint8_t IMC106; /*!< interrupt Mode Control Register 106 */
+ __IO uint8_t IMC107; /*!< interrupt Mode Control Register 107 */
+ __IO uint8_t IMC108; /*!< interrupt Mode Control Register 108 */
+ __IO uint8_t IMC109; /*!< interrupt Mode Control Register 109 */
+ __IO uint8_t IMC110; /*!< interrupt Mode Control Register 110 */
+ __IO uint8_t IMC111; /*!< interrupt Mode Control Register 111 */
+ __IO uint8_t IMC112; /*!< interrupt Mode Control Register 112 */
+ __IO uint8_t IMC113; /*!< interrupt Mode Control Register 113 */
+ __IO uint8_t IMC114; /*!< interrupt Mode Control Register 114 */
+ __IO uint8_t IMC115; /*!< interrupt Mode Control Register 115 */
+ __IO uint8_t IMC116; /*!< interrupt Mode Control Register 116 */
+ __IO uint8_t IMC117; /*!< interrupt Mode Control Register 117 */
+ __IO uint8_t IMC118; /*!< interrupt Mode Control Register 118 */
+ __IO uint8_t IMC119; /*!< interrupt Mode Control Register 119 */
+ __IO uint8_t IMC120; /*!< interrupt Mode Control Register 120 */
+ __IO uint8_t IMC121; /*!< interrupt Mode Control Register 121 */
+ __IO uint8_t IMC122; /*!< interrupt Mode Control Register 122 */
+ __IO uint8_t IMC123; /*!< interrupt Mode Control Register 123 */
+ __IO uint8_t IMC124; /*!< interrupt Mode Control Register 124 */
+ __IO uint8_t IMC125; /*!< interrupt Mode Control Register 125 */
+ __IO uint8_t IMC126; /*!< interrupt Mode Control Register 126 */
+ __IO uint8_t IMC127; /*!< interrupt Mode Control Register 127 */
+ __IO uint8_t IMC128; /*!< interrupt Mode Control Register 128 */
+ __IO uint8_t IMC129; /*!< interrupt Mode Control Register 129 */
+ __IO uint8_t IMC130; /*!< interrupt Mode Control Register 130 */
+ __IO uint8_t IMC131; /*!< interrupt Mode Control Register 131 */
+ __IO uint8_t IMC132; /*!< interrupt Mode Control Register 132 */
+ __IO uint8_t IMC133; /*!< interrupt Mode Control Register 133 */
+ __IO uint8_t IMC134; /*!< interrupt Mode Control Register 134 */
+ __IO uint8_t IMC135; /*!< interrupt Mode Control Register 135 */
+ __IO uint8_t IMC136; /*!< interrupt Mode Control Register 136 */
+ __IO uint8_t IMC137; /*!< interrupt Mode Control Register 137 */
+ __IO uint8_t IMC138; /*!< interrupt Mode Control Register 138 */
+ __IO uint8_t IMC139; /*!< interrupt Mode Control Register 139 */
+ __IO uint8_t IMC140; /*!< interrupt Mode Control Register 140 */
+ __IO uint8_t IMC141; /*!< interrupt Mode Control Register 141 */
+} TSB_IB_TypeDef;
+
+/**
+ * @brief Interrupt Monitor Register
+ */
+typedef struct
+{
+ __I uint32_t FLGNMI; /*!< NMI Interrupt Monitor Flag 0 */
+ __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 (032 - 063) */
+ __I uint32_t FLG2; /*!< Interrupt Monitor Flag 2 (064 - 095) */
+ __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 (096 - 127) */
+ __I uint32_t FLG4; /*!< Interrupt Monitor Flag 4 (128 - 159) */
+ __I uint32_t FLG5; /*!< Interrupt Monitor Flag 5 (160 - 191) */
+ __I uint32_t FLG6; /*!< Interrupt Monitor Flag 6 (192 - 223) */
+ __I uint32_t FLG7; /*!< Interrupt Monitor Flag 7 (224 - 225) */
+} TSB_IMN_TypeDef;
+
+/**
+ * @brief DNF
+ */
+typedef struct
+{
+ __IO uint32_t CKCR; /*!< DNF clock Control register */
+ __IO uint32_t ENCR; /*!< DNF Enable register */
+} TSB_DNF_TypeDef;
+
+/**
+ * @brief Watchdog Timer (WD)
+ */
+typedef struct
+{
+ __IO uint32_t PRO; /*!< SIWD Protect Register */
+ __IO uint32_t EN; /*!< SIWD Enable Register */
+ __O uint32_t CR; /*!< SIWD Control Register */
+ __IO uint32_t MOD; /*!< SIWD Mode Register */
+ __I uint32_t MONI; /*!< SIWD Monitor Register */
+} TSB_SIWD_TypeDef;
+
+/**
+ * @brief NBD
+ */
+typedef struct
+{
+ __IO uint32_t CR0; /*!< NBD control register 0 */
+ __IO uint32_t CR1; /*!< NBD control register 1 */
+} TSB_NBD_TypeDef;
+
+/**
+ * @brief Malti Porpose Direct Memory Accsess(MDMA)
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t CEN; /*!< MDMAC Channel Enable Register */
+ __IO uint32_t REQ; /*!< MDMAC Transfer Request Register */
+ __IO uint32_t SUS; /*!< MDMAC Transfer Suspension Register */
+ __IO uint32_t ACT; /*!< MDMAC Transfer Active Register */
+ __IO uint32_t END; /*!< MDMAC Transfer End Register */
+ __IO uint32_t PRI; /*!< MDMAC Priority Setting Register */
+ __IO uint32_t ENE; /*!< MDMAC End Interrupt Enable Register */
+ __IO uint32_t DTAB; /*!< MDMAC Channel Information Address Register */
+ uint32_t RESERVED1;
+ __I uint32_t CHN; /*!< MDMAC Channel Number Register */
+ __I uint32_t XFTYP; /*!< MDMAC Channel Number Register */
+ __I uint32_t XFSAD; /*!< MDMAC Transfer Source Address Register */
+ __I uint32_t XFDAD; /*!< MDMAC Transfer Destination Address Register */
+ __I uint32_t XFSIZ; /*!< MDMAC Transfer Size Register */
+ __I uint32_t DSADS; /*!< MDMAC Descriptor Address Register */
+ __I uint32_t DSNUM; /*!< MDMAC Descriptor Number Register */
+ uint32_t RESERVED2[3];
+ __I uint32_t C00XFTYP; /*!< MDMAC Channel 00 Number Avoidance Register */
+ __I uint32_t C00XFSAD; /*!< MDMAC Channel 00 Transfer Source Address Avoidance Register*/
+ __I uint32_t C00XFDAD; /*!< MDMAC Channel 00 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C00XFSIZ; /*!< MDMAC Channel 00 Transfer Size Avoidance Register*/
+ __I uint32_t C00DSADS; /*!< MDMAC Channel 00 Descriptor Address Avoidance Register*/
+ __I uint32_t C00DSNUM; /*!< MDMAC Channel 00 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED3[2];
+ __I uint32_t C01XFTYP; /*!< MDMAC Channel 01 Number Avoidance Register */
+ __I uint32_t C01XFSAD; /*!< MDMAC Channel 01 Transfer Source Address Avoidance Register*/
+ __I uint32_t C01XFDAD; /*!< MDMAC Channel 01 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C01XFSIZ; /*!< MDMAC Channel 01 Transfer Size Avoidance Register*/
+ __I uint32_t C01DSADS; /*!< MDMAC Channel 01 Descriptor Address Avoidance Register*/
+ __I uint32_t C01DSNUM; /*!< MDMAC Channel 01 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED4[2];
+ __I uint32_t C02XFTYP; /*!< MDMAC Channel 02 Number Avoidance Register */
+ __I uint32_t C02XFSAD; /*!< MDMAC Channel 02 Transfer Source Address Avoidance Register*/
+ __I uint32_t C02XFDAD; /*!< MDMAC Channel 02 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C02XFSIZ; /*!< MDMAC Channel 02 Transfer Size Avoidance Register*/
+ __I uint32_t C02DSADS; /*!< MDMAC Channel 02 Descriptor Address Avoidance Register*/
+ __I uint32_t C02DSNUM; /*!< MDMAC Channel 02 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED5[2];
+ __I uint32_t C03XFTYP; /*!< MDMAC Channel 03 Number Avoidance Register */
+ __I uint32_t C03XFSAD; /*!< MDMAC Channel 03 Transfer Source Address Avoidance Register*/
+ __I uint32_t C03XFDAD; /*!< MDMAC Channel 03 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C03XFSIZ; /*!< MDMAC Channel 03 Transfer Size Avoidance Register*/
+ __I uint32_t C03DSADS; /*!< MDMAC Channel 03 Descriptor Address Avoidance Register*/
+ __I uint32_t C03DSNUM; /*!< MDMAC Channel 03 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED6[2];
+ __I uint32_t C04XFTYP; /*!< MDMAC Channel 04 Number Avoidance Register */
+ __I uint32_t C04XFSAD; /*!< MDMAC Channel 04 Transfer Source Address Avoidance Register*/
+ __I uint32_t C04XFDAD; /*!< MDMAC Channel 04 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C04XFSIZ; /*!< MDMAC Channel 04 Transfer Size Avoidance Register*/
+ __I uint32_t C04DSADS; /*!< MDMAC Channel 04 Descriptor Address Avoidance Register*/
+ __I uint32_t C04DSNUM; /*!< MDMAC Channel 04 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED7[2];
+ __I uint32_t C05XFTYP; /*!< MDMAC Channel 05 Number Avoidance Register */
+ __I uint32_t C05XFSAD; /*!< MDMAC Channel 05 Transfer Source Address Avoidance Register*/
+ __I uint32_t C05XFDAD; /*!< MDMAC Channel 05 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C05XFSIZ; /*!< MDMAC Channel 05 Transfer Size Avoidance Register*/
+ __I uint32_t C05DSADS; /*!< MDMAC Channel 05 Descriptor Address Avoidance Register*/
+ __I uint32_t C05DSNUM; /*!< MDMAC Channel 05 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED8[2];
+ __I uint32_t C06XFTYP; /*!< MDMAC Channel 06 Number Avoidance Register */
+ __I uint32_t C06XFSAD; /*!< MDMAC Channel 06 Transfer Source Address Avoidance Register*/
+ __I uint32_t C06XFDAD; /*!< MDMAC Channel 06 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C06XFSIZ; /*!< MDMAC Channel 06 Transfer Size Avoidance Register*/
+ __I uint32_t C06DSADS; /*!< MDMAC Channel 06 Descriptor Address Avoidance Register*/
+ __I uint32_t C06DSNUM; /*!< MDMAC Channel 06 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED9[2];
+ __I uint32_t C07XFTYP; /*!< MDMAC Channel 07 Number Avoidance Register */
+ __I uint32_t C07XFSAD; /*!< MDMAC Channel 07 Transfer Source Address Avoidance Register*/
+ __I uint32_t C07XFDAD; /*!< MDMAC Channel 07 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C07XFSIZ; /*!< MDMAC Channel 07 Transfer Size Avoidance Register*/
+ __I uint32_t C07DSADS; /*!< MDMAC Channel 07 Descriptor Address Avoidance Register*/
+ __I uint32_t C07DSNUM; /*!< MDMAC Channel 07 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED10[2];
+ __I uint32_t C08XFTYP; /*!< MDMAC Channel 08 Number Avoidance Register */
+ __I uint32_t C08XFSAD; /*!< MDMAC Channel 08 Transfer Source Address Avoidance Register*/
+ __I uint32_t C08XFDAD; /*!< MDMAC Channel 08 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C08XFSIZ; /*!< MDMAC Channel 08 Transfer Size Avoidance Register*/
+ __I uint32_t C08DSADS; /*!< MDMAC Channel 08 Descriptor Address Avoidance Register*/
+ __I uint32_t C08DSNUM; /*!< MDMAC Channel 08 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED11[2];
+ __I uint32_t C09XFTYP; /*!< MDMAC Channel 09 Number Avoidance Register */
+ __I uint32_t C09XFSAD; /*!< MDMAC Channel 09 Transfer Source Address Avoidance Register*/
+ __I uint32_t C09XFDAD; /*!< MDMAC Channel 09 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C09XFSIZ; /*!< MDMAC Channel 09 Transfer Size Avoidance Register*/
+ __I uint32_t C09DSADS; /*!< MDMAC Channel 09 Descriptor Address Avoidance Register*/
+ __I uint32_t C09DSNUM; /*!< MDMAC Channel 09 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED12[2];
+ __I uint32_t C10XFTYP; /*!< MDMAC Channel 10 Number Avoidance Register */
+ __I uint32_t C10XFSAD; /*!< MDMAC Channel 10 Transfer Source Address Avoidance Register*/
+ __I uint32_t C10XFDAD; /*!< MDMAC Channel 10 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C10XFSIZ; /*!< MDMAC Channel 10 Transfer Size Avoidance Register*/
+ __I uint32_t C10DSADS; /*!< MDMAC Channel 10 Descriptor Address Avoidance Register*/
+ __I uint32_t C10DSNUM; /*!< MDMAC Channel 10 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED13[2];
+ __I uint32_t C11XFTYP; /*!< MDMAC Channel 11 Number Avoidance Register */
+ __I uint32_t C11XFSAD; /*!< MDMAC Channel 11 Transfer Source Address Avoidance Register*/
+ __I uint32_t C11XFDAD; /*!< MDMAC Channel 11 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C11XFSIZ; /*!< MDMAC Channel 11 Transfer Size Avoidance Register*/
+ __I uint32_t C11DSADS; /*!< MDMAC Channel 11 Descriptor Address Avoidance Register*/
+ __I uint32_t C11DSNUM; /*!< MDMAC Channel 11 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED14[2];
+ __I uint32_t C12XFTYP; /*!< MDMAC Channel 12 Number Avoidance Register */
+ __I uint32_t C12XFSAD; /*!< MDMAC Channel 12 Transfer Source Address Avoidance Register*/
+ __I uint32_t C12XFDAD; /*!< MDMAC Channel 12 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C12XFSIZ; /*!< MDMAC Channel 12 Transfer Size Avoidance Register*/
+ __I uint32_t C12DSADS; /*!< MDMAC Channel 12 Descriptor Address Avoidance Register*/
+ __I uint32_t C12DSNUM; /*!< MDMAC Channel 12 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED15[2];
+ __I uint32_t C13XFTYP; /*!< MDMAC Channel 13 Number Avoidance Register */
+ __I uint32_t C13XFSAD; /*!< MDMAC Channel 13 Transfer Source Address Avoidance Register*/
+ __I uint32_t C13XFDAD; /*!< MDMAC Channel 13 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C13XFSIZ; /*!< MDMAC Channel 13 Transfer Size Avoidance Register*/
+ __I uint32_t C13DSADS; /*!< MDMAC Channel 13 Descriptor Address Avoidance Register*/
+ __I uint32_t C13DSNUM; /*!< MDMAC Channel 13 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED16[2];
+ __I uint32_t C14XFTYP; /*!< MDMAC Channel 14 Number Avoidance Register */
+ __I uint32_t C14XFSAD; /*!< MDMAC Channel 14 Transfer Source Address Avoidance Register*/
+ __I uint32_t C14XFDAD; /*!< MDMAC Channel 14 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C14XFSIZ; /*!< MDMAC Channel 14 Transfer Size Avoidance Register*/
+ __I uint32_t C14DSADS; /*!< MDMAC Channel 14 Descriptor Address Avoidance Register*/
+ __I uint32_t C14DSNUM; /*!< MDMAC Channel 14 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED17[2];
+ __I uint32_t C15XFTYP; /*!< MDMAC Channel 15 Number Avoidance Register */
+ __I uint32_t C15XFSAD; /*!< MDMAC Channel 15 Transfer Source Address Avoidance Register*/
+ __I uint32_t C15XFDAD; /*!< MDMAC Channel 15 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C15XFSIZ; /*!< MDMAC Channel 15 Transfer Size Avoidance Register*/
+ __I uint32_t C15DSADS; /*!< MDMAC Channel 15 Descriptor Address Avoidance Register*/
+ __I uint32_t C15DSNUM; /*!< MDMAC Channel 15 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED18[2];
+ __I uint32_t C16XFTYP; /*!< MDMAC Channel 16 Number Avoidance Register */
+ __I uint32_t C16XFSAD; /*!< MDMAC Channel 16 Transfer Source Address Avoidance Register*/
+ __I uint32_t C16XFDAD; /*!< MDMAC Channel 16 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C16XFSIZ; /*!< MDMAC Channel 16 Transfer Size Avoidance Register*/
+ __I uint32_t C16DSADS; /*!< MDMAC Channel 16 Descriptor Address Avoidance Register*/
+ __I uint32_t C16DSNUM; /*!< MDMAC Channel 16 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED19[2];
+ __I uint32_t C17XFTYP; /*!< MDMAC Channel 17 Number Avoidance Register */
+ __I uint32_t C17XFSAD; /*!< MDMAC Channel 17 Transfer Source Address Avoidance Register*/
+ __I uint32_t C17XFDAD; /*!< MDMAC Channel 17 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C17XFSIZ; /*!< MDMAC Channel 17 Transfer Size Avoidance Register*/
+ __I uint32_t C17DSADS; /*!< MDMAC Channel 17 Descriptor Address Avoidance Register*/
+ __I uint32_t C17DSNUM; /*!< MDMAC Channel 17 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED20[2];
+ __I uint32_t C18XFTYP; /*!< MDMAC Channel 18 Number Avoidance Register */
+ __I uint32_t C18XFSAD; /*!< MDMAC Channel 18 Transfer Source Address Avoidance Register*/
+ __I uint32_t C18XFDAD; /*!< MDMAC Channel 18 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C18XFSIZ; /*!< MDMAC Channel 18 Transfer Size Avoidance Register*/
+ __I uint32_t C18DSADS; /*!< MDMAC Channel 18 Descriptor Address Avoidance Register*/
+ __I uint32_t C18DSNUM; /*!< MDMAC Channel 18 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED21[2];
+ __I uint32_t C19XFTYP; /*!< MDMAC Channel 19 Number Avoidance Register */
+ __I uint32_t C19XFSAD; /*!< MDMAC Channel 19 Transfer Source Address Avoidance Register*/
+ __I uint32_t C19XFDAD; /*!< MDMAC Channel 19 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C19XFSIZ; /*!< MDMAC Channel 19 Transfer Size Avoidance Register*/
+ __I uint32_t C19DSADS; /*!< MDMAC Channel 19 Descriptor Address Avoidance Register*/
+ __I uint32_t C19DSNUM; /*!< MDMAC Channel 19 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED22[2];
+ __I uint32_t C20XFTYP; /*!< MDMAC Channel 20 Number Avoidance Register */
+ __I uint32_t C20XFSAD; /*!< MDMAC Channel 20 Transfer Source Address Avoidance Register*/
+ __I uint32_t C20XFDAD; /*!< MDMAC Channel 20 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C20XFSIZ; /*!< MDMAC Channel 20 Transfer Size Avoidance Register*/
+ __I uint32_t C20DSADS; /*!< MDMAC Channel 20 Descriptor Address Avoidance Register*/
+ __I uint32_t C20DSNUM; /*!< MDMAC Channel 20 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED23[2];
+ __I uint32_t C21XFTYP; /*!< MDMAC Channel 21 Number Avoidance Register */
+ __I uint32_t C21XFSAD; /*!< MDMAC Channel 21 Transfer Source Address Avoidance Register*/
+ __I uint32_t C21XFDAD; /*!< MDMAC Channel 21 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C21XFSIZ; /*!< MDMAC Channel 21 Transfer Size Avoidance Register*/
+ __I uint32_t C21DSADS; /*!< MDMAC Channel 21 Descriptor Address Avoidance Register*/
+ __I uint32_t C21DSNUM; /*!< MDMAC Channel 21 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED24[2];
+ __I uint32_t C22XFTYP; /*!< MDMAC Channel 22 Number Avoidance Register */
+ __I uint32_t C22XFSAD; /*!< MDMAC Channel 22 Transfer Source Address Avoidance Register*/
+ __I uint32_t C22XFDAD; /*!< MDMAC Channel 22 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C22XFSIZ; /*!< MDMAC Channel 22 Transfer Size Avoidance Register*/
+ __I uint32_t C22DSADS; /*!< MDMAC Channel 22 Descriptor Address Avoidance Register*/
+ __I uint32_t C22DSNUM; /*!< MDMAC Channel 22 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED25[2];
+ __I uint32_t C23XFTYP; /*!< MDMAC Channel 23 Number Avoidance Register */
+ __I uint32_t C23XFSAD; /*!< MDMAC Channel 23 Transfer Source Address Avoidance Register*/
+ __I uint32_t C23XFDAD; /*!< MDMAC Channel 23 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C23XFSIZ; /*!< MDMAC Channel 23 Transfer Size Avoidance Register*/
+ __I uint32_t C23DSADS; /*!< MDMAC Channel 23 Descriptor Address Avoidance Register*/
+ __I uint32_t C23DSNUM; /*!< MDMAC Channel 23 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED26[2];
+ __I uint32_t C24XFTYP; /*!< MDMAC Channel 24 Number Avoidance Register */
+ __I uint32_t C24XFSAD; /*!< MDMAC Channel 24 Transfer Source Address Avoidance Register*/
+ __I uint32_t C24XFDAD; /*!< MDMAC Channel 24 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C24XFSIZ; /*!< MDMAC Channel 24 Transfer Size Avoidance Register*/
+ __I uint32_t C24DSADS; /*!< MDMAC Channel 24 Descriptor Address Avoidance Register*/
+ __I uint32_t C24DSNUM; /*!< MDMAC Channel 24 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED27[2];
+ __I uint32_t C25XFTYP; /*!< MDMAC Channel 25 Number Avoidance Register */
+ __I uint32_t C25XFSAD; /*!< MDMAC Channel 25 Transfer Source Address Avoidance Register*/
+ __I uint32_t C25XFDAD; /*!< MDMAC Channel 25 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C25XFSIZ; /*!< MDMAC Channel 25 Transfer Size Avoidance Register*/
+ __I uint32_t C25DSADS; /*!< MDMAC Channel 25 Descriptor Address Avoidance Register*/
+ __I uint32_t C25DSNUM; /*!< MDMAC Channel 25 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED28[2];
+ __I uint32_t C26XFTYP; /*!< MDMAC Channel 26 Number Avoidance Register */
+ __I uint32_t C26XFSAD; /*!< MDMAC Channel 26 Transfer Source Address Avoidance Register*/
+ __I uint32_t C26XFDAD; /*!< MDMAC Channel 26 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C26XFSIZ; /*!< MDMAC Channel 26 Transfer Size Avoidance Register*/
+ __I uint32_t C26DSADS; /*!< MDMAC Channel 26 Descriptor Address Avoidance Register*/
+ __I uint32_t C26DSNUM; /*!< MDMAC Channel 26 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED29[2];
+ __I uint32_t C27XFTYP; /*!< MDMAC Channel 27 Number Avoidance Register */
+ __I uint32_t C27XFSAD; /*!< MDMAC Channel 27 Transfer Source Address Avoidance Register*/
+ __I uint32_t C27XFDAD; /*!< MDMAC Channel 27 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C27XFSIZ; /*!< MDMAC Channel 27 Transfer Size Avoidance Register*/
+ __I uint32_t C27DSADS; /*!< MDMAC Channel 27 Descriptor Address Avoidance Register*/
+ __I uint32_t C27DSNUM; /*!< MDMAC Channel 27 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED30[2];
+ __I uint32_t C28XFTYP; /*!< MDMAC Channel 28 Number Avoidance Register */
+ __I uint32_t C28XFSAD; /*!< MDMAC Channel 28 Transfer Source Address Avoidance Register*/
+ __I uint32_t C28XFDAD; /*!< MDMAC Channel 28 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C28XFSIZ; /*!< MDMAC Channel 28 Transfer Size Avoidance Register*/
+ __I uint32_t C28DSADS; /*!< MDMAC Channel 28 Descriptor Address Avoidance Register*/
+ __I uint32_t C28DSNUM; /*!< MDMAC Channel 28 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED31[2];
+ __I uint32_t C29XFTYP; /*!< MDMAC Channel 29 Number Avoidance Register */
+ __I uint32_t C29XFSAD; /*!< MDMAC Channel 29 Transfer Source Address Avoidance Register*/
+ __I uint32_t C29XFDAD; /*!< MDMAC Channel 29 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C29XFSIZ; /*!< MDMAC Channel 29 Transfer Size Avoidance Register*/
+ __I uint32_t C29DSADS; /*!< MDMAC Channel 29 Descriptor Address Avoidance Register*/
+ __I uint32_t C29DSNUM; /*!< MDMAC Channel 29 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED32[2];
+ __I uint32_t C30XFTYP; /*!< MDMAC Channel 30 Number Avoidance Register */
+ __I uint32_t C30XFSAD; /*!< MDMAC Channel 30 Transfer Source Address Avoidance Register*/
+ __I uint32_t C30XFDAD; /*!< MDMAC Channel 30 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C30XFSIZ; /*!< MDMAC Channel 30 Transfer Size Avoidance Register*/
+ __I uint32_t C30DSADS; /*!< MDMAC Channel 30 Descriptor Address Avoidance Register*/
+ __I uint32_t C30DSNUM; /*!< MDMAC Channel 30 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED33[2];
+ __I uint32_t C31XFTYP; /*!< MDMAC Channel 31 Number Avoidance Register */
+ __I uint32_t C31XFSAD; /*!< MDMAC Channel 31 Transfer Source Address Avoidance Register*/
+ __I uint32_t C31XFDAD; /*!< MDMAC Channel 31 Transfer Destination Address Avoidance Register*/
+ __I uint32_t C31XFSIZ; /*!< MDMAC Channel 31 Transfer Size Avoidance Register*/
+ __I uint32_t C31DSADS; /*!< MDMAC Channel 31 Descriptor Address Avoidance Register*/
+ __I uint32_t C31DSNUM; /*!< MDMAC Channel 31 Descriptor Number Avoidance Register*/
+ uint32_t RESERVED34[238];
+ __IO uint32_t MSK; /*!< MDMAC Mask Register */
+} TSB_MDMA_TypeDef;
+
+#if defined ( __CC_ARM ) /* RealView Compiler */
+#pragma anon_unions
+#elif (defined (__ICCARM__)) /* ICC Compiler */
+#pragma language=extended
+#endif
+
+/**
+ * @brief ARM Prime Cell PL011
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< Data Register */
+union {
+ __I uint32_t RSR; /*!< Receive Status Register */
+ __O uint32_t ECR; /*!< Error Clear Register */
+ };
+ uint32_t RESERVED0[4];
+ __I uint32_t FR; /*!< Flag Register */
+ uint32_t RESERVED1;
+ __IO uint32_t ILPR; /*!< IrDA Low-power Counter register */
+ __IO uint32_t BRD; /*!< Integer Baud Rate Register */
+ __IO uint32_t FBRD; /*!< Fractional Baud Rate Register */
+ __IO uint32_t LCR_H; /*!< Line Control Register */
+ __IO uint32_t CR; /*!< Cntrol Register */
+ __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select Register */
+ __IO uint32_t IMSC; /*!< Interrupt Mask set/Clear Register */
+ __I uint32_t RIS; /*!< Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< Interrupt Clear Register */
+ __IO uint32_t DMACR; /*!< DMA Control Register */
+} TSB_FURT_TypeDef;
+
+/**
+ * @brief ADC
+ */
+typedef struct
+{
+ __IO uint32_t CR0; /*!< AD Control Register 0 */
+ __IO uint32_t CR1; /*!< AD Control Register 1 */
+ __I uint32_t ST; /*!< AD Status Register */
+ __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */
+ __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */
+ __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */
+ __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */
+ uint32_t RESERVED0;
+ __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */
+ __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */
+ __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */
+ __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */
+ __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */
+ __IO uint32_t CMPCR2; /*!< AD Conversion Monitor Function setting Register 2*/
+ __IO uint32_t CMPCR3; /*!< AD Conversion Monitor Function setting Register 3*/
+ __IO uint32_t CMP2; /*!< AD Conversion Result Comparison Register 2 */
+ __IO uint32_t CMP3; /*!< AD Conversion Result Comparison Register 3 */
+ uint32_t RESERVED1[30];
+ __IO uint32_t EXAZSEL; /*!< AIN sampling period selection register */
+ __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/
+ __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/
+ __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/
+ __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/
+ __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/
+ __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/
+ __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/
+ __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/
+ __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/
+ __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/
+ __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/
+ __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/
+ __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/
+ __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/
+ __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/
+ __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/
+ __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/
+ __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/
+ __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/
+ __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/
+ __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/
+ __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/
+ __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/
+ __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/
+ uint32_t RESERVED2[8];
+ __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */
+ __I uint32_t REG1; /*!< AD Conversion Result Register 1 */
+ __I uint32_t REG2; /*!< AD Conversion Result Register 2 */
+ __I uint32_t REG3; /*!< AD Conversion Result Register 3 */
+ __I uint32_t REG4; /*!< AD Conversion Result Register 4 */
+ __I uint32_t REG5; /*!< AD Conversion Result Register 5 */
+ __I uint32_t REG6; /*!< AD Conversion Result Register 6 */
+ __I uint32_t REG7; /*!< AD Conversion Result Register 7 */
+ __I uint32_t REG8; /*!< AD Conversion Result Register 8 */
+ __I uint32_t REG9; /*!< AD Conversion Result Register 9 */
+ __I uint32_t REG10; /*!< AD Conversion Result Register 10 */
+ __I uint32_t REG11; /*!< AD Conversion Result Register 11 */
+ __I uint32_t REG12; /*!< AD Conversion Result Register 12 */
+ __I uint32_t REG13; /*!< AD Conversion Result Register 13 */
+ __I uint32_t REG14; /*!< AD Conversion Result Register 14 */
+ __I uint32_t REG15; /*!< AD Conversion Result Register 15 */
+ __I uint32_t REG16; /*!< AD Conversion Result Register 16 */
+ __I uint32_t REG17; /*!< AD Conversion Result Register 17 */
+ __I uint32_t REG18; /*!< AD Conversion Result Register 18 */
+ __I uint32_t REG19; /*!< AD Conversion Result Register 19 */
+ __I uint32_t REG20; /*!< AD Conversion Result Register 20 */
+ __I uint32_t REG21; /*!< AD Conversion Result Register 21 */
+ __I uint32_t REG22; /*!< AD Conversion Result Register 22 */
+ __I uint32_t REG23; /*!< AD Conversion Result Register 23 */
+} TSB_AD_TypeDef;
+
+/**
+ * @brief Digital analog converter (DAC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC Control Register */
+ __IO uint32_t REG; /*!< DAC output Register */
+} TSB_DA_TypeDef;
+
+/**
+ * @brief 16-bit Timer/Event Counter (TB)
+ */
+typedef struct
+{
+ __IO uint32_t MOD; /*!< T32A Mode Register */
+ uint32_t RESERVED0[15];
+ __IO uint32_t RUNA; /*!< T32A Run Register A */
+ __IO uint32_t CRA; /*!< T32A Counter Control Register A */
+ __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */
+ __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */
+ __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */
+ __IO uint32_t STA; /*!< T32A Status Register A */
+ __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */
+ __I uint32_t TMRA; /*!< T32A Counter Capture Register A */
+ __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */
+ __IO uint32_t RGA0; /*!< T32A Timer Register A0 */
+ __IO uint32_t RGA1; /*!< T32A Timer Register A1 */
+ __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */
+ __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */
+ __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */
+ uint32_t RESERVED1[2];
+ __IO uint32_t RUNB; /*!< T32A Run Register B */
+ __IO uint32_t CRB; /*!< T32A Counter Control Register B */
+ __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */
+ __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */
+ __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */
+ __IO uint32_t STB; /*!< T32A Status Register B */
+ __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */
+ __I uint32_t TMRB; /*!< T32A Counter Capture Register B */
+ __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */
+ __IO uint32_t RGB0; /*!< T32A Timer Register B0 */
+ __IO uint32_t RGB1; /*!< T32A Timer Register B1 */
+ __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */
+ __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */
+ __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */
+ uint32_t RESERVED2[2];
+ __IO uint32_t RUNC; /*!< T32A Run Register C */
+ __IO uint32_t CRC; /*!< T32A Counter Control Register C */
+ __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */
+ __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */
+ __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */
+ __IO uint32_t STC; /*!< T32A Status Register C */
+ __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */
+ __I uint32_t TMRC; /*!< T32A Counter Capture Register C */
+ __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */
+ __IO uint32_t RGC0; /*!< T32A Timer Register C0 */
+ __IO uint32_t RGC1; /*!< T32A Timer Register C1 */
+ __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */
+ __I uint32_t CAPC1; /*!< T32A Capture Register C1 */
+ __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */
+ __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */
+} TSB_T32A_TypeDef;
+
+/**
+ * @brief UART
+ */
+typedef struct
+{
+ __IO uint32_t SWRST; /*!< UART Software Reset Register */
+ __IO uint32_t CR0; /*!< UART Control Register 0 */
+ __IO uint32_t CR1; /*!< UART Control Register 1 */
+ __IO uint32_t CLK; /*!< UART Clock Control Register */
+ __IO uint32_t BRD; /*!< UART Baud Rate Register */
+ __IO uint32_t TRANS; /*!< UART Transfer Enable Register */
+ __IO uint32_t DR; /*!< UART Data Register */
+ __IO uint32_t SR; /*!< UART Status Register */
+ __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */
+ __IO uint32_t ERR; /*!< UART Error Register */
+} TSB_UART_TypeDef;
+
+/**
+ * @brief I2C
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control Register 1 */
+ __IO uint32_t DBR; /*!< I2C Data Buffer Register */
+ __IO uint32_t AR; /*!< I2C Bus address Register */
+union {
+ __O uint32_t CR2; /*!< I2C Control Register 2 */
+ __I uint32_t SR; /*!< I2C Status Register */
+ };
+ __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */
+ __IO uint32_t IE; /*!< I2C Interrupt Enable Register */
+ __IO uint32_t ST; /*!< Interrupt Register */
+ __IO uint32_t OP; /*!< Optiononal Function register */
+ __I uint32_t PM; /*!< Bus Monitor register */
+ __IO uint32_t AR2; /*!< Second Slave address register */
+} TSB_I2C_TypeDef;
+
+/**
+ * @brief Port A
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port A Data Register */
+ __IO uint32_t CR; /*!< Port A Output Control Register */
+ __IO uint32_t FR1; /*!< Port A Function Register 1 */
+ __IO uint32_t FR2; /*!< Port A Function Register 2 */
+ __IO uint32_t FR3; /*!< Port A Function Register 3 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR5; /*!< Port A Function Register 5 */
+ __IO uint32_t FR6; /*!< Port A Function Register 6 */
+ __IO uint32_t FR7; /*!< Port A Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port A Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port A Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port A Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port A Input Control Register */
+} TSB_PA_TypeDef;
+
+/**
+ * @brief Port B
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port B Data Register */
+ __IO uint32_t CR; /*!< Port B Output Control Register */
+ __IO uint32_t FR1; /*!< Port B Function Register 1 */
+ __IO uint32_t FR2; /*!< Port B Function Register 2 */
+ __IO uint32_t FR3; /*!< Port B Function Register 3 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR5; /*!< Port B Function Register 5 */
+ __IO uint32_t FR6; /*!< Port B Function Register 6 */
+ uint32_t RESERVED1[2];
+ __IO uint32_t OD; /*!< Port B Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port B Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port B Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port B Input Control Register */
+} TSB_PB_TypeDef;
+
+/**
+ * @brief Port C
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port C Data Register */
+ __IO uint32_t CR; /*!< Port C Output Control Register */
+ __IO uint32_t FR1; /*!< Port C Function Register 1 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR3; /*!< Port C Function Register 3 */
+ uint32_t RESERVED1;
+ __IO uint32_t FR5; /*!< Port C Function Register 5 */
+ uint32_t RESERVED2[3];
+ __IO uint32_t OD; /*!< Port C Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port C Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port C Pull-down Control Register */
+ uint32_t RESERVED3;
+ __IO uint32_t IE; /*!< Port C Input Control Register */
+} TSB_PC_TypeDef;
+
+/**
+ * @brief Port D
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port D Data Register */
+ __IO uint32_t CR; /*!< Port D Output Control Register */
+ __IO uint32_t FR1; /*!< Port D Function Register 1 */
+ __IO uint32_t FR2; /*!< Port D Function Register 2 */
+ __IO uint32_t FR3; /*!< Port D Function Register 3 */
+ __IO uint32_t FR4; /*!< Port D Function Register 4 */
+ __IO uint32_t FR5; /*!< Port D Function Register 5 */
+ __IO uint32_t FR6; /*!< Port D Function Register 6 */
+ __IO uint32_t FR7; /*!< Port D Function Register 7 */
+ uint32_t RESERVED0;
+ __IO uint32_t OD; /*!< Port D Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port D Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port D Pull-down Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t IE; /*!< Port D Input Control Register */
+} TSB_PD_TypeDef;
+
+/**
+ * @brief Port E
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port E Data Register */
+ __IO uint32_t CR; /*!< Port E Output Control Register */
+ __IO uint32_t FR1; /*!< Port E Function Register 1 */
+ __IO uint32_t FR2; /*!< Port E Function Register 2 */
+ __IO uint32_t FR3; /*!< Port E Function Register 3 */
+ __IO uint32_t FR4; /*!< Port E Function Register 4 */
+ __IO uint32_t FR5; /*!< Port E Function Register 5 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR7; /*!< Port E Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port E Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port E Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port E Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port E Input Control Register */
+} TSB_PE_TypeDef;
+
+/**
+ * @brief Port F
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port F Data Register */
+ __IO uint32_t CR; /*!< Port F Output Control Register */
+ __IO uint32_t FR1; /*!< Port F Function Register 1 */
+ uint32_t RESERVED0[5];
+ __IO uint32_t FR7; /*!< Port F Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port F Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port F Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port F Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port F Input Control Register */
+} TSB_PF_TypeDef;
+
+/**
+ * @brief Port G
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port G Data Register */
+ __IO uint32_t CR; /*!< Port G Output Control Register */
+ __IO uint32_t FR1; /*!< Port G Function Register 1 */
+ __IO uint32_t FR2; /*!< Port G Function Register 2 */
+ __IO uint32_t FR3; /*!< Port G Function Register 3 */
+ __IO uint32_t FR4; /*!< Port G Function Register 4 */
+ __IO uint32_t FR5; /*!< Port G Function Register 5 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR7; /*!< Port G Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port G Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port G Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port G Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port G Input Control Register */
+} TSB_PG_TypeDef;
+
+/**
+ * @brief Port H
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port H Data Register */
+ __IO uint32_t CR; /*!< Port H Output Control Register */
+ __IO uint32_t FR1; /*!< Port H Function Register 1 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR3; /*!< Port H Function Register 3 */
+ __IO uint32_t FR4; /*!< Port H Function Register 4 */
+ __IO uint32_t FR5; /*!< Port H Function Register 5 */
+ uint32_t RESERVED1[3];
+ __IO uint32_t OD; /*!< Port H Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port H Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port H Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port H Input Control Register */
+} TSB_PH_TypeDef;
+
+/**
+ * @brief Port J
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port J Data Register */
+ __IO uint32_t CR; /*!< Port J Output Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port J Function Register 2 */
+ __IO uint32_t FR3; /*!< Port J Function Register 3 */
+ uint32_t RESERVED1;
+ __IO uint32_t FR5; /*!< Port J Function Register 5 */
+ uint32_t RESERVED2;
+ __IO uint32_t FR7; /*!< Port J Function Register 7 */
+ uint32_t RESERVED3;
+ __IO uint32_t OD; /*!< Port J Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port J Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port J Pull-down Control Register */
+ uint32_t RESERVED4;
+ __IO uint32_t IE; /*!< Port J Input Control Register */
+} TSB_PJ_TypeDef;
+
+/**
+ * @brief Port K
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port K Data Register */
+ __IO uint32_t CR; /*!< Port K Output Control Register */
+ __IO uint32_t FR1; /*!< Port K Function Register 1 */
+ __IO uint32_t FR2; /*!< Port K Function Register 2 */
+ __IO uint32_t FR3; /*!< Port K Function Register 3 */
+ __IO uint32_t FR4; /*!< Port K Function Register 4 */
+ uint32_t RESERVED0;
+ __IO uint32_t FR6; /*!< Port K Function Register 6 */
+ __IO uint32_t FR7; /*!< Port K Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port K Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port K Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port K Pull-up Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port K Input Control Register */
+} TSB_PK_TypeDef;
+
+/**
+ * @brief Port L
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port L Data Register */
+ __IO uint32_t CR; /*!< Port L Output Control Register */
+ __IO uint32_t FR1; /*!< Port L Function Register 1 */
+ __IO uint32_t FR2; /*!< Port L Function Register 2 */
+ __IO uint32_t FR3; /*!< Port L Function Register 3 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t FR6; /*!< Port L Function Register 6 */
+ __IO uint32_t FR7; /*!< Port L Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port L Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port L Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port L Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port L Input Control Register */
+} TSB_PL_TypeDef;
+
+/**
+ * @brief Port M
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port M Data Register */
+ __IO uint32_t CR; /*!< Port M Output Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port M Function Register 2 */
+ __IO uint32_t FR3; /*!< Port M Function Register 3 */
+ __IO uint32_t FR4; /*!< Port M Function Register 4 */
+ __IO uint32_t FR5; /*!< Port M Function Register 5 */
+ __IO uint32_t FR6; /*!< Port M Function Register 6 */
+ __IO uint32_t FR7; /*!< Port M Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port M Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port M Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port M Pull-up Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port M Input Control Register */
+} TSB_PM_TypeDef;
+
+/**
+ * @brief Port N
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port N Data Register */
+ __IO uint32_t CR; /*!< Port N Output Control Register */
+ uint32_t RESERVED0[8];
+ __IO uint32_t OD; /*!< Port N Opend Drain Control Register */
+ __IO uint32_t PUP; /*!< Port N Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port N Pull-down Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t IE; /*!< Port N Input Control Register */
+} TSB_PN_TypeDef;
+
+/**
+ * @brief Port P
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port P Data Register */
+ __IO uint32_t CR; /*!< Port P Output Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port P Function Register 2 */
+ __IO uint32_t FR3; /*!< Port P Function Register 3 */
+ uint32_t RESERVED1;
+ __IO uint32_t FR5; /*!< Port P Function Register 5 */
+ uint32_t RESERVED2[3];
+ __IO uint32_t OD; /*!< Port P Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port P Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port P Pull-down Control Register */
+ uint32_t RESERVED3;
+ __IO uint32_t IE; /*!< Port P Input Control Register */
+} TSB_PP_TypeDef;
+
+/**
+ * @brief Port R
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port R Data Register */
+ __IO uint32_t CR; /*!< Port R Output Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port R Function Register 2 */
+ __IO uint32_t FR3; /*!< Port R Function Register 3 */
+ uint32_t RESERVED1[5];
+ __IO uint32_t OD; /*!< Port R Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port R Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port R Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port R Input Control Register */
+} TSB_PR_TypeDef;
+
+/**
+ * @brief Port T
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port T Data Register */
+ __IO uint32_t CR; /*!< Port T Output Control Register */
+ __IO uint32_t FR1; /*!< Port T Function Register 1 */
+ __IO uint32_t FR2; /*!< Port T Function Register 2 */
+ __IO uint32_t FR3; /*!< Port T Function Register 3 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t FR6; /*!< Port T Function Register 6 */
+ __IO uint32_t FR7; /*!< Port T Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port T Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port T Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port T Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port T Input Control Register */
+} TSB_PT_TypeDef;
+
+/**
+ * @brief Port U
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port U Data Register */
+ __IO uint32_t CR; /*!< Port U Output Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port U Function Register 2 */
+ __IO uint32_t FR3; /*!< Port U Function Register 3 */
+ uint32_t RESERVED1[3];
+ __IO uint32_t FR7; /*!< Port U Function Register 7 */
+ uint32_t RESERVED2;
+ __IO uint32_t OD; /*!< Port U Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port U Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port U Pull-down Control Register */
+ uint32_t RESERVED3;
+ __IO uint32_t IE; /*!< Port U Input Control Register */
+} TSB_PU_TypeDef;
+
+/**
+ * @brief Port V
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port V Data Register */
+ __IO uint32_t CR; /*!< Port V OutPut Control Register */
+ uint32_t RESERVED0;
+ __IO uint32_t FR2; /*!< Port V Function Register 2 */
+ __IO uint32_t FR3; /*!< Port V Function Register 3 */
+ __IO uint32_t FR4; /*!< Port V Function Register 4 */
+ __IO uint32_t FR5; /*!< Port V Function Register 5 */
+ __IO uint32_t FR6; /*!< Port V Function Register 6 */
+ __IO uint32_t FR7; /*!< Port V Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port V Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port V Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port V Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port V InPut Control Register */
+} TSB_PV_TypeDef;
+
+/**
+ * @brief Port W
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port W Data Register */
+ __IO uint32_t CR; /*!< Port W OutPut Control Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t FR3; /*!< Port W Function Register 3 */
+ __IO uint32_t FR4; /*!< Port W Function Register 4 */
+ __IO uint32_t FR5; /*!< Port W Function Register 5 */
+ __IO uint32_t FR6; /*!< Port W Function Register 6 */
+ __IO uint32_t FR7; /*!< Port W Function Register 7 */
+ uint32_t RESERVED1;
+ __IO uint32_t OD; /*!< Port W Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port W Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port W Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port W InPut Control Register */
+} TSB_PW_TypeDef;
+
+/**
+ * @brief Port Y
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Port Y Data Register */
+ __IO uint32_t CR; /*!< Port Y OutPut Control Register */
+ __IO uint32_t FR1; /*!< Port Y Function Register 1 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t FR4; /*!< Port Y Function Register 4 */
+ uint32_t RESERVED1[4];
+ __IO uint32_t OD; /*!< Port Y Open Drain Control Register */
+ __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */
+ __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */
+ uint32_t RESERVED2;
+ __IO uint32_t IE; /*!< Port Y InPut Control Register */
+} TSB_PY_TypeDef;
+
+/**
+ * @brief Internal High-speed Oscillation Adjustment
+ */
+typedef struct
+{
+ __IO uint32_t OSCPRO; /*!< TRM Protection Register */
+ __IO uint32_t OSCEN; /*!< TRM Enable Register */
+ __I uint32_t OSCINIT; /*!< TRM Initial Trimming Level Monitor Register */
+ __IO uint32_t OSCSET; /*!< TRM Trimming Level Setting Register */
+} TSB_TRM_TypeDef;
+
+/**
+ * @brief Oscillation Frequency Detector (OFD)
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< OFD Control Register 1 */
+ __IO uint32_t CR2; /*!< OFD Control Register 2 */
+ __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/
+ __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/
+ __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/
+ __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/
+ __IO uint32_t RST; /*!< OFD Reset Enable Control Register */
+ __I uint32_t STAT; /*!< OFD Status Register */
+ __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */
+} TSB_OFD_TypeDef;
+
+/**
+ * @brief Real Time Clock (RTC)
+ */
+typedef struct
+{
+ __IO uint8_t SECR; /*!< RTC Sec setting register */
+ __IO uint8_t MINR; /*!< RTC Min settging register */
+ __IO uint8_t HOURR; /*!< RTC Hour setting register */
+ uint8_t RESERVED0;
+ __IO uint8_t DAYR; /*!< RTC Day setting register */
+ __IO uint8_t DATER; /*!< RTC Date setting register */
+ __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */
+ __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */
+ __IO uint8_t PAGER; /*!< RTC Page register */
+ uint8_t RESERVED1[3];
+ __IO uint8_t RESTR; /*!< RTC Reset register */
+ uint8_t RESERVED2;
+ __IO uint8_t PROTECT; /*!< RTC protect register */
+ __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */
+ __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */
+ __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */
+} TSB_RTC_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t EN; /*!< CEC Enable Register */
+ __IO uint32_t ADD; /*!< CEC Logical Address Register */
+ __O uint32_t RESET; /*!< CEC Software Reset Register */
+ __IO uint32_t REN; /*!< CEC Receive Enable Register */
+ __I uint32_t RBUF; /*!< CEC Receive Buffer Register */
+ __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */
+ __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */
+ __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */
+ __IO uint32_t TEN; /*!< CEC Transmit Enable Register */
+ __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */
+ __IO uint32_t TCR; /*!< CEC Transmit Control Register */
+ __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */
+ __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */
+ __IO uint32_t FSSEL; /*!< CEC sampling clock selection Register */
+} TSB_CEC_TypeDef;
+
+/**
+ * @brief Remote Control Signal Preprocessor (RMC)
+ */
+typedef struct
+{
+ __IO uint32_t EN; /*!< RMC Enable Register */
+ __IO uint32_t REN; /*!< RMC Receive Enable Register */
+ __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */
+ __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */
+ __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */
+ __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */
+ __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */
+ __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */
+ __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */
+ __I uint32_t RSTAT; /*!< RMC Receive Status Register */
+ __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */
+ __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */
+ __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */
+ __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */
+} TSB_RMC_TypeDef;
+
+/**
+ * @brief
+ */
+typedef struct
+{
+ __IO uint32_t MDEN; /*!< PMD Enable Register */
+ __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */
+ __IO uint32_t MDCR; /*!< PMD Control Register */
+ __I uint32_t CARSTA; /*!< PWM Carrier Status Register */
+ __I uint32_t BCARI; /*!< PWM Basic Carrier Register */
+ __IO uint32_t RATE; /*!< PWM Frequency Register */
+ __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */
+ __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */
+ __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */
+ __IO uint32_t MODESEL; /*!< PMD Mode Select Register */
+ __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */
+ __IO uint32_t MDPOT; /*!< PMD Output Setting Register */
+ __O uint32_t EMGREL; /*!< PMD EMG Release Register */
+ __IO uint32_t EMGCR; /*!< PMD EMG Control Register */
+ __I uint32_t EMGSTA; /*!< PMD EMG Status Register */
+ __IO uint32_t OVVCR; /*!< PMD OVV Control Register */
+ __I uint32_t OVVSTA; /*!< PMD OVV Status Register */
+ __IO uint32_t DTR; /*!< PMD Dead Time Register */
+ __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */
+ __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */
+ __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */
+ __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */
+ __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */
+ __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */
+ __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */
+ __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */
+ __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */
+ __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */
+ __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */
+ __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/
+} TSB_PMD_TypeDef;
+
+/**
+ * @brief
+ */
+typedef struct
+{
+ __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */
+ __IO uint32_t CLKCR; /*!< Clock Control Register */
+ __IO uint32_t OCR0; /*!< Output Control Register 0 */
+ __IO uint32_t OCR1; /*!< Output Control Register 1 */
+ __IO uint32_t ICR; /*!< Input Control Register */
+ __IO uint32_t CR; /*!< Control Register */
+ __I uint32_t BR; /*!< Buffer Register */
+ __I uint32_t SR; /*!< Status Register */
+ __IO uint32_t INTCR; /*!< interrupt Control Register */
+} TSB_ISD_TypeDef;
+
+/**
+ * @brief
+ */
+typedef struct
+{
+ uint32_t RESERVED0[4];
+ __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */
+ __IO uint32_t SSR; /*!< Flash Security Status Register */
+ __O uint32_t KCR; /*!< Flash Key Code Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SR0; /*!< Flash Status Register 0 */
+ uint32_t RESERVED2[3];
+ __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */
+ __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */
+ uint32_t RESERVED3;
+ __I uint32_t PSR3; /*!< Flash Protect Status Register 3 */
+ __I uint32_t PSR4; /*!< Flash Protect Status Register 4 */
+ uint32_t RESERVED4;
+ __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */
+ uint32_t RESERVED5;
+ __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */
+ __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */
+ uint32_t RESERVED6;
+ __IO uint32_t PMR3; /*!< Flash Protect Mask Register 3 */
+ __IO uint32_t PMR4; /*!< Flash Protect Mask Register 4 */
+ uint32_t RESERVED7;
+ __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */
+ uint32_t RESERVED8[37];
+ __I uint32_t SR1; /*!< Flash Status Register 1 */
+ __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */
+ uint32_t RESERVED9[14];
+ __IO uint32_t AREASEL; /*!< Flash Area Selection Register */
+ uint32_t RESERVED10;
+ __IO uint32_t CR; /*!< Flash Control Register */
+ __IO uint32_t STSCLR; /*!< Flash Status Clear Register */
+ __IO uint32_t BNKCR; /*!< Flash Bank Change Register */
+ uint32_t RESERVED11;
+ __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */
+} TSB_FC_TypeDef;
+
+
+/* Memory map */
+#define FLASH_BASE (0x00000000UL)
+#define RAM_BASE (0x20000000UL)
+#define PERI_BASE (0x40000000UL)
+
+
+#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL)
+#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL)
+#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL)
+#define TSB_IA_BASE (PERI_BASE + 0x003E000UL)
+#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL)
+#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL)
+#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL)
+#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL)
+#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL)
+#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL)
+#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL)
+#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL)
+#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL)
+#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL)
+#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL)
+#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL)
+#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL)
+#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL)
+#define TSB_CG_BASE (PERI_BASE + 0x0083000UL)
+#define TSB_IB_BASE (PERI_BASE + 0x0083200UL)
+#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL)
+#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL)
+#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL)
+#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL)
+#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL)
+#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL)
+#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL)
+#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL)
+#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL)
+#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL)
+#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL)
+#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL)
+#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL)
+#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL)
+#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL)
+#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL)
+#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL)
+#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL)
+#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL)
+#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL)
+#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL)
+#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL)
+#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL)
+#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL)
+#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL)
+#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL)
+#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL)
+#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL)
+#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL)
+#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL)
+#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL)
+#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL)
+#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL)
+#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL)
+#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL)
+#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL)
+#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL)
+#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL)
+#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL)
+#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL)
+#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL)
+#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL)
+#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL)
+#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL)
+#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL)
+#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL)
+#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL)
+#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL)
+#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL)
+#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL)
+#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL)
+#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL)
+#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL)
+#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL)
+#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL)
+#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL)
+#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL)
+#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL)
+#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL)
+#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL)
+#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL)
+#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL)
+#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL)
+#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL)
+#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL)
+#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL)
+#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL)
+
+
+/* Peripheral declaration */
+#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE)
+#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE)
+#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE)
+#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE)
+#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE)
+#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE)
+#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE)
+#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE)
+#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE)
+#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE)
+#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE)
+#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE)
+#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE)
+#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE)
+#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE)
+#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE)
+#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE)
+#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE)
+#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE)
+#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE)
+#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE)
+#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE)
+#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE)
+#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE)
+#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE)
+#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE)
+#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE)
+#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE)
+#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE)
+#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE)
+#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE)
+#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE)
+#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE)
+#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE)
+#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE)
+#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE)
+#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE)
+#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE)
+#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE)
+#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE)
+#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE)
+#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE)
+#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE)
+#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE)
+#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE)
+#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE)
+#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE)
+#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE)
+#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE)
+#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE)
+#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE)
+#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE)
+#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE)
+#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE)
+#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE)
+#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE)
+#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE)
+#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE)
+#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE)
+#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE)
+#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE)
+#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE)
+#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE)
+#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE)
+#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE)
+#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE)
+#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE)
+#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE)
+#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE)
+#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE)
+#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE)
+#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE)
+#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE)
+#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE)
+#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE)
+#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE)
+#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE)
+#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE)
+#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE)
+#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE)
+#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE)
+#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE)
+#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE)
+#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE)
+#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE)
+#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE)
+#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE)
+
+
+/* Bit-Band for Device Specific Peripheral Registers */
+#define BITBAND_OFFSET (0x02000000UL)
+#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET)
+#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2))
+
+
+
+/* DMA Controller */
+#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0)))
+#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1)))
+#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0)))
+#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1)))
+#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0)))
+#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1)))
+#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0)))
+#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1)))
+#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0)))
+#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1)))
+#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0)))
+#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1)))
+#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0)))
+#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26)))
+#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27)))
+#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31)))
+#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0)))
+#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14)))
+#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15)))
+#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16)))
+#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17)))
+#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18)))
+#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26)))
+#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27)))
+#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31)))
+#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0)))
+#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14)))
+#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15)))
+#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16)))
+#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17)))
+#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18)))
+
+#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0)))
+#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1)))
+#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0)))
+#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1)))
+#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0)))
+#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1)))
+#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0)))
+#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1)))
+#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0)))
+#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1)))
+#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0)))
+#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1)))
+#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0)))
+#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26)))
+#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27)))
+#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31)))
+#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0)))
+#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14)))
+#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15)))
+#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16)))
+#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17)))
+#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18)))
+#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26)))
+#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27)))
+#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31)))
+#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0)))
+#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14)))
+#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15)))
+#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16)))
+#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17)))
+#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18)))
+
+
+/* */
+#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0)))
+#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0)))
+#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6)))
+#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6)))
+#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0)))
+#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1)))
+#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4)))
+#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5)))
+#define TSB_SMI0_INT_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0)))
+#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0)))
+#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1)))
+
+
+
+
+
+/* TRGSEL */
+#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0)))
+#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1)))
+#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2)))
+#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8)))
+#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9)))
+#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10)))
+#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16)))
+#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17)))
+#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18)))
+#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24)))
+#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25)))
+#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26)))
+#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0)))
+#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1)))
+#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2)))
+#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8)))
+#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9)))
+#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10)))
+#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16)))
+#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17)))
+#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18)))
+#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24)))
+#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25)))
+#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26)))
+#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0)))
+#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1)))
+#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2)))
+#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8)))
+#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9)))
+#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10)))
+#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16)))
+#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17)))
+#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18)))
+#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24)))
+#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25)))
+#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26)))
+#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0)))
+#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1)))
+#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2)))
+#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8)))
+#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9)))
+#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10)))
+#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16)))
+#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17)))
+#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18)))
+#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24)))
+#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25)))
+#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26)))
+#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0)))
+#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1)))
+#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2)))
+#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8)))
+#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9)))
+#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10)))
+#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16)))
+#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17)))
+#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18)))
+#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24)))
+#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25)))
+#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26)))
+#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0)))
+#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1)))
+#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2)))
+#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8)))
+#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9)))
+#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10)))
+#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16)))
+#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17)))
+#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18)))
+#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24)))
+#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25)))
+#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26)))
+#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0)))
+#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1)))
+#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2)))
+#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8)))
+#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9)))
+#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10)))
+#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16)))
+#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17)))
+#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18)))
+#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24)))
+#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25)))
+#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26)))
+#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0)))
+#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1)))
+#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2)))
+#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8)))
+#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9)))
+#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10)))
+#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16)))
+#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17)))
+#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18)))
+#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24)))
+#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25)))
+#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26)))
+#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0)))
+#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1)))
+#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2)))
+#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8)))
+#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9)))
+#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10)))
+#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16)))
+#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17)))
+#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18)))
+#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24)))
+#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25)))
+#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26)))
+#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0)))
+#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1)))
+#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2)))
+#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8)))
+#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9)))
+#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10)))
+#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16)))
+#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17)))
+#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18)))
+#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24)))
+#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25)))
+#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26)))
+#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0)))
+#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1)))
+#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2)))
+#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8)))
+#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9)))
+#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10)))
+#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16)))
+#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17)))
+#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18)))
+#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24)))
+#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25)))
+#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26)))
+#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0)))
+#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1)))
+#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2)))
+#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8)))
+#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9)))
+#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10)))
+#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16)))
+#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17)))
+#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18)))
+#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24)))
+#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25)))
+#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26)))
+#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0)))
+#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1)))
+#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2)))
+#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8)))
+#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9)))
+#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10)))
+#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16)))
+#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17)))
+#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18)))
+#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24)))
+#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25)))
+#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26)))
+#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0)))
+#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1)))
+#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2)))
+#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8)))
+#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9)))
+#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10)))
+#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16)))
+#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17)))
+#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18)))
+#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24)))
+#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25)))
+#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26)))
+
+
+
+/* Serial Interface (TSPI) */
+#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0)))
+#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12)))
+#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13)))
+#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14)))
+#define TSB_TSPI0_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15)))
+#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0)))
+#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1)))
+#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2)))
+#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4)))
+#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5)))
+#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6)))
+#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7)))
+#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16)))
+#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21)))
+#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0)))
+#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1)))
+#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14)))
+#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15)))
+#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16)))
+#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17)))
+#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18)))
+#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19)))
+#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31)))
+#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0)))
+#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1)))
+#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4)))
+#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5)))
+#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6)))
+#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7)))
+#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20)))
+#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21)))
+#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22)))
+#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23)))
+#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31)))
+#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1)))
+#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2)))
+#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3)))
+
+#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0)))
+#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12)))
+#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13)))
+#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14)))
+#define TSB_TSPI1_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15)))
+#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0)))
+#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1)))
+#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2)))
+#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4)))
+#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5)))
+#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6)))
+#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7)))
+#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16)))
+#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21)))
+#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0)))
+#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1)))
+#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14)))
+#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15)))
+#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16)))
+#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17)))
+#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18)))
+#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19)))
+#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31)))
+#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0)))
+#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1)))
+#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4)))
+#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5)))
+#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6)))
+#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7)))
+#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20)))
+#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21)))
+#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22)))
+#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23)))
+#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31)))
+#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1)))
+#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2)))
+#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3)))
+
+#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0)))
+#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12)))
+#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13)))
+#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14)))
+#define TSB_TSPI2_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15)))
+#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0)))
+#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1)))
+#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2)))
+#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4)))
+#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5)))
+#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6)))
+#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7)))
+#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16)))
+#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21)))
+#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0)))
+#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1)))
+#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14)))
+#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15)))
+#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16)))
+#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17)))
+#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18)))
+#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19)))
+#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31)))
+#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0)))
+#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1)))
+#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4)))
+#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5)))
+#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6)))
+#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7)))
+#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20)))
+#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21)))
+#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22)))
+#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23)))
+#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31)))
+#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1)))
+#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2)))
+#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3)))
+
+#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0)))
+#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12)))
+#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13)))
+#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14)))
+#define TSB_TSPI3_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15)))
+#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0)))
+#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1)))
+#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2)))
+#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4)))
+#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5)))
+#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6)))
+#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7)))
+#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16)))
+#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21)))
+#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0)))
+#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1)))
+#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14)))
+#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15)))
+#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16)))
+#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17)))
+#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18)))
+#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19)))
+#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31)))
+#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0)))
+#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1)))
+#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4)))
+#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5)))
+#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6)))
+#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7)))
+#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20)))
+#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21)))
+#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22)))
+#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23)))
+#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31)))
+#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1)))
+#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2)))
+#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3)))
+
+#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0)))
+#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12)))
+#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13)))
+#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14)))
+#define TSB_TSPI4_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15)))
+#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0)))
+#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1)))
+#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2)))
+#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4)))
+#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5)))
+#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6)))
+#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7)))
+#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16)))
+#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21)))
+#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0)))
+#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1)))
+#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14)))
+#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15)))
+#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16)))
+#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17)))
+#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18)))
+#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19)))
+#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31)))
+#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0)))
+#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1)))
+#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4)))
+#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5)))
+#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6)))
+#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7)))
+#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20)))
+#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21)))
+#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22)))
+#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23)))
+#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31)))
+#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1)))
+#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2)))
+#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3)))
+
+#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0)))
+#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12)))
+#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13)))
+#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14)))
+#define TSB_TSPI5_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15)))
+#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0)))
+#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1)))
+#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2)))
+#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4)))
+#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5)))
+#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6)))
+#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7)))
+#define TSB_TSPI5_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,16)))
+#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21)))
+#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0)))
+#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1)))
+#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14)))
+#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15)))
+#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16)))
+#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17)))
+#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18)))
+#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19)))
+#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31)))
+#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0)))
+#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1)))
+#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4)))
+#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5)))
+#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6)))
+#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7)))
+#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20)))
+#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21)))
+#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22)))
+#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23)))
+#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31)))
+#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1)))
+#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2)))
+#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3)))
+
+#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0)))
+#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12)))
+#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13)))
+#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14)))
+#define TSB_TSPI6_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15)))
+#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0)))
+#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1)))
+#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2)))
+#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4)))
+#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5)))
+#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6)))
+#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7)))
+#define TSB_TSPI6_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,16)))
+#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21)))
+#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0)))
+#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1)))
+#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14)))
+#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15)))
+#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16)))
+#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17)))
+#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18)))
+#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19)))
+#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31)))
+#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0)))
+#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1)))
+#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4)))
+#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5)))
+#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6)))
+#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7)))
+#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20)))
+#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21)))
+#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22)))
+#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23)))
+#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31)))
+#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1)))
+#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2)))
+#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3)))
+
+#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0)))
+#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12)))
+#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13)))
+#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14)))
+#define TSB_TSPI7_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15)))
+#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0)))
+#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1)))
+#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2)))
+#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4)))
+#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5)))
+#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6)))
+#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7)))
+#define TSB_TSPI7_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,16)))
+#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21)))
+#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0)))
+#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1)))
+#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14)))
+#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15)))
+#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16)))
+#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17)))
+#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18)))
+#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19)))
+#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31)))
+#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0)))
+#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1)))
+#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4)))
+#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5)))
+#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6)))
+#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7)))
+#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20)))
+#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21)))
+#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22)))
+#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23)))
+#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31)))
+#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1)))
+#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2)))
+#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3)))
+
+#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0)))
+#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12)))
+#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13)))
+#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14)))
+#define TSB_TSPI8_CR1_TRGIN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15)))
+#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0)))
+#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1)))
+#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2)))
+#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4)))
+#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5)))
+#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6)))
+#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7)))
+#define TSB_TSPI8_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,16)))
+#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21)))
+#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0)))
+#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1)))
+#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14)))
+#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15)))
+#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16)))
+#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17)))
+#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18)))
+#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19)))
+#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31)))
+#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0)))
+#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1)))
+#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4)))
+#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5)))
+#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6)))
+#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7)))
+#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20)))
+#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21)))
+#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22)))
+#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23)))
+#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31)))
+#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1)))
+#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2)))
+#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3)))
+
+
+/* External Bus Interface(EXB) */
+#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0)))
+#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0)))
+#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12)))
+#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13)))
+#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0)))
+#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12)))
+#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13)))
+#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0)))
+#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12)))
+#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13)))
+#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0)))
+#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12)))
+#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13)))
+#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0)))
+
+
+/* Clock Generator (CG) */
+#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0)))
+#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8)))
+#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9)))
+#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16)))
+#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0)))
+#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1)))
+#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2)))
+#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0)))
+#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1)))
+#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8)))
+#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0)))
+#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1)))
+#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0)))
+#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1)))
+#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2)))
+#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3)))
+#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4)))
+#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5)))
+#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6)))
+#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7)))
+#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8)))
+#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9)))
+#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10)))
+#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11)))
+#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12)))
+#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13)))
+#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14)))
+#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15)))
+#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16)))
+#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17)))
+#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18)))
+#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19)))
+#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20)))
+#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21)))
+#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22)))
+#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23)))
+#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24)))
+#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25)))
+#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26)))
+#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27)))
+#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28)))
+#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29)))
+#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30)))
+#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31)))
+#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0)))
+#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1)))
+#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2)))
+#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3)))
+#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4)))
+#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5)))
+#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6)))
+#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7)))
+#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8)))
+#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9)))
+#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10)))
+#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11)))
+#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12)))
+#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13)))
+#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14)))
+#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15)))
+#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16)))
+#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17)))
+#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18)))
+#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19)))
+#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20)))
+#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21)))
+#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22)))
+#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23)))
+#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24)))
+#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28)))
+#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29)))
+#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30)))
+#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31)))
+#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0)))
+#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1)))
+#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2)))
+#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3)))
+#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4)))
+#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5)))
+#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6)))
+#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7)))
+#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8)))
+#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9)))
+#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10)))
+#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11)))
+#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12)))
+#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23)))
+#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26)))
+#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27)))
+#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0)))
+#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16)))
+#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0)))
+#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1)))
+#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2)))
+
+
+
+/* Interrupt Monitor Register */
+#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0)))
+#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16)))
+#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0)))
+#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1)))
+#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2)))
+#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3)))
+#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4)))
+#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5)))
+#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6)))
+#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7)))
+#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8)))
+#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9)))
+#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10)))
+#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11)))
+#define TSB_IMN_FLG1_INT044FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,12)))
+#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13)))
+#define TSB_IMN_FLG1_INT046FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,14)))
+#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15)))
+#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16)))
+#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17)))
+#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18)))
+#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19)))
+#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20)))
+#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21)))
+#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22)))
+#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23)))
+#define TSB_IMN_FLG1_INT056FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,24)))
+#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25)))
+#define TSB_IMN_FLG1_INT058FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,26)))
+#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27)))
+#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28)))
+#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29)))
+#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30)))
+#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31)))
+#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17)))
+#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18)))
+#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19)))
+#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20)))
+#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21)))
+#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22)))
+#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23)))
+#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24)))
+#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25)))
+#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0)))
+#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1)))
+#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2)))
+#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3)))
+#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4)))
+#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5)))
+#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6)))
+#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7)))
+#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8)))
+#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9)))
+#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10)))
+#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11)))
+#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12)))
+#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13)))
+#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14)))
+#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15)))
+#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16)))
+#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17)))
+#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18)))
+#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19)))
+#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20)))
+#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21)))
+#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22)))
+#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23)))
+#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24)))
+#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25)))
+#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26)))
+#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27)))
+#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28)))
+#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29)))
+#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30)))
+#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31)))
+#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0)))
+#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1)))
+#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2)))
+#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3)))
+#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4)))
+#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5)))
+#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6)))
+#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7)))
+#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8)))
+#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9)))
+#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10)))
+#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11)))
+#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12)))
+#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13)))
+#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14)))
+#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15)))
+#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16)))
+#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17)))
+#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18)))
+#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19)))
+#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20)))
+#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21)))
+#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22)))
+#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23)))
+#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24)))
+#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25)))
+#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26)))
+#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27)))
+#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28)))
+#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29)))
+#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30)))
+#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31)))
+#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0)))
+#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1)))
+#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2)))
+#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3)))
+#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4)))
+#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5)))
+#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6)))
+#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7)))
+#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8)))
+#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9)))
+#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10)))
+#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11)))
+#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12)))
+#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13)))
+#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14)))
+#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15)))
+#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16)))
+#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17)))
+#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18)))
+#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19)))
+#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20)))
+#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21)))
+#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22)))
+#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23)))
+#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24)))
+#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25)))
+#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26)))
+#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27)))
+#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28)))
+#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29)))
+#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30)))
+#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31)))
+#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0)))
+#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1)))
+#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2)))
+#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3)))
+#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4)))
+#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5)))
+#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6)))
+#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7)))
+#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8)))
+#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9)))
+#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10)))
+#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11)))
+#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12)))
+#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13)))
+#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14)))
+#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15)))
+#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16)))
+#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17)))
+#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18)))
+#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19)))
+#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20)))
+#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21)))
+#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22)))
+#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23)))
+#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24)))
+#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25)))
+#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26)))
+#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27)))
+#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28)))
+#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29)))
+#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30)))
+#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31)))
+#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0)))
+#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1)))
+#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2)))
+#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3)))
+#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4)))
+#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5)))
+#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6)))
+#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7)))
+#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8)))
+#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9)))
+#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10)))
+#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11)))
+
+
+/* DNF */
+#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0)))
+#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1)))
+#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2)))
+#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3)))
+#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4)))
+#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5)))
+#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6)))
+#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7)))
+#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8)))
+#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9)))
+#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10)))
+#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11)))
+#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12)))
+#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13)))
+#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14)))
+#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15)))
+
+#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0)))
+#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1)))
+#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2)))
+#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3)))
+#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4)))
+#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5)))
+#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6)))
+#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7)))
+#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8)))
+#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9)))
+#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10)))
+#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11)))
+#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12)))
+#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13)))
+#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14)))
+#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15)))
+
+
+/* Watchdog Timer (WD) */
+#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0)))
+#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1)))
+#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0)))
+#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1)))
+
+
+/* NBD */
+#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0)))
+
+
+/* Malti Porpose Direct Memory Accsess(MDMA) */
+#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16)))
+#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24)))
+#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8)))
+#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16)))
+#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24)))
+#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8)))
+#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16)))
+#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24)))
+#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8)))
+#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16)))
+#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24)))
+#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8)))
+#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16)))
+#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24)))
+#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8)))
+#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16)))
+#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24)))
+#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8)))
+#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16)))
+#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24)))
+#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8)))
+#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16)))
+#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24)))
+#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8)))
+#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16)))
+#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24)))
+#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8)))
+#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16)))
+#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24)))
+#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8)))
+#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16)))
+#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24)))
+#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8)))
+#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16)))
+#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24)))
+#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8)))
+#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16)))
+#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24)))
+#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8)))
+#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16)))
+#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24)))
+#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8)))
+#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16)))
+#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24)))
+#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8)))
+#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16)))
+#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24)))
+#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8)))
+#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16)))
+#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24)))
+#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8)))
+#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16)))
+#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24)))
+#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8)))
+#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16)))
+#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24)))
+#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8)))
+#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16)))
+#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24)))
+#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8)))
+#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16)))
+#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24)))
+#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8)))
+#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16)))
+#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24)))
+#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8)))
+#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16)))
+#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24)))
+#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8)))
+#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16)))
+#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24)))
+#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8)))
+#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16)))
+#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24)))
+#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8)))
+#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16)))
+#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24)))
+#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8)))
+#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16)))
+#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24)))
+#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8)))
+#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16)))
+#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24)))
+#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8)))
+#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16)))
+#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24)))
+#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8)))
+#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16)))
+#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24)))
+#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8)))
+#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16)))
+#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24)))
+#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8)))
+#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16)))
+#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24)))
+#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8)))
+#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16)))
+#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24)))
+#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8)))
+#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0)))
+#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1)))
+#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2)))
+#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3)))
+#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4)))
+#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5)))
+#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6)))
+#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7)))
+#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8)))
+#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9)))
+#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10)))
+#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11)))
+#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12)))
+#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13)))
+#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14)))
+#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15)))
+#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16)))
+#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17)))
+#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18)))
+#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19)))
+#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20)))
+#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21)))
+#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22)))
+#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23)))
+#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24)))
+#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25)))
+#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26)))
+#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27)))
+#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28)))
+#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29)))
+#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30)))
+#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31)))
+
+
+/* ARM Prime Cell PL011 */
+#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8)))
+#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9)))
+#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10)))
+#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11)))
+#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0)))
+#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1)))
+#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2)))
+#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3)))
+#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0)))
+#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3)))
+#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4)))
+#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5)))
+#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6)))
+#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7)))
+#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0)))
+#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1)))
+#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2)))
+#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3)))
+#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4)))
+#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7)))
+#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0)))
+#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1)))
+#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2)))
+#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8)))
+#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9)))
+#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14)))
+#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15)))
+#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4)))
+#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5)))
+#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6)))
+#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7)))
+#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8)))
+#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9)))
+#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10)))
+#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4)))
+#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5)))
+#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6)))
+#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7)))
+#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8)))
+#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9)))
+#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10)))
+#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4)))
+#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5)))
+#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6)))
+#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7)))
+#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8)))
+#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9)))
+#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10)))
+#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4)))
+#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5)))
+#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6)))
+#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7)))
+#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8)))
+#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9)))
+#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10)))
+#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0)))
+#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1)))
+#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2)))
+
+#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8)))
+#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9)))
+#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10)))
+#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11)))
+#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0)))
+#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1)))
+#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2)))
+#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3)))
+#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0)))
+#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3)))
+#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4)))
+#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5)))
+#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6)))
+#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7)))
+#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0)))
+#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1)))
+#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2)))
+#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3)))
+#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4)))
+#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7)))
+#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0)))
+#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1)))
+#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2)))
+#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8)))
+#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9)))
+#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14)))
+#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15)))
+#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4)))
+#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5)))
+#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6)))
+#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7)))
+#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8)))
+#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9)))
+#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10)))
+#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4)))
+#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5)))
+#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6)))
+#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7)))
+#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8)))
+#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9)))
+#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10)))
+#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4)))
+#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5)))
+#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6)))
+#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7)))
+#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8)))
+#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9)))
+#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10)))
+#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4)))
+#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5)))
+#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6)))
+#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7)))
+#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8)))
+#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9)))
+#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10)))
+#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0)))
+#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1)))
+#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2)))
+
+
+/* ADC */
+#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0)))
+#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1)))
+#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2)))
+#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7)))
+#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0)))
+#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1)))
+#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4)))
+#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5)))
+#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6)))
+#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7)))
+#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0)))
+#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1)))
+#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2)))
+#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3)))
+#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7)))
+#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0)))
+#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1)))
+#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0)))
+#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1)))
+#define TSB_ADA_CMPEN_CMP2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,2)))
+#define TSB_ADA_CMPEN_CMP3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,3)))
+#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5)))
+#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6)))
+#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5)))
+#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6)))
+#define TSB_ADA_CMPCR2_ADBIG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,5)))
+#define TSB_ADA_CMPCR2_CMPCND2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR2,6)))
+#define TSB_ADA_CMPCR3_ADBIG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,5)))
+#define TSB_ADA_CMPCR3_CMPCND3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR3,6)))
+#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7)))
+#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7)))
+#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7)))
+#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7)))
+#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7)))
+#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7)))
+#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7)))
+#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7)))
+#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7)))
+#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7)))
+#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7)))
+#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7)))
+#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7)))
+#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7)))
+#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7)))
+#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7)))
+#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7)))
+#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7)))
+#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7)))
+#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7)))
+#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7)))
+#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7)))
+#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7)))
+#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7)))
+#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0)))
+#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1)))
+#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28)))
+#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29)))
+#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0)))
+#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1)))
+#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28)))
+#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29)))
+#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0)))
+#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1)))
+#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28)))
+#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29)))
+#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0)))
+#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1)))
+#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28)))
+#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29)))
+#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0)))
+#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1)))
+#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28)))
+#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29)))
+#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0)))
+#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1)))
+#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28)))
+#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29)))
+#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0)))
+#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1)))
+#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28)))
+#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29)))
+#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0)))
+#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1)))
+#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28)))
+#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29)))
+#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0)))
+#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1)))
+#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28)))
+#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29)))
+#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0)))
+#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1)))
+#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28)))
+#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29)))
+#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0)))
+#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1)))
+#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28)))
+#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29)))
+#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0)))
+#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1)))
+#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28)))
+#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29)))
+#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0)))
+#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1)))
+#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28)))
+#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29)))
+#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0)))
+#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1)))
+#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28)))
+#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29)))
+#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0)))
+#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1)))
+#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28)))
+#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29)))
+#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0)))
+#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1)))
+#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28)))
+#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29)))
+#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0)))
+#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1)))
+#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28)))
+#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29)))
+#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0)))
+#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1)))
+#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28)))
+#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29)))
+#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0)))
+#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1)))
+#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28)))
+#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29)))
+#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0)))
+#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1)))
+#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28)))
+#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29)))
+#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0)))
+#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1)))
+#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28)))
+#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29)))
+#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0)))
+#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1)))
+#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28)))
+#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29)))
+#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0)))
+#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1)))
+#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28)))
+#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29)))
+#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0)))
+#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1)))
+#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28)))
+#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29)))
+
+
+/* Digital analog converter (DAC) */
+#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0)))
+
+#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0)))
+
+
+/* 16-bit Timer/Event Counter (TB) */
+#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0)))
+#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1)))
+#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0)))
+#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1)))
+#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2)))
+#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4)))
+#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20)))
+#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0)))
+#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1)))
+#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2)))
+#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3)))
+#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0)))
+#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1)))
+#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2)))
+#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3)))
+#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0)))
+#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1)))
+#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2)))
+#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0)))
+#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1)))
+#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2)))
+#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4)))
+#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20)))
+#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0)))
+#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1)))
+#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2)))
+#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3)))
+#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0)))
+#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1)))
+#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2)))
+#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3)))
+#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0)))
+#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1)))
+#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2)))
+#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0)))
+#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1)))
+#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2)))
+#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4)))
+#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20)))
+#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0)))
+#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1)))
+#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2)))
+#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3)))
+#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4)))
+#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0)))
+#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1)))
+#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2)))
+#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3)))
+#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4)))
+#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0)))
+#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1)))
+#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2)))
+#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0)))
+#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1)))
+
+#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0)))
+#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1)))
+#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0)))
+#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1)))
+#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2)))
+#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4)))
+#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20)))
+#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0)))
+#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1)))
+#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2)))
+#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3)))
+#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0)))
+#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1)))
+#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2)))
+#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3)))
+#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0)))
+#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1)))
+#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2)))
+#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0)))
+#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1)))
+#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2)))
+#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4)))
+#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20)))
+#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0)))
+#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1)))
+#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2)))
+#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3)))
+#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0)))
+#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1)))
+#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2)))
+#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3)))
+#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0)))
+#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1)))
+#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2)))
+#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0)))
+#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1)))
+#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2)))
+#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4)))
+#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20)))
+#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0)))
+#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1)))
+#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2)))
+#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3)))
+#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4)))
+#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0)))
+#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1)))
+#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2)))
+#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3)))
+#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4)))
+#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0)))
+#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1)))
+#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2)))
+#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0)))
+#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1)))
+
+#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0)))
+#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1)))
+#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0)))
+#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1)))
+#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2)))
+#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4)))
+#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20)))
+#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0)))
+#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1)))
+#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2)))
+#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3)))
+#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0)))
+#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1)))
+#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2)))
+#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3)))
+#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0)))
+#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1)))
+#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2)))
+#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0)))
+#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1)))
+#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2)))
+#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4)))
+#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20)))
+#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0)))
+#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1)))
+#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2)))
+#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3)))
+#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0)))
+#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1)))
+#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2)))
+#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3)))
+#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0)))
+#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1)))
+#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2)))
+#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0)))
+#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1)))
+#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2)))
+#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4)))
+#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20)))
+#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0)))
+#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1)))
+#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2)))
+#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3)))
+#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4)))
+#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0)))
+#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1)))
+#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2)))
+#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3)))
+#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4)))
+#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0)))
+#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1)))
+#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2)))
+#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0)))
+#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1)))
+
+#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0)))
+#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1)))
+#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0)))
+#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1)))
+#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2)))
+#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4)))
+#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20)))
+#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0)))
+#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1)))
+#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2)))
+#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3)))
+#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0)))
+#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1)))
+#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2)))
+#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3)))
+#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0)))
+#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1)))
+#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2)))
+#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0)))
+#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1)))
+#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2)))
+#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4)))
+#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20)))
+#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0)))
+#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1)))
+#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2)))
+#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3)))
+#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0)))
+#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1)))
+#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2)))
+#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3)))
+#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0)))
+#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1)))
+#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2)))
+#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0)))
+#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1)))
+#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2)))
+#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4)))
+#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20)))
+#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0)))
+#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1)))
+#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2)))
+#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3)))
+#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4)))
+#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0)))
+#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1)))
+#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2)))
+#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3)))
+#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4)))
+#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0)))
+#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1)))
+#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2)))
+#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0)))
+#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1)))
+
+#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0)))
+#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1)))
+#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0)))
+#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1)))
+#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2)))
+#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4)))
+#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20)))
+#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0)))
+#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1)))
+#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2)))
+#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3)))
+#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0)))
+#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1)))
+#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2)))
+#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3)))
+#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0)))
+#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1)))
+#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2)))
+#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0)))
+#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1)))
+#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2)))
+#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4)))
+#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20)))
+#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0)))
+#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1)))
+#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2)))
+#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3)))
+#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0)))
+#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1)))
+#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2)))
+#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3)))
+#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0)))
+#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1)))
+#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2)))
+#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0)))
+#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1)))
+#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2)))
+#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4)))
+#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20)))
+#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0)))
+#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1)))
+#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2)))
+#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3)))
+#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4)))
+#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0)))
+#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1)))
+#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2)))
+#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3)))
+#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4)))
+#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0)))
+#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1)))
+#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2)))
+#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0)))
+#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1)))
+
+#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0)))
+#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1)))
+#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0)))
+#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1)))
+#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2)))
+#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4)))
+#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20)))
+#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0)))
+#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1)))
+#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2)))
+#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3)))
+#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0)))
+#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1)))
+#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2)))
+#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3)))
+#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0)))
+#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1)))
+#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2)))
+#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0)))
+#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1)))
+#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2)))
+#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4)))
+#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20)))
+#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0)))
+#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1)))
+#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2)))
+#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3)))
+#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0)))
+#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1)))
+#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2)))
+#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3)))
+#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0)))
+#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1)))
+#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2)))
+#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0)))
+#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1)))
+#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2)))
+#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4)))
+#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20)))
+#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0)))
+#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1)))
+#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2)))
+#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3)))
+#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4)))
+#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0)))
+#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1)))
+#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2)))
+#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3)))
+#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4)))
+#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0)))
+#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1)))
+#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2)))
+#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0)))
+#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1)))
+
+#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0)))
+#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1)))
+#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0)))
+#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1)))
+#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2)))
+#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4)))
+#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20)))
+#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0)))
+#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1)))
+#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2)))
+#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3)))
+#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0)))
+#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1)))
+#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2)))
+#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3)))
+#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0)))
+#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1)))
+#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2)))
+#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0)))
+#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1)))
+#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2)))
+#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4)))
+#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20)))
+#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0)))
+#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1)))
+#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2)))
+#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3)))
+#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0)))
+#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1)))
+#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2)))
+#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3)))
+#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0)))
+#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1)))
+#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2)))
+#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0)))
+#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1)))
+#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2)))
+#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4)))
+#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20)))
+#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0)))
+#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1)))
+#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2)))
+#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3)))
+#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4)))
+#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0)))
+#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1)))
+#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2)))
+#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3)))
+#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4)))
+#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0)))
+#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1)))
+#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2)))
+#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0)))
+#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1)))
+
+#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0)))
+#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1)))
+#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0)))
+#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1)))
+#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2)))
+#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4)))
+#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20)))
+#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0)))
+#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1)))
+#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2)))
+#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3)))
+#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0)))
+#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1)))
+#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2)))
+#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3)))
+#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0)))
+#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1)))
+#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2)))
+#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0)))
+#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1)))
+#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2)))
+#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4)))
+#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20)))
+#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0)))
+#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1)))
+#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2)))
+#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3)))
+#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0)))
+#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1)))
+#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2)))
+#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3)))
+#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0)))
+#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1)))
+#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2)))
+#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0)))
+#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1)))
+#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2)))
+#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4)))
+#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20)))
+#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0)))
+#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1)))
+#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2)))
+#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3)))
+#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4)))
+#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0)))
+#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1)))
+#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2)))
+#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3)))
+#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4)))
+#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0)))
+#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1)))
+#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2)))
+#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0)))
+#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1)))
+
+#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0)))
+#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1)))
+#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0)))
+#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1)))
+#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2)))
+#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4)))
+#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20)))
+#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0)))
+#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1)))
+#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2)))
+#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3)))
+#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0)))
+#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1)))
+#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2)))
+#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3)))
+#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0)))
+#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1)))
+#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2)))
+#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0)))
+#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1)))
+#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2)))
+#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4)))
+#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20)))
+#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0)))
+#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1)))
+#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2)))
+#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3)))
+#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0)))
+#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1)))
+#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2)))
+#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3)))
+#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0)))
+#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1)))
+#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2)))
+#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0)))
+#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1)))
+#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2)))
+#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4)))
+#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20)))
+#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0)))
+#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1)))
+#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2)))
+#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3)))
+#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4)))
+#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0)))
+#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1)))
+#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2)))
+#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3)))
+#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4)))
+#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0)))
+#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1)))
+#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2)))
+#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0)))
+#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1)))
+
+#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0)))
+#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1)))
+#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0)))
+#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1)))
+#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2)))
+#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4)))
+#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20)))
+#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0)))
+#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1)))
+#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2)))
+#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3)))
+#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0)))
+#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1)))
+#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2)))
+#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3)))
+#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0)))
+#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1)))
+#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2)))
+#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0)))
+#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1)))
+#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2)))
+#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4)))
+#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20)))
+#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0)))
+#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1)))
+#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2)))
+#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3)))
+#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0)))
+#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1)))
+#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2)))
+#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3)))
+#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0)))
+#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1)))
+#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2)))
+#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0)))
+#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1)))
+#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2)))
+#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4)))
+#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20)))
+#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0)))
+#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1)))
+#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2)))
+#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3)))
+#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4)))
+#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0)))
+#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1)))
+#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2)))
+#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3)))
+#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4)))
+#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0)))
+#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1)))
+#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2)))
+#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0)))
+#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1)))
+
+#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0)))
+#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1)))
+#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0)))
+#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1)))
+#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2)))
+#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4)))
+#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20)))
+#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0)))
+#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1)))
+#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2)))
+#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3)))
+#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0)))
+#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1)))
+#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2)))
+#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3)))
+#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0)))
+#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1)))
+#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2)))
+#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0)))
+#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1)))
+#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2)))
+#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4)))
+#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20)))
+#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0)))
+#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1)))
+#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2)))
+#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3)))
+#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0)))
+#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1)))
+#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2)))
+#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3)))
+#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0)))
+#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1)))
+#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2)))
+#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0)))
+#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1)))
+#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2)))
+#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4)))
+#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20)))
+#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0)))
+#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1)))
+#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2)))
+#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3)))
+#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4)))
+#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0)))
+#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1)))
+#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2)))
+#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3)))
+#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4)))
+#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0)))
+#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1)))
+#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2)))
+#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0)))
+#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1)))
+
+#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0)))
+#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1)))
+#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0)))
+#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1)))
+#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2)))
+#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4)))
+#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20)))
+#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0)))
+#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1)))
+#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2)))
+#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3)))
+#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0)))
+#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1)))
+#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2)))
+#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3)))
+#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0)))
+#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1)))
+#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2)))
+#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0)))
+#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1)))
+#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2)))
+#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4)))
+#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20)))
+#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0)))
+#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1)))
+#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2)))
+#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3)))
+#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0)))
+#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1)))
+#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2)))
+#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3)))
+#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0)))
+#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1)))
+#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2)))
+#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0)))
+#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1)))
+#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2)))
+#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4)))
+#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20)))
+#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0)))
+#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1)))
+#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2)))
+#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3)))
+#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4)))
+#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0)))
+#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1)))
+#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2)))
+#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3)))
+#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4)))
+#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0)))
+#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1)))
+#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2)))
+#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0)))
+#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1)))
+
+#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0)))
+#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1)))
+#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0)))
+#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1)))
+#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2)))
+#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4)))
+#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20)))
+#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0)))
+#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1)))
+#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2)))
+#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3)))
+#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0)))
+#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1)))
+#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2)))
+#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3)))
+#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0)))
+#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1)))
+#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2)))
+#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0)))
+#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1)))
+#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2)))
+#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4)))
+#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20)))
+#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0)))
+#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1)))
+#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2)))
+#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3)))
+#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0)))
+#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1)))
+#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2)))
+#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3)))
+#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0)))
+#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1)))
+#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2)))
+#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0)))
+#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1)))
+#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2)))
+#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4)))
+#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20)))
+#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0)))
+#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1)))
+#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2)))
+#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3)))
+#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4)))
+#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0)))
+#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1)))
+#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2)))
+#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3)))
+#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4)))
+#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0)))
+#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1)))
+#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2)))
+#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0)))
+#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1)))
+
+#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0)))
+#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1)))
+#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0)))
+#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1)))
+#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2)))
+#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4)))
+#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20)))
+#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0)))
+#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1)))
+#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2)))
+#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3)))
+#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0)))
+#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1)))
+#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2)))
+#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3)))
+#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0)))
+#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1)))
+#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2)))
+#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0)))
+#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1)))
+#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2)))
+#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4)))
+#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20)))
+#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0)))
+#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1)))
+#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2)))
+#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3)))
+#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0)))
+#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1)))
+#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2)))
+#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3)))
+#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0)))
+#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1)))
+#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2)))
+#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0)))
+#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1)))
+#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2)))
+#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4)))
+#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20)))
+#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0)))
+#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1)))
+#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2)))
+#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3)))
+#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4)))
+#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0)))
+#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1)))
+#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2)))
+#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3)))
+#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4)))
+#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0)))
+#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1)))
+#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2)))
+#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0)))
+#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1)))
+
+
+/* UART */
+#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7)))
+#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2)))
+#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3)))
+#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4)))
+#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5)))
+#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6)))
+#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8)))
+#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9)))
+#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10)))
+#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15)))
+#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0)))
+#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1)))
+#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2)))
+#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4)))
+#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5)))
+#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6)))
+#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7)))
+#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23)))
+#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0)))
+#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1)))
+#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2)))
+#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3)))
+#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16)))
+#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17)))
+#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18)))
+#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5)))
+#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6)))
+#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7)))
+#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13)))
+#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14)))
+#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15)))
+#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31)))
+#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0)))
+#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1)))
+#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0)))
+#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1)))
+#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2)))
+#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3)))
+#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4)))
+
+#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7)))
+#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2)))
+#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3)))
+#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4)))
+#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5)))
+#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6)))
+#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8)))
+#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9)))
+#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10)))
+#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15)))
+#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0)))
+#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1)))
+#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2)))
+#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4)))
+#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5)))
+#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6)))
+#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7)))
+#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23)))
+#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0)))
+#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1)))
+#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2)))
+#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3)))
+#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16)))
+#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17)))
+#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18)))
+#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5)))
+#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6)))
+#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7)))
+#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13)))
+#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14)))
+#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15)))
+#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31)))
+#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0)))
+#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1)))
+#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0)))
+#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1)))
+#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2)))
+#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3)))
+#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4)))
+
+#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7)))
+#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2)))
+#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3)))
+#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4)))
+#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5)))
+#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6)))
+#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8)))
+#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9)))
+#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10)))
+#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15)))
+#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0)))
+#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1)))
+#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2)))
+#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4)))
+#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5)))
+#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6)))
+#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7)))
+#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23)))
+#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0)))
+#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1)))
+#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2)))
+#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3)))
+#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16)))
+#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17)))
+#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18)))
+#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5)))
+#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6)))
+#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7)))
+#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13)))
+#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14)))
+#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15)))
+#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31)))
+#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0)))
+#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1)))
+#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0)))
+#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1)))
+#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2)))
+#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3)))
+#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4)))
+
+#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7)))
+#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2)))
+#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3)))
+#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4)))
+#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5)))
+#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6)))
+#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8)))
+#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9)))
+#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10)))
+#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15)))
+#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0)))
+#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1)))
+#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2)))
+#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4)))
+#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5)))
+#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6)))
+#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7)))
+#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23)))
+#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0)))
+#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1)))
+#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2)))
+#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3)))
+#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16)))
+#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17)))
+#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18)))
+#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5)))
+#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6)))
+#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7)))
+#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13)))
+#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14)))
+#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15)))
+#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31)))
+#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0)))
+#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1)))
+#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0)))
+#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1)))
+#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2)))
+#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3)))
+#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4)))
+
+#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7)))
+#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2)))
+#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3)))
+#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4)))
+#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5)))
+#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6)))
+#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8)))
+#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9)))
+#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10)))
+#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15)))
+#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0)))
+#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1)))
+#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2)))
+#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4)))
+#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5)))
+#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6)))
+#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7)))
+#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23)))
+#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0)))
+#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1)))
+#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2)))
+#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3)))
+#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16)))
+#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17)))
+#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18)))
+#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5)))
+#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6)))
+#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7)))
+#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13)))
+#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14)))
+#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15)))
+#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31)))
+#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0)))
+#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1)))
+#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0)))
+#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1)))
+#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2)))
+#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3)))
+#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4)))
+
+#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7)))
+#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2)))
+#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3)))
+#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4)))
+#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5)))
+#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6)))
+#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8)))
+#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9)))
+#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10)))
+#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15)))
+#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0)))
+#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1)))
+#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2)))
+#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4)))
+#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5)))
+#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6)))
+#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7)))
+#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23)))
+#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0)))
+#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1)))
+#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2)))
+#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3)))
+#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16)))
+#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17)))
+#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18)))
+#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5)))
+#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6)))
+#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7)))
+#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13)))
+#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14)))
+#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15)))
+#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31)))
+#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0)))
+#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1)))
+#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0)))
+#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1)))
+#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2)))
+#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3)))
+#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4)))
+
+
+/* I2C */
+#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3)))
+#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4)))
+#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0)))
+#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3)))
+#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4)))
+#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5)))
+#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6)))
+#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7)))
+#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0)))
+#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1)))
+#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2)))
+#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3)))
+#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4)))
+#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5)))
+#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6)))
+#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7)))
+#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0)))
+#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1)))
+#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2)))
+#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3)))
+#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4)))
+#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5)))
+#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6)))
+#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0)))
+#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1)))
+#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2)))
+#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3)))
+#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0)))
+#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1)))
+#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2)))
+#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3)))
+#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4)))
+#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5)))
+#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6)))
+#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7)))
+#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0)))
+#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1)))
+#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0)))
+
+#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3)))
+#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4)))
+#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0)))
+#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3)))
+#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4)))
+#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5)))
+#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6)))
+#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7)))
+#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0)))
+#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1)))
+#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2)))
+#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3)))
+#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4)))
+#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5)))
+#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6)))
+#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7)))
+#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0)))
+#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1)))
+#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2)))
+#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3)))
+#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4)))
+#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5)))
+#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6)))
+#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0)))
+#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1)))
+#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2)))
+#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3)))
+#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0)))
+#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1)))
+#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2)))
+#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3)))
+#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4)))
+#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5)))
+#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6)))
+#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7)))
+#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0)))
+#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1)))
+#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0)))
+
+#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3)))
+#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4)))
+#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0)))
+#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3)))
+#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4)))
+#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5)))
+#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6)))
+#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7)))
+#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0)))
+#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1)))
+#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2)))
+#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3)))
+#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4)))
+#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5)))
+#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6)))
+#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7)))
+#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0)))
+#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1)))
+#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2)))
+#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3)))
+#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4)))
+#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5)))
+#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6)))
+#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0)))
+#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1)))
+#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2)))
+#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3)))
+#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0)))
+#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1)))
+#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2)))
+#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3)))
+#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4)))
+#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5)))
+#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6)))
+#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7)))
+#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0)))
+#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1)))
+#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0)))
+
+#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3)))
+#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4)))
+#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0)))
+#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3)))
+#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4)))
+#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5)))
+#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6)))
+#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7)))
+#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0)))
+#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1)))
+#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2)))
+#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3)))
+#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4)))
+#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5)))
+#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6)))
+#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7)))
+#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0)))
+#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1)))
+#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2)))
+#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3)))
+#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4)))
+#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5)))
+#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6)))
+#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0)))
+#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1)))
+#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2)))
+#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3)))
+#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0)))
+#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1)))
+#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2)))
+#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3)))
+#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4)))
+#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5)))
+#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6)))
+#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7)))
+#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0)))
+#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1)))
+#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0)))
+
+#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3)))
+#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4)))
+#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0)))
+#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3)))
+#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4)))
+#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5)))
+#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6)))
+#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7)))
+#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0)))
+#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1)))
+#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2)))
+#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3)))
+#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4)))
+#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5)))
+#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6)))
+#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7)))
+#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0)))
+#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1)))
+#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2)))
+#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3)))
+#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4)))
+#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5)))
+#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6)))
+#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0)))
+#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1)))
+#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2)))
+#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3)))
+#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0)))
+#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1)))
+#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2)))
+#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3)))
+#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4)))
+#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5)))
+#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6)))
+#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7)))
+#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0)))
+#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1)))
+#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0)))
+
+
+/* Port A */
+#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0)))
+#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1)))
+#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2)))
+#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3)))
+#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4)))
+#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5)))
+#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6)))
+#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7)))
+#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0)))
+#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1)))
+#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2)))
+#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3)))
+#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4)))
+#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5)))
+#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6)))
+#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7)))
+#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0)))
+#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1)))
+#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2)))
+#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3)))
+#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4)))
+#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5)))
+#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6)))
+#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7)))
+#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0)))
+#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3)))
+#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4)))
+#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7)))
+#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0)))
+#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1)))
+#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2)))
+#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3)))
+#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4)))
+#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5)))
+#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6)))
+#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7)))
+#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0)))
+#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1)))
+#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3)))
+#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4)))
+#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5)))
+#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7)))
+#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0)))
+#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3)))
+#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4)))
+#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5)))
+#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6)))
+#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7)))
+#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0)))
+#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1)))
+#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2)))
+#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3)))
+#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4)))
+#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5)))
+#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6)))
+#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7)))
+#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0)))
+#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1)))
+#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2)))
+#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3)))
+#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4)))
+#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5)))
+#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6)))
+#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7)))
+#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0)))
+#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1)))
+#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2)))
+#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3)))
+#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4)))
+#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5)))
+#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6)))
+#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7)))
+#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0)))
+#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1)))
+#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2)))
+#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3)))
+#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4)))
+#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5)))
+#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6)))
+#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7)))
+#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0)))
+#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1)))
+#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2)))
+#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3)))
+#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4)))
+#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5)))
+#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6)))
+#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7)))
+
+
+/* Port B */
+#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0)))
+#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1)))
+#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2)))
+#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3)))
+#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4)))
+#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5)))
+#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6)))
+#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7)))
+#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0)))
+#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1)))
+#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2)))
+#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3)))
+#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4)))
+#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5)))
+#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6)))
+#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7)))
+#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1)))
+#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2)))
+#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3)))
+#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4)))
+#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5)))
+#define TSB_PB_FR1_PB6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6)))
+#define TSB_PB_FR1_PB7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,7)))
+#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0)))
+#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1)))
+#define TSB_PB_FR2_PB6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6)))
+#define TSB_PB_FR2_PB7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,7)))
+#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0)))
+#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1)))
+#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2)))
+#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3)))
+#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4)))
+#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5)))
+#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6)))
+#define TSB_PB_FR3_PB7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,7)))
+#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0)))
+#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1)))
+#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2)))
+#define TSB_PB_FR5_PB4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4)))
+#define TSB_PB_FR5_PB6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6)))
+#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7)))
+#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1)))
+#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0)))
+#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1)))
+#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2)))
+#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3)))
+#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4)))
+#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5)))
+#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6)))
+#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7)))
+#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0)))
+#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1)))
+#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2)))
+#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3)))
+#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4)))
+#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5)))
+#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6)))
+#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7)))
+#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0)))
+#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1)))
+#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2)))
+#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3)))
+#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4)))
+#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5)))
+#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6)))
+#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7)))
+#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0)))
+#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1)))
+#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2)))
+#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3)))
+#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4)))
+#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5)))
+#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6)))
+#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7)))
+
+
+/* Port C */
+#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0)))
+#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1)))
+#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2)))
+#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3)))
+#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4)))
+#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5)))
+#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6)))
+#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7)))
+#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0)))
+#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1)))
+#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2)))
+#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3)))
+#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4)))
+#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5)))
+#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6)))
+#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7)))
+#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1)))
+#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2)))
+#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3)))
+#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4)))
+#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5)))
+#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6)))
+#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7)))
+#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1)))
+#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2)))
+#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3)))
+#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4)))
+#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5)))
+#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1)))
+#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2)))
+#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4)))
+#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0)))
+#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1)))
+#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2)))
+#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3)))
+#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4)))
+#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5)))
+#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6)))
+#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7)))
+#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0)))
+#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1)))
+#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2)))
+#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3)))
+#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4)))
+#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5)))
+#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6)))
+#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7)))
+#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0)))
+#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1)))
+#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2)))
+#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3)))
+#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4)))
+#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5)))
+#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6)))
+#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7)))
+#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0)))
+#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1)))
+#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2)))
+#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3)))
+#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4)))
+#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5)))
+#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6)))
+#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7)))
+
+
+/* Port D */
+#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0)))
+#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1)))
+#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2)))
+#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3)))
+#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4)))
+#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5)))
+#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6)))
+#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7)))
+#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0)))
+#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1)))
+#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2)))
+#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3)))
+#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4)))
+#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5)))
+#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6)))
+#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7)))
+#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1)))
+#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2)))
+#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3)))
+#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4)))
+#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5)))
+#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6)))
+#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7)))
+#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0)))
+#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1)))
+#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6)))
+#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7)))
+#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0)))
+#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1)))
+#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2)))
+#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3)))
+#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4)))
+#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5)))
+#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6)))
+#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7)))
+#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0)))
+#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1)))
+#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2)))
+#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3)))
+#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0)))
+#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1)))
+#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2)))
+#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4)))
+#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6)))
+#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7)))
+#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0)))
+#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0)))
+#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1)))
+#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2)))
+#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3)))
+#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4)))
+#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5)))
+#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6)))
+#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7)))
+#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0)))
+#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1)))
+#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2)))
+#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3)))
+#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4)))
+#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5)))
+#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6)))
+#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7)))
+#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0)))
+#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1)))
+#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2)))
+#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3)))
+#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4)))
+#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5)))
+#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6)))
+#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7)))
+#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0)))
+#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1)))
+#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2)))
+#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3)))
+#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4)))
+#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5)))
+#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6)))
+#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7)))
+#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0)))
+#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1)))
+#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2)))
+#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3)))
+#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4)))
+#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5)))
+#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6)))
+#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7)))
+
+
+/* Port E */
+#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0)))
+#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1)))
+#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2)))
+#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3)))
+#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4)))
+#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5)))
+#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6)))
+#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7)))
+#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0)))
+#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1)))
+#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2)))
+#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3)))
+#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4)))
+#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5)))
+#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6)))
+#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7)))
+#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0)))
+#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1)))
+#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2)))
+#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3)))
+#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4)))
+#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5)))
+#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6)))
+#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7)))
+#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0)))
+#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7)))
+#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0)))
+#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1)))
+#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2)))
+#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3)))
+#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4)))
+#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5)))
+#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6)))
+#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7)))
+#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0)))
+#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1)))
+#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2)))
+#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3)))
+#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4)))
+#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5)))
+#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6)))
+#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7)))
+#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0)))
+#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1)))
+#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2)))
+#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3)))
+#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4)))
+#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5)))
+#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6)))
+#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7)))
+#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0)))
+#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1)))
+#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2)))
+#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3)))
+#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0)))
+#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1)))
+#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2)))
+#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3)))
+#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4)))
+#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5)))
+#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6)))
+#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7)))
+#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0)))
+#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1)))
+#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2)))
+#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3)))
+#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4)))
+#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5)))
+#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6)))
+#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7)))
+#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0)))
+#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1)))
+#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2)))
+#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3)))
+#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4)))
+#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5)))
+#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6)))
+#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7)))
+#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0)))
+#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1)))
+#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2)))
+#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3)))
+#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4)))
+#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5)))
+#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6)))
+#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7)))
+
+
+/* Port F */
+#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0)))
+#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1)))
+#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2)))
+#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3)))
+#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4)))
+#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5)))
+#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6)))
+#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7)))
+#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0)))
+#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1)))
+#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2)))
+#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3)))
+#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4)))
+#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5)))
+#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6)))
+#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7)))
+#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0)))
+#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1)))
+#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4)))
+#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5)))
+#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6)))
+#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7)))
+#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2)))
+#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3)))
+#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0)))
+#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1)))
+#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2)))
+#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3)))
+#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4)))
+#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5)))
+#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6)))
+#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7)))
+#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0)))
+#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1)))
+#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2)))
+#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3)))
+#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4)))
+#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5)))
+#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6)))
+#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7)))
+#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0)))
+#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1)))
+#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2)))
+#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3)))
+#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4)))
+#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5)))
+#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6)))
+#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7)))
+#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0)))
+#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1)))
+#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2)))
+#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3)))
+#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4)))
+#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5)))
+#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6)))
+#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7)))
+
+
+/* Port G */
+#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0)))
+#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1)))
+#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2)))
+#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3)))
+#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4)))
+#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5)))
+#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6)))
+#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7)))
+#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0)))
+#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1)))
+#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2)))
+#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3)))
+#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4)))
+#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5)))
+#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6)))
+#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7)))
+#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0)))
+#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1)))
+#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6)))
+#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7)))
+#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4)))
+#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5)))
+#define TSB_PG_FR3_PG0F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0)))
+#define TSB_PG_FR3_PG1F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1)))
+#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2)))
+#define TSB_PG_FR3_PG3F3 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3)))
+#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5)))
+#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2)))
+#define TSB_PG_FR4_PG3F4 (*((__I uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3)))
+#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4)))
+#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5)))
+#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6)))
+#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7)))
+#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0)))
+#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1)))
+#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2)))
+#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3)))
+#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4)))
+#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5)))
+#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6)))
+#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7)))
+#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2)))
+#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3)))
+#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4)))
+#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5)))
+#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0)))
+#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1)))
+#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2)))
+#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3)))
+#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4)))
+#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5)))
+#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6)))
+#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7)))
+#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0)))
+#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1)))
+#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2)))
+#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3)))
+#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4)))
+#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5)))
+#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6)))
+#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7)))
+#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0)))
+#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1)))
+#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2)))
+#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3)))
+#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4)))
+#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5)))
+#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6)))
+#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7)))
+#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0)))
+#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1)))
+#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2)))
+#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3)))
+#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4)))
+#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5)))
+#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6)))
+#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7)))
+
+
+/* Port H */
+#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0)))
+#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1)))
+#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2)))
+#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3)))
+#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4)))
+#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5)))
+#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6)))
+#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7)))
+#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0)))
+#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1)))
+#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2)))
+#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3)))
+#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4)))
+#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5)))
+#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6)))
+#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7)))
+#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0)))
+#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1)))
+#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2)))
+#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3)))
+#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4)))
+#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5)))
+#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6)))
+#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7)))
+#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0)))
+#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1)))
+#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2)))
+#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3)))
+#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4)))
+#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5)))
+#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6)))
+#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7)))
+#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0)))
+#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1)))
+#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2)))
+#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3)))
+#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0)))
+#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1)))
+#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2)))
+#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3)))
+#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4)))
+#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5)))
+#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6)))
+#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7)))
+#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0)))
+#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1)))
+#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2)))
+#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3)))
+#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4)))
+#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5)))
+#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6)))
+#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7)))
+#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0)))
+#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1)))
+#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2)))
+#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3)))
+#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4)))
+#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5)))
+#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6)))
+#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7)))
+#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0)))
+#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1)))
+#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2)))
+#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3)))
+#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4)))
+#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5)))
+#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6)))
+#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7)))
+#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0)))
+#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1)))
+#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2)))
+#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3)))
+#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4)))
+#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5)))
+#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6)))
+#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7)))
+
+
+/* Port J */
+#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0)))
+#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1)))
+#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2)))
+#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3)))
+#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4)))
+#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5)))
+#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6)))
+#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7)))
+#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0)))
+#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1)))
+#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2)))
+#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3)))
+#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4)))
+#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5)))
+#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6)))
+#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7)))
+#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4)))
+#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5)))
+#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0)))
+#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1)))
+#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2)))
+#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3)))
+#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4)))
+#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5)))
+#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0)))
+#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1)))
+#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2)))
+#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3)))
+#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4)))
+#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5)))
+#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6)))
+#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7)))
+#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2)))
+#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3)))
+#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6)))
+#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7)))
+#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0)))
+#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1)))
+#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2)))
+#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3)))
+#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4)))
+#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5)))
+#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6)))
+#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7)))
+#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0)))
+#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1)))
+#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2)))
+#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3)))
+#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4)))
+#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5)))
+#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6)))
+#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7)))
+#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0)))
+#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1)))
+#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2)))
+#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3)))
+#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4)))
+#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5)))
+#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6)))
+#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7)))
+#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0)))
+#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1)))
+#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2)))
+#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3)))
+#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4)))
+#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5)))
+#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6)))
+#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7)))
+
+
+/* Port K */
+#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0)))
+#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1)))
+#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2)))
+#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3)))
+#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4)))
+#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5)))
+#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6)))
+#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7)))
+#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0)))
+#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1)))
+#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2)))
+#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3)))
+#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4)))
+#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5)))
+#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6)))
+#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7)))
+#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0)))
+#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1)))
+#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2)))
+#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3)))
+#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4)))
+#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5)))
+#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0)))
+#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1)))
+#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6)))
+#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7)))
+#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0)))
+#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1)))
+#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6)))
+#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7)))
+#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1)))
+#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4)))
+#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5)))
+#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6)))
+#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7)))
+#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2)))
+#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3)))
+#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4)))
+#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5)))
+#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6)))
+#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7)))
+#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7)))
+#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0)))
+#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1)))
+#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2)))
+#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3)))
+#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4)))
+#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5)))
+#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6)))
+#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7)))
+#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0)))
+#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1)))
+#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2)))
+#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3)))
+#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4)))
+#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5)))
+#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6)))
+#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7)))
+#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0)))
+#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1)))
+#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2)))
+#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3)))
+#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4)))
+#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5)))
+#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6)))
+#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7)))
+#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0)))
+#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1)))
+#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2)))
+#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3)))
+#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4)))
+#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5)))
+#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6)))
+#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7)))
+
+
+/* Port L */
+#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0)))
+#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1)))
+#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2)))
+#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3)))
+#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4)))
+#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5)))
+#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6)))
+#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7)))
+#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0)))
+#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1)))
+#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2)))
+#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3)))
+#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4)))
+#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5)))
+#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6)))
+#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7)))
+#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7)))
+#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0)))
+#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3)))
+#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4)))
+#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5)))
+#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6)))
+#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7)))
+#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0)))
+#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3)))
+#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4)))
+#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6)))
+#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0)))
+#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3)))
+#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0)))
+#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1)))
+#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2)))
+#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3)))
+#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0)))
+#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1)))
+#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2)))
+#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3)))
+#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4)))
+#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5)))
+#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6)))
+#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7)))
+#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0)))
+#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1)))
+#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2)))
+#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3)))
+#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4)))
+#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5)))
+#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6)))
+#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7)))
+#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0)))
+#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1)))
+#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2)))
+#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3)))
+#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4)))
+#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5)))
+#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6)))
+#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7)))
+#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0)))
+#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1)))
+#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2)))
+#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3)))
+#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4)))
+#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5)))
+#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6)))
+#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7)))
+
+
+/* Port M */
+#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0)))
+#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1)))
+#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2)))
+#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3)))
+#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4)))
+#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5)))
+#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6)))
+#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7)))
+#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0)))
+#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1)))
+#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2)))
+#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3)))
+#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4)))
+#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5)))
+#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6)))
+#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7)))
+#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2)))
+#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3)))
+#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4)))
+#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5)))
+#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6)))
+#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7)))
+#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2)))
+#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5)))
+#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6)))
+#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0)))
+#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1)))
+#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3)))
+#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4)))
+#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6)))
+#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7)))
+#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0)))
+#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1)))
+#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2)))
+#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3)))
+#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6)))
+#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7)))
+#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0)))
+#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1)))
+#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2)))
+#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3)))
+#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4)))
+#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5)))
+#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6)))
+#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7)))
+#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0)))
+#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1)))
+#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2)))
+#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3)))
+#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4)))
+#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5)))
+#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6)))
+#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7)))
+#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0)))
+#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1)))
+#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2)))
+#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3)))
+#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4)))
+#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5)))
+#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6)))
+#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7)))
+#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0)))
+#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1)))
+#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2)))
+#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3)))
+#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4)))
+#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5)))
+#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6)))
+#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7)))
+#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0)))
+#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1)))
+#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2)))
+#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3)))
+#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4)))
+#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5)))
+#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6)))
+#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7)))
+#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0)))
+#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1)))
+#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2)))
+#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3)))
+#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4)))
+#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5)))
+#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6)))
+#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7)))
+
+
+/* Port N */
+#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0)))
+#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1)))
+#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2)))
+#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3)))
+#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4)))
+#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5)))
+#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6)))
+#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7)))
+#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0)))
+#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1)))
+#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2)))
+#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3)))
+#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4)))
+#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5)))
+#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6)))
+#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7)))
+#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0)))
+#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1)))
+#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2)))
+#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3)))
+#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4)))
+#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5)))
+#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6)))
+#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7)))
+#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0)))
+#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1)))
+#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2)))
+#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3)))
+#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4)))
+#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5)))
+#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6)))
+#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7)))
+#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0)))
+#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1)))
+#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2)))
+#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3)))
+#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4)))
+#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5)))
+#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6)))
+#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7)))
+#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0)))
+#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1)))
+#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2)))
+#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3)))
+#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4)))
+#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5)))
+#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6)))
+#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7)))
+
+
+/* Port P */
+#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0)))
+#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1)))
+#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2)))
+#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3)))
+#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4)))
+#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5)))
+#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6)))
+#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7)))
+#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0)))
+#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1)))
+#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2)))
+#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3)))
+#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4)))
+#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5)))
+#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6)))
+#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7)))
+#define TSB_PP_FR2_PP0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0)))
+#define TSB_PP_FR2_PP1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1)))
+#define TSB_PP_FR2_PP2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2)))
+#define TSB_PP_FR2_PP3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3)))
+#define TSB_PP_FR2_PP4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4)))
+#define TSB_PP_FR2_PP5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5)))
+#define TSB_PP_FR2_PP6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6)))
+#define TSB_PP_FR2_PP7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7)))
+#define TSB_PP_FR3_PP0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0)))
+#define TSB_PP_FR3_PP1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1)))
+#define TSB_PP_FR3_PP2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2)))
+#define TSB_PP_FR3_PP3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3)))
+#define TSB_PP_FR3_PP4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4)))
+#define TSB_PP_FR3_PP5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5)))
+#define TSB_PP_FR3_PP6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6)))
+#define TSB_PP_FR3_PP7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7)))
+#define TSB_PP_FR5_PP0FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0)))
+#define TSB_PP_FR5_PP1FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1)))
+#define TSB_PP_FR5_PP2FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2)))
+#define TSB_PP_FR5_PP3FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3)))
+#define TSB_PP_FR5_PP4FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4)))
+#define TSB_PP_FR5_PP5FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5)))
+#define TSB_PP_FR5_PP6FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6)))
+#define TSB_PP_FR5_PP7FR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7)))
+#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0)))
+#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1)))
+#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2)))
+#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3)))
+#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4)))
+#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5)))
+#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6)))
+#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7)))
+#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0)))
+#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1)))
+#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2)))
+#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3)))
+#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4)))
+#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5)))
+#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6)))
+#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7)))
+#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0)))
+#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1)))
+#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2)))
+#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3)))
+#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4)))
+#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5)))
+#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6)))
+#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7)))
+#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0)))
+#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1)))
+#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2)))
+#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3)))
+#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4)))
+#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5)))
+#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6)))
+#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7)))
+
+
+/* Port R */
+#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0)))
+#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1)))
+#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2)))
+#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3)))
+#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4)))
+#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5)))
+#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6)))
+#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7)))
+#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0)))
+#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1)))
+#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2)))
+#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3)))
+#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4)))
+#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5)))
+#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6)))
+#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7)))
+#define TSB_PR_FR2_PR0FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0)))
+#define TSB_PR_FR2_PR1FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1)))
+#define TSB_PR_FR2_PR2FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2)))
+#define TSB_PR_FR2_PR3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3)))
+#define TSB_PR_FR2_PR4FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4)))
+#define TSB_PR_FR2_PR5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5)))
+#define TSB_PR_FR2_PR6FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6)))
+#define TSB_PR_FR2_PR7FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7)))
+#define TSB_PR_FR3_PR0FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0)))
+#define TSB_PR_FR3_PR1FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1)))
+#define TSB_PR_FR3_PR2FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2)))
+#define TSB_PR_FR3_PR3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3)))
+#define TSB_PR_FR3_PR4FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4)))
+#define TSB_PR_FR3_PR5FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5)))
+#define TSB_PR_FR3_PR6FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6)))
+#define TSB_PR_FR3_PR7FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7)))
+#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0)))
+#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1)))
+#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2)))
+#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3)))
+#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4)))
+#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5)))
+#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6)))
+#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7)))
+#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0)))
+#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1)))
+#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2)))
+#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3)))
+#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4)))
+#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5)))
+#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6)))
+#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7)))
+#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0)))
+#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1)))
+#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2)))
+#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3)))
+#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4)))
+#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5)))
+#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6)))
+#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7)))
+#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0)))
+#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1)))
+#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2)))
+#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3)))
+#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4)))
+#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5)))
+#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6)))
+#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7)))
+
+
+/* Port T */
+#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0)))
+#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1)))
+#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2)))
+#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3)))
+#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4)))
+#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5)))
+#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0)))
+#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1)))
+#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2)))
+#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3)))
+#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4)))
+#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5)))
+#define TSB_PT_FR1_PT3FR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3)))
+#define TSB_PT_FR2_PT3FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3)))
+#define TSB_PT_FR2_PT5FR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5)))
+#define TSB_PT_FR3_PT3FR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3)))
+#define TSB_PT_FR6_PT3FR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3)))
+#define TSB_PT_FR7_PT2FR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2)))
+#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0)))
+#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1)))
+#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2)))
+#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3)))
+#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4)))
+#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5)))
+#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0)))
+#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1)))
+#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2)))
+#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3)))
+#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4)))
+#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5)))
+#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0)))
+#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1)))
+#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2)))
+#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3)))
+#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4)))
+#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5)))
+#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0)))
+#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1)))
+#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2)))
+#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3)))
+#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4)))
+#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5)))
+
+
+/* Port U */
+#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0)))
+#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1)))
+#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2)))
+#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3)))
+#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4)))
+#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5)))
+#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6)))
+#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7)))
+#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0)))
+#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1)))
+#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2)))
+#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3)))
+#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4)))
+#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5)))
+#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6)))
+#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7)))
+#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0)))
+#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1)))
+#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2)))
+#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3)))
+#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4)))
+#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5)))
+#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6)))
+#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7)))
+#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0)))
+#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2)))
+#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3)))
+#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4)))
+#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5)))
+#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6)))
+#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0)))
+#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1)))
+#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2)))
+#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3)))
+#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4)))
+#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5)))
+#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6)))
+#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7)))
+#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0)))
+#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1)))
+#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2)))
+#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3)))
+#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4)))
+#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5)))
+#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6)))
+#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7)))
+#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0)))
+#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1)))
+#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2)))
+#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3)))
+#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4)))
+#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5)))
+#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6)))
+#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7)))
+#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0)))
+#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1)))
+#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2)))
+#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3)))
+#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4)))
+#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5)))
+#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6)))
+#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7)))
+#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0)))
+#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1)))
+#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2)))
+#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3)))
+#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4)))
+#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5)))
+#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6)))
+#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7)))
+
+
+/* Port V */
+#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0)))
+#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1)))
+#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2)))
+#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3)))
+#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4)))
+#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5)))
+#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6)))
+#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7)))
+#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0)))
+#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1)))
+#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2)))
+#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3)))
+#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4)))
+#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5)))
+#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6)))
+#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7)))
+#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0)))
+#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1)))
+#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2)))
+#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3)))
+#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4)))
+#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5)))
+#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6)))
+#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7)))
+#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0)))
+#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1)))
+#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2)))
+#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5)))
+#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6)))
+#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4)))
+#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5)))
+#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6)))
+#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7)))
+#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0)))
+#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1)))
+#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2)))
+#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3)))
+#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4)))
+#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5)))
+#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6)))
+#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7)))
+#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0)))
+#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1)))
+#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2)))
+#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3)))
+#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4)))
+#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5)))
+#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7)))
+#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0)))
+#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1)))
+#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2)))
+#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3)))
+#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4)))
+#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5)))
+#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6)))
+#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7)))
+#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0)))
+#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1)))
+#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2)))
+#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3)))
+#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4)))
+#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5)))
+#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6)))
+#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7)))
+#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0)))
+#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1)))
+#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2)))
+#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3)))
+#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4)))
+#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5)))
+#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6)))
+#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7)))
+#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0)))
+#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1)))
+#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2)))
+#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3)))
+#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4)))
+#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5)))
+#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6)))
+#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7)))
+#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0)))
+#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1)))
+#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2)))
+#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3)))
+#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4)))
+#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5)))
+#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6)))
+#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7)))
+
+
+/* Port W */
+#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0)))
+#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1)))
+#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2)))
+#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3)))
+#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4)))
+#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5)))
+#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6)))
+#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7)))
+#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0)))
+#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1)))
+#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2)))
+#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3)))
+#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4)))
+#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5)))
+#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6)))
+#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7)))
+#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4)))
+#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7)))
+#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0)))
+#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1)))
+#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2)))
+#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3)))
+#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0)))
+#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1)))
+#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2)))
+#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3)))
+#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4)))
+#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5)))
+#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6)))
+#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7)))
+#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0)))
+#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1)))
+#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2)))
+#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4)))
+#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5)))
+#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6)))
+#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7)))
+#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0)))
+#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1)))
+#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2)))
+#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3)))
+#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4)))
+#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5)))
+#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6)))
+#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7)))
+#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0)))
+#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1)))
+#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2)))
+#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3)))
+#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4)))
+#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5)))
+#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6)))
+#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7)))
+#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0)))
+#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1)))
+#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2)))
+#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3)))
+#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4)))
+#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5)))
+#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6)))
+#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7)))
+#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0)))
+#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1)))
+#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2)))
+#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3)))
+#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4)))
+#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5)))
+#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6)))
+#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7)))
+
+
+/* Port Y */
+#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0)))
+#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1)))
+#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2)))
+#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3)))
+#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4)))
+#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4)))
+#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4)))
+#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4)))
+#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4)))
+#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0)))
+#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1)))
+#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2)))
+#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3)))
+#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4)))
+#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0)))
+#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1)))
+#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2)))
+#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3)))
+#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4)))
+#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0)))
+#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1)))
+#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2)))
+#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3)))
+#define TSB_PY_IE_PY4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,4)))
+
+
+/* Internal High-speed Oscillation Adjustment */
+#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0)))
+
+
+/* Oscillation Frequency Detector (OFD) */
+#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0)))
+#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0)))
+#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1)))
+#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0)))
+
+
+
+/* Consumer Electronics Control (CEC) */
+#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0)))
+#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0)))
+#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0)))
+#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8)))
+#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9)))
+#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0)))
+#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1)))
+#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24)))
+#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0)))
+#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1)))
+#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0)))
+#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1)))
+#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8)))
+#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4)))
+#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0)))
+#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1)))
+#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2)))
+#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3)))
+#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4)))
+#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5)))
+#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6)))
+#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0)))
+#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1)))
+#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2)))
+#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3)))
+#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4)))
+#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0)))
+
+
+/* Remote Control Signal Preprocessor (RMC) */
+#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0)))
+#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0)))
+#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24)))
+#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25)))
+#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29)))
+#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30)))
+#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31)))
+#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15)))
+#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7)))
+#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7)))
+#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8)))
+#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11)))
+#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12)))
+#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13)))
+#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14)))
+#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15)))
+#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0)))
+
+#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0)))
+#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0)))
+#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24)))
+#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25)))
+#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29)))
+#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30)))
+#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31)))
+#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15)))
+#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7)))
+#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7)))
+#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8)))
+#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11)))
+#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12)))
+#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13)))
+#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14)))
+#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15)))
+#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0)))
+
+
+/* */
+#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0)))
+#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3)))
+#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4)))
+#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5)))
+#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6)))
+#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7)))
+#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0)))
+#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1)))
+#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2)))
+#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0)))
+#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1)))
+#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2)))
+#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3)))
+#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7)))
+#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8)))
+#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9)))
+#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10)))
+#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2)))
+#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3)))
+#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0)))
+#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1)))
+#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2)))
+#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5)))
+#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7)))
+#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13)))
+#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14)))
+#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15)))
+#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0)))
+#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1)))
+#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0)))
+#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1)))
+#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2)))
+#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5)))
+#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6)))
+#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7)))
+#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15)))
+#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0)))
+#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1)))
+#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3)))
+#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7)))
+#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11)))
+#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15)))
+#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16)))
+#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0)))
+#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1)))
+#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0)))
+
+
+/* */
+#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0)))
+#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0)))
+#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1)))
+#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0)))
+#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0)))
+#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0)))
+#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1)))
+#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2)))
+#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3)))
+#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0)))
+#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1)))
+#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2)))
+#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3)))
+#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0)))
+
+#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0)))
+#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0)))
+#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1)))
+#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0)))
+#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0)))
+#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0)))
+#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1)))
+#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2)))
+#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3)))
+#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0)))
+#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1)))
+#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2)))
+#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3)))
+#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0)))
+
+#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0)))
+#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0)))
+#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1)))
+#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0)))
+#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0)))
+#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0)))
+#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1)))
+#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2)))
+#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3)))
+#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0)))
+#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1)))
+#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2)))
+#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3)))
+#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0)))
+
+/** @} */ /* End of group Device_Peripheral_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TMPM4G9_H__ */
+
+/** @} */ /* End of group TMPM4G9 */
+/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_ARM_STD/startup_TMPM4G9.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,534 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4G9.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4G9' Device Series +; * @version V1.0.6.0 +; * $Date:: 2017-10-04 #$ +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ + +__initial_sp EQU 0x20030000 + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b + DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b + DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b + DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt + DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) + DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) + DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) + DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) + DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) + DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 + DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 + DCD INTLTTMR_IRQHandler ; 24: Long Term Timer Interrupt + DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) + DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) + DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) + DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) + DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) + DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A00_B_C01_CPC_IRQHandler ; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A01_B_C01_CPC_IRQHandler ; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A02_B_C01_CPC_IRQHandler ; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A03_B_C01_CPC_IRQHandler ; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A04_B_C01_CPC_IRQHandler ; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A05_B_C01_CPC_IRQHandler ; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A06_B_C01_CPC_IRQHandler ; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A07_B_C01_CPC_IRQHandler ; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A08_B_C01_CPC_IRQHandler ; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A09_B_C01_CPC_IRQHandler ; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A10_B_C01_CPC_IRQHandler ; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A11_B_C01_CPC_IRQHandler ; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A12_B_C01_CPC_IRQHandler ; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A13_B_C01_CPC_IRQHandler ; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt + DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt + DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) + DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) + DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) + DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) + DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) + DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) + DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) + DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) + DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) + DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) + DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) + DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) + DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) + DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) + DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) + DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) + DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) + DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) + DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) + DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) + DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) + DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) + DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt + DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) + DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) + DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) + DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) + DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) + DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) + DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) + DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) + DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) + DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) + DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) + DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) + DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt + DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt + DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt + DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt + DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt + DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt + DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt + DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt + DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt + DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt + DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt + DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt + DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished + DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt + DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt + DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt + DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt + DCD 0 ; 138: Reserved + DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) + DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTCEC0RX_IRQHandler [WEAK] + EXPORT INTCEC0TX_IRQHandler [WEAK] + EXPORT INTISDA_IRQHandler [WEAK] + EXPORT INTISDB_IRQHandler [WEAK] + EXPORT INTISDC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTRMC1_IRQHandler [WEAK] + EXPORT INTLTTMR_IRQHandler [WEAK] + EXPORT INTHDMAATC_IRQHandler [WEAK] + EXPORT INTHDMAAERR_IRQHandler [WEAK] + EXPORT INTHDMABTC_IRQHandler [WEAK] + EXPORT INTHDMABERR_IRQHandler [WEAK] + EXPORT INTMDMAATC_IRQHandler [WEAK] + EXPORT INTT32A00_A_CT_IRQHandler [WEAK] + EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A01_A_CT_IRQHandler [WEAK] + EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A02_A_CT_IRQHandler [WEAK] + EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A03_A_CT_IRQHandler [WEAK] + EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A04_A_CT_IRQHandler [WEAK] + EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A05_A_CT_IRQHandler [WEAK] + EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A06_A_CT_IRQHandler [WEAK] + EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A07_A_CT_IRQHandler [WEAK] + EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A08_A_CT_IRQHandler [WEAK] + EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A09_A_CT_IRQHandler [WEAK] + EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A10_A_CT_IRQHandler [WEAK] + EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A11_A_CT_IRQHandler [WEAK] + EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A12_A_CT_IRQHandler [WEAK] + EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A13_A_CT_IRQHandler [WEAK] + EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTT2RX_IRQHandler [WEAK] + EXPORT INTT2TX_IRQHandler [WEAK] + EXPORT INTT2ERR_IRQHandler [WEAK] + EXPORT INTT3RX_IRQHandler [WEAK] + EXPORT INTT3TX_IRQHandler [WEAK] + EXPORT INTT3ERR_IRQHandler [WEAK] + EXPORT INTT4RX_IRQHandler [WEAK] + EXPORT INTT4TX_IRQHandler [WEAK] + EXPORT INTT4ERR_IRQHandler [WEAK] + EXPORT INTT5RX_IRQHandler [WEAK] + EXPORT INTT5TX_IRQHandler [WEAK] + EXPORT INTT5ERR_IRQHandler [WEAK] + EXPORT INTT6RX_IRQHandler [WEAK] + EXPORT INTT6TX_IRQHandler [WEAK] + EXPORT INTT6ERR_IRQHandler [WEAK] + EXPORT INTT7RX_IRQHandler [WEAK] + EXPORT INTT7TX_IRQHandler [WEAK] + EXPORT INTT7ERR_IRQHandler [WEAK] + EXPORT INTT8RX_IRQHandler [WEAK] + EXPORT INTT8TX_IRQHandler [WEAK] + EXPORT INTT8ERR_IRQHandler [WEAK] + EXPORT INTSMI0_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTUART3RX_IRQHandler [WEAK] + EXPORT INTUART3TX_IRQHandler [WEAK] + EXPORT INTUART3ERR_IRQHandler [WEAK] + EXPORT INTUART4RX_IRQHandler [WEAK] + EXPORT INTUART4TX_IRQHandler [WEAK] + EXPORT INTUART4ERR_IRQHandler [WEAK] + EXPORT INTUART5RX_IRQHandler [WEAK] + EXPORT INTUART5TX_IRQHandler [WEAK] + EXPORT INTUART5ERR_IRQHandler [WEAK] + EXPORT INTFUART0_IRQHandler [WEAK] + EXPORT INTFUART1_IRQHandler [WEAK] + EXPORT INTI2C0_IRQHandler [WEAK] + EXPORT INTI2C0AL_IRQHandler [WEAK] + EXPORT INTI2C0BF_IRQHandler [WEAK] + EXPORT INTI2C0NACK_IRQHandler [WEAK] + EXPORT INTI2C1_IRQHandler [WEAK] + EXPORT INTI2C1AL_IRQHandler [WEAK] + EXPORT INTI2C1BF_IRQHandler [WEAK] + EXPORT INTI2C1NACK_IRQHandler [WEAK] + EXPORT INTI2C2_IRQHandler [WEAK] + EXPORT INTI2C2AL_IRQHandler [WEAK] + EXPORT INTI2C2BF_IRQHandler [WEAK] + EXPORT INTI2C2NACK_IRQHandler [WEAK] + EXPORT INTI2C3_IRQHandler [WEAK] + EXPORT INTI2C3AL_IRQHandler [WEAK] + EXPORT INTI2C3BF_IRQHandler [WEAK] + EXPORT INTI2C3NACK_IRQHandler [WEAK] + EXPORT INTI2C4_IRQHandler [WEAK] + EXPORT INTI2C4AL_IRQHandler [WEAK] + EXPORT INTI2C4BF_IRQHandler [WEAK] + EXPORT INTI2C4NACK_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADAHP_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + EXPORT INTFLCRDY0_IRQHandler [WEAK] + EXPORT INTFLCRDY1_IRQHandler [WEAK] + EXPORT INTMDMAABERR_IRQHandler [WEAK] + EXPORT INTMDMAADERR_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INTRTC_IRQHandler +INTCEC0RX_IRQHandler +INTCEC0TX_IRQHandler +INTISDA_IRQHandler +INTISDB_IRQHandler +INTISDC_IRQHandler +INTRMC0_IRQHandler +INTRMC1_IRQHandler +INTLTTMR_IRQHandler +INTHDMAATC_IRQHandler +INTHDMAAERR_IRQHandler +INTHDMABTC_IRQHandler +INTHDMABERR_IRQHandler +INTMDMAATC_IRQHandler +INTT32A00_A_CT_IRQHandler +INTT32A00_B_C01_CPC_IRQHandler +INTT32A01_A_CT_IRQHandler +INTT32A01_B_C01_CPC_IRQHandler +INTT32A02_A_CT_IRQHandler +INTT32A02_B_C01_CPC_IRQHandler +INTT32A03_A_CT_IRQHandler +INTT32A03_B_C01_CPC_IRQHandler +INTT32A04_A_CT_IRQHandler +INTT32A04_B_C01_CPC_IRQHandler +INTT32A05_A_CT_IRQHandler +INTT32A05_B_C01_CPC_IRQHandler +INTT32A06_A_CT_IRQHandler +INTT32A06_B_C01_CPC_IRQHandler +INTT32A07_A_CT_IRQHandler +INTT32A07_B_C01_CPC_IRQHandler +INTT32A08_A_CT_IRQHandler +INTT32A08_B_C01_CPC_IRQHandler +INTT32A09_A_CT_IRQHandler +INTT32A09_B_C01_CPC_IRQHandler +INTT32A10_A_CT_IRQHandler +INTT32A10_B_C01_CPC_IRQHandler +INTT32A11_A_CT_IRQHandler +INTT32A11_B_C01_CPC_IRQHandler +INTT32A12_A_CT_IRQHandler +INTT32A12_B_C01_CPC_IRQHandler +INTT32A13_A_CT_IRQHandler +INTT32A13_B_C01_CPC_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPWM0_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTT2RX_IRQHandler +INTT2TX_IRQHandler +INTT2ERR_IRQHandler +INTT3RX_IRQHandler +INTT3TX_IRQHandler +INTT3ERR_IRQHandler +INTT4RX_IRQHandler +INTT4TX_IRQHandler +INTT4ERR_IRQHandler +INTT5RX_IRQHandler +INTT5TX_IRQHandler +INTT5ERR_IRQHandler +INTT6RX_IRQHandler +INTT6TX_IRQHandler +INTT6ERR_IRQHandler +INTT7RX_IRQHandler +INTT7TX_IRQHandler +INTT7ERR_IRQHandler +INTT8RX_IRQHandler +INTT8TX_IRQHandler +INTT8ERR_IRQHandler +INTSMI0_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTUART3RX_IRQHandler +INTUART3TX_IRQHandler +INTUART3ERR_IRQHandler +INTUART4RX_IRQHandler +INTUART4TX_IRQHandler +INTUART4ERR_IRQHandler +INTUART5RX_IRQHandler +INTUART5TX_IRQHandler +INTUART5ERR_IRQHandler +INTFUART0_IRQHandler +INTFUART1_IRQHandler +INTI2C0_IRQHandler +INTI2C0AL_IRQHandler +INTI2C0BF_IRQHandler +INTI2C0NACK_IRQHandler +INTI2C1_IRQHandler +INTI2C1AL_IRQHandler +INTI2C1BF_IRQHandler +INTI2C1NACK_IRQHandler +INTI2C2_IRQHandler +INTI2C2AL_IRQHandler +INTI2C2BF_IRQHandler +INTI2C2NACK_IRQHandler +INTI2C3_IRQHandler +INTI2C3AL_IRQHandler +INTI2C3BF_IRQHandler +INTI2C3NACK_IRQHandler +INTI2C4_IRQHandler +INTI2C4AL_IRQHandler +INTI2C4BF_IRQHandler +INTI2C4NACK_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADAHP_IRQHandler +INTFLDRDY_IRQHandler +INTFLCRDY0_IRQHandler +INTFLCRDY1_IRQHandler +INTMDMAABERR_IRQHandler +INTMDMAADERR_IRQHandler + + B . + + ENDP + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_ARM_STD/tmpm4g9f15.sct Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,41 @@
+#! armcc -E -I. --cpu Cortex-M4
+;; TMPM4G9F15FG scatter file
+
+;; Vector table starts at 0
+;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
+;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
+;; Initial PC == &__main (with LSB set to indicate Thumb)
+;; These two values are provided by the library
+;; Other vectors must be provided by the user
+;; Code starts after the last possible vector
+;; Data starts at 0x20000000
+;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
+;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
+
+;; Compatible with ISSM model
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x000180000
+#endif
+
+; TMPM4G9: 1536 KB FLASH (0x180000) + 192 KB SRAM (0x30000)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
+{
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000320 (0x30000 - 0x320)
+ {
+ tmpm4g9_fc.o (+RO)
+ .ANY (+RW, +ZI)
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_GCC_ARM/startup_TMPM4G9.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,532 @@ +/** + ******************************************************************************* + * @file startup_TMPM4G9.s + * @brief CMSIS Cortex-M4F Core Device Startup File for the + * TOSHIBA 'TMPM4G9' Device Series + * @version + * @date + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// <h> Stack Configuration +// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// <h> Heap Configuration +// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT00_IRQHandler // 0: Interrupt pin 00a/00b + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09a/09b + .long INT10_IRQHandler // 10: Interrupt pin 10a/10b + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12a/12b + .long INT13_IRQHandler // 13: Interrupt pin 13a/13b + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15a/15b + .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt + .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) + .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) + .long INTISDA_IRQHandler // 19: Interval Sensing Detector Interrupt (Unit A) + .long INTISDB_IRQHandler // 20: Interval Sensing Detector Interrupt (Unit B) + .long INTISDC_IRQHandler // 21: Interval Sensing Detector Interrupt (Unit C) + .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 + .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 + .long INTLTTMR_IRQHandler // 24: Long Term Timer Interrupt + .long INTHDMAATC_IRQHandler // 25: HDMA Complete of transfer(Unit A) + .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) + .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) + .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) + .long INTMDMAATC_IRQHandler // 29: MDMA Complete of transfer(Unit A) + .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA All Interrupt/Timer Interrupt C + .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA All Interrupt/Timer Interrupt C + .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA All Interrupt/Timer Interrupt C + .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA All Interrupt/Timer Interrupt C + .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA All Interrupt/Timer Interrupt C + .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA All Interrupt/Timer Interrupt C + .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA All Interrupt/Timer Interrupt C + .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA All Interrupt/Timer Interrupt C + .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA All Interrupt/Timer Interrupt C + .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA All Interrupt/Timer Interrupt C + .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA All Interrupt/Timer Interrupt C + .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA All Interrupt/Timer Interrupt C + .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA All Interrupt/Timer Interrupt C + .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA All Interrupt/Timer Interrupt C + .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt + .long INTPWM0_IRQHandler // 60: PMD0 interrupt + .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) + .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) + .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) + .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) + .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) + .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) + .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) + .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) + .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) + .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) + .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) + .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) + .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) + .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) + .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) + .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) + .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) + .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) + .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) + .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) + .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) + .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) + .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) + .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) + .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) + .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) + .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) + .long INTSMI0_IRQHandler // 88: Serial Memory Interface Interrupt + .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) + .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) + .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) + .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) + .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) + .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) + .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) + .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) + .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) + .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) + .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) + .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) + .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) + .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) + .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) + .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) + .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) + .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) + .long INTFUART0_IRQHandler // 107: FUART Interrupt(channel 0) + .long INTFUART1_IRQHandler // 108: FUART Interrupt(channel 1) + .long INTI2C0_IRQHandler // 109: I2C0 transmission and reception interrupt + .long INTI2C0AL_IRQHandler // 110: I2C0 arbitration lost interrupt + .long INTI2C0BF_IRQHandler // 111: I2C0 bus free interrupt + .long INTI2C0NACK_IRQHandler // 112: I2C0 no ack interrupt + .long INTI2C1_IRQHandler // 113: I2C1 transmission and reception interrupt + .long INTI2C1AL_IRQHandler // 114: I2C1 arbitration lost interrupt + .long INTI2C1BF_IRQHandler // 115: I2C1 bus free interrupt + .long INTI2C1NACK_IRQHandler // 116: I2C1 no ack interrupt + .long INTI2C2_IRQHandler // 117: I2C2 transmission and reception interrupt + .long INTI2C2AL_IRQHandler // 118: I2C2 arbitration lost interrupt + .long INTI2C2BF_IRQHandler // 119: I2C2 bus free interrupt + .long INTI2C2NACK_IRQHandler // 120: I2C2 no ack interrupt + .long INTI2C3_IRQHandler // 121: I2C3 transmission and reception interrupt + .long INTI2C3AL_IRQHandler // 122: I2C3 arbitration lost interrupt + .long INTI2C3BF_IRQHandler // 123: I2C3 bus free interrupt + .long INTI2C3NACK_IRQHandler // 124: I2C3 no ack interrupt + .long INTI2C4_IRQHandler // 125: I2C4 transmission and reception interrupt + .long INTI2C4AL_IRQHandler // 126: I2C4 arbitration lost interrupt + .long INTI2C4BF_IRQHandler // 127: I2C4 bus free interrupt + .long INTI2C4NACK_IRQHandler // 128: I2C4 no ack interrupt + .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 + .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 + .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished + .long INTADAHP_IRQHandler // 134: ADC High Priority AD conversion interrupt + .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt + .long INTFLCRDY0_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt + .long INTFLCRDY1_IRQHandler // 137: Code FLASH Area2 Ready interrupt + .long 0 // 138: Reserved + .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) + .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTCEC0RX_IRQHandler + def_irq_handler INTCEC0TX_IRQHandler + def_irq_handler INTISDA_IRQHandler + def_irq_handler INTISDB_IRQHandler + def_irq_handler INTISDC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTRMC1_IRQHandler + def_irq_handler INTLTTMR_IRQHandler + def_irq_handler INTHDMAATC_IRQHandler + def_irq_handler INTHDMAAERR_IRQHandler + def_irq_handler INTHDMABTC_IRQHandler + def_irq_handler INTHDMABERR_IRQHandler + def_irq_handler INTMDMAATC_IRQHandler + def_irq_handler INTT32A00_A_CT_IRQHandler + def_irq_handler INTT32A00_B_C01_CPC_IRQHandler + def_irq_handler INTT32A01_A_CT_IRQHandler + def_irq_handler INTT32A01_B_C01_CPC_IRQHandler + def_irq_handler INTT32A02_A_CT_IRQHandler + def_irq_handler INTT32A02_B_C01_CPC_IRQHandler + def_irq_handler INTT32A03_A_CT_IRQHandler + def_irq_handler INTT32A03_B_C01_CPC_IRQHandler + def_irq_handler INTT32A04_A_CT_IRQHandler + def_irq_handler INTT32A04_B_C01_CPC_IRQHandler + def_irq_handler INTT32A05_A_CT_IRQHandler + def_irq_handler INTT32A05_B_C01_CPC_IRQHandler + def_irq_handler INTT32A06_A_CT_IRQHandler + def_irq_handler INTT32A06_B_C01_CPC_IRQHandler + def_irq_handler INTT32A07_A_CT_IRQHandler + def_irq_handler INTT32A07_B_C01_CPC_IRQHandler + def_irq_handler INTT32A08_A_CT_IRQHandler + def_irq_handler INTT32A08_B_C01_CPC_IRQHandler + def_irq_handler INTT32A09_A_CT_IRQHandler + def_irq_handler INTT32A09_B_C01_CPC_IRQHandler + def_irq_handler INTT32A10_A_CT_IRQHandler + def_irq_handler INTT32A10_B_C01_CPC_IRQHandler + def_irq_handler INTT32A11_A_CT_IRQHandler + def_irq_handler INTT32A11_B_C01_CPC_IRQHandler + def_irq_handler INTT32A12_A_CT_IRQHandler + def_irq_handler INTT32A12_B_C01_CPC_IRQHandler + def_irq_handler INTT32A13_A_CT_IRQHandler + def_irq_handler INTT32A13_B_C01_CPC_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTT2RX_IRQHandler + def_irq_handler INTT2TX_IRQHandler + def_irq_handler INTT2ERR_IRQHandler + def_irq_handler INTT3RX_IRQHandler + def_irq_handler INTT3TX_IRQHandler + def_irq_handler INTT3ERR_IRQHandler + def_irq_handler INTT4RX_IRQHandler + def_irq_handler INTT4TX_IRQHandler + def_irq_handler INTT4ERR_IRQHandler + def_irq_handler INTT5RX_IRQHandler + def_irq_handler INTT5TX_IRQHandler + def_irq_handler INTT5ERR_IRQHandler + def_irq_handler INTT6RX_IRQHandler + def_irq_handler INTT6TX_IRQHandler + def_irq_handler INTT6ERR_IRQHandler + def_irq_handler INTT7RX_IRQHandler + def_irq_handler INTT7TX_IRQHandler + def_irq_handler INTT7ERR_IRQHandler + def_irq_handler INTT8RX_IRQHandler + def_irq_handler INTT8TX_IRQHandler + def_irq_handler INTT8ERR_IRQHandler + def_irq_handler INTSMI0_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTUART3RX_IRQHandler + def_irq_handler INTUART3TX_IRQHandler + def_irq_handler INTUART3ERR_IRQHandler + def_irq_handler INTUART4RX_IRQHandler + def_irq_handler INTUART4TX_IRQHandler + def_irq_handler INTUART4ERR_IRQHandler + def_irq_handler INTUART5RX_IRQHandler + def_irq_handler INTUART5TX_IRQHandler + def_irq_handler INTUART5ERR_IRQHandler + def_irq_handler INTFUART0_IRQHandler + def_irq_handler INTFUART1_IRQHandler + def_irq_handler INTI2C0_IRQHandler + def_irq_handler INTI2C0AL_IRQHandler + def_irq_handler INTI2C0BF_IRQHandler + def_irq_handler INTI2C0NACK_IRQHandler + def_irq_handler INTI2C1_IRQHandler + def_irq_handler INTI2C1AL_IRQHandler + def_irq_handler INTI2C1BF_IRQHandler + def_irq_handler INTI2C1NACK_IRQHandler + def_irq_handler INTI2C2_IRQHandler + def_irq_handler INTI2C2AL_IRQHandler + def_irq_handler INTI2C2BF_IRQHandler + def_irq_handler INTI2C2NACK_IRQHandler + def_irq_handler INTI2C3_IRQHandler + def_irq_handler INTI2C3AL_IRQHandler + def_irq_handler INTI2C3BF_IRQHandler + def_irq_handler INTI2C3NACK_IRQHandler + def_irq_handler INTI2C4_IRQHandler + def_irq_handler INTI2C4AL_IRQHandler + def_irq_handler INTI2C4BF_IRQHandler + def_irq_handler INTI2C4NACK_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADAHP_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + def_irq_handler INTFLCRDY0_IRQHandler + def_irq_handler INTFLCRDY1_IRQHandler + //def_irq_handler 0 + def_irq_handler INTMDMAABERR_IRQHandler + def_irq_handler INTMDMAADERR_IRQHandler + + .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_GCC_ARM/tmpm4g9f15fg.ld Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,207 @@
+/* Linker script for Toshiba TMPM4G9 */
+
+/* Linker script to configure memory regions. */
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x180000
+#endif
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x20000320, LENGTH = (192K - 0x320)
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ *(.ram_func*)
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_IAR/startup_TMPM4G9.S Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,952 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4G9.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4G9' Device Series +; * @version V1.0.9.0 +; * $Date:: 2018-04-02 #$ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b + DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b + DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b + DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt + DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) + DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) + DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector Interrupt (Unit A) + DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector Interrupt (Unit B) + DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector Interrupt (Unit C) + DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 + DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 + DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) + DCD INTHDMAATC_IRQHandler ; 25: HDMA Complete of transfer(Unit A) + DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) + DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) + DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) + DCD INTMDMAATC_IRQHandler ; 29: MDMA Complete of transfer(Unit A) + DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A00_B_C01_CPC_IRQHandler ; 31: T32A00 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A01_B_C01_CPC_IRQHandler ; 33: T32A01 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A02_B_C01_CPC_IRQHandler ; 35: T32A02 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A03_B_C01_CPC_IRQHandler ; 37: T32A03 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A04_B_C01_CPC_IRQHandler ; 39: T32A04 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A05_B_C01_CPC_IRQHandler ; 41: T32A05 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A06_B_C01_CPC_IRQHandler ; 43: T32A06 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A07_B_C01_CPC_IRQHandler ; 45: T32A07 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A08_B_C01_CPC_IRQHandler ; 47: T32A08 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A09_B_C01_CPC_IRQHandler ; 49: T32A09 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A10_B_C01_CPC_IRQHandler ; 51: T32A10 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A11_B_C01_CPC_IRQHandler ; 53: T32A11 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A12_B_C01_CPC_IRQHandler ; 55: T32A12 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA All Interrupt/Timer Interrupt C + DCD INTT32A13_B_C01_CPC_IRQHandler ; 57: T32A13 Timer Interrupt B/Capture C0,C1 Interrupt/ Timer Interrupt C + DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt + DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt + DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) + DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) + DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) + DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) + DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) + DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) + DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) + DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) + DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) + DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) + DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) + DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) + DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) + DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) + DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) + DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) + DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) + DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) + DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) + DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) + DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) + DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) + DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface Interrupt + DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) + DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) + DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) + DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) + DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) + DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) + DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) + DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) + DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) + DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) + DCD INTFUART0_IRQHandler ; 107: FUART Interrupt(channel 0) + DCD INTFUART1_IRQHandler ; 108: FUART Interrupt(channel 1) + DCD INTI2C0_IRQHandler ; 109: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 110: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 111: I2C0 bus free interrupt + DCD INTI2C0NACK_IRQHandler ; 112: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 113: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 114: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 115: I2C1 bus free interrupt + DCD INTI2C1NACK_IRQHandler ; 116: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 117: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 118: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 119: I2C2 bus free interrupt + DCD INTI2C2NACK_IRQHandler ; 120: I2C2 no ack interrupt + DCD INTI2C3_IRQHandler ; 121: I2C3 transmission and reception interrupt + DCD INTI2C3AL_IRQHandler ; 122: I2C3 arbitration lost interrupt + DCD INTI2C3BF_IRQHandler ; 123: I2C3 bus free interrupt + DCD INTI2C3NACK_IRQHandler ; 124: I2C3 no ack interrupt + DCD INTI2C4_IRQHandler ; 125: I2C4 transmission and reception interrupt + DCD INTI2C4AL_IRQHandler ; 126: I2C4 arbitration lost interrupt + DCD INTI2C4BF_IRQHandler ; 127: I2C4 bus free interrupt + DCD INTI2C4NACK_IRQHandler ; 128: I2C4 no ack interrupt + DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished + DCD INTADAHP_IRQHandler ; 134: ADC High Priority AD conversion interrupt + DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt + DCD INTFLCRDY0_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt + DCD INTFLCRDY1_IRQHandler ; 137: Code FLASH Area2 Ready interrupt + DCD 0 ; 138: Reserved + DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) + DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK INT00_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT00_IRQHandler + B INT00_IRQHandler + + PUBWEAK INT01_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT01_IRQHandler + B INT01_IRQHandler + + PUBWEAK INT02_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT02_IRQHandler + B INT02_IRQHandler + + PUBWEAK INT03_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT03_IRQHandler + B INT03_IRQHandler + + PUBWEAK INT04_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT04_IRQHandler + B INT04_IRQHandler + + PUBWEAK INT05_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT05_IRQHandler + B INT05_IRQHandler + + PUBWEAK INT06_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT06_IRQHandler + B INT06_IRQHandler + + PUBWEAK INT07_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT07_IRQHandler + B INT07_IRQHandler + + PUBWEAK INT08_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT08_IRQHandler + B INT08_IRQHandler + + PUBWEAK INT09_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT09_IRQHandler + B INT09_IRQHandler + + PUBWEAK INT10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT10_IRQHandler + B INT10_IRQHandler + + PUBWEAK INT11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT11_IRQHandler + B INT11_IRQHandler + + PUBWEAK INT12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT12_IRQHandler + B INT12_IRQHandler + + PUBWEAK INT13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT13_IRQHandler + B INT13_IRQHandler + + PUBWEAK INT14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT14_IRQHandler + B INT14_IRQHandler + + PUBWEAK INT15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT15_IRQHandler + B INT15_IRQHandler + + PUBWEAK INTRTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRTC_IRQHandler + B INTRTC_IRQHandler + + PUBWEAK INTCEC0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTCEC0RX_IRQHandler + B INTCEC0RX_IRQHandler + + PUBWEAK INTCEC0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTCEC0TX_IRQHandler + B INTCEC0TX_IRQHandler + + PUBWEAK INTISDA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTISDA_IRQHandler + B INTISDA_IRQHandler + + PUBWEAK INTISDB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTISDB_IRQHandler + B INTISDB_IRQHandler + + PUBWEAK INTISDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTISDC_IRQHandler + B INTISDC_IRQHandler + + PUBWEAK INTRMC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRMC0_IRQHandler + B INTRMC0_IRQHandler + + PUBWEAK INTRMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRMC1_IRQHandler + B INTRMC1_IRQHandler + + PUBWEAK INTLTTMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTLTTMR0_IRQHandler + B INTLTTMR0_IRQHandler + + PUBWEAK INTHDMAATC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTHDMAATC_IRQHandler + B INTHDMAATC_IRQHandler + + PUBWEAK INTHDMAAERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTHDMAAERR_IRQHandler + B INTHDMAAERR_IRQHandler + + PUBWEAK INTHDMABTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTHDMABTC_IRQHandler + B INTHDMABTC_IRQHandler + + PUBWEAK INTHDMABERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTHDMABERR_IRQHandler + B INTHDMABERR_IRQHandler + + PUBWEAK INTMDMAATC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTMDMAATC_IRQHandler + B INTMDMAATC_IRQHandler + + PUBWEAK INTT32A00_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00_A_CT_IRQHandler + B INTT32A00_A_CT_IRQHandler + + PUBWEAK INTT32A00_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00_B_C01_CPC_IRQHandler + B INTT32A00_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A01_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01_A_CT_IRQHandler + B INTT32A01_A_CT_IRQHandler + + PUBWEAK INTT32A01_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01_B_C01_CPC_IRQHandler + B INTT32A01_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A02_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02_A_CT_IRQHandler + B INTT32A02_A_CT_IRQHandler + + PUBWEAK INTT32A02_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02_B_C01_CPC_IRQHandler + B INTT32A02_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A03_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03_A_CT_IRQHandler + B INTT32A03_A_CT_IRQHandler + + PUBWEAK INTT32A03_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03_B_C01_CPC_IRQHandler + B INTT32A03_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A04_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04_A_CT_IRQHandler + B INTT32A04_A_CT_IRQHandler + + PUBWEAK INTT32A04_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04_B_C01_CPC_IRQHandler + B INTT32A04_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A05_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05_A_CT_IRQHandler + B INTT32A05_A_CT_IRQHandler + + PUBWEAK INTT32A05_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05_B_C01_CPC_IRQHandler + B INTT32A05_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A06_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06_A_CT_IRQHandler + B INTT32A06_A_CT_IRQHandler + + PUBWEAK INTT32A06_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06_B_C01_CPC_IRQHandler + B INTT32A06_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A07_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07_A_CT_IRQHandler + B INTT32A07_A_CT_IRQHandler + + PUBWEAK INTT32A07_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07_B_C01_CPC_IRQHandler + B INTT32A07_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A08_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A08_A_CT_IRQHandler + B INTT32A08_A_CT_IRQHandler + + PUBWEAK INTT32A08_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A08_B_C01_CPC_IRQHandler + B INTT32A08_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A09_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A09_A_CT_IRQHandler + B INTT32A09_A_CT_IRQHandler + + PUBWEAK INTT32A09_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A09_B_C01_CPC_IRQHandler + B INTT32A09_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A10_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A10_A_CT_IRQHandler + B INTT32A10_A_CT_IRQHandler + + PUBWEAK INTT32A10_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A10_B_C01_CPC_IRQHandler + B INTT32A10_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A11_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A11_A_CT_IRQHandler + B INTT32A11_A_CT_IRQHandler + + PUBWEAK INTT32A11_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A11_B_C01_CPC_IRQHandler + B INTT32A11_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A12_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A12_A_CT_IRQHandler + B INTT32A12_A_CT_IRQHandler + + PUBWEAK INTT32A12_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A12_B_C01_CPC_IRQHandler + B INTT32A12_B_C01_CPC_IRQHandler + + PUBWEAK INTT32A13_A_CT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A13_A_CT_IRQHandler + B INTT32A13_A_CT_IRQHandler + + PUBWEAK INTT32A13_B_C01_CPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A13_B_C01_CPC_IRQHandler + B INTT32A13_B_C01_CPC_IRQHandler + + PUBWEAK INTEMG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTEMG0_IRQHandler + B INTEMG0_IRQHandler + + PUBWEAK INTOVV0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTOVV0_IRQHandler + B INTOVV0_IRQHandler + + PUBWEAK INTPWM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTPWM0_IRQHandler + B INTPWM0_IRQHandler + + PUBWEAK INTT0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0RX_IRQHandler + B INTT0RX_IRQHandler + + PUBWEAK INTT0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0TX_IRQHandler + B INTT0TX_IRQHandler + + PUBWEAK INTT0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0ERR_IRQHandler + B INTT0ERR_IRQHandler + + PUBWEAK INTT1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1RX_IRQHandler + B INTT1RX_IRQHandler + + PUBWEAK INTT1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1TX_IRQHandler + B INTT1TX_IRQHandler + + PUBWEAK INTT1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1ERR_IRQHandler + B INTT1ERR_IRQHandler + + PUBWEAK INTT2RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2RX_IRQHandler + B INTT2RX_IRQHandler + + PUBWEAK INTT2TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2TX_IRQHandler + B INTT2TX_IRQHandler + + PUBWEAK INTT2ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2ERR_IRQHandler + B INTT2ERR_IRQHandler + + PUBWEAK INTT3RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3RX_IRQHandler + B INTT3RX_IRQHandler + + PUBWEAK INTT3TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3TX_IRQHandler + B INTT3TX_IRQHandler + + PUBWEAK INTT3ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3ERR_IRQHandler + B INTT3ERR_IRQHandler + + PUBWEAK INTT4RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4RX_IRQHandler + B INTT4RX_IRQHandler + + PUBWEAK INTT4TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4TX_IRQHandler + B INTT4TX_IRQHandler + + PUBWEAK INTT4ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4ERR_IRQHandler + B INTT4ERR_IRQHandler + + PUBWEAK INTT5RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT5RX_IRQHandler + B INTT5RX_IRQHandler + + PUBWEAK INTT5TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT5TX_IRQHandler + B INTT5TX_IRQHandler + + PUBWEAK INTT5ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT5ERR_IRQHandler + B INTT5ERR_IRQHandler + + PUBWEAK INTT6RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT6RX_IRQHandler + B INTT6RX_IRQHandler + + PUBWEAK INTT6TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT6TX_IRQHandler + B INTT6TX_IRQHandler + + PUBWEAK INTT6ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT6ERR_IRQHandler + B INTT6ERR_IRQHandler + + PUBWEAK INTT7RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT7RX_IRQHandler + B INTT7RX_IRQHandler + + PUBWEAK INTT7TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT7TX_IRQHandler + B INTT7TX_IRQHandler + + PUBWEAK INTT7ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT7ERR_IRQHandler + B INTT7ERR_IRQHandler + + PUBWEAK INTT8RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT8RX_IRQHandler + B INTT8RX_IRQHandler + + PUBWEAK INTT8TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT8TX_IRQHandler + B INTT8TX_IRQHandler + + PUBWEAK INTT8ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT8ERR_IRQHandler + B INTT8ERR_IRQHandler + + PUBWEAK INTSMI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTSMI0_IRQHandler + B INTSMI0_IRQHandler + + PUBWEAK INTUART0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0RX_IRQHandler + B INTUART0RX_IRQHandler + + PUBWEAK INTUART0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0TX_IRQHandler + B INTUART0TX_IRQHandler + + PUBWEAK INTUART0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0ERR_IRQHandler + B INTUART0ERR_IRQHandler + + PUBWEAK INTUART1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1RX_IRQHandler + B INTUART1RX_IRQHandler + + PUBWEAK INTUART1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1TX_IRQHandler + B INTUART1TX_IRQHandler + + PUBWEAK INTUART1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1ERR_IRQHandler + B INTUART1ERR_IRQHandler + + PUBWEAK INTUART2RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2RX_IRQHandler + B INTUART2RX_IRQHandler + + PUBWEAK INTUART2TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2TX_IRQHandler + B INTUART2TX_IRQHandler + + PUBWEAK INTUART2ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2ERR_IRQHandler + B INTUART2ERR_IRQHandler + + PUBWEAK INTUART3RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3RX_IRQHandler + B INTUART3RX_IRQHandler + + PUBWEAK INTUART3TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3TX_IRQHandler + B INTUART3TX_IRQHandler + + PUBWEAK INTUART3ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3ERR_IRQHandler + B INTUART3ERR_IRQHandler + + PUBWEAK INTUART4RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4RX_IRQHandler + B INTUART4RX_IRQHandler + + PUBWEAK INTUART4TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4TX_IRQHandler + B INTUART4TX_IRQHandler + + PUBWEAK INTUART4ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4ERR_IRQHandler + B INTUART4ERR_IRQHandler + + PUBWEAK INTUART5RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5RX_IRQHandler + B INTUART5RX_IRQHandler + + PUBWEAK INTUART5TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5TX_IRQHandler + B INTUART5TX_IRQHandler + + PUBWEAK INTUART5ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5ERR_IRQHandler + B INTUART5ERR_IRQHandler + + PUBWEAK INTFUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFUART0_IRQHandler + B INTFUART0_IRQHandler + + PUBWEAK INTFUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFUART1_IRQHandler + B INTFUART1_IRQHandler + + PUBWEAK INTI2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0_IRQHandler + B INTI2C0_IRQHandler + + PUBWEAK INTI2C0AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0AL_IRQHandler + B INTI2C0AL_IRQHandler + + PUBWEAK INTI2C0BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0BF_IRQHandler + B INTI2C0BF_IRQHandler + + PUBWEAK INTI2C0NACK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0NACK_IRQHandler + B INTI2C0NACK_IRQHandler + + PUBWEAK INTI2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1_IRQHandler + B INTI2C1_IRQHandler + + PUBWEAK INTI2C1AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1AL_IRQHandler + B INTI2C1AL_IRQHandler + + PUBWEAK INTI2C1BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1BF_IRQHandler + B INTI2C1BF_IRQHandler + + PUBWEAK INTI2C1NACK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1NACK_IRQHandler + B INTI2C1NACK_IRQHandler + + PUBWEAK INTI2C2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2_IRQHandler + B INTI2C2_IRQHandler + + PUBWEAK INTI2C2AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2AL_IRQHandler + B INTI2C2AL_IRQHandler + + PUBWEAK INTI2C2BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2BF_IRQHandler + B INTI2C2BF_IRQHandler + + PUBWEAK INTI2C2NACK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2NACK_IRQHandler + B INTI2C2NACK_IRQHandler + + PUBWEAK INTI2C3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3_IRQHandler + B INTI2C3_IRQHandler + + PUBWEAK INTI2C3AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3AL_IRQHandler + B INTI2C3AL_IRQHandler + + PUBWEAK INTI2C3BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3BF_IRQHandler + B INTI2C3BF_IRQHandler + + PUBWEAK INTI2C3NACK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3NACK_IRQHandler + B INTI2C3NACK_IRQHandler + + PUBWEAK INTI2C4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C4_IRQHandler + B INTI2C4_IRQHandler + + PUBWEAK INTI2C4AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C4AL_IRQHandler + B INTI2C4AL_IRQHandler + + PUBWEAK INTI2C4BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C4BF_IRQHandler + B INTI2C4BF_IRQHandler + + PUBWEAK INTI2C4NACK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C4NACK_IRQHandler + B INTI2C4NACK_IRQHandler + + PUBWEAK INTADACP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP0_IRQHandler + B INTADACP0_IRQHandler + + PUBWEAK INTADACP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP1_IRQHandler + B INTADACP1_IRQHandler + + PUBWEAK INTADATRG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADATRG_IRQHandler + B INTADATRG_IRQHandler + + PUBWEAK INTADASGL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADASGL_IRQHandler + B INTADASGL_IRQHandler + + PUBWEAK INTADACNT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACNT_IRQHandler + B INTADACNT_IRQHandler + + PUBWEAK INTADAHP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADAHP_IRQHandler + B INTADAHP_IRQHandler + + PUBWEAK INTFLDRDY_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLDRDY_IRQHandler + B INTFLDRDY_IRQHandler + + PUBWEAK INTFLCRDY0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLCRDY0_IRQHandler + B INTFLCRDY0_IRQHandler + + PUBWEAK INTFLCRDY1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLCRDY1_IRQHandler + B INTFLCRDY1_IRQHandler + + PUBWEAK INTMDMAABERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTMDMAABERR_IRQHandler + B INTMDMAABERR_IRQHandler + + PUBWEAK INTMDMAADERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTMDMAADERR_IRQHandler + B INTMDMAADERR_IRQHandler + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/TOOLCHAIN_IAR/tmpm4g9f15.icf Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,45 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x180000; }
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000320;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+define symbol __ICFEDIT_region_BRAM_start__ = 0x20030000;
+define symbol __ICFEDIT_region_BRAM_end__ = 0x200307FF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__ = 0x6000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+initialize by copy { section RAMCODE };
+
+/* Place both in a block */
+define block RamCode { section RAMCODE };
+define block RamCodeInit { section RAMCODE_init };
+
+/* Place them in ROM and RAM */
+place in ROM_region { block RamCodeInit };
+place in RAM_region { block RamCode };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in ROM_region { readonly };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/cmsis.h Thu Nov 08 11:46:34 2018 +0000 @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS for TMPM4G9 + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in TMPM4G9 specifics + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4G9.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/cmsis_nvic.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic for TMPM4G9
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+
+#if defined(__ICCARM__)
+ #pragma section=".intvec"
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM)
+ extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+ extern uint32_t vectors[];
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors)
+#else
+ #error "Flash vector address not set for this toolchain"
+#endif
+
+
+#define NVIC_NUM_VECTORS (157)
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/system_TMPM4G9.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,336 @@
+/**
+ *******************************************************************************
+ * @file system_TMPM4G9.c
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
+ * TOSHIBA 'TMPM4Gx' Device Series
+ * @version 1.0.0.0
+ * $Date:: 2018-04-02 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *******************************************************************************
+ */
+
+#include "TMPM4G9.h"
+
+/*-------- <<< Start of configuration section >>> ----------------------------*/
+
+/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
+#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
+#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
+#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
+
+/* Clock Generator (CG) Configuration */
+#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
+#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */
+#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */
+
+#define STBYCR_Val (0x00000000UL)
+
+#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */
+#define CG_10M_MUL_16_FPLL (0x002E5020UL<<8U) /* fPLL = 10MHz * 16 */
+#define CG_12M_MUL_13_3125_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.3125 */
+#define CG_16M_MUL_10_FPLL (0x0048D014UL<<8U) /* fPLL = 16MHz * 10 */
+#define CG_20M_MUL_8_FPLL (0x005AD010UL<<8U) /* fPLL = 20MHz * 8 */
+
+#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL)
+#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL)
+#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL)
+#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL)
+
+#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U)
+#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U)
+#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U)
+
+#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL)
+#define CG_OSCCR_EOSCEN_SET (0x00000002UL)
+#define CG_OSCCR_OSCSEL_SET (0x00000100UL)
+
+#define CG_WUPHCR_WUON_START_SET (0x00000001UL)
+
+#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */
+#if (CLOCK_SETUP)
+ #define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */
+ #define PLL0SEL_Ready CG_10M_MUL_16_FPLL
+#else
+ #define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */
+ #define PLL0SEL_Ready CG_10M_MUL_16_FPLL
+#endif
+#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
+#define PLL0SEL_MASK (0xFFFFFF00UL)
+
+/*-------- <<< End of configuration section >>> ------------------------------*/
+
+/*-------- DEFINES -----------------------------------------------------------*/
+/* Define clocks */
+#define EOSC_8M (8000000UL)
+#define EOSC_10M (10000000UL)
+#define EOSC_12M (12000000UL)
+#define EOSC_16M (16000000UL)
+#define EOSC_20M (20000000UL)
+#define IOSC_10M (10000000UL)
+#define EXTALH EOSC_10M /* External high-speed oscillator freq */
+#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
+#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */
+#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
+#define EOSC_12M_DIV2_PLLON (159750000UL) /* 12.00MHz * 26.6250 / 2 */
+#define EOSC_16M_DIV2_PLLON (160000000UL) /* 16.00MHz * 20.0000 / 2 */
+#define EOSC_20M_DIV2_PLLON (160000000UL) /* 20.00MHz * 16.0000 / 2 */
+#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
+
+/* Configure Warm-up time */
+#define HZ_1M (1000000UL)
+#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
+#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
+#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
+#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */
+#if (CLOCK_SETUP)
+ #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
+ #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
+#else
+ #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
+ #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
+#endif
+
+/* Determine core clock frequency according to settings */
+/* System clock is high-speed clock*/
+#if (CLOCK_SETUP)
+ #define CORE_TALH (EXTALH)
+#else
+ #define CORE_TALH (IXTALH)
+#endif
+
+#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
+ #if (CORE_TALH == EOSC_8M) /* If input is 8MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL))
+ #define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 8MHz */
+ #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
+ #define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 10MHz */
+ #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL)
+ #define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 12MHz */
+ #elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL)
+ #define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 160MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 16MHz */
+ #elif (CORE_TALH == EOSC_20M) /* If input is 20MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL)
+ #define __CORE_CLK EOSC_20M_DIV2_PLLON /* output clock is 160MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 20MHz */
+ #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
+ #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
+ #define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */
+ #else /* fc -> reserved */
+ #define __CORE_CLK (0U)
+ #endif /* End input is 10MHz */
+ #else /* input clock not known */
+ #define __CORE_CLK (0U)
+ #error "Core Oscillator Frequency invalid!"
+ #endif /* End switch input clock */
+#else
+ #define __CORE_CLK (CORE_TALH)
+#endif
+
+#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */
+ #define __CORE_SYS (__CORE_CLK)
+#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */
+ #define __CORE_SYS (__CORE_CLK / 2U)
+#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */
+ #define __CORE_SYS (__CORE_CLK / 4U )
+#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */
+ #define __CORE_SYS (__CORE_CLK / 8U)
+#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */
+ #define __CORE_SYS (__CORE_CLK / 16U)
+#else /* Gear -> reserved */
+ #define __CORE_SYS (0U)
+#endif
+
+
+/* Clock Variable definitions */
+uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
+uint32_t CoreClockInput = 0U;
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Update SystemCoreClock according register values.
+ */
+void SystemCoreClockUpdate(void)
+{ /* Get Core Clock Frequency */
+ uint32_t CoreClock = 0U;
+ uint32_t regval = 0U;
+ uint32_t oscsel = 0U;
+ uint32_t pll0sel = 0U;
+ uint32_t pll0on = 0U;
+
+ CoreClockInput = 0U;
+ /* Determine clock frequency according to clock register values */
+ /* System clock is high-speed clock */
+ regval = TSB_CG->OSCCR;
+ oscsel = regval & CG_OSCCR_OSCSEL_SET;
+ if (oscsel) { /* If system clock is External high-speed oscillator freq */
+ CoreClock = EXTALH;
+ } else { /* If system clock is Internal high-speed oscillator freq */
+ CoreClock = IXTALH;
+ }
+ regval = TSB_CG->PLL0SEL;
+ pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
+ pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
+ if (pll0sel && pll0on) { /* If PLL enabled */
+ if (CoreClock == EOSC_8M) { /* If input is 8MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) {
+ CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
+ CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_3125_FPLL) {
+ CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_10_FPLL) {
+ CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 160MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else if (CoreClock == EOSC_20M) { /* If input is 20MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_20M_MUL_8_FPLL) {
+ CoreClockInput = EOSC_20M_DIV2_PLLON; /* output clock is 160MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
+ if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
+ CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
+ } else {
+ CoreClockInput = 0U; /* fc -> reserved */
+ }
+ } else {
+ CoreClockInput = 0U;
+ }
+ } else { /* If PLL not used */
+ CoreClockInput = CoreClock;
+ }
+
+ switch (TSB_CG->SYSCR & 7U) {
+ case 0U: /* Gear -> fc */
+ SystemCoreClock = CoreClockInput;
+ break;
+ case 1U: /* Gear -> fc/2 */
+ SystemCoreClock = CoreClockInput / 2U;
+ break;
+ case 2U: /* Gear -> fc/4 */
+ SystemCoreClock = CoreClockInput / 4U;
+ break;
+ case 3U: /* Gear -> fc/8 */
+ SystemCoreClock = CoreClockInput / 8U;
+ break;
+ case 4U: /* Gear -> fc/16 */
+ SystemCoreClock = CoreClockInput / 16U;
+ break;
+ case 5U:
+ case 6U:
+ case 7U:
+ SystemCoreClock = 0U;
+ break;
+ default:
+ SystemCoreClock = 0U;
+ break;
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit(void)
+{
+#if (SIWD_SETUP) /* Watchdog Setup */
+ /* SIWD Disable */
+ TSB_SIWD0->EN = SIWDEN_Val;
+ TSB_SIWD0->CR = SIWDCR_Val;
+#else
+ /* SIWD Enable (Setting after a Reset) */
+#endif
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+
+#if (CLOCK_SETUP) /* Clock(external) Setup */
+ TSB_CG->SYSCR = SYSCR_GEAR_Val;
+
+ TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET);
+ TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
+ TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
+ while (TSB_CG_WUPHCR_WUEF) {
+ ;
+ } /* Warm-up */
+
+ TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+ while (!TSB_CG_OSCCR_OSCF) {
+ ;
+ } /* Confirm CGOSCCR<OSCF>="1" */
+ TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
+#else
+ /* Internal HOSC Enable (Setting after a Reset) */
+#endif
+
+ TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set <MCKSEL> */
+ while((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))
+ != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))){
+ ;
+ }
+
+ TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
+ TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
+ TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
+ TSB_CG->PLL0SEL = PLL0SEL_Ready;
+ TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
+ while (TSB_CG_WUPHCR_WUEF) {
+ ;
+ } /* Warm-up */
+
+ TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
+ TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
+ TSB_CG->STBYCR = STBYCR_Val;
+ TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
+ while (TSB_CG_WUPHCR_WUEF) {
+ ;
+ } /* Lockup */
+ TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
+ while (!TSB_CG_PLL0SEL_PLL0ST) {
+ ;
+ } /*Confirm CGPLL0SEL<PLL0ST> = "1" */
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/device/system_TMPM4G9.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,53 @@
+/**
+ *****************************************************************************
+ * @file system_TMPM4G9.h
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the
+ * TOSHIBA 'TMPM4G9' Device Series
+ * @version V0.0.0.0
+ * $Date:: 2018-04-02 #$
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *****************************************************************************
+ */
+
+#include <stdint.h>
+
+#ifndef __SYSTEM_TMPM4G9_H
+#define __SYSTEM_TMPM4G9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/flash_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,123 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+#include "tmpm4g9_fc.h"
+
+#define PROGRAM_WIRTE_MAX (16U) // Page program could be written 16 bytes/4 words once
+#define SECTOR_SIZE (0x8000) // 32KB each sectors or block
+#define FLASH_CHIP_SIZE (0x00180000) // Flash chip size is 1536KByte
+#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL)
+
+#define SUCCESS (0U)
+#define FAIL (-1)
+// IHOSC1EN
+#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask
+#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable
+#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable
+
+static void internal_hosc_enable(void);
+
+int32_t flash_init(flash_t *obj)
+{
+ obj->flash_inited = 0;
+ obj->flash_inited = 1;
+ internal_hosc_enable(); // Internal HOSC enable
+ return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+ obj->flash_inited = 0;
+
+ return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ int status = FAIL;
+
+ if (obj->flash_inited == 0) {
+ flash_init(obj);
+ }
+
+ // We need to prevent flash accesses during erase operation
+ core_util_critical_section_enter();
+
+ if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) {
+ status = SUCCESS;
+ } else {
+ // Do nothing
+ }
+
+ core_util_critical_section_exit();
+
+ return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+ int status = SUCCESS;
+
+ address &= MASK_CHIP_ID_FROM_ADD;
+
+ // We need to prevent flash accesses during program operation
+ core_util_critical_section_enter();
+
+ if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) {
+ // Do nothing
+ } else {
+ status = FAIL;
+ }
+
+ core_util_critical_section_exit();
+
+ return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+ if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) {
+ return SECTOR_SIZE;
+ } else {
+ // Do nothing
+ }
+
+ return MBED_FLASH_INVALID_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ return PROGRAM_WIRTE_MAX;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ return FC_CODE_FLASH_ADDRESS_TOP;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return FLASH_CHIP_SIZE;
+}
+
+static void internal_hosc_enable(void)
+{
+ uint32_t work;
+ work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK);
+ TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,123 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "txz_gpio.h"
+
+#define GPIO_DATA PIN_DATA(0, 2)
+#define ALT_FUNC_GPIO 0
+
+_gpio_t gpio_port_add = {
+ .p_pa_instance = TSB_PA,
+ .p_pb_instance = TSB_PB,
+ .p_pc_instance = TSB_PC,
+ .p_pd_instance = TSB_PD,
+ .p_pe_instance = TSB_PE,
+ .p_pf_instance = TSB_PF,
+ .p_pg_instance = TSB_PG,
+ .p_ph_instance = TSB_PH,
+ .p_pj_instance = TSB_PJ,
+ .p_pk_instance = TSB_PK,
+ .p_pl_instance = TSB_PL,
+ .p_pm_instance = TSB_PM,
+ .p_pn_instance = TSB_PN,
+ .p_pp_instance = TSB_PP,
+ .p_pr_instance = TSB_PR,
+ .p_pt_instance = TSB_PT,
+ .p_pu_instance = TSB_PU,
+ .p_pv_instance = TSB_PV,
+ .p_pw_instance = TSB_PW,
+ .p_py_instance = TSB_PY
+};
+
+uint32_t gpio_set(PinName pin)
+{
+ // Check that pin is valid
+ MBED_ASSERT(pin != (PinName)NC);
+
+ // Set pin function as GPIO pin
+ pin_function(pin, GPIO_DATA);
+
+ // Return pin mask
+ return (1 << (pin & 0x07));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ // Store above pin mask, pin name into GPIO object
+ obj->pin = pin;
+ obj->pin_num = PIN_POS(pin);
+ obj->mask = gpio_set(pin);
+ obj->port = (PortName) PIN_PORT(pin);
+ // Enable clock for particular port
+ TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2));
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ // Set pin mode
+ pin_mode(obj->pin, mode);
+}
+
+// Set gpio object pin direction
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ // Set direction
+ switch (direction) {
+ case PIN_INPUT:
+ // Set pin input
+ gpio_func(&gpio_port_add,
+ (gpio_gr_t)obj->port,
+ (gpio_num_t)obj->pin_num,
+ (uint32_t)ALT_FUNC_GPIO,
+ GPIO_PIN_INPUT);
+ break;
+ case PIN_OUTPUT:
+ // Set pin output
+ gpio_func(&gpio_port_add,
+ (gpio_gr_t)obj->port,
+ (gpio_num_t)obj->pin_num,
+ (uint32_t)ALT_FUNC_GPIO,
+ GPIO_PIN_OUTPUT);
+ break;
+ case PIN_INOUT:
+ // Set pin both input and output
+ gpio_func(&gpio_port_add,
+ (gpio_gr_t)obj->port,
+ (gpio_num_t)obj->pin_num,
+ (uint32_t)ALT_FUNC_GPIO,
+ GPIO_PIN_INOUT);
+ break;
+ default:
+ break;
+ }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+ // Write gpio object pin data
+ gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value);
+}
+
+int gpio_read(gpio_t *obj)
+{
+ // Read gpio object pin data
+ gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable
+ gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val);
+ return val;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_irq_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,288 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_critical.h"
+#include "txz_gpio.h"
+
+#define CHANNEL_NUM (16)
+#define DISABLE (0)
+#define ENABLE (1)
+#define CLR_INT_FLAG (0xC0)
+
+const PinMap PinMap_GPIO_IRQ[] = {
+ {PK7, GPIO_IRQ_0, PIN_DATA(0, 0)},
+ {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)},
+ {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)},
+ {PA7, GPIO_IRQ_3, PIN_DATA(0, 0)},
+ {PB0, GPIO_IRQ_4, PIN_DATA(0, 0)},
+ {PB1, GPIO_IRQ_5, PIN_DATA(0, 0)},
+ {PB6, GPIO_IRQ_6, PIN_DATA(0, 0)},
+ {PB7, GPIO_IRQ_7, PIN_DATA(0, 0)},
+ {PG0, GPIO_IRQ_8, PIN_DATA(0, 0)},
+ {PG1, GPIO_IRQ_9, PIN_DATA(0, 0)},
+ {PK0, GPIO_IRQ_A, PIN_DATA(0, 0)},
+ {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)},
+ {PC0, GPIO_IRQ_C, PIN_DATA(0, 0)},
+ {PC1, GPIO_IRQ_D, PIN_DATA(0, 0)},
+ {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)},
+ {PC7, GPIO_IRQ_F, PIN_DATA(0, 0)},
+ {NC, NC, 0}
+};
+
+extern _gpio_t gpio_port_add;
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
+static CG_INTActiveState CurrentState;
+
+static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t);
+static void INT_IRQHandler(PinName, uint32_t);
+
+void INT00_IRQHandler(void)
+{
+ INT_IRQHandler(PK7, 0);
+}
+
+void INT01_IRQHandler(void)
+{
+ INT_IRQHandler(PL0, 1);
+}
+
+void INT02_IRQHandler(void)
+{
+ INT_IRQHandler(PA0, 2);
+}
+
+void INT03_IRQHandler(void)
+{
+ INT_IRQHandler(PA7, 3);
+}
+
+void INT04_IRQHandler(void)
+{
+ INT_IRQHandler(PB0, 4);
+}
+
+void INT05_IRQHandler(void)
+{
+ INT_IRQHandler(PB1, 5);
+}
+
+void INT06_IRQHandler(void)
+{
+ INT_IRQHandler(PB6, 6);
+}
+
+void INT07_IRQHandler(void)
+{
+ INT_IRQHandler(PB7, 7);
+}
+
+void INT08_IRQHandler(void)
+{
+ INT_IRQHandler(PG0, 8);
+}
+
+void INT09_IRQHandler(void)
+{
+ INT_IRQHandler(PG1, 9);
+}
+
+void INT10_IRQHandler(void)
+{
+ INT_IRQHandler(PK0, 10);
+}
+
+void INT11_IRQHandler(void)
+{
+ INT_IRQHandler(PK1, 11);
+}
+
+void INT12_IRQHandler(void)
+{
+ INT_IRQHandler(PC0, 12);
+}
+void INT13_IRQHandler(void)
+{
+ INT_IRQHandler(PC1, 13);
+}
+void INT14_IRQHandler(void)
+{
+ INT_IRQHandler(PC6, 14);
+}
+void INT15_IRQHandler(void)
+{
+ INT_IRQHandler(PC7, 15);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ // Get gpio interrupt ID
+ obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
+ core_util_critical_section_enter();
+ // Get GPIO port and pin num
+ obj->port = (PortName)PIN_PORT(pin);
+ obj->pin_num = PIN_POS(pin);
+ // Set pin level as LOW
+ gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0);
+ // Enable gpio interrupt function
+ pinmap_pinout(pin, PinMap_GPIO_IRQ);
+ // Get GPIO irq source
+ obj->irq_src = (CG_INTSrc)obj->irq_id;
+ // Save irq handler
+ hal_irq_handler[obj->irq_src] = handler;
+ // Save irq id
+ channel_ids[obj->irq_src] = id;
+ // Initialize interrupt event as both edges detection
+ obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+ // Clear gpio pending interrupt
+ NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+ // Set interrupt event and enable INTx clear
+ CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
+ core_util_critical_section_exit();
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ // Clear gpio_irq
+ NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+ // Reset interrupt handler
+ hal_irq_handler[obj->irq_src] = NULL;
+ // Reset interrupt id
+ channel_ids[obj->irq_src] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ // Disable GPIO interrupt on obj
+ gpio_irq_disable(obj);
+
+ if (enable) {
+ // Get gpio interrupt event
+ if (event == IRQ_RISE) {
+ if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
+ (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
+ obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+ } else {
+ obj->event = CG_INT_ACTIVE_STATE_RISING;
+ }
+ } else if (event == IRQ_FALL) {
+ if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
+ (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
+ obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+ } else {
+ obj->event = CG_INT_ACTIVE_STATE_FALLING;
+ }
+ } else {
+ error("Not supported event\n");
+ }
+ } else {
+ // Get gpio interrupt event
+ if (event == IRQ_RISE) {
+ if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
+ (obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
+ obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+ } else {
+ obj->event = CG_INT_ACTIVE_STATE_FALLING;
+ }
+ } else if (event == IRQ_FALL) {
+ if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
+ (obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
+ obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+ } else {
+ obj->event = CG_INT_ACTIVE_STATE_RISING;
+ }
+ } else {
+ error("Not supported event\n");
+ }
+ }
+
+ CurrentState = obj->event;
+ if (obj->event != CG_INT_ACTIVE_STATE_INVALID ) {
+ // Set interrupt event and enable INTx clear
+ CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
+ gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0);
+ } else {
+ gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1);
+ }
+
+ // Clear interrupt request
+ NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+ // Enable GPIO interrupt on obj
+ gpio_irq_enable(obj);
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ // Clear and Enable gpio_irq object
+ NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+ NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ // Disable gpio_irq object
+ NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
+}
+
+static void INT_IRQHandler(PinName pin, uint32_t index)
+{
+ PortName port;
+ uint8_t pin_num;
+
+ gpio_pinstate_t data = GPIO_PIN_RESET;
+ pin_num = PIN_POS(pin);
+ port = (PortName)PIN_PORT(pin);
+
+ // Clear interrupt request
+ CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE);
+ // Get pin value
+ gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data);
+
+ switch (data) {
+ // Falling edge detection
+ case 0:
+ hal_irq_handler[index](channel_ids[index], IRQ_FALL);
+ break;
+ // Rising edge detection
+ case 1:
+ hal_irq_handler[index](channel_ids[index], IRQ_RISE);
+ break;
+ default:
+ break;
+ }
+
+ // Clear gpio pending interrupt
+ NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index));
+ // Enable interrupt request
+ CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE);
+}
+
+static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState)
+{
+ uint8_t *ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2));
+ // Clear pending falling and rising edge bit
+ *ptr = CLR_INT_FLAG;
+ *ptr = (ActiveState | NewState);
+ {
+ uint8_t regval = *ptr;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_object.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "txz_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ uint32_t pin_num;
+ uint32_t mask;
+ PinName pin;
+ PortName port;
+} gpio_t;
+
+typedef enum {
+ CG_INT_SRC_0 = 0U,
+ CG_INT_SRC_1,
+ CG_INT_SRC_2,
+ CG_INT_SRC_3,
+ CG_INT_SRC_4,
+ CG_INT_SRC_5,
+ CG_INT_SRC_6,
+ CG_INT_SRC_7,
+ CG_INT_SRC_8,
+ CG_INT_SRC_9,
+ CG_INT_SRC_A,
+ CG_INT_SRC_B,
+ CG_INT_SRC_C,
+ CG_INT_SRC_D,
+ CG_INT_SRC_E,
+ CG_INT_SRC_F
+} CG_INTSrc;
+
+typedef enum {
+ CG_INT_ACTIVE_STATE_L = 0x00U,
+ CG_INT_ACTIVE_STATE_H = 0x02U,
+ CG_INT_ACTIVE_STATE_FALLING = 0x04U,
+ CG_INT_ACTIVE_STATE_RISING = 0x06U,
+ CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U,
+ CG_INT_ACTIVE_STATE_INVALID = 0x0AU
+} CG_INTActiveState;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return (obj->pin != (PinName)NC);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/i2c_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,203 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <string.h>
+#include "i2c_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "txz_i2c_api.h"
+
+#define MAX_I2C_FREQ 1000000
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {PG2, I2C_0, PIN_DATA(7, 2)},
+ {PF2, I2C_1, PIN_DATA(7, 2)},
+ {PG4, I2C_2, PIN_DATA(7, 2)},
+ {PJ6, I2C_3, PIN_DATA(7, 2)},
+ {PJ3, I2C_4, PIN_DATA(7, 2)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {PG3, I2C_0, PIN_DATA(7, 2)},
+ {PF3, I2C_1, PIN_DATA(7, 2)},
+ {PG5, I2C_2, PIN_DATA(7, 2)},
+ {PJ7, I2C_3, PIN_DATA(7, 2)},
+ {PJ2, I2C_4, PIN_DATA(7, 2)},
+ {NC, NC, 0}
+};
+
+// Initialize the I2C peripheral. It sets the default parameters for I2C
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ MBED_ASSERT(obj != NULL);
+
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+
+ MBED_ASSERT((int)i2c_name != NC);
+
+ switch (i2c_name) {
+ case I2C_0:
+ TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; // Enable clock for I2C_0
+ TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G
+ obj->my_i2c.i2c.p_instance = TSB_I2C0;
+ obj->my_i2c.info.irqn = INTI2C0_IRQn;
+ break;
+ case I2C_1:
+ TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; // Enable clock for I2C_1
+ TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; // Enable clock for GPIO F
+ obj->my_i2c.i2c.p_instance = TSB_I2C1;
+ obj->my_i2c.info.irqn = INTI2C1_IRQn;
+ break;
+ case I2C_2:
+ TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; // Enable clock for I2C_2
+ TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G
+ obj->my_i2c.i2c.p_instance = TSB_I2C2;
+ obj->my_i2c.info.irqn = INTI2C2_IRQn;
+ break;
+ case I2C_3:
+ TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; // Enable clock for I2C_3
+ TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J
+ obj->my_i2c.i2c.p_instance = TSB_I2C3;
+ obj->my_i2c.info.irqn = INTI2C3_IRQn;
+ break;
+ case I2C_4:
+ TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; // Enable clock for I2C_4
+ TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J
+ obj->my_i2c.i2c.p_instance = TSB_I2C4;
+ obj->my_i2c.info.irqn = INTI2C4_IRQn;
+ break;
+ default:
+ error("I2C is not available");
+ break;
+ }
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pin_mode(sda, OpenDrain);
+ pin_mode(sda, PullUp);
+
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ pin_mode(scl, OpenDrain);
+ pin_mode(scl, PullUp);
+
+ i2c_reset(obj);
+ i2c_frequency(obj, 100000);
+ I2C_init(&obj->my_i2c.i2c);
+}
+
+// Configure the I2C frequency
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ if (hz <= MAX_I2C_FREQ) {
+ i2c_frequency_t(&obj->my_i2c, hz);
+ } else {
+ error("Failed : Max I2C frequency is 1000000");
+ }
+}
+
+int i2c_start(i2c_t *obj)
+{
+ i2c_start_t(&obj->my_i2c);
+ return TXZ_SUCCESS;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+ i2c_stop_t(&obj->my_i2c);
+ return TXZ_SUCCESS;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+ // Software reset
+ i2c_reset_t(&obj->my_i2c);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ int32_t count = 0;
+
+ count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop);
+
+ return count;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ int32_t count = 0;
+
+ count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop);
+
+ return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ int32_t data = 0;
+
+ data = i2c_byte_read_t(&obj->my_i2c, last);
+
+ return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ int32_t result = 0;
+
+ result = i2c_byte_write_t(&obj->my_i2c, data);
+
+ return result;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ i2c_slave_mode_t(&obj->my_i2c, enable_slave);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+ i2c_slave_address_t(&obj->my_i2c, address);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+ int32_t result = 0;
+
+ result = i2c_slave_receive_t(&obj->my_i2c);
+
+ return result;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ int32_t count = 0;
+
+ count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ int32_t count = 0;
+
+ count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length);
+
+ return count;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/objects.h Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include <stdbool.h>
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "gpio_object.h"
+#include "txz_gpio.h"
+#include "txz_uart.h"
+#include "txz_fuart.h"
+#include "txz_tspi.h"
+#include "txz_t32a.h"
+#include "txz_cg.h"
+#include "txz_driver_def.h"
+#include "adc.h"
+#include "txz_i2c_api.h"
+#include "txz_i2c.h"
+#include "txz_fuart_include.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct port_s {
+ uint32_t mask;
+ PortName port;
+};
+
+struct dac_s {
+ DACName dac;
+ TSB_DA_TypeDef *DACx;
+};
+
+struct serial_s {
+ uint32_t index;
+ uint32_t mode;
+ TSB_UART_TypeDef *UARTx;
+ TSB_FURT_TypeDef *FUARTx;
+ uart_boudrate_t boud_obj;
+ fuart_boudrate_t fboud_obj;
+};
+
+struct pwmout_s {
+ uint32_t divisor;
+ uint32_t type;
+ uint32_t trailing_timing;
+ uint32_t leading_timing;
+ float period;
+ t32a_t p_t32a;
+ PinName pin;
+};
+
+struct spi_s {
+ uint8_t bits;
+ tspi_t p_obj;
+ SPIName module;
+};
+
+struct gpio_irq_s {
+ PortName port;
+ uint8_t pin_num;
+ uint32_t irq_id;
+ CG_INTSrc irq_src;
+ CG_INTActiveState event;
+};
+
+struct flash_s {
+ int flash_inited;
+};
+
+struct analogin_s {
+ adc_t p_adc;
+ PinName pin;
+ ADCName adc;
+ adc_channel_setting_t param;
+};
+
+struct i2c_s {
+ int address;
+ uint32_t index;
+ _i2c_t my_i2c;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/pinmap.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+#include "txz_gpio.h"
+
+#define PIN_FUNC_MAX 8
+
+extern _gpio_t gpio_port_add;
+
+void pin_function(PinName pin, int function)
+{
+ uint32_t port = 0;
+ uint8_t bit = 0;
+ uint8_t func = 0;
+ uint8_t dir = 0;
+
+ // Assert that pin is valid
+ MBED_ASSERT(pin != NC);
+
+ // Calculate pin function and pin direction
+ func = PIN_FUNC(function);
+ dir = PIN_DIR(function);
+ // Calculate port and pin position
+ port = PIN_PORT(pin);
+ bit = PIN_POS(pin);
+
+ // Find function is in range or not
+ if (func <= PIN_FUNC_MAX) {
+ // Set pin function and direction if direction is in range
+ switch (dir) {
+ case PIN_INPUT:
+ // Set pin input
+ gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT);
+ break;
+ case PIN_OUTPUT:
+ // Set pin output
+ gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT);
+ break;
+ case PIN_INOUT:
+ // Set pin both input and output
+ gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT);
+ break;
+ default:
+ break;
+ }
+ } else {
+ // Do nothing
+ }
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+ uint32_t port = 0;
+ uint8_t bit = 0;
+
+ // Assert that pin is valid
+ MBED_ASSERT(pin != NC);
+
+ // Check if function is in range
+ if (mode > OpenDrain) {
+ return;
+ }
+
+ // Calculate port and pin position
+ port = PIN_PORT(pin);
+ bit = PIN_POS(pin);
+
+ // Set pin mode
+ switch (mode) {
+ case PullNone:
+ gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
+ gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
+ gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET);
+ break;
+ case PullUp:
+ gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
+ break;
+ case PullDown:
+ gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
+ break;
+ case OpenDrain:
+ gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET);
+ break;
+ default:
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/port_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "txz_gpio.h"
+#include "pinmap.h"
+
+#define PORT_PIN_NUM (8)
+#define ALT_FUNC_GPIO (0)
+
+extern _gpio_t gpio_port_add;
+static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num);
+
+PinName port_pin(PortName port, int pin_n)
+{
+ PinName pin = NC;
+ pin = (PinName)((port << 3) | pin_n);
+ return pin;
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ uint8_t i = 0;
+
+ // Assert that port is valid
+ MBED_ASSERT(port <= PortY);
+
+ // Store port and port mask for future use
+ obj->port = port;
+ obj->mask = mask;
+
+ // Enable the clock for particular port
+ _gpio_init(&gpio_port_add, obj->port);
+
+ // Set port function and port direction
+ for (i = 0; i < PORT_PIN_NUM; i++) {
+ // If the pin is used
+ if (obj->mask & (1 << i)) {
+ pin_function(port_pin(obj->port, i), dir);
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint8_t i = 0;
+
+ // Assert that port is valid
+ MBED_ASSERT(obj->port <= PortY);
+
+ // Set mode for masked pins
+ for (i = 0; i < PORT_PIN_NUM; i++) {
+ // If the pin is used
+ if (obj->mask & (1 << i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ uint8_t i = 0;
+
+ // Assert that port is valid
+ MBED_ASSERT(obj->port <= PortY);
+
+ for (i = 0; i < PORT_PIN_NUM; i++) {
+ // Set direction for masked pins
+ if (obj->mask & (1 << i)) {
+ gpio_pin_dir(obj, dir, i);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ uint32_t port_data = 0;
+ uint32_t data = 0;
+
+ // Assert that port is valid
+ MBED_ASSERT(obj->port <= PortY);
+
+ // Get current data of port
+ gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
+
+ // Calculate data to write to masked pins
+ data = (port_data & ~obj->mask) | (value & obj->mask);
+
+ // Write data to masked pins of the port
+ gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data);
+}
+
+int port_read(port_t *obj)
+{
+ uint32_t port_data = 0;
+ uint32_t data = 0;
+
+ // Assert that port is valid
+ MBED_ASSERT(obj->port <= PortY);
+
+ // Get current data of port
+ gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
+
+ // Calculate data of masked pins
+ data = port_data & obj->mask;
+
+ return data;
+}
+
+static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num)
+{
+ switch (dir) {
+ case PIN_INPUT:
+ // Set pin input
+ gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT);
+ break;
+ case PIN_OUTPUT:
+ // Set pin output
+ gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT);
+ break;
+ case PIN_INOUT:
+ // Set pin both input and output
+ gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT);
+ break;
+ default:
+ // error("Invalid direction\n");
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/pwmout_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,225 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+
+#define GPIO_CLK_OFFSET 2
+// Because Timer operating frequency is 2.5 MhZ
+#define CALCULATE_RGC1_VAL 2.5
+
+static const PinMap PinMap_PWM[] = {
+ {PA5, PWM_0, PIN_DATA(5, 1)},
+ {PB2, PWM_1, PIN_DATA(5, 1)},
+ {PB4, PWM_2, PIN_DATA(5, 1)},
+ {PD2, PWM_3, PIN_DATA(5, 1)},
+ {PD4, PWM_4, PIN_DATA(5, 1)},
+ {PE1, PWM_5, PIN_DATA(5, 1)},
+ {PE6, PWM_6, PIN_DATA(5, 1)},
+ {PC2, PWM_7, PIN_DATA(5, 1)},
+ {PL6, PWM_8, PIN_DATA(3, 1)},
+ {PC4, PWM_9, PIN_DATA(5, 1)},
+ {PM2, PWM_10, PIN_DATA(3, 1)},
+ {PU0, PWM_11, PIN_DATA(3, 1)},
+ {PU6, PWM_12, PIN_DATA(3, 1)},
+ {NC, NC, 0}
+};
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+ // Determine the pwm channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+
+ // Assert input is valid
+ MBED_ASSERT(pwm != (PWMName)NC);
+
+ switch (pwm) {
+ case PWM_0:
+ obj->p_t32a.p_instance = TSB_T32A1;
+ // Clock enable of T32A ch01
+ TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE;
+ break;
+ case PWM_1:
+ obj->p_t32a.p_instance = TSB_T32A2;
+ // Clock enable of T32A ch02
+ TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE;
+ break;
+ case PWM_2:
+ obj->p_t32a.p_instance = TSB_T32A3;
+ // Clock enable of T32A ch03
+ TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE;
+ break;
+ case PWM_3:
+ obj->p_t32a.p_instance = TSB_T32A4;
+ // Clock enable of T32A ch04
+ TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE;
+ break;
+ case PWM_4:
+ obj->p_t32a.p_instance = TSB_T32A5;
+ // Clock enable of T32A ch05
+ TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE;
+ break;
+ case PWM_5:
+ obj->p_t32a.p_instance = TSB_T32A6;
+ // Clock enable of T32A ch06
+ TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE;
+ break;
+ case PWM_6:
+ obj->p_t32a.p_instance = TSB_T32A7;
+ // Clock enable of T32A ch07
+ TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE;
+ break;
+ case PWM_7:
+ obj->p_t32a.p_instance = TSB_T32A8;
+ // Clock enable of T32A ch08
+ TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE;
+ break;
+ case PWM_8:
+ obj->p_t32a.p_instance = TSB_T32A9;
+ // Clock enable of T32A ch09
+ TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE;
+ break;
+ case PWM_9:
+ obj->p_t32a.p_instance = TSB_T32A10;
+ // Clock enable of T32A ch10
+ TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE;
+ break;
+ case PWM_10:
+ obj->p_t32a.p_instance = TSB_T32A11;
+ // Clock enable of T32A ch11
+ TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE;
+ break;
+ case PWM_11:
+ obj->p_t32a.p_instance = TSB_T32A12;
+ // Clock enable of T32A ch12
+ TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE;
+ break;
+ case PWM_12:
+ obj->p_t32a.p_instance = TSB_T32A13;
+ // Clock enable of T32A ch13
+ TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE;
+ break;
+ default:
+ obj->p_t32a.p_instance = NULL;
+ break;
+ }
+
+ if (obj->p_t32a.p_instance == NULL) {
+ return;
+ }
+
+ // Enable clock for GPIO port.
+ TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET));
+
+ // Set pin function as PWM
+ pinmap_pinout(pin, PinMap_PWM);
+
+ // Default to 20ms, 0% duty cycle
+ pwmout_period_ms(obj, 20);
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+ // Stop PWM
+ obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
+ obj->trailing_timing = TXZ_DISABLE;
+ obj->leading_timing = TXZ_DISABLE;
+ obj->p_t32a.p_instance = NULL;
+}
+
+void pwmout_write(pwmout_t *obj, float value)
+{
+ // Stop PWM
+ obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
+
+ if (value <= 0.0f) {
+ value = TXZ_DISABLE;
+ } else if (value >= 1.0f) {
+ value = TXZ_ENABLE;
+ }
+
+ // Store the new leading_timing value
+ obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value);
+
+ // Setting T32A_RGA0 register
+ obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
+
+ // Start PWM
+ obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+ float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
+ return duty_cycle;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+ pwmout_period_us(obj, (int)(seconds * 1000000.0f));
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+ pwmout_period_us(obj, (ms * 1000));
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+ uint32_t prscl = 0;
+ float duty_cycle = 0;
+ float seconds = (float)((us) / 1000000.0f);
+
+ obj->period = seconds;
+ // Restore the duty-cycle
+ duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
+ prscl = T32A_PRSCLx_32;
+
+ obj->trailing_timing = (us * CALCULATE_RGC1_VAL);
+ obj->leading_timing = ((obj->trailing_timing)- (obj->trailing_timing * duty_cycle));
+
+ obj->p_t32a.p_instance->MOD = T32A_MODE_32;
+ obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
+ obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx);
+ obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ |
+ T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ);
+ obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
+ obj->p_t32a.p_instance->RGC1 = obj->trailing_timing;
+ obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE;
+ obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET);
+ obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, (seconds * 1000000.0f));
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, (ms * 1000));
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+ float seconds = 0;
+ float value = 0;
+
+ seconds = (float)(us / 1000000.0f);
+ value = (((seconds / obj->period) * 100.0f) / 100.0f);
+ pwmout_write(obj, value);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/serial_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,399 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_error.h"
+#include "serial_api.h"
+#include "pinmap.h"
+
+#define UART_NUM 8
+#define UART_ENABLE_RX ((uint32_t)0x00000001)
+#define UART_ENABLE_TX ((uint32_t)0x00000002)
+#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
+#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
+#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
+#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
+#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
+#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
+#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
+#define FUART_ENABLE_RX ((uint32_t)0x00000200)
+#define FUART_ENABLE_TX ((uint32_t)0x00000100)
+#define BAUDRATE_DEFAULT (9600)
+#define CLR_REGISTER (0x00)
+
+static const PinMap PinMap_UART_TX[] = {
+ {PE3, SERIAL_0, PIN_DATA(7, 1)},
+ {PH1, SERIAL_1, PIN_DATA(3, 1)},
+ {PG1, SERIAL_2, PIN_DATA(3, 1)},
+ {PU7, SERIAL_3, PIN_DATA(7, 1)},
+ {PU0, SERIAL_4, PIN_DATA(7, 1)},
+ {PJ1, SERIAL_5, PIN_DATA(3, 1)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {PE2, SERIAL_0, PIN_DATA(7, 0)},
+ {PH0, SERIAL_1, PIN_DATA(3, 0)},
+ {PG0, SERIAL_2, PIN_DATA(3, 0)},
+ {PU6, SERIAL_3, PIN_DATA(7, 0)},
+ {PU1, SERIAL_4, PIN_DATA(7, 0)},
+ {PJ0, SERIAL_5, PIN_DATA(3, 0)},
+ {NC, NC, 0}
+};
+
+static int serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void uart_swreset(TSB_UART_TypeDef *UARTx);
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ int is_stdio_uart = 0;
+ obj->mode = 0;
+ cg_t paramCG;
+ paramCG.p_instance = TSB_CG;
+ uart_clock_t prescal = {0};
+
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
+
+ MBED_ASSERT((int)uart_name != NC);
+
+ obj->index = uart_name;
+ // Initialize UART instance
+ switch (uart_name) {
+ case SERIAL_0:
+ obj->UARTx = TSB_UART0;
+ // Enable clock for UART0 and Port E
+ TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE;
+ break;
+ case SERIAL_1:
+ obj->UARTx = TSB_UART1;
+ // Enable clock for UART1 and Port H
+ TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB09 = TXZ_ENABLE;
+ break;
+ case SERIAL_2:
+ obj->UARTx = TSB_UART2;
+ // Enable clock for UART2 and Port G
+ TSB_CG_FSYSMENA_IPMENA25 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE;
+ break;
+ case SERIAL_3:
+ obj->UARTx = TSB_UART3;
+ // Enable clock for UART3 and Port U
+ TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE;
+ break;
+ case SERIAL_4:
+ obj->UARTx = TSB_UART4;
+ // Enable clock for UART4 and Port U
+ TSB_CG_FSYSMENA_IPMENA27 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE;
+ break;
+ case SERIAL_5:
+ obj->UARTx = TSB_UART5;
+ // Enable clock for UART5 and Port J
+ TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE;
+ break;
+ default:
+ break;
+ }
+
+ // Set alternate function
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ if (tx != NC && rx != NC) {
+ obj->mode = UART_ENABLE_RX | UART_ENABLE_TX;
+ } else {
+ if (tx != NC) {
+ obj->mode = UART_ENABLE_TX;
+ } else {
+ if (rx != NC) {
+ obj->mode = UART_ENABLE_RX;
+ }
+ }
+ }
+
+ // Software reset
+ uart_swreset(obj->UARTx);
+
+ // Mbed default configurations
+ obj->UARTx->CR0 |= (1U); // Data lengh 8 bit No parity one stop bit
+ prescal.prsel = UART_PLESCALER_1;
+ uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj);
+
+ obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));
+ obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO
+ obj->UARTx->TRANS |= obj->mode; // Enable TX RX block.
+ obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE);
+
+ is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ obj->UARTx->TRANS = CLR_REGISTER;
+ obj->UARTx->CR0 = CLR_REGISTER;
+ obj->UARTx->CR1 = CLR_REGISTER;
+ obj->UARTx = CLR_REGISTER;
+ uart_swreset(obj->UARTx);
+ obj->index = (uint32_t)NC;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ cg_t paramCG;
+ paramCG.p_instance = TSB_CG;
+ uart_clock_t prescal;
+ prescal.prsel = UART_PLESCALER_1;
+ uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj);
+ obj->UARTx->BRD = CLR_REGISTER; // Clear BRD register
+ obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ uint32_t parity_check = 0;
+ uint32_t data_length = 0;
+ uint32_t tmp = 0;
+ uint32_t sblen = 0;
+
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
+ MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
+
+ parity_check = ((parity == ParityOdd) ? 1 :((parity == ParityEven) ? 3 : 0));
+ data_length = (data_bits == 8 ? 1 :((data_bits == 7) ? 0 : 2));
+ sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits
+ tmp = ((sblen << 4) |(parity_check << 2) | data_length);
+ obj->UARTx->CR0 = tmp;
+}
+
+// INTERRUPT HANDLING
+void INTUART0RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
+}
+
+void INTUART0TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
+}
+
+void INTUART1RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
+}
+
+void INTUART1TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
+}
+
+void INTUART2RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
+}
+
+void INTUART2TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
+}
+
+void INTUART3RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_3], RxIrq);
+}
+
+void INTUART3TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_3], TxIrq);
+}
+
+void INTUART4RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_4], RxIrq);
+}
+
+void INTUART4TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_4], TxIrq);
+}
+
+void INTUART5RX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_5], RxIrq);
+}
+
+void INTUART5TX_IRQHandler(void)
+{
+ irq_handler(serial_irq_ids[SERIAL_5], TxIrq);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+
+ switch (obj->index) {
+ case SERIAL_0:
+ if (irq == RxIrq) {
+ irq_n = INTUART0RX_IRQn;
+ } else {
+ irq_n = INTUART0TX_IRQn;
+ }
+ break;
+ case SERIAL_1:
+ if (irq == RxIrq) {
+ irq_n = INTUART1RX_IRQn;
+ } else {
+ irq_n = INTUART1TX_IRQn;
+ }
+ break;
+ case SERIAL_2:
+ if (irq == RxIrq) {
+ irq_n = INTUART2RX_IRQn;
+ } else {
+ irq_n = INTUART2TX_IRQn;
+ }
+ break;
+ case SERIAL_3:
+ if (irq == RxIrq) {
+ irq_n = INTUART3RX_IRQn;
+ } else {
+ irq_n = INTUART3TX_IRQn;
+ }
+ break;
+ case SERIAL_4:
+ if (irq == RxIrq) {
+ irq_n = INTUART4RX_IRQn;
+ } else {
+ irq_n = INTUART4TX_IRQn;
+ }
+ break;
+ case SERIAL_5:
+ if (irq == RxIrq) {
+ irq_n = INTUART5RX_IRQn;
+ } else {
+ irq_n = INTUART5TX_IRQn;
+ }
+ break;
+ default:
+ break;
+ }
+
+ NVIC_ClearPendingIRQ(irq_n);
+
+ if (enable) {
+ NVIC_EnableIRQ(irq_n);
+ } else {
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+int serial_getc(serial_t *obj)
+{
+ int data = 0;
+
+ while (!serial_readable(obj)) { // Wait until Rx buffer is full
+ // Do nothing
+ }
+
+ // Read Data Register
+ data = (obj->UARTx->DR & 0xFFU);
+ obj->UARTx->SR |= (1U << 6); // Clear RXEND flag
+
+ return data;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ while (!serial_writable(obj)) {
+ // Do nothing
+ }
+
+ // Write Data Register
+ obj->UARTx->DR = (c & 0xFF);
+
+ while ((obj->UARTx->SR & (1U << 14)) == 0) {
+ // Do nothing
+ }
+
+ obj->UARTx->SR |= (1U << 14); // Clear TXEND flag
+}
+
+int serial_readable(serial_t *obj)
+{
+ int ret = 0;
+
+ if ((obj->UARTx->SR & 0x000F) != 0) {
+ ret = 1;
+ }
+
+ return ret;
+}
+
+int serial_writable(serial_t *obj)
+{
+ int ret = 0;
+
+ if ((obj->UARTx->SR & 0x8000) == 0) {
+ ret = 1;
+ }
+
+ return ret;
+}
+
+// Pause transmission
+void serial_break_set(serial_t *obj)
+{
+ obj->UARTx->TRANS |= 0x08;
+}
+
+// Switch to normal transmission
+void serial_break_clear(serial_t *obj)
+{
+ obj->UARTx->TRANS &= ~(0x08);
+}
+
+static void uart_swreset(TSB_UART_TypeDef *UARTx)
+{
+ while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
+ // No process
+ }
+
+ UARTx->SWRST = UARTxSWRST_SWRST_10;
+ UARTx->SWRST = UARTxSWRST_SWRST_01;
+
+ while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
+ // No process
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/sleep.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+
+// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16
+#define CG_WUODR_INT_5MS ((uint16_t)0x0C34)
+#define CG_STBY_MODE_IDLE 0x0
+#define CG_STBY_MODE_STOP1 0x1
+#define EXTERNEL_OSC_MASK 0xFFFFFFF1
+#define SIWDT_DISABLE 0xB1
+#define WUPT_LOWER_MASK 0x000F
+#define WUPT_UPPER_MASK 0xFFF0
+
+static void external_losc_enable(void);
+
+void hal_sleep(void)
+{
+ // Set low power consumption mode IDLE
+ TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
+
+ // Enter idle mode
+ __DSB();
+ __WFI();
+}
+
+void hal_deepsleep(void)
+{
+ uint32_t wupt_lower = 0;
+ uint32_t wupt_upper = 0;
+ uint32_t tmp = 0;
+
+ TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE;
+
+ TSB_SIWD0->EN = TXZ_DISABLE;
+ TSB_SIWD0->CR = SIWDT_DISABLE;
+
+
+ while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) {
+ // Flash wait
+ }
+
+ while (TSB_CG_WUPHCR_WUEF) {
+ // Wait for end of Warming-up for IHOSC1
+ }
+
+ TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE;
+ wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U);
+ wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U);
+ TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
+ TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
+ TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE;
+
+
+ while (TSB_CG_PLL0SEL_PLL0ST) {
+ // Wait for PLL status of fsys until off state(fosc=0)
+ }
+
+ // Stop PLL of fsys
+ TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE;
+ TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE;
+ TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE;
+
+ while (TSB_CG_OSCCR_OSCF) {
+ // Wait for fosc status until IHOSC1 = 0
+ }
+
+ tmp = TSB_CG->OSCCR;
+ tmp &= EXTERNEL_OSC_MASK;
+ TSB_CG->OSCCR = tmp;
+
+
+ // Enter stop1 mode
+ __DSB();
+ __WFI();
+
+ // Switch over from IHOSC to EHOSC
+ // After coming out off sleep mode, Restore the clock setting to EHOSC.
+ external_losc_enable();
+}
+
+static void external_losc_enable(void)
+{
+ uint32_t wupt_lower = 0;
+ uint32_t wupt_upper = 0;
+
+ // Enable high-speed oscillator
+ TSB_CG->OSCCR |= (TXZ_ENABLE << 1);
+
+ // Select internal(fIHOSC) as warm-up clock
+ wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U);
+ wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U);
+ TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
+
+ // Start warm-up
+ TSB_CG->WUPHCR |= TXZ_ENABLE;
+
+ // Wait until EHOSC become stable
+ while ((TSB_CG->WUPHCR & 0x0002)) {
+ // Do nothing
+ }
+
+ // Set fosc source
+ TSB_CG->OSCCR |= (1 << 8);
+
+ // Wait for <OSCSEL> to become "1"
+ while (!((TSB_CG->OSCCR & 0x200)>> 9)) {
+ // Do nothing
+ }
+
+ // Stop IHOSC
+ TSB_CG->OSCCR &= ~TXZ_ENABLE;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/spi_api.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,335 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "spi_api.h"
+#include "mbed_error.h"
+#include "txz_tspi.h"
+#include "pinmap.h"
+
+#define TIMEOUT (5000)
+#define BAUDRATE_1MHZ_BRS (0x0A)
+#define BAUDRATE_1MHZ_BRCK (0x30)
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {PA1, SPI_0, PIN_DATA(7, 1)},
+ {PL1, SPI_1, PIN_DATA(7, 1)},
+ {PA6, SPI_2, PIN_DATA(7, 1)},
+ {PK6, SPI_3, PIN_DATA(4, 1)},
+ {PD1, SPI_4, PIN_DATA(4, 1)},
+ {PV6, SPI_5, PIN_DATA(4, 1)},
+ {PM2, SPI_6, PIN_DATA(6, 1)},
+ {PM5, SPI_7, PIN_DATA(6, 1)},
+ {PW1, SPI_8, PIN_DATA(4, 1)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {PA3, SPI_0, PIN_DATA(7, 1)},
+ {PL3, SPI_1, PIN_DATA(7, 1)},
+ {PA4, SPI_2, PIN_DATA(7, 1)},
+ {PK4, SPI_3, PIN_DATA(4, 1)},
+ {PD3, SPI_4, PIN_DATA(4, 1)},
+ {PV5, SPI_5, PIN_DATA(4, 1)},
+ {PM0, SPI_6, PIN_DATA(6, 1)},
+ {PM7, SPI_7, PIN_DATA(6, 1)},
+ {PW3, SPI_8, PIN_DATA(4, 1)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {PA2, SPI_0, PIN_DATA(7, 0)},
+ {PL2, SPI_1, PIN_DATA(7, 0)},
+ {PA5, SPI_2, PIN_DATA(7, 0)},
+ {PK5, SPI_3, PIN_DATA(4, 0)},
+ {PD2, SPI_4, PIN_DATA(4, 0)},
+ {PV4, SPI_5, PIN_DATA(4, 0)},
+ {PM1, SPI_6, PIN_DATA(6, 0)},
+ {PM6, SPI_7, PIN_DATA(6, 0)},
+ {PW2, SPI_8, PIN_DATA(4, 0)},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {PA0, SPI_0, PIN_DATA(7, 1)},
+ {PL0, SPI_1, PIN_DATA(7, 1)},
+ {PA7, SPI_2, PIN_DATA(7, 1)},
+ {PK7, SPI_3, PIN_DATA(4, 1)},
+ {PD0, SPI_4, PIN_DATA(4, 1)},
+ {PV7, SPI_5, PIN_DATA(4, 1)},
+ {PM3, SPI_6, PIN_DATA(6, 1)},
+ {PM4, SPI_7, PIN_DATA(6, 1)},
+ {PW0, SPI_8, PIN_DATA(4, 1)},
+ {NC, NC, 0}
+};
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ // Check pin parameters
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
+ obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT((int)obj->module!= NC);
+
+ // Identify SPI module to use
+ switch ((int)obj->module) {
+ case SPI_0:
+ obj->p_obj.p_instance = TSB_TSPI0;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
+ break;
+ case SPI_1:
+ obj->p_obj.p_instance = TSB_TSPI1;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE;
+ break;
+ case SPI_2:
+ obj->p_obj.p_instance = TSB_TSPI2;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
+ break;
+ case SPI_3:
+ obj->p_obj.p_instance = TSB_TSPI3;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE;
+ break;
+ case SPI_4:
+ obj->p_obj.p_instance = TSB_TSPI4;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE;
+ break;
+ case SPI_5:
+ obj->p_obj.p_instance = TSB_TSPI5;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSENA_IPENA09 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE;
+ break;
+ case SPI_6:
+ obj->p_obj.p_instance = TSB_TSPI6;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE;
+ break;
+ case SPI_7:
+ obj->p_obj.p_instance = TSB_TSPI7;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE;
+ break;
+ case SPI_8:
+ obj->p_obj.p_instance = TSB_TSPI8;
+ // Enable clock for particular Port and SPI
+ TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE;
+ TSB_CG_FSYSMENB_IPMENB20 = TXZ_ENABLE;
+ break;
+ default:
+ obj->p_obj.p_instance = NULL;
+ obj->module = (SPIName)NC;
+ error("Cannot found SPI module corresponding with input pins.");
+ break;
+ }
+
+ // Pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+
+ // Default configurations 8 bit, 1Mhz frequency
+ // Control 1 configurations
+ obj->p_obj.init.id = (uint32_t)obj->module;
+ obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
+ obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication
+ obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
+ obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // Master mode operation
+ obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
+ obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid
+ obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // Transfer single frame at a time contineously
+
+ // Control 2 configurations
+ obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
+ obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // When slave underruns TxD fixed to low
+ obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_SET;
+ obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // Transmit FIFO Level
+ obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // Receive FIFO Level
+ obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
+ obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
+ obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
+ obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
+ obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
+ obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
+ obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
+
+ // Control 3 configurations
+ obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // Transmit buffer clear
+ obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // Receive buffer clear
+
+ // Baudrate settings - 1 Mhz default
+ obj->p_obj.init.brd.brck = BAUDRATE_1MHZ_BRCK;
+ obj->p_obj.init.brd.brs = BAUDRATE_1MHZ_BRS;
+
+ // Format Control 0 settings
+ obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
+ obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
+ obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
+
+ // Special control on polarity of signal and generation timing
+ obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
+ obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
+ obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
+ obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
+ obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
+ obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
+ obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
+
+ obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
+ obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
+
+ // Format Control 1 settings tspi_fmtr1_t
+ obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
+ obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
+
+ obj->bits = (uint8_t)TSPI_DATA_LENGTH_8;
+
+ // Initialize SPI
+ tspi_init(&obj->p_obj);
+}
+
+void spi_free(spi_t *obj)
+{
+ tspi_deinit(&obj->p_obj);
+ obj->module = (SPIName)NC;
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ MBED_ASSERT((slave == 0U)); // 0: master mode, 1: slave mode
+ MBED_ASSERT((bits >= 8) && (bits <= 32));
+
+ obj->bits = bits;
+ obj->p_obj.init.fmr0.fl = (bits << 24);
+
+ if ((mode >> 1) & 0x1) {
+ obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
+ } else {
+ obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
+ }
+
+ if (mode & 0x1) {
+ obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
+ } else {
+ obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
+ }
+
+ tspi_init(&obj->p_obj);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ SystemCoreClockUpdate();
+ uint8_t brs = 0;
+ uint8_t brck = 0;
+ uint16_t prsck = 1;
+ uint64_t fscl = 0;
+ uint64_t tmp_fscl = 0;
+ uint64_t fx = 0;
+ uint64_t tmpvar = SystemCoreClock / 2;
+
+ for (prsck = 1; prsck <= 512; prsck *= 2) {
+ fx = ((uint64_t)tmpvar / prsck);
+ for (brs = 1; brs <= 16; brs++) {
+ fscl = fx /brs;
+ if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
+ tmp_fscl = fscl;
+ obj->p_obj.init.brd.brck = (brck << 4);
+ if (brs == 16) {
+ obj->p_obj.init.brd.brs = 0;
+ } else {
+ obj->p_obj.init.brd.brs = brs;
+ }
+ }
+ }
+ brck ++;
+ }
+
+ tspi_init(&obj->p_obj);
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+ uint8_t ret_value = 0;
+
+ tspi_transmit_t send_obj;
+ tspi_receive_t rec_obj;
+
+ // Transmit data
+ send_obj.tx8.p_data = (uint8_t *)&value;
+ send_obj.tx8.num = 1;
+ tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT);
+
+ // Read received data
+ rec_obj.rx8.p_data = &ret_value;
+ rec_obj.rx8.num = 1;
+ tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT);
+
+ return ret_value;
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+ char *rx_buffer, int rx_length, char write_fill)
+{
+ int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+ for (int i = 0; i < total; i++) {
+ char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+ char in = spi_master_write(obj, out);
+ if (i < rx_length) {
+ rx_buffer[i] = in;
+ }
+ }
+
+ return total;
+}
+
+int spi_busy(spi_t *obj)
+{
+ int ret = 1;
+ uint32_t status = 0;
+
+ tspi_get_status(&obj->p_obj, &status);
+
+ if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
+ ret = 0;
+ }
+
+ return ret;
+}
+
+uint8_t spi_get_module(spi_t *obj)
+{
+ return (uint8_t)(obj->module);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+#include "TMPM4G9.h"
+#include "txz_t32a.h"
+
+#define CLR_TIMER_INT_FLAG (uint8_t)0x41
+
+static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
+
+const ticker_info_t* us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ 2500000,
+ 32
+ };
+ return &info;
+}
+
+// Initialize us_ticker
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) {
+ us_ticker_disable_interrupt();
+ return;
+ }
+ us_ticker_inited = 1;
+
+ // Enable clock for T32A0
+ TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE;
+
+ // T32A ch0 TimerC Reg Match/Over Flow/Under Flow
+ TSB_IB->IMC006 = TXZ_ENABLE;
+
+ // Configure Timer T32A0
+ TSB_T32A0->MOD = T32A_MODE_32;
+ TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
+ TSB_T32A0->CRC = T32A_PRSCLx_32;
+ TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
+ TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
+
+ NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
+}
+
+uint32_t us_ticker_read(void)
+{
+ uint32_t ret_val = 0;
+
+ if (!us_ticker_inited) {
+ us_ticker_init();
+ }
+
+ ret_val = (TSB_T32A0->TMRC);
+ return ret_val;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
+ TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
+ TSB_T32A0->RGC1 = timestamp ;
+ NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
+ TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+ NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn);
+ NVIC_EnableIRQ(INTT32A00_A_CT_IRQn);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ // Disable interrupts in NVIC
+ TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
+ NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
+ NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
+ NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
+}
+
+void us_ticker_free(void)
+{
+ TSB_T32A0->RUNC = T32A_RUN_DISABLE;
+ TSB_IB->IMC006 = CLR_TIMER_INT_FLAG;
+ NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn);
+ NVIC_DisableIRQ(INTT32A00_A_CT_IRQn);
+ TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE;
+}
--- a/targets/TARGET_TOSHIBA/mbed_rtx.h Thu Sep 06 13:40:20 2018 +0100 +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h Thu Nov 08 11:46:34 2018 +0000 @@ -22,6 +22,10 @@ #ifndef INITIAL_SP #define INITIAL_SP (0x20004000UL) #endif +#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#endif +#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 #endif @@ -30,6 +34,10 @@ #ifndef INITIAL_SP #define INITIAL_SP (0x20080000UL) #endif +#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#endif +#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 #endif @@ -41,4 +49,12 @@ #endif +#if defined(TARGET_TMPM4G9) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20030000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -115,11 +115,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Nov 08 11:46:34 2018 +0000
@@ -8,9 +8,9 @@
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
-/*-Sizes-*/
+/*-Heap 1/4 of ram and stack 1/8-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
-define symbol __ICFEDIT_size_heap__ = 0x00000400;
+define symbol __ICFEDIT_size_heap__ = 0x00000C00;
/**** End of ICF editor section. ###ICF###*/
@@ -28,4 +28,4 @@
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -115,11 +115,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Nov 08 11:46:34 2018 +0000
@@ -8,9 +8,9 @@
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
-/*-Sizes-*/
+/*-Heap 1/4 of ram and stack 1/8-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
-define symbol __ICFEDIT_size_heap__ = 0x00000400;
+define symbol __ICFEDIT_size_heap__ = 0x00000C00;
/**** End of ICF editor section. ###ICF###*/
@@ -28,4 +28,4 @@
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/W7500.ld Thu Nov 08 11:46:34 2018 +0000
@@ -85,13 +85,13 @@
*(vtable)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
@@ -99,7 +99,7 @@
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -107,7 +107,7 @@
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
- . = ALIGN(4);
+ . = ALIGN(8);
/* All data end */
__data_end__ = .;
@@ -115,11 +115,11 @@
.bss :
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf Thu Nov 08 11:46:34 2018 +0000
@@ -8,9 +8,9 @@
define symbol __ICFEDIT_region_ROM_end__ = 0x00020000;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004000;
-/*-Sizes-*/
+/*-Heap 1/4 of ram and stack 1/8-*/
define symbol __ICFEDIT_size_cstack__ = 0x00000400;
-define symbol __ICFEDIT_size_heap__ = 0x00000400;
+define symbol __ICFEDIT_size_heap__ = 0x00000C00;
/**** End of ICF editor section. ###ICF###*/
@@ -28,4 +28,4 @@
place in ROM_region { readonly };
place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
+ block CSTACK, block HEAP };
--- a/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -130,3 +130,8 @@
{
DUALTIMER_IntClear(TIMER_0);
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_GCC_ARM/hi2110.ld Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_GCC_ARM/hi2110.ld Thu Nov 08 11:46:34 2018 +0000
@@ -24,7 +24,7 @@
/* Code and const data */
.text :
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(.text)
*(.text*)
@@ -77,20 +77,20 @@
*(.data)
*(.data*)
- . = ALIGN(4);
+ . = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
+ . = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
@@ -105,12 +105,12 @@
/* Uninitialised data */
.bss (NOLOAD):
{
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
- . = ALIGN(4);
+ . = ALIGN(8);
__bss_end__ = .;
} > RAM
@@ -118,7 +118,7 @@
.resume (NOLOAD):
{
- . = ALIGN(4);
+ . = ALIGN(8);
*(preserve)
} > RAM
@@ -161,7 +161,7 @@
/* The size of this section (256 bytes) is already taken off the size of RAM so there is no danger of the heap overflowing into it */
.ipc_mailbox (NOLOAD):
{
- . = ALIGN(4);
+ . = ALIGN(8);
__ipc_mailbox_start__ = .;
*(.ipc_mailbox)
*(.ipc_mailbox*)
--- a/targets/TARGET_ublox/TARGET_HI2110/lp_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/lp_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -346,3 +346,8 @@
g_user_interrupt_pending = false;
g_user_interrupt_set = false;
}
+
+void lp_ticker_free(void)
+{
+
+}
--- a/targets/TARGET_ublox/TARGET_HI2110/us_ticker.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/us_ticker.c Thu Nov 08 11:46:34 2018 +0000
@@ -251,3 +251,8 @@
g_timer_extra_loops_required = 0;
g_us_overflow_increment = 0;
}
+
+void us_ticker_free(void)
+{
+
+}
--- a/targets/targets.json Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/targets.json Thu Nov 08 11:46:34 2018 +0000
@@ -72,7 +72,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "small",
"release_versions": ["2"],
@@ -131,7 +131,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
@@ -143,7 +143,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"release_versions": ["2"],
@@ -155,7 +155,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC11U35FHI33/501"
@@ -169,7 +169,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
"device_name": "LPC11U35FHI33/501"
@@ -180,7 +180,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"default_lib": "small",
"device_name": "LPC11U37FBD64/501"
},
@@ -195,7 +195,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
@@ -207,7 +207,7 @@
"core": "Cortex-M0+",
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11U6X"],
- "supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"detect_code": ["1168"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI"],
@@ -229,7 +229,7 @@
"core": "Cortex-M3",
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC15XX"],
- "supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"detect_code": ["1549"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
@@ -241,13 +241,18 @@
"inherits": ["LPCTarget"],
"core": "Cortex-M3",
"extra_labels": ["NXP", "LPC176X", "MBED_LPC1768", "NXP_EMAC"],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"detect_code": ["1010"],
- "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+ "device_has": ["RTC", "USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
- "features": ["LWIP"],
"device_name": "LPC1768",
"bootloader_supported": true,
+ "config": {
+ "us-ticker-timer": {
+ "help": "Chooses which timer (0-3) to use for us_ticker.c",
+ "value": 3
+ }
+ },
"overrides": {
"network-default-interface-type": "ETHERNET"
}
@@ -259,13 +264,12 @@
"ARCH_PRO": {
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
"macros": ["TARGET_LPC1768"],
"inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
- "features": ["LWIP"],
"device_name": "LPC1768",
"bootloader_supported": true,
"overrides": {
@@ -275,7 +279,7 @@
"UBLOX_C027": {
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
"config": {
"modem_is_on_board": {
@@ -293,7 +297,6 @@
"inherits": ["LPCTarget"],
"device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
- "features": ["LWIP"],
"device_name": "LPC1768",
"bootloader_supported": true,
"overrides": {
@@ -303,7 +306,7 @@
"XBED_LPC1768": {
"inherits": ["LPCTarget"],
"core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
"macros": ["TARGET_LPC1768"],
"detect_code": ["1010"],
@@ -341,7 +344,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC82X"],
"is_disk_virtual": true,
- "supported_toolchains": ["uARM", "GCC_ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
"inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
@@ -364,12 +367,11 @@
"core": "Cortex-M4F",
"extra_labels": ["NXP", "LPC408X", "NXP_EMAC"],
"is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_CR", "GCC_ARM", "IAR"],
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"post_binary_hook": {
"function": "LPC4088Code.binary_hook"
},
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
- "features": ["LWIP"],
"device_name": "LPC4088FBD144",
"overrides": {
"network-default-interface-type": "ETHERNET"
@@ -387,7 +389,7 @@
"inherits": ["LPCTarget"],
"core": "Cortex-M4F",
"extra_labels": ["NXP", "LPC43XX", "LPC4330"],
- "supported_toolchains": ["ARM", "GCC_CR", "IAR", "GCC_ARM"],
+ "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
"device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC4330"
},
@@ -395,7 +397,7 @@
"inherits": ["LPCTarget"],
"core": "Cortex-M0",
"extra_labels": ["NXP", "LPC43XX", "LPC4330"],
- "supported_toolchains": ["ARM", "GCC_CR", "IAR"],
+ "supported_toolchains": ["ARM", "IAR"],
"device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
},
"LPC4337": {
@@ -412,7 +414,7 @@
"core": "Cortex-M3",
"extra_labels": ["NXP", "LPC43XX"],
"public": false,
- "supported_toolchains": ["ARM", "GCC_CR", "IAR"]
+ "supported_toolchains": ["ARM", "IAR"]
},
"LPC11U37H_401": {
"supported_form_factors": ["ARDUINO"],
@@ -420,7 +422,7 @@
"default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
"inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small",
@@ -522,7 +524,7 @@
"macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0231"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
"device_name": "MK22DN512xxx5"
},
"K22F": {
@@ -555,7 +557,7 @@
"is_disk_virtual": true,
"inherits": ["Target"],
"detect_code": ["0262"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "MKL43Z256xxx4"
},
@@ -568,13 +570,14 @@
"is_disk_virtual": true,
"inherits": ["Target"],
"detect_code": ["0218"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "MKL82Z128xxx7"
},
"USENSE": {
"inherits": ["KL82Z"],
"extra_labels_remove": ["FRDM"],
+ "device_has_remove": ["QSPI"],
"supported_form_factors": []
},
"KW24D": {
@@ -586,10 +589,13 @@
"macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0250"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "802_15_4_PHY"],
"release_versions": ["2", "5"],
"device_name": "MKW24D512xxx5",
- "bootloader_supported": true
+ "bootloader_supported": true,
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ }
},
"KW41Z": {
"supported_form_factors": ["ARDUINO"],
@@ -600,7 +606,7 @@
"macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0201"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "MKW41Z512xxx4"
},
@@ -623,6 +629,7 @@
},
"K64F": {
"supported_form_factors": ["ARDUINO"],
+ "components": ["SD"],
"core": "Cortex-M4F",
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F", "Freescale_EMAC"],
@@ -631,7 +638,7 @@
"inherits": ["Target"],
"detect_code": ["0240"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "CRC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
- "features": ["LWIP", "STORAGE"],
+ "features": ["STORAGE"],
"release_versions": ["2", "5"],
"device_name": "MK64FN1M0xxx12",
"bootloader_supported": true,
@@ -639,6 +646,14 @@
"network-default-interface-type": "ETHERNET"
}
},
+ "SDT64B": {
+ "inherits": ["K64F"],
+ "extra_labels_add": ["K64F"],
+ "extra_labels_remove": ["FRDM"],
+ "components_remove": ["SD"],
+ "supported_form_factors": [],
+ "detect_code": ["3105"]
+ },
"EV_COG_AD4050LZ": {
"inherits": ["Target"],
"core": "Cortex-M4F",
@@ -688,8 +703,33 @@
"device_name": "MK64FN1M0xxx12",
"bootloader_supported": true
},
+ "RAPIDIOT": {
+ "inherits": ["Target"],
+ "public": false,
+ "core": "null",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "macros": ["FSL_RTOS_MBED", "USE_EXTERNAL_RTC"],
+ "default_toolchain": "ARM",
+ "default_lib": "std",
+ "release_versions": ["2", "5"]
+ },
+ "RAPIDIOT_K64F": {
+ "inherits": ["RAPIDIOT"],
+ "core": "Cortex-M4F",
+ "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K64F"],
+ "macros_add": ["CPU_MK64FN1M0VMD12", "TARGET_K64F"],
+ "is_disk_virtual": true,
+ "mbed_rom_start": "0x00014000",
+ "mbed_rom_size": "0xEC000",
+ "detect_code": ["0228"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "forced_reset_timeout": 7,
+ "device_name": "MK64FN1M0xxx12",
+ "bootloader_supported": true
+ },
"K66F": {
"supported_form_factors": ["ARDUINO"],
+ "components": ["SD"],
"core": "Cortex-M4F",
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "Freescale_EMAC"],
@@ -698,7 +738,6 @@
"inherits": ["Target"],
"detect_code": ["0311"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
- "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "MK66FN2M0xxx18",
"bootloader_supported": true,
@@ -708,6 +747,7 @@
},
"K82F": {
"supported_form_factors": ["ARDUINO"],
+ "components": ["SPIF"],
"core": "Cortex-M4F",
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
@@ -715,13 +755,15 @@
"macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0217"],
- "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+ "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "MK82FN256xxx15"
},
"UBRIDGE": {
"inherits": ["K82F"],
"extra_labels_remove": ["FRDM"],
+ "components_remove": ["SPIF"],
+ "device_has_remove": ["QSPI"],
"supported_form_factors": []
},
"FAMILY_STM32": {
@@ -744,7 +786,12 @@
},
"stdio_uart_rx": {
"help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
- }
+ },
+ "lpticker_delay_ticks": {
+ "help": "https://os.mbed.com/docs/latest/porting/low-power-ticker.html",
+ "value": 1,
+ "macro_name": "LPTICKER_DELAY_TICKS"
+ }
},
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
},
@@ -757,7 +804,7 @@
"macros": ["CPU_MIMXRT1052DVL6B", "FSL_RTOS_MBED", "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", "XIP_BOOT_HEADER_DCD_ENABLE=1", "SKIP_SYSCLK_INIT"],
"inherits": ["Target"],
"detect_code": ["0227"],
- "device_has": ["SLEEP", "USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2CSLAVE", "ERROR_RED", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["RTC", "SLEEP", "USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2CSLAVE", "ERROR_RED", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "MIMXRT1052"
},
@@ -772,6 +819,7 @@
"detect_code": ["1054"],
"device_has": ["USTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
"release_versions": ["2", "5"],
+ "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
"device_name" : "LPC54114J256BD64"
},
"MCU_LPC546XX": {
@@ -782,8 +830,8 @@
"macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"device_has": ["USTICKER", "RTC", "ANALOGIN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH", "TRNG"],
- "features": ["LWIP"],
"device_name" : "LPC54628J512ET180",
+ "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
"overrides": {
"network-default-interface-type": "ETHERNET"
}
@@ -874,11 +922,6 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
- },
- "lpticker_delay_ticks": {
- "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
- "value": 1,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0755"],
@@ -897,11 +940,6 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
- },
- "lpticker_delay_ticks": {
- "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
- "value": 1,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0730"],
@@ -920,11 +958,6 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
- },
- "lpticker_delay_ticks": {
- "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
- "value": 1,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0750"],
@@ -977,9 +1010,9 @@
"macros_add": ["USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
"device_has_remove": ["LPTICKER"],
- "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F207ZG",
+ "bootloader_supported": true,
"overrides": {
"network-default-interface-type": "ETHERNET"
}
@@ -1123,11 +1156,6 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0744"],
@@ -1182,7 +1210,6 @@
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW43362"],
- "features": ["LWIP"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["5"],
@@ -1201,9 +1228,10 @@
},
"USI_WM_BN_BM_22": {
"inherits": ["FAMILY_STM32"],
+ "components": ["SPIF"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW4343X", "CORDIO"],
- "features": ["BLE", "LWIP"],
+ "features": ["BLE", "STORAGE"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["5"],
@@ -1253,16 +1281,12 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0743"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
+ "bootloader_supported": true,
"release_versions": ["2", "5"],
"device_name": "STM32F413ZH"
},
@@ -1280,16 +1304,12 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0743"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "bootloader_supported": true,
"release_versions": ["2", "5"],
"device_name": "STM32F413ZH"
},
@@ -1331,7 +1351,6 @@
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["0796"],
- "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "STM32F429ZI",
"bootloader_supported": true,
@@ -1364,7 +1383,6 @@
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["0797"],
- "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name" : "STM32F439ZI",
"bootloader_supported": true,
@@ -1437,17 +1455,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"macros_add": ["USBHOST_OTHER"],
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0816"],
- "features": ["LWIP"],
"device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F746ZG",
@@ -1474,17 +1486,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0819"],
- "features": ["LWIP"],
"device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F756ZG",
@@ -1514,17 +1520,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"supported_form_factors": ["ARDUINO"],
"macros_add": ["USBHOST_OTHER"],
"detect_code": ["0818"],
- "features": ["LWIP"],
"device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32F767ZI",
@@ -1549,13 +1549,9 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
+ "overrides": {"lpticker_delay_ticks": 4},
"detect_code": ["0780"],
"device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
"default_lib": "small",
@@ -1577,13 +1573,9 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
+ "overrides": {"lpticker_delay_ticks": 4},
"detect_code": ["0790"],
"device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
"default_lib": "small",
@@ -1604,13 +1596,9 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
+ "overrides": {"lpticker_delay_ticks": 4},
"detect_code": ["0715"],
"device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
"default_lib": "small",
@@ -1631,13 +1619,9 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
+ "overrides": {"lpticker_delay_ticks": 4},
"detect_code": ["0760"],
"device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
@@ -1653,11 +1637,6 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
- },
- "lpticker_delay_ticks": {
- "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
- "value": 1,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0710"],
@@ -1679,11 +1658,6 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0770"],
@@ -1706,11 +1680,6 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0779"],
@@ -1721,7 +1690,6 @@
},
"MTB_ADV_WISE_1510": {
"inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32L4", "STM32L443xC", "STM32L443RC"],
"config": {
@@ -1754,11 +1722,6 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0765"],
@@ -1800,11 +1763,6 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0827"],
@@ -1814,6 +1772,7 @@
"device_name": "STM32L486RG"
},
"MTB_ADV_WISE_1570": {
+ "components": ["FLASHIAP"],
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG", "WISE_1570"],
@@ -1841,7 +1800,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
"program_cycle_s": 2,
"extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
- "device_has_add": ["ANALOGOUT"],
+ "device_has_add": ["ANALOGOUT", "TRNG"],
"release_versions": ["2"],
"device_name": "STM32F407VG"
},
@@ -1874,7 +1833,6 @@
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["9014"],
- "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name" : "STM32F439VI",
"bootloader_supported": true
@@ -1954,7 +1912,7 @@
},
"macros_add": ["USB_STM_HAL"],
"overrides": {"lse_available": 0},
- "device_has_add": ["ANALOGOUT"],
+ "device_has_add": ["ANALOGOUT", "TRNG"],
"release_versions": ["2", "5"],
"device_name": "STM32F407VG"
},
@@ -1995,7 +1953,7 @@
},
"detect_code": ["0788"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "STM32F469NI"
},
@@ -2013,14 +1971,12 @@
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
- "overrides": {"lse_available": 0},
+ "overrides": {
+ "lse_available": 0,
+ "lpticker_delay_ticks": 4
+ },
"device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "FLASH"],
"default_lib": "small",
"release_versions": ["2"],
@@ -2040,13 +1996,9 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
+ "overrides": {"lpticker_delay_ticks": 4},
"detect_code": ["0833"],
"device_has_add": ["ANALOGOUT", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
@@ -2080,17 +2032,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0815"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "features": ["LWIP"],
- "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "STM32F746NG",
"overrides": {
@@ -2115,17 +2061,12 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0817"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "features": ["LWIP"],
"device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+ "bootloader_supported": true,
"release_versions": ["2", "5"],
"device_name": "STM32F769NI",
"overrides": {
@@ -2145,17 +2086,12 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0764"],
"macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
- "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "STM32L475VG",
"bootloader_supported": true
@@ -2173,16 +2109,11 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0820"],
"macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
- "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
"release_versions": ["2", "5"],
"device_name": "STM32L476VG",
"bootloader_supported": true
@@ -2236,6 +2167,35 @@
"release_versions": ["2", "5"],
"device_name": "STM32F411RE"
},
+ "MTS_DRAGONFLY_L471QG": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L471QG", "STM32L471xG", "STM32L471xx"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "modem_is_on_board": {
+ "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD"
+ },
+ "modem_data_connection_type": {
+ "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+ "value": 1,
+ "macro_name": "MODEM_ON_BOARD_UART"
+ }
+ },
+ "macros_add": ["TWO_RAM_REGIONS"],
+ "detect_code": ["0312"],
+ "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L471QG",
+ "bootloader_supported": true
+ },
"MTB_MTS_DRAGONFLY": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
@@ -2320,14 +2280,14 @@
},
"MOTE_L152RC": {
"inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO"],
"core": "Cortex-M3",
- "default_toolchain": "uARM",
+ "default_toolchain": "ARM",
+ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels_add": ["STM32L1", "STM32L152RC"],
- "overrides": {"lse_available": 0},
"detect_code": ["4100"],
- "device_has_add": ["ANALOGOUT"],
- "default_lib": "small",
- "release_versions": ["2"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "FLASH"],
+ "release_versions": ["2", "5"],
"device_name": "STM32L152RC"
},
"DISCO_F401VC": {
@@ -2342,14 +2302,21 @@
"MODULE_UBLOX_ODIN_W2": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI", "STM_EMAC"],
+ "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI", "STM_EMAC","CORDIO", "CORDIO_ODIN_W2"],
"macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","CB_FEATURE_802DOT11W","CB_FEATURE_802DOT11R","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
- "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH", "WIFI"],
+ "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH", "WIFI", "SERIAL_FC", "SERIAL"],
+ "features": ["BLE"],
"device_has_remove": [],
- "features": ["LWIP"],
"device_name": "STM32F439ZI",
"public": false,
"bootloader_supported": true,
+ "config": {
+ "BLE_STACK_UBX": {
+ "help": "It should be set to true to enable ublox ODIN own stack/driver rather than CORDIO",
+ "value": false,
+ "macro_name": "BLE_STACK_UBX"
+ }
+ },
"overrides": {
"network-default-interface-type": "WIFI"
}
@@ -2414,7 +2381,6 @@
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
"overrides": {"lse_available": 0},
"device_has_add": ["ANALOGOUT", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
- "features": ["LWIP"],
"public": false,
"device_name": "STM32F437VG",
"bootloader_supported": true,
@@ -2976,7 +2942,6 @@
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["RENESAS", "RZ_A1XX"],
"device_has": ["SLEEP", "USTICKER", "RTC", "ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
- "features": ["LWIP"],
"program_cycle_s": 2,
"overrides": {
"network-default-interface-type": "ETHERNET"
@@ -3003,7 +2968,6 @@
"extra_labels_add": ["RZA1UL", "MBRZA1LU"],
"device_has_add": ["TRNG", "FLASH", "LPTICKER"],
"device_has_remove": ["ETHERNET"],
- "features_remove": ["LWIP"],
"release_versions": ["2", "5"],
"device_name": "R7S72103",
"bootloader_supported": true,
@@ -3048,6 +3012,16 @@
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
"release_versions": ["2", "5"]
},
+ "SDT32620B": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"],
+ "detect_code": ["3101"],
+ "extra_labels": ["Maxim", "MAX32620C"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+ "release_versions": ["2", "5"]
+ },
"MAX32625_BASE": {
"inherits": ["Target"],
"core": "Cortex-M4F",
@@ -3055,33 +3029,26 @@
"extra_labels": ["Maxim", "MAX32625"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+ "device_name": "MAX32625",
"release_versions": ["2", "5"],
"public": false
},
- "MAX32625_BOOT": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625_BOOT"],
- "public": false
- },
- "MAX32625_NO_BOOT": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625_NO_BOOT"],
- "public": false
- },
"MAX32625MBED": {
- "inherits": ["MAX32625_NO_BOOT"]
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_NO_BOOT"]
+ },
+ "SDT32625B": {
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_NO_BOOT"],
+ "detect_code": ["3102"]
},
"MAX32625PICO": {
- "inherits": ["MAX32625_BOOT"],
- "extra_labels_add": ["MAX32625PICO_BASE"]
- },
- "MAX32625PICO_NO_BOOT": {
- "inherits": ["MAX32625_NO_BOOT"],
- "extra_labels_add": ["MAX32625PICO_BASE"]
+ "inherits": ["MAX32625_BASE"],
+ "extra_labels_add": ["MAX32625_BOOT"],
+ "bootloader_supported": true
},
"MAX32625NEXPAQ": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625NEXPAQ"]
+ "inherits": ["MAX32625_BASE"]
},
"MAX32630FTHR": {
"inherits": ["Target"],
@@ -3445,7 +3412,7 @@
},
"EFR32MG1_BRD4150": {
"inherits": ["EFR32MG1P132F256GM48"],
- "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "device_has": ["802_15_4_PHY", "ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
"forced_reset_timeout": 2,
"config": {
"hf_clock_src": {
@@ -3484,11 +3451,14 @@
"macro_name": "EFM_BC_EN"
}
},
+ "overrides": {
+ "network-default-interface-type": "MESH"
+ },
"public": false
},
"TB_SENSE_1": {
"inherits": ["EFR32MG1P233F256GM48"],
- "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
+ "device_has": ["802_15_4_PHY", "ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
"forced_reset_timeout": 5,
"config": {
"hf_clock_src": {
@@ -3521,6 +3491,9 @@
"value": "cmuHFRCOFreq_32M0Hz",
"macro_name": "HFRCO_FREQUENCY_ENUM"
}
+ },
+ "overrides": {
+ "network-default-interface-type": "MESH"
}
},
"EFM32PG12B500F1024GL125": {
@@ -3590,7 +3563,7 @@
"TB_SENSE_12": {
"inherits": ["EFR32MG12P332F1024GL125"],
"device_name": "EFR32MG12P332F1024GL125",
- "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
+ "device_has": ["802_15_4_PHY", "ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
"forced_reset_timeout": 5,
"config": {
"hf_clock_src": {
@@ -3623,6 +3596,9 @@
"value": "cmuHFRCOFreq_32M0Hz",
"macro_name": "HFRCO_FREQUENCY_ENUM"
}
+ },
+ "overrides": {
+ "network-default-interface-type": "MESH"
}
},
"EFM32GG11B820F2048GL192": {
@@ -3639,8 +3615,7 @@
"EFM32GG11_STK3701": {
"inherits": ["EFM32GG11B820F2048GL192"],
"device_name": "EFM32GG11B820F2048GL192",
- "device_has": ["ANALOGIN", "CRC", "EMAC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
- "features": ["LWIP"],
+ "device_has": ["ANALOGIN", "CRC", "EMAC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "QSPI", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
"forced_reset_timeout": 5,
"config": {
"hf_clock_src": {
@@ -3677,7 +3652,15 @@
"help": "Pin to pull high for enabling the USB serial port",
"value": "PE1",
"macro_name": "EFM_BC_EN"
+ },
+ "qspi_flash_enable": {
+ "help": "Pin to pull high for enabling the on-board QSPI flash",
+ "value": "PG13",
+ "macro_name": "QSPI_FLASH_EN"
}
+ },
+ "overrides": {
+ "network-default-interface-type": "ETHERNET"
}
},
"WIZWIKI_W7500": {
@@ -3835,6 +3818,13 @@
"release_versions": ["2", "5"],
"device_name": "nRF51822_xxAA"
},
+ "SDT51822B": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "detect_code": ["3103"],
+ "release_versions": ["2", "5"],
+ "device_name": "nRF51822_xxAA"
+ },
"NRF51_DONGLE": {
"inherits": ["MCU_NRF51_32K_UNIFIED"],
"progen": {"target": "nrf51-dongle"},
@@ -3876,7 +3866,7 @@
"SLEEP",
"SPI",
"SPI_ASYNCH",
- "STCLK_OFF_DURING_SLEEP",
+ "SYSTICK_CLK_OFF_DURING_SLEEP",
"TRNG",
"USTICKER"
],
@@ -3917,6 +3907,12 @@
"release_versions": ["5"],
"device_name": "nRF52832_xxAA"
},
+ "SDT52832B": {
+ "inherits": ["MCU_NRF52832"],
+ "release_versions": ["5"],
+ "detect_code": ["3104"],
+ "device_name": "nRF52832_xxAA"
+ },
"UBLOX_EVA_NINA": {
"inherits": ["MCU_NRF52832"],
"release_versions": ["5"],
@@ -3975,9 +3971,10 @@
"SLEEP",
"SPI",
"SPI_ASYNCH",
- "STCLK_OFF_DURING_SLEEP",
+ "SYSTICK_CLK_OFF_DURING_SLEEP",
"TRNG",
- "USTICKER"
+ "USTICKER",
+ "QSPI"
],
"extra_labels": [
"NORDIC",
@@ -4016,13 +4013,24 @@
"release_versions": ["5"],
"device_name": "nRF52840_xxAA"
},
+ "MTB_LAIRD_BL654": {
+ "inherits": ["MCU_NRF52840"],
+ "release_versions": ["5"],
+ "device_name": "nRF52840_xxAA",
+ "detect_code": ["0465"],
+ "features_remove": ["CRYPTOCELL310"],
+ "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+ "overrides": {
+ "lf_clock_src": "NRF_LF_SRC_RC"
+ }
+ },
"BLUEPILL_F103C8": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M3",
"default_toolchain": "GCC_ARM",
"extra_labels_add": ["STM32F1", "STM32F103C8"],
"supported_toolchains": ["GCC_ARM"],
- "device_has_add": [],
+ "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
"device_has_remove": ["STDIO_MESSAGES", "LPTICKER"]
},
"NUMAKER_PFM_NUC472": {
@@ -4050,7 +4058,6 @@
}
},
"inherits": ["Target"],
- "features": ["LWIP"],
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH", "EMAC"],
"release_versions": ["5"],
@@ -4094,7 +4101,7 @@
"post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
"macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "TRNG", "SPISLAVE"],
+ "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "TRNG", "SPISLAVE", "802_15_4_PHY"],
"release_versions": ["2", "5"]
},
"NUMAKER_PFM_M453": {
@@ -4199,7 +4206,6 @@
"extra_labels": ["Realtek", "AMEBA", "RTL8195A", "RTW_EMAC"],
"macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS","MBED_FAULT_HANDLER_DISABLED"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "features": ["LWIP"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "TRNG", "FLASH"],
"post_binary_hook": {
"function": "RTL8195ACode.binary_hook",
@@ -4256,17 +4262,13 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0822"],
"device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "STM32L496AG"
+ "device_name": "STM32L496AG",
+ "bootloader_supported": true
},
"NUCLEO_L496ZG": {
"inherits": ["FAMILY_STM32"],
@@ -4282,31 +4284,50 @@
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
- },
- "lpticker_delay_ticks": {
- "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
- "value": 3,
- "macro_name": "LPTICKER_DELAY_TICKS"
}
},
"detect_code": ["0823"],
"device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "STM32L496ZG"
+ "device_name": "STM32L496ZG",
+ "bootloader_supported": true
},
"NUCLEO_L496ZG_P": {
"inherits": ["NUCLEO_L496ZG"],
"detect_code": ["0828"]
+ },
+ "NUCLEO_L4R5ZI": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": ["ARDUINO", "MORPHO"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32L4", "STM32L4R5ZI", "STM32L4R5xI"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+ "value": "USE_PLL_MSI",
+ "macro_name": "CLOCK_SOURCE"
+ },
+ "lpticker_lptim": {
+ "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+ "value": 1
+ }
},
+ "detect_code": ["0776"],
+ "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+ "release_versions": ["2", "5"],
+ "device_name": "STM32L4R5ZI",
+ "bootloader_supported": true
+ },
"VBLUNO52": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52832"],
"release_versions": ["5"],
"device_name": "nRF52832_xxAA"
},
- "NUMAKER_PFM_M487": {
+ "MCU_M480": {
"core": "Cortex-M4F",
"default_toolchain": "ARM",
+ "public": false,
"extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO","NUVOTON_EMAC"],
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
@@ -4337,16 +4358,22 @@
}
},
"inherits": ["Target"],
- "features": ["LWIP"],
"macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN", "EMAC"],
"release_versions": ["5"],
- "device_name": "M487JIDAE",
"bootloader_supported": true,
"overrides": {
"network-default-interface-type": "ETHERNET"
}
},
+ "NUMAKER_PFM_M487": {
+ "inherits": ["MCU_M480"],
+ "device_name": "M487JIDAE"
+ },
+ "NUMAKER_IOT_M487": {
+ "inherits": ["MCU_M480"],
+ "device_name": "M487JIDAE"
+ },
"TMPM066": {
"inherits": ["Target"],
"core": "Cortex-M0",
@@ -4354,7 +4381,7 @@
"extra_labels": ["TOSHIBA"],
"macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"],
+ "device_has": ["USTICKER", "ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"],
"device_name": "TMPM066FWUG",
"detect_code": ["7011"],
"release_versions": ["5"]
@@ -4383,7 +4410,7 @@
"extra_labels": ["TOSHIBA"],
"macros": ["__TMPM46B__"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
+ "device_has": ["USTICKER", "ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
"device_name": "TMPM46BF10FG",
"detect_code": ["7013"],
"release_versions": ["5"],
@@ -4392,6 +4419,7 @@
"ARM_FM": {
"inherits": ["Target"],
"public": false,
+ "macros": ["__ARM_FM"],
"extra_labels": ["ARM_FM"]
},
"FVP_MPS2": {
@@ -4405,27 +4433,27 @@
"FVP_MPS2_M0": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M0",
- "macros": ["CMSDK_CM0"]
+ "macros_add": ["CMSDK_CM0"]
},
"FVP_MPS2_M0P": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M0+",
- "macros": ["CMSDK_CM0plus"]
+ "macros_add": ["CMSDK_CM0plus"]
},
"FVP_MPS2_M3": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M3",
- "macros": ["CMSDK_CM3"]
+ "macros_add": ["CMSDK_CM3"]
},
"FVP_MPS2_M4": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M4",
- "macros": ["CMSDK_CM4"]
+ "macros_add": ["CMSDK_CM4"]
},
"FVP_MPS2_M7": {
"inherits": ["FVP_MPS2"],
"core": "Cortex-M7",
- "macros": ["CMSDK_CM7"]
+ "macros_add": ["CMSDK_CM7"]
},
"NUMAKER_PFM_M2351": {
"core": "Cortex-M23-NS",
@@ -4456,7 +4484,7 @@
"mbed_rom_start": "0x10040000",
"mbed_rom_size": "0x40000",
"mbed_ram_start": "0x30008000",
- "mbed_ram_size": "0x10000",
+ "mbed_ram_size": "0x10000",
"inherits": ["Target"],
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"],
"detect_code": ["1305"],
@@ -4475,5 +4503,96 @@
"device_name": "TMPM3H6FWFG",
"detect_code": ["7012"],
"release_versions": ["5"]
+ },
+ "TMPM4G9": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4",
+ "is_disk_virtual": true,
+ "extra_labels": ["TOSHIBA"],
+ "macros": ["__TMPM4G9__"],
+ "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "FLASH", "SLEEP", "USTICKER"],
+ "device_name": "TMPM4G9F15FG",
+ "detect_code": ["7016"],
+ "release_versions": ["5"],
+ "bootloader_supported": true
+ },
+ "MCU_PSOC6": {
+ "inherits": ["Target"],
+ "default_toolchain": "GCC_ARM",
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "core": "Cortex-M4F",
+ "OUTPUT_EXT": "hex",
+ "device_has": ["USTICKER", "INTERRUPTIN", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "PORTIN", "PORTOUT", "PORTINOUT", "RTC", "PWMOUT", "ANALOGIN", "ANALOGOUT", "I2C", "I2C_ASYNCH", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES", "LPTICKER", "SLEEP", "FLASH" ],
+ "release_versions": ["5"],
+ "extra_labels": ["Cypress", "PSOC6"],
+ "public": false
+ },
+ "MCU_PSOC6_M0": {
+ "inherits": ["MCU_PSOC6"],
+ "core": "Cortex-M0+",
+ "macros": ["MCU_PSOC6_M0"],
+ "public": false
+ },
+ "MCU_PSOC6_M4": {
+ "inherits": ["MCU_PSOC6"],
+ "macros": ["MCU_PSOC6_M4"],
+ "public": false
+ },
+ "FUTURE_SEQUANA_M0": {
+ "inherits": ["MCU_PSOC6_M0"],
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["CY8C63XX", "FUTURE_SEQUANA"],
+ "macros_add": ["CY8C6347BZI_BLD53"],
+ "detect_code": ["6000"],
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "config": {
+ "system-clock": {
+ "help": "Desired frequency of main clock (Hz)",
+ "value": "100000000UL",
+ "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
+ },
+ "peri-clock": {
+ "help": "Desired frequency of peripheral clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
+ },
+ "m0-clock": {
+ "help": "Desired frequency of M0+ core clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
+ }
+ }
+ },
+ "FUTURE_SEQUANA": {
+ "inherits": ["MCU_PSOC6_M4"],
+ "sub_target": "FUTURE_SEQUANA_M0",
+ "supported_form_factors": ["ARDUINO"],
+ "extra_labels_add": ["CY8C63XX", "CORDIO"],
+ "macros_add": ["CY8C6347BZI_BLD53"],
+ "detect_code": ["6000"],
+ "m0_core_img": "psoc63_m0_default_1.01.hex",
+ "post_binary_hook": {
+ "function": "PSOC6Code.complete"
+ },
+ "config": {
+ "system-clock": {
+ "help": "Desired frequency of main clock (Hz)",
+ "value": "100000000UL",
+ "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
+ },
+ "peri-clock": {
+ "help": "Desired frequency of peripheral clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
+ },
+ "m0-clock": {
+ "help": "Desired frequency of M0+ core clock (Hz)",
+ "value": "50000000UL",
+ "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
+ }
+ }
}
}
